drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  *  and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #ifndef __DC_LINK_ENCODER__DCN10_H__
  27 #define __DC_LINK_ENCODER__DCN10_H__
  28
  29 #include "link_encoder.h"
  30
  31 #define TO_DCN10_LINK_ENC(link_encoder)\
  32         container_of(link_encoder, struct dcn10_link_encoder, base)
  33
  34 #define AUX_REG_LIST(id)\
  35         SRI(AUX_CONTROL, DP_AUX, id), \
  36         SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id), \
  37         SRI(AUX_DPHY_RX_CONTROL1, DP_AUX, id)
  38
  39 #define HPD_REG_LIST(id)\
  40         SRI(DC_HPD_CONTROL, HPD, id)
  41
  42 #define LE_DCN_COMMON_REG_LIST(id) \
  43         SRI(DIG_BE_CNTL, DIG, id), \
  44         SRI(DIG_BE_EN_CNTL, DIG, id), \
  45         SRI(DIG_CLOCK_PATTERN, DIG, id), \
  46         SRI(TMDS_CTL_BITS, DIG, id), \
  47         SRI(DP_CONFIG, DP, id), \
  48         SRI(DP_DPHY_CNTL, DP, id), \
  49         SRI(DP_DPHY_PRBS_CNTL, DP, id), \
  50         SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
  51         SRI(DP_DPHY_SYM0, DP, id), \
  52         SRI(DP_DPHY_SYM1, DP, id), \
  53         SRI(DP_DPHY_SYM2, DP, id), \
  54         SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
  55         SRI(DP_LINK_CNTL, DP, id), \
  56         SRI(DP_LINK_FRAMING_CNTL, DP, id), \
  57         SRI(DP_MSE_SAT0, DP, id), \
  58         SRI(DP_MSE_SAT1, DP, id), \
  59         SRI(DP_MSE_SAT2, DP, id), \
  60         SRI(DP_MSE_SAT_UPDATE, DP, id), \
  61         SRI(DP_SEC_CNTL, DP, id), \
  62         SRI(DP_VID_STREAM_CNTL, DP, id), \
  63         SRI(DP_DPHY_FAST_TRAINING, DP, id), \
  64         SRI(DP_SEC_CNTL1, DP, id), \
  65         SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
  66         SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id)
  67
  68
  69 #define LE_DCN10_REG_LIST(id)\
  70         SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
  71         LE_DCN_COMMON_REG_LIST(id)
  72
  73 struct dcn10_link_enc_aux_registers {
  74         uint32_t AUX_CONTROL;
  75         uint32_t AUX_DPHY_RX_CONTROL0;
  76         uint32_t AUX_DPHY_TX_CONTROL;
  77         uint32_t AUX_DPHY_RX_CONTROL1;
  78 };
  79
  80 struct dcn10_link_enc_hpd_registers {
  81         uint32_t DC_HPD_CONTROL;
  82 };
  83
  84 struct dcn10_link_enc_registers {
  85         uint32_t DIG_BE_CNTL;
  86         uint32_t DIG_BE_EN_CNTL;
  87         uint32_t DIG_CLOCK_PATTERN;
  88         uint32_t DP_CONFIG;
  89         uint32_t DP_DPHY_CNTL;
  90         uint32_t DP_DPHY_INTERNAL_CTRL;
  91         uint32_t DP_DPHY_PRBS_CNTL;
  92         uint32_t DP_DPHY_SCRAM_CNTL;
  93         uint32_t DP_DPHY_SYM0;
  94         uint32_t DP_DPHY_SYM1;
  95         uint32_t DP_DPHY_SYM2;
  96         uint32_t DP_DPHY_TRAINING_PATTERN_SEL;
  97         uint32_t DP_LINK_CNTL;
  98         uint32_t DP_LINK_FRAMING_CNTL;
  99         uint32_t DP_MSE_SAT0;
 100         uint32_t DP_MSE_SAT1;
 101         uint32_t DP_MSE_SAT2;
 102         uint32_t DP_MSE_SAT_UPDATE;
 103         uint32_t DP_SEC_CNTL;
 104         uint32_t DP_VID_STREAM_CNTL;
 105         uint32_t DP_DPHY_FAST_TRAINING;
 106         uint32_t DP_DPHY_BS_SR_SWAP_CNTL;
 107         uint32_t DP_DPHY_HBR2_PATTERN_CONTROL;
 108         uint32_t DP_SEC_CNTL1;
 109         uint32_t TMDS_CTL_BITS;
 110         /* DCCG  */
 111         uint32_t CLOCK_ENABLE;
 112         /* DIG */
 113         uint32_t DIG_LANE_ENABLE;
 114         /* UNIPHY */
 115         uint32_t CHANNEL_XBAR_CNTL;
 116         /* DPCS */
 117         uint32_t RDPCSTX_PHY_CNTL3;
 118         uint32_t RDPCSTX_PHY_CNTL4;
 119         uint32_t RDPCSTX_PHY_CNTL5;
 120         uint32_t RDPCSTX_PHY_CNTL6;
 121         uint32_t RDPCSTX_PHY_CNTL7;
 122         uint32_t RDPCSTX_PHY_CNTL8;
 123         uint32_t RDPCSTX_PHY_CNTL9;
 124         uint32_t RDPCSTX_PHY_CNTL10;
 125         uint32_t RDPCSTX_PHY_CNTL11;
 126         uint32_t RDPCSTX_PHY_CNTL12;
 127         uint32_t RDPCSTX_PHY_CNTL13;
 128         uint32_t RDPCSTX_PHY_CNTL14;
 129         uint32_t RDPCSTX_PHY_CNTL15;
 130         uint32_t RDPCSTX_CNTL;
 131         uint32_t RDPCSTX_CLOCK_CNTL;
 132         uint32_t RDPCSTX_PHY_CNTL0;
 133         uint32_t RDPCSTX_PHY_CNTL2;
 134         uint32_t RDPCSTX_PLL_UPDATE_DATA;
 135         uint32_t RDPCS_TX_CR_ADDR;
 136         uint32_t RDPCS_TX_CR_DATA;
 137         uint32_t DPCSTX_TX_CLOCK_CNTL;
 138         uint32_t DPCSTX_TX_CNTL;
 139         uint32_t RDPCSTX_INTERRUPT_CONTROL;
 140         uint32_t RDPCSTX_PHY_FUSE0;
 141         uint32_t RDPCSTX_PHY_FUSE1;
 142         uint32_t RDPCSTX_PHY_FUSE2;
 143         uint32_t RDPCSTX_PHY_FUSE3;
 144         uint32_t RDPCSTX_PHY_RX_LD_VAL;
 145         uint32_t DPCSTX_DEBUG_CONFIG;
 146         uint32_t RDPCSTX_DEBUG_CONFIG;
 147         uint32_t RDPCSTX0_RDPCSTX_SCRATCH;
 148         uint32_t RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG;
 149         uint32_t DCIO_SOFT_RESET;
 150         /* indirect registers */
 151         uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2;
 152         uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3;
 153         uint32_t RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2;
 154         uint32_t RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3;
 155         uint32_t RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2;
 156         uint32_t RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3;
 157         uint32_t RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2;
 158         uint32_t RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3;
 159         uint32_t TMDS_DCBALANCER_CONTROL;
 160         uint32_t PHYA_LINK_CNTL2;
 161         uint32_t PHYB_LINK_CNTL2;
 162         uint32_t PHYC_LINK_CNTL2;
 163         uint32_t DIO_LINKA_CNTL;
 164         uint32_t DIO_LINKB_CNTL;
 165         uint32_t DIO_LINKC_CNTL;
 166         uint32_t DIO_LINKD_CNTL;
 167         uint32_t DIO_LINKE_CNTL;
 168         uint32_t DIO_LINKF_CNTL;
 169 };
 170
 171 #define LE_SF(reg_name, field_name, post_fix)\
 172         .field_name = reg_name ## __ ## field_name ## post_fix
 173
 174 #define LINK_ENCODER_MASK_SH_LIST_DCN10(mask_sh)\
 175         LE_SF(DIG0_DIG_BE_EN_CNTL, DIG_ENABLE, mask_sh),\
 176         LE_SF(DIG0_DIG_BE_CNTL, DIG_HPD_SELECT, mask_sh),\
 177         LE_SF(DIG0_DIG_BE_CNTL, DIG_MODE, mask_sh),\
 178         LE_SF(DIG0_DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, mask_sh),\
 179         LE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh),\
 180         LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \
 181         LE_SF(DP0_DP_DPHY_CNTL, DPHY_BYPASS, mask_sh),\
 182         LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE0, mask_sh),\
 183         LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE1, mask_sh),\
 184         LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE2, mask_sh),\
 185         LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE3, mask_sh),\
 186         LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, mask_sh),\
 187         LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_SEL, mask_sh),\
 188         LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM1, mask_sh),\
 189         LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM2, mask_sh),\
 190         LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM3, mask_sh),\
 191         LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM4, mask_sh),\
 192         LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM5, mask_sh),\
 193         LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM6, mask_sh),\
 194         LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM7, mask_sh),\
 195         LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM8, mask_sh),\
 196         LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, mask_sh),\
 197         LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, mask_sh),\
 198         LE_SF(DP0_DP_DPHY_FAST_TRAINING, DPHY_RX_FAST_TRAINING_CAPABLE, mask_sh),\
 199         LE_SF(DP0_DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, mask_sh),\
 200         LE_SF(DP0_DP_DPHY_TRAINING_PATTERN_SEL, DPHY_TRAINING_PATTERN_SEL, mask_sh),\
 201         LE_SF(DP0_DP_DPHY_HBR2_PATTERN_CONTROL, DP_DPHY_HBR2_PATTERN_CONTROL, mask_sh),\
 202         LE_SF(DP0_DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, mask_sh),\
 203         LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_IDLE_BS_INTERVAL, mask_sh),\
 204         LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VBID_DISABLE, mask_sh),\
 205         LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VID_ENHANCED_FRAME_MODE, mask_sh),\
 206         LE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
 207         LE_SF(DP0_DP_CONFIG, DP_UDI_LANES, mask_sh),\
 208         LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_LINE_NUM, mask_sh),\
 209         LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_PRIORITY, mask_sh),\
 210         LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC0, mask_sh),\
 211         LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC1, mask_sh),\
 212         LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT0, mask_sh),\
 213         LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT1, mask_sh),\
 214         LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC2, mask_sh),\
 215         LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC3, mask_sh),\
 216         LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT2, mask_sh),\
 217         LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT3, mask_sh),\
 218         LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_SAT_UPDATE, mask_sh),\
 219         LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_16_MTP_KEEPOUT, mask_sh),\
 220         LE_SF(DP_AUX0_AUX_CONTROL, AUX_HPD_SEL, mask_sh),\
 221         LE_SF(DP_AUX0_AUX_CONTROL, AUX_LS_READ_EN, mask_sh),\
 222         LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_RECEIVE_WINDOW, mask_sh),\
 223         LE_SF(HPD0_DC_HPD_CONTROL, DC_HPD_EN, mask_sh)
 224
 225 #define DCN_LINK_ENCODER_REG_FIELD_LIST(type) \
 226         type DIG_ENABLE;\
 227         type DIG_HPD_SELECT;\
 228         type DIG_MODE;\
 229         type DIG_FE_SOURCE_SELECT;\
 230         type DIG_CLOCK_PATTERN;\
 231         type DPHY_BYPASS;\
 232         type DPHY_ATEST_SEL_LANE0;\
 233         type DPHY_ATEST_SEL_LANE1;\
 234         type DPHY_ATEST_SEL_LANE2;\
 235         type DPHY_ATEST_SEL_LANE3;\
 236         type DPHY_PRBS_EN;\
 237         type DPHY_PRBS_SEL;\
 238         type DPHY_SYM1;\
 239         type DPHY_SYM2;\
 240         type DPHY_SYM3;\
 241         type DPHY_SYM4;\
 242         type DPHY_SYM5;\
 243         type DPHY_SYM6;\
 244         type DPHY_SYM7;\
 245         type DPHY_SYM8;\
 246         type DPHY_SCRAMBLER_BS_COUNT;\
 247         type DPHY_SCRAMBLER_ADVANCE;\
 248         type DPHY_RX_FAST_TRAINING_CAPABLE;\
 249         type DPHY_LOAD_BS_COUNT;\
 250         type DPHY_TRAINING_PATTERN_SEL;\
 251         type DP_DPHY_HBR2_PATTERN_CONTROL;\
 252         type DP_LINK_TRAINING_COMPLETE;\
 253         type DP_IDLE_BS_INTERVAL;\
 254         type DP_VBID_DISABLE;\
 255         type DP_VID_ENHANCED_FRAME_MODE;\
 256         type DP_VID_STREAM_ENABLE;\
 257         type DP_UDI_LANES;\
 258         type DP_SEC_GSP0_LINE_NUM;\
 259         type DP_SEC_GSP0_PRIORITY;\
 260         type DP_MSE_SAT_SRC0;\
 261         type DP_MSE_SAT_SRC1;\
 262         type DP_MSE_SAT_SRC2;\
 263         type DP_MSE_SAT_SRC3;\
 264         type DP_MSE_SAT_SLOT_COUNT0;\
 265         type DP_MSE_SAT_SLOT_COUNT1;\
 266         type DP_MSE_SAT_SLOT_COUNT2;\
 267         type DP_MSE_SAT_SLOT_COUNT3;\
 268         type DP_MSE_SAT_UPDATE;\
 269         type DP_MSE_16_MTP_KEEPOUT;\
 270         type DC_HPD_EN;\
 271         type TMDS_CTL0;\
 272         type AUX_HPD_SEL;\
 273         type AUX_LS_READ_EN;\
 274         type AUX_RX_RECEIVE_WINDOW
 275
 276
 277 #define DCN20_LINK_ENCODER_DPCS_REG_FIELD_LIST(type) \
 278                 type RDPCS_PHY_DP_TX0_DATA_EN;\
 279                 type RDPCS_PHY_DP_TX1_DATA_EN;\
 280                 type RDPCS_PHY_DP_TX2_DATA_EN;\
 281                 type RDPCS_PHY_DP_TX3_DATA_EN;\
 282                 type RDPCS_PHY_DP_TX0_PSTATE;\
 283                 type RDPCS_PHY_DP_TX1_PSTATE;\
 284                 type RDPCS_PHY_DP_TX2_PSTATE;\
 285                 type RDPCS_PHY_DP_TX3_PSTATE;\
 286                 type RDPCS_PHY_DP_TX0_MPLL_EN;\
 287                 type RDPCS_PHY_DP_TX1_MPLL_EN;\
 288                 type RDPCS_PHY_DP_TX2_MPLL_EN;\
 289                 type RDPCS_PHY_DP_TX3_MPLL_EN;\
 290                 type RDPCS_TX_FIFO_LANE0_EN;\
 291                 type RDPCS_TX_FIFO_LANE1_EN;\
 292                 type RDPCS_TX_FIFO_LANE2_EN;\
 293                 type RDPCS_TX_FIFO_LANE3_EN;\
 294                 type RDPCS_EXT_REFCLK_EN;\
 295                 type RDPCS_TX_FIFO_EN;\
 296                 type UNIPHY_LINK_ENABLE;\
 297                 type UNIPHY_CHANNEL0_XBAR_SOURCE;\
 298                 type UNIPHY_CHANNEL1_XBAR_SOURCE;\
 299                 type UNIPHY_CHANNEL2_XBAR_SOURCE;\
 300                 type UNIPHY_CHANNEL3_XBAR_SOURCE;\
 301                 type UNIPHY_CHANNEL0_INVERT;\
 302                 type UNIPHY_CHANNEL1_INVERT;\
 303                 type UNIPHY_CHANNEL2_INVERT;\
 304                 type UNIPHY_CHANNEL3_INVERT;\
 305                 type UNIPHY_LINK_ENABLE_HPD_MASK;\
 306                 type UNIPHY_LANE_STAGGER_DELAY;\
 307                 type RDPCS_SRAMCLK_BYPASS;\
 308                 type RDPCS_SRAMCLK_EN;\
 309                 type RDPCS_SRAMCLK_CLOCK_ON;\
 310                 type DPCS_TX_FIFO_EN;\
 311                 type RDPCS_PHY_DP_TX0_DISABLE;\
 312                 type RDPCS_PHY_DP_TX1_DISABLE;\
 313                 type RDPCS_PHY_DP_TX2_DISABLE;\
 314                 type RDPCS_PHY_DP_TX3_DISABLE;\
 315                 type RDPCS_PHY_DP_TX0_CLK_RDY;\
 316                 type RDPCS_PHY_DP_TX1_CLK_RDY;\
 317                 type RDPCS_PHY_DP_TX2_CLK_RDY;\
 318                 type RDPCS_PHY_DP_TX3_CLK_RDY;\
 319                 type RDPCS_PHY_DP_TX0_REQ;\
 320                 type RDPCS_PHY_DP_TX1_REQ;\
 321                 type RDPCS_PHY_DP_TX2_REQ;\
 322                 type RDPCS_PHY_DP_TX3_REQ;\
 323                 type RDPCS_PHY_DP_TX0_ACK;\
 324                 type RDPCS_PHY_DP_TX1_ACK;\
 325                 type RDPCS_PHY_DP_TX2_ACK;\
 326                 type RDPCS_PHY_DP_TX3_ACK;\
 327                 type RDPCS_PHY_DP_TX0_RESET;\
 328                 type RDPCS_PHY_DP_TX1_RESET;\
 329                 type RDPCS_PHY_DP_TX2_RESET;\
 330                 type RDPCS_PHY_DP_TX3_RESET;\
 331                 type RDPCS_PHY_RESET;\
 332                 type RDPCS_PHY_CR_MUX_SEL;\
 333                 type RDPCS_PHY_REF_RANGE;\
 334                 type RDPCS_PHY_DP4_POR;\
 335                 type RDPCS_SRAM_BYPASS;\
 336                 type RDPCS_SRAM_EXT_LD_DONE;\
 337                 type RDPCS_PHY_DP_TX0_TERM_CTRL;\
 338                 type RDPCS_PHY_DP_TX1_TERM_CTRL;\
 339                 type RDPCS_PHY_DP_TX2_TERM_CTRL;\
 340                 type RDPCS_PHY_DP_TX3_TERM_CTRL;\
 341                 type RDPCS_PHY_DP_REF_CLK_MPLLB_DIV;\
 342                 type RDPCS_PHY_DP_MPLLB_MULTIPLIER;\
 343                 type RDPCS_PHY_DP_MPLLB_SSC_EN;\
 344                 type RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN;\
 345                 type RDPCS_PHY_DP_MPLLB_TX_CLK_DIV;\
 346                 type RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN;\
 347                 type RDPCS_PHY_DP_MPLLB_FRACN_EN;\
 348                 type RDPCS_PHY_DP_MPLLB_PMIX_EN;\
 349                 type RDPCS_PHY_DP_MPLLB_FRACN_QUOT;\
 350                 type RDPCS_PHY_DP_MPLLB_FRACN_DEN;\
 351                 type RDPCS_PHY_DP_MPLLB_FRACN_REM;\
 352                 type RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD;\
 353                 type RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE;\
 354                 type RDPCS_PHY_DP_MPLLB_SSC_PEAK;\
 355                 type RDPCS_PHY_DP_MPLLB_DIV_CLK_EN;\
 356                 type RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER;\
 357                 type RDPCS_PHY_TX_VBOOST_LVL;\
 358                 type RDPCS_PHY_HDMIMODE_ENABLE;\
 359                 type RDPCS_PHY_DP_REF_CLK_EN;\
 360                 type RDPCS_PLL_UPDATE_DATA;\
 361                 type RDPCS_SRAM_INIT_DONE;\
 362                 type RDPCS_TX_CR_ADDR;\
 363                 type RDPCS_TX_CR_DATA;\
 364                 type RDPCS_PHY_HDMI_MPLLB_HDMI_DIV;\
 365                 type RDPCS_PHY_DP_MPLLB_STATE;\
 366                 type RDPCS_PHY_DP_TX0_WIDTH;\
 367                 type RDPCS_PHY_DP_TX0_RATE;\
 368                 type RDPCS_PHY_DP_TX1_WIDTH;\
 369                 type RDPCS_PHY_DP_TX1_RATE;\
 370                 type RDPCS_PHY_DP_TX2_WIDTH;\
 371                 type RDPCS_PHY_DP_TX2_RATE;\
 372                 type RDPCS_PHY_DP_TX3_WIDTH;\
 373                 type RDPCS_PHY_DP_TX3_RATE;\
 374                 type DPCS_SYMCLK_CLOCK_ON;\
 375                 type DPCS_SYMCLK_GATE_DIS;\
 376                 type DPCS_SYMCLK_EN;\
 377                 type RDPCS_SYMCLK_DIV2_CLOCK_ON;\
 378                 type RDPCS_SYMCLK_DIV2_GATE_DIS;\
 379                 type RDPCS_SYMCLK_DIV2_EN;\
 380                 type DPCS_TX_DATA_SWAP;\
 381                 type DPCS_TX_DATA_ORDER_INVERT;\
 382                 type DPCS_TX_FIFO_RD_START_DELAY;\
 383                 type RDPCS_TX_FIFO_RD_START_DELAY;\
 384                 type RDPCS_REG_FIFO_ERROR_MASK;\
 385                 type RDPCS_TX_FIFO_ERROR_MASK;\
 386                 type RDPCS_DPALT_DISABLE_TOGGLE_MASK;\
 387                 type RDPCS_DPALT_4LANE_TOGGLE_MASK;\
 388                 type RDPCS_PHY_DPALT_DP4;\
 389                 type RDPCS_PHY_DPALT_DISABLE;\
 390                 type RDPCS_PHY_DPALT_DISABLE_ACK;\
 391                 type RDPCS_PHY_DP_MPLLB_V2I;\
 392                 type RDPCS_PHY_DP_MPLLB_FREQ_VCO;\
 393                 type RDPCS_PHY_DP_MPLLB_CP_INT_GS;\
 394                 type RDPCS_PHY_RX_VREF_CTRL;\
 395                 type RDPCS_PHY_DP_MPLLB_CP_INT;\
 396                 type RDPCS_PHY_DP_MPLLB_CP_PROP;\
 397                 type RDPCS_PHY_RX_REF_LD_VAL;\
 398                 type RDPCS_PHY_RX_VCO_LD_VAL;\
 399                 type DPCSTX_DEBUG_CONFIG; \
 400                 type RDPCSTX_DEBUG_CONFIG; \
 401                 type RDPCS_PHY_DP_TX0_EQ_MAIN;\
 402                 type RDPCS_PHY_DP_TX0_EQ_PRE;\
 403                 type RDPCS_PHY_DP_TX0_EQ_POST;\
 404                 type RDPCS_PHY_DP_TX1_EQ_MAIN;\
 405                 type RDPCS_PHY_DP_TX1_EQ_PRE;\
 406                 type RDPCS_PHY_DP_TX1_EQ_POST;\
 407                 type RDPCS_PHY_DP_TX2_EQ_MAIN;\
 408                 type RDPCS_PHY_DP_MPLLB_CP_PROP_GS;\
 409                 type RDPCS_PHY_DP_TX2_EQ_PRE;\
 410                 type RDPCS_PHY_DP_TX2_EQ_POST;\
 411                 type RDPCS_PHY_DP_TX3_EQ_MAIN;\
 412                 type RDPCS_PHY_DCO_RANGE;\
 413                 type RDPCS_PHY_DCO_FINETUNE;\
 414                 type RDPCS_PHY_DP_TX3_EQ_PRE;\
 415                 type RDPCS_PHY_DP_TX3_EQ_POST;\
 416                 type RDPCS_PHY_SUP_PRE_HP;\
 417                 type RDPCS_PHY_DP_TX0_VREGDRV_BYP;\
 418                 type RDPCS_PHY_DP_TX1_VREGDRV_BYP;\
 419                 type RDPCS_PHY_DP_TX2_VREGDRV_BYP;\
 420                 type RDPCS_PHY_DP_TX3_VREGDRV_BYP;\
 421                 type RDPCS_DMCU_DPALT_DIS_BLOCK_REG;\
 422                 type UNIPHYA_SOFT_RESET;\
 423                 type UNIPHYB_SOFT_RESET;\
 424                 type UNIPHYC_SOFT_RESET;\
 425                 type UNIPHYD_SOFT_RESET;\
 426                 type UNIPHYE_SOFT_RESET;\
 427                 type UNIPHYF_SOFT_RESET
 428
 429 #define DCN20_LINK_ENCODER_REG_FIELD_LIST(type) \
 430         type DIG_LANE0EN;\
 431         type DIG_LANE1EN;\
 432         type DIG_LANE2EN;\
 433         type DIG_LANE3EN;\
 434         type DIG_CLK_EN;\
 435         type SYMCLKA_CLOCK_ENABLE;\
 436         type DPHY_FEC_EN;\
 437         type DPHY_FEC_READY_SHADOW;\
 438         type DPHY_FEC_ACTIVE_STATUS;\
 439         DCN20_LINK_ENCODER_DPCS_REG_FIELD_LIST(type);\
 440         type VCO_LD_VAL_OVRD;\
 441         type VCO_LD_VAL_OVRD_EN;\
 442         type REF_LD_VAL_OVRD;\
 443         type REF_LD_VAL_OVRD_EN;\
 444         type AUX_RX_START_WINDOW; \
 445         type AUX_RX_HALF_SYM_DETECT_LEN; \
 446         type AUX_RX_TRANSITION_FILTER_EN; \
 447         type AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT; \
 448         type AUX_RX_ALLOW_BELOW_THRESHOLD_START; \
 449         type AUX_RX_ALLOW_BELOW_THRESHOLD_STOP; \
 450         type AUX_RX_PHASE_DETECT_LEN; \
 451         type AUX_RX_DETECTION_THRESHOLD; \
 452         type AUX_TX_PRECHARGE_LEN; \
 453         type AUX_TX_PRECHARGE_SYMBOLS; \
 454         type AUX_MODE_DET_CHECK_DELAY;\
 455         type DPCS_DBG_CBUS_DIS;\
 456         type AUX_RX_PRECHARGE_SKIP;\
 457         type AUX_RX_TIMEOUT_LEN;\
 458         type AUX_RX_TIMEOUT_LEN_MUL
 459
 460 #define DCN30_LINK_ENCODER_REG_FIELD_LIST(type) \
 461         type TMDS_SYNC_DCBAL_EN;\
 462         type PHY_HPO_DIG_SRC_SEL;\
 463         type PHY_HPO_ENC_SRC_SEL;\
 464         type DPCS_TX_HDMI_FRL_MODE;\
 465         type DPCS_TX_DATA_SWAP_10_BIT;\
 466         type DPCS_TX_DATA_ORDER_INVERT_18_BIT;\
 467         type RDPCS_TX_CLK_EN
 468
 469 #define DCN31_LINK_ENCODER_REG_FIELD_LIST(type) \
 470         type ENC_TYPE_SEL;\
 471         type HPO_DP_ENC_SEL;\
 472         type HPO_HDMI_ENC_SEL
 473
 474 struct dcn10_link_enc_shift {
 475         DCN_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
 476         DCN20_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
 477         DCN30_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
 478         DCN31_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
 479 };
 480
 481 struct dcn10_link_enc_mask {
 482         DCN_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
 483         DCN20_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
 484         DCN30_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
 485         DCN31_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
 486 };
 487
 488 struct dcn10_link_encoder {
 489         struct link_encoder base;
 490         const struct dcn10_link_enc_registers *link_regs;
 491         const struct dcn10_link_enc_aux_registers *aux_regs;
 492         const struct dcn10_link_enc_hpd_registers *hpd_regs;
 493         const struct dcn10_link_enc_shift *link_shift;
 494         const struct dcn10_link_enc_mask *link_mask;
 495 };
 496
 497
 498 void dcn10_link_encoder_construct(
 499         struct dcn10_link_encoder *enc10,
 500         const struct encoder_init_data *init_data,
 501         const struct encoder_feature_support *enc_features,
 502         const struct dcn10_link_enc_registers *link_regs,
 503         const struct dcn10_link_enc_aux_registers *aux_regs,
 504         const struct dcn10_link_enc_hpd_registers *hpd_regs,
 505         const struct dcn10_link_enc_shift *link_shift,
 506         const struct dcn10_link_enc_mask *link_mask);
 507
 508 bool dcn10_link_encoder_validate_dvi_output(
 509         const struct dcn10_link_encoder *enc10,
 510         enum signal_type connector_signal,
 511         enum signal_type signal,
 512         const struct dc_crtc_timing *crtc_timing);
 513
 514 bool dcn10_link_encoder_validate_rgb_output(
 515         const struct dcn10_link_encoder *enc10,
 516         const struct dc_crtc_timing *crtc_timing);
 517
 518 bool dcn10_link_encoder_validate_dp_output(
 519         const struct dcn10_link_encoder *enc10,
 520         const struct dc_crtc_timing *crtc_timing);
 521
 522 bool dcn10_link_encoder_validate_wireless_output(
 523         const struct dcn10_link_encoder *enc10,
 524         const struct dc_crtc_timing *crtc_timing);
 525
 526 bool dcn10_link_encoder_validate_output_with_stream(
 527         struct link_encoder *enc,
 528         const struct dc_stream_state *stream);
 529
 530 /****************** HW programming ************************/
 531
 532 /* initialize HW */  /* why do we initialze aux in here? */
 533 void dcn10_link_encoder_hw_init(struct link_encoder *enc);
 534
 535 void dcn10_link_encoder_destroy(struct link_encoder **enc);
 536
 537 /* program DIG_MODE in DIG_BE */
 538 /* TODO can this be combined with enable_output? */
 539 void dcn10_link_encoder_setup(
 540         struct link_encoder *enc,
 541         enum signal_type signal);
 542
 543 void enc1_configure_encoder(
 544         struct dcn10_link_encoder *enc10,
 545         const struct dc_link_settings *link_settings);
 546
 547 /* enables TMDS PHY output */
 548 /* TODO: still need depth or just pass in adjusted pixel clock? */
 549 void dcn10_link_encoder_enable_tmds_output(
 550         struct link_encoder *enc,
 551         enum clock_source_id clock_source,
 552         enum dc_color_depth color_depth,
 553         enum signal_type signal,
 554         uint32_t pixel_clock);
 555
 556 void dcn10_link_encoder_enable_tmds_output_with_clk_pattern_wa(
 557         struct link_encoder *enc,
 558         enum clock_source_id clock_source,
 559         enum dc_color_depth color_depth,
 560         enum signal_type signal,
 561         uint32_t pixel_clock);
 562
 563 /* enables DP PHY output */
 564 void dcn10_link_encoder_enable_dp_output(
 565         struct link_encoder *enc,
 566         const struct dc_link_settings *link_settings,
 567         enum clock_source_id clock_source);
 568
 569 /* enables DP PHY output in MST mode */
 570 void dcn10_link_encoder_enable_dp_mst_output(
 571         struct link_encoder *enc,
 572         const struct dc_link_settings *link_settings,
 573         enum clock_source_id clock_source);
 574
 575 /* disable PHY output */
 576 void dcn10_link_encoder_disable_output(
 577         struct link_encoder *enc,
 578         enum signal_type signal);
 579
 580 /* set DP lane settings */
 581 void dcn10_link_encoder_dp_set_lane_settings(
 582         struct link_encoder *enc,
 583         const struct link_training_settings *link_settings);
 584
 585 void dcn10_link_encoder_dp_set_phy_pattern(
 586         struct link_encoder *enc,
 587         const struct encoder_set_dp_phy_pattern_param *param);
 588
 589 /* programs DP MST VC payload allocation */
 590 void dcn10_link_encoder_update_mst_stream_allocation_table(
 591         struct link_encoder *enc,
 592         const struct link_mst_stream_allocation_table *table);
 593
 594 void dcn10_link_encoder_connect_dig_be_to_fe(
 595         struct link_encoder *enc,
 596         enum engine_id engine,
 597         bool connect);
 598
 599 void dcn10_link_encoder_set_dp_phy_pattern_training_pattern(
 600         struct link_encoder *enc,
 601         uint32_t index);
 602
 603 void dcn10_link_encoder_enable_hpd(struct link_encoder *enc);
 604
 605 void dcn10_link_encoder_disable_hpd(struct link_encoder *enc);
 606
 607 void dcn10_psr_program_dp_dphy_fast_training(struct link_encoder *enc,
 608                         bool exit_link_training_required);
 609
 610 void dcn10_psr_program_secondary_packet(struct link_encoder *enc,
 611                         unsigned int sdp_transmit_line_num_deadline);
 612
 613 bool dcn10_is_dig_enabled(struct link_encoder *enc);
 614
 615 unsigned int dcn10_get_dig_frontend(struct link_encoder *enc);
 616
 617 void dcn10_aux_initialize(struct dcn10_link_encoder *enc10);
 618
 619 enum signal_type dcn10_get_dig_mode(
 620         struct link_encoder *enc);
 621
 622 void dcn10_link_encoder_get_max_link_cap(struct link_encoder *enc,
 623         struct dc_link_settings *link_settings);
 624 #endif /* __DC_LINK_ENCODER__DCN10_H__ */