drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 #include "dm_services.h"
  26 #include "dce_calcs.h"
  27 #include "reg_helper.h"
  28 #include "basics/conversion.h"
  29 #include "dcn10_hubp.h"
  30
  31 #define REG(reg)\
  32         hubp1->hubp_regs->reg
  33
  34 #define CTX \
  35         hubp1->base.ctx
  36
  37 #undef FN
  38 #define FN(reg_name, field_name) \
  39         hubp1->hubp_shift->field_name, hubp1->hubp_mask->field_name
  40
  41 void hubp1_set_blank(struct hubp *hubp, bool blank)
  42 {
  43         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
  44         uint32_t blank_en = blank ? 1 : 0;
  45
  46         REG_UPDATE_2(DCHUBP_CNTL,
  47                         HUBP_BLANK_EN, blank_en,
  48                         HUBP_TTU_DISABLE, blank_en);
  49
  50         if (blank) {
  51                 uint32_t reg_val = REG_READ(DCHUBP_CNTL);
  52
  53                 if (reg_val) {
  54                         /* init sequence workaround: in case HUBP is
  55                          * power gated, this wait would timeout.
  56                          *
  57                          * we just wrote reg_val to non-0, if it stay 0
  58                          * it means HUBP is gated
  59                          */
  60                         REG_WAIT(DCHUBP_CNTL,
  61                                         HUBP_NO_OUTSTANDING_REQ, 1,
  62                                         1, 200);
  63                 }
  64
  65                 hubp->mpcc_id = 0xf;
  66                 hubp->opp_id = OPP_ID_INVALID;
  67         }
  68 }
  69
  70 static void hubp1_disconnect(struct hubp *hubp)
  71 {
  72         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
  73
  74         REG_UPDATE(DCHUBP_CNTL,
  75                         HUBP_TTU_DISABLE, 1);
  76
  77         REG_UPDATE(CURSOR_CONTROL,
  78                         CURSOR_ENABLE, 0);
  79 }
  80
  81 static void hubp1_disable_control(struct hubp *hubp, bool disable_hubp)
  82 {
  83         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
  84         uint32_t disable = disable_hubp ? 1 : 0;
  85
  86         REG_UPDATE(DCHUBP_CNTL,
  87                         HUBP_DISABLE, disable);
  88 }
  89
  90 static unsigned int hubp1_get_underflow_status(struct hubp *hubp)
  91 {
  92         uint32_t hubp_underflow = 0;
  93         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
  94
  95         REG_GET(DCHUBP_CNTL,
  96                 HUBP_UNDERFLOW_STATUS,
  97                 &hubp_underflow);
  98
  99         return hubp_underflow;
 100 }
 101
 102
 103 void hubp1_clear_underflow(struct hubp *hubp)
 104 {
 105         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 106
 107         REG_UPDATE(DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, 1);
 108 }
 109
 110 static void hubp1_set_hubp_blank_en(struct hubp *hubp, bool blank)
 111 {
 112         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 113         uint32_t blank_en = blank ? 1 : 0;
 114
 115         REG_UPDATE(DCHUBP_CNTL, HUBP_BLANK_EN, blank_en);
 116 }
 117
 118 void hubp1_vready_workaround(struct hubp *hubp,
 119                 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
 120 {
 121         uint32_t value = 0;
 122         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 123
 124         /* set HBUBREQ_DEBUG_DB[12] = 1 */
 125         value = REG_READ(HUBPREQ_DEBUG_DB);
 126
 127         /* hack mode disable */
 128         value |= 0x100;
 129         value &= ~0x1000;
 130
 131         if ((pipe_dest->vstartup_start - 2*(pipe_dest->vready_offset+pipe_dest->vupdate_width
 132                 + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) {
 133                 /* if (eco_fix_needed(otg_global_sync_timing)
 134                  * set HBUBREQ_DEBUG_DB[12] = 1 */
 135                 value |= 0x1000;
 136         }
 137
 138         REG_WRITE(HUBPREQ_DEBUG_DB, value);
 139 }
 140
 141 void hubp1_program_tiling(
 142         struct hubp *hubp,
 143         const union dc_tiling_info *info,
 144         const enum surface_pixel_format pixel_format)
 145 {
 146         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 147
 148         REG_UPDATE_6(DCSURF_ADDR_CONFIG,
 149                         NUM_PIPES, log_2(info->gfx9.num_pipes),
 150                         NUM_BANKS, log_2(info->gfx9.num_banks),
 151                         PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
 152                         NUM_SE, log_2(info->gfx9.num_shader_engines),
 153                         NUM_RB_PER_SE, log_2(info->gfx9.num_rb_per_se),
 154                         MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags));
 155
 156         REG_UPDATE_4(DCSURF_TILING_CONFIG,
 157                         SW_MODE, info->gfx9.swizzle,
 158                         META_LINEAR, info->gfx9.meta_linear,
 159                         RB_ALIGNED, info->gfx9.rb_aligned,
 160                         PIPE_ALIGNED, info->gfx9.pipe_aligned);
 161 }
 162
 163 void hubp1_program_size(
 164         struct hubp *hubp,
 165         enum surface_pixel_format format,
 166         const struct plane_size *plane_size,
 167         struct dc_plane_dcc_param *dcc)
 168 {
 169         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 170         uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c;
 171
 172         /* Program data and meta surface pitch (calculation from addrlib)
 173          * 444 or 420 luma
 174          */
 175         if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN && format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END) {
 176                 ASSERT(plane_size->chroma_pitch != 0);
 177                 /* Chroma pitch zero can cause system hang! */
 178
 179                 pitch = plane_size->surface_pitch - 1;
 180                 meta_pitch = dcc->meta_pitch - 1;
 181                 pitch_c = plane_size->chroma_pitch - 1;
 182                 meta_pitch_c = dcc->meta_pitch_c - 1;
 183         } else {
 184                 pitch = plane_size->surface_pitch - 1;
 185                 meta_pitch = dcc->meta_pitch - 1;
 186                 pitch_c = 0;
 187                 meta_pitch_c = 0;
 188         }
 189
 190         if (!dcc->enable) {
 191                 meta_pitch = 0;
 192                 meta_pitch_c = 0;
 193         }
 194
 195         REG_UPDATE_2(DCSURF_SURFACE_PITCH,
 196                         PITCH, pitch, META_PITCH, meta_pitch);
 197
 198         if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
 199                 REG_UPDATE_2(DCSURF_SURFACE_PITCH_C,
 200                         PITCH_C, pitch_c, META_PITCH_C, meta_pitch_c);
 201 }
 202
 203 void hubp1_program_rotation(
 204         struct hubp *hubp,
 205         enum dc_rotation_angle rotation,
 206         bool horizontal_mirror)
 207 {
 208         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 209         uint32_t mirror;
 210
 211
 212         if (horizontal_mirror)
 213                 mirror = 1;
 214         else
 215                 mirror = 0;
 216
 217         /* Program rotation angle and horz mirror - no mirror */
 218         if (rotation == ROTATION_ANGLE_0)
 219                 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
 220                                 ROTATION_ANGLE, 0,
 221                                 H_MIRROR_EN, mirror);
 222         else if (rotation == ROTATION_ANGLE_90)
 223                 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
 224                                 ROTATION_ANGLE, 1,
 225                                 H_MIRROR_EN, mirror);
 226         else if (rotation == ROTATION_ANGLE_180)
 227                 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
 228                                 ROTATION_ANGLE, 2,
 229                                 H_MIRROR_EN, mirror);
 230         else if (rotation == ROTATION_ANGLE_270)
 231                 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
 232                                 ROTATION_ANGLE, 3,
 233                                 H_MIRROR_EN, mirror);
 234 }
 235
 236 void hubp1_program_pixel_format(
 237         struct hubp *hubp,
 238         enum surface_pixel_format format)
 239 {
 240         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 241         uint32_t red_bar = 3;
 242         uint32_t blue_bar = 2;
 243
 244         /* swap for ABGR format */
 245         if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888
 246                         || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010
 247                         || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS
 248                         || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616
 249                         || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) {
 250                 red_bar = 2;
 251                 blue_bar = 3;
 252         }
 253
 254         REG_UPDATE_2(HUBPRET_CONTROL,
 255                         CROSSBAR_SRC_CB_B, blue_bar,
 256                         CROSSBAR_SRC_CR_R, red_bar);
 257
 258         /* Mapping is same as ipp programming (cnvc) */
 259
 260         switch (format) {
 261         case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
 262                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 263                                 SURFACE_PIXEL_FORMAT, 1);
 264                 break;
 265         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
 266                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 267                                 SURFACE_PIXEL_FORMAT, 3);
 268                 break;
 269         case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
 270         case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
 271                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 272                                 SURFACE_PIXEL_FORMAT, 8);
 273                 break;
 274         case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
 275         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
 276         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
 277                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 278                                 SURFACE_PIXEL_FORMAT, 10);
 279                 break;
 280         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
 281                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 282                                 SURFACE_PIXEL_FORMAT, 22);
 283                 break;
 284         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: /*we use crossbar already*/
 285                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 286                                 SURFACE_PIXEL_FORMAT, 26); /* ARGB16161616_UNORM */
 287                 break;
 288         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
 289         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/
 290                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 291                                 SURFACE_PIXEL_FORMAT, 24);
 292                 break;
 293
 294         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
 295                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 296                                 SURFACE_PIXEL_FORMAT, 65);
 297                 break;
 298         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
 299                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 300                                 SURFACE_PIXEL_FORMAT, 64);
 301                 break;
 302         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
 303                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 304                                 SURFACE_PIXEL_FORMAT, 67);
 305                 break;
 306         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
 307                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 308                                 SURFACE_PIXEL_FORMAT, 66);
 309                 break;
 310         case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888:
 311                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 312                                 SURFACE_PIXEL_FORMAT, 12);
 313                 break;
 314         case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:
 315                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 316                                 SURFACE_PIXEL_FORMAT, 112);
 317                 break;
 318         case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX:
 319                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 320                                 SURFACE_PIXEL_FORMAT, 113);
 321                 break;
 322         case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010:
 323                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 324                                 SURFACE_PIXEL_FORMAT, 114);
 325                 break;
 326         case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT:
 327                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 328                                 SURFACE_PIXEL_FORMAT, 118);
 329                 break;
 330         case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT:
 331                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 332                                 SURFACE_PIXEL_FORMAT, 119);
 333                 break;
 334         case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
 335                 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
 336                                 SURFACE_PIXEL_FORMAT, 116,
 337                                 ALPHA_PLANE_EN, 0);
 338                 break;
 339         case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
 340                 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
 341                                 SURFACE_PIXEL_FORMAT, 116,
 342                                 ALPHA_PLANE_EN, 1);
 343                 break;
 344         default:
 345                 BREAK_TO_DEBUGGER();
 346                 break;
 347         }
 348
 349         /* don't see the need of program the xbar in DCN 1.0 */
 350 }
 351
 352 bool hubp1_program_surface_flip_and_addr(
 353         struct hubp *hubp,
 354         const struct dc_plane_address *address,
 355         bool flip_immediate)
 356 {
 357         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 358
 359
 360         //program flip type
 361         REG_UPDATE(DCSURF_FLIP_CONTROL,
 362                         SURFACE_FLIP_TYPE, flip_immediate);
 363
 364
 365         if (address->type == PLN_ADDR_TYPE_GRPH_STEREO) {
 366                 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x1);
 367                 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x1);
 368
 369         } else {
 370                 // turn off stereo if not in stereo
 371                 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x0);
 372                 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x0);
 373         }
 374
 375
 376
 377         /* HW automatically latch rest of address register on write to
 378          * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used
 379          *
 380          * program high first and then the low addr, order matters!
 381          */
 382         switch (address->type) {
 383         case PLN_ADDR_TYPE_GRAPHICS:
 384                 /* DCN1.0 does not support const color
 385                  * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1
 386                  * base on address->grph.dcc_const_color
 387                  * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma
 388                  * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma
 389                  */
 390
 391                 if (address->grph.addr.quad_part == 0)
 392                         break;
 393
 394                 REG_UPDATE_2(DCSURF_SURFACE_CONTROL,
 395                                 PRIMARY_SURFACE_TMZ, address->tmz_surface,
 396                                 PRIMARY_META_SURFACE_TMZ, address->tmz_surface);
 397
 398                 if (address->grph.meta_addr.quad_part != 0) {
 399                         REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
 400                                         PRIMARY_META_SURFACE_ADDRESS_HIGH,
 401                                         address->grph.meta_addr.high_part);
 402
 403                         REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
 404                                         PRIMARY_META_SURFACE_ADDRESS,
 405                                         address->grph.meta_addr.low_part);
 406                 }
 407
 408                 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
 409                                 PRIMARY_SURFACE_ADDRESS_HIGH,
 410                                 address->grph.addr.high_part);
 411
 412                 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
 413                                 PRIMARY_SURFACE_ADDRESS,
 414                                 address->grph.addr.low_part);
 415                 break;
 416         case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE:
 417                 if (address->video_progressive.luma_addr.quad_part == 0
 418                         || address->video_progressive.chroma_addr.quad_part == 0)
 419                         break;
 420
 421                 REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
 422                                 PRIMARY_SURFACE_TMZ, address->tmz_surface,
 423                                 PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
 424                                 PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
 425                                 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface);
 426
 427                 if (address->video_progressive.luma_meta_addr.quad_part != 0) {
 428                         REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
 429                                 PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
 430                                 address->video_progressive.chroma_meta_addr.high_part);
 431
 432                         REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,
 433                                 PRIMARY_META_SURFACE_ADDRESS_C,
 434                                 address->video_progressive.chroma_meta_addr.low_part);
 435
 436                         REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
 437                                 PRIMARY_META_SURFACE_ADDRESS_HIGH,
 438                                 address->video_progressive.luma_meta_addr.high_part);
 439
 440                         REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
 441                                 PRIMARY_META_SURFACE_ADDRESS,
 442                                 address->video_progressive.luma_meta_addr.low_part);
 443                 }
 444
 445                 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,
 446                         PRIMARY_SURFACE_ADDRESS_HIGH_C,
 447                         address->video_progressive.chroma_addr.high_part);
 448
 449                 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,
 450                         PRIMARY_SURFACE_ADDRESS_C,
 451                         address->video_progressive.chroma_addr.low_part);
 452
 453                 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
 454                         PRIMARY_SURFACE_ADDRESS_HIGH,
 455                         address->video_progressive.luma_addr.high_part);
 456
 457                 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
 458                         PRIMARY_SURFACE_ADDRESS,
 459                         address->video_progressive.luma_addr.low_part);
 460                 break;
 461         case PLN_ADDR_TYPE_GRPH_STEREO:
 462                 if (address->grph_stereo.left_addr.quad_part == 0)
 463                         break;
 464                 if (address->grph_stereo.right_addr.quad_part == 0)
 465                         break;
 466
 467                 REG_UPDATE_8(DCSURF_SURFACE_CONTROL,
 468                                 PRIMARY_SURFACE_TMZ, address->tmz_surface,
 469                                 PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
 470                                 PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
 471                                 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface,
 472                                 SECONDARY_SURFACE_TMZ, address->tmz_surface,
 473                                 SECONDARY_SURFACE_TMZ_C, address->tmz_surface,
 474                                 SECONDARY_META_SURFACE_TMZ, address->tmz_surface,
 475                                 SECONDARY_META_SURFACE_TMZ_C, address->tmz_surface);
 476
 477                 if (address->grph_stereo.right_meta_addr.quad_part != 0) {
 478
 479                         REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0,
 480                                         SECONDARY_META_SURFACE_ADDRESS_HIGH,
 481                                         address->grph_stereo.right_meta_addr.high_part);
 482
 483                         REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0,
 484                                         SECONDARY_META_SURFACE_ADDRESS,
 485                                         address->grph_stereo.right_meta_addr.low_part);
 486                 }
 487                 if (address->grph_stereo.left_meta_addr.quad_part != 0) {
 488
 489                         REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
 490                                         PRIMARY_META_SURFACE_ADDRESS_HIGH,
 491                                         address->grph_stereo.left_meta_addr.high_part);
 492
 493                         REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
 494                                         PRIMARY_META_SURFACE_ADDRESS,
 495                                         address->grph_stereo.left_meta_addr.low_part);
 496                 }
 497
 498                 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0,
 499                                 SECONDARY_SURFACE_ADDRESS_HIGH,
 500                                 address->grph_stereo.right_addr.high_part);
 501
 502                 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0,
 503                                 SECONDARY_SURFACE_ADDRESS,
 504                                 address->grph_stereo.right_addr.low_part);
 505
 506                 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
 507                                 PRIMARY_SURFACE_ADDRESS_HIGH,
 508                                 address->grph_stereo.left_addr.high_part);
 509
 510                 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
 511                                 PRIMARY_SURFACE_ADDRESS,
 512                                 address->grph_stereo.left_addr.low_part);
 513                 break;
 514         default:
 515                 BREAK_TO_DEBUGGER();
 516                 break;
 517         }
 518
 519         hubp->request_address = *address;
 520
 521         return true;
 522 }
 523
 524 void hubp1_dcc_control(struct hubp *hubp, bool enable,
 525                 enum hubp_ind_block_size independent_64b_blks)
 526 {
 527         uint32_t dcc_en = enable ? 1 : 0;
 528         uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0;
 529         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 530
 531         REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
 532                         PRIMARY_SURFACE_DCC_EN, dcc_en,
 533                         PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk,
 534                         SECONDARY_SURFACE_DCC_EN, dcc_en,
 535                         SECONDARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk);
 536 }
 537
 538 void hubp1_program_surface_config(
 539         struct hubp *hubp,
 540         enum surface_pixel_format format,
 541         union dc_tiling_info *tiling_info,
 542         struct plane_size *plane_size,
 543         enum dc_rotation_angle rotation,
 544         struct dc_plane_dcc_param *dcc,
 545         bool horizontal_mirror,
 546         unsigned int compat_level)
 547 {
 548         hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks);
 549         hubp1_program_tiling(hubp, tiling_info, format);
 550         hubp1_program_size(hubp, format, plane_size, dcc);
 551         hubp1_program_rotation(hubp, rotation, horizontal_mirror);
 552         hubp1_program_pixel_format(hubp, format);
 553 }
 554
 555 void hubp1_program_requestor(
 556                 struct hubp *hubp,
 557                 struct _vcs_dpi_display_rq_regs_st *rq_regs)
 558 {
 559         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 560
 561         REG_UPDATE(HUBPRET_CONTROL,
 562                         DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address);
 563         REG_SET_4(DCN_EXPANSION_MODE, 0,
 564                         DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode,
 565                         PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode,
 566                         MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode,
 567                         CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
 568         REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0,
 569                 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
 570                 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
 571                 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
 572                 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size,
 573                 DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size,
 574                 MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size,
 575                 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height,
 576                 PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear);
 577         REG_SET_8(DCHUBP_REQ_SIZE_CONFIG_C, 0,
 578                 CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size,
 579                 MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size,
 580                 META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size,
 581                 MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size,
 582                 DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size,
 583                 MPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.mpte_group_size,
 584                 SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height,
 585                 PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear);
 586 }
 587
 588
 589 void hubp1_program_deadline(
 590                 struct hubp *hubp,
 591                 struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
 592                 struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
 593 {
 594         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 595
 596         /* DLG - Per hubp */
 597         REG_SET_2(BLANK_OFFSET_0, 0,
 598                 REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end,
 599                 DLG_V_BLANK_END, dlg_attr->dlg_vblank_end);
 600
 601         REG_SET(BLANK_OFFSET_1, 0,
 602                 MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start);
 603
 604         REG_SET(DST_DIMENSIONS, 0,
 605                 REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal);
 606
 607         REG_SET_2(DST_AFTER_SCALER, 0,
 608                 REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler,
 609                 DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler);
 610
 611         REG_SET(REF_FREQ_TO_PIX_FREQ, 0,
 612                 REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq);
 613
 614         /* DLG - Per luma/chroma */
 615         REG_SET(VBLANK_PARAMETERS_1, 0,
 616                 REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l);
 617
 618         if (REG(NOM_PARAMETERS_0))
 619                 REG_SET(NOM_PARAMETERS_0, 0,
 620                         DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l);
 621
 622         if (REG(NOM_PARAMETERS_1))
 623                 REG_SET(NOM_PARAMETERS_1, 0,
 624                         REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l);
 625
 626         REG_SET(NOM_PARAMETERS_4, 0,
 627                 DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l);
 628
 629         REG_SET(NOM_PARAMETERS_5, 0,
 630                 REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l);
 631
 632         REG_SET_2(PER_LINE_DELIVERY, 0,
 633                 REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l,
 634                 REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c);
 635
 636         REG_SET(VBLANK_PARAMETERS_2, 0,
 637                 REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c);
 638
 639         if (REG(NOM_PARAMETERS_2))
 640                 REG_SET(NOM_PARAMETERS_2, 0,
 641                         DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c);
 642
 643         if (REG(NOM_PARAMETERS_3))
 644                 REG_SET(NOM_PARAMETERS_3, 0,
 645                         REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c);
 646
 647         REG_SET(NOM_PARAMETERS_6, 0,
 648                 DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c);
 649
 650         REG_SET(NOM_PARAMETERS_7, 0,
 651                 REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c);
 652
 653         /* TTU - per hubp */
 654         REG_SET_2(DCN_TTU_QOS_WM, 0,
 655                 QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm,
 656                 QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm);
 657
 658         /* TTU - per luma/chroma */
 659         /* Assumed surf0 is luma and 1 is chroma */
 660
 661         REG_SET_3(DCN_SURF0_TTU_CNTL0, 0,
 662                 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l,
 663                 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l,
 664                 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l);
 665
 666         REG_SET_3(DCN_SURF1_TTU_CNTL0, 0,
 667                 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c,
 668                 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c,
 669                 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c);
 670
 671         REG_SET_3(DCN_CUR0_TTU_CNTL0, 0,
 672                 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0,
 673                 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0,
 674                 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0);
 675 }
 676
 677 static void hubp1_setup(
 678                 struct hubp *hubp,
 679                 struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
 680                 struct _vcs_dpi_display_ttu_regs_st *ttu_attr,
 681                 struct _vcs_dpi_display_rq_regs_st *rq_regs,
 682                 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
 683 {
 684         /* otg is locked when this func is called. Register are double buffered.
 685          * disable the requestors is not needed
 686          */
 687         hubp1_program_requestor(hubp, rq_regs);
 688         hubp1_program_deadline(hubp, dlg_attr, ttu_attr);
 689         hubp1_vready_workaround(hubp, pipe_dest);
 690 }
 691
 692 static void hubp1_setup_interdependent(
 693                 struct hubp *hubp,
 694                 struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
 695                 struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
 696 {
 697         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 698
 699         REG_SET_2(PREFETCH_SETTINS, 0,
 700                 DST_Y_PREFETCH, dlg_attr->dst_y_prefetch,
 701                 VRATIO_PREFETCH, dlg_attr->vratio_prefetch);
 702
 703         REG_SET(PREFETCH_SETTINS_C, 0,
 704                 VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c);
 705
 706         REG_SET_2(VBLANK_PARAMETERS_0, 0,
 707                 DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank,
 708                 DST_Y_PER_ROW_VBLANK, dlg_attr->dst_y_per_row_vblank);
 709
 710         REG_SET(VBLANK_PARAMETERS_3, 0,
 711                 REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l);
 712
 713         REG_SET(VBLANK_PARAMETERS_4, 0,
 714                 REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c);
 715
 716         REG_SET_2(PER_LINE_DELIVERY_PRE, 0,
 717                 REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l,
 718                 REFCYC_PER_LINE_DELIVERY_PRE_C, dlg_attr->refcyc_per_line_delivery_pre_c);
 719
 720         REG_SET(DCN_SURF0_TTU_CNTL1, 0,
 721                 REFCYC_PER_REQ_DELIVERY_PRE,
 722                 ttu_attr->refcyc_per_req_delivery_pre_l);
 723         REG_SET(DCN_SURF1_TTU_CNTL1, 0,
 724                 REFCYC_PER_REQ_DELIVERY_PRE,
 725                 ttu_attr->refcyc_per_req_delivery_pre_c);
 726         REG_SET(DCN_CUR0_TTU_CNTL1, 0,
 727                 REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0);
 728
 729         REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0,
 730                 MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank,
 731                 QoS_LEVEL_FLIP, ttu_attr->qos_level_flip);
 732 }
 733
 734 bool hubp1_is_flip_pending(struct hubp *hubp)
 735 {
 736         uint32_t flip_pending = 0;
 737         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 738         struct dc_plane_address earliest_inuse_address;
 739
 740         if (hubp && hubp->power_gated)
 741                 return false;
 742
 743         REG_GET(DCSURF_FLIP_CONTROL,
 744                         SURFACE_FLIP_PENDING, &flip_pending);
 745
 746         REG_GET(DCSURF_SURFACE_EARLIEST_INUSE,
 747                         SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part);
 748
 749         REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,
 750                         SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part);
 751
 752         if (flip_pending)
 753                 return true;
 754
 755         if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part)
 756                 return true;
 757
 758         return false;
 759 }
 760
 761 uint32_t aperture_default_system = 1;
 762 uint32_t context0_default_system; /* = 0;*/
 763
 764 static void hubp1_set_vm_system_aperture_settings(struct hubp *hubp,
 765                 struct vm_system_aperture_param *apt)
 766 {
 767         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 768         PHYSICAL_ADDRESS_LOC mc_vm_apt_default;
 769         PHYSICAL_ADDRESS_LOC mc_vm_apt_low;
 770         PHYSICAL_ADDRESS_LOC mc_vm_apt_high;
 771
 772         mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12;
 773         mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 12;
 774         mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 12;
 775
 776         REG_SET_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 0,
 777                 MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, aperture_default_system, /* 1 = system physical memory */
 778                 MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mc_vm_apt_default.high_part);
 779         REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0,
 780                 MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mc_vm_apt_default.low_part);
 781
 782         REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, 0,
 783                         MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mc_vm_apt_low.high_part);
 784         REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, 0,
 785                         MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mc_vm_apt_low.low_part);
 786
 787         REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, 0,
 788                         MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mc_vm_apt_high.high_part);
 789         REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, 0,
 790                         MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mc_vm_apt_high.low_part);
 791 }
 792
 793 static void hubp1_set_vm_context0_settings(struct hubp *hubp,
 794                 const struct vm_context0_param *vm0)
 795 {
 796         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 797         /* pte base */
 798         REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, 0,
 799                         VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, vm0->pte_base.high_part);
 800         REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, 0,
 801                         VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, vm0->pte_base.low_part);
 802
 803         /* pte start */
 804         REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, 0,
 805                         VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, vm0->pte_start.high_part);
 806         REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, 0,
 807                         VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, vm0->pte_start.low_part);
 808
 809         /* pte end */
 810         REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, 0,
 811                         VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, vm0->pte_end.high_part);
 812         REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, 0,
 813                         VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, vm0->pte_end.low_part);
 814
 815         /* fault handling */
 816         REG_SET_2(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0,
 817                         VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, vm0->fault_default.high_part,
 818                         VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, context0_default_system);
 819         REG_SET(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0,
 820                         VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, vm0->fault_default.low_part);
 821
 822         /* control: enable VM PTE*/
 823         REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,
 824                         ENABLE_L1_TLB, 1,
 825                         SYSTEM_ACCESS_MODE, 3);
 826 }
 827
 828 void min_set_viewport(
 829         struct hubp *hubp,
 830         const struct rect *viewport,
 831         const struct rect *viewport_c)
 832 {
 833         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 834
 835         REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0,
 836                   PRI_VIEWPORT_WIDTH, viewport->width,
 837                   PRI_VIEWPORT_HEIGHT, viewport->height);
 838
 839         REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0,
 840                   PRI_VIEWPORT_X_START, viewport->x,
 841                   PRI_VIEWPORT_Y_START, viewport->y);
 842
 843         /*for stereo*/
 844         REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0,
 845                   SEC_VIEWPORT_WIDTH, viewport->width,
 846                   SEC_VIEWPORT_HEIGHT, viewport->height);
 847
 848         REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0,
 849                   SEC_VIEWPORT_X_START, viewport->x,
 850                   SEC_VIEWPORT_Y_START, viewport->y);
 851
 852         /* DC supports NV12 only at the moment */
 853         REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0,
 854                   PRI_VIEWPORT_WIDTH_C, viewport_c->width,
 855                   PRI_VIEWPORT_HEIGHT_C, viewport_c->height);
 856
 857         REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0,
 858                   PRI_VIEWPORT_X_START_C, viewport_c->x,
 859                   PRI_VIEWPORT_Y_START_C, viewport_c->y);
 860
 861         REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION_C, 0,
 862                   SEC_VIEWPORT_WIDTH_C, viewport_c->width,
 863                   SEC_VIEWPORT_HEIGHT_C, viewport_c->height);
 864
 865         REG_SET_2(DCSURF_SEC_VIEWPORT_START_C, 0,
 866                   SEC_VIEWPORT_X_START_C, viewport_c->x,
 867                   SEC_VIEWPORT_Y_START_C, viewport_c->y);
 868 }
 869
 870 void hubp1_read_state_common(struct hubp *hubp)
 871 {
 872         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 873         struct dcn_hubp_state *s = &hubp1->state;
 874         struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr;
 875         struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr;
 876         struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
 877         uint32_t aperture_low_msb, aperture_low_lsb;
 878         uint32_t aperture_high_msb, aperture_high_lsb;
 879
 880         /* Requester */
 881         REG_GET(HUBPRET_CONTROL,
 882                         DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address);
 883         REG_GET_4(DCN_EXPANSION_MODE,
 884                         DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode,
 885                         PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode,
 886                         MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode,
 887                         CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode);
 888
 889         REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB,
 890                         MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, &aperture_low_msb);
 891
 892         REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB,
 893                         MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, &aperture_low_lsb);
 894
 895         REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB,
 896                         MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, &aperture_high_msb);
 897
 898         REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB,
 899                         MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, &aperture_high_lsb);
 900
 901         // On DCN1, aperture is broken down into MSB and LSB; only keep bits [47:18] to match later DCN format
 902         rq_regs->aperture_low_addr = (aperture_low_msb << 26) | (aperture_low_lsb >> 6);
 903         rq_regs->aperture_high_addr = (aperture_high_msb << 26) | (aperture_high_lsb >> 6);
 904
 905         /* DLG - Per hubp */
 906         REG_GET_2(BLANK_OFFSET_0,
 907                 REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end,
 908                 DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end);
 909
 910         REG_GET(BLANK_OFFSET_1,
 911                 MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start);
 912
 913         REG_GET(DST_DIMENSIONS,
 914                 REFCYC_PER_HTOTAL, &dlg_attr->refcyc_per_htotal);
 915
 916         REG_GET_2(DST_AFTER_SCALER,
 917                 REFCYC_X_AFTER_SCALER, &dlg_attr->refcyc_x_after_scaler,
 918                 DST_Y_AFTER_SCALER, &dlg_attr->dst_y_after_scaler);
 919
 920         if (REG(PREFETCH_SETTINS))
 921                 REG_GET_2(PREFETCH_SETTINS,
 922                         DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch,
 923                         VRATIO_PREFETCH, &dlg_attr->vratio_prefetch);
 924         else
 925                 REG_GET_2(PREFETCH_SETTINGS,
 926                         DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch,
 927                         VRATIO_PREFETCH, &dlg_attr->vratio_prefetch);
 928
 929         REG_GET_2(VBLANK_PARAMETERS_0,
 930                 DST_Y_PER_VM_VBLANK, &dlg_attr->dst_y_per_vm_vblank,
 931                 DST_Y_PER_ROW_VBLANK, &dlg_attr->dst_y_per_row_vblank);
 932
 933         REG_GET(REF_FREQ_TO_PIX_FREQ,
 934                 REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq);
 935
 936         /* DLG - Per luma/chroma */
 937         REG_GET(VBLANK_PARAMETERS_1,
 938                 REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr->refcyc_per_pte_group_vblank_l);
 939
 940         REG_GET(VBLANK_PARAMETERS_3,
 941                 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l);
 942
 943         if (REG(NOM_PARAMETERS_0))
 944                 REG_GET(NOM_PARAMETERS_0,
 945                         DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr->dst_y_per_pte_row_nom_l);
 946
 947         if (REG(NOM_PARAMETERS_1))
 948                 REG_GET(NOM_PARAMETERS_1,
 949                         REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr->refcyc_per_pte_group_nom_l);
 950
 951         REG_GET(NOM_PARAMETERS_4,
 952                 DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l);
 953
 954         REG_GET(NOM_PARAMETERS_5,
 955                 REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr->refcyc_per_meta_chunk_nom_l);
 956
 957         REG_GET_2(PER_LINE_DELIVERY_PRE,
 958                 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l,
 959                 REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr->refcyc_per_line_delivery_pre_c);
 960
 961         REG_GET_2(PER_LINE_DELIVERY,
 962                 REFCYC_PER_LINE_DELIVERY_L, &dlg_attr->refcyc_per_line_delivery_l,
 963                 REFCYC_PER_LINE_DELIVERY_C, &dlg_attr->refcyc_per_line_delivery_c);
 964
 965         if (REG(PREFETCH_SETTINS_C))
 966                 REG_GET(PREFETCH_SETTINS_C,
 967                         VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c);
 968         else
 969                 REG_GET(PREFETCH_SETTINGS_C,
 970                         VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c);
 971
 972         REG_GET(VBLANK_PARAMETERS_2,
 973                 REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr->refcyc_per_pte_group_vblank_c);
 974
 975         REG_GET(VBLANK_PARAMETERS_4,
 976                 REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr->refcyc_per_meta_chunk_vblank_c);
 977
 978         if (REG(NOM_PARAMETERS_2))
 979                 REG_GET(NOM_PARAMETERS_2,
 980                         DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr->dst_y_per_pte_row_nom_c);
 981
 982         if (REG(NOM_PARAMETERS_3))
 983                 REG_GET(NOM_PARAMETERS_3,
 984                         REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr->refcyc_per_pte_group_nom_c);
 985
 986         REG_GET(NOM_PARAMETERS_6,
 987                 DST_Y_PER_META_ROW_NOM_C, &dlg_attr->dst_y_per_meta_row_nom_c);
 988
 989         REG_GET(NOM_PARAMETERS_7,
 990                 REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr->refcyc_per_meta_chunk_nom_c);
 991
 992         /* TTU - per hubp */
 993         REG_GET_2(DCN_TTU_QOS_WM,
 994                 QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm,
 995                 QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm);
 996
 997         REG_GET_2(DCN_GLOBAL_TTU_CNTL,
 998                 MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank,
 999                 QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip);
1000
1001         /* TTU - per luma/chroma */
1002         /* Assumed surf0 is luma and 1 is chroma */
1003
1004         REG_GET_3(DCN_SURF0_TTU_CNTL0,
1005                 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l,
1006                 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l,
1007                 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l);
1008
1009         REG_GET(DCN_SURF0_TTU_CNTL1,
1010                 REFCYC_PER_REQ_DELIVERY_PRE,
1011                 &ttu_attr->refcyc_per_req_delivery_pre_l);
1012
1013         REG_GET_3(DCN_SURF1_TTU_CNTL0,
1014                 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c,
1015                 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c,
1016                 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c);
1017
1018         REG_GET(DCN_SURF1_TTU_CNTL1,
1019                 REFCYC_PER_REQ_DELIVERY_PRE,
1020                 &ttu_attr->refcyc_per_req_delivery_pre_c);
1021
1022         /* Rest of hubp */
1023         REG_GET(DCSURF_SURFACE_CONFIG,
1024                         SURFACE_PIXEL_FORMAT, &s->pixel_format);
1025
1026         REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,
1027                         SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi);
1028
1029         REG_GET(DCSURF_SURFACE_EARLIEST_INUSE,
1030                         SURFACE_EARLIEST_INUSE_ADDRESS, &s->inuse_addr_lo);
1031
1032         REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION,
1033                         PRI_VIEWPORT_WIDTH, &s->viewport_width,
1034                         PRI_VIEWPORT_HEIGHT, &s->viewport_height);
1035
1036         REG_GET_2(DCSURF_SURFACE_CONFIG,
1037                         ROTATION_ANGLE, &s->rotation_angle,
1038                         H_MIRROR_EN, &s->h_mirror_en);
1039
1040         REG_GET(DCSURF_TILING_CONFIG,
1041                         SW_MODE, &s->sw_mode);
1042
1043         REG_GET(DCSURF_SURFACE_CONTROL,
1044                         PRIMARY_SURFACE_DCC_EN, &s->dcc_en);
1045
1046         REG_GET_3(DCHUBP_CNTL,
1047                         HUBP_BLANK_EN, &s->blank_en,
1048                         HUBP_TTU_DISABLE, &s->ttu_disable,
1049                         HUBP_UNDERFLOW_STATUS, &s->underflow_status);
1050
1051         REG_GET(HUBP_CLK_CNTL,
1052                         HUBP_CLOCK_ENABLE, &s->clock_en);
1053
1054         REG_GET(DCN_GLOBAL_TTU_CNTL,
1055                         MIN_TTU_VBLANK, &s->min_ttu_vblank);
1056
1057         REG_GET_2(DCN_TTU_QOS_WM,
1058                         QoS_LEVEL_LOW_WM, &s->qos_level_low_wm,
1059                         QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm);
1060
1061         REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS,
1062                         PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_lo);
1063
1064         REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH,
1065                         PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_hi);
1066
1067         REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS,
1068                         PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_lo);
1069
1070         REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH,
1071                         PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_hi);
1072 }
1073
1074 void hubp1_read_state(struct hubp *hubp)
1075 {
1076         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1077         struct dcn_hubp_state *s = &hubp1->state;
1078         struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
1079
1080         hubp1_read_state_common(hubp);
1081
1082         REG_GET_8(DCHUBP_REQ_SIZE_CONFIG,
1083                 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size,
1084                 MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size,
1085                 META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size,
1086                 MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size,
1087                 DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size,
1088                 MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size,
1089                 SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height,
1090                 PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear);
1091
1092         REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C,
1093                 CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size,
1094                 MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size,
1095                 META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size,
1096                 MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size,
1097                 DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size,
1098                 MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size,
1099                 SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height,
1100                 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear);
1101
1102 }
1103 enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch)
1104 {
1105         enum cursor_pitch hw_pitch;
1106
1107         switch (pitch) {
1108         case 64:
1109                 hw_pitch = CURSOR_PITCH_64_PIXELS;
1110                 break;
1111         case 128:
1112                 hw_pitch = CURSOR_PITCH_128_PIXELS;
1113                 break;
1114         case 256:
1115                 hw_pitch = CURSOR_PITCH_256_PIXELS;
1116                 break;
1117         default:
1118                 DC_ERR("Invalid cursor pitch of %d. "
1119                                 "Only 64/128/256 is supported on DCN.\n", pitch);
1120                 hw_pitch = CURSOR_PITCH_64_PIXELS;
1121                 break;
1122         }
1123         return hw_pitch;
1124 }
1125
1126 static enum cursor_lines_per_chunk hubp1_get_lines_per_chunk(
1127                 unsigned int cur_width,
1128                 enum dc_cursor_color_format format)
1129 {
1130         enum cursor_lines_per_chunk line_per_chunk;
1131
1132         if (format == CURSOR_MODE_MONO)
1133                 /* impl B. expansion in CUR Buffer reader */
1134                 line_per_chunk = CURSOR_LINE_PER_CHUNK_16;
1135         else if (cur_width <= 32)
1136                 line_per_chunk = CURSOR_LINE_PER_CHUNK_16;
1137         else if (cur_width <= 64)
1138                 line_per_chunk = CURSOR_LINE_PER_CHUNK_8;
1139         else if (cur_width <= 128)
1140                 line_per_chunk = CURSOR_LINE_PER_CHUNK_4;
1141         else
1142                 line_per_chunk = CURSOR_LINE_PER_CHUNK_2;
1143
1144         return line_per_chunk;
1145 }
1146
1147 void hubp1_cursor_set_attributes(
1148                 struct hubp *hubp,
1149                 const struct dc_cursor_attributes *attr)
1150 {
1151         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1152         enum cursor_pitch hw_pitch = hubp1_get_cursor_pitch(attr->pitch);
1153         enum cursor_lines_per_chunk lpc = hubp1_get_lines_per_chunk(
1154                         attr->width, attr->color_format);
1155
1156         hubp->curs_attr = *attr;
1157
1158         REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH,
1159                         CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part);
1160         REG_UPDATE(CURSOR_SURFACE_ADDRESS,
1161                         CURSOR_SURFACE_ADDRESS, attr->address.low_part);
1162
1163         REG_UPDATE_2(CURSOR_SIZE,
1164                         CURSOR_WIDTH, attr->width,
1165                         CURSOR_HEIGHT, attr->height);
1166
1167         REG_UPDATE_3(CURSOR_CONTROL,
1168                         CURSOR_MODE, attr->color_format,
1169                         CURSOR_PITCH, hw_pitch,
1170                         CURSOR_LINES_PER_CHUNK, lpc);
1171
1172         REG_SET_2(CURSOR_SETTINS, 0,
1173                         /* no shift of the cursor HDL schedule */
1174                         CURSOR0_DST_Y_OFFSET, 0,
1175                          /* used to shift the cursor chunk request deadline */
1176                         CURSOR0_CHUNK_HDL_ADJUST, 3);
1177 }
1178
1179 void hubp1_cursor_set_position(
1180                 struct hubp *hubp,
1181                 const struct dc_cursor_position *pos,
1182                 const struct dc_cursor_mi_param *param)
1183 {
1184         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1185         int src_x_offset = pos->x - pos->x_hotspot - param->viewport.x;
1186         int src_y_offset = pos->y - pos->y_hotspot - param->viewport.y;
1187         int x_hotspot = pos->x_hotspot;
1188         int y_hotspot = pos->y_hotspot;
1189         int cursor_height = (int)hubp->curs_attr.height;
1190         int cursor_width = (int)hubp->curs_attr.width;
1191         uint32_t dst_x_offset;
1192         uint32_t cur_en = pos->enable ? 1 : 0;
1193
1194         hubp->curs_pos = *pos;
1195
1196         /*
1197          * Guard aganst cursor_set_position() from being called with invalid
1198          * attributes
1199          *
1200          * TODO: Look at combining cursor_set_position() and
1201          * cursor_set_attributes() into cursor_update()
1202          */
1203         if (hubp->curs_attr.address.quad_part == 0)
1204                 return;
1205
1206         // Rotated cursor width/height and hotspots tweaks for offset calculation
1207         if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) {
1208                 swap(cursor_height, cursor_width);
1209                 if (param->rotation == ROTATION_ANGLE_90) {
1210                         src_x_offset = pos->x - pos->y_hotspot - param->viewport.x;
1211                         src_y_offset = pos->y - pos->x_hotspot - param->viewport.y;
1212                 }
1213         } else if (param->rotation == ROTATION_ANGLE_180) {
1214                 src_x_offset = pos->x - param->viewport.x;
1215                 src_y_offset = pos->y - param->viewport.y;
1216         }
1217
1218         if (param->mirror) {
1219                 x_hotspot = param->viewport.width - x_hotspot;
1220                 src_x_offset = param->viewport.x + param->viewport.width - src_x_offset;
1221         }
1222
1223         dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0;
1224         dst_x_offset *= param->ref_clk_khz;
1225         dst_x_offset /= param->pixel_clk_khz;
1226
1227         ASSERT(param->h_scale_ratio.value);
1228
1229         if (param->h_scale_ratio.value)
1230                 dst_x_offset = dc_fixpt_floor(dc_fixpt_div(
1231                                 dc_fixpt_from_int(dst_x_offset),
1232                                 param->h_scale_ratio));
1233
1234         if (src_x_offset >= (int)param->viewport.width)
1235                 cur_en = 0;  /* not visible beyond right edge*/
1236
1237         if (src_x_offset + cursor_width <= 0)
1238                 cur_en = 0;  /* not visible beyond left edge*/
1239
1240         if (src_y_offset >= (int)param->viewport.height)
1241                 cur_en = 0;  /* not visible beyond bottom edge*/
1242
1243         if (src_y_offset + cursor_height <= 0)
1244                 cur_en = 0;  /* not visible beyond top edge*/
1245
1246         if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)
1247                 hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr);
1248
1249         REG_UPDATE(CURSOR_CONTROL,
1250                         CURSOR_ENABLE, cur_en);
1251
1252         REG_SET_2(CURSOR_POSITION, 0,
1253                         CURSOR_X_POSITION, pos->x,
1254                         CURSOR_Y_POSITION, pos->y);
1255
1256         REG_SET_2(CURSOR_HOT_SPOT, 0,
1257                         CURSOR_HOT_SPOT_X, x_hotspot,
1258                         CURSOR_HOT_SPOT_Y, y_hotspot);
1259
1260         REG_SET(CURSOR_DST_OFFSET, 0,
1261                         CURSOR_DST_X_OFFSET, dst_x_offset);
1262         /* TODO Handle surface pixel formats other than 4:4:4 */
1263 }
1264
1265 /**
1266  * hubp1_clk_cntl - Disable or enable clocks for DCHUBP
1267  *
1268  * @hubp: hubp struct reference.
1269  * @enable: Set true for enabling gate clock.
1270  *
1271  * When enabling/disabling DCHUBP clock, we affect dcfclk/dppclk.
1272  */
1273 void hubp1_clk_cntl(struct hubp *hubp, bool enable)
1274 {
1275         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1276         uint32_t clk_enable = enable ? 1 : 0;
1277
1278         REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable);
1279 }
1280
1281 void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst)
1282 {
1283         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1284
1285         REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst);
1286 }
1287
1288 bool hubp1_in_blank(struct hubp *hubp)
1289 {
1290         uint32_t in_blank;
1291         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1292
1293         REG_GET(DCHUBP_CNTL, HUBP_IN_BLANK, &in_blank);
1294         return in_blank ? true : false;
1295 }
1296
1297 void hubp1_soft_reset(struct hubp *hubp, bool reset)
1298 {
1299         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1300
1301         REG_UPDATE(DCHUBP_CNTL, HUBP_DISABLE, reset ? 1 : 0);
1302 }
1303
1304 /**
1305  * hubp1_set_flip_int - Enable surface flip interrupt
1306  *
1307  * @hubp: hubp struct reference.
1308  */
1309 void hubp1_set_flip_int(struct hubp *hubp)
1310 {
1311         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1312
1313         REG_UPDATE(DCSURF_SURFACE_FLIP_INTERRUPT,
1314                 SURFACE_FLIP_INT_MASK, 1);
1315
1316         return;
1317 }
1318
1319 /**
1320  * hubp1_wait_pipe_read_start - wait for hubp ret path starting read.
1321  *
1322  * @hubp: hubp struct reference.
1323  */
1324 static void hubp1_wait_pipe_read_start(struct hubp *hubp)
1325 {
1326         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1327
1328         REG_WAIT(HUBPRET_READ_LINE_STATUS,
1329                 PIPE_READ_VBLANK, 0,
1330                  1, 1000);
1331 }
1332
1333 void hubp1_init(struct hubp *hubp)
1334 {
1335         //do nothing
1336 }
1337 static const struct hubp_funcs dcn10_hubp_funcs = {
1338         .hubp_program_surface_flip_and_addr =
1339                         hubp1_program_surface_flip_and_addr,
1340         .hubp_program_surface_config =
1341                         hubp1_program_surface_config,
1342         .hubp_is_flip_pending = hubp1_is_flip_pending,
1343         .hubp_setup = hubp1_setup,
1344         .hubp_setup_interdependent = hubp1_setup_interdependent,
1345         .hubp_set_vm_system_aperture_settings = hubp1_set_vm_system_aperture_settings,
1346         .hubp_set_vm_context0_settings = hubp1_set_vm_context0_settings,
1347         .set_blank = hubp1_set_blank,
1348         .dcc_control = hubp1_dcc_control,
1349         .mem_program_viewport = min_set_viewport,
1350         .set_hubp_blank_en = hubp1_set_hubp_blank_en,
1351         .set_cursor_attributes  = hubp1_cursor_set_attributes,
1352         .set_cursor_position    = hubp1_cursor_set_position,
1353         .hubp_disconnect = hubp1_disconnect,
1354         .hubp_clk_cntl = hubp1_clk_cntl,
1355         .hubp_vtg_sel = hubp1_vtg_sel,
1356         .hubp_read_state = hubp1_read_state,
1357         .hubp_clear_underflow = hubp1_clear_underflow,
1358         .hubp_disable_control =  hubp1_disable_control,
1359         .hubp_get_underflow_status = hubp1_get_underflow_status,
1360         .hubp_init = hubp1_init,
1361
1362         .dmdata_set_attributes = NULL,
1363         .dmdata_load = NULL,
1364         .hubp_soft_reset = hubp1_soft_reset,
1365         .hubp_in_blank = hubp1_in_blank,
1366         .hubp_set_flip_int = hubp1_set_flip_int,
1367         .hubp_wait_pipe_read_start = hubp1_wait_pipe_read_start,
1368 };
1369
1370 /*****************************************/
1371 /* Constructor, Destructor               */
1372 /*****************************************/
1373
1374 void dcn10_hubp_construct(
1375         struct dcn10_hubp *hubp1,
1376         struct dc_context *ctx,
1377         uint32_t inst,
1378         const struct dcn_mi_registers *hubp_regs,
1379         const struct dcn_mi_shift *hubp_shift,
1380         const struct dcn_mi_mask *hubp_mask)
1381 {
1382         hubp1->base.funcs = &dcn10_hubp_funcs;
1383         hubp1->base.ctx = ctx;
1384         hubp1->hubp_regs = hubp_regs;
1385         hubp1->hubp_shift = hubp_shift;
1386         hubp1->hubp_mask = hubp_mask;
1387         hubp1->base.inst = inst;
1388         hubp1->base.opp_id = OPP_ID_INVALID;
1389         hubp1->base.mpcc_id = 0xf;
1390 }
1391
1392