drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27 #include "dc.h"
  28 #include "dc_bios_types.h"
  29 #include "core_types.h"
  30 #include "core_status.h"
  31 #include "resource.h"
  32 #include "dm_helpers.h"
  33 #include "dce110_timing_generator.h"
  34 #include "dce/dce_hwseq.h"
  35 #include "gpio_service_interface.h"
  36
  37 #include "dce110_compressor.h"
  38
  39 #include "bios/bios_parser_helper.h"
  40 #include "timing_generator.h"
  41 #include "mem_input.h"
  42 #include "opp.h"
  43 #include "ipp.h"
  44 #include "transform.h"
  45 #include "stream_encoder.h"
  46 #include "link_encoder.h"
  47 #include "link_enc_cfg.h"
  48 #include "link_hwss.h"
  49 #include "link.h"
  50 #include "dccg.h"
  51 #include "clock_source.h"
  52 #include "clk_mgr.h"
  53 #include "abm.h"
  54 #include "audio.h"
  55 #include "reg_helper.h"
  56 #include "panel_cntl.h"
  57 #include "dpcd_defs.h"
  58 /* include DCE11 register header files */
  59 #include "dce/dce_11_0_d.h"
  60 #include "dce/dce_11_0_sh_mask.h"
  61 #include "custom_float.h"
  62
  63 #include "atomfirmware.h"
  64
  65 #include "dcn10/dcn10_hw_sequencer.h"
  66
  67 #include "dce110_hw_sequencer.h"
  68
  69 #define GAMMA_HW_POINTS_NUM 256
  70
  71 /*
  72  * All values are in milliseconds;
  73  * For eDP, after power-up/power/down,
  74  * 300/500 msec max. delay from LCDVCC to black video generation
  75  */
  76 #define PANEL_POWER_UP_TIMEOUT 300
  77 #define PANEL_POWER_DOWN_TIMEOUT 500
  78 #define HPD_CHECK_INTERVAL 10
  79 #define OLED_POST_T7_DELAY 100
  80 #define OLED_PRE_T11_DELAY 150
  81
  82 #define CTX \
  83         hws->ctx
  84
  85 #define DC_LOGGER_INIT()
  86
  87 #define REG(reg)\
  88         hws->regs->reg
  89
  90 #undef FN
  91 #define FN(reg_name, field_name) \
  92         hws->shifts->field_name, hws->masks->field_name
  93
  94 struct dce110_hw_seq_reg_offsets {
  95         uint32_t crtc;
  96 };
  97
  98 static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
  99 {
 100         .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
 101 },
 102 {
 103         .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
 104 },
 105 {
 106         .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
 107 },
 108 {
 109         .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),
 110 }
 111 };
 112
 113 #define HW_REG_BLND(reg, id)\
 114         (reg + reg_offsets[id].blnd)
 115
 116 #define HW_REG_CRTC(reg, id)\
 117         (reg + reg_offsets[id].crtc)
 118
 119 #define MAX_WATERMARK 0xFFFF
 120 #define SAFE_NBP_MARK 0x7FFF
 121
 122 /*******************************************************************************
 123  * Private definitions
 124  ******************************************************************************/
 125 /***************************PIPE_CONTROL***********************************/
 126 static void dce110_init_pte(struct dc_context *ctx)
 127 {
 128         uint32_t addr;
 129         uint32_t value = 0;
 130         uint32_t chunk_int = 0;
 131         uint32_t chunk_mul = 0;
 132
 133         addr = mmUNP_DVMM_PTE_CONTROL;
 134         value = dm_read_reg(ctx, addr);
 135
 136         set_reg_field_value(
 137                 value,
 138                 0,
 139                 DVMM_PTE_CONTROL,
 140                 DVMM_USE_SINGLE_PTE);
 141
 142         set_reg_field_value(
 143                 value,
 144                 1,
 145                 DVMM_PTE_CONTROL,
 146                 DVMM_PTE_BUFFER_MODE0);
 147
 148         set_reg_field_value(
 149                 value,
 150                 1,
 151                 DVMM_PTE_CONTROL,
 152                 DVMM_PTE_BUFFER_MODE1);
 153
 154         dm_write_reg(ctx, addr, value);
 155
 156         addr = mmDVMM_PTE_REQ;
 157         value = dm_read_reg(ctx, addr);
 158
 159         chunk_int = get_reg_field_value(
 160                 value,
 161                 DVMM_PTE_REQ,
 162                 HFLIP_PTEREQ_PER_CHUNK_INT);
 163
 164         chunk_mul = get_reg_field_value(
 165                 value,
 166                 DVMM_PTE_REQ,
 167                 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
 168
 169         if (chunk_int != 0x4 || chunk_mul != 0x4) {
 170
 171                 set_reg_field_value(
 172                         value,
 173                         255,
 174                         DVMM_PTE_REQ,
 175                         MAX_PTEREQ_TO_ISSUE);
 176
 177                 set_reg_field_value(
 178                         value,
 179                         4,
 180                         DVMM_PTE_REQ,
 181                         HFLIP_PTEREQ_PER_CHUNK_INT);
 182
 183                 set_reg_field_value(
 184                         value,
 185                         4,
 186                         DVMM_PTE_REQ,
 187                         HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
 188
 189                 dm_write_reg(ctx, addr, value);
 190         }
 191 }
 192 /**************************************************************************/
 193
 194 static void enable_display_pipe_clock_gating(
 195         struct dc_context *ctx,
 196         bool clock_gating)
 197 {
 198         /*TODO*/
 199 }
 200
 201 static bool dce110_enable_display_power_gating(
 202         struct dc *dc,
 203         uint8_t controller_id,
 204         struct dc_bios *dcb,
 205         enum pipe_gating_control power_gating)
 206 {
 207         enum bp_result bp_result = BP_RESULT_OK;
 208         enum bp_pipe_control_action cntl;
 209         struct dc_context *ctx = dc->ctx;
 210         unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
 211
 212         if (power_gating == PIPE_GATING_CONTROL_INIT)
 213                 cntl = ASIC_PIPE_INIT;
 214         else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
 215                 cntl = ASIC_PIPE_ENABLE;
 216         else
 217                 cntl = ASIC_PIPE_DISABLE;
 218
 219         if (controller_id == underlay_idx)
 220                 controller_id = CONTROLLER_ID_UNDERLAY0 - 1;
 221
 222         if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0) {
 223
 224                 bp_result = dcb->funcs->enable_disp_power_gating(
 225                                                 dcb, controller_id + 1, cntl);
 226
 227                 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
 228                  * by default when command table is called
 229                  *
 230                  * Bios parser accepts controller_id = 6 as indicative of
 231                  * underlay pipe in dce110. But we do not support more
 232                  * than 3.
 233                  */
 234                 if (controller_id < CONTROLLER_ID_MAX - 1)
 235                         dm_write_reg(ctx,
 236                                 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),
 237                                 0);
 238         }
 239
 240         if (power_gating != PIPE_GATING_CONTROL_ENABLE)
 241                 dce110_init_pte(ctx);
 242
 243         if (bp_result == BP_RESULT_OK)
 244                 return true;
 245         else
 246                 return false;
 247 }
 248
 249 static void build_prescale_params(struct ipp_prescale_params *prescale_params,
 250                 const struct dc_plane_state *plane_state)
 251 {
 252         prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED;
 253
 254         switch (plane_state->format) {
 255         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
 256                 prescale_params->scale = 0x2082;
 257                 break;
 258         case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
 259         case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
 260                 prescale_params->scale = 0x2020;
 261                 break;
 262         case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
 263         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
 264                 prescale_params->scale = 0x2008;
 265                 break;
 266         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
 267         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
 268         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 269                 prescale_params->scale = 0x2000;
 270                 break;
 271         default:
 272                 ASSERT(false);
 273                 break;
 274         }
 275 }
 276
 277 static bool
 278 dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
 279                                const struct dc_plane_state *plane_state)
 280 {
 281         struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
 282         const struct dc_transfer_func *tf = NULL;
 283         struct ipp_prescale_params prescale_params = { 0 };
 284         bool result = true;
 285
 286         if (ipp == NULL)
 287                 return false;
 288
 289         if (plane_state->in_transfer_func)
 290                 tf = plane_state->in_transfer_func;
 291
 292         build_prescale_params(&prescale_params, plane_state);
 293         ipp->funcs->ipp_program_prescale(ipp, &prescale_params);
 294
 295         if (plane_state->gamma_correction &&
 296                         !plane_state->gamma_correction->is_identity &&
 297                         dce_use_lut(plane_state->format))
 298                 ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction);
 299
 300         if (tf == NULL) {
 301                 /* Default case if no input transfer function specified */
 302                 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
 303         } else if (tf->type == TF_TYPE_PREDEFINED) {
 304                 switch (tf->tf) {
 305                 case TRANSFER_FUNCTION_SRGB:
 306                         ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
 307                         break;
 308                 case TRANSFER_FUNCTION_BT709:
 309                         ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC);
 310                         break;
 311                 case TRANSFER_FUNCTION_LINEAR:
 312                         ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
 313                         break;
 314                 case TRANSFER_FUNCTION_PQ:
 315                 default:
 316                         result = false;
 317                         break;
 318                 }
 319         } else if (tf->type == TF_TYPE_BYPASS) {
 320                 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
 321         } else {
 322                 /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/
 323                 result = false;
 324         }
 325
 326         return result;
 327 }
 328
 329 static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted,
 330                                     struct curve_points *arr_points,
 331                                     uint32_t hw_points_num)
 332 {
 333         struct custom_float_format fmt;
 334
 335         struct pwl_result_data *rgb = rgb_resulted;
 336
 337         uint32_t i = 0;
 338
 339         fmt.exponenta_bits = 6;
 340         fmt.mantissa_bits = 12;
 341         fmt.sign = true;
 342
 343         if (!convert_to_custom_float_format(arr_points[0].x, &fmt,
 344                                             &arr_points[0].custom_float_x)) {
 345                 BREAK_TO_DEBUGGER();
 346                 return false;
 347         }
 348
 349         if (!convert_to_custom_float_format(arr_points[0].offset, &fmt,
 350                                             &arr_points[0].custom_float_offset)) {
 351                 BREAK_TO_DEBUGGER();
 352                 return false;
 353         }
 354
 355         if (!convert_to_custom_float_format(arr_points[0].slope, &fmt,
 356                                             &arr_points[0].custom_float_slope)) {
 357                 BREAK_TO_DEBUGGER();
 358                 return false;
 359         }
 360
 361         fmt.mantissa_bits = 10;
 362         fmt.sign = false;
 363
 364         if (!convert_to_custom_float_format(arr_points[1].x, &fmt,
 365                                             &arr_points[1].custom_float_x)) {
 366                 BREAK_TO_DEBUGGER();
 367                 return false;
 368         }
 369
 370         if (!convert_to_custom_float_format(arr_points[1].y, &fmt,
 371                                             &arr_points[1].custom_float_y)) {
 372                 BREAK_TO_DEBUGGER();
 373                 return false;
 374         }
 375
 376         if (!convert_to_custom_float_format(arr_points[1].slope, &fmt,
 377                                             &arr_points[1].custom_float_slope)) {
 378                 BREAK_TO_DEBUGGER();
 379                 return false;
 380         }
 381
 382         fmt.mantissa_bits = 12;
 383         fmt.sign = true;
 384
 385         while (i != hw_points_num) {
 386                 if (!convert_to_custom_float_format(rgb->red, &fmt,
 387                                                     &rgb->red_reg)) {
 388                         BREAK_TO_DEBUGGER();
 389                         return false;
 390                 }
 391
 392                 if (!convert_to_custom_float_format(rgb->green, &fmt,
 393                                                     &rgb->green_reg)) {
 394                         BREAK_TO_DEBUGGER();
 395                         return false;
 396                 }
 397
 398                 if (!convert_to_custom_float_format(rgb->blue, &fmt,
 399                                                     &rgb->blue_reg)) {
 400                         BREAK_TO_DEBUGGER();
 401                         return false;
 402                 }
 403
 404                 if (!convert_to_custom_float_format(rgb->delta_red, &fmt,
 405                                                     &rgb->delta_red_reg)) {
 406                         BREAK_TO_DEBUGGER();
 407                         return false;
 408                 }
 409
 410                 if (!convert_to_custom_float_format(rgb->delta_green, &fmt,
 411                                                     &rgb->delta_green_reg)) {
 412                         BREAK_TO_DEBUGGER();
 413                         return false;
 414                 }
 415
 416                 if (!convert_to_custom_float_format(rgb->delta_blue, &fmt,
 417                                                     &rgb->delta_blue_reg)) {
 418                         BREAK_TO_DEBUGGER();
 419                         return false;
 420                 }
 421
 422                 ++rgb;
 423                 ++i;
 424         }
 425
 426         return true;
 427 }
 428
 429 #define MAX_LOW_POINT      25
 430 #define NUMBER_REGIONS     16
 431 #define NUMBER_SW_SEGMENTS 16
 432
 433 static bool
 434 dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf,
 435                                       struct pwl_params *regamma_params)
 436 {
 437         struct curve_points *arr_points;
 438         struct pwl_result_data *rgb_resulted;
 439         struct pwl_result_data *rgb;
 440         struct pwl_result_data *rgb_plus_1;
 441         struct fixed31_32 y_r;
 442         struct fixed31_32 y_g;
 443         struct fixed31_32 y_b;
 444         struct fixed31_32 y1_min;
 445         struct fixed31_32 y3_max;
 446
 447         int32_t region_start, region_end;
 448         uint32_t i, j, k, seg_distr[NUMBER_REGIONS], increment, start_index, hw_points;
 449
 450         if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS)
 451                 return false;
 452
 453         arr_points = regamma_params->arr_points;
 454         rgb_resulted = regamma_params->rgb_resulted;
 455         hw_points = 0;
 456
 457         memset(regamma_params, 0, sizeof(struct pwl_params));
 458
 459         if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
 460                 /* 16 segments
 461                  * segments are from 2^-11 to 2^5
 462                  */
 463                 region_start = -11;
 464                 region_end = region_start + NUMBER_REGIONS;
 465
 466                 for (i = 0; i < NUMBER_REGIONS; i++)
 467                         seg_distr[i] = 4;
 468
 469         } else {
 470                 /* 10 segments
 471                  * segment is from 2^-10 to 2^1
 472                  * We include an extra segment for range [2^0, 2^1). This is to
 473                  * ensure that colors with normalized values of 1 don't miss the
 474                  * LUT.
 475                  */
 476                 region_start = -10;
 477                 region_end = 1;
 478
 479                 seg_distr[0] = 4;
 480                 seg_distr[1] = 4;
 481                 seg_distr[2] = 4;
 482                 seg_distr[3] = 4;
 483                 seg_distr[4] = 4;
 484                 seg_distr[5] = 4;
 485                 seg_distr[6] = 4;
 486                 seg_distr[7] = 4;
 487                 seg_distr[8] = 4;
 488                 seg_distr[9] = 4;
 489                 seg_distr[10] = 0;
 490                 seg_distr[11] = -1;
 491                 seg_distr[12] = -1;
 492                 seg_distr[13] = -1;
 493                 seg_distr[14] = -1;
 494                 seg_distr[15] = -1;
 495         }
 496
 497         for (k = 0; k < 16; k++) {
 498                 if (seg_distr[k] != -1)
 499                         hw_points += (1 << seg_distr[k]);
 500         }
 501
 502         j = 0;
 503         for (k = 0; k < (region_end - region_start); k++) {
 504                 increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]);
 505                 start_index = (region_start + k + MAX_LOW_POINT) *
 506                                 NUMBER_SW_SEGMENTS;
 507                 for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS;
 508                                 i += increment) {
 509                         if (j == hw_points - 1)
 510                                 break;
 511                         rgb_resulted[j].red = output_tf->tf_pts.red[i];
 512                         rgb_resulted[j].green = output_tf->tf_pts.green[i];
 513                         rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
 514                         j++;
 515                 }
 516         }
 517
 518         /* last point */
 519         start_index = (region_end + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS;
 520         rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index];
 521         rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index];
 522         rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
 523
 524         arr_points[0].x = dc_fixpt_pow(dc_fixpt_from_int(2),
 525                                              dc_fixpt_from_int(region_start));
 526         arr_points[1].x = dc_fixpt_pow(dc_fixpt_from_int(2),
 527                                              dc_fixpt_from_int(region_end));
 528
 529         y_r = rgb_resulted[0].red;
 530         y_g = rgb_resulted[0].green;
 531         y_b = rgb_resulted[0].blue;
 532
 533         y1_min = dc_fixpt_min(y_r, dc_fixpt_min(y_g, y_b));
 534
 535         arr_points[0].y = y1_min;
 536         arr_points[0].slope = dc_fixpt_div(arr_points[0].y,
 537                                                  arr_points[0].x);
 538
 539         y_r = rgb_resulted[hw_points - 1].red;
 540         y_g = rgb_resulted[hw_points - 1].green;
 541         y_b = rgb_resulted[hw_points - 1].blue;
 542
 543         /* see comment above, m_arrPoints[1].y should be the Y value for the
 544          * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
 545          */
 546         y3_max = dc_fixpt_max(y_r, dc_fixpt_max(y_g, y_b));
 547
 548         arr_points[1].y = y3_max;
 549
 550         arr_points[1].slope = dc_fixpt_zero;
 551
 552         if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
 553                 /* for PQ, we want to have a straight line from last HW X point,
 554                  * and the slope to be such that we hit 1.0 at 10000 nits.
 555                  */
 556                 const struct fixed31_32 end_value = dc_fixpt_from_int(125);
 557
 558                 arr_points[1].slope = dc_fixpt_div(
 559                                 dc_fixpt_sub(dc_fixpt_one, arr_points[1].y),
 560                                 dc_fixpt_sub(end_value, arr_points[1].x));
 561         }
 562
 563         regamma_params->hw_points_num = hw_points;
 564
 565         k = 0;
 566         for (i = 1; i < 16; i++) {
 567                 if (seg_distr[k] != -1) {
 568                         regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
 569                         regamma_params->arr_curve_points[i].offset =
 570                                         regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
 571                 }
 572                 k++;
 573         }
 574
 575         if (seg_distr[k] != -1)
 576                 regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
 577
 578         rgb = rgb_resulted;
 579         rgb_plus_1 = rgb_resulted + 1;
 580
 581         i = 1;
 582
 583         while (i != hw_points + 1) {
 584                 if (dc_fixpt_lt(rgb_plus_1->red, rgb->red))
 585                         rgb_plus_1->red = rgb->red;
 586                 if (dc_fixpt_lt(rgb_plus_1->green, rgb->green))
 587                         rgb_plus_1->green = rgb->green;
 588                 if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue))
 589                         rgb_plus_1->blue = rgb->blue;
 590
 591                 rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red);
 592                 rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green);
 593                 rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue);
 594
 595                 ++rgb_plus_1;
 596                 ++rgb;
 597                 ++i;
 598         }
 599
 600         convert_to_custom_float(rgb_resulted, arr_points, hw_points);
 601
 602         return true;
 603 }
 604
 605 static bool
 606 dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
 607                                 const struct dc_stream_state *stream)
 608 {
 609         struct transform *xfm = pipe_ctx->plane_res.xfm;
 610
 611         xfm->funcs->opp_power_on_regamma_lut(xfm, true);
 612         xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
 613
 614         if (stream->out_transfer_func &&
 615             stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
 616             stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) {
 617                 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB);
 618         } else if (dce110_translate_regamma_to_hw_format(stream->out_transfer_func,
 619                                                          &xfm->regamma_params)) {
 620                 xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params);
 621                 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER);
 622         } else {
 623                 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS);
 624         }
 625
 626         xfm->funcs->opp_power_on_regamma_lut(xfm, false);
 627
 628         return true;
 629 }
 630
 631 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)
 632 {
 633         bool is_hdmi_tmds;
 634         bool is_dp;
 635
 636         ASSERT(pipe_ctx->stream);
 637
 638         if (pipe_ctx->stream_res.stream_enc == NULL)
 639                 return;  /* this is not root pipe */
 640
 641         is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);
 642         is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);
 643
 644         if (!is_hdmi_tmds && !is_dp)
 645                 return;
 646
 647         if (is_hdmi_tmds)
 648                 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
 649                         pipe_ctx->stream_res.stream_enc,
 650                         &pipe_ctx->stream_res.encoder_info_frame);
 651         else {
 652                 if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num)
 653                         pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num(
 654                                 pipe_ctx->stream_res.stream_enc,
 655                                 &pipe_ctx->stream_res.encoder_info_frame);
 656
 657                 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
 658                         pipe_ctx->stream_res.stream_enc,
 659                         &pipe_ctx->stream_res.encoder_info_frame);
 660         }
 661 }
 662
 663 void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
 664 {
 665         enum dc_lane_count lane_count =
 666                 pipe_ctx->stream->link->cur_link_settings.lane_count;
 667         struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
 668         struct dc_link *link = pipe_ctx->stream->link;
 669         const struct dc *dc = link->dc;
 670         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
 671         uint32_t active_total_with_borders;
 672         uint32_t early_control = 0;
 673         struct timing_generator *tg = pipe_ctx->stream_res.tg;
 674
 675         link_hwss->setup_stream_encoder(pipe_ctx);
 676
 677         dc->hwss.update_info_frame(pipe_ctx);
 678
 679         /* enable early control to avoid corruption on DP monitor*/
 680         active_total_with_borders =
 681                         timing->h_addressable
 682                                 + timing->h_border_left
 683                                 + timing->h_border_right;
 684
 685         if (lane_count != 0)
 686                 early_control = active_total_with_borders % lane_count;
 687
 688         if (early_control == 0)
 689                 early_control = lane_count;
 690
 691         tg->funcs->set_early_control(tg, early_control);
 692 }
 693
 694 static enum bp_result link_transmitter_control(
 695                 struct dc_bios *bios,
 696         struct bp_transmitter_control *cntl)
 697 {
 698         enum bp_result result;
 699
 700         result = bios->funcs->transmitter_control(bios, cntl);
 701
 702         return result;
 703 }
 704
 705 /*
 706  * @brief
 707  * eDP only.
 708  */
 709 void dce110_edp_wait_for_hpd_ready(
 710                 struct dc_link *link,
 711                 bool power_up)
 712 {
 713         struct dc_context *ctx = link->ctx;
 714         struct graphics_object_id connector = link->link_enc->connector;
 715         struct gpio *hpd;
 716         bool edp_hpd_high = false;
 717         uint32_t time_elapsed = 0;
 718         uint32_t timeout = power_up ?
 719                 PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT;
 720
 721         if (dal_graphics_object_id_get_connector_id(connector)
 722                         != CONNECTOR_ID_EDP) {
 723                 BREAK_TO_DEBUGGER();
 724                 return;
 725         }
 726
 727         if (!power_up)
 728                 /*
 729                  * From KV, we will not HPD low after turning off VCC -
 730                  * instead, we will check the SW timer in power_up().
 731                  */
 732                 return;
 733
 734         /*
 735          * When we power on/off the eDP panel,
 736          * we need to wait until SENSE bit is high/low.
 737          */
 738
 739         /* obtain HPD */
 740         /* TODO what to do with this? */
 741         hpd = ctx->dc->link_srv->get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service);
 742
 743         if (!hpd) {
 744                 BREAK_TO_DEBUGGER();
 745                 return;
 746         }
 747
 748         if (link != NULL) {
 749                 if (link->panel_config.pps.extra_t3_ms > 0) {
 750                         int extra_t3_in_ms = link->panel_config.pps.extra_t3_ms;
 751
 752                         msleep(extra_t3_in_ms);
 753                 }
 754         }
 755
 756         dal_gpio_open(hpd, GPIO_MODE_INTERRUPT);
 757
 758         /* wait until timeout or panel detected */
 759
 760         do {
 761                 uint32_t detected = 0;
 762
 763                 dal_gpio_get_value(hpd, &detected);
 764
 765                 if (!(detected ^ power_up)) {
 766                         edp_hpd_high = true;
 767                         break;
 768                 }
 769
 770                 msleep(HPD_CHECK_INTERVAL);
 771
 772                 time_elapsed += HPD_CHECK_INTERVAL;
 773         } while (time_elapsed < timeout);
 774
 775         dal_gpio_close(hpd);
 776
 777         dal_gpio_destroy_irq(&hpd);
 778
 779         /* ensure that the panel is detected */
 780         if (!edp_hpd_high)
 781                 DC_LOG_DC("%s: wait timed out!\n", __func__);
 782 }
 783
 784 void dce110_edp_power_control(
 785                 struct dc_link *link,
 786                 bool power_up)
 787 {
 788         struct dc_context *ctx = link->ctx;
 789         struct bp_transmitter_control cntl = { 0 };
 790         enum bp_result bp_result;
 791         uint8_t pwrseq_instance;
 792
 793
 794         if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
 795                         != CONNECTOR_ID_EDP) {
 796                 BREAK_TO_DEBUGGER();
 797                 return;
 798         }
 799
 800         if (!link->panel_cntl)
 801                 return;
 802         if (power_up !=
 803                 link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl)) {
 804
 805                 unsigned long long current_ts = dm_get_timestamp(ctx);
 806                 unsigned long long time_since_edp_poweroff_ms =
 807                                 div64_u64(dm_get_elapse_time_in_ns(
 808                                                 ctx,
 809                                                 current_ts,
 810                                                 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link)), 1000000);
 811                 unsigned long long time_since_edp_poweron_ms =
 812                                 div64_u64(dm_get_elapse_time_in_ns(
 813                                                 ctx,
 814                                                 current_ts,
 815                                                 ctx->dc->link_srv->dp_trace_get_edp_poweron_timestamp(link)), 1000000);
 816                 DC_LOG_HW_RESUME_S3(
 817                                 "%s: transition: power_up=%d current_ts=%llu edp_poweroff=%llu edp_poweron=%llu time_since_edp_poweroff_ms=%llu time_since_edp_poweron_ms=%llu",
 818                                 __func__,
 819                                 power_up,
 820                                 current_ts,
 821                                 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link),
 822                                 ctx->dc->link_srv->dp_trace_get_edp_poweron_timestamp(link),
 823                                 time_since_edp_poweroff_ms,
 824                                 time_since_edp_poweron_ms);
 825
 826                 /* Send VBIOS command to prompt eDP panel power */
 827                 if (power_up) {
 828                         /* edp requires a min of 500ms from LCDVDD off to on */
 829                         unsigned long long remaining_min_edp_poweroff_time_ms = 500;
 830
 831                         /* add time defined by a patch, if any (usually patch extra_t12_ms is 0) */
 832                         if (link->local_sink != NULL)
 833                                 remaining_min_edp_poweroff_time_ms +=
 834                                         link->panel_config.pps.extra_t12_ms;
 835
 836                         /* Adjust remaining_min_edp_poweroff_time_ms if this is not the first time. */
 837                         if (ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link) != 0) {
 838                                 if (time_since_edp_poweroff_ms < remaining_min_edp_poweroff_time_ms)
 839                                         remaining_min_edp_poweroff_time_ms =
 840                                                 remaining_min_edp_poweroff_time_ms - time_since_edp_poweroff_ms;
 841                                 else
 842                                         remaining_min_edp_poweroff_time_ms = 0;
 843                         }
 844
 845                         if (remaining_min_edp_poweroff_time_ms) {
 846                                 DC_LOG_HW_RESUME_S3(
 847                                                 "%s: remaining_min_edp_poweroff_time_ms=%llu: begin wait.\n",
 848                                                 __func__, remaining_min_edp_poweroff_time_ms);
 849                                 msleep(remaining_min_edp_poweroff_time_ms);
 850                                 DC_LOG_HW_RESUME_S3(
 851                                                 "%s: remaining_min_edp_poweroff_time_ms=%llu: end wait.\n",
 852                                                 __func__, remaining_min_edp_poweroff_time_ms);
 853                                 dm_output_to_console("%s: wait %lld ms to power on eDP.\n",
 854                                                 __func__, remaining_min_edp_poweroff_time_ms);
 855                         } else {
 856                                 DC_LOG_HW_RESUME_S3(
 857                                                 "%s: remaining_min_edp_poweroff_time_ms=%llu: no wait required.\n",
 858                                                 __func__, remaining_min_edp_poweroff_time_ms);
 859                         }
 860                 }
 861
 862                 DC_LOG_HW_RESUME_S3(
 863                                 "%s: BEGIN: Panel Power action: %s\n",
 864                                 __func__, (power_up ? "On":"Off"));
 865
 866                 cntl.action = power_up ?
 867                         TRANSMITTER_CONTROL_POWER_ON :
 868                         TRANSMITTER_CONTROL_POWER_OFF;
 869                 cntl.transmitter = link->link_enc->transmitter;
 870                 cntl.connector_obj_id = link->link_enc->connector;
 871                 cntl.coherent = false;
 872                 cntl.lanes_number = LANE_COUNT_FOUR;
 873                 cntl.hpd_sel = link->link_enc->hpd_source;
 874                 pwrseq_instance = link->panel_cntl->pwrseq_inst;
 875
 876                 if (ctx->dc->ctx->dmub_srv &&
 877                                 ctx->dc->debug.dmub_command_table) {
 878
 879                         if (cntl.action == TRANSMITTER_CONTROL_POWER_ON) {
 880                                 bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
 881                                                 LVTMA_CONTROL_POWER_ON,
 882                                                 pwrseq_instance, link->link_powered_externally);
 883                         } else {
 884                                 bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
 885                                                 LVTMA_CONTROL_POWER_OFF,
 886                                                 pwrseq_instance, link->link_powered_externally);
 887                         }
 888                 }
 889
 890                 bp_result = link_transmitter_control(ctx->dc_bios, &cntl);
 891
 892                 DC_LOG_HW_RESUME_S3(
 893                                 "%s: END: Panel Power action: %s bp_result=%u\n",
 894                                 __func__, (power_up ? "On":"Off"),
 895                                 bp_result);
 896
 897                 ctx->dc->link_srv->dp_trace_set_edp_power_timestamp(link, power_up);
 898
 899                 DC_LOG_HW_RESUME_S3(
 900                                 "%s: updated values: edp_poweroff=%llu edp_poweron=%llu\n",
 901                                 __func__,
 902                                 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link),
 903                                 ctx->dc->link_srv->dp_trace_get_edp_poweron_timestamp(link));
 904
 905                 if (bp_result != BP_RESULT_OK)
 906                         DC_LOG_ERROR(
 907                                         "%s: Panel Power bp_result: %d\n",
 908                                         __func__, bp_result);
 909         } else {
 910                 DC_LOG_HW_RESUME_S3(
 911                                 "%s: Skipping Panel Power action: %s\n",
 912                                 __func__, (power_up ? "On":"Off"));
 913         }
 914 }
 915
 916 void dce110_edp_wait_for_T12(
 917                 struct dc_link *link)
 918 {
 919         struct dc_context *ctx = link->ctx;
 920
 921         if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
 922                         != CONNECTOR_ID_EDP) {
 923                 BREAK_TO_DEBUGGER();
 924                 return;
 925         }
 926
 927         if (!link->panel_cntl)
 928                 return;
 929
 930         if (!link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl) &&
 931                         ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link) != 0) {
 932                 unsigned int t12_duration = 500; // Default T12 as per spec
 933                 unsigned long long current_ts = dm_get_timestamp(ctx);
 934                 unsigned long long time_since_edp_poweroff_ms =
 935                                 div64_u64(dm_get_elapse_time_in_ns(
 936                                                 ctx,
 937                                                 current_ts,
 938                                                 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link)), 1000000);
 939
 940                 t12_duration += link->panel_config.pps.extra_t12_ms; // Add extra T12
 941
 942                 if (time_since_edp_poweroff_ms < t12_duration)
 943                         msleep(t12_duration - time_since_edp_poweroff_ms);
 944         }
 945 }
 946 /*todo: cloned in stream enc, fix*/
 947 /*
 948  * @brief
 949  * eDP only. Control the backlight of the eDP panel
 950  */
 951 void dce110_edp_backlight_control(
 952                 struct dc_link *link,
 953                 bool enable)
 954 {
 955         struct dc_context *ctx = link->ctx;
 956         struct bp_transmitter_control cntl = { 0 };
 957         uint8_t pwrseq_instance;
 958         unsigned int pre_T11_delay = OLED_PRE_T11_DELAY;
 959         unsigned int post_T7_delay = OLED_POST_T7_DELAY;
 960
 961         if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
 962                 != CONNECTOR_ID_EDP) {
 963                 BREAK_TO_DEBUGGER();
 964                 return;
 965         }
 966
 967         if (link->panel_cntl && !(link->dpcd_sink_ext_caps.bits.oled ||
 968                 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||
 969                 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)) {
 970                 bool is_backlight_on = link->panel_cntl->funcs->is_panel_backlight_on(link->panel_cntl);
 971
 972                 if ((enable && is_backlight_on) || (!enable && !is_backlight_on)) {
 973                         DC_LOG_HW_RESUME_S3(
 974                                 "%s: panel already powered up/off. Do nothing.\n",
 975                                 __func__);
 976                         return;
 977                 }
 978         }
 979
 980         /* Send VBIOS command to control eDP panel backlight */
 981
 982         DC_LOG_HW_RESUME_S3(
 983                         "%s: backlight action: %s\n",
 984                         __func__, (enable ? "On":"Off"));
 985
 986         cntl.action = enable ?
 987                 TRANSMITTER_CONTROL_BACKLIGHT_ON :
 988                 TRANSMITTER_CONTROL_BACKLIGHT_OFF;
 989
 990         /*cntl.engine_id = ctx->engine;*/
 991         cntl.transmitter = link->link_enc->transmitter;
 992         cntl.connector_obj_id = link->link_enc->connector;
 993         /*todo: unhardcode*/
 994         cntl.lanes_number = LANE_COUNT_FOUR;
 995         cntl.hpd_sel = link->link_enc->hpd_source;
 996         cntl.signal = SIGNAL_TYPE_EDP;
 997
 998         /* For eDP, the following delays might need to be considered
 999          * after link training completed:
1000          * idle period - min. accounts for required BS-Idle pattern,
1001          * max. allows for source frame synchronization);
1002          * 50 msec max. delay from valid video data from source
1003          * to video on dislpay or backlight enable.
1004          *
1005          * Disable the delay for now.
1006          * Enable it in the future if necessary.
1007          */
1008         /* dc_service_sleep_in_milliseconds(50); */
1009                 /*edp 1.2*/
1010         pwrseq_instance = link->panel_cntl->pwrseq_inst;
1011
1012         if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) {
1013                 if (!link->dc->config.edp_no_power_sequencing)
1014                 /*
1015                  * Sometimes, DP receiver chip power-controlled externally by an
1016                  * Embedded Controller could be treated and used as eDP,
1017                  * if it drives mobile display. In this case,
1018                  * we shouldn't be doing power-sequencing, hence we can skip
1019                  * waiting for T7-ready.
1020                  */
1021                         ctx->dc->link_srv->edp_receiver_ready_T7(link);
1022                 else
1023                         DC_LOG_DC("edp_receiver_ready_T7 skipped\n");
1024         }
1025
1026         /* Setting link_powered_externally will bypass delays in the backlight
1027          * as they are not required if the link is being powered by a different
1028          * source.
1029          */
1030         if (ctx->dc->ctx->dmub_srv &&
1031                         ctx->dc->debug.dmub_command_table) {
1032                 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON)
1033                         ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
1034                                         LVTMA_CONTROL_LCD_BLON,
1035                                         pwrseq_instance, link->link_powered_externally);
1036                 else
1037                         ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
1038                                         LVTMA_CONTROL_LCD_BLOFF,
1039                                         pwrseq_instance, link->link_powered_externally);
1040         }
1041
1042         link_transmitter_control(ctx->dc_bios, &cntl);
1043
1044         if (enable && link->dpcd_sink_ext_caps.bits.oled) {
1045                 post_T7_delay += link->panel_config.pps.extra_post_t7_ms;
1046                 msleep(post_T7_delay);
1047         }
1048
1049         if (link->dpcd_sink_ext_caps.bits.oled ||
1050                 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||
1051                 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)
1052                 ctx->dc->link_srv->edp_backlight_enable_aux(link, enable);
1053
1054         /*edp 1.2*/
1055         if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF) {
1056                 if (!link->dc->config.edp_no_power_sequencing)
1057                 /*
1058                  * Sometimes, DP receiver chip power-controlled externally by an
1059                  * Embedded Controller could be treated and used as eDP,
1060                  * if it drives mobile display. In this case,
1061                  * we shouldn't be doing power-sequencing, hence we can skip
1062                  * waiting for T9-ready.
1063                  */
1064                         ctx->dc->link_srv->edp_add_delay_for_T9(link);
1065                 else
1066                         DC_LOG_DC("edp_receiver_ready_T9 skipped\n");
1067         }
1068
1069         if (!enable && link->dpcd_sink_ext_caps.bits.oled) {
1070                 pre_T11_delay += link->panel_config.pps.extra_pre_t11_ms;
1071                 msleep(pre_T11_delay);
1072         }
1073 }
1074
1075 void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
1076 {
1077         /* notify audio driver for audio modes of monitor */
1078         struct dc *dc;
1079         struct clk_mgr *clk_mgr;
1080         unsigned int i, num_audio = 1;
1081         const struct link_hwss *link_hwss;
1082
1083         if (!pipe_ctx->stream)
1084                 return;
1085
1086         dc = pipe_ctx->stream->ctx->dc;
1087         clk_mgr = dc->clk_mgr;
1088         link_hwss = get_link_hwss(pipe_ctx->stream->link, &pipe_ctx->link_res);
1089
1090         if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == true)
1091                 return;
1092
1093         if (pipe_ctx->stream_res.audio) {
1094                 for (i = 0; i < MAX_PIPES; i++) {
1095                         /*current_state not updated yet*/
1096                         if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL)
1097                                 num_audio++;
1098                 }
1099
1100                 pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio);
1101
1102                 if (num_audio >= 1 && clk_mgr->funcs->enable_pme_wa)
1103                         /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
1104                         clk_mgr->funcs->enable_pme_wa(clk_mgr);
1105
1106                 link_hwss->enable_audio_packet(pipe_ctx);
1107
1108                 if (pipe_ctx->stream_res.audio)
1109                         pipe_ctx->stream_res.audio->enabled = true;
1110         }
1111 }
1112
1113 void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx)
1114 {
1115         struct dc *dc;
1116         struct clk_mgr *clk_mgr;
1117         const struct link_hwss *link_hwss;
1118
1119         if (!pipe_ctx || !pipe_ctx->stream)
1120                 return;
1121
1122         dc = pipe_ctx->stream->ctx->dc;
1123         clk_mgr = dc->clk_mgr;
1124         link_hwss = get_link_hwss(pipe_ctx->stream->link, &pipe_ctx->link_res);
1125
1126         if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == false)
1127                 return;
1128
1129         link_hwss->disable_audio_packet(pipe_ctx);
1130
1131         if (pipe_ctx->stream_res.audio) {
1132                 pipe_ctx->stream_res.audio->enabled = false;
1133
1134                 if (clk_mgr->funcs->enable_pme_wa)
1135                         /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
1136                         clk_mgr->funcs->enable_pme_wa(clk_mgr);
1137
1138                 /* TODO: notify audio driver for if audio modes list changed
1139                  * add audio mode list change flag */
1140                 /* dal_audio_disable_azalia_audio_jack_presence(stream->audio,
1141                  * stream->stream_engine_id);
1142                  */
1143         }
1144 }
1145
1146 void dce110_disable_stream(struct pipe_ctx *pipe_ctx)
1147 {
1148         struct dc_stream_state *stream = pipe_ctx->stream;
1149         struct dc_link *link = stream->link;
1150         struct dc *dc = pipe_ctx->stream->ctx->dc;
1151         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
1152         struct dccg *dccg = dc->res_pool->dccg;
1153         struct timing_generator *tg = pipe_ctx->stream_res.tg;
1154         struct dtbclk_dto_params dto_params = {0};
1155         int dp_hpo_inst;
1156         struct link_encoder *link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link);
1157         struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
1158
1159         if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) {
1160                 pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(
1161                         pipe_ctx->stream_res.stream_enc);
1162                 pipe_ctx->stream_res.stream_enc->funcs->hdmi_reset_stream_attribute(
1163                         pipe_ctx->stream_res.stream_enc);
1164         }
1165
1166         if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
1167                 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->stop_dp_info_packets(
1168                                         pipe_ctx->stream_res.hpo_dp_stream_enc);
1169         } else if (dc_is_dp_signal(pipe_ctx->stream->signal))
1170                 pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets(
1171                         pipe_ctx->stream_res.stream_enc);
1172
1173         dc->hwss.disable_audio_stream(pipe_ctx);
1174
1175         link_hwss->reset_stream_encoder(pipe_ctx);
1176
1177         if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
1178                 dto_params.otg_inst = tg->inst;
1179                 dto_params.timing = &pipe_ctx->stream->timing;
1180                 dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;
1181                 if (dccg) {
1182                         dccg->funcs->set_dtbclk_dto(dccg, &dto_params);
1183                         dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst);
1184                         dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, dp_hpo_inst);
1185                 }
1186         } else if (dccg && dccg->funcs->disable_symclk_se) {
1187                 dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst,
1188                                 link_enc->transmitter - TRANSMITTER_UNIPHY_A);
1189         }
1190
1191         if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
1192                 /* TODO: This looks like a bug to me as we are disabling HPO IO when
1193                  * we are just disabling a single HPO stream. Shouldn't we disable HPO
1194                  * HW control only when HPOs for all streams are disabled?
1195                  */
1196                 if (pipe_ctx->stream->ctx->dc->hwseq->funcs.setup_hpo_hw_control)
1197                         pipe_ctx->stream->ctx->dc->hwseq->funcs.setup_hpo_hw_control(
1198                                         pipe_ctx->stream->ctx->dc->hwseq, false);
1199         }
1200 }
1201
1202 void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
1203                 struct dc_link_settings *link_settings)
1204 {
1205         struct encoder_unblank_param params = { { 0 } };
1206         struct dc_stream_state *stream = pipe_ctx->stream;
1207         struct dc_link *link = stream->link;
1208         struct dce_hwseq *hws = link->dc->hwseq;
1209
1210         /* only 3 items below are used by unblank */
1211         params.timing = pipe_ctx->stream->timing;
1212         params.link_settings.link_rate = link_settings->link_rate;
1213
1214         if (dc_is_dp_signal(pipe_ctx->stream->signal))
1215                 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, &params);
1216
1217         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1218                 hws->funcs.edp_backlight_control(link, true);
1219         }
1220 }
1221
1222 void dce110_blank_stream(struct pipe_ctx *pipe_ctx)
1223 {
1224         struct dc_stream_state *stream = pipe_ctx->stream;
1225         struct dc_link *link = stream->link;
1226         struct dce_hwseq *hws = link->dc->hwseq;
1227
1228         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1229                 if (!link->skip_implict_edp_power_control)
1230                         hws->funcs.edp_backlight_control(link, false);
1231                 link->dc->hwss.set_abm_immediate_disable(pipe_ctx);
1232         }
1233
1234         if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
1235                 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */
1236                 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_blank(
1237                                 pipe_ctx->stream_res.hpo_dp_stream_enc);
1238         } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
1239                 pipe_ctx->stream_res.stream_enc->funcs->dp_blank(link, pipe_ctx->stream_res.stream_enc);
1240
1241                 if (!dc_is_embedded_signal(pipe_ctx->stream->signal)) {
1242                         /*
1243                          * After output is idle pattern some sinks need time to recognize the stream
1244                          * has changed or they enter protection state and hang.
1245                          */
1246                         msleep(60);
1247                 } else if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {
1248                         if (!link->dc->config.edp_no_power_sequencing) {
1249                                 /*
1250                                  * Sometimes, DP receiver chip power-controlled externally by an
1251                                  * Embedded Controller could be treated and used as eDP,
1252                                  * if it drives mobile display. In this case,
1253                                  * we shouldn't be doing power-sequencing, hence we can skip
1254                                  * waiting for T9-ready.
1255                                  */
1256                                 link->dc->link_srv->edp_receiver_ready_T9(link);
1257                         }
1258                 }
1259         }
1260
1261 }
1262
1263
1264 void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
1265 {
1266         if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL)
1267                 pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable);
1268 }
1269
1270 static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
1271 {
1272         switch (crtc_id) {
1273         case CONTROLLER_ID_D0:
1274                 return DTO_SOURCE_ID0;
1275         case CONTROLLER_ID_D1:
1276                 return DTO_SOURCE_ID1;
1277         case CONTROLLER_ID_D2:
1278                 return DTO_SOURCE_ID2;
1279         case CONTROLLER_ID_D3:
1280                 return DTO_SOURCE_ID3;
1281         case CONTROLLER_ID_D4:
1282                 return DTO_SOURCE_ID4;
1283         case CONTROLLER_ID_D5:
1284                 return DTO_SOURCE_ID5;
1285         default:
1286                 return DTO_SOURCE_UNKNOWN;
1287         }
1288 }
1289
1290 static void build_audio_output(
1291         struct dc_state *state,
1292         const struct pipe_ctx *pipe_ctx,
1293         struct audio_output *audio_output)
1294 {
1295         const struct dc_stream_state *stream = pipe_ctx->stream;
1296         audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id;
1297
1298         audio_output->signal = pipe_ctx->stream->signal;
1299
1300         /* audio_crtc_info  */
1301
1302         audio_output->crtc_info.h_total =
1303                 stream->timing.h_total;
1304
1305         /*
1306          * Audio packets are sent during actual CRTC blank physical signal, we
1307          * need to specify actual active signal portion
1308          */
1309         audio_output->crtc_info.h_active =
1310                         stream->timing.h_addressable
1311                         + stream->timing.h_border_left
1312                         + stream->timing.h_border_right;
1313
1314         audio_output->crtc_info.v_active =
1315                         stream->timing.v_addressable
1316                         + stream->timing.v_border_top
1317                         + stream->timing.v_border_bottom;
1318
1319         audio_output->crtc_info.pixel_repetition = 1;
1320
1321         audio_output->crtc_info.interlaced =
1322                         stream->timing.flags.INTERLACE;
1323
1324         audio_output->crtc_info.refresh_rate =
1325                 (stream->timing.pix_clk_100hz*100)/
1326                 (stream->timing.h_total*stream->timing.v_total);
1327
1328         audio_output->crtc_info.color_depth =
1329                 stream->timing.display_color_depth;
1330
1331         audio_output->crtc_info.requested_pixel_clock_100Hz =
1332                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;
1333
1334         audio_output->crtc_info.calculated_pixel_clock_100Hz =
1335                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;
1336
1337 /*for HDMI, audio ACR is with deep color ratio factor*/
1338         if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) &&
1339                 audio_output->crtc_info.requested_pixel_clock_100Hz ==
1340                                 (stream->timing.pix_clk_100hz)) {
1341                 if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
1342                         audio_output->crtc_info.requested_pixel_clock_100Hz =
1343                                         audio_output->crtc_info.requested_pixel_clock_100Hz/2;
1344                         audio_output->crtc_info.calculated_pixel_clock_100Hz =
1345                                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/2;
1346
1347                 }
1348         }
1349
1350         if (state->clk_mgr &&
1351                 (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
1352                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)) {
1353                 audio_output->pll_info.dp_dto_source_clock_in_khz =
1354                                 state->clk_mgr->funcs->get_dp_ref_clk_frequency(
1355                                                 state->clk_mgr);
1356         }
1357
1358         audio_output->pll_info.feed_back_divider =
1359                         pipe_ctx->pll_settings.feedback_divider;
1360
1361         audio_output->pll_info.dto_source =
1362                 translate_to_dto_source(
1363                         pipe_ctx->stream_res.tg->inst + 1);
1364
1365         /* TODO hard code to enable for now. Need get from stream */
1366         audio_output->pll_info.ss_enabled = true;
1367
1368         audio_output->pll_info.ss_percentage =
1369                         pipe_ctx->pll_settings.ss_percentage;
1370 }
1371
1372 static void program_scaler(const struct dc *dc,
1373                 const struct pipe_ctx *pipe_ctx)
1374 {
1375         struct tg_color color = {0};
1376
1377         /* TOFPGA */
1378         if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL)
1379                 return;
1380
1381         if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
1382                 get_surface_visual_confirm_color(pipe_ctx, &color);
1383         else
1384                 color_space_to_black_color(dc,
1385                                 pipe_ctx->stream->output_color_space,
1386                                 &color);
1387
1388         pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
1389                 pipe_ctx->plane_res.xfm,
1390                 pipe_ctx->plane_res.scl_data.lb_params.depth,
1391                 &pipe_ctx->stream->bit_depth_params);
1392
1393         if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) {
1394                 /*
1395                  * The way 420 is packed, 2 channels carry Y component, 1 channel
1396                  * alternate between Cb and Cr, so both channels need the pixel
1397                  * value for Y
1398                  */
1399                 if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1400                         color.color_r_cr = color.color_g_y;
1401
1402                 pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color(
1403                                 pipe_ctx->stream_res.tg,
1404                                 &color);
1405         }
1406
1407         pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm,
1408                 &pipe_ctx->plane_res.scl_data);
1409 }
1410
1411 static enum dc_status dce110_enable_stream_timing(
1412                 struct pipe_ctx *pipe_ctx,
1413                 struct dc_state *context,
1414                 struct dc *dc)
1415 {
1416         struct dc_stream_state *stream = pipe_ctx->stream;
1417         struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.
1418                         pipe_ctx[pipe_ctx->pipe_idx];
1419         struct tg_color black_color = {0};
1420
1421         if (!pipe_ctx_old->stream) {
1422
1423                 /* program blank color */
1424                 color_space_to_black_color(dc,
1425                                 stream->output_color_space, &black_color);
1426                 pipe_ctx->stream_res.tg->funcs->set_blank_color(
1427                                 pipe_ctx->stream_res.tg,
1428                                 &black_color);
1429
1430                 /*
1431                  * Must blank CRTC after disabling power gating and before any
1432                  * programming, otherwise CRTC will be hung in bad state
1433                  */
1434                 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
1435
1436                 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
1437                                 pipe_ctx->clock_source,
1438                                 &pipe_ctx->stream_res.pix_clk_params,
1439                                 dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings),
1440                                 &pipe_ctx->pll_settings)) {
1441                         BREAK_TO_DEBUGGER();
1442                         return DC_ERROR_UNEXPECTED;
1443                 }
1444
1445                 if (dc_is_hdmi_tmds_signal(stream->signal)) {
1446                         stream->link->phy_state.symclk_ref_cnts.otg = 1;
1447                         if (stream->link->phy_state.symclk_state == SYMCLK_OFF_TX_OFF)
1448                                 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_OFF;
1449                         else
1450                                 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_ON;
1451                 }
1452
1453                 pipe_ctx->stream_res.tg->funcs->program_timing(
1454                                 pipe_ctx->stream_res.tg,
1455                                 &stream->timing,
1456                                 0,
1457                                 0,
1458                                 0,
1459                                 0,
1460                                 pipe_ctx->stream->signal,
1461                                 true);
1462         }
1463
1464         if (!pipe_ctx_old->stream) {
1465                 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(
1466                                 pipe_ctx->stream_res.tg)) {
1467                         BREAK_TO_DEBUGGER();
1468                         return DC_ERROR_UNEXPECTED;
1469                 }
1470         }
1471
1472         return DC_OK;
1473 }
1474
1475 static enum dc_status apply_single_controller_ctx_to_hw(
1476                 struct pipe_ctx *pipe_ctx,
1477                 struct dc_state *context,
1478                 struct dc *dc)
1479 {
1480         struct dc_stream_state *stream = pipe_ctx->stream;
1481         struct dc_link *link = stream->link;
1482         struct drr_params params = {0};
1483         unsigned int event_triggers = 0;
1484         struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
1485         struct dce_hwseq *hws = dc->hwseq;
1486         const struct link_hwss *link_hwss = get_link_hwss(
1487                         link, &pipe_ctx->link_res);
1488
1489
1490         if (hws->funcs.disable_stream_gating) {
1491                 hws->funcs.disable_stream_gating(dc, pipe_ctx);
1492         }
1493
1494         if (pipe_ctx->stream_res.audio != NULL) {
1495                 struct audio_output audio_output;
1496
1497                 build_audio_output(context, pipe_ctx, &audio_output);
1498
1499                 link_hwss->setup_audio_output(pipe_ctx, &audio_output,
1500                                 pipe_ctx->stream_res.audio->inst);
1501
1502                 pipe_ctx->stream_res.audio->funcs->az_configure(
1503                                 pipe_ctx->stream_res.audio,
1504                                 pipe_ctx->stream->signal,
1505                                 &audio_output.crtc_info,
1506                                 &pipe_ctx->stream->audio_info);
1507         }
1508
1509         /* make sure no pipes syncd to the pipe being enabled */
1510         if (!pipe_ctx->stream->apply_seamless_boot_optimization && dc->config.use_pipe_ctx_sync_logic)
1511                 check_syncd_pipes_for_disabled_master_pipe(dc, context, pipe_ctx->pipe_idx);
1512
1513         pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1514                 pipe_ctx->stream_res.opp,
1515                 &stream->bit_depth_params,
1516                 &stream->clamping);
1517
1518         pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1519                         pipe_ctx->stream_res.opp,
1520                         COLOR_SPACE_YCBCR601,
1521                         stream->timing.display_color_depth,
1522                         stream->signal);
1523
1524         while (odm_pipe) {
1525                 odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion(
1526                                 odm_pipe->stream_res.opp,
1527                                 COLOR_SPACE_YCBCR601,
1528                                 stream->timing.display_color_depth,
1529                                 stream->signal);
1530
1531                 odm_pipe->stream_res.opp->funcs->opp_program_fmt(
1532                                 odm_pipe->stream_res.opp,
1533                                 &stream->bit_depth_params,
1534                                 &stream->clamping);
1535                 odm_pipe = odm_pipe->next_odm_pipe;
1536         }
1537
1538         /* DCN3.1 FPGA Workaround
1539          * Need to enable HPO DP Stream Encoder before setting OTG master enable.
1540          * To do so, move calling function enable_stream_timing to only be done AFTER calling
1541          * function core_link_enable_stream
1542          */
1543         if (!(hws->wa.dp_hpo_and_otg_sequence && dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)))
1544                 /*  */
1545                 /* Do not touch stream timing on seamless boot optimization. */
1546                 if (!pipe_ctx->stream->apply_seamless_boot_optimization)
1547                         hws->funcs.enable_stream_timing(pipe_ctx, context, dc);
1548
1549         if (hws->funcs.setup_vupdate_interrupt)
1550                 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
1551
1552         params.vertical_total_min = stream->adjust.v_total_min;
1553         params.vertical_total_max = stream->adjust.v_total_max;
1554         if (pipe_ctx->stream_res.tg->funcs->set_drr)
1555                 pipe_ctx->stream_res.tg->funcs->set_drr(
1556                         pipe_ctx->stream_res.tg, &params);
1557
1558         // DRR should set trigger event to monitor surface update event
1559         if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0)
1560                 event_triggers = 0x80;
1561         /* Event triggers and num frames initialized for DRR, but can be
1562          * later updated for PSR use. Note DRR trigger events are generated
1563          * regardless of whether num frames met.
1564          */
1565         if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
1566                 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
1567                                 pipe_ctx->stream_res.tg, event_triggers, 2);
1568
1569         if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
1570                 pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg(
1571                         pipe_ctx->stream_res.stream_enc,
1572                         pipe_ctx->stream_res.tg->inst);
1573
1574         if (dc_is_dp_signal(pipe_ctx->stream->signal))
1575                 dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_OTG);
1576
1577         if (!stream->dpms_off)
1578                 dc->link_srv->set_dpms_on(context, pipe_ctx);
1579
1580         /* DCN3.1 FPGA Workaround
1581          * Need to enable HPO DP Stream Encoder before setting OTG master enable.
1582          * To do so, move calling function enable_stream_timing to only be done AFTER calling
1583          * function core_link_enable_stream
1584          */
1585         if (hws->wa.dp_hpo_and_otg_sequence && dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
1586                 if (!pipe_ctx->stream->apply_seamless_boot_optimization)
1587                         hws->funcs.enable_stream_timing(pipe_ctx, context, dc);
1588         }
1589
1590         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL;
1591
1592         /* Phantom and main stream share the same link (because the stream
1593          * is constructed with the same sink). Make sure not to override
1594          * and link programming on the main.
1595          */
1596         if (pipe_ctx->stream->mall_stream_config.type != SUBVP_PHANTOM) {
1597                 pipe_ctx->stream->link->psr_settings.psr_feature_enabled = false;
1598                 pipe_ctx->stream->link->replay_settings.replay_feature_enabled = false;
1599         }
1600         return DC_OK;
1601 }
1602
1603 /******************************************************************************/
1604
1605 static void power_down_encoders(struct dc *dc)
1606 {
1607         int i;
1608
1609         for (i = 0; i < dc->link_count; i++) {
1610                 enum signal_type signal = dc->links[i]->connector_signal;
1611
1612                 dc->link_srv->blank_dp_stream(dc->links[i], false);
1613
1614                 if (signal != SIGNAL_TYPE_EDP)
1615                         signal = SIGNAL_TYPE_NONE;
1616
1617                 if (dc->links[i]->ep_type == DISPLAY_ENDPOINT_PHY)
1618                         dc->links[i]->link_enc->funcs->disable_output(
1619                                         dc->links[i]->link_enc, signal);
1620
1621                 dc->links[i]->link_status.link_active = false;
1622                 memset(&dc->links[i]->cur_link_settings, 0,
1623                                 sizeof(dc->links[i]->cur_link_settings));
1624         }
1625 }
1626
1627 static void power_down_controllers(struct dc *dc)
1628 {
1629         int i;
1630
1631         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
1632                 dc->res_pool->timing_generators[i]->funcs->disable_crtc(
1633                                 dc->res_pool->timing_generators[i]);
1634         }
1635 }
1636
1637 static void power_down_clock_sources(struct dc *dc)
1638 {
1639         int i;
1640
1641         if (dc->res_pool->dp_clock_source->funcs->cs_power_down(
1642                 dc->res_pool->dp_clock_source) == false)
1643                 dm_error("Failed to power down pll! (dp clk src)\n");
1644
1645         for (i = 0; i < dc->res_pool->clk_src_count; i++) {
1646                 if (dc->res_pool->clock_sources[i]->funcs->cs_power_down(
1647                                 dc->res_pool->clock_sources[i]) == false)
1648                         dm_error("Failed to power down pll! (clk src index=%d)\n", i);
1649         }
1650 }
1651
1652 static void power_down_all_hw_blocks(struct dc *dc)
1653 {
1654         power_down_encoders(dc);
1655
1656         power_down_controllers(dc);
1657
1658         power_down_clock_sources(dc);
1659
1660         if (dc->fbc_compressor)
1661                 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
1662 }
1663
1664 static void disable_vga_and_power_gate_all_controllers(
1665                 struct dc *dc)
1666 {
1667         int i;
1668         struct timing_generator *tg;
1669         struct dc_context *ctx = dc->ctx;
1670
1671         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
1672                 tg = dc->res_pool->timing_generators[i];
1673
1674                 if (tg->funcs->disable_vga)
1675                         tg->funcs->disable_vga(tg);
1676         }
1677         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1678                 /* Enable CLOCK gating for each pipe BEFORE controller
1679                  * powergating. */
1680                 enable_display_pipe_clock_gating(ctx,
1681                                 true);
1682
1683                 dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i;
1684                 dc->hwss.disable_plane(dc,
1685                         &dc->current_state->res_ctx.pipe_ctx[i]);
1686         }
1687 }
1688
1689
1690 static void get_edp_streams(struct dc_state *context,
1691                 struct dc_stream_state **edp_streams,
1692                 int *edp_stream_num)
1693 {
1694         int i;
1695
1696         *edp_stream_num = 0;
1697         for (i = 0; i < context->stream_count; i++) {
1698                 if (context->streams[i]->signal == SIGNAL_TYPE_EDP) {
1699                         edp_streams[*edp_stream_num] = context->streams[i];
1700                         if (++(*edp_stream_num) == MAX_NUM_EDP)
1701                                 return;
1702                 }
1703         }
1704 }
1705
1706 static void get_edp_links_with_sink(
1707                 struct dc *dc,
1708                 struct dc_link **edp_links_with_sink,
1709                 int *edp_with_sink_num)
1710 {
1711         int i;
1712
1713         /* check if there is an eDP panel not in use */
1714         *edp_with_sink_num = 0;
1715         for (i = 0; i < dc->link_count; i++) {
1716                 if (dc->links[i]->local_sink &&
1717                         dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1718                         edp_links_with_sink[*edp_with_sink_num] = dc->links[i];
1719                         if (++(*edp_with_sink_num) == MAX_NUM_EDP)
1720                                 return;
1721                 }
1722         }
1723 }
1724
1725 /*
1726  * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need:
1727  *  1. Power down all DC HW blocks
1728  *  2. Disable VGA engine on all controllers
1729  *  3. Enable power gating for controller
1730  *  4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS)
1731  */
1732 void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
1733 {
1734         struct dc_link *edp_links_with_sink[MAX_NUM_EDP];
1735         struct dc_link *edp_links[MAX_NUM_EDP];
1736         struct dc_stream_state *edp_streams[MAX_NUM_EDP];
1737         struct dc_link *edp_link_with_sink = NULL;
1738         struct dc_link *edp_link = NULL;
1739         struct dce_hwseq *hws = dc->hwseq;
1740         int edp_with_sink_num;
1741         int edp_num;
1742         int edp_stream_num;
1743         int i;
1744         bool can_apply_edp_fast_boot = false;
1745         bool can_apply_seamless_boot = false;
1746         bool keep_edp_vdd_on = false;
1747         DC_LOGGER_INIT();
1748
1749
1750         get_edp_links_with_sink(dc, edp_links_with_sink, &edp_with_sink_num);
1751         dc_get_edp_links(dc, edp_links, &edp_num);
1752
1753         if (hws->funcs.init_pipes)
1754                 hws->funcs.init_pipes(dc, context);
1755
1756         get_edp_streams(context, edp_streams, &edp_stream_num);
1757
1758         // Check fastboot support, disable on DCE8 because of blank screens
1759         if (edp_num && edp_stream_num && dc->ctx->dce_version != DCE_VERSION_8_0 &&
1760                     dc->ctx->dce_version != DCE_VERSION_8_1 &&
1761                     dc->ctx->dce_version != DCE_VERSION_8_3) {
1762                 for (i = 0; i < edp_num; i++) {
1763                         edp_link = edp_links[i];
1764                         if (edp_link != edp_streams[0]->link)
1765                                 continue;
1766                         // enable fastboot if backend is enabled on eDP
1767                         if (edp_link->link_enc->funcs->is_dig_enabled &&
1768                             edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&
1769                             edp_link->link_status.link_active) {
1770                                 struct dc_stream_state *edp_stream = edp_streams[0];
1771
1772                                 can_apply_edp_fast_boot = dc_validate_boot_timing(dc,
1773                                         edp_stream->sink, &edp_stream->timing);
1774                                 edp_stream->apply_edp_fast_boot_optimization = can_apply_edp_fast_boot;
1775                                 if (can_apply_edp_fast_boot)
1776                                         DC_LOG_EVENT_LINK_TRAINING("eDP fast boot disabled to optimize link rate\n");
1777
1778                                 break;
1779                         }
1780                 }
1781                 // We are trying to enable eDP, don't power down VDD
1782                 if (can_apply_edp_fast_boot)
1783                         keep_edp_vdd_on = true;
1784         }
1785
1786         // Check seamless boot support
1787         for (i = 0; i < context->stream_count; i++) {
1788                 if (context->streams[i]->apply_seamless_boot_optimization) {
1789                         can_apply_seamless_boot = true;
1790                         break;
1791                 }
1792         }
1793
1794         /* eDP should not have stream in resume from S4 and so even with VBios post
1795          * it should get turned off
1796          */
1797         if (edp_with_sink_num)
1798                 edp_link_with_sink = edp_links_with_sink[0];
1799
1800         if (!can_apply_edp_fast_boot && !can_apply_seamless_boot) {
1801                 if (edp_link_with_sink && !keep_edp_vdd_on) {
1802                         /*turn off backlight before DP_blank and encoder powered down*/
1803                         hws->funcs.edp_backlight_control(edp_link_with_sink, false);
1804                 }
1805                 /*resume from S3, no vbios posting, no need to power down again*/
1806                 clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
1807
1808                 power_down_all_hw_blocks(dc);
1809                 disable_vga_and_power_gate_all_controllers(dc);
1810                 if (edp_link_with_sink && !keep_edp_vdd_on)
1811                         dc->hwss.edp_power_control(edp_link_with_sink, false);
1812                 clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
1813         }
1814         bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 1);
1815 }
1816
1817 static uint32_t compute_pstate_blackout_duration(
1818         struct bw_fixed blackout_duration,
1819         const struct dc_stream_state *stream)
1820 {
1821         uint32_t total_dest_line_time_ns;
1822         uint32_t pstate_blackout_duration_ns;
1823
1824         pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24;
1825
1826         total_dest_line_time_ns = 1000000UL *
1827                 (stream->timing.h_total * 10) /
1828                 stream->timing.pix_clk_100hz +
1829                 pstate_blackout_duration_ns;
1830
1831         return total_dest_line_time_ns;
1832 }
1833
1834 static void dce110_set_displaymarks(
1835         const struct dc *dc,
1836         struct dc_state *context)
1837 {
1838         uint8_t i, num_pipes;
1839         unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
1840
1841         for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) {
1842                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1843                 uint32_t total_dest_line_time_ns;
1844
1845                 if (pipe_ctx->stream == NULL)
1846                         continue;
1847
1848                 total_dest_line_time_ns = compute_pstate_blackout_duration(
1849                         dc->bw_vbios->blackout_duration, pipe_ctx->stream);
1850                 pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks(
1851                         pipe_ctx->plane_res.mi,
1852                         context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes],
1853                         context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes],
1854                         context->bw_ctx.bw.dce.stutter_entry_wm_ns[num_pipes],
1855                         context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes],
1856                         total_dest_line_time_ns);
1857                 if (i == underlay_idx) {
1858                         num_pipes++;
1859                         pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1860                                 pipe_ctx->plane_res.mi,
1861                                 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes],
1862                                 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes],
1863                                 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes],
1864                                 total_dest_line_time_ns);
1865                 }
1866                 num_pipes++;
1867         }
1868 }
1869
1870 void dce110_set_safe_displaymarks(
1871                 struct resource_context *res_ctx,
1872                 const struct resource_pool *pool)
1873 {
1874         int i;
1875         int underlay_idx = pool->underlay_pipe_index;
1876         struct dce_watermarks max_marks = {
1877                 MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK };
1878         struct dce_watermarks nbp_marks = {
1879                 SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK };
1880         struct dce_watermarks min_marks = { 0, 0, 0, 0};
1881
1882         for (i = 0; i < MAX_PIPES; i++) {
1883                 if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL)
1884                         continue;
1885
1886                 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks(
1887                                 res_ctx->pipe_ctx[i].plane_res.mi,
1888                                 nbp_marks,
1889                                 max_marks,
1890                                 min_marks,
1891                                 max_marks,
1892                                 MAX_WATERMARK);
1893
1894                 if (i == underlay_idx)
1895                         res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1896                                 res_ctx->pipe_ctx[i].plane_res.mi,
1897                                 nbp_marks,
1898                                 max_marks,
1899                                 max_marks,
1900                                 MAX_WATERMARK);
1901
1902         }
1903 }
1904
1905 /*******************************************************************************
1906  * Public functions
1907  ******************************************************************************/
1908
1909 static void set_drr(struct pipe_ctx **pipe_ctx,
1910                 int num_pipes, struct dc_crtc_timing_adjust adjust)
1911 {
1912         int i = 0;
1913         struct drr_params params = {0};
1914         // DRR should set trigger event to monitor surface update event
1915         unsigned int event_triggers = 0x80;
1916         // Note DRR trigger events are generated regardless of whether num frames met.
1917         unsigned int num_frames = 2;
1918
1919         params.vertical_total_max = adjust.v_total_max;
1920         params.vertical_total_min = adjust.v_total_min;
1921
1922         /* TODO: If multiple pipes are to be supported, you need
1923          * some GSL stuff. Static screen triggers may be programmed differently
1924          * as well.
1925          */
1926         for (i = 0; i < num_pipes; i++) {
1927                 pipe_ctx[i]->stream_res.tg->funcs->set_drr(
1928                         pipe_ctx[i]->stream_res.tg, &params);
1929
1930                 if (adjust.v_total_max != 0 && adjust.v_total_min != 0)
1931                         pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(
1932                                         pipe_ctx[i]->stream_res.tg,
1933                                         event_triggers, num_frames);
1934         }
1935 }
1936
1937 static void get_position(struct pipe_ctx **pipe_ctx,
1938                 int num_pipes,
1939                 struct crtc_position *position)
1940 {
1941         int i = 0;
1942
1943         /* TODO: handle pipes > 1
1944          */
1945         for (i = 0; i < num_pipes; i++)
1946                 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
1947 }
1948
1949 static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
1950                 int num_pipes, const struct dc_static_screen_params *params)
1951 {
1952         unsigned int i;
1953         unsigned int triggers = 0;
1954
1955         if (params->triggers.overlay_update)
1956                 triggers |= 0x100;
1957         if (params->triggers.surface_update)
1958                 triggers |= 0x80;
1959         if (params->triggers.cursor_update)
1960                 triggers |= 0x2;
1961         if (params->triggers.force_trigger)
1962                 triggers |= 0x1;
1963
1964         if (num_pipes) {
1965                 struct dc *dc = pipe_ctx[0]->stream->ctx->dc;
1966
1967                 if (dc->fbc_compressor)
1968                         triggers |= 0x84;
1969         }
1970
1971         for (i = 0; i < num_pipes; i++)
1972                 pipe_ctx[i]->stream_res.tg->funcs->
1973                         set_static_screen_control(pipe_ctx[i]->stream_res.tg,
1974                                         triggers, params->num_frames);
1975 }
1976
1977 /*
1978  *  Check if FBC can be enabled
1979  */
1980 static bool should_enable_fbc(struct dc *dc,
1981                 struct dc_state *context,
1982                 uint32_t *pipe_idx)
1983 {
1984         uint32_t i;
1985         struct pipe_ctx *pipe_ctx = NULL;
1986         struct resource_context *res_ctx = &context->res_ctx;
1987         unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
1988
1989
1990         ASSERT(dc->fbc_compressor);
1991
1992         /* FBC memory should be allocated */
1993         if (!dc->ctx->fbc_gpu_addr)
1994                 return false;
1995
1996         /* Only supports single display */
1997         if (context->stream_count != 1)
1998                 return false;
1999
2000         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2001                 if (res_ctx->pipe_ctx[i].stream) {
2002
2003                         pipe_ctx = &res_ctx->pipe_ctx[i];
2004
2005                         if (!pipe_ctx)
2006                                 continue;
2007
2008                         /* fbc not applicable on underlay pipe */
2009                         if (pipe_ctx->pipe_idx != underlay_idx) {
2010                                 *pipe_idx = i;
2011                                 break;
2012                         }
2013                 }
2014         }
2015
2016         if (i == dc->res_pool->pipe_count)
2017                 return false;
2018
2019         if (!pipe_ctx->stream->link)
2020                 return false;
2021
2022         /* Only supports eDP */
2023         if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP)
2024                 return false;
2025
2026         /* PSR should not be enabled */
2027         if (pipe_ctx->stream->link->psr_settings.psr_feature_enabled)
2028                 return false;
2029
2030         /* Replay should not be enabled */
2031         if (pipe_ctx->stream->link->replay_settings.replay_feature_enabled)
2032                 return false;
2033
2034         /* Nothing to compress */
2035         if (!pipe_ctx->plane_state)
2036                 return false;
2037
2038         /* Only for non-linear tiling */
2039         if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
2040                 return false;
2041
2042         return true;
2043 }
2044
2045 /*
2046  *  Enable FBC
2047  */
2048 static void enable_fbc(
2049                 struct dc *dc,
2050                 struct dc_state *context)
2051 {
2052         uint32_t pipe_idx = 0;
2053
2054         if (should_enable_fbc(dc, context, &pipe_idx)) {
2055                 /* Program GRPH COMPRESSED ADDRESS and PITCH */
2056                 struct compr_addr_and_pitch_params params = {0, 0, 0};
2057                 struct compressor *compr = dc->fbc_compressor;
2058                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
2059
2060                 params.source_view_width = pipe_ctx->stream->timing.h_addressable;
2061                 params.source_view_height = pipe_ctx->stream->timing.v_addressable;
2062                 params.inst = pipe_ctx->stream_res.tg->inst;
2063                 compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr;
2064
2065                 compr->funcs->surface_address_and_pitch(compr, &params);
2066                 compr->funcs->set_fbc_invalidation_triggers(compr, 1);
2067
2068                 compr->funcs->enable_fbc(compr, &params);
2069         }
2070 }
2071
2072 static void dce110_reset_hw_ctx_wrap(
2073                 struct dc *dc,
2074                 struct dc_state *context)
2075 {
2076         int i;
2077
2078         /* Reset old context */
2079         /* look up the targets that have been removed since last commit */
2080         for (i = 0; i < MAX_PIPES; i++) {
2081                 struct pipe_ctx *pipe_ctx_old =
2082                         &dc->current_state->res_ctx.pipe_ctx[i];
2083                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2084
2085                 /* Note: We need to disable output if clock sources change,
2086                  * since bios does optimization and doesn't apply if changing
2087                  * PHY when not already disabled.
2088                  */
2089
2090                 /* Skip underlay pipe since it will be handled in commit surface*/
2091                 if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe)
2092                         continue;
2093
2094                 if (!pipe_ctx->stream ||
2095                                 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
2096                         struct clock_source *old_clk = pipe_ctx_old->clock_source;
2097
2098                         /* Disable if new stream is null. O/w, if stream is
2099                          * disabled already, no need to disable again.
2100                          */
2101                         if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off) {
2102                                 dc->link_srv->set_dpms_off(pipe_ctx_old);
2103
2104                                 /* free acquired resources*/
2105                                 if (pipe_ctx_old->stream_res.audio) {
2106                                         /*disable az_endpoint*/
2107                                         pipe_ctx_old->stream_res.audio->funcs->
2108                                                         az_disable(pipe_ctx_old->stream_res.audio);
2109
2110                                         /*free audio*/
2111                                         if (dc->caps.dynamic_audio == true) {
2112                                                 /*we have to dynamic arbitrate the audio endpoints*/
2113                                                 /*we free the resource, need reset is_audio_acquired*/
2114                                                 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
2115                                                                 pipe_ctx_old->stream_res.audio, false);
2116                                                 pipe_ctx_old->stream_res.audio = NULL;
2117                                         }
2118                                 }
2119                         }
2120
2121                         pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true);
2122                         if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) {
2123                                 dm_error("DC: failed to blank crtc!\n");
2124                                 BREAK_TO_DEBUGGER();
2125                         }
2126                         pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg);
2127                         if (dc_is_hdmi_tmds_signal(pipe_ctx_old->stream->signal))
2128                                 pipe_ctx_old->stream->link->phy_state.symclk_ref_cnts.otg = 0;
2129                         pipe_ctx_old->plane_res.mi->funcs->free_mem_input(
2130                                         pipe_ctx_old->plane_res.mi, dc->current_state->stream_count);
2131
2132                         if (old_clk && 0 == resource_get_clock_source_reference(&context->res_ctx,
2133                                                                                 dc->res_pool,
2134                                                                                 old_clk))
2135                                 old_clk->funcs->cs_power_down(old_clk);
2136
2137                         dc->hwss.disable_plane(dc, pipe_ctx_old);
2138
2139                         pipe_ctx_old->stream = NULL;
2140                 }
2141         }
2142 }
2143
2144 static void dce110_setup_audio_dto(
2145                 struct dc *dc,
2146                 struct dc_state *context)
2147 {
2148         int i;
2149
2150         /* program audio wall clock. use HDMI as clock source if HDMI
2151          * audio active. Otherwise, use DP as clock source
2152          * first, loop to find any HDMI audio, if not, loop find DP audio
2153          */
2154         /* Setup audio rate clock source */
2155         /* Issue:
2156         * Audio lag happened on DP monitor when unplug a HDMI monitor
2157         *
2158         * Cause:
2159         * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL
2160         * is set to either dto0 or dto1, audio should work fine.
2161         * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1,
2162         * set to dto0 will cause audio lag.
2163         *
2164         * Solution:
2165         * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx,
2166         * find first available pipe with audio, setup audio wall DTO per topology
2167         * instead of per pipe.
2168         */
2169         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2170                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2171
2172                 if (pipe_ctx->stream == NULL)
2173                         continue;
2174
2175                 if (pipe_ctx->top_pipe)
2176                         continue;
2177                 if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
2178                         continue;
2179                 if (pipe_ctx->stream_res.audio != NULL) {
2180                         struct audio_output audio_output;
2181
2182                         build_audio_output(context, pipe_ctx, &audio_output);
2183
2184                         if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) {
2185                                 struct dtbclk_dto_params dto_params = {0};
2186
2187                                 dc->res_pool->dccg->funcs->set_audio_dtbclk_dto(
2188                                         dc->res_pool->dccg, &dto_params);
2189
2190                                 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2191                                                 pipe_ctx->stream_res.audio,
2192                                                 pipe_ctx->stream->signal,
2193                                                 &audio_output.crtc_info,
2194                                                 &audio_output.pll_info);
2195                         } else
2196                                 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2197                                         pipe_ctx->stream_res.audio,
2198                                         pipe_ctx->stream->signal,
2199                                         &audio_output.crtc_info,
2200                                         &audio_output.pll_info);
2201                         break;
2202                 }
2203         }
2204
2205         /* no HDMI audio is found, try DP audio */
2206         if (i == dc->res_pool->pipe_count) {
2207                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2208                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2209
2210                         if (pipe_ctx->stream == NULL)
2211                                 continue;
2212
2213                         if (pipe_ctx->top_pipe)
2214                                 continue;
2215
2216                         if (!dc_is_dp_signal(pipe_ctx->stream->signal))
2217                                 continue;
2218
2219                         if (pipe_ctx->stream_res.audio != NULL) {
2220                                 struct audio_output audio_output;
2221
2222                                 build_audio_output(context, pipe_ctx, &audio_output);
2223
2224                                 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2225                                         pipe_ctx->stream_res.audio,
2226                                         pipe_ctx->stream->signal,
2227                                         &audio_output.crtc_info,
2228                                         &audio_output.pll_info);
2229                                 break;
2230                         }
2231                 }
2232         }
2233 }
2234
2235 enum dc_status dce110_apply_ctx_to_hw(
2236                 struct dc *dc,
2237                 struct dc_state *context)
2238 {
2239         struct dce_hwseq *hws = dc->hwseq;
2240         struct dc_bios *dcb = dc->ctx->dc_bios;
2241         enum dc_status status;
2242         int i;
2243
2244         /* reset syncd pipes from disabled pipes */
2245         if (dc->config.use_pipe_ctx_sync_logic)
2246                 reset_syncd_pipes_from_disabled_pipes(dc, context);
2247
2248         /* Reset old context */
2249         /* look up the targets that have been removed since last commit */
2250         hws->funcs.reset_hw_ctx_wrap(dc, context);
2251
2252         /* Skip applying if no targets */
2253         if (context->stream_count <= 0)
2254                 return DC_OK;
2255
2256         /* Apply new context */
2257         dcb->funcs->set_scratch_critical_state(dcb, true);
2258
2259         /* below is for real asic only */
2260         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2261                 struct pipe_ctx *pipe_ctx_old =
2262                                         &dc->current_state->res_ctx.pipe_ctx[i];
2263                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2264
2265                 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe)
2266                         continue;
2267
2268                 if (pipe_ctx->stream == pipe_ctx_old->stream) {
2269                         if (pipe_ctx_old->clock_source != pipe_ctx->clock_source)
2270                                 dce_crtc_switch_to_clk_src(dc->hwseq,
2271                                                 pipe_ctx->clock_source, i);
2272                         continue;
2273                 }
2274
2275                 hws->funcs.enable_display_power_gating(
2276                                 dc, i, dc->ctx->dc_bios,
2277                                 PIPE_GATING_CONTROL_DISABLE);
2278         }
2279
2280         if (dc->fbc_compressor)
2281                 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
2282
2283         dce110_setup_audio_dto(dc, context);
2284
2285         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2286                 struct pipe_ctx *pipe_ctx_old =
2287                                         &dc->current_state->res_ctx.pipe_ctx[i];
2288                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2289
2290                 if (pipe_ctx->stream == NULL)
2291                         continue;
2292
2293                 if (pipe_ctx->stream == pipe_ctx_old->stream &&
2294                         pipe_ctx->stream->link->link_state_valid) {
2295                         continue;
2296                 }
2297
2298                 if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
2299                         continue;
2300
2301                 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe)
2302                         continue;
2303
2304                 status = apply_single_controller_ctx_to_hw(
2305                                 pipe_ctx,
2306                                 context,
2307                                 dc);
2308
2309                 if (DC_OK != status)
2310                         return status;
2311
2312 #ifdef CONFIG_DRM_AMD_DC_FP
2313                 if (hws->funcs.resync_fifo_dccg_dio)
2314                         hws->funcs.resync_fifo_dccg_dio(hws, dc, context);
2315 #endif
2316         }
2317
2318         if (dc->fbc_compressor)
2319                 enable_fbc(dc, dc->current_state);
2320
2321         dcb->funcs->set_scratch_critical_state(dcb, false);
2322
2323         return DC_OK;
2324 }
2325
2326 /*******************************************************************************
2327  * Front End programming
2328  ******************************************************************************/
2329 static void set_default_colors(struct pipe_ctx *pipe_ctx)
2330 {
2331         struct default_adjustment default_adjust = { 0 };
2332
2333         default_adjust.force_hw_default = false;
2334         default_adjust.in_color_space = pipe_ctx->plane_state->color_space;
2335         default_adjust.out_color_space = pipe_ctx->stream->output_color_space;
2336         default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW;
2337         default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format;
2338
2339         /* display color depth */
2340         default_adjust.color_depth =
2341                 pipe_ctx->stream->timing.display_color_depth;
2342
2343         /* Lb color depth */
2344         default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth;
2345
2346         pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default(
2347                                         pipe_ctx->plane_res.xfm, &default_adjust);
2348 }
2349
2350
2351 /*******************************************************************************
2352  * In order to turn on/off specific surface we will program
2353  * Blender + CRTC
2354  *
2355  * In case that we have two surfaces and they have a different visibility
2356  * we can't turn off the CRTC since it will turn off the entire display
2357  *
2358  * |----------------------------------------------- |
2359  * |bottom pipe|curr pipe  |              |         |
2360  * |Surface    |Surface    | Blender      |  CRCT   |
2361  * |visibility |visibility | Configuration|         |
2362  * |------------------------------------------------|
2363  * |   off     |    off    | CURRENT_PIPE | blank   |
2364  * |   off     |    on     | CURRENT_PIPE | unblank |
2365  * |   on      |    off    | OTHER_PIPE   | unblank |
2366  * |   on      |    on     | BLENDING     | unblank |
2367  * -------------------------------------------------|
2368  *
2369  ******************************************************************************/
2370 static void program_surface_visibility(const struct dc *dc,
2371                 struct pipe_ctx *pipe_ctx)
2372 {
2373         enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE;
2374         bool blank_target = false;
2375
2376         if (pipe_ctx->bottom_pipe) {
2377
2378                 /* For now we are supporting only two pipes */
2379                 ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL);
2380
2381                 if (pipe_ctx->bottom_pipe->plane_state->visible) {
2382                         if (pipe_ctx->plane_state->visible)
2383                                 blender_mode = BLND_MODE_BLENDING;
2384                         else
2385                                 blender_mode = BLND_MODE_OTHER_PIPE;
2386
2387                 } else if (!pipe_ctx->plane_state->visible)
2388                         blank_target = true;
2389
2390         } else if (!pipe_ctx->plane_state->visible)
2391                 blank_target = true;
2392
2393         dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode);
2394         pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target);
2395
2396 }
2397
2398 static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
2399 {
2400         int i = 0;
2401         struct xfm_grph_csc_adjustment adjust;
2402         memset(&adjust, 0, sizeof(adjust));
2403         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2404
2405
2406         if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2407                 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2408
2409                 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
2410                         adjust.temperature_matrix[i] =
2411                                 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
2412         }
2413
2414         pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2415 }
2416 static void update_plane_addr(const struct dc *dc,
2417                 struct pipe_ctx *pipe_ctx)
2418 {
2419         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2420
2421         if (plane_state == NULL)
2422                 return;
2423
2424         pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr(
2425                         pipe_ctx->plane_res.mi,
2426                         &plane_state->address,
2427                         plane_state->flip_immediate);
2428
2429         plane_state->status.requested_address = plane_state->address;
2430 }
2431
2432 static void dce110_update_pending_status(struct pipe_ctx *pipe_ctx)
2433 {
2434         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2435
2436         if (plane_state == NULL)
2437                 return;
2438
2439         plane_state->status.is_flip_pending =
2440                         pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending(
2441                                         pipe_ctx->plane_res.mi);
2442
2443         if (plane_state->status.is_flip_pending && !plane_state->visible)
2444                 pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address;
2445
2446         plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address;
2447         if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2448                         pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) {
2449                 plane_state->status.is_right_eye =\
2450                                 !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2451         }
2452 }
2453
2454 void dce110_power_down(struct dc *dc)
2455 {
2456         power_down_all_hw_blocks(dc);
2457         disable_vga_and_power_gate_all_controllers(dc);
2458 }
2459
2460 static bool wait_for_reset_trigger_to_occur(
2461         struct dc_context *dc_ctx,
2462         struct timing_generator *tg)
2463 {
2464         bool rc = false;
2465
2466         /* To avoid endless loop we wait at most
2467          * frames_to_wait_on_triggered_reset frames for the reset to occur. */
2468         const uint32_t frames_to_wait_on_triggered_reset = 10;
2469         uint32_t i;
2470
2471         for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
2472
2473                 if (!tg->funcs->is_counter_moving(tg)) {
2474                         DC_ERROR("TG counter is not moving!\n");
2475                         break;
2476                 }
2477
2478                 if (tg->funcs->did_triggered_reset_occur(tg)) {
2479                         rc = true;
2480                         /* usually occurs at i=1 */
2481                         DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
2482                                         i);
2483                         break;
2484                 }
2485
2486                 /* Wait for one frame. */
2487                 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
2488                 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
2489         }
2490
2491         if (false == rc)
2492                 DC_ERROR("GSL: Timeout on reset trigger!\n");
2493
2494         return rc;
2495 }
2496
2497 /* Enable timing synchronization for a group of Timing Generators. */
2498 static void dce110_enable_timing_synchronization(
2499                 struct dc *dc,
2500                 int group_index,
2501                 int group_size,
2502                 struct pipe_ctx *grouped_pipes[])
2503 {
2504         struct dc_context *dc_ctx = dc->ctx;
2505         struct dcp_gsl_params gsl_params = { 0 };
2506         int i;
2507
2508         DC_SYNC_INFO("GSL: Setting-up...\n");
2509
2510         /* Designate a single TG in the group as a master.
2511          * Since HW doesn't care which one, we always assign
2512          * the 1st one in the group. */
2513         gsl_params.gsl_group = 0;
2514         gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst;
2515
2516         for (i = 0; i < group_size; i++)
2517                 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2518                                         grouped_pipes[i]->stream_res.tg, &gsl_params);
2519
2520         /* Reset slave controllers on master VSync */
2521         DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2522
2523         for (i = 1 /* skip the master */; i < group_size; i++)
2524                 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
2525                                 grouped_pipes[i]->stream_res.tg,
2526                                 gsl_params.gsl_group);
2527
2528         for (i = 1 /* skip the master */; i < group_size; i++) {
2529                 DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2530                 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2531                 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
2532                                 grouped_pipes[i]->stream_res.tg);
2533         }
2534
2535         /* GSL Vblank synchronization is a one time sync mechanism, assumption
2536          * is that the sync'ed displays will not drift out of sync over time*/
2537         DC_SYNC_INFO("GSL: Restoring register states.\n");
2538         for (i = 0; i < group_size; i++)
2539                 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2540
2541         DC_SYNC_INFO("GSL: Set-up complete.\n");
2542 }
2543
2544 static void dce110_enable_per_frame_crtc_position_reset(
2545                 struct dc *dc,
2546                 int group_size,
2547                 struct pipe_ctx *grouped_pipes[])
2548 {
2549         struct dc_context *dc_ctx = dc->ctx;
2550         struct dcp_gsl_params gsl_params = { 0 };
2551         int i;
2552
2553         gsl_params.gsl_group = 0;
2554         gsl_params.gsl_master = 0;
2555
2556         for (i = 0; i < group_size; i++)
2557                 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2558                                         grouped_pipes[i]->stream_res.tg, &gsl_params);
2559
2560         DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2561
2562         for (i = 1; i < group_size; i++)
2563                 grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
2564                                 grouped_pipes[i]->stream_res.tg,
2565                                 gsl_params.gsl_master,
2566                                 &grouped_pipes[i]->stream->triggered_crtc_reset);
2567
2568         DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2569         for (i = 1; i < group_size; i++)
2570                 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2571
2572         for (i = 0; i < group_size; i++)
2573                 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2574
2575 }
2576
2577 static void init_pipes(struct dc *dc, struct dc_state *context)
2578 {
2579         // Do nothing
2580 }
2581
2582 static void init_hw(struct dc *dc)
2583 {
2584         int i;
2585         struct dc_bios *bp;
2586         struct transform *xfm;
2587         struct abm *abm;
2588         struct dmcu *dmcu;
2589         struct dce_hwseq *hws = dc->hwseq;
2590         uint32_t backlight = MAX_BACKLIGHT_LEVEL;
2591
2592         bp = dc->ctx->dc_bios;
2593         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2594                 xfm = dc->res_pool->transforms[i];
2595                 xfm->funcs->transform_reset(xfm);
2596
2597                 hws->funcs.enable_display_power_gating(
2598                                 dc, i, bp,
2599                                 PIPE_GATING_CONTROL_INIT);
2600                 hws->funcs.enable_display_power_gating(
2601                                 dc, i, bp,
2602                                 PIPE_GATING_CONTROL_DISABLE);
2603                 hws->funcs.enable_display_pipe_clock_gating(
2604                         dc->ctx,
2605                         true);
2606         }
2607
2608         dce_clock_gating_power_up(dc->hwseq, false);
2609         /***************************************/
2610
2611         for (i = 0; i < dc->link_count; i++) {
2612                 /****************************************/
2613                 /* Power up AND update implementation according to the
2614                  * required signal (which may be different from the
2615                  * default signal on connector). */
2616                 struct dc_link *link = dc->links[i];
2617
2618                 link->link_enc->funcs->hw_init(link->link_enc);
2619         }
2620
2621         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2622                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2623
2624                 tg->funcs->disable_vga(tg);
2625
2626                 /* Blank controller using driver code instead of
2627                  * command table. */
2628                 tg->funcs->set_blank(tg, true);
2629                 hwss_wait_for_blank_complete(tg);
2630         }
2631
2632         for (i = 0; i < dc->res_pool->audio_count; i++) {
2633                 struct audio *audio = dc->res_pool->audios[i];
2634                 audio->funcs->hw_init(audio);
2635         }
2636
2637         for (i = 0; i < dc->link_count; i++) {
2638                 struct dc_link *link = dc->links[i];
2639
2640                 if (link->panel_cntl)
2641                         backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);
2642         }
2643
2644         abm = dc->res_pool->abm;
2645         if (abm != NULL)
2646                 abm->funcs->abm_init(abm, backlight);
2647
2648         dmcu = dc->res_pool->dmcu;
2649         if (dmcu != NULL && abm != NULL)
2650                 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
2651
2652         if (dc->fbc_compressor)
2653                 dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor);
2654
2655 }
2656
2657
2658 void dce110_prepare_bandwidth(
2659                 struct dc *dc,
2660                 struct dc_state *context)
2661 {
2662         struct clk_mgr *dccg = dc->clk_mgr;
2663
2664         dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
2665         if (dccg)
2666                 dccg->funcs->update_clocks(
2667                                 dccg,
2668                                 context,
2669                                 false);
2670 }
2671
2672 void dce110_optimize_bandwidth(
2673                 struct dc *dc,
2674                 struct dc_state *context)
2675 {
2676         struct clk_mgr *dccg = dc->clk_mgr;
2677
2678         dce110_set_displaymarks(dc, context);
2679
2680         if (dccg)
2681                 dccg->funcs->update_clocks(
2682                                 dccg,
2683                                 context,
2684                                 true);
2685 }
2686
2687 static void dce110_program_front_end_for_pipe(
2688                 struct dc *dc, struct pipe_ctx *pipe_ctx)
2689 {
2690         struct mem_input *mi = pipe_ctx->plane_res.mi;
2691         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2692         struct xfm_grph_csc_adjustment adjust;
2693         struct out_csc_color_matrix tbl_entry;
2694         unsigned int i;
2695         struct dce_hwseq *hws = dc->hwseq;
2696
2697         DC_LOGGER_INIT();
2698         memset(&tbl_entry, 0, sizeof(tbl_entry));
2699
2700         memset(&adjust, 0, sizeof(adjust));
2701         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2702
2703         dce_enable_fe_clock(dc->hwseq, mi->inst, true);
2704
2705         set_default_colors(pipe_ctx);
2706         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
2707                         == true) {
2708                 tbl_entry.color_space =
2709                         pipe_ctx->stream->output_color_space;
2710
2711                 for (i = 0; i < 12; i++)
2712                         tbl_entry.regval[i] =
2713                         pipe_ctx->stream->csc_color_matrix.matrix[i];
2714
2715                 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment
2716                                 (pipe_ctx->plane_res.xfm, &tbl_entry);
2717         }
2718
2719         if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2720                 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2721
2722                 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
2723                         adjust.temperature_matrix[i] =
2724                                 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
2725         }
2726
2727         pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2728
2729         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL;
2730
2731         program_scaler(dc, pipe_ctx);
2732
2733         mi->funcs->mem_input_program_surface_config(
2734                         mi,
2735                         plane_state->format,
2736                         &plane_state->tiling_info,
2737                         &plane_state->plane_size,
2738                         plane_state->rotation,
2739                         NULL,
2740                         false);
2741         if (mi->funcs->set_blank)
2742                 mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
2743
2744         if (dc->config.gpu_vm_support)
2745                 mi->funcs->mem_input_program_pte_vm(
2746                                 pipe_ctx->plane_res.mi,
2747                                 plane_state->format,
2748                                 &plane_state->tiling_info,
2749                                 plane_state->rotation);
2750
2751         /* Moved programming gamma from dc to hwss */
2752         if (pipe_ctx->plane_state->update_flags.bits.full_update ||
2753                         pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
2754                         pipe_ctx->plane_state->update_flags.bits.gamma_change)
2755                 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
2756
2757         if (pipe_ctx->plane_state->update_flags.bits.full_update)
2758                 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
2759
2760         DC_LOG_SURFACE(
2761                         "Pipe:%d %p: addr hi:0x%x, "
2762                         "addr low:0x%x, "
2763                         "src: %d, %d, %d,"
2764                         " %d; dst: %d, %d, %d, %d;"
2765                         "clip: %d, %d, %d, %d\n",
2766                         pipe_ctx->pipe_idx,
2767                         (void *) pipe_ctx->plane_state,
2768                         pipe_ctx->plane_state->address.grph.addr.high_part,
2769                         pipe_ctx->plane_state->address.grph.addr.low_part,
2770                         pipe_ctx->plane_state->src_rect.x,
2771                         pipe_ctx->plane_state->src_rect.y,
2772                         pipe_ctx->plane_state->src_rect.width,
2773                         pipe_ctx->plane_state->src_rect.height,
2774                         pipe_ctx->plane_state->dst_rect.x,
2775                         pipe_ctx->plane_state->dst_rect.y,
2776                         pipe_ctx->plane_state->dst_rect.width,
2777                         pipe_ctx->plane_state->dst_rect.height,
2778                         pipe_ctx->plane_state->clip_rect.x,
2779                         pipe_ctx->plane_state->clip_rect.y,
2780                         pipe_ctx->plane_state->clip_rect.width,
2781                         pipe_ctx->plane_state->clip_rect.height);
2782
2783         DC_LOG_SURFACE(
2784                         "Pipe %d: width, height, x, y\n"
2785                         "viewport:%d, %d, %d, %d\n"
2786                         "recout:  %d, %d, %d, %d\n",
2787                         pipe_ctx->pipe_idx,
2788                         pipe_ctx->plane_res.scl_data.viewport.width,
2789                         pipe_ctx->plane_res.scl_data.viewport.height,
2790                         pipe_ctx->plane_res.scl_data.viewport.x,
2791                         pipe_ctx->plane_res.scl_data.viewport.y,
2792                         pipe_ctx->plane_res.scl_data.recout.width,
2793                         pipe_ctx->plane_res.scl_data.recout.height,
2794                         pipe_ctx->plane_res.scl_data.recout.x,
2795                         pipe_ctx->plane_res.scl_data.recout.y);
2796 }
2797
2798 static void dce110_apply_ctx_for_surface(
2799                 struct dc *dc,
2800                 const struct dc_stream_state *stream,
2801                 int num_planes,
2802                 struct dc_state *context)
2803 {
2804         int i;
2805
2806         if (num_planes == 0)
2807                 return;
2808
2809         if (dc->fbc_compressor)
2810                 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
2811
2812         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2813                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2814
2815                 if (pipe_ctx->stream != stream)
2816                         continue;
2817
2818                 /* Need to allocate mem before program front end for Fiji */
2819                 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(
2820                                 pipe_ctx->plane_res.mi,
2821                                 pipe_ctx->stream->timing.h_total,
2822                                 pipe_ctx->stream->timing.v_total,
2823                                 pipe_ctx->stream->timing.pix_clk_100hz / 10,
2824                                 context->stream_count);
2825
2826                 dce110_program_front_end_for_pipe(dc, pipe_ctx);
2827
2828                 dc->hwss.update_plane_addr(dc, pipe_ctx);
2829
2830                 program_surface_visibility(dc, pipe_ctx);
2831
2832         }
2833
2834         if (dc->fbc_compressor)
2835                 enable_fbc(dc, context);
2836 }
2837
2838 static void dce110_post_unlock_program_front_end(
2839                 struct dc *dc,
2840                 struct dc_state *context)
2841 {
2842 }
2843
2844 static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx)
2845 {
2846         struct dce_hwseq *hws = dc->hwseq;
2847         int fe_idx = pipe_ctx->plane_res.mi ?
2848                 pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx;
2849
2850         /* Do not power down fe when stream is active on dce*/
2851         if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream)
2852                 return;
2853
2854         hws->funcs.enable_display_power_gating(
2855                 dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE);
2856
2857         dc->res_pool->transforms[fe_idx]->funcs->transform_reset(
2858                                 dc->res_pool->transforms[fe_idx]);
2859 }
2860
2861 static void dce110_wait_for_mpcc_disconnect(
2862                 struct dc *dc,
2863                 struct resource_pool *res_pool,
2864                 struct pipe_ctx *pipe_ctx)
2865 {
2866         /* do nothing*/
2867 }
2868
2869 static void program_output_csc(struct dc *dc,
2870                 struct pipe_ctx *pipe_ctx,
2871                 enum dc_color_space colorspace,
2872                 uint16_t *matrix,
2873                 int opp_id)
2874 {
2875         int i;
2876         struct out_csc_color_matrix tbl_entry;
2877
2878         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
2879                 enum dc_color_space color_space = pipe_ctx->stream->output_color_space;
2880
2881                 for (i = 0; i < 12; i++)
2882                         tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i];
2883
2884                 tbl_entry.color_space = color_space;
2885
2886                 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment(
2887                                 pipe_ctx->plane_res.xfm, &tbl_entry);
2888         }
2889 }
2890
2891 static void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx)
2892 {
2893         struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
2894         struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
2895         struct mem_input *mi = pipe_ctx->plane_res.mi;
2896         struct dc_cursor_mi_param param = {
2897                 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,
2898                 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.xtalin_clock_inKhz,
2899                 .viewport = pipe_ctx->plane_res.scl_data.viewport,
2900                 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,
2901                 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,
2902                 .rotation = pipe_ctx->plane_state->rotation,
2903                 .mirror = pipe_ctx->plane_state->horizontal_mirror
2904         };
2905
2906         /**
2907          * If the cursor's source viewport is clipped then we need to
2908          * translate the cursor to appear in the correct position on
2909          * the screen.
2910          *
2911          * This translation isn't affected by scaling so it needs to be
2912          * done *after* we adjust the position for the scale factor.
2913          *
2914          * This is only done by opt-in for now since there are still
2915          * some usecases like tiled display that might enable the
2916          * cursor on both streams while expecting dc to clip it.
2917          */
2918         if (pos_cpy.translate_by_source) {
2919                 pos_cpy.x += pipe_ctx->plane_state->src_rect.x;
2920                 pos_cpy.y += pipe_ctx->plane_state->src_rect.y;
2921         }
2922
2923         if (pipe_ctx->plane_state->address.type
2924                         == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
2925                 pos_cpy.enable = false;
2926
2927         if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
2928                 pos_cpy.enable = false;
2929
2930         if (ipp->funcs->ipp_cursor_set_position)
2931                 ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, &param);
2932         if (mi->funcs->set_cursor_position)
2933                 mi->funcs->set_cursor_position(mi, &pos_cpy, &param);
2934 }
2935
2936 static void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
2937 {
2938         struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
2939
2940         if (pipe_ctx->plane_res.ipp &&
2941             pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes)
2942                 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes(
2943                                 pipe_ctx->plane_res.ipp, attributes);
2944
2945         if (pipe_ctx->plane_res.mi &&
2946             pipe_ctx->plane_res.mi->funcs->set_cursor_attributes)
2947                 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes(
2948                                 pipe_ctx->plane_res.mi, attributes);
2949
2950         if (pipe_ctx->plane_res.xfm &&
2951             pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes)
2952                 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes(
2953                                 pipe_ctx->plane_res.xfm, attributes);
2954 }
2955
2956 bool dce110_set_backlight_level(struct pipe_ctx *pipe_ctx,
2957                 uint32_t backlight_pwm_u16_16,
2958                 uint32_t frame_ramp)
2959 {
2960         struct dc_link *link = pipe_ctx->stream->link;
2961         struct dc  *dc = link->ctx->dc;
2962         struct abm *abm = pipe_ctx->stream_res.abm;
2963         struct panel_cntl *panel_cntl = link->panel_cntl;
2964         struct dmcu *dmcu = dc->res_pool->dmcu;
2965         bool fw_set_brightness = true;
2966         /* DMCU -1 for all controller id values,
2967          * therefore +1 here
2968          */
2969         uint32_t controller_id = pipe_ctx->stream_res.tg->inst + 1;
2970
2971         if (abm == NULL || panel_cntl == NULL || (abm->funcs->set_backlight_level_pwm == NULL))
2972                 return false;
2973
2974         if (dmcu)
2975                 fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
2976
2977         if (!fw_set_brightness && panel_cntl->funcs->driver_set_backlight)
2978                 panel_cntl->funcs->driver_set_backlight(panel_cntl, backlight_pwm_u16_16);
2979         else
2980                 abm->funcs->set_backlight_level_pwm(
2981                                 abm,
2982                                 backlight_pwm_u16_16,
2983                                 frame_ramp,
2984                                 controller_id,
2985                                 link->panel_cntl->inst);
2986
2987         return true;
2988 }
2989
2990 void dce110_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx)
2991 {
2992         struct abm *abm = pipe_ctx->stream_res.abm;
2993         struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;
2994
2995         if (abm)
2996                 abm->funcs->set_abm_immediate_disable(abm,
2997                                 pipe_ctx->stream->link->panel_cntl->inst);
2998
2999         if (panel_cntl)
3000                 panel_cntl->funcs->store_backlight_level(panel_cntl);
3001 }
3002
3003 void dce110_set_pipe(struct pipe_ctx *pipe_ctx)
3004 {
3005         struct abm *abm = pipe_ctx->stream_res.abm;
3006         struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;
3007         uint32_t otg_inst = pipe_ctx->stream_res.tg->inst + 1;
3008
3009         if (abm && panel_cntl)
3010                 abm->funcs->set_pipe(abm, otg_inst, panel_cntl->inst);
3011 }
3012
3013 void dce110_enable_lvds_link_output(struct dc_link *link,
3014                 const struct link_resource *link_res,
3015                 enum clock_source_id clock_source,
3016                 uint32_t pixel_clock)
3017 {
3018         link->link_enc->funcs->enable_lvds_output(
3019                         link->link_enc,
3020                         clock_source,
3021                         pixel_clock);
3022         link->phy_state.symclk_state = SYMCLK_ON_TX_ON;
3023 }
3024
3025 void dce110_enable_tmds_link_output(struct dc_link *link,
3026                 const struct link_resource *link_res,
3027                 enum signal_type signal,
3028                 enum clock_source_id clock_source,
3029                 enum dc_color_depth color_depth,
3030                 uint32_t pixel_clock)
3031 {
3032         link->link_enc->funcs->enable_tmds_output(
3033                         link->link_enc,
3034                         clock_source,
3035                         color_depth,
3036                         signal,
3037                         pixel_clock);
3038         link->phy_state.symclk_state = SYMCLK_ON_TX_ON;
3039 }
3040
3041 void dce110_enable_dp_link_output(
3042                 struct dc_link *link,
3043                 const struct link_resource *link_res,
3044                 enum signal_type signal,
3045                 enum clock_source_id clock_source,
3046                 const struct dc_link_settings *link_settings)
3047 {
3048         struct dc  *dc = link->ctx->dc;
3049         struct dmcu *dmcu = dc->res_pool->dmcu;
3050         struct pipe_ctx *pipes =
3051                         link->dc->current_state->res_ctx.pipe_ctx;
3052         struct clock_source *dp_cs =
3053                         link->dc->res_pool->dp_clock_source;
3054         const struct link_hwss *link_hwss = get_link_hwss(link, link_res);
3055         unsigned int i;
3056
3057         /*
3058          * Add the logic to extract BOTH power up and power down sequences
3059          * from enable/disable link output and only call edp panel control
3060          * in enable_link_dp and disable_link_dp once.
3061          */
3062         if (link->connector_signal == SIGNAL_TYPE_EDP) {
3063                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
3064         }
3065
3066         /* If the current pixel clock source is not DTO(happens after
3067          * switching from HDMI passive dongle to DP on the same connector),
3068          * switch the pixel clock source to DTO.
3069          */
3070
3071         for (i = 0; i < MAX_PIPES; i++) {
3072                 if (pipes[i].stream != NULL &&
3073                                 pipes[i].stream->link == link) {
3074                         if (pipes[i].clock_source != NULL &&
3075                                         pipes[i].clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
3076                                 pipes[i].clock_source = dp_cs;
3077                                 pipes[i].stream_res.pix_clk_params.requested_pix_clk_100hz =
3078                                                 pipes[i].stream->timing.pix_clk_100hz;
3079                                 pipes[i].clock_source->funcs->program_pix_clk(
3080                                                 pipes[i].clock_source,
3081                                                 &pipes[i].stream_res.pix_clk_params,
3082                                                 dc->link_srv->dp_get_encoding_format(link_settings),
3083                                                 &pipes[i].pll_settings);
3084                         }
3085                 }
3086         }
3087
3088         if (dc->link_srv->dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) {
3089                 if (dc->clk_mgr->funcs->notify_link_rate_change)
3090                         dc->clk_mgr->funcs->notify_link_rate_change(dc->clk_mgr, link);
3091         }
3092
3093         if (dmcu != NULL && dmcu->funcs->lock_phy)
3094                 dmcu->funcs->lock_phy(dmcu);
3095
3096         if (link_hwss->ext.enable_dp_link_output)
3097                 link_hwss->ext.enable_dp_link_output(link, link_res, signal,
3098                                 clock_source, link_settings);
3099
3100         link->phy_state.symclk_state = SYMCLK_ON_TX_ON;
3101
3102         if (dmcu != NULL && dmcu->funcs->unlock_phy)
3103                 dmcu->funcs->unlock_phy(dmcu);
3104
3105         dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_LINK_PHY);
3106 }
3107
3108 void dce110_disable_link_output(struct dc_link *link,
3109                 const struct link_resource *link_res,
3110                 enum signal_type signal)
3111 {
3112         struct dc *dc = link->ctx->dc;
3113         const struct link_hwss *link_hwss = get_link_hwss(link, link_res);
3114         struct dmcu *dmcu = dc->res_pool->dmcu;
3115
3116         if (signal == SIGNAL_TYPE_EDP &&
3117                         link->dc->hwss.edp_backlight_control)
3118                 link->dc->hwss.edp_backlight_control(link, false);
3119         else if (dmcu != NULL && dmcu->funcs->lock_phy)
3120                 dmcu->funcs->lock_phy(dmcu);
3121
3122         link_hwss->disable_link_output(link, link_res, signal);
3123         link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF;
3124         /*
3125          * Add the logic to extract BOTH power up and power down sequences
3126          * from enable/disable link output and only call edp panel control
3127          * in enable_link_dp and disable_link_dp once.
3128          */
3129         if (dmcu != NULL && dmcu->funcs->lock_phy)
3130                 dmcu->funcs->unlock_phy(dmcu);
3131         dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);
3132 }
3133
3134 static const struct hw_sequencer_funcs dce110_funcs = {
3135         .program_gamut_remap = program_gamut_remap,
3136         .program_output_csc = program_output_csc,
3137         .init_hw = init_hw,
3138         .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
3139         .apply_ctx_for_surface = dce110_apply_ctx_for_surface,
3140         .post_unlock_program_front_end = dce110_post_unlock_program_front_end,
3141         .update_plane_addr = update_plane_addr,
3142         .update_pending_status = dce110_update_pending_status,
3143         .enable_accelerated_mode = dce110_enable_accelerated_mode,
3144         .enable_timing_synchronization = dce110_enable_timing_synchronization,
3145         .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset,
3146         .update_info_frame = dce110_update_info_frame,
3147         .enable_stream = dce110_enable_stream,
3148         .disable_stream = dce110_disable_stream,
3149         .unblank_stream = dce110_unblank_stream,
3150         .blank_stream = dce110_blank_stream,
3151         .enable_audio_stream = dce110_enable_audio_stream,
3152         .disable_audio_stream = dce110_disable_audio_stream,
3153         .disable_plane = dce110_power_down_fe,
3154         .pipe_control_lock = dce_pipe_control_lock,
3155         .interdependent_update_lock = NULL,
3156         .cursor_lock = dce_pipe_control_lock,
3157         .prepare_bandwidth = dce110_prepare_bandwidth,
3158         .optimize_bandwidth = dce110_optimize_bandwidth,
3159         .set_drr = set_drr,
3160         .get_position = get_position,
3161         .set_static_screen_control = set_static_screen_control,
3162         .setup_stereo = NULL,
3163         .set_avmute = dce110_set_avmute,
3164         .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect,
3165         .edp_backlight_control = dce110_edp_backlight_control,
3166         .edp_power_control = dce110_edp_power_control,
3167         .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
3168         .set_cursor_position = dce110_set_cursor_position,
3169         .set_cursor_attribute = dce110_set_cursor_attribute,
3170         .set_backlight_level = dce110_set_backlight_level,
3171         .set_abm_immediate_disable = dce110_set_abm_immediate_disable,
3172         .set_pipe = dce110_set_pipe,
3173         .enable_lvds_link_output = dce110_enable_lvds_link_output,
3174         .enable_tmds_link_output = dce110_enable_tmds_link_output,
3175         .enable_dp_link_output = dce110_enable_dp_link_output,
3176         .disable_link_output = dce110_disable_link_output,
3177 };
3178
3179 static const struct hwseq_private_funcs dce110_private_funcs = {
3180         .init_pipes = init_pipes,
3181         .update_plane_addr = update_plane_addr,
3182         .set_input_transfer_func = dce110_set_input_transfer_func,
3183         .set_output_transfer_func = dce110_set_output_transfer_func,
3184         .power_down = dce110_power_down,
3185         .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating,
3186         .enable_display_power_gating = dce110_enable_display_power_gating,
3187         .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap,
3188         .enable_stream_timing = dce110_enable_stream_timing,
3189         .disable_stream_gating = NULL,
3190         .enable_stream_gating = NULL,
3191         .edp_backlight_control = dce110_edp_backlight_control,
3192 };
3193
3194 void dce110_hw_sequencer_construct(struct dc *dc)
3195 {
3196         dc->hwss = dce110_funcs;
3197         dc->hwseq->funcs = dce110_private_funcs;
3198 }
3199