drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27
  28
  29 #include "dc_types.h"
  30 #include "core_types.h"
  31
  32 #include "include/grph_object_id.h"
  33 #include "include/logger_interface.h"
  34
  35 #include "dce_clock_source.h"
  36 #include "clk_mgr.h"
  37
  38 #include "reg_helper.h"
  39
  40 #define REG(reg)\
  41         (clk_src->regs->reg)
  42
  43 #define CTX \
  44         clk_src->base.ctx
  45
  46 #define DC_LOGGER_INIT()
  47
  48 #undef FN
  49 #define FN(reg_name, field_name) \
  50         clk_src->cs_shift->field_name, clk_src->cs_mask->field_name
  51
  52 #define FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM 6
  53 #define CALC_PLL_CLK_SRC_ERR_TOLERANCE 1
  54 #define MAX_PLL_CALC_ERROR 0xFFFFFFFF
  55
  56 #define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))
  57
  58 static const struct spread_spectrum_data *get_ss_data_entry(
  59                 struct dce110_clk_src *clk_src,
  60                 enum signal_type signal,
  61                 uint32_t pix_clk_khz)
  62 {
  63
  64         uint32_t entrys_num;
  65         uint32_t i;
  66         struct spread_spectrum_data *ss_parm = NULL;
  67         struct spread_spectrum_data *ret = NULL;
  68
  69         switch (signal) {
  70         case SIGNAL_TYPE_DVI_SINGLE_LINK:
  71         case SIGNAL_TYPE_DVI_DUAL_LINK:
  72                 ss_parm = clk_src->dvi_ss_params;
  73                 entrys_num = clk_src->dvi_ss_params_cnt;
  74                 break;
  75
  76         case SIGNAL_TYPE_HDMI_TYPE_A:
  77                 ss_parm = clk_src->hdmi_ss_params;
  78                 entrys_num = clk_src->hdmi_ss_params_cnt;
  79                 break;
  80
  81         case SIGNAL_TYPE_LVDS:
  82                 ss_parm = clk_src->lvds_ss_params;
  83                 entrys_num = clk_src->lvds_ss_params_cnt;
  84                 break;
  85
  86         case SIGNAL_TYPE_DISPLAY_PORT:
  87         case SIGNAL_TYPE_DISPLAY_PORT_MST:
  88         case SIGNAL_TYPE_EDP:
  89         case SIGNAL_TYPE_VIRTUAL:
  90                 ss_parm = clk_src->dp_ss_params;
  91                 entrys_num = clk_src->dp_ss_params_cnt;
  92                 break;
  93
  94         default:
  95                 ss_parm = NULL;
  96                 entrys_num = 0;
  97                 break;
  98         }
  99
 100         if (ss_parm == NULL)
 101                 return ret;
 102
 103         for (i = 0; i < entrys_num; ++i, ++ss_parm) {
 104                 if (ss_parm->freq_range_khz >= pix_clk_khz) {
 105                         ret = ss_parm;
 106                         break;
 107                 }
 108         }
 109
 110         return ret;
 111 }
 112
 113 /**
 114  * calculate_fb_and_fractional_fb_divider - Calculates feedback and fractional
 115  *                                          feedback dividers values
 116  *
 117  * @calc_pll_cs:            Pointer to clock source information
 118  * @target_pix_clk_100hz:   Desired frequency in 100 Hz
 119  * @ref_divider:            Reference divider (already known)
 120  * @post_divider:           Post Divider (already known)
 121  * @feedback_divider_param: Pointer where to store
 122  *                          calculated feedback divider value
 123  * @fract_feedback_divider_param: Pointer where to store
 124  *                          calculated fract feedback divider value
 125  *
 126  * return:
 127  * It fills the locations pointed by feedback_divider_param
 128  *                                      and fract_feedback_divider_param
 129  * It returns   - true if feedback divider not 0
 130  *              - false should never happen)
 131  */
 132 static bool calculate_fb_and_fractional_fb_divider(
 133                 struct calc_pll_clock_source *calc_pll_cs,
 134                 uint32_t target_pix_clk_100hz,
 135                 uint32_t ref_divider,
 136                 uint32_t post_divider,
 137                 uint32_t *feedback_divider_param,
 138                 uint32_t *fract_feedback_divider_param)
 139 {
 140         uint64_t feedback_divider;
 141
 142         feedback_divider =
 143                 (uint64_t)target_pix_clk_100hz * ref_divider * post_divider;
 144         feedback_divider *= 10;
 145         /* additional factor, since we divide by 10 afterwards */
 146         feedback_divider *= (uint64_t)(calc_pll_cs->fract_fb_divider_factor);
 147         feedback_divider = div_u64(feedback_divider, calc_pll_cs->ref_freq_khz * 10ull);
 148
 149 /*Round to the number of precision
 150  * The following code replace the old code (ullfeedbackDivider + 5)/10
 151  * for example if the difference between the number
 152  * of fractional feedback decimal point and the fractional FB Divider precision
 153  * is 2 then the equation becomes (ullfeedbackDivider + 5*100) / (10*100))*/
 154
 155         feedback_divider += 5ULL *
 156                             calc_pll_cs->fract_fb_divider_precision_factor;
 157         feedback_divider =
 158                 div_u64(feedback_divider,
 159                         calc_pll_cs->fract_fb_divider_precision_factor * 10);
 160         feedback_divider *= (uint64_t)
 161                         (calc_pll_cs->fract_fb_divider_precision_factor);
 162
 163         *feedback_divider_param =
 164                 div_u64_rem(
 165                         feedback_divider,
 166                         calc_pll_cs->fract_fb_divider_factor,
 167                         fract_feedback_divider_param);
 168
 169         if (*feedback_divider_param != 0)
 170                 return true;
 171         return false;
 172 }
 173
 174 /**
 175  * calc_fb_divider_checking_tolerance - Calculates Feedback and
 176  *                                      Fractional Feedback divider values
 177  *                                      for passed Reference and Post divider,
 178  *                                      checking for tolerance.
 179  * @calc_pll_cs:        Pointer to clock source information
 180  * @pll_settings:       Pointer to PLL settings
 181  * @ref_divider:        Reference divider (already known)
 182  * @post_divider:       Post Divider (already known)
 183  * @tolerance:          Tolerance for Calculated Pixel Clock to be within
 184  *
 185  * return:
 186  *  It fills the PLLSettings structure with PLL Dividers values
 187  *  if calculated values are within required tolerance
 188  *  It returns  - true if error is within tolerance
 189  *              - false if error is not within tolerance
 190  */
 191 static bool calc_fb_divider_checking_tolerance(
 192                 struct calc_pll_clock_source *calc_pll_cs,
 193                 struct pll_settings *pll_settings,
 194                 uint32_t ref_divider,
 195                 uint32_t post_divider,
 196                 uint32_t tolerance)
 197 {
 198         uint32_t feedback_divider;
 199         uint32_t fract_feedback_divider;
 200         uint32_t actual_calculated_clock_100hz;
 201         uint32_t abs_err;
 202         uint64_t actual_calc_clk_100hz;
 203
 204         calculate_fb_and_fractional_fb_divider(
 205                         calc_pll_cs,
 206                         pll_settings->adjusted_pix_clk_100hz,
 207                         ref_divider,
 208                         post_divider,
 209                         &feedback_divider,
 210                         &fract_feedback_divider);
 211
 212         /*Actual calculated value*/
 213         actual_calc_clk_100hz = (uint64_t)feedback_divider *
 214                                         calc_pll_cs->fract_fb_divider_factor +
 215                                                         fract_feedback_divider;
 216         actual_calc_clk_100hz *= calc_pll_cs->ref_freq_khz * 10;
 217         actual_calc_clk_100hz =
 218                 div_u64(actual_calc_clk_100hz,
 219                         ref_divider * post_divider *
 220                                 calc_pll_cs->fract_fb_divider_factor);
 221
 222         actual_calculated_clock_100hz = (uint32_t)(actual_calc_clk_100hz);
 223
 224         abs_err = (actual_calculated_clock_100hz >
 225                                         pll_settings->adjusted_pix_clk_100hz)
 226                         ? actual_calculated_clock_100hz -
 227                                         pll_settings->adjusted_pix_clk_100hz
 228                         : pll_settings->adjusted_pix_clk_100hz -
 229                                                 actual_calculated_clock_100hz;
 230
 231         if (abs_err <= tolerance) {
 232                 /*found good values*/
 233                 pll_settings->reference_freq = calc_pll_cs->ref_freq_khz;
 234                 pll_settings->reference_divider = ref_divider;
 235                 pll_settings->feedback_divider = feedback_divider;
 236                 pll_settings->fract_feedback_divider = fract_feedback_divider;
 237                 pll_settings->pix_clk_post_divider = post_divider;
 238                 pll_settings->calculated_pix_clk_100hz =
 239                         actual_calculated_clock_100hz;
 240                 pll_settings->vco_freq =
 241                         div_u64((u64)actual_calculated_clock_100hz * post_divider, 10);
 242                 return true;
 243         }
 244         return false;
 245 }
 246
 247 static bool calc_pll_dividers_in_range(
 248                 struct calc_pll_clock_source *calc_pll_cs,
 249                 struct pll_settings *pll_settings,
 250                 uint32_t min_ref_divider,
 251                 uint32_t max_ref_divider,
 252                 uint32_t min_post_divider,
 253                 uint32_t max_post_divider,
 254                 uint32_t err_tolerance)
 255 {
 256         uint32_t ref_divider;
 257         uint32_t post_divider;
 258         uint32_t tolerance;
 259
 260 /* This is err_tolerance / 10000 = 0.0025 - acceptable error of 0.25%
 261  * This is errorTolerance / 10000 = 0.0001 - acceptable error of 0.01%*/
 262         tolerance = (pll_settings->adjusted_pix_clk_100hz * err_tolerance) /
 263                                                                         100000;
 264         if (tolerance < CALC_PLL_CLK_SRC_ERR_TOLERANCE)
 265                 tolerance = CALC_PLL_CLK_SRC_ERR_TOLERANCE;
 266
 267         for (
 268                         post_divider = max_post_divider;
 269                         post_divider >= min_post_divider;
 270                         --post_divider) {
 271                 for (
 272                                 ref_divider = min_ref_divider;
 273                                 ref_divider <= max_ref_divider;
 274                                 ++ref_divider) {
 275                         if (calc_fb_divider_checking_tolerance(
 276                                         calc_pll_cs,
 277                                         pll_settings,
 278                                         ref_divider,
 279                                         post_divider,
 280                                         tolerance)) {
 281                                 return true;
 282                         }
 283                 }
 284         }
 285
 286         return false;
 287 }
 288
 289 static uint32_t calculate_pixel_clock_pll_dividers(
 290                 struct calc_pll_clock_source *calc_pll_cs,
 291                 struct pll_settings *pll_settings)
 292 {
 293         uint32_t err_tolerance;
 294         uint32_t min_post_divider;
 295         uint32_t max_post_divider;
 296         uint32_t min_ref_divider;
 297         uint32_t max_ref_divider;
 298
 299         if (pll_settings->adjusted_pix_clk_100hz == 0) {
 300                 DC_LOG_ERROR(
 301                         "%s Bad requested pixel clock", __func__);
 302                 return MAX_PLL_CALC_ERROR;
 303         }
 304
 305 /* 1) Find Post divider ranges */
 306         if (pll_settings->pix_clk_post_divider) {
 307                 min_post_divider = pll_settings->pix_clk_post_divider;
 308                 max_post_divider = pll_settings->pix_clk_post_divider;
 309         } else {
 310                 min_post_divider = calc_pll_cs->min_pix_clock_pll_post_divider;
 311                 if (min_post_divider * pll_settings->adjusted_pix_clk_100hz <
 312                                                 calc_pll_cs->min_vco_khz * 10) {
 313                         min_post_divider = calc_pll_cs->min_vco_khz * 10 /
 314                                         pll_settings->adjusted_pix_clk_100hz;
 315                         if ((min_post_divider *
 316                                         pll_settings->adjusted_pix_clk_100hz) <
 317                                                 calc_pll_cs->min_vco_khz * 10)
 318                                 min_post_divider++;
 319                 }
 320
 321                 max_post_divider = calc_pll_cs->max_pix_clock_pll_post_divider;
 322                 if (max_post_divider * pll_settings->adjusted_pix_clk_100hz
 323                                 > calc_pll_cs->max_vco_khz * 10)
 324                         max_post_divider = calc_pll_cs->max_vco_khz * 10 /
 325                                         pll_settings->adjusted_pix_clk_100hz;
 326         }
 327
 328 /* 2) Find Reference divider ranges
 329  * When SS is enabled, or for Display Port even without SS,
 330  * pll_settings->referenceDivider is not zero.
 331  * So calculate PPLL FB and fractional FB divider
 332  * using the passed reference divider*/
 333
 334         if (pll_settings->reference_divider) {
 335                 min_ref_divider = pll_settings->reference_divider;
 336                 max_ref_divider = pll_settings->reference_divider;
 337         } else {
 338                 min_ref_divider = ((calc_pll_cs->ref_freq_khz
 339                                 / calc_pll_cs->max_pll_input_freq_khz)
 340                                 > calc_pll_cs->min_pll_ref_divider)
 341                         ? calc_pll_cs->ref_freq_khz
 342                                         / calc_pll_cs->max_pll_input_freq_khz
 343                         : calc_pll_cs->min_pll_ref_divider;
 344
 345                 max_ref_divider = ((calc_pll_cs->ref_freq_khz
 346                                 / calc_pll_cs->min_pll_input_freq_khz)
 347                                 < calc_pll_cs->max_pll_ref_divider)
 348                         ? calc_pll_cs->ref_freq_khz /
 349                                         calc_pll_cs->min_pll_input_freq_khz
 350                         : calc_pll_cs->max_pll_ref_divider;
 351         }
 352
 353 /* If some parameters are invalid we could have scenario when  "min">"max"
 354  * which produced endless loop later.
 355  * We should investigate why we get the wrong parameters.
 356  * But to follow the similar logic when "adjustedPixelClock" is set to be 0
 357  * it is better to return here than cause system hang/watchdog timeout later.
 358  *  ## SVS Wed 15 Jul 2009 */
 359
 360         if (min_post_divider > max_post_divider) {
 361                 DC_LOG_ERROR(
 362                         "%s Post divider range is invalid", __func__);
 363                 return MAX_PLL_CALC_ERROR;
 364         }
 365
 366         if (min_ref_divider > max_ref_divider) {
 367                 DC_LOG_ERROR(
 368                         "%s Reference divider range is invalid", __func__);
 369                 return MAX_PLL_CALC_ERROR;
 370         }
 371
 372 /* 3) Try to find PLL dividers given ranges
 373  * starting with minimal error tolerance.
 374  * Increase error tolerance until PLL dividers found*/
 375         err_tolerance = MAX_PLL_CALC_ERROR;
 376
 377         while (!calc_pll_dividers_in_range(
 378                         calc_pll_cs,
 379                         pll_settings,
 380                         min_ref_divider,
 381                         max_ref_divider,
 382                         min_post_divider,
 383                         max_post_divider,
 384                         err_tolerance))
 385                 err_tolerance += (err_tolerance > 10)
 386                                 ? (err_tolerance / 10)
 387                                 : 1;
 388
 389         return err_tolerance;
 390 }
 391
 392 static bool pll_adjust_pix_clk(
 393                 struct dce110_clk_src *clk_src,
 394                 struct pixel_clk_params *pix_clk_params,
 395                 struct pll_settings *pll_settings)
 396 {
 397         uint32_t actual_pix_clk_100hz = 0;
 398         uint32_t requested_clk_100hz = 0;
 399         struct bp_adjust_pixel_clock_parameters bp_adjust_pixel_clock_params = {
 400                                                         0 };
 401         enum bp_result bp_result;
 402         switch (pix_clk_params->signal_type) {
 403         case SIGNAL_TYPE_HDMI_TYPE_A: {
 404                 requested_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
 405                 if (pix_clk_params->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
 406                         switch (pix_clk_params->color_depth) {
 407                         case COLOR_DEPTH_101010:
 408                                 requested_clk_100hz = (requested_clk_100hz * 5) >> 2;
 409                                 break; /* x1.25*/
 410                         case COLOR_DEPTH_121212:
 411                                 requested_clk_100hz = (requested_clk_100hz * 6) >> 2;
 412                                 break; /* x1.5*/
 413                         case COLOR_DEPTH_161616:
 414                                 requested_clk_100hz = requested_clk_100hz * 2;
 415                                 break; /* x2.0*/
 416                         default:
 417                                 break;
 418                         }
 419                 }
 420                 actual_pix_clk_100hz = requested_clk_100hz;
 421         }
 422                 break;
 423
 424         case SIGNAL_TYPE_DISPLAY_PORT:
 425         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 426         case SIGNAL_TYPE_EDP:
 427                 requested_clk_100hz = pix_clk_params->requested_sym_clk * 10;
 428                 actual_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
 429                 break;
 430
 431         default:
 432                 requested_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
 433                 actual_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
 434                 break;
 435         }
 436
 437         bp_adjust_pixel_clock_params.pixel_clock = requested_clk_100hz / 10;
 438         bp_adjust_pixel_clock_params.
 439                 encoder_object_id = pix_clk_params->encoder_object_id;
 440         bp_adjust_pixel_clock_params.signal_type = pix_clk_params->signal_type;
 441         bp_adjust_pixel_clock_params.
 442                 ss_enable = pix_clk_params->flags.ENABLE_SS;
 443         bp_result = clk_src->bios->funcs->adjust_pixel_clock(
 444                         clk_src->bios, &bp_adjust_pixel_clock_params);
 445         if (bp_result == BP_RESULT_OK) {
 446                 pll_settings->actual_pix_clk_100hz = actual_pix_clk_100hz;
 447                 pll_settings->adjusted_pix_clk_100hz =
 448                         bp_adjust_pixel_clock_params.adjusted_pixel_clock * 10;
 449                 pll_settings->reference_divider =
 450                         bp_adjust_pixel_clock_params.reference_divider;
 451                 pll_settings->pix_clk_post_divider =
 452                         bp_adjust_pixel_clock_params.pixel_clock_post_divider;
 453
 454                 return true;
 455         }
 456
 457         return false;
 458 }
 459
 460 /*
 461  * Calculate PLL Dividers for given Clock Value.
 462  * First will call VBIOS Adjust Exec table to check if requested Pixel clock
 463  * will be Adjusted based on usage.
 464  * Then it will calculate PLL Dividers for this Adjusted clock using preferred
 465  * method (Maximum VCO frequency).
 466  *
 467  * \return
 468  *     Calculation error in units of 0.01%
 469  */
 470
 471 static uint32_t dce110_get_pix_clk_dividers_helper (
 472                 struct dce110_clk_src *clk_src,
 473                 struct pll_settings *pll_settings,
 474                 struct pixel_clk_params *pix_clk_params)
 475 {
 476         uint32_t field = 0;
 477         uint32_t pll_calc_error = MAX_PLL_CALC_ERROR;
 478         DC_LOGGER_INIT();
 479         /* Check if reference clock is external (not pcie/xtalin)
 480         * HW Dce80 spec:
 481         * 00 - PCIE_REFCLK, 01 - XTALIN,    02 - GENERICA,    03 - GENERICB
 482         * 04 - HSYNCA,      05 - GENLK_CLK, 06 - PCIE_REFCLK, 07 - DVOCLK0 */
 483         REG_GET(PLL_CNTL, PLL_REF_DIV_SRC, &field);
 484         pll_settings->use_external_clk = (field > 1);
 485
 486         /* VBIOS by default enables DP SS (spread on IDCLK) for DCE 8.0 always
 487          * (we do not care any more from SI for some older DP Sink which
 488          * does not report SS support, no known issues) */
 489         if ((pix_clk_params->flags.ENABLE_SS) ||
 490                         (dc_is_dp_signal(pix_clk_params->signal_type))) {
 491
 492                 const struct spread_spectrum_data *ss_data = get_ss_data_entry(
 493                                         clk_src,
 494                                         pix_clk_params->signal_type,
 495                                         pll_settings->adjusted_pix_clk_100hz / 10);
 496
 497                 if (NULL != ss_data)
 498                         pll_settings->ss_percentage = ss_data->percentage;
 499         }
 500
 501         /* Check VBIOS AdjustPixelClock Exec table */
 502         if (!pll_adjust_pix_clk(clk_src, pix_clk_params, pll_settings)) {
 503                 /* Should never happen, ASSERT and fill up values to be able
 504                  * to continue. */
 505                 DC_LOG_ERROR(
 506                         "%s: Failed to adjust pixel clock!!", __func__);
 507                 pll_settings->actual_pix_clk_100hz =
 508                                 pix_clk_params->requested_pix_clk_100hz;
 509                 pll_settings->adjusted_pix_clk_100hz =
 510                                 pix_clk_params->requested_pix_clk_100hz;
 511
 512                 if (dc_is_dp_signal(pix_clk_params->signal_type))
 513                         pll_settings->adjusted_pix_clk_100hz = 1000000;
 514         }
 515
 516         /* Calculate Dividers */
 517         if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A)
 518                 /*Calculate Dividers by HDMI object, no SS case or SS case */
 519                 pll_calc_error =
 520                         calculate_pixel_clock_pll_dividers(
 521                                         &clk_src->calc_pll_hdmi,
 522                                         pll_settings);
 523         else
 524                 /*Calculate Dividers by default object, no SS case or SS case */
 525                 pll_calc_error =
 526                         calculate_pixel_clock_pll_dividers(
 527                                         &clk_src->calc_pll,
 528                                         pll_settings);
 529
 530         return pll_calc_error;
 531 }
 532
 533 static void dce112_get_pix_clk_dividers_helper (
 534                 struct dce110_clk_src *clk_src,
 535                 struct pll_settings *pll_settings,
 536                 struct pixel_clk_params *pix_clk_params)
 537 {
 538         uint32_t actual_pixel_clock_100hz;
 539
 540         actual_pixel_clock_100hz = pix_clk_params->requested_pix_clk_100hz;
 541         /* Calculate Dividers */
 542         if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) {
 543                 switch (pix_clk_params->color_depth) {
 544                 case COLOR_DEPTH_101010:
 545                         actual_pixel_clock_100hz = (actual_pixel_clock_100hz * 5) >> 2;
 546                         break;
 547                 case COLOR_DEPTH_121212:
 548                         actual_pixel_clock_100hz = (actual_pixel_clock_100hz * 6) >> 2;
 549                         break;
 550                 case COLOR_DEPTH_161616:
 551                         actual_pixel_clock_100hz = actual_pixel_clock_100hz * 2;
 552                         break;
 553                 default:
 554                         break;
 555                 }
 556         }
 557         pll_settings->actual_pix_clk_100hz = actual_pixel_clock_100hz;
 558         pll_settings->adjusted_pix_clk_100hz = actual_pixel_clock_100hz;
 559         pll_settings->calculated_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
 560 }
 561
 562 static uint32_t dce110_get_pix_clk_dividers(
 563                 struct clock_source *cs,
 564                 struct pixel_clk_params *pix_clk_params,
 565                 struct pll_settings *pll_settings)
 566 {
 567         struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs);
 568         uint32_t pll_calc_error = MAX_PLL_CALC_ERROR;
 569         DC_LOGGER_INIT();
 570
 571         if (pix_clk_params == NULL || pll_settings == NULL
 572                         || pix_clk_params->requested_pix_clk_100hz == 0) {
 573                 DC_LOG_ERROR(
 574                         "%s: Invalid parameters!!\n", __func__);
 575                 return pll_calc_error;
 576         }
 577
 578         memset(pll_settings, 0, sizeof(*pll_settings));
 579
 580         if (cs->id == CLOCK_SOURCE_ID_DP_DTO ||
 581                         cs->id == CLOCK_SOURCE_ID_EXTERNAL) {
 582                 pll_settings->adjusted_pix_clk_100hz = clk_src->ext_clk_khz * 10;
 583                 pll_settings->calculated_pix_clk_100hz = clk_src->ext_clk_khz * 10;
 584                 pll_settings->actual_pix_clk_100hz =
 585                                         pix_clk_params->requested_pix_clk_100hz;
 586                 return 0;
 587         }
 588
 589         pll_calc_error = dce110_get_pix_clk_dividers_helper(clk_src,
 590                         pll_settings, pix_clk_params);
 591
 592         return pll_calc_error;
 593 }
 594
 595 static uint32_t dce112_get_pix_clk_dividers(
 596                 struct clock_source *cs,
 597                 struct pixel_clk_params *pix_clk_params,
 598                 struct pll_settings *pll_settings)
 599 {
 600         struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs);
 601         DC_LOGGER_INIT();
 602
 603         if (pix_clk_params == NULL || pll_settings == NULL
 604                         || pix_clk_params->requested_pix_clk_100hz == 0) {
 605                 DC_LOG_ERROR(
 606                         "%s: Invalid parameters!!\n", __func__);
 607                 return -1;
 608         }
 609
 610         memset(pll_settings, 0, sizeof(*pll_settings));
 611
 612         if (cs->id == CLOCK_SOURCE_ID_DP_DTO ||
 613                         cs->id == CLOCK_SOURCE_ID_EXTERNAL) {
 614                 pll_settings->adjusted_pix_clk_100hz = clk_src->ext_clk_khz * 10;
 615                 pll_settings->calculated_pix_clk_100hz = clk_src->ext_clk_khz * 10;
 616                 pll_settings->actual_pix_clk_100hz =
 617                                         pix_clk_params->requested_pix_clk_100hz;
 618                 return -1;
 619         }
 620
 621         dce112_get_pix_clk_dividers_helper(clk_src,
 622                         pll_settings, pix_clk_params);
 623
 624         return 0;
 625 }
 626
 627 static bool disable_spread_spectrum(struct dce110_clk_src *clk_src)
 628 {
 629         enum bp_result result;
 630         struct bp_spread_spectrum_parameters bp_ss_params = {0};
 631
 632         bp_ss_params.pll_id = clk_src->base.id;
 633
 634         /*Call ASICControl to process ATOMBIOS Exec table*/
 635         result = clk_src->bios->funcs->enable_spread_spectrum_on_ppll(
 636                         clk_src->bios,
 637                         &bp_ss_params,
 638                         false);
 639
 640         return result == BP_RESULT_OK;
 641 }
 642
 643 static bool calculate_ss(
 644                 const struct pll_settings *pll_settings,
 645                 const struct spread_spectrum_data *ss_data,
 646                 struct delta_sigma_data *ds_data)
 647 {
 648         struct fixed31_32 fb_div;
 649         struct fixed31_32 ss_amount;
 650         struct fixed31_32 ss_nslip_amount;
 651         struct fixed31_32 ss_ds_frac_amount;
 652         struct fixed31_32 ss_step_size;
 653         struct fixed31_32 modulation_time;
 654
 655         if (ds_data == NULL)
 656                 return false;
 657         if (ss_data == NULL)
 658                 return false;
 659         if (ss_data->percentage == 0)
 660                 return false;
 661         if (pll_settings == NULL)
 662                 return false;
 663
 664         memset(ds_data, 0, sizeof(struct delta_sigma_data));
 665
 666         /* compute SS_AMOUNT_FBDIV & SS_AMOUNT_NFRAC_SLIP & SS_AMOUNT_DSFRAC*/
 667         /* 6 decimal point support in fractional feedback divider */
 668         fb_div  = dc_fixpt_from_fraction(
 669                 pll_settings->fract_feedback_divider, 1000000);
 670         fb_div = dc_fixpt_add_int(fb_div, pll_settings->feedback_divider);
 671
 672         ds_data->ds_frac_amount = 0;
 673         /*spreadSpectrumPercentage is in the unit of .01%,
 674          * so have to divided by 100 * 100*/
 675         ss_amount = dc_fixpt_mul(
 676                 fb_div, dc_fixpt_from_fraction(ss_data->percentage,
 677                                         100 * ss_data->percentage_divider));
 678         ds_data->feedback_amount = dc_fixpt_floor(ss_amount);
 679
 680         ss_nslip_amount = dc_fixpt_sub(ss_amount,
 681                 dc_fixpt_from_int(ds_data->feedback_amount));
 682         ss_nslip_amount = dc_fixpt_mul_int(ss_nslip_amount, 10);
 683         ds_data->nfrac_amount = dc_fixpt_floor(ss_nslip_amount);
 684
 685         ss_ds_frac_amount = dc_fixpt_sub(ss_nslip_amount,
 686                 dc_fixpt_from_int(ds_data->nfrac_amount));
 687         ss_ds_frac_amount = dc_fixpt_mul_int(ss_ds_frac_amount, 65536);
 688         ds_data->ds_frac_amount = dc_fixpt_floor(ss_ds_frac_amount);
 689
 690         /* compute SS_STEP_SIZE_DSFRAC */
 691         modulation_time = dc_fixpt_from_fraction(
 692                 pll_settings->reference_freq * 1000,
 693                 pll_settings->reference_divider * ss_data->modulation_freq_hz);
 694
 695         if (ss_data->flags.CENTER_SPREAD)
 696                 modulation_time = dc_fixpt_div_int(modulation_time, 4);
 697         else
 698                 modulation_time = dc_fixpt_div_int(modulation_time, 2);
 699
 700         ss_step_size = dc_fixpt_div(ss_amount, modulation_time);
 701         /* SS_STEP_SIZE_DSFRAC_DEC = Int(SS_STEP_SIZE * 2 ^ 16 * 10)*/
 702         ss_step_size = dc_fixpt_mul_int(ss_step_size, 65536 * 10);
 703         ds_data->ds_frac_size =  dc_fixpt_floor(ss_step_size);
 704
 705         return true;
 706 }
 707
 708 static bool enable_spread_spectrum(
 709                 struct dce110_clk_src *clk_src,
 710                 enum signal_type signal, struct pll_settings *pll_settings)
 711 {
 712         struct bp_spread_spectrum_parameters bp_params = {0};
 713         struct delta_sigma_data d_s_data;
 714         const struct spread_spectrum_data *ss_data = NULL;
 715
 716         ss_data = get_ss_data_entry(
 717                         clk_src,
 718                         signal,
 719                         pll_settings->calculated_pix_clk_100hz / 10);
 720
 721 /* Pixel clock PLL has been programmed to generate desired pixel clock,
 722  * now enable SS on pixel clock */
 723 /* TODO is it OK to return true not doing anything ??*/
 724         if (ss_data != NULL && pll_settings->ss_percentage != 0) {
 725                 if (calculate_ss(pll_settings, ss_data, &d_s_data)) {
 726                         bp_params.ds.feedback_amount =
 727                                         d_s_data.feedback_amount;
 728                         bp_params.ds.nfrac_amount =
 729                                         d_s_data.nfrac_amount;
 730                         bp_params.ds.ds_frac_size = d_s_data.ds_frac_size;
 731                         bp_params.ds_frac_amount =
 732                                         d_s_data.ds_frac_amount;
 733                         bp_params.flags.DS_TYPE = 1;
 734                         bp_params.pll_id = clk_src->base.id;
 735                         bp_params.percentage = ss_data->percentage;
 736                         if (ss_data->flags.CENTER_SPREAD)
 737                                 bp_params.flags.CENTER_SPREAD = 1;
 738                         if (ss_data->flags.EXTERNAL_SS)
 739                                 bp_params.flags.EXTERNAL_SS = 1;
 740
 741                         if (BP_RESULT_OK !=
 742                                 clk_src->bios->funcs->
 743                                         enable_spread_spectrum_on_ppll(
 744                                                         clk_src->bios,
 745                                                         &bp_params,
 746                                                         true))
 747                                 return false;
 748                 } else
 749                         return false;
 750         }
 751         return true;
 752 }
 753
 754 static void dce110_program_pixel_clk_resync(
 755                 struct dce110_clk_src *clk_src,
 756                 enum signal_type signal_type,
 757                 enum dc_color_depth colordepth)
 758 {
 759         REG_UPDATE(RESYNC_CNTL,
 760                         DCCG_DEEP_COLOR_CNTL1, 0);
 761         /*
 762          24 bit mode: TMDS clock = 1.0 x pixel clock  (1:1)
 763          30 bit mode: TMDS clock = 1.25 x pixel clock (5:4)
 764          36 bit mode: TMDS clock = 1.5 x pixel clock  (3:2)
 765          48 bit mode: TMDS clock = 2 x pixel clock    (2:1)
 766          */
 767         if (signal_type != SIGNAL_TYPE_HDMI_TYPE_A)
 768                 return;
 769
 770         switch (colordepth) {
 771         case COLOR_DEPTH_888:
 772                 REG_UPDATE(RESYNC_CNTL,
 773                                 DCCG_DEEP_COLOR_CNTL1, 0);
 774                 break;
 775         case COLOR_DEPTH_101010:
 776                 REG_UPDATE(RESYNC_CNTL,
 777                                 DCCG_DEEP_COLOR_CNTL1, 1);
 778                 break;
 779         case COLOR_DEPTH_121212:
 780                 REG_UPDATE(RESYNC_CNTL,
 781                                 DCCG_DEEP_COLOR_CNTL1, 2);
 782                 break;
 783         case COLOR_DEPTH_161616:
 784                 REG_UPDATE(RESYNC_CNTL,
 785                                 DCCG_DEEP_COLOR_CNTL1, 3);
 786                 break;
 787         default:
 788                 break;
 789         }
 790 }
 791
 792 static void dce112_program_pixel_clk_resync(
 793                 struct dce110_clk_src *clk_src,
 794                 enum signal_type signal_type,
 795                 enum dc_color_depth colordepth,
 796                 bool enable_ycbcr420)
 797 {
 798         uint32_t deep_color_cntl = 0;
 799         uint32_t double_rate_enable = 0;
 800
 801         /*
 802          24 bit mode: TMDS clock = 1.0 x pixel clock  (1:1)
 803          30 bit mode: TMDS clock = 1.25 x pixel clock (5:4)
 804          36 bit mode: TMDS clock = 1.5 x pixel clock  (3:2)
 805          48 bit mode: TMDS clock = 2 x pixel clock    (2:1)
 806          */
 807         if (signal_type == SIGNAL_TYPE_HDMI_TYPE_A) {
 808                 double_rate_enable = enable_ycbcr420 ? 1 : 0;
 809
 810                 switch (colordepth) {
 811                 case COLOR_DEPTH_888:
 812                         deep_color_cntl = 0;
 813                         break;
 814                 case COLOR_DEPTH_101010:
 815                         deep_color_cntl = 1;
 816                         break;
 817                 case COLOR_DEPTH_121212:
 818                         deep_color_cntl = 2;
 819                         break;
 820                 case COLOR_DEPTH_161616:
 821                         deep_color_cntl = 3;
 822                         break;
 823                 default:
 824                         break;
 825                 }
 826         }
 827
 828         if (clk_src->cs_mask->PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE)
 829                 REG_UPDATE_2(PIXCLK_RESYNC_CNTL,
 830                                 PHYPLLA_DCCG_DEEP_COLOR_CNTL, deep_color_cntl,
 831                                 PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, double_rate_enable);
 832         else
 833                 REG_UPDATE(PIXCLK_RESYNC_CNTL,
 834                                 PHYPLLA_DCCG_DEEP_COLOR_CNTL, deep_color_cntl);
 835
 836 }
 837
 838 static bool dce110_program_pix_clk(
 839                 struct clock_source *clock_source,
 840                 struct pixel_clk_params *pix_clk_params,
 841                 enum dp_link_encoding encoding,
 842                 struct pll_settings *pll_settings)
 843 {
 844         struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
 845         struct bp_pixel_clock_parameters bp_pc_params = {0};
 846
 847         /* First disable SS
 848          * ATOMBIOS will enable by default SS on PLL for DP,
 849          * do not disable it here
 850          */
 851         if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL &&
 852                         !dc_is_dp_signal(pix_clk_params->signal_type) &&
 853                         clock_source->ctx->dce_version <= DCE_VERSION_11_0)
 854                 disable_spread_spectrum(clk_src);
 855
 856         /*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/
 857         bp_pc_params.controller_id = pix_clk_params->controller_id;
 858         bp_pc_params.pll_id = clock_source->id;
 859         bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz;
 860         bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id;
 861         bp_pc_params.signal_type = pix_clk_params->signal_type;
 862
 863         bp_pc_params.reference_divider = pll_settings->reference_divider;
 864         bp_pc_params.feedback_divider = pll_settings->feedback_divider;
 865         bp_pc_params.fractional_feedback_divider =
 866                         pll_settings->fract_feedback_divider;
 867         bp_pc_params.pixel_clock_post_divider =
 868                         pll_settings->pix_clk_post_divider;
 869         bp_pc_params.flags.SET_EXTERNAL_REF_DIV_SRC =
 870                                         pll_settings->use_external_clk;
 871
 872         switch (pix_clk_params->color_depth) {
 873         case COLOR_DEPTH_101010:
 874                 bp_pc_params.color_depth = TRANSMITTER_COLOR_DEPTH_30;
 875                 break;
 876         case COLOR_DEPTH_121212:
 877                 bp_pc_params.color_depth = TRANSMITTER_COLOR_DEPTH_36;
 878                 break;
 879         case COLOR_DEPTH_161616:
 880                 bp_pc_params.color_depth = TRANSMITTER_COLOR_DEPTH_48;
 881                 break;
 882         default:
 883                 break;
 884         }
 885
 886         if (clk_src->bios->funcs->set_pixel_clock(
 887                         clk_src->bios, &bp_pc_params) != BP_RESULT_OK)
 888                 return false;
 889         /* Enable SS
 890          * ATOMBIOS will enable by default SS for DP on PLL ( DP ID clock),
 891          * based on HW display PLL team, SS control settings should be programmed
 892          * during PLL Reset, but they do not have effect
 893          * until SS_EN is asserted.*/
 894         if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL
 895                         && !dc_is_dp_signal(pix_clk_params->signal_type)) {
 896
 897                 if (pix_clk_params->flags.ENABLE_SS)
 898                         if (!enable_spread_spectrum(clk_src,
 899                                                         pix_clk_params->signal_type,
 900                                                         pll_settings))
 901                                 return false;
 902
 903                 /* Resync deep color DTO */
 904                 dce110_program_pixel_clk_resync(clk_src,
 905                                         pix_clk_params->signal_type,
 906                                         pix_clk_params->color_depth);
 907         }
 908
 909         return true;
 910 }
 911
 912 static bool dce112_program_pix_clk(
 913                 struct clock_source *clock_source,
 914                 struct pixel_clk_params *pix_clk_params,
 915                 enum dp_link_encoding encoding,
 916                 struct pll_settings *pll_settings)
 917 {
 918         struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
 919         struct bp_pixel_clock_parameters bp_pc_params = {0};
 920
 921         if (IS_FPGA_MAXIMUS_DC(clock_source->ctx->dce_environment)) {
 922                 unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
 923                 unsigned dp_dto_ref_100hz = 7000000;
 924                 unsigned clock_100hz = pll_settings->actual_pix_clk_100hz;
 925
 926                 /* Set DTO values: phase = target clock, modulo = reference clock */
 927                 REG_WRITE(PHASE[inst], clock_100hz);
 928                 REG_WRITE(MODULO[inst], dp_dto_ref_100hz);
 929
 930                 /* Enable DTO */
 931                 REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);
 932                 return true;
 933         }
 934         /* First disable SS
 935          * ATOMBIOS will enable by default SS on PLL for DP,
 936          * do not disable it here
 937          */
 938         if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL &&
 939                         !dc_is_dp_signal(pix_clk_params->signal_type) &&
 940                         clock_source->ctx->dce_version <= DCE_VERSION_11_0)
 941                 disable_spread_spectrum(clk_src);
 942
 943         /*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/
 944         bp_pc_params.controller_id = pix_clk_params->controller_id;
 945         bp_pc_params.pll_id = clock_source->id;
 946         bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz;
 947         bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id;
 948         bp_pc_params.signal_type = pix_clk_params->signal_type;
 949
 950         if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
 951                 bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC =
 952                                                 pll_settings->use_external_clk;
 953                 bp_pc_params.flags.SET_XTALIN_REF_SRC =
 954                                                 !pll_settings->use_external_clk;
 955                 if (pix_clk_params->flags.SUPPORT_YCBCR420) {
 956                         bp_pc_params.flags.SUPPORT_YUV_420 = 1;
 957                 }
 958         }
 959         if (clk_src->bios->funcs->set_pixel_clock(
 960                         clk_src->bios, &bp_pc_params) != BP_RESULT_OK)
 961                 return false;
 962         /* Resync deep color DTO */
 963         if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO)
 964                 dce112_program_pixel_clk_resync(clk_src,
 965                                         pix_clk_params->signal_type,
 966                                         pix_clk_params->color_depth,
 967                                         pix_clk_params->flags.SUPPORT_YCBCR420);
 968
 969         return true;
 970 }
 971
 972 static bool dcn31_program_pix_clk(
 973                 struct clock_source *clock_source,
 974                 struct pixel_clk_params *pix_clk_params,
 975                 enum dp_link_encoding encoding,
 976                 struct pll_settings *pll_settings)
 977 {
 978         struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
 979         unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
 980         unsigned int dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz;
 981         const struct pixel_rate_range_table_entry *e =
 982                         look_up_in_video_optimized_rate_tlb(pix_clk_params->requested_pix_clk_100hz / 10);
 983         struct bp_pixel_clock_parameters bp_pc_params = {0};
 984         enum transmitter_color_depth bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24;
 985         // For these signal types Driver to program DP_DTO without calling VBIOS Command table
 986         if (dc_is_dp_signal(pix_clk_params->signal_type) || dc_is_virtual_signal(pix_clk_params->signal_type)) {
 987                 if (e) {
 988                         /* Set DTO values: phase = target clock, modulo = reference clock*/
 989                         REG_WRITE(PHASE[inst], e->target_pixel_rate_khz * e->mult_factor);
 990                         REG_WRITE(MODULO[inst], dp_dto_ref_khz * e->div_factor);
 991                 } else {
 992                         /* Set DTO values: phase = target clock, modulo = reference clock*/
 993                         REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100);
 994                         REG_WRITE(MODULO[inst], dp_dto_ref_khz * 1000);
 995                 }
 996 #if defined(CONFIG_DRM_AMD_DC_DCN)
 997                 /* Enable DTO */
 998                 if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL)
 999                         if (encoding == DP_128b_132b_ENCODING)
1000                                 REG_UPDATE_2(PIXEL_RATE_CNTL[inst],
1001                                                 DP_DTO0_ENABLE, 1,
1002                                                 PIPE0_DTO_SRC_SEL, 2);
1003                         else
1004                                 REG_UPDATE_2(PIXEL_RATE_CNTL[inst],
1005                                                 DP_DTO0_ENABLE, 1,
1006                                                 PIPE0_DTO_SRC_SEL, 1);
1007                 else
1008                         REG_UPDATE(PIXEL_RATE_CNTL[inst],
1009                                         DP_DTO0_ENABLE, 1);
1010 #else
1011                 REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);
1012 #endif
1013         } else {
1014                 if (IS_FPGA_MAXIMUS_DC(clock_source->ctx->dce_environment)) {
1015                         unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
1016                         unsigned dp_dto_ref_100hz = 7000000;
1017                         unsigned clock_100hz = pll_settings->actual_pix_clk_100hz;
1018
1019                         /* Set DTO values: phase = target clock, modulo = reference clock */
1020                         REG_WRITE(PHASE[inst], clock_100hz);
1021                         REG_WRITE(MODULO[inst], dp_dto_ref_100hz);
1022
1023                         /* Enable DTO */
1024         #if defined(CONFIG_DRM_AMD_DC_DCN)
1025                         if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL)
1026                                 REG_UPDATE_2(PIXEL_RATE_CNTL[inst],
1027                                                 DP_DTO0_ENABLE, 1,
1028                                                 PIPE0_DTO_SRC_SEL, 1);
1029                         else
1030                                 REG_UPDATE(PIXEL_RATE_CNTL[inst],
1031                                                 DP_DTO0_ENABLE, 1);
1032         #else
1033                         REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);
1034         #endif
1035                         return true;
1036                 }
1037
1038 #if defined(CONFIG_DRM_AMD_DC_DCN)
1039                 if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL)
1040                         REG_UPDATE(PIXEL_RATE_CNTL[inst],
1041                                         PIPE0_DTO_SRC_SEL, 0);
1042 #endif
1043
1044                 /*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/
1045                 bp_pc_params.controller_id = pix_clk_params->controller_id;
1046                 bp_pc_params.pll_id = clock_source->id;
1047                 bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz;
1048                 bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id;
1049                 bp_pc_params.signal_type = pix_clk_params->signal_type;
1050
1051                 // Make sure we send the correct color depth to DMUB for HDMI
1052                 if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) {
1053                         switch (pix_clk_params->color_depth) {
1054                         case COLOR_DEPTH_888:
1055                                 bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24;
1056                                 break;
1057                         case COLOR_DEPTH_101010:
1058                                 bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_30;
1059                                 break;
1060                         case COLOR_DEPTH_121212:
1061                                 bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_36;
1062                                 break;
1063                         case COLOR_DEPTH_161616:
1064                                 bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_48;
1065                                 break;
1066                         default:
1067                                 bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24;
1068                                 break;
1069                         }
1070                         bp_pc_params.color_depth = bp_pc_colour_depth;
1071                 }
1072
1073                 if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
1074                         bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC =
1075                                                         pll_settings->use_external_clk;
1076                         bp_pc_params.flags.SET_XTALIN_REF_SRC =
1077                                                         !pll_settings->use_external_clk;
1078                         if (pix_clk_params->flags.SUPPORT_YCBCR420) {
1079                                 bp_pc_params.flags.SUPPORT_YUV_420 = 1;
1080                         }
1081                 }
1082                 if (clk_src->bios->funcs->set_pixel_clock(
1083                                 clk_src->bios, &bp_pc_params) != BP_RESULT_OK)
1084                         return false;
1085                 /* Resync deep color DTO */
1086                 if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO)
1087                         dce112_program_pixel_clk_resync(clk_src,
1088                                                 pix_clk_params->signal_type,
1089                                                 pix_clk_params->color_depth,
1090                                                 pix_clk_params->flags.SUPPORT_YCBCR420);
1091         }
1092
1093         return true;
1094 }
1095
1096 static bool dce110_clock_source_power_down(
1097                 struct clock_source *clk_src)
1098 {
1099         struct dce110_clk_src *dce110_clk_src = TO_DCE110_CLK_SRC(clk_src);
1100         enum bp_result bp_result;
1101         struct bp_pixel_clock_parameters bp_pixel_clock_params = {0};
1102
1103         if (clk_src->dp_clk_src)
1104                 return true;
1105
1106         /* If Pixel Clock is 0 it means Power Down Pll*/
1107         bp_pixel_clock_params.controller_id = CONTROLLER_ID_UNDEFINED;
1108         bp_pixel_clock_params.pll_id = clk_src->id;
1109         bp_pixel_clock_params.flags.FORCE_PROGRAMMING_OF_PLL = 1;
1110
1111         /*Call ASICControl to process ATOMBIOS Exec table*/
1112         bp_result = dce110_clk_src->bios->funcs->set_pixel_clock(
1113                         dce110_clk_src->bios,
1114                         &bp_pixel_clock_params);
1115
1116         return bp_result == BP_RESULT_OK;
1117 }
1118
1119 static bool get_pixel_clk_frequency_100hz(
1120                 const struct clock_source *clock_source,
1121                 unsigned int inst,
1122                 unsigned int *pixel_clk_khz)
1123 {
1124         struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
1125         unsigned int clock_hz = 0;
1126         unsigned int modulo_hz = 0;
1127
1128         if (clock_source->id == CLOCK_SOURCE_ID_DP_DTO) {
1129                 clock_hz = REG_READ(PHASE[inst]);
1130
1131                 if (clock_source->ctx->dc->hwss.enable_vblanks_synchronization &&
1132                         clock_source->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0) {
1133                         /* NOTE: In case VBLANK syncronization is enabled, MODULO may
1134                          * not be programmed equal to DPREFCLK
1135                          */
1136                         modulo_hz = REG_READ(MODULO[inst]);
1137                         if (modulo_hz)
1138                                 *pixel_clk_khz = div_u64((uint64_t)clock_hz*
1139                                         clock_source->ctx->dc->clk_mgr->dprefclk_khz*10,
1140                                         modulo_hz);
1141                         else
1142                                 *pixel_clk_khz = 0;
1143                 } else {
1144                         /* NOTE: There is agreement with VBIOS here that MODULO is
1145                          * programmed equal to DPREFCLK, in which case PHASE will be
1146                          * equivalent to pixel clock.
1147                          */
1148                         *pixel_clk_khz = clock_hz / 100;
1149                 }
1150                 return true;
1151         }
1152
1153         return false;
1154 }
1155
1156 /* this table is use to find *1.001 and /1.001 pixel rates from non-precise pixel rate */
1157 const struct pixel_rate_range_table_entry video_optimized_pixel_rates[] = {
1158         // /1.001 rates
1159         {25170, 25180, 25200, 1000, 1001},      //25.2MHz   ->   25.17
1160         {59340, 59350, 59400, 1000, 1001},      //59.4Mhz   ->   59.340
1161         {74170, 74180, 74250, 1000, 1001},      //74.25Mhz  ->   74.1758
1162         {125870, 125880, 126000, 1000, 1001},   //126Mhz    ->  125.87
1163         {148350, 148360, 148500, 1000, 1001},   //148.5Mhz  ->  148.3516
1164         {167830, 167840, 168000, 1000, 1001},   //168Mhz    ->  167.83
1165         {222520, 222530, 222750, 1000, 1001},   //222.75Mhz ->  222.527
1166         {257140, 257150, 257400, 1000, 1001},   //257.4Mhz  ->  257.1429
1167         {296700, 296710, 297000, 1000, 1001},   //297Mhz    ->  296.7033
1168         {342850, 342860, 343200, 1000, 1001},   //343.2Mhz  ->  342.857
1169         {395600, 395610, 396000, 1000, 1001},   //396Mhz    ->  395.6
1170         {409090, 409100, 409500, 1000, 1001},   //409.5Mhz  ->  409.091
1171         {445050, 445060, 445500, 1000, 1001},   //445.5Mhz  ->  445.055
1172         {467530, 467540, 468000, 1000, 1001},   //468Mhz    ->  467.5325
1173         {519230, 519240, 519750, 1000, 1001},   //519.75Mhz ->  519.231
1174         {525970, 525980, 526500, 1000, 1001},   //526.5Mhz  ->  525.974
1175         {545450, 545460, 546000, 1000, 1001},   //546Mhz    ->  545.455
1176         {593400, 593410, 594000, 1000, 1001},   //594Mhz    ->  593.4066
1177         {623370, 623380, 624000, 1000, 1001},   //624Mhz    ->  623.377
1178         {692300, 692310, 693000, 1000, 1001},   //693Mhz    ->  692.308
1179         {701290, 701300, 702000, 1000, 1001},   //702Mhz    ->  701.2987
1180         {791200, 791210, 792000, 1000, 1001},   //792Mhz    ->  791.209
1181         {890100, 890110, 891000, 1000, 1001},   //891Mhz    ->  890.1099
1182         {1186810, 1186820, 1188000, 1000, 1001},//1188Mhz   -> 1186.8131
1183
1184         // *1.001 rates
1185         {27020, 27030, 27000, 1001, 1000}, //27Mhz
1186         {54050, 54060, 54000, 1001, 1000}, //54Mhz
1187         {108100, 108110, 108000, 1001, 1000},//108Mhz
1188 };
1189
1190 const struct pixel_rate_range_table_entry *look_up_in_video_optimized_rate_tlb(
1191                 unsigned int pixel_rate_khz)
1192 {
1193         int i;
1194
1195         for (i = 0; i < NUM_ELEMENTS(video_optimized_pixel_rates); i++) {
1196                 const struct pixel_rate_range_table_entry *e = &video_optimized_pixel_rates[i];
1197
1198                 if (e->range_min_khz <= pixel_rate_khz && pixel_rate_khz <= e->range_max_khz) {
1199                         return e;
1200                 }
1201         }
1202
1203         return NULL;
1204 }
1205
1206 static bool dcn20_program_pix_clk(
1207                 struct clock_source *clock_source,
1208                 struct pixel_clk_params *pix_clk_params,
1209                 enum dp_link_encoding encoding,
1210                 struct pll_settings *pll_settings)
1211 {
1212         struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
1213         unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
1214
1215         dce112_program_pix_clk(clock_source, pix_clk_params, encoding, pll_settings);
1216
1217         if (clock_source->ctx->dc->hwss.enable_vblanks_synchronization &&
1218                         clock_source->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0) {
1219                 /* NOTE: In case VBLANK syncronization is enabled,
1220                  * we need to set modulo to default DPREFCLK first
1221                  * dce112_program_pix_clk does not set default DPREFCLK
1222                  */
1223                 REG_WRITE(MODULO[inst],
1224                         clock_source->ctx->dc->clk_mgr->dprefclk_khz*1000);
1225         }
1226         return true;
1227 }
1228
1229 static bool dcn20_override_dp_pix_clk(
1230                 struct clock_source *clock_source,
1231                 unsigned int inst,
1232                 unsigned int pixel_clk,
1233                 unsigned int ref_clk)
1234 {
1235         struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
1236
1237         REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 0);
1238         REG_WRITE(PHASE[inst], pixel_clk);
1239         REG_WRITE(MODULO[inst], ref_clk);
1240         REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);
1241         return true;
1242 }
1243
1244 static const struct clock_source_funcs dcn20_clk_src_funcs = {
1245         .cs_power_down = dce110_clock_source_power_down,
1246         .program_pix_clk = dcn20_program_pix_clk,
1247         .get_pix_clk_dividers = dce112_get_pix_clk_dividers,
1248         .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz,
1249         .override_dp_pix_clk = dcn20_override_dp_pix_clk
1250 };
1251
1252 static bool dcn3_program_pix_clk(
1253                 struct clock_source *clock_source,
1254                 struct pixel_clk_params *pix_clk_params,
1255                 enum dp_link_encoding encoding,
1256                 struct pll_settings *pll_settings)
1257 {
1258         struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
1259         unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
1260         unsigned int dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz;
1261         const struct pixel_rate_range_table_entry *e =
1262                         look_up_in_video_optimized_rate_tlb(pix_clk_params->requested_pix_clk_100hz / 10);
1263
1264         // For these signal types Driver to program DP_DTO without calling VBIOS Command table
1265         if (dc_is_dp_signal(pix_clk_params->signal_type)) {
1266                 if (e) {
1267                         /* Set DTO values: phase = target clock, modulo = reference clock*/
1268                         REG_WRITE(PHASE[inst], e->target_pixel_rate_khz * e->mult_factor);
1269                         REG_WRITE(MODULO[inst], dp_dto_ref_khz * e->div_factor);
1270                 } else {
1271                         /* Set DTO values: phase = target clock, modulo = reference clock*/
1272                         REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100);
1273                         REG_WRITE(MODULO[inst], dp_dto_ref_khz * 1000);
1274                 }
1275                 REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);
1276         } else
1277                 // For other signal types(HDMI_TYPE_A, DVI) Driver still to call VBIOS Command table
1278                 dce112_program_pix_clk(clock_source, pix_clk_params, encoding, pll_settings);
1279
1280         return true;
1281 }
1282
1283 static uint32_t dcn3_get_pix_clk_dividers(
1284                 struct clock_source *cs,
1285                 struct pixel_clk_params *pix_clk_params,
1286                 struct pll_settings *pll_settings)
1287 {
1288         unsigned long long actual_pix_clk_100Hz = pix_clk_params ? pix_clk_params->requested_pix_clk_100hz : 0;
1289
1290         DC_LOGGER_INIT();
1291
1292         if (pix_clk_params == NULL || pll_settings == NULL
1293                         || pix_clk_params->requested_pix_clk_100hz == 0) {
1294                 DC_LOG_ERROR(
1295                         "%s: Invalid parameters!!\n", __func__);
1296                 return -1;
1297         }
1298
1299         memset(pll_settings, 0, sizeof(*pll_settings));
1300         /* Adjust for HDMI Type A deep color */
1301         if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) {
1302                 switch (pix_clk_params->color_depth) {
1303                 case COLOR_DEPTH_101010:
1304                         actual_pix_clk_100Hz = (actual_pix_clk_100Hz * 5) >> 2;
1305                         break;
1306                 case COLOR_DEPTH_121212:
1307                         actual_pix_clk_100Hz = (actual_pix_clk_100Hz * 6) >> 2;
1308                         break;
1309                 case COLOR_DEPTH_161616:
1310                         actual_pix_clk_100Hz = actual_pix_clk_100Hz * 2;
1311                         break;
1312                 default:
1313                         break;
1314                 }
1315         }
1316         pll_settings->actual_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz;
1317         pll_settings->adjusted_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz;
1318         pll_settings->calculated_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz;
1319
1320         return 0;
1321 }
1322
1323 static const struct clock_source_funcs dcn3_clk_src_funcs = {
1324         .cs_power_down = dce110_clock_source_power_down,
1325         .program_pix_clk = dcn3_program_pix_clk,
1326         .get_pix_clk_dividers = dcn3_get_pix_clk_dividers,
1327         .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz
1328 };
1329
1330 static const struct clock_source_funcs dcn31_clk_src_funcs = {
1331         .cs_power_down = dce110_clock_source_power_down,
1332         .program_pix_clk = dcn31_program_pix_clk,
1333         .get_pix_clk_dividers = dcn3_get_pix_clk_dividers,
1334         .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz
1335 };
1336
1337 /*****************************************/
1338 /* Constructor                           */
1339 /*****************************************/
1340
1341 static const struct clock_source_funcs dce112_clk_src_funcs = {
1342         .cs_power_down = dce110_clock_source_power_down,
1343         .program_pix_clk = dce112_program_pix_clk,
1344         .get_pix_clk_dividers = dce112_get_pix_clk_dividers,
1345         .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz
1346 };
1347 static const struct clock_source_funcs dce110_clk_src_funcs = {
1348         .cs_power_down = dce110_clock_source_power_down,
1349         .program_pix_clk = dce110_program_pix_clk,
1350         .get_pix_clk_dividers = dce110_get_pix_clk_dividers,
1351         .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz
1352 };
1353
1354
1355 static void get_ss_info_from_atombios(
1356                 struct dce110_clk_src *clk_src,
1357                 enum as_signal_type as_signal,
1358                 struct spread_spectrum_data *spread_spectrum_data[],
1359                 uint32_t *ss_entries_num)
1360 {
1361         enum bp_result bp_result = BP_RESULT_FAILURE;
1362         struct spread_spectrum_info *ss_info;
1363         struct spread_spectrum_data *ss_data;
1364         struct spread_spectrum_info *ss_info_cur;
1365         struct spread_spectrum_data *ss_data_cur;
1366         uint32_t i;
1367         DC_LOGGER_INIT();
1368         if (ss_entries_num == NULL) {
1369                 DC_LOG_SYNC(
1370                         "Invalid entry !!!\n");
1371                 return;
1372         }
1373         if (spread_spectrum_data == NULL) {
1374                 DC_LOG_SYNC(
1375                         "Invalid array pointer!!!\n");
1376                 return;
1377         }
1378
1379         spread_spectrum_data[0] = NULL;
1380         *ss_entries_num = 0;
1381
1382         *ss_entries_num = clk_src->bios->funcs->get_ss_entry_number(
1383                         clk_src->bios,
1384                         as_signal);
1385
1386         if (*ss_entries_num == 0)
1387                 return;
1388
1389         ss_info = kcalloc(*ss_entries_num,
1390                           sizeof(struct spread_spectrum_info),
1391                           GFP_KERNEL);
1392         ss_info_cur = ss_info;
1393         if (ss_info == NULL)
1394                 return;
1395
1396         ss_data = kcalloc(*ss_entries_num,
1397                           sizeof(struct spread_spectrum_data),
1398                           GFP_KERNEL);
1399         if (ss_data == NULL)
1400                 goto out_free_info;
1401
1402         for (i = 0, ss_info_cur = ss_info;
1403                 i < (*ss_entries_num);
1404                 ++i, ++ss_info_cur) {
1405
1406                 bp_result = clk_src->bios->funcs->get_spread_spectrum_info(
1407                                 clk_src->bios,
1408                                 as_signal,
1409                                 i,
1410                                 ss_info_cur);
1411
1412                 if (bp_result != BP_RESULT_OK)
1413                         goto out_free_data;
1414         }
1415
1416         for (i = 0, ss_info_cur = ss_info, ss_data_cur = ss_data;
1417                 i < (*ss_entries_num);
1418                 ++i, ++ss_info_cur, ++ss_data_cur) {
1419
1420                 if (ss_info_cur->type.STEP_AND_DELAY_INFO != false) {
1421                         DC_LOG_SYNC(
1422                                 "Invalid ATOMBIOS SS Table!!!\n");
1423                         goto out_free_data;
1424                 }
1425
1426                 /* for HDMI check SS percentage,
1427                  * if it is > 6 (0.06%), the ATOMBIOS table info is invalid*/
1428                 if (as_signal == AS_SIGNAL_TYPE_HDMI
1429                                 && ss_info_cur->spread_spectrum_percentage > 6){
1430                         /* invalid input, do nothing */
1431                         DC_LOG_SYNC(
1432                                 "Invalid SS percentage ");
1433                         DC_LOG_SYNC(
1434                                 "for HDMI in ATOMBIOS info Table!!!\n");
1435                         continue;
1436                 }
1437                 if (ss_info_cur->spread_percentage_divider == 1000) {
1438                         /* Keep previous precision from ATOMBIOS for these
1439                         * in case new precision set by ATOMBIOS for these
1440                         * (otherwise all code in DCE specific classes
1441                         * for all previous ASICs would need
1442                         * to be updated for SS calculations,
1443                         * Audio SS compensation and DP DTO SS compensation
1444                         * which assumes fixed SS percentage Divider = 100)*/
1445                         ss_info_cur->spread_spectrum_percentage /= 10;
1446                         ss_info_cur->spread_percentage_divider = 100;
1447                 }
1448
1449                 ss_data_cur->freq_range_khz = ss_info_cur->target_clock_range;
1450                 ss_data_cur->percentage =
1451                                 ss_info_cur->spread_spectrum_percentage;
1452                 ss_data_cur->percentage_divider =
1453                                 ss_info_cur->spread_percentage_divider;
1454                 ss_data_cur->modulation_freq_hz =
1455                                 ss_info_cur->spread_spectrum_range;
1456
1457                 if (ss_info_cur->type.CENTER_MODE)
1458                         ss_data_cur->flags.CENTER_SPREAD = 1;
1459
1460                 if (ss_info_cur->type.EXTERNAL)
1461                         ss_data_cur->flags.EXTERNAL_SS = 1;
1462
1463         }
1464
1465         *spread_spectrum_data = ss_data;
1466         kfree(ss_info);
1467         return;
1468
1469 out_free_data:
1470         kfree(ss_data);
1471         *ss_entries_num = 0;
1472 out_free_info:
1473         kfree(ss_info);
1474 }
1475
1476 static void ss_info_from_atombios_create(
1477         struct dce110_clk_src *clk_src)
1478 {
1479         get_ss_info_from_atombios(
1480                 clk_src,
1481                 AS_SIGNAL_TYPE_DISPLAY_PORT,
1482                 &clk_src->dp_ss_params,
1483                 &clk_src->dp_ss_params_cnt);
1484         get_ss_info_from_atombios(
1485                 clk_src,
1486                 AS_SIGNAL_TYPE_HDMI,
1487                 &clk_src->hdmi_ss_params,
1488                 &clk_src->hdmi_ss_params_cnt);
1489         get_ss_info_from_atombios(
1490                 clk_src,
1491                 AS_SIGNAL_TYPE_DVI,
1492                 &clk_src->dvi_ss_params,
1493                 &clk_src->dvi_ss_params_cnt);
1494         get_ss_info_from_atombios(
1495                 clk_src,
1496                 AS_SIGNAL_TYPE_LVDS,
1497                 &clk_src->lvds_ss_params,
1498                 &clk_src->lvds_ss_params_cnt);
1499 }
1500
1501 static bool calc_pll_max_vco_construct(
1502                         struct calc_pll_clock_source *calc_pll_cs,
1503                         struct calc_pll_clock_source_init_data *init_data)
1504 {
1505         uint32_t i;
1506         struct dc_firmware_info *fw_info;
1507         if (calc_pll_cs == NULL ||
1508                         init_data == NULL ||
1509                         init_data->bp == NULL)
1510                 return false;
1511
1512         if (!init_data->bp->fw_info_valid)
1513                 return false;
1514
1515         fw_info = &init_data->bp->fw_info;
1516         calc_pll_cs->ctx = init_data->ctx;
1517         calc_pll_cs->ref_freq_khz = fw_info->pll_info.crystal_frequency;
1518         calc_pll_cs->min_vco_khz =
1519                         fw_info->pll_info.min_output_pxl_clk_pll_frequency;
1520         calc_pll_cs->max_vco_khz =
1521                         fw_info->pll_info.max_output_pxl_clk_pll_frequency;
1522
1523         if (init_data->max_override_input_pxl_clk_pll_freq_khz != 0)
1524                 calc_pll_cs->max_pll_input_freq_khz =
1525                         init_data->max_override_input_pxl_clk_pll_freq_khz;
1526         else
1527                 calc_pll_cs->max_pll_input_freq_khz =
1528                         fw_info->pll_info.max_input_pxl_clk_pll_frequency;
1529
1530         if (init_data->min_override_input_pxl_clk_pll_freq_khz != 0)
1531                 calc_pll_cs->min_pll_input_freq_khz =
1532                         init_data->min_override_input_pxl_clk_pll_freq_khz;
1533         else
1534                 calc_pll_cs->min_pll_input_freq_khz =
1535                         fw_info->pll_info.min_input_pxl_clk_pll_frequency;
1536
1537         calc_pll_cs->min_pix_clock_pll_post_divider =
1538                         init_data->min_pix_clk_pll_post_divider;
1539         calc_pll_cs->max_pix_clock_pll_post_divider =
1540                         init_data->max_pix_clk_pll_post_divider;
1541         calc_pll_cs->min_pll_ref_divider =
1542                         init_data->min_pll_ref_divider;
1543         calc_pll_cs->max_pll_ref_divider =
1544                         init_data->max_pll_ref_divider;
1545
1546         if (init_data->num_fract_fb_divider_decimal_point == 0 ||
1547                 init_data->num_fract_fb_divider_decimal_point_precision >
1548                                 init_data->num_fract_fb_divider_decimal_point) {
1549                 DC_LOG_ERROR(
1550                         "The dec point num or precision is incorrect!");
1551                 return false;
1552         }
1553         if (init_data->num_fract_fb_divider_decimal_point_precision == 0) {
1554                 DC_LOG_ERROR(
1555                         "Incorrect fract feedback divider precision num!");
1556                 return false;
1557         }
1558
1559         calc_pll_cs->fract_fb_divider_decimal_points_num =
1560                                 init_data->num_fract_fb_divider_decimal_point;
1561         calc_pll_cs->fract_fb_divider_precision =
1562                         init_data->num_fract_fb_divider_decimal_point_precision;
1563         calc_pll_cs->fract_fb_divider_factor = 1;
1564         for (i = 0; i < calc_pll_cs->fract_fb_divider_decimal_points_num; ++i)
1565                 calc_pll_cs->fract_fb_divider_factor *= 10;
1566
1567         calc_pll_cs->fract_fb_divider_precision_factor = 1;
1568         for (
1569                 i = 0;
1570                 i < (calc_pll_cs->fract_fb_divider_decimal_points_num -
1571                                 calc_pll_cs->fract_fb_divider_precision);
1572                 ++i)
1573                 calc_pll_cs->fract_fb_divider_precision_factor *= 10;
1574
1575         return true;
1576 }
1577
1578 bool dce110_clk_src_construct(
1579         struct dce110_clk_src *clk_src,
1580         struct dc_context *ctx,
1581         struct dc_bios *bios,
1582         enum clock_source_id id,
1583         const struct dce110_clk_src_regs *regs,
1584         const struct dce110_clk_src_shift *cs_shift,
1585         const struct dce110_clk_src_mask *cs_mask)
1586 {
1587         struct calc_pll_clock_source_init_data calc_pll_cs_init_data_hdmi;
1588         struct calc_pll_clock_source_init_data calc_pll_cs_init_data;
1589
1590         clk_src->base.ctx = ctx;
1591         clk_src->bios = bios;
1592         clk_src->base.id = id;
1593         clk_src->base.funcs = &dce110_clk_src_funcs;
1594
1595         clk_src->regs = regs;
1596         clk_src->cs_shift = cs_shift;
1597         clk_src->cs_mask = cs_mask;
1598
1599         if (!clk_src->bios->fw_info_valid) {
1600                 ASSERT_CRITICAL(false);
1601                 goto unexpected_failure;
1602         }
1603
1604         clk_src->ext_clk_khz = clk_src->bios->fw_info.external_clock_source_frequency_for_dp;
1605
1606         /* structure normally used with PLL ranges from ATOMBIOS; DS on by default */
1607         calc_pll_cs_init_data.bp = bios;
1608         calc_pll_cs_init_data.min_pix_clk_pll_post_divider = 1;
1609         calc_pll_cs_init_data.max_pix_clk_pll_post_divider =
1610                         clk_src->cs_mask->PLL_POST_DIV_PIXCLK;
1611         calc_pll_cs_init_data.min_pll_ref_divider =     1;
1612         calc_pll_cs_init_data.max_pll_ref_divider =     clk_src->cs_mask->PLL_REF_DIV;
1613         /* when 0 use minInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
1614         calc_pll_cs_init_data.min_override_input_pxl_clk_pll_freq_khz = 0;
1615         /* when 0 use maxInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
1616         calc_pll_cs_init_data.max_override_input_pxl_clk_pll_freq_khz = 0;
1617         /*numberOfFractFBDividerDecimalPoints*/
1618         calc_pll_cs_init_data.num_fract_fb_divider_decimal_point =
1619                         FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM;
1620         /*number of decimal point to round off for fractional feedback divider value*/
1621         calc_pll_cs_init_data.num_fract_fb_divider_decimal_point_precision =
1622                         FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM;
1623         calc_pll_cs_init_data.ctx =     ctx;
1624
1625         /*structure for HDMI, no SS or SS% <= 0.06% for 27 MHz Ref clock */
1626         calc_pll_cs_init_data_hdmi.bp = bios;
1627         calc_pll_cs_init_data_hdmi.min_pix_clk_pll_post_divider = 1;
1628         calc_pll_cs_init_data_hdmi.max_pix_clk_pll_post_divider =
1629                         clk_src->cs_mask->PLL_POST_DIV_PIXCLK;
1630         calc_pll_cs_init_data_hdmi.min_pll_ref_divider = 1;
1631         calc_pll_cs_init_data_hdmi.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV;
1632         /* when 0 use minInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
1633         calc_pll_cs_init_data_hdmi.min_override_input_pxl_clk_pll_freq_khz = 13500;
1634         /* when 0 use maxInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
1635         calc_pll_cs_init_data_hdmi.max_override_input_pxl_clk_pll_freq_khz = 27000;
1636         /*numberOfFractFBDividerDecimalPoints*/
1637         calc_pll_cs_init_data_hdmi.num_fract_fb_divider_decimal_point =
1638                         FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM;
1639         /*number of decimal point to round off for fractional feedback divider value*/
1640         calc_pll_cs_init_data_hdmi.num_fract_fb_divider_decimal_point_precision =
1641                         FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM;
1642         calc_pll_cs_init_data_hdmi.ctx = ctx;
1643
1644         clk_src->ref_freq_khz = clk_src->bios->fw_info.pll_info.crystal_frequency;
1645
1646         if (clk_src->base.id == CLOCK_SOURCE_ID_EXTERNAL)
1647                 return true;
1648
1649         /* PLL only from here on */
1650         ss_info_from_atombios_create(clk_src);
1651
1652         if (!calc_pll_max_vco_construct(
1653                         &clk_src->calc_pll,
1654                         &calc_pll_cs_init_data)) {
1655                 ASSERT_CRITICAL(false);
1656                 goto unexpected_failure;
1657         }
1658
1659
1660         calc_pll_cs_init_data_hdmi.
1661                         min_override_input_pxl_clk_pll_freq_khz = clk_src->ref_freq_khz/2;
1662         calc_pll_cs_init_data_hdmi.
1663                         max_override_input_pxl_clk_pll_freq_khz = clk_src->ref_freq_khz;
1664
1665
1666         if (!calc_pll_max_vco_construct(
1667                         &clk_src->calc_pll_hdmi, &calc_pll_cs_init_data_hdmi)) {
1668                 ASSERT_CRITICAL(false);
1669                 goto unexpected_failure;
1670         }
1671
1672         return true;
1673
1674 unexpected_failure:
1675         return false;
1676 }
1677
1678 bool dce112_clk_src_construct(
1679         struct dce110_clk_src *clk_src,
1680         struct dc_context *ctx,
1681         struct dc_bios *bios,
1682         enum clock_source_id id,
1683         const struct dce110_clk_src_regs *regs,
1684         const struct dce110_clk_src_shift *cs_shift,
1685         const struct dce110_clk_src_mask *cs_mask)
1686 {
1687         clk_src->base.ctx = ctx;
1688         clk_src->bios = bios;
1689         clk_src->base.id = id;
1690         clk_src->base.funcs = &dce112_clk_src_funcs;
1691
1692         clk_src->regs = regs;
1693         clk_src->cs_shift = cs_shift;
1694         clk_src->cs_mask = cs_mask;
1695
1696         if (!clk_src->bios->fw_info_valid) {
1697                 ASSERT_CRITICAL(false);
1698                 return false;
1699         }
1700
1701         clk_src->ext_clk_khz = clk_src->bios->fw_info.external_clock_source_frequency_for_dp;
1702
1703         return true;
1704 }
1705
1706 bool dcn20_clk_src_construct(
1707         struct dce110_clk_src *clk_src,
1708         struct dc_context *ctx,
1709         struct dc_bios *bios,
1710         enum clock_source_id id,
1711         const struct dce110_clk_src_regs *regs,
1712         const struct dce110_clk_src_shift *cs_shift,
1713         const struct dce110_clk_src_mask *cs_mask)
1714 {
1715         bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask);
1716
1717         clk_src->base.funcs = &dcn20_clk_src_funcs;
1718
1719         return ret;
1720 }
1721
1722 bool dcn3_clk_src_construct(
1723         struct dce110_clk_src *clk_src,
1724         struct dc_context *ctx,
1725         struct dc_bios *bios,
1726         enum clock_source_id id,
1727         const struct dce110_clk_src_regs *regs,
1728         const struct dce110_clk_src_shift *cs_shift,
1729         const struct dce110_clk_src_mask *cs_mask)
1730 {
1731         bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask);
1732
1733         clk_src->base.funcs = &dcn3_clk_src_funcs;
1734
1735         return ret;
1736 }
1737
1738 bool dcn31_clk_src_construct(
1739         struct dce110_clk_src *clk_src,
1740         struct dc_context *ctx,
1741         struct dc_bios *bios,
1742         enum clock_source_id id,
1743         const struct dce110_clk_src_regs *regs,
1744         const struct dce110_clk_src_shift *cs_shift,
1745         const struct dce110_clk_src_mask *cs_mask)
1746 {
1747         bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask);
1748
1749         clk_src->base.funcs = &dcn31_clk_src_funcs;
1750
1751         return ret;
1752 }
1753
1754 bool dcn301_clk_src_construct(
1755         struct dce110_clk_src *clk_src,
1756         struct dc_context *ctx,
1757         struct dc_bios *bios,
1758         enum clock_source_id id,
1759         const struct dce110_clk_src_regs *regs,
1760         const struct dce110_clk_src_shift *cs_shift,
1761         const struct dce110_clk_src_mask *cs_mask)
1762 {
1763         bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask);
1764
1765         clk_src->base.funcs = &dcn3_clk_src_funcs;
1766
1767         return ret;
1768 }