2 * Copyright 2012-14 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #ifndef DC_INTERFACE_H_
27 #define DC_INTERFACE_H_
30 #include "grph_object_defs.h"
31 #include "logger_types.h"
32 #include "gpio_types.h"
33 #include "link_service_types.h"
34 #include "grph_object_ctrl_defs.h"
35 #include <inc/hw/opp.h>
37 #include "inc/hw_sequencer.h"
38 #include "inc/compressor.h"
39 #include "dml/display_mode_lib.h"
41 #define DC_VER "3.1.01"
43 #define MAX_SURFACES 3
45 #define MAX_SINKS_PER_LINK 4
48 /*******************************************************************************
49 * Display Core Interfaces
50 ******************************************************************************/
55 uint32_t max_slave_planes;
57 uint32_t max_downscale_ratio;
58 uint32_t i2c_speed_in_khz;
60 unsigned int max_cursor_size;
64 struct dc_dcc_surface_param {
65 struct dc_size surface_size;
66 enum surface_pixel_format format;
67 enum swizzle_mode_values swizzle_mode;
68 enum dc_scan_direction scan;
71 struct dc_dcc_setting {
72 unsigned int max_compressed_blk_size;
73 unsigned int max_uncompressed_blk_size;
74 bool independent_64b_blks;
77 struct dc_surface_dcc_cap {
80 struct dc_dcc_setting rgb;
84 struct dc_dcc_setting luma;
85 struct dc_dcc_setting chroma;
90 bool const_color_support;
93 struct dc_static_screen_events {
99 /* Forward declaration*/
101 struct dc_plane_state;
104 struct dc_cap_funcs {
105 bool (*get_dcc_compression_cap)(const struct dc *dc,
106 const struct dc_dcc_surface_param *input,
107 struct dc_surface_dcc_cap *output);
110 struct dc_stream_state_funcs {
111 bool (*adjust_vmin_vmax)(struct dc *dc,
112 struct dc_stream_state **stream,
116 bool (*get_crtc_position)(struct dc *dc,
117 struct dc_stream_state **stream,
120 unsigned int *nom_v_pos);
122 bool (*set_gamut_remap)(struct dc *dc,
123 const struct dc_stream_state *stream);
125 bool (*program_csc_matrix)(struct dc *dc,
126 struct dc_stream_state *stream);
128 void (*set_static_screen_events)(struct dc *dc,
129 struct dc_stream_state **stream,
131 const struct dc_static_screen_events *events);
133 void (*set_dither_option)(struct dc_stream_state *stream,
134 enum dc_dither_option option);
137 struct link_training_settings;
139 struct dc_link_funcs {
140 void (*set_drive_settings)(struct dc *dc,
141 struct link_training_settings *lt_settings,
142 const struct dc_link *link);
143 void (*perform_link_training)(struct dc *dc,
144 struct dc_link_settings *link_setting,
145 bool skip_video_pattern);
146 void (*set_preferred_link_settings)(struct dc *dc,
147 struct dc_link_settings *link_setting,
148 struct dc_link *link);
149 void (*enable_hpd)(const struct dc_link *link);
150 void (*disable_hpd)(const struct dc_link *link);
151 void (*set_test_pattern)(
152 struct dc_link *link,
153 enum dp_test_pattern test_pattern,
154 const struct link_training_settings *p_link_settings,
155 const unsigned char *p_custom_pattern,
156 unsigned int cust_pattern_size);
159 /* Structure to hold configuration flags set by dm at dc creation. */
162 bool disable_disp_pll_sharing;
166 bool surface_visual_confirm;
172 bool validation_trace;
173 bool disable_stutter;
175 bool disable_dfs_bypass;
176 bool disable_dpp_power_gate;
177 bool disable_hubp_power_gate;
178 bool disable_pplib_wm_range;
180 bool disable_pipe_split;
181 int sr_exit_time_dpm0_ns;
182 int sr_enter_plus_exit_time_dpm0_ns;
184 int sr_enter_plus_exit_time_ns;
185 int urgent_latency_ns;
186 int percent_of_ideal_drambw;
187 int dram_clock_change_latency_ns;
189 bool disable_pplib_clock_request;
190 bool disable_clock_gate;
193 bool force_abm_enable;
196 struct resource_pool;
200 struct dc_cap_funcs cap_funcs;
201 struct dc_stream_state_funcs stream_funcs;
202 struct dc_link_funcs link_funcs;
203 struct dc_config config;
204 struct dc_debug debug;
206 struct dc_context *ctx;
209 struct dc_link *links[MAX_PIPES * 2];
211 struct dc_state *current_state;
212 struct resource_pool *res_pool;
214 /* Display Engine Clock levels */
215 struct dm_pp_clock_levels sclk_lvls;
217 /* Inputs into BW and WM calculations. */
218 struct bw_calcs_dceip *bw_dceip;
219 struct bw_calcs_vbios *bw_vbios;
220 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
221 struct dcn_soc_bounding_box *dcn_soc;
222 struct dcn_ip_params *dcn_ip;
223 struct display_mode_lib dml;
227 struct hw_sequencer_funcs hwss;
228 struct dce_hwseq *hwseq;
230 /* temp store of dm_pp_display_configuration
231 * to compare to see if display config changed
233 struct dm_pp_display_configuration prev_display_config;
237 struct compressor *fbc_compressor;
241 enum frame_buffer_mode {
242 FRAME_BUFFER_MODE_LOCAL_ONLY = 0,
243 FRAME_BUFFER_MODE_ZFB_ONLY,
244 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL,
247 struct dchub_init_data {
248 int64_t zfb_phys_addr_base;
249 int64_t zfb_mc_base_addr;
250 uint64_t zfb_size_in_byte;
251 enum frame_buffer_mode fb_mode;
252 bool dchub_initialzied;
253 bool dchub_info_valid;
256 struct dc_init_data {
257 struct hw_asic_id asic_id;
258 void *driver; /* ctx */
259 struct cgs_device *cgs_device;
261 int num_virtual_links;
263 * If 'vbios_override' not NULL, it will be called instead
264 * of the real VBIOS. Intended use is Diagnostics on FPGA.
266 struct dc_bios *vbios_override;
267 enum dce_environment dce_environment;
269 struct dc_config flags;
271 uint64_t fbc_gpu_addr;
275 struct dc *dc_create(const struct dc_init_data *init_params);
277 void dc_destroy(struct dc **dc);
279 bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data);
281 void dc_log_hw_state(struct dc *dc);
283 /*******************************************************************************
285 ******************************************************************************/
288 TRANSFER_FUNC_POINTS = 1025
291 struct dc_hdr_static_metadata {
292 /* display chromaticities and white point in units of 0.00001 */
293 unsigned int chromaticity_green_x;
294 unsigned int chromaticity_green_y;
295 unsigned int chromaticity_blue_x;
296 unsigned int chromaticity_blue_y;
297 unsigned int chromaticity_red_x;
298 unsigned int chromaticity_red_y;
299 unsigned int chromaticity_white_point_x;
300 unsigned int chromaticity_white_point_y;
302 uint32_t min_luminance;
303 uint32_t max_luminance;
304 uint32_t maximum_content_light_level;
305 uint32_t maximum_frame_average_light_level;
311 enum dc_transfer_func_type {
313 TF_TYPE_DISTRIBUTED_POINTS,
317 struct dc_transfer_func_distributed_points {
318 struct fixed31_32 red[TRANSFER_FUNC_POINTS];
319 struct fixed31_32 green[TRANSFER_FUNC_POINTS];
320 struct fixed31_32 blue[TRANSFER_FUNC_POINTS];
322 uint16_t end_exponent;
323 uint16_t x_point_at_y1_red;
324 uint16_t x_point_at_y1_green;
325 uint16_t x_point_at_y1_blue;
328 enum dc_transfer_func_predefined {
329 TRANSFER_FUNCTION_SRGB,
330 TRANSFER_FUNCTION_BT709,
331 TRANSFER_FUNCTION_PQ,
332 TRANSFER_FUNCTION_LINEAR,
335 struct dc_transfer_func {
336 struct dc_transfer_func_distributed_points tf_pts;
337 enum dc_transfer_func_type type;
338 enum dc_transfer_func_predefined tf;
339 struct dc_context *ctx;
344 * This structure is filled in by dc_surface_get_status and contains
345 * the last requested address and the currently active address so the called
346 * can determine if there are any outstanding flips
348 struct dc_plane_status {
349 struct dc_plane_address requested_address;
350 struct dc_plane_address current_address;
351 bool is_flip_pending;
355 struct dc_plane_state {
356 struct dc_plane_address address;
357 struct scaling_taps scaling_quality;
358 struct rect src_rect;
359 struct rect dst_rect;
360 struct rect clip_rect;
362 union plane_size plane_size;
363 union dc_tiling_info tiling_info;
365 struct dc_plane_dcc_param dcc;
366 struct dc_hdr_static_metadata hdr_static_ctx;
368 struct dc_gamma *gamma_correction;
369 struct dc_transfer_func *in_transfer_func;
371 enum dc_color_space color_space;
372 enum surface_pixel_format format;
373 enum dc_rotation_angle rotation;
374 enum plane_stereo_format stereo_format;
376 bool per_pixel_alpha;
379 bool horizontal_mirror;
381 /* private to DC core */
382 struct dc_plane_status status;
383 struct dc_context *ctx;
385 /* private to dc_surface.c */
386 enum dc_irq_source irq_source;
390 struct dc_plane_info {
391 union plane_size plane_size;
392 union dc_tiling_info tiling_info;
393 struct dc_plane_dcc_param dcc;
394 enum surface_pixel_format format;
395 enum dc_rotation_angle rotation;
396 enum plane_stereo_format stereo_format;
397 enum dc_color_space color_space; /*todo: wrong place, fits in scaling info*/
398 bool horizontal_mirror;
400 bool per_pixel_alpha;
403 struct dc_scaling_info {
404 struct rect src_rect;
405 struct rect dst_rect;
406 struct rect clip_rect;
407 struct scaling_taps scaling_quality;
410 struct dc_surface_update {
411 struct dc_plane_state *surface;
413 /* isr safe update parameters. null means no updates */
414 struct dc_flip_addrs *flip_addr;
415 struct dc_plane_info *plane_info;
416 struct dc_scaling_info *scaling_info;
417 /* following updates require alloc/sleep/spin that is not isr safe,
418 * null means no updates
420 /* gamma TO BE REMOVED */
421 struct dc_gamma *gamma;
422 struct dc_transfer_func *in_transfer_func;
423 struct dc_hdr_static_metadata *hdr_static_metadata;
427 * Create a new surface with default parameters;
429 struct dc_plane_state *dc_create_plane_state(struct dc *dc);
430 const struct dc_plane_status *dc_plane_get_status(
431 const struct dc_plane_state *plane_state);
433 void dc_plane_state_retain(struct dc_plane_state *plane_state);
434 void dc_plane_state_release(struct dc_plane_state *plane_state);
436 void dc_gamma_retain(struct dc_gamma *dc_gamma);
437 void dc_gamma_release(struct dc_gamma **dc_gamma);
438 struct dc_gamma *dc_create_gamma(void);
440 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf);
441 void dc_transfer_func_release(struct dc_transfer_func *dc_tf);
442 struct dc_transfer_func *dc_create_transfer_func(void);
445 * This structure holds a surface address. There could be multiple addresses
446 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such
447 * as frame durations and DCC format can also be set.
449 struct dc_flip_addrs {
450 struct dc_plane_address address;
452 /* TODO: add flip duration for FreeSync */
456 * Set up surface attributes and associate to a stream
457 * The surfaces parameter is an absolute set of all surface active for the stream.
458 * If no surfaces are provided, the stream will be blanked; no memory read.
459 * Any flip related attribute changes must be done through this interface.
462 * Surfaces attributes are programmed and configured to be composed into stream.
463 * This does not trigger a flip. No surface address is programmed.
466 bool dc_commit_planes_to_stream(
468 struct dc_plane_state **plane_states,
469 uint8_t new_plane_count,
470 struct dc_stream_state *stream);
472 bool dc_post_update_surfaces_to_stream(
475 /* Surface update type is used by dc_update_surfaces_and_stream
476 * The update type is determined at the very beginning of the function based
477 * on parameters passed in and decides how much programming (or updating) is
478 * going to be done during the call.
480 * UPDATE_TYPE_FAST is used for really fast updates that do not require much
481 * logical calculations or hardware register programming. This update MUST be
482 * ISR safe on windows. Currently fast update will only be used to flip surface
485 * UPDATE_TYPE_MED is used for slower updates which require significant hw
486 * re-programming however do not affect bandwidth consumption or clock
487 * requirements. At present, this is the level at which front end updates
488 * that do not require us to run bw_calcs happen. These are in/out transfer func
489 * updates, viewport offset changes, recout size changes and pixel depth changes.
490 * This update can be done at ISR, but we want to minimize how often this happens.
492 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our
493 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front
494 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or
495 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do
496 * a full update. This cannot be done at ISR level and should be a rare event.
497 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting
498 * underscan we don't expect to see this call at all.
501 enum surface_update_type {
502 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
503 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/
504 UPDATE_TYPE_FULL, /* may need to shuffle resources */
507 /*******************************************************************************
509 ******************************************************************************/
511 struct dc_stream_status {
512 int primary_otg_inst;
515 struct dc_plane_state *plane_states[MAX_SURFACE_NUM];
518 * link this stream passes through
520 struct dc_link *link;
523 struct dc_stream_state {
524 struct dc_sink *sink;
525 struct dc_crtc_timing timing;
527 struct rect src; /* composition area */
528 struct rect dst; /* stream addressable area */
530 struct audio_info audio_info;
532 struct freesync_context freesync_ctx;
534 struct dc_transfer_func *out_transfer_func;
535 struct colorspace_transform gamut_remap_matrix;
536 struct csc_transform csc_color_matrix;
538 enum signal_type output_signal;
540 enum dc_color_space output_color_space;
541 enum dc_dither_option dither_option;
543 enum view_3d_format view_format;
545 bool ignore_msa_timing_param;
546 /* TODO: custom INFO packets */
547 /* TODO: ABM info (DMCU) */
551 /* from core_stream struct */
552 struct dc_context *ctx;
554 /* used by DCP and FMT */
555 struct bit_depth_reduction_params bit_depth_params;
556 struct clamping_and_pixel_encoding_params clamping;
559 enum signal_type signal;
561 struct dc_stream_status status;
563 /* from stream struct */
567 struct dc_stream_update {
570 struct dc_transfer_func *out_transfer_func;
573 bool dc_is_stream_unchanged(
574 struct dc_stream_state *old_stream, struct dc_stream_state *stream);
577 * Setup stream attributes if no stream updates are provided
578 * there will be no impact on the stream parameters
580 * Set up surface attributes and associate to a stream
581 * The surfaces parameter is an absolute set of all surface active for the stream.
582 * If no surfaces are provided, the stream will be blanked; no memory read.
583 * Any flip related attribute changes must be done through this interface.
586 * Surfaces attributes are programmed and configured to be composed into stream.
587 * This does not trigger a flip. No surface address is programmed.
591 void dc_update_planes_and_stream(struct dc *dc,
592 struct dc_surface_update *surface_updates, int surface_count,
593 struct dc_stream_state *dc_stream,
594 struct dc_stream_update *stream_update);
597 * Log the current stream state.
600 const struct dc_stream_state *stream,
601 struct dal_logger *dc_logger,
602 enum dc_log_type log_type);
604 uint8_t dc_get_current_stream_count(struct dc *dc);
605 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i);
608 * Return the current frame counter.
610 uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream);
612 /* TODO: Return parsed values rather than direct register read
613 * This has a dependency on the caller (amdgpu_get_crtc_scanoutpos)
614 * being refactored properly to be dce-specific
616 bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
617 uint32_t *v_blank_start,
618 uint32_t *v_blank_end,
619 uint32_t *h_position,
620 uint32_t *v_position);
622 bool dc_add_stream_to_ctx(
624 struct dc_state *new_ctx,
625 struct dc_stream_state *stream);
627 bool dc_remove_stream_from_ctx(
629 struct dc_state *new_ctx,
630 struct dc_stream_state *stream);
633 bool dc_add_plane_to_context(
635 struct dc_stream_state *stream,
636 struct dc_plane_state *plane_state,
637 struct dc_state *context);
639 bool dc_remove_plane_from_context(
641 struct dc_stream_state *stream,
642 struct dc_plane_state *plane_state,
643 struct dc_state *context);
645 bool dc_rem_all_planes_for_stream(
647 struct dc_stream_state *stream,
648 struct dc_state *context);
650 bool dc_add_all_planes_for_stream(
652 struct dc_stream_state *stream,
653 struct dc_plane_state * const *plane_states,
655 struct dc_state *context);
658 * Structure to store surface/stream associations for validation
660 struct dc_validation_set {
661 struct dc_stream_state *stream;
662 struct dc_plane_state *plane_states[MAX_SURFACES];
666 bool dc_validate_stream(struct dc *dc, struct dc_stream_state *stream);
668 bool dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
670 bool dc_validate_global_state(
672 struct dc_state *new_ctx);
675 * This function takes a stream and checks if it is guaranteed to be supported.
676 * Guaranteed means that MAX_COFUNC similar streams are supported.
679 * No hardware is programmed for call. Only validation is done.
683 void dc_resource_state_construct(
685 struct dc_state *dst_ctx);
687 void dc_resource_state_copy_construct(
688 const struct dc_state *src_ctx,
689 struct dc_state *dst_ctx);
691 void dc_resource_state_copy_construct_current(
693 struct dc_state *dst_ctx);
695 void dc_resource_state_destruct(struct dc_state *context);
698 * TODO update to make it about validation sets
699 * Set up streams and links associated to drive sinks
700 * The streams parameter is an absolute set of all active streams.
703 * Phy, Encoder, Timing Generator are programmed and enabled.
704 * New streams are enabled with blank stream; no memory read.
706 bool dc_commit_state(struct dc *dc, struct dc_state *context);
709 * Set up streams and links associated to drive sinks
710 * The streams parameter is an absolute set of all active streams.
713 * Phy, Encoder, Timing Generator are programmed and enabled.
714 * New streams are enabled with blank stream; no memory read.
717 * Enable stereo when commit_streams is not required,
718 * for example, frame alternate.
720 bool dc_enable_stereo(
722 struct dc_state *context,
723 struct dc_stream_state *streams[],
724 uint8_t stream_count);
727 * Create a new default stream for the requested sink
729 struct dc_stream_state *dc_create_stream_for_sink(struct dc_sink *dc_sink);
731 void dc_stream_retain(struct dc_stream_state *dc_stream);
732 void dc_stream_release(struct dc_stream_state *dc_stream);
734 struct dc_stream_status *dc_stream_get_status(
735 struct dc_stream_state *dc_stream);
737 enum surface_update_type dc_check_update_surfaces_for_stream(
739 struct dc_surface_update *updates,
741 struct dc_stream_update *stream_update,
742 const struct dc_stream_status *stream_status);
745 struct dc_state *dc_create_state(void);
746 void dc_retain_state(struct dc_state *context);
747 void dc_release_state(struct dc_state *context);
749 /*******************************************************************************
751 ******************************************************************************/
754 union dpcd_rev dpcd_rev;
755 union max_lane_count max_ln_count;
756 union max_down_spread max_down_spread;
758 /* dongle type (DP converter, CV smart dongle) */
759 enum display_dongle_type dongle_type;
760 /* Dongle's downstream count. */
761 union sink_count sink_count;
762 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
763 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
764 struct dc_dongle_caps dongle_caps;
766 uint32_t sink_dev_id;
767 uint32_t branch_dev_id;
768 int8_t branch_dev_name[6];
769 int8_t branch_hw_revision;
771 bool allow_invalid_MSA_timing_param;
773 bool dpcd_display_control_capable;
776 struct dc_link_status {
777 struct dpcd_caps *dpcd_caps;
780 /* DP MST stream allocation (payload bandwidth number) */
781 struct link_mst_stream_allocation {
783 const struct stream_encoder *stream_enc;
784 /* associate DRM payload table with DC stream encoder */
786 /* number of slots required for the DP stream in transport packet */
790 /* DP MST stream allocation table */
791 struct link_mst_stream_allocation_table {
792 /* number of DP video streams */
794 /* array of stream allocations */
795 struct link_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM];
799 * A link contains one or more sinks and their connected status.
800 * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported.
803 struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK];
804 unsigned int sink_count;
805 struct dc_sink *local_sink;
806 unsigned int link_index;
807 enum dc_connection_type type;
808 enum signal_type connector_signal;
809 enum dc_irq_source irq_source_hpd;
810 enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */
811 /* caps is the same as reported_link_cap. link_traing use
812 * reported_link_cap. Will clean up. TODO
814 struct dc_link_settings reported_link_cap;
815 struct dc_link_settings verified_link_cap;
816 struct dc_link_settings cur_link_settings;
817 struct dc_lane_settings cur_lane_setting;
818 struct dc_link_settings preferred_link_setting;
824 uint8_t link_enc_hw_inst;
826 bool test_pattern_enabled;
827 union compliance_test_state compliance_test_state;
831 struct ddc_service *ddc;
835 /* Private to DC core */
839 struct dc_context *ctx;
841 struct link_encoder *link_enc;
842 struct graphics_object_id link_id;
843 union ddi_channel_mapping ddi_channel_mapping;
844 struct connector_device_tag_info device_tag;
845 struct dpcd_caps dpcd_caps;
846 unsigned short chip_caps;
847 unsigned int dpcd_sink_count;
848 enum edp_revision edp_revision;
851 /* MST record stream using this link */
853 bool dp_keep_receiver_powered;
855 struct link_mst_stream_allocation_table mst_stream_alloc_table;
857 struct dc_link_status link_status;
861 const struct dc_link_status *dc_link_get_status(const struct dc_link *dc_link);
864 * Return an enumerated dc_link. dc_link order is constant and determined at
865 * boot time. They cannot be created or destroyed.
866 * Use dc_get_caps() to get number of links.
868 struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index);
870 /* Set backlight level of an embedded panel (eDP, LVDS). */
871 bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level,
872 uint32_t frame_ramp, const struct dc_stream_state *stream);
874 bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable);
876 bool dc_link_get_psr_state(const struct dc_link *dc_link, uint32_t *psr_state);
878 bool dc_link_setup_psr(struct dc_link *dc_link,
879 const struct dc_stream_state *stream, struct psr_config *psr_config,
880 struct psr_context *psr_context);
882 /* Request DC to detect if there is a Panel connected.
883 * boot - If this call is during initial boot.
884 * Return false for any type of detection failure or MST detection
885 * true otherwise. True meaning further action is required (status update
886 * and OS notification).
888 bool dc_link_detect(struct dc_link *dc_link, bool boot);
890 /* Notify DC about DP RX Interrupt (aka Short Pulse Interrupt).
892 * true - Downstream port status changed. DM should call DC to do the
894 * false - no change in Downstream port status. No further action required
896 bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link,
897 union hpd_irq_data *hpd_irq_dpcd_data);
899 struct dc_sink_init_data;
901 struct dc_sink *dc_link_add_remote_sink(
902 struct dc_link *dc_link,
905 struct dc_sink_init_data *init_data);
907 void dc_link_remove_remote_sink(
908 struct dc_link *link,
909 struct dc_sink *sink);
911 /* Used by diagnostics for virtual link at the moment */
913 void dc_link_dp_set_drive_settings(
914 struct dc_link *link,
915 struct link_training_settings *lt_settings);
917 enum link_training_result dc_link_dp_perform_link_training(
918 struct dc_link *link,
919 const struct dc_link_settings *link_setting,
920 bool skip_video_pattern);
922 void dc_link_dp_enable_hpd(const struct dc_link *link);
924 void dc_link_dp_disable_hpd(const struct dc_link *link);
926 bool dc_link_dp_set_test_pattern(
927 struct dc_link *link,
928 enum dp_test_pattern test_pattern,
929 const struct link_training_settings *p_link_settings,
930 const unsigned char *p_custom_pattern,
931 unsigned int cust_pattern_size);
933 /*******************************************************************************
934 * Sink Interfaces - A sink corresponds to a display output device
935 ******************************************************************************/
937 struct dc_container_id {
938 // 128bit GUID in binary form
939 unsigned char guid[16];
940 // 8 byte port ID -> ELD.PortID
941 unsigned int portId[2];
942 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName
943 unsigned short manufacturerName;
944 // 2 byte product code -> ELD.ProductCode
945 unsigned short productCode;
951 * The sink structure contains EDID and other display device properties
954 enum signal_type sink_signal;
955 struct dc_edid dc_edid; /* raw edid */
956 struct dc_edid_caps edid_caps; /* parse display caps */
957 struct dc_container_id *dc_container_id;
958 uint32_t dongle_max_pix_clk;
960 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
961 bool converter_disable_audio;
963 /* private to DC core */
964 struct dc_link *link;
965 struct dc_context *ctx;
967 /* private to dc_sink.c */
971 void dc_sink_retain(struct dc_sink *sink);
972 void dc_sink_release(struct dc_sink *sink);
974 struct dc_sink_init_data {
975 enum signal_type sink_signal;
976 struct dc_link *link;
977 uint32_t dongle_max_pix_clk;
978 bool converter_disable_audio;
981 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
983 /*******************************************************************************
984 * Cursor interfaces - To manages the cursor within a stream
985 ******************************************************************************/
986 /* TODO: Deprecated once we switch to dc_set_cursor_position */
987 bool dc_stream_set_cursor_attributes(
988 const struct dc_stream_state *stream,
989 const struct dc_cursor_attributes *attributes);
991 bool dc_stream_set_cursor_position(
992 struct dc_stream_state *stream,
993 const struct dc_cursor_position *position);
995 /* Newer interfaces */
997 struct dc_plane_address address;
998 struct dc_cursor_attributes attributes;
1001 /*******************************************************************************
1002 * Interrupt interfaces
1003 ******************************************************************************/
1004 enum dc_irq_source dc_interrupt_to_irq_source(
1008 void dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
1009 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
1010 enum dc_irq_source dc_get_hpd_irq_source_at_index(
1011 struct dc *dc, uint32_t link_index);
1013 /*******************************************************************************
1015 ******************************************************************************/
1017 void dc_set_power_state(
1019 enum dc_acpi_cm_power_state power_state);
1020 void dc_resume(struct dc *dc);
1023 * DPCD access interfaces
1028 uint32_t link_index,
1029 struct i2c_command *cmd);
1032 #endif /* DC_INTERFACE_H_ */