drivers/gpu/drm/amd/display/dc/core/dc_resource.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27
  28 #include "resource.h"
  29 #include "include/irq_service_interface.h"
  30 #include "link_encoder.h"
  31 #include "stream_encoder.h"
  32 #include "opp.h"
  33 #include "timing_generator.h"
  34 #include "transform.h"
  35 #include "dccg.h"
  36 #include "dchubbub.h"
  37 #include "dpp.h"
  38 #include "core_types.h"
  39 #include "set_mode_types.h"
  40 #include "virtual/virtual_stream_encoder.h"
  41 #include "dpcd_defs.h"
  42 #include "link_enc_cfg.h"
  43 #include "dc_link_dp.h"
  44 #include "virtual/virtual_link_hwss.h"
  45 #include "link/link_hwss_dio.h"
  46 #include "link/link_hwss_dpia.h"
  47 #include "link/link_hwss_hpo_dp.h"
  48
  49 #if defined(CONFIG_DRM_AMD_DC_SI)
  50 #include "dce60/dce60_resource.h"
  51 #endif
  52 #include "dce80/dce80_resource.h"
  53 #include "dce100/dce100_resource.h"
  54 #include "dce110/dce110_resource.h"
  55 #include "dce112/dce112_resource.h"
  56 #include "dce120/dce120_resource.h"
  57 #include "dcn10/dcn10_resource.h"
  58 #include "dcn20/dcn20_resource.h"
  59 #include "dcn21/dcn21_resource.h"
  60 #include "dcn201/dcn201_resource.h"
  61 #include "dcn30/dcn30_resource.h"
  62 #include "dcn301/dcn301_resource.h"
  63 #include "dcn302/dcn302_resource.h"
  64 #include "dcn303/dcn303_resource.h"
  65 #include "dcn31/dcn31_resource.h"
  66 #include "dcn314/dcn314_resource.h"
  67 #include "dcn315/dcn315_resource.h"
  68 #include "dcn316/dcn316_resource.h"
  69 #include "../dcn32/dcn32_resource.h"
  70 #include "../dcn321/dcn321_resource.h"
  71
  72 #define DC_LOGGER_INIT(logger)
  73
  74 enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
  75 {
  76         enum dce_version dc_version = DCE_VERSION_UNKNOWN;
  77
  78         switch (asic_id.chip_family) {
  79
  80 #if defined(CONFIG_DRM_AMD_DC_SI)
  81         case FAMILY_SI:
  82                 if (ASIC_REV_IS_TAHITI_P(asic_id.hw_internal_rev) ||
  83                     ASIC_REV_IS_PITCAIRN_PM(asic_id.hw_internal_rev) ||
  84                     ASIC_REV_IS_CAPEVERDE_M(asic_id.hw_internal_rev))
  85                         dc_version = DCE_VERSION_6_0;
  86                 else if (ASIC_REV_IS_OLAND_M(asic_id.hw_internal_rev))
  87                         dc_version = DCE_VERSION_6_4;
  88                 else
  89                         dc_version = DCE_VERSION_6_1;
  90                 break;
  91 #endif
  92         case FAMILY_CI:
  93                 dc_version = DCE_VERSION_8_0;
  94                 break;
  95         case FAMILY_KV:
  96                 if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) ||
  97                     ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) ||
  98                     ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev))
  99                         dc_version = DCE_VERSION_8_3;
 100                 else
 101                         dc_version = DCE_VERSION_8_1;
 102                 break;
 103         case FAMILY_CZ:
 104                 dc_version = DCE_VERSION_11_0;
 105                 break;
 106
 107         case FAMILY_VI:
 108                 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
 109                                 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
 110                         dc_version = DCE_VERSION_10_0;
 111                         break;
 112                 }
 113                 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
 114                                 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
 115                                 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
 116                         dc_version = DCE_VERSION_11_2;
 117                 }
 118                 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev))
 119                         dc_version = DCE_VERSION_11_22;
 120                 break;
 121         case FAMILY_AI:
 122                 if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev))
 123                         dc_version = DCE_VERSION_12_1;
 124                 else
 125                         dc_version = DCE_VERSION_12_0;
 126                 break;
 127         case FAMILY_RV:
 128                 dc_version = DCN_VERSION_1_0;
 129                 if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
 130                         dc_version = DCN_VERSION_1_01;
 131                 if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev))
 132                         dc_version = DCN_VERSION_2_1;
 133                 if (ASICREV_IS_GREEN_SARDINE(asic_id.hw_internal_rev))
 134                         dc_version = DCN_VERSION_2_1;
 135                 break;
 136
 137         case FAMILY_NV:
 138                 dc_version = DCN_VERSION_2_0;
 139                 if (asic_id.chip_id == DEVICE_ID_NV_13FE || asic_id.chip_id == DEVICE_ID_NV_143F) {
 140                         dc_version = DCN_VERSION_2_01;
 141                         break;
 142                 }
 143                 if (ASICREV_IS_SIENNA_CICHLID_P(asic_id.hw_internal_rev))
 144                         dc_version = DCN_VERSION_3_0;
 145                 if (ASICREV_IS_DIMGREY_CAVEFISH_P(asic_id.hw_internal_rev))
 146                         dc_version = DCN_VERSION_3_02;
 147                 if (ASICREV_IS_BEIGE_GOBY_P(asic_id.hw_internal_rev))
 148                         dc_version = DCN_VERSION_3_03;
 149                 break;
 150
 151         case FAMILY_VGH:
 152                 dc_version = DCN_VERSION_3_01;
 153                 break;
 154
 155         case FAMILY_YELLOW_CARP:
 156                 if (ASICREV_IS_YELLOW_CARP(asic_id.hw_internal_rev))
 157                         dc_version = DCN_VERSION_3_1;
 158                 break;
 159         case AMDGPU_FAMILY_GC_10_3_6:
 160                 if (ASICREV_IS_GC_10_3_6(asic_id.hw_internal_rev))
 161                         dc_version = DCN_VERSION_3_15;
 162                 break;
 163         case AMDGPU_FAMILY_GC_10_3_7:
 164                 if (ASICREV_IS_GC_10_3_7(asic_id.hw_internal_rev))
 165                         dc_version = DCN_VERSION_3_16;
 166                 break;
 167         case AMDGPU_FAMILY_GC_11_0_0:
 168                 dc_version = DCN_VERSION_3_2;
 169                 if (ASICREV_IS_GC_11_0_2(asic_id.hw_internal_rev))
 170                         dc_version = DCN_VERSION_3_21;
 171                 break;
 172         case AMDGPU_FAMILY_GC_11_0_2:
 173                 dc_version = DCN_VERSION_3_14;
 174                 break;
 175         default:
 176                 dc_version = DCE_VERSION_UNKNOWN;
 177                 break;
 178         }
 179         return dc_version;
 180 }
 181
 182 struct resource_pool *dc_create_resource_pool(struct dc  *dc,
 183                                               const struct dc_init_data *init_data,
 184                                               enum dce_version dc_version)
 185 {
 186         struct resource_pool *res_pool = NULL;
 187
 188         switch (dc_version) {
 189 #if defined(CONFIG_DRM_AMD_DC_SI)
 190         case DCE_VERSION_6_0:
 191                 res_pool = dce60_create_resource_pool(
 192                         init_data->num_virtual_links, dc);
 193                 break;
 194         case DCE_VERSION_6_1:
 195                 res_pool = dce61_create_resource_pool(
 196                         init_data->num_virtual_links, dc);
 197                 break;
 198         case DCE_VERSION_6_4:
 199                 res_pool = dce64_create_resource_pool(
 200                         init_data->num_virtual_links, dc);
 201                 break;
 202 #endif
 203         case DCE_VERSION_8_0:
 204                 res_pool = dce80_create_resource_pool(
 205                                 init_data->num_virtual_links, dc);
 206                 break;
 207         case DCE_VERSION_8_1:
 208                 res_pool = dce81_create_resource_pool(
 209                                 init_data->num_virtual_links, dc);
 210                 break;
 211         case DCE_VERSION_8_3:
 212                 res_pool = dce83_create_resource_pool(
 213                                 init_data->num_virtual_links, dc);
 214                 break;
 215         case DCE_VERSION_10_0:
 216                 res_pool = dce100_create_resource_pool(
 217                                 init_data->num_virtual_links, dc);
 218                 break;
 219         case DCE_VERSION_11_0:
 220                 res_pool = dce110_create_resource_pool(
 221                                 init_data->num_virtual_links, dc,
 222                                 init_data->asic_id);
 223                 break;
 224         case DCE_VERSION_11_2:
 225         case DCE_VERSION_11_22:
 226                 res_pool = dce112_create_resource_pool(
 227                                 init_data->num_virtual_links, dc);
 228                 break;
 229         case DCE_VERSION_12_0:
 230         case DCE_VERSION_12_1:
 231                 res_pool = dce120_create_resource_pool(
 232                                 init_data->num_virtual_links, dc);
 233                 break;
 234
 235 #if defined(CONFIG_DRM_AMD_DC_DCN)
 236         case DCN_VERSION_1_0:
 237         case DCN_VERSION_1_01:
 238                 res_pool = dcn10_create_resource_pool(init_data, dc);
 239                 break;
 240         case DCN_VERSION_2_0:
 241                 res_pool = dcn20_create_resource_pool(init_data, dc);
 242                 break;
 243         case DCN_VERSION_2_1:
 244                 res_pool = dcn21_create_resource_pool(init_data, dc);
 245                 break;
 246         case DCN_VERSION_2_01:
 247                 res_pool = dcn201_create_resource_pool(init_data, dc);
 248                 break;
 249         case DCN_VERSION_3_0:
 250                 res_pool = dcn30_create_resource_pool(init_data, dc);
 251                 break;
 252         case DCN_VERSION_3_01:
 253                 res_pool = dcn301_create_resource_pool(init_data, dc);
 254                 break;
 255         case DCN_VERSION_3_02:
 256                 res_pool = dcn302_create_resource_pool(init_data, dc);
 257                 break;
 258         case DCN_VERSION_3_03:
 259                 res_pool = dcn303_create_resource_pool(init_data, dc);
 260                 break;
 261         case DCN_VERSION_3_1:
 262                 res_pool = dcn31_create_resource_pool(init_data, dc);
 263                 break;
 264         case DCN_VERSION_3_14:
 265                 res_pool = dcn314_create_resource_pool(init_data, dc);
 266                 break;
 267         case DCN_VERSION_3_15:
 268                 res_pool = dcn315_create_resource_pool(init_data, dc);
 269                 break;
 270         case DCN_VERSION_3_16:
 271                 res_pool = dcn316_create_resource_pool(init_data, dc);
 272                 break;
 273         case DCN_VERSION_3_2:
 274                 res_pool = dcn32_create_resource_pool(init_data, dc);
 275                 break;
 276         case DCN_VERSION_3_21:
 277                 res_pool = dcn321_create_resource_pool(init_data, dc);
 278                 break;
 279 #endif
 280         default:
 281                 break;
 282         }
 283
 284         if (res_pool != NULL) {
 285                 if (dc->ctx->dc_bios->fw_info_valid) {
 286                         res_pool->ref_clocks.xtalin_clock_inKhz =
 287                                 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
 288                         /* initialize with firmware data first, no all
 289                          * ASIC have DCCG SW component. FPGA or
 290                          * simulation need initialization of
 291                          * dccg_ref_clock_inKhz, dchub_ref_clock_inKhz
 292                          * with xtalin_clock_inKhz
 293                          */
 294                         res_pool->ref_clocks.dccg_ref_clock_inKhz =
 295                                 res_pool->ref_clocks.xtalin_clock_inKhz;
 296                         res_pool->ref_clocks.dchub_ref_clock_inKhz =
 297                                 res_pool->ref_clocks.xtalin_clock_inKhz;
 298                 } else
 299                         ASSERT_CRITICAL(false);
 300         }
 301
 302         return res_pool;
 303 }
 304
 305 void dc_destroy_resource_pool(struct dc  *dc)
 306 {
 307         if (dc) {
 308                 if (dc->res_pool)
 309                         dc->res_pool->funcs->destroy(&dc->res_pool);
 310
 311                 kfree(dc->hwseq);
 312         }
 313 }
 314
 315 static void update_num_audio(
 316         const struct resource_straps *straps,
 317         unsigned int *num_audio,
 318         struct audio_support *aud_support)
 319 {
 320         aud_support->dp_audio = true;
 321         aud_support->hdmi_audio_native = false;
 322         aud_support->hdmi_audio_on_dongle = false;
 323
 324         if (straps->hdmi_disable == 0) {
 325                 if (straps->dc_pinstraps_audio & 0x2) {
 326                         aud_support->hdmi_audio_on_dongle = true;
 327                         aud_support->hdmi_audio_native = true;
 328                 }
 329         }
 330
 331         switch (straps->audio_stream_number) {
 332         case 0: /* multi streams supported */
 333                 break;
 334         case 1: /* multi streams not supported */
 335                 *num_audio = 1;
 336                 break;
 337         default:
 338                 DC_ERR("DC: unexpected audio fuse!\n");
 339         }
 340 }
 341
 342 bool resource_construct(
 343         unsigned int num_virtual_links,
 344         struct dc  *dc,
 345         struct resource_pool *pool,
 346         const struct resource_create_funcs *create_funcs)
 347 {
 348         struct dc_context *ctx = dc->ctx;
 349         const struct resource_caps *caps = pool->res_cap;
 350         int i;
 351         unsigned int num_audio = caps->num_audio;
 352         struct resource_straps straps = {0};
 353
 354         if (create_funcs->read_dce_straps)
 355                 create_funcs->read_dce_straps(dc->ctx, &straps);
 356
 357         pool->audio_count = 0;
 358         if (create_funcs->create_audio) {
 359                 /* find the total number of streams available via the
 360                  * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
 361                  * registers (one for each pin) starting from pin 1
 362                  * up to the max number of audio pins.
 363                  * We stop on the first pin where
 364                  * PORT_CONNECTIVITY == 1 (as instructed by HW team).
 365                  */
 366                 update_num_audio(&straps, &num_audio, &pool->audio_support);
 367                 for (i = 0; i < caps->num_audio; i++) {
 368                         struct audio *aud = create_funcs->create_audio(ctx, i);
 369
 370                         if (aud == NULL) {
 371                                 DC_ERR("DC: failed to create audio!\n");
 372                                 return false;
 373                         }
 374                         if (!aud->funcs->endpoint_valid(aud)) {
 375                                 aud->funcs->destroy(&aud);
 376                                 break;
 377                         }
 378                         pool->audios[i] = aud;
 379                         pool->audio_count++;
 380                 }
 381         }
 382
 383         pool->stream_enc_count = 0;
 384         if (create_funcs->create_stream_encoder) {
 385                 for (i = 0; i < caps->num_stream_encoder; i++) {
 386                         pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx);
 387                         if (pool->stream_enc[i] == NULL)
 388                                 DC_ERR("DC: failed to create stream_encoder!\n");
 389                         pool->stream_enc_count++;
 390                 }
 391         }
 392
 393         pool->hpo_dp_stream_enc_count = 0;
 394         if (create_funcs->create_hpo_dp_stream_encoder) {
 395                 for (i = 0; i < caps->num_hpo_dp_stream_encoder; i++) {
 396                         pool->hpo_dp_stream_enc[i] = create_funcs->create_hpo_dp_stream_encoder(i+ENGINE_ID_HPO_DP_0, ctx);
 397                         if (pool->hpo_dp_stream_enc[i] == NULL)
 398                                 DC_ERR("DC: failed to create HPO DP stream encoder!\n");
 399                         pool->hpo_dp_stream_enc_count++;
 400
 401                 }
 402         }
 403
 404         pool->hpo_dp_link_enc_count = 0;
 405         if (create_funcs->create_hpo_dp_link_encoder) {
 406                 for (i = 0; i < caps->num_hpo_dp_link_encoder; i++) {
 407                         pool->hpo_dp_link_enc[i] = create_funcs->create_hpo_dp_link_encoder(i, ctx);
 408                         if (pool->hpo_dp_link_enc[i] == NULL)
 409                                 DC_ERR("DC: failed to create HPO DP link encoder!\n");
 410                         pool->hpo_dp_link_enc_count++;
 411                 }
 412         }
 413
 414         for (i = 0; i < caps->num_mpc_3dlut; i++) {
 415                 pool->mpc_lut[i] = dc_create_3dlut_func();
 416                 if (pool->mpc_lut[i] == NULL)
 417                         DC_ERR("DC: failed to create MPC 3dlut!\n");
 418                 pool->mpc_shaper[i] = dc_create_transfer_func();
 419                 if (pool->mpc_shaper[i] == NULL)
 420                         DC_ERR("DC: failed to create MPC shaper!\n");
 421         }
 422
 423         dc->caps.dynamic_audio = false;
 424         if (pool->audio_count < pool->stream_enc_count) {
 425                 dc->caps.dynamic_audio = true;
 426         }
 427         for (i = 0; i < num_virtual_links; i++) {
 428                 pool->stream_enc[pool->stream_enc_count] =
 429                         virtual_stream_encoder_create(
 430                                         ctx, ctx->dc_bios);
 431                 if (pool->stream_enc[pool->stream_enc_count] == NULL) {
 432                         DC_ERR("DC: failed to create stream_encoder!\n");
 433                         return false;
 434                 }
 435                 pool->stream_enc_count++;
 436         }
 437
 438         dc->hwseq = create_funcs->create_hwseq(ctx);
 439
 440         return true;
 441 }
 442 static int find_matching_clock_source(
 443                 const struct resource_pool *pool,
 444                 struct clock_source *clock_source)
 445 {
 446
 447         int i;
 448
 449         for (i = 0; i < pool->clk_src_count; i++) {
 450                 if (pool->clock_sources[i] == clock_source)
 451                         return i;
 452         }
 453         return -1;
 454 }
 455
 456 void resource_unreference_clock_source(
 457                 struct resource_context *res_ctx,
 458                 const struct resource_pool *pool,
 459                 struct clock_source *clock_source)
 460 {
 461         int i = find_matching_clock_source(pool, clock_source);
 462
 463         if (i > -1)
 464                 res_ctx->clock_source_ref_count[i]--;
 465
 466         if (pool->dp_clock_source == clock_source)
 467                 res_ctx->dp_clock_source_ref_count--;
 468 }
 469
 470 void resource_reference_clock_source(
 471                 struct resource_context *res_ctx,
 472                 const struct resource_pool *pool,
 473                 struct clock_source *clock_source)
 474 {
 475         int i = find_matching_clock_source(pool, clock_source);
 476
 477         if (i > -1)
 478                 res_ctx->clock_source_ref_count[i]++;
 479
 480         if (pool->dp_clock_source == clock_source)
 481                 res_ctx->dp_clock_source_ref_count++;
 482 }
 483
 484 int resource_get_clock_source_reference(
 485                 struct resource_context *res_ctx,
 486                 const struct resource_pool *pool,
 487                 struct clock_source *clock_source)
 488 {
 489         int i = find_matching_clock_source(pool, clock_source);
 490
 491         if (i > -1)
 492                 return res_ctx->clock_source_ref_count[i];
 493
 494         if (pool->dp_clock_source == clock_source)
 495                 return res_ctx->dp_clock_source_ref_count;
 496
 497         return -1;
 498 }
 499
 500 bool resource_are_vblanks_synchronizable(
 501         struct dc_stream_state *stream1,
 502         struct dc_stream_state *stream2)
 503 {
 504         uint32_t base60_refresh_rates[] = {10, 20, 5};
 505         uint8_t i;
 506         uint8_t rr_count = ARRAY_SIZE(base60_refresh_rates);
 507         uint64_t frame_time_diff;
 508
 509         if (stream1->ctx->dc->config.vblank_alignment_dto_params &&
 510                 stream1->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0 &&
 511                 dc_is_dp_signal(stream1->signal) &&
 512                 dc_is_dp_signal(stream2->signal) &&
 513                 false == stream1->has_non_synchronizable_pclk &&
 514                 false == stream2->has_non_synchronizable_pclk &&
 515                 stream1->timing.flags.VBLANK_SYNCHRONIZABLE &&
 516                 stream2->timing.flags.VBLANK_SYNCHRONIZABLE) {
 517                 /* disable refresh rates higher than 60Hz for now */
 518                 if (stream1->timing.pix_clk_100hz*100/stream1->timing.h_total/
 519                                 stream1->timing.v_total > 60)
 520                         return false;
 521                 if (stream2->timing.pix_clk_100hz*100/stream2->timing.h_total/
 522                                 stream2->timing.v_total > 60)
 523                         return false;
 524                 frame_time_diff = (uint64_t)10000 *
 525                         stream1->timing.h_total *
 526                         stream1->timing.v_total *
 527                         stream2->timing.pix_clk_100hz;
 528                 frame_time_diff = div_u64(frame_time_diff, stream1->timing.pix_clk_100hz);
 529                 frame_time_diff = div_u64(frame_time_diff, stream2->timing.h_total);
 530                 frame_time_diff = div_u64(frame_time_diff, stream2->timing.v_total);
 531                 for (i = 0; i < rr_count; i++) {
 532                         int64_t diff = (int64_t)div_u64(frame_time_diff * base60_refresh_rates[i], 10) - 10000;
 533
 534                         if (diff < 0)
 535                                 diff = -diff;
 536                         if (diff < stream1->ctx->dc->config.vblank_alignment_max_frame_time_diff)
 537                                 return true;
 538                 }
 539         }
 540         return false;
 541 }
 542
 543 bool resource_are_streams_timing_synchronizable(
 544         struct dc_stream_state *stream1,
 545         struct dc_stream_state *stream2)
 546 {
 547         if (stream1->timing.h_total != stream2->timing.h_total)
 548                 return false;
 549
 550         if (stream1->timing.v_total != stream2->timing.v_total)
 551                 return false;
 552
 553         if (stream1->timing.h_addressable
 554                                 != stream2->timing.h_addressable)
 555                 return false;
 556
 557         if (stream1->timing.v_addressable
 558                                 != stream2->timing.v_addressable)
 559                 return false;
 560
 561         if (stream1->timing.v_front_porch
 562                                 != stream2->timing.v_front_porch)
 563                 return false;
 564
 565         if (stream1->timing.pix_clk_100hz
 566                                 != stream2->timing.pix_clk_100hz)
 567                 return false;
 568
 569         if (stream1->clamping.c_depth != stream2->clamping.c_depth)
 570                 return false;
 571
 572         if (stream1->phy_pix_clk != stream2->phy_pix_clk
 573                         && (!dc_is_dp_signal(stream1->signal)
 574                         || !dc_is_dp_signal(stream2->signal)))
 575                 return false;
 576
 577         if (stream1->view_format != stream2->view_format)
 578                 return false;
 579
 580         if (stream1->ignore_msa_timing_param || stream2->ignore_msa_timing_param)
 581                 return false;
 582
 583         return true;
 584 }
 585 static bool is_dp_and_hdmi_sharable(
 586                 struct dc_stream_state *stream1,
 587                 struct dc_stream_state *stream2)
 588 {
 589         if (stream1->ctx->dc->caps.disable_dp_clk_share)
 590                 return false;
 591
 592         if (stream1->clamping.c_depth != COLOR_DEPTH_888 ||
 593                 stream2->clamping.c_depth != COLOR_DEPTH_888)
 594                 return false;
 595
 596         return true;
 597
 598 }
 599
 600 static bool is_sharable_clk_src(
 601         const struct pipe_ctx *pipe_with_clk_src,
 602         const struct pipe_ctx *pipe)
 603 {
 604         if (pipe_with_clk_src->clock_source == NULL)
 605                 return false;
 606
 607         if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL)
 608                 return false;
 609
 610         if (dc_is_dp_signal(pipe_with_clk_src->stream->signal) ||
 611                 (dc_is_dp_signal(pipe->stream->signal) &&
 612                 !is_dp_and_hdmi_sharable(pipe_with_clk_src->stream,
 613                                      pipe->stream)))
 614                 return false;
 615
 616         if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal)
 617                         && dc_is_dual_link_signal(pipe->stream->signal))
 618                 return false;
 619
 620         if (dc_is_hdmi_signal(pipe->stream->signal)
 621                         && dc_is_dual_link_signal(pipe_with_clk_src->stream->signal))
 622                 return false;
 623
 624         if (!resource_are_streams_timing_synchronizable(
 625                         pipe_with_clk_src->stream, pipe->stream))
 626                 return false;
 627
 628         return true;
 629 }
 630
 631 struct clock_source *resource_find_used_clk_src_for_sharing(
 632                                         struct resource_context *res_ctx,
 633                                         struct pipe_ctx *pipe_ctx)
 634 {
 635         int i;
 636
 637         for (i = 0; i < MAX_PIPES; i++) {
 638                 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
 639                         return res_ctx->pipe_ctx[i].clock_source;
 640         }
 641
 642         return NULL;
 643 }
 644
 645 static enum pixel_format convert_pixel_format_to_dalsurface(
 646                 enum surface_pixel_format surface_pixel_format)
 647 {
 648         enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
 649
 650         switch (surface_pixel_format) {
 651         case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
 652                 dal_pixel_format = PIXEL_FORMAT_INDEX8;
 653                 break;
 654         case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
 655                 dal_pixel_format = PIXEL_FORMAT_RGB565;
 656                 break;
 657         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
 658                 dal_pixel_format = PIXEL_FORMAT_RGB565;
 659                 break;
 660         case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
 661                 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
 662                 break;
 663         case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
 664                 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
 665                 break;
 666         case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
 667                 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
 668                 break;
 669         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
 670                 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
 671                 break;
 672         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
 673                 dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS;
 674                 break;
 675         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 676         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
 677                 dal_pixel_format = PIXEL_FORMAT_FP16;
 678                 break;
 679         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
 680         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
 681                 dal_pixel_format = PIXEL_FORMAT_420BPP8;
 682                 break;
 683         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
 684         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
 685                 dal_pixel_format = PIXEL_FORMAT_420BPP10;
 686                 break;
 687         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
 688         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
 689         default:
 690                 dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
 691                 break;
 692         }
 693         return dal_pixel_format;
 694 }
 695
 696 static inline void get_vp_scan_direction(
 697         enum dc_rotation_angle rotation,
 698         bool horizontal_mirror,
 699         bool *orthogonal_rotation,
 700         bool *flip_vert_scan_dir,
 701         bool *flip_horz_scan_dir)
 702 {
 703         *orthogonal_rotation = false;
 704         *flip_vert_scan_dir = false;
 705         *flip_horz_scan_dir = false;
 706         if (rotation == ROTATION_ANGLE_180) {
 707                 *flip_vert_scan_dir = true;
 708                 *flip_horz_scan_dir = true;
 709         } else if (rotation == ROTATION_ANGLE_90) {
 710                 *orthogonal_rotation = true;
 711                 *flip_horz_scan_dir = true;
 712         } else if (rotation == ROTATION_ANGLE_270) {
 713                 *orthogonal_rotation = true;
 714                 *flip_vert_scan_dir = true;
 715         }
 716
 717         if (horizontal_mirror)
 718                 *flip_horz_scan_dir = !*flip_horz_scan_dir;
 719 }
 720
 721 int get_num_mpc_splits(struct pipe_ctx *pipe)
 722 {
 723         int mpc_split_count = 0;
 724         struct pipe_ctx *other_pipe = pipe->bottom_pipe;
 725
 726         while (other_pipe && other_pipe->plane_state == pipe->plane_state) {
 727                 mpc_split_count++;
 728                 other_pipe = other_pipe->bottom_pipe;
 729         }
 730         other_pipe = pipe->top_pipe;
 731         while (other_pipe && other_pipe->plane_state == pipe->plane_state) {
 732                 mpc_split_count++;
 733                 other_pipe = other_pipe->top_pipe;
 734         }
 735
 736         return mpc_split_count;
 737 }
 738
 739 int get_num_odm_splits(struct pipe_ctx *pipe)
 740 {
 741         int odm_split_count = 0;
 742         struct pipe_ctx *next_pipe = pipe->next_odm_pipe;
 743         while (next_pipe) {
 744                 odm_split_count++;
 745                 next_pipe = next_pipe->next_odm_pipe;
 746         }
 747         pipe = pipe->prev_odm_pipe;
 748         while (pipe) {
 749                 odm_split_count++;
 750                 pipe = pipe->prev_odm_pipe;
 751         }
 752         return odm_split_count;
 753 }
 754
 755 static void calculate_split_count_and_index(struct pipe_ctx *pipe_ctx, int *split_count, int *split_idx)
 756 {
 757         *split_count = get_num_odm_splits(pipe_ctx);
 758         *split_idx = 0;
 759         if (*split_count == 0) {
 760                 /*Check for mpc split*/
 761                 struct pipe_ctx *split_pipe = pipe_ctx->top_pipe;
 762
 763                 *split_count = get_num_mpc_splits(pipe_ctx);
 764                 while (split_pipe && split_pipe->plane_state == pipe_ctx->plane_state) {
 765                         (*split_idx)++;
 766                         split_pipe = split_pipe->top_pipe;
 767                 }
 768
 769                 /* MPO window on right side of ODM split */
 770                 if (split_pipe && split_pipe->prev_odm_pipe && !pipe_ctx->prev_odm_pipe)
 771                         (*split_idx)++;
 772         } else {
 773                 /*Get odm split index*/
 774                 struct pipe_ctx *split_pipe = pipe_ctx->prev_odm_pipe;
 775
 776                 while (split_pipe) {
 777                         (*split_idx)++;
 778                         split_pipe = split_pipe->prev_odm_pipe;
 779                 }
 780         }
 781 }
 782
 783 /*
 784  * This is a preliminary vp size calculation to allow us to check taps support.
 785  * The result is completely overridden afterwards.
 786  */
 787 static void calculate_viewport_size(struct pipe_ctx *pipe_ctx)
 788 {
 789         struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
 790
 791         data->viewport.width = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.horz, data->recout.width));
 792         data->viewport.height = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.vert, data->recout.height));
 793         data->viewport_c.width = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.horz_c, data->recout.width));
 794         data->viewport_c.height = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.vert_c, data->recout.height));
 795         if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
 796                         pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) {
 797                 swap(data->viewport.width, data->viewport.height);
 798                 swap(data->viewport_c.width, data->viewport_c.height);
 799         }
 800 }
 801
 802 static void calculate_recout(struct pipe_ctx *pipe_ctx)
 803 {
 804         const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
 805         const struct dc_stream_state *stream = pipe_ctx->stream;
 806         struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
 807         struct rect surf_clip = plane_state->clip_rect;
 808         bool split_tb = stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM;
 809         int split_count, split_idx;
 810
 811         calculate_split_count_and_index(pipe_ctx, &split_count, &split_idx);
 812         if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
 813                 split_idx = 0;
 814
 815         /*
 816          * Only the leftmost ODM pipe should be offset by a nonzero distance
 817          */
 818         if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->prev_odm_pipe && !pipe_ctx->prev_odm_pipe) {
 819                 /* MPO window on right side of ODM split */
 820                 data->recout.x = stream->dst.x + (surf_clip.x - stream->src.x - stream->src.width/2) *
 821                                 stream->dst.width / stream->src.width;
 822         } else if (!pipe_ctx->prev_odm_pipe || split_idx == split_count) {
 823                 data->recout.x = stream->dst.x;
 824                 if (stream->src.x < surf_clip.x)
 825                         data->recout.x += (surf_clip.x - stream->src.x) * stream->dst.width
 826                                                 / stream->src.width;
 827         } else
 828                 data->recout.x = 0;
 829
 830         if (stream->src.x > surf_clip.x)
 831                 surf_clip.width -= stream->src.x - surf_clip.x;
 832         data->recout.width = surf_clip.width * stream->dst.width / stream->src.width;
 833         if (data->recout.width + data->recout.x > stream->dst.x + stream->dst.width)
 834                 data->recout.width = stream->dst.x + stream->dst.width - data->recout.x;
 835
 836         data->recout.y = stream->dst.y;
 837         if (stream->src.y < surf_clip.y)
 838                 data->recout.y += (surf_clip.y - stream->src.y) * stream->dst.height
 839                                                 / stream->src.height;
 840         else if (stream->src.y > surf_clip.y)
 841                 surf_clip.height -= stream->src.y - surf_clip.y;
 842
 843         data->recout.height = surf_clip.height * stream->dst.height / stream->src.height;
 844         if (data->recout.height + data->recout.y > stream->dst.y + stream->dst.height)
 845                 data->recout.height = stream->dst.y + stream->dst.height - data->recout.y;
 846
 847         /* Handle h & v split */
 848         if (split_tb) {
 849                 ASSERT(data->recout.height % 2 == 0);
 850                 data->recout.height /= 2;
 851         } else if (split_count) {
 852                 if (!pipe_ctx->next_odm_pipe && !pipe_ctx->prev_odm_pipe) {
 853                         /* extra pixels in the division remainder need to go to pipes after
 854                          * the extra pixel index minus one(epimo) defined here as:
 855                          */
 856                         int epimo = split_count - data->recout.width % (split_count + 1);
 857
 858                         data->recout.x += (data->recout.width / (split_count + 1)) * split_idx;
 859                         if (split_idx > epimo)
 860                                 data->recout.x += split_idx - epimo - 1;
 861                         ASSERT(stream->view_format != VIEW_3D_FORMAT_SIDE_BY_SIDE || data->recout.width % 2 == 0);
 862                         data->recout.width = data->recout.width / (split_count + 1) + (split_idx > epimo ? 1 : 0);
 863                 } else {
 864                         /* odm */
 865                         if (split_idx == split_count) {
 866                                 /* rightmost pipe is the remainder recout */
 867                                 data->recout.width -= data->h_active * split_count - data->recout.x;
 868
 869                                 /* ODM combine cases with MPO we can get negative widths */
 870                                 if (data->recout.width < 0)
 871                                         data->recout.width = 0;
 872
 873                                 data->recout.x = 0;
 874                         } else
 875                                 data->recout.width = data->h_active - data->recout.x;
 876                 }
 877         }
 878 }
 879
 880 static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
 881 {
 882         const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
 883         const struct dc_stream_state *stream = pipe_ctx->stream;
 884         struct rect surf_src = plane_state->src_rect;
 885         const int in_w = stream->src.width;
 886         const int in_h = stream->src.height;
 887         const int out_w = stream->dst.width;
 888         const int out_h = stream->dst.height;
 889
 890         /*Swap surf_src height and width since scaling ratios are in recout rotation*/
 891         if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
 892                         pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
 893                 swap(surf_src.height, surf_src.width);
 894
 895         pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction(
 896                                         surf_src.width,
 897                                         plane_state->dst_rect.width);
 898         pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction(
 899                                         surf_src.height,
 900                                         plane_state->dst_rect.height);
 901
 902         if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
 903                 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2;
 904         else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
 905                 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2;
 906
 907         pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64(
 908                 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h);
 909         pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64(
 910                 pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w);
 911
 912         pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz;
 913         pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert;
 914
 915         if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8
 916                         || pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) {
 917                 pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2;
 918                 pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2;
 919         }
 920         pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_truncate(
 921                         pipe_ctx->plane_res.scl_data.ratios.horz, 19);
 922         pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_truncate(
 923                         pipe_ctx->plane_res.scl_data.ratios.vert, 19);
 924         pipe_ctx->plane_res.scl_data.ratios.horz_c = dc_fixpt_truncate(
 925                         pipe_ctx->plane_res.scl_data.ratios.horz_c, 19);
 926         pipe_ctx->plane_res.scl_data.ratios.vert_c = dc_fixpt_truncate(
 927                         pipe_ctx->plane_res.scl_data.ratios.vert_c, 19);
 928 }
 929
 930
 931 /*
 932  * We completely calculate vp offset, size and inits here based entirely on scaling
 933  * ratios and recout for pixel perfect pipe combine.
 934  */
 935 static void calculate_init_and_vp(
 936                 bool flip_scan_dir,
 937                 int recout_offset_within_recout_full,
 938                 int recout_size,
 939                 int src_size,
 940                 int taps,
 941                 struct fixed31_32 ratio,
 942                 struct fixed31_32 *init,
 943                 int *vp_offset,
 944                 int *vp_size)
 945 {
 946         struct fixed31_32 temp;
 947         int int_part;
 948
 949         /*
 950          * First of the taps starts sampling pixel number <init_int_part> corresponding to recout
 951          * pixel 1. Next recout pixel samples int part of <init + scaling ratio> and so on.
 952          * All following calculations are based on this logic.
 953          *
 954          * Init calculated according to formula:
 955          *      init = (scaling_ratio + number_of_taps + 1) / 2
 956          *      init_bot = init + scaling_ratio
 957          *      to get pixel perfect combine add the fraction from calculating vp offset
 958          */
 959         temp = dc_fixpt_mul_int(ratio, recout_offset_within_recout_full);
 960         *vp_offset = dc_fixpt_floor(temp);
 961         temp.value &= 0xffffffff;
 962         *init = dc_fixpt_truncate(dc_fixpt_add(dc_fixpt_div_int(
 963                         dc_fixpt_add_int(ratio, taps + 1), 2), temp), 19);
 964         /*
 965          * If viewport has non 0 offset and there are more taps than covered by init then
 966          * we should decrease the offset and increase init so we are never sampling
 967          * outside of viewport.
 968          */
 969         int_part = dc_fixpt_floor(*init);
 970         if (int_part < taps) {
 971                 int_part = taps - int_part;
 972                 if (int_part > *vp_offset)
 973                         int_part = *vp_offset;
 974                 *vp_offset -= int_part;
 975                 *init = dc_fixpt_add_int(*init, int_part);
 976         }
 977         /*
 978          * If taps are sampling outside of viewport at end of recout and there are more pixels
 979          * available in the surface we should increase the viewport size, regardless set vp to
 980          * only what is used.
 981          */
 982         temp = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_size - 1));
 983         *vp_size = dc_fixpt_floor(temp);
 984         if (*vp_size + *vp_offset > src_size)
 985                 *vp_size = src_size - *vp_offset;
 986
 987         /* We did all the math assuming we are scanning same direction as display does,
 988          * however mirror/rotation changes how vp scans vs how it is offset. If scan direction
 989          * is flipped we simply need to calculate offset from the other side of plane.
 990          * Note that outside of viewport all scaling hardware works in recout space.
 991          */
 992         if (flip_scan_dir)
 993                 *vp_offset = src_size - *vp_offset - *vp_size;
 994 }
 995
 996 static void calculate_inits_and_viewports(struct pipe_ctx *pipe_ctx)
 997 {
 998         const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
 999         const struct dc_stream_state *stream = pipe_ctx->stream;
1000         struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
1001         struct rect src = plane_state->src_rect;
1002         int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
1003                                 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
1004         int split_count, split_idx, ro_lb, ro_tb, recout_full_x, recout_full_y;
1005         bool orthogonal_rotation, flip_vert_scan_dir, flip_horz_scan_dir;
1006
1007         calculate_split_count_and_index(pipe_ctx, &split_count, &split_idx);
1008         /*
1009          * recout full is what the recout would have been if we didnt clip
1010          * the source plane at all. We only care about left(ro_lb) and top(ro_tb)
1011          * offsets of recout within recout full because those are the directions
1012          * we scan from and therefore the only ones that affect inits.
1013          */
1014         recout_full_x = stream->dst.x + (plane_state->dst_rect.x - stream->src.x)
1015                         * stream->dst.width / stream->src.width;
1016         recout_full_y = stream->dst.y + (plane_state->dst_rect.y - stream->src.y)
1017                         * stream->dst.height / stream->src.height;
1018         if (pipe_ctx->prev_odm_pipe && split_idx)
1019                 ro_lb = data->h_active * split_idx - recout_full_x;
1020         else if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->prev_odm_pipe)
1021                 ro_lb = data->h_active * split_idx - recout_full_x + data->recout.x;
1022         else
1023                 ro_lb = data->recout.x - recout_full_x;
1024         ro_tb = data->recout.y - recout_full_y;
1025         ASSERT(ro_lb >= 0 && ro_tb >= 0);
1026
1027         /*
1028          * Work in recout rotation since that requires less transformations
1029          */
1030         get_vp_scan_direction(
1031                         plane_state->rotation,
1032                         plane_state->horizontal_mirror,
1033                         &orthogonal_rotation,
1034                         &flip_vert_scan_dir,
1035                         &flip_horz_scan_dir);
1036
1037         if (orthogonal_rotation) {
1038                 swap(src.width, src.height);
1039                 swap(flip_vert_scan_dir, flip_horz_scan_dir);
1040         }
1041
1042         calculate_init_and_vp(
1043                         flip_horz_scan_dir,
1044                         ro_lb,
1045                         data->recout.width,
1046                         src.width,
1047                         data->taps.h_taps,
1048                         data->ratios.horz,
1049                         &data->inits.h,
1050                         &data->viewport.x,
1051                         &data->viewport.width);
1052         calculate_init_and_vp(
1053                         flip_horz_scan_dir,
1054                         ro_lb,
1055                         data->recout.width,
1056                         src.width / vpc_div,
1057                         data->taps.h_taps_c,
1058                         data->ratios.horz_c,
1059                         &data->inits.h_c,
1060                         &data->viewport_c.x,
1061                         &data->viewport_c.width);
1062         calculate_init_and_vp(
1063                         flip_vert_scan_dir,
1064                         ro_tb,
1065                         data->recout.height,
1066                         src.height,
1067                         data->taps.v_taps,
1068                         data->ratios.vert,
1069                         &data->inits.v,
1070                         &data->viewport.y,
1071                         &data->viewport.height);
1072         calculate_init_and_vp(
1073                         flip_vert_scan_dir,
1074                         ro_tb,
1075                         data->recout.height,
1076                         src.height / vpc_div,
1077                         data->taps.v_taps_c,
1078                         data->ratios.vert_c,
1079                         &data->inits.v_c,
1080                         &data->viewport_c.y,
1081                         &data->viewport_c.height);
1082         if (orthogonal_rotation) {
1083                 swap(data->viewport.x, data->viewport.y);
1084                 swap(data->viewport.width, data->viewport.height);
1085                 swap(data->viewport_c.x, data->viewport_c.y);
1086                 swap(data->viewport_c.width, data->viewport_c.height);
1087         }
1088         data->viewport.x += src.x;
1089         data->viewport.y += src.y;
1090         ASSERT(src.x % vpc_div == 0 && src.y % vpc_div == 0);
1091         data->viewport_c.x += src.x / vpc_div;
1092         data->viewport_c.y += src.y / vpc_div;
1093 }
1094
1095 bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
1096 {
1097         const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1098         struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
1099         bool res = false;
1100         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1101
1102         /* Invalid input */
1103         if (!plane_state->dst_rect.width ||
1104                         !plane_state->dst_rect.height ||
1105                         !plane_state->src_rect.width ||
1106                         !plane_state->src_rect.height) {
1107                 ASSERT(0);
1108                 return false;
1109         }
1110
1111         pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(
1112                         pipe_ctx->plane_state->format);
1113
1114         /* Timing borders are part of vactive that we are also supposed to skip in addition
1115          * to any stream dst offset. Since dm logic assumes dst is in addressable
1116          * space we need to add the left and top borders to dst offsets temporarily.
1117          * TODO: fix in DM, stream dst is supposed to be in vactive
1118          */
1119         pipe_ctx->stream->dst.x += timing->h_border_left;
1120         pipe_ctx->stream->dst.y += timing->v_border_top;
1121
1122         /* Calculate H and V active size */
1123         pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable +
1124                         timing->h_border_left + timing->h_border_right;
1125         pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable +
1126                 timing->v_border_top + timing->v_border_bottom;
1127         if (pipe_ctx->next_odm_pipe || pipe_ctx->prev_odm_pipe) {
1128                 pipe_ctx->plane_res.scl_data.h_active /= get_num_odm_splits(pipe_ctx) + 1;
1129
1130                 DC_LOG_SCALER("%s pipe %d: next_odm_pipe:%d   prev_odm_pipe:%d\n",
1131                                 __func__,
1132                                 pipe_ctx->pipe_idx,
1133                                 pipe_ctx->next_odm_pipe ? pipe_ctx->next_odm_pipe->pipe_idx : -1,
1134                                 pipe_ctx->prev_odm_pipe ? pipe_ctx->prev_odm_pipe->pipe_idx : -1);
1135         }       /* ODM + windows MPO, where window is on either right or left ODM half */
1136         else if (pipe_ctx->top_pipe && (pipe_ctx->top_pipe->next_odm_pipe || pipe_ctx->top_pipe->prev_odm_pipe)) {
1137
1138                 pipe_ctx->plane_res.scl_data.h_active /= get_num_odm_splits(pipe_ctx->top_pipe) + 1;
1139
1140                 DC_LOG_SCALER("%s ODM + windows MPO: pipe:%d top_pipe:%d   top_pipe->next_odm_pipe:%d   top_pipe->prev_odm_pipe:%d\n",
1141                                 __func__,
1142                                 pipe_ctx->pipe_idx,
1143                                 pipe_ctx->top_pipe->pipe_idx,
1144                                 pipe_ctx->top_pipe->next_odm_pipe ? pipe_ctx->top_pipe->next_odm_pipe->pipe_idx : -1,
1145                                 pipe_ctx->top_pipe->prev_odm_pipe ? pipe_ctx->top_pipe->prev_odm_pipe->pipe_idx : -1);
1146         }
1147         /* depends on h_active */
1148         calculate_recout(pipe_ctx);
1149         /* depends on pixel format */
1150         calculate_scaling_ratios(pipe_ctx);
1151         /* depends on scaling ratios and recout, does not calculate offset yet */
1152         calculate_viewport_size(pipe_ctx);
1153
1154         if (!pipe_ctx->stream->ctx->dc->config.enable_windowed_mpo_odm) {
1155                 /* Stopgap for validation of ODM + MPO on one side of screen case */
1156                 if (pipe_ctx->plane_res.scl_data.viewport.height < 1 ||
1157                                 pipe_ctx->plane_res.scl_data.viewport.width < 1)
1158                         return false;
1159         }
1160
1161         /*
1162          * LB calculations depend on vp size, h/v_active and scaling ratios
1163          * Setting line buffer pixel depth to 24bpp yields banding
1164          * on certain displays, such as the Sharp 4k. 36bpp is needed
1165          * to support SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 and
1166          * SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 with actual > 10 bpc
1167          * precision on DCN display engines, but apparently not for DCE, as
1168          * far as testing on DCE-11.2 and DCE-8 showed. Various DCE parts have
1169          * problems: Carrizo with DCE_VERSION_11_0 does not like 36 bpp lb depth,
1170          * neither do DCE-8 at 4k resolution, or DCE-11.2 (broken identify pixel
1171          * passthrough). Therefore only use 36 bpp on DCN where it is actually needed.
1172          */
1173         if (plane_state->ctx->dce_version > DCE_VERSION_MAX)
1174                 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_36BPP;
1175         else
1176                 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
1177
1178         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = plane_state->per_pixel_alpha;
1179
1180         if (pipe_ctx->plane_res.xfm != NULL)
1181                 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
1182                                 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
1183
1184         if (pipe_ctx->plane_res.dpp != NULL)
1185                 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
1186                                 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
1187
1188
1189         if (!res) {
1190                 /* Try 24 bpp linebuffer */
1191                 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;
1192
1193                 if (pipe_ctx->plane_res.xfm != NULL)
1194                         res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
1195                                         pipe_ctx->plane_res.xfm,
1196                                         &pipe_ctx->plane_res.scl_data,
1197                                         &plane_state->scaling_quality);
1198
1199                 if (pipe_ctx->plane_res.dpp != NULL)
1200                         res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
1201                                         pipe_ctx->plane_res.dpp,
1202                                         &pipe_ctx->plane_res.scl_data,
1203                                         &plane_state->scaling_quality);
1204         }
1205
1206         /*
1207          * Depends on recout, scaling ratios, h_active and taps
1208          * May need to re-check lb size after this in some obscure scenario
1209          */
1210         if (res)
1211                 calculate_inits_and_viewports(pipe_ctx);
1212
1213         /*
1214          * Handle side by side and top bottom 3d recout offsets after vp calculation
1215          * since 3d is special and needs to calculate vp as if there is no recout offset
1216          * This may break with rotation, good thing we aren't mixing hw rotation and 3d
1217          */
1218         if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->plane_state == plane_state) {
1219                 ASSERT(plane_state->rotation == ROTATION_ANGLE_0 ||
1220                         (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_TOP_AND_BOTTOM &&
1221                                 pipe_ctx->stream->view_format != VIEW_3D_FORMAT_SIDE_BY_SIDE));
1222                 if (pipe_ctx->stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
1223                         pipe_ctx->plane_res.scl_data.recout.y += pipe_ctx->plane_res.scl_data.recout.height;
1224                 else if (pipe_ctx->stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
1225                         pipe_ctx->plane_res.scl_data.recout.x += pipe_ctx->plane_res.scl_data.recout.width;
1226         }
1227
1228         if (!pipe_ctx->stream->ctx->dc->config.enable_windowed_mpo_odm) {
1229                 if (pipe_ctx->plane_res.scl_data.viewport.height < MIN_VIEWPORT_SIZE ||
1230                                 pipe_ctx->plane_res.scl_data.viewport.width < MIN_VIEWPORT_SIZE)
1231                         res = false;
1232         } else {
1233                 /* Clamp minimum viewport size */
1234                 if (pipe_ctx->plane_res.scl_data.viewport.height < MIN_VIEWPORT_SIZE)
1235                         pipe_ctx->plane_res.scl_data.viewport.height = MIN_VIEWPORT_SIZE;
1236                 if (pipe_ctx->plane_res.scl_data.viewport.width < MIN_VIEWPORT_SIZE)
1237                         pipe_ctx->plane_res.scl_data.viewport.width = MIN_VIEWPORT_SIZE;
1238         }
1239
1240         DC_LOG_SCALER("%s pipe %d:\nViewport: height:%d width:%d x:%d y:%d  Recout: height:%d width:%d x:%d y:%d  HACTIVE:%d VACTIVE:%d\n"
1241                         "src_rect: height:%d width:%d x:%d y:%d  dst_rect: height:%d width:%d x:%d y:%d  clip_rect: height:%d width:%d x:%d y:%d\n",
1242                         __func__,
1243                         pipe_ctx->pipe_idx,
1244                         pipe_ctx->plane_res.scl_data.viewport.height,
1245                         pipe_ctx->plane_res.scl_data.viewport.width,
1246                         pipe_ctx->plane_res.scl_data.viewport.x,
1247                         pipe_ctx->plane_res.scl_data.viewport.y,
1248                         pipe_ctx->plane_res.scl_data.recout.height,
1249                         pipe_ctx->plane_res.scl_data.recout.width,
1250                         pipe_ctx->plane_res.scl_data.recout.x,
1251                         pipe_ctx->plane_res.scl_data.recout.y,
1252                         pipe_ctx->plane_res.scl_data.h_active,
1253                         pipe_ctx->plane_res.scl_data.v_active,
1254                         plane_state->src_rect.height,
1255                         plane_state->src_rect.width,
1256                         plane_state->src_rect.x,
1257                         plane_state->src_rect.y,
1258                         plane_state->dst_rect.height,
1259                         plane_state->dst_rect.width,
1260                         plane_state->dst_rect.x,
1261                         plane_state->dst_rect.y,
1262                         plane_state->clip_rect.height,
1263                         plane_state->clip_rect.width,
1264                         plane_state->clip_rect.x,
1265                         plane_state->clip_rect.y);
1266
1267         pipe_ctx->stream->dst.x -= timing->h_border_left;
1268         pipe_ctx->stream->dst.y -= timing->v_border_top;
1269
1270         return res;
1271 }
1272
1273
1274 enum dc_status resource_build_scaling_params_for_context(
1275         const struct dc  *dc,
1276         struct dc_state *context)
1277 {
1278         int i;
1279
1280         for (i = 0; i < MAX_PIPES; i++) {
1281                 if (context->res_ctx.pipe_ctx[i].plane_state != NULL &&
1282                                 context->res_ctx.pipe_ctx[i].stream != NULL)
1283                         if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i]))
1284                                 return DC_FAIL_SCALING;
1285         }
1286
1287         return DC_OK;
1288 }
1289
1290 struct pipe_ctx *find_idle_secondary_pipe(
1291                 struct resource_context *res_ctx,
1292                 const struct resource_pool *pool,
1293                 const struct pipe_ctx *primary_pipe)
1294 {
1295         int i;
1296         struct pipe_ctx *secondary_pipe = NULL;
1297
1298         /*
1299          * We add a preferred pipe mapping to avoid the chance that
1300          * MPCCs already in use will need to be reassigned to other trees.
1301          * For example, if we went with the strict, assign backwards logic:
1302          *
1303          * (State 1)
1304          * Display A on, no surface, top pipe = 0
1305          * Display B on, no surface, top pipe = 1
1306          *
1307          * (State 2)
1308          * Display A on, no surface, top pipe = 0
1309          * Display B on, surface enable, top pipe = 1, bottom pipe = 5
1310          *
1311          * (State 3)
1312          * Display A on, surface enable, top pipe = 0, bottom pipe = 5
1313          * Display B on, surface enable, top pipe = 1, bottom pipe = 4
1314          *
1315          * The state 2->3 transition requires remapping MPCC 5 from display B
1316          * to display A.
1317          *
1318          * However, with the preferred pipe logic, state 2 would look like:
1319          *
1320          * (State 2)
1321          * Display A on, no surface, top pipe = 0
1322          * Display B on, surface enable, top pipe = 1, bottom pipe = 4
1323          *
1324          * This would then cause 2->3 to not require remapping any MPCCs.
1325          */
1326         if (primary_pipe) {
1327                 int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx;
1328                 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
1329                         secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
1330                         secondary_pipe->pipe_idx = preferred_pipe_idx;
1331                 }
1332         }
1333
1334         /*
1335          * search backwards for the second pipe to keep pipe
1336          * assignment more consistent
1337          */
1338         if (!secondary_pipe)
1339                 for (i = pool->pipe_count - 1; i >= 0; i--) {
1340                         if (res_ctx->pipe_ctx[i].stream == NULL) {
1341                                 secondary_pipe = &res_ctx->pipe_ctx[i];
1342                                 secondary_pipe->pipe_idx = i;
1343                                 break;
1344                         }
1345                 }
1346
1347         return secondary_pipe;
1348 }
1349
1350 struct pipe_ctx *resource_get_head_pipe_for_stream(
1351                 struct resource_context *res_ctx,
1352                 struct dc_stream_state *stream)
1353 {
1354         int i;
1355
1356         for (i = 0; i < MAX_PIPES; i++) {
1357                 if (res_ctx->pipe_ctx[i].stream == stream
1358                                 && !res_ctx->pipe_ctx[i].top_pipe
1359                                 && !res_ctx->pipe_ctx[i].prev_odm_pipe)
1360                         return &res_ctx->pipe_ctx[i];
1361         }
1362         return NULL;
1363 }
1364
1365 static struct pipe_ctx *resource_get_tail_pipe(
1366                 struct resource_context *res_ctx,
1367                 struct pipe_ctx *head_pipe)
1368 {
1369         struct pipe_ctx *tail_pipe;
1370
1371         tail_pipe = head_pipe->bottom_pipe;
1372
1373         while (tail_pipe) {
1374                 head_pipe = tail_pipe;
1375                 tail_pipe = tail_pipe->bottom_pipe;
1376         }
1377
1378         return head_pipe;
1379 }
1380
1381 /*
1382  * A free_pipe for a stream is defined here as a pipe
1383  * that has no surface attached yet
1384  */
1385 static struct pipe_ctx *acquire_free_pipe_for_head(
1386                 struct dc_state *context,
1387                 const struct resource_pool *pool,
1388                 struct pipe_ctx *head_pipe)
1389 {
1390         int i;
1391         struct resource_context *res_ctx = &context->res_ctx;
1392
1393         if (!head_pipe->plane_state)
1394                 return head_pipe;
1395
1396         /* Re-use pipe already acquired for this stream if available*/
1397         for (i = pool->pipe_count - 1; i >= 0; i--) {
1398                 if (res_ctx->pipe_ctx[i].stream == head_pipe->stream &&
1399                                 !res_ctx->pipe_ctx[i].plane_state) {
1400                         return &res_ctx->pipe_ctx[i];
1401                 }
1402         }
1403
1404         /*
1405          * At this point we have no re-useable pipe for this stream and we need
1406          * to acquire an idle one to satisfy the request
1407          */
1408
1409         if (!pool->funcs->acquire_idle_pipe_for_layer) {
1410                 if (!pool->funcs->acquire_idle_pipe_for_head_pipe_in_layer)
1411                         return NULL;
1412                 else
1413                         return pool->funcs->acquire_idle_pipe_for_head_pipe_in_layer(context, pool, head_pipe->stream, head_pipe);
1414         }
1415
1416         return pool->funcs->acquire_idle_pipe_for_layer(context, pool, head_pipe->stream);
1417 }
1418
1419 static int acquire_first_split_pipe(
1420                 struct resource_context *res_ctx,
1421                 const struct resource_pool *pool,
1422                 struct dc_stream_state *stream)
1423 {
1424         int i;
1425
1426         for (i = 0; i < pool->pipe_count; i++) {
1427                 struct pipe_ctx *split_pipe = &res_ctx->pipe_ctx[i];
1428
1429                 if (split_pipe->top_pipe &&
1430                                 split_pipe->top_pipe->plane_state == split_pipe->plane_state) {
1431                         split_pipe->top_pipe->bottom_pipe = split_pipe->bottom_pipe;
1432                         if (split_pipe->bottom_pipe)
1433                                 split_pipe->bottom_pipe->top_pipe = split_pipe->top_pipe;
1434
1435                         if (split_pipe->top_pipe->plane_state)
1436                                 resource_build_scaling_params(split_pipe->top_pipe);
1437
1438                         memset(split_pipe, 0, sizeof(*split_pipe));
1439                         split_pipe->stream_res.tg = pool->timing_generators[i];
1440                         split_pipe->plane_res.hubp = pool->hubps[i];
1441                         split_pipe->plane_res.ipp = pool->ipps[i];
1442                         split_pipe->plane_res.dpp = pool->dpps[i];
1443                         split_pipe->stream_res.opp = pool->opps[i];
1444                         split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst;
1445                         split_pipe->pipe_idx = i;
1446
1447                         split_pipe->stream = stream;
1448                         return i;
1449                 }
1450         }
1451         return -1;
1452 }
1453
1454 bool dc_add_plane_to_context(
1455                 const struct dc *dc,
1456                 struct dc_stream_state *stream,
1457                 struct dc_plane_state *plane_state,
1458                 struct dc_state *context)
1459 {
1460         int i;
1461         struct resource_pool *pool = dc->res_pool;
1462         struct pipe_ctx *head_pipe, *tail_pipe, *free_pipe;
1463         struct dc_stream_status *stream_status = NULL;
1464         struct pipe_ctx *prev_right_head = NULL;
1465         struct pipe_ctx *free_right_pipe = NULL;
1466         struct pipe_ctx *prev_left_head = NULL;
1467
1468         DC_LOGGER_INIT(stream->ctx->logger);
1469         for (i = 0; i < context->stream_count; i++)
1470                 if (context->streams[i] == stream) {
1471                         stream_status = &context->stream_status[i];
1472                         break;
1473                 }
1474         if (stream_status == NULL) {
1475                 dm_error("Existing stream not found; failed to attach surface!\n");
1476                 return false;
1477         }
1478
1479
1480         if (stream_status->plane_count == MAX_SURFACE_NUM) {
1481                 dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n",
1482                                 plane_state, MAX_SURFACE_NUM);
1483                 return false;
1484         }
1485
1486         head_pipe = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1487
1488         if (!head_pipe) {
1489                 dm_error("Head pipe not found for stream_state %p !\n", stream);
1490                 return false;
1491         }
1492
1493         /* retain new surface, but only once per stream */
1494         dc_plane_state_retain(plane_state);
1495
1496         while (head_pipe) {
1497                 free_pipe = acquire_free_pipe_for_head(context, pool, head_pipe);
1498
1499                 if (!free_pipe) {
1500                         int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
1501                         if (pipe_idx >= 0)
1502                                 free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
1503                 }
1504
1505                 if (!free_pipe) {
1506                         dc_plane_state_release(plane_state);
1507                         return false;
1508                 }
1509
1510                 free_pipe->plane_state = plane_state;
1511
1512                 if (head_pipe != free_pipe) {
1513                         tail_pipe = resource_get_tail_pipe(&context->res_ctx, head_pipe);
1514                         ASSERT(tail_pipe);
1515
1516                         /* ODM + window MPO, where MPO window is on right half only */
1517                         if (free_pipe->plane_state &&
1518                                 (free_pipe->plane_state->clip_rect.x >= free_pipe->stream->src.x + free_pipe->stream->src.width/2) &&
1519                                 tail_pipe->next_odm_pipe) {
1520
1521                                 /* For ODM + window MPO, in 3 plane case, if we already have a MPO window on
1522                                  *  the right side, then we will invalidate a 2nd one on the right side
1523                                  */
1524                                 if (head_pipe->next_odm_pipe && tail_pipe->next_odm_pipe->bottom_pipe) {
1525                                         dc_plane_state_release(plane_state);
1526                                         return false;
1527                                 }
1528
1529                                 DC_LOG_SCALER("%s - ODM + window MPO(right). free_pipe:%d  tail_pipe->next_odm_pipe:%d\n",
1530                                                 __func__,
1531                                                 free_pipe->pipe_idx,
1532                                                 tail_pipe->next_odm_pipe ? tail_pipe->next_odm_pipe->pipe_idx : -1);
1533
1534                                 /*
1535                                  * We want to avoid the case where the right side already has a pipe assigned to
1536                                  *  it and is different from free_pipe ( which would cause trigger a pipe
1537                                  *  reallocation ).
1538                                  * Check the old context to see if the right side already has a pipe allocated
1539                                  * - If not, continue to use free_pipe
1540                                  * - If the right side already has a pipe, use that pipe instead if its available
1541                                  */
1542
1543                                 /*
1544                                  * We also want to avoid the case where with three plane ( 2 MPO videos ), we have
1545                                  *  both videos on the left side so one of the videos is invalidated.  Then we
1546                                  *  move the invalidated video back to the right side.  If the order of the plane
1547                                  *  states is such that the right MPO plane is processed first, the free pipe
1548                                  *  selected by the head will be the left MPO pipe. But since there was no right
1549                                  *  MPO pipe, it will assign the free pipe to the right MPO pipe instead and
1550                                  *  a pipe reallocation will occur.
1551                                  * Check the old context to see if the left side already has a pipe allocated
1552                                  * - If not, continue to use free_pipe
1553                                  * - If the left side is already using this pipe, then pick another pipe for right
1554                                  */
1555
1556                                 prev_right_head = &dc->current_state->res_ctx.pipe_ctx[tail_pipe->next_odm_pipe->pipe_idx];
1557                                 if ((prev_right_head->bottom_pipe) &&
1558                                         (free_pipe->pipe_idx != prev_right_head->bottom_pipe->pipe_idx)) {
1559                                         free_right_pipe = acquire_free_pipe_for_head(context, pool, tail_pipe->next_odm_pipe);
1560                                 } else {
1561                                         prev_left_head = &dc->current_state->res_ctx.pipe_ctx[head_pipe->pipe_idx];
1562                                         if ((prev_left_head->bottom_pipe) &&
1563                                                 (free_pipe->pipe_idx == prev_left_head->bottom_pipe->pipe_idx)) {
1564                                                 free_right_pipe = acquire_free_pipe_for_head(context, pool, head_pipe);
1565                                         }
1566                                 }
1567
1568                                 if (free_right_pipe) {
1569                                         free_pipe->stream = NULL;
1570                                         memset(&free_pipe->stream_res, 0, sizeof(struct stream_resource));
1571                                         memset(&free_pipe->plane_res, 0, sizeof(struct plane_resource));
1572                                         free_pipe->plane_state = NULL;
1573                                         free_pipe->pipe_idx = 0;
1574                                         free_right_pipe->plane_state = plane_state;
1575                                         free_pipe = free_right_pipe;
1576                                 }
1577
1578                                 free_pipe->stream_res.tg = tail_pipe->next_odm_pipe->stream_res.tg;
1579                                 free_pipe->stream_res.abm = tail_pipe->next_odm_pipe->stream_res.abm;
1580                                 free_pipe->stream_res.opp = tail_pipe->next_odm_pipe->stream_res.opp;
1581                                 free_pipe->stream_res.stream_enc = tail_pipe->next_odm_pipe->stream_res.stream_enc;
1582                                 free_pipe->stream_res.audio = tail_pipe->next_odm_pipe->stream_res.audio;
1583                                 free_pipe->clock_source = tail_pipe->next_odm_pipe->clock_source;
1584
1585                                 free_pipe->top_pipe = tail_pipe->next_odm_pipe;
1586                                 tail_pipe->next_odm_pipe->bottom_pipe = free_pipe;
1587                         } else if (free_pipe->plane_state &&
1588                                 (free_pipe->plane_state->clip_rect.x >= free_pipe->stream->src.x + free_pipe->stream->src.width/2)
1589                                 && head_pipe->next_odm_pipe) {
1590
1591                                 /* For ODM + window MPO, support 3 plane ( 2 MPO ) case.
1592                                  * Here we have a desktop ODM + left window MPO and a new MPO window appears
1593                                  *  on the right side only.  It fails the first case, because tail_pipe is the
1594                                  *  left window MPO, so it has no next_odm_pipe.  So in this scenario, we check
1595                                  *  for head_pipe->next_odm_pipe instead
1596                                  */
1597                                 DC_LOG_SCALER("%s - ODM + win MPO (left) + win MPO (right). free_pipe:%d  head_pipe->next_odm:%d\n",
1598                                                 __func__,
1599                                                 free_pipe->pipe_idx,
1600                                                 head_pipe->next_odm_pipe ? head_pipe->next_odm_pipe->pipe_idx : -1);
1601
1602                                 /*
1603                                  * We want to avoid the case where the right side already has a pipe assigned to
1604                                  *  it and is different from free_pipe ( which would cause trigger a pipe
1605                                  *  reallocation ).
1606                                  * Check the old context to see if the right side already has a pipe allocated
1607                                  * - If not, continue to use free_pipe
1608                                  * - If the right side already has a pipe, use that pipe instead if its available
1609                                  */
1610                                 prev_right_head = &dc->current_state->res_ctx.pipe_ctx[head_pipe->next_odm_pipe->pipe_idx];
1611                                 if ((prev_right_head->bottom_pipe) &&
1612                                         (free_pipe->pipe_idx != prev_right_head->bottom_pipe->pipe_idx)) {
1613                                         free_right_pipe = acquire_free_pipe_for_head(context, pool, head_pipe->next_odm_pipe);
1614                                         if (free_right_pipe) {
1615                                                 free_pipe->stream = NULL;
1616                                                 memset(&free_pipe->stream_res, 0, sizeof(struct stream_resource));
1617                                                 memset(&free_pipe->plane_res, 0, sizeof(struct plane_resource));
1618                                                 free_pipe->plane_state = NULL;
1619                                                 free_pipe->pipe_idx = 0;
1620                                                 free_right_pipe->plane_state = plane_state;
1621                                                 free_pipe = free_right_pipe;
1622                                         }
1623                                 }
1624
1625                                 free_pipe->stream_res.tg = head_pipe->next_odm_pipe->stream_res.tg;
1626                                 free_pipe->stream_res.abm = head_pipe->next_odm_pipe->stream_res.abm;
1627                                 free_pipe->stream_res.opp = head_pipe->next_odm_pipe->stream_res.opp;
1628                                 free_pipe->stream_res.stream_enc = head_pipe->next_odm_pipe->stream_res.stream_enc;
1629                                 free_pipe->stream_res.audio = head_pipe->next_odm_pipe->stream_res.audio;
1630                                 free_pipe->clock_source = head_pipe->next_odm_pipe->clock_source;
1631
1632                                 free_pipe->top_pipe = head_pipe->next_odm_pipe;
1633                                 head_pipe->next_odm_pipe->bottom_pipe = free_pipe;
1634                         } else {
1635
1636                                 /* For ODM + window MPO, in 3 plane case, if we already have a MPO window on
1637                                  *  the left side, then we will invalidate a 2nd one on the left side
1638                                  */
1639                                 if (head_pipe->next_odm_pipe && tail_pipe->top_pipe) {
1640                                         dc_plane_state_release(plane_state);
1641                                         return false;
1642                                 }
1643
1644                                 free_pipe->stream_res.tg = tail_pipe->stream_res.tg;
1645                                 free_pipe->stream_res.abm = tail_pipe->stream_res.abm;
1646                                 free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
1647                                 free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc;
1648                                 free_pipe->stream_res.audio = tail_pipe->stream_res.audio;
1649                                 free_pipe->clock_source = tail_pipe->clock_source;
1650
1651                                 free_pipe->top_pipe = tail_pipe;
1652                                 tail_pipe->bottom_pipe = free_pipe;
1653
1654                                 /* Connect MPO pipes together if MPO window is in the centre */
1655                                 if (!(free_pipe->plane_state &&
1656                                                 (free_pipe->plane_state->clip_rect.x + free_pipe->plane_state->clip_rect.width <=
1657                                                 free_pipe->stream->src.x + free_pipe->stream->src.width/2))) {
1658                                         if (!free_pipe->next_odm_pipe &&
1659                                                 tail_pipe->next_odm_pipe && tail_pipe->next_odm_pipe->bottom_pipe) {
1660                                                 free_pipe->next_odm_pipe = tail_pipe->next_odm_pipe->bottom_pipe;
1661                                                 tail_pipe->next_odm_pipe->bottom_pipe->prev_odm_pipe = free_pipe;
1662                                         }
1663                                         if (!free_pipe->prev_odm_pipe &&
1664                                                 tail_pipe->prev_odm_pipe && tail_pipe->prev_odm_pipe->bottom_pipe) {
1665                                                 free_pipe->prev_odm_pipe = tail_pipe->prev_odm_pipe->bottom_pipe;
1666                                                 tail_pipe->prev_odm_pipe->bottom_pipe->next_odm_pipe = free_pipe;
1667                                         }
1668                                 }
1669                         }
1670                 }
1671
1672                 /* ODM + window MPO, where MPO window is on left half only */
1673                 if (free_pipe->plane_state &&
1674                         (free_pipe->plane_state->clip_rect.x + free_pipe->plane_state->clip_rect.width <=
1675                         free_pipe->stream->src.x + free_pipe->stream->src.width/2)) {
1676                         DC_LOG_SCALER("%s - ODM + window MPO(left). free_pipe:%d\n",
1677                                         __func__,
1678                                         free_pipe->pipe_idx);
1679                         break;
1680                 }
1681                 /* ODM + window MPO, where MPO window is on right half only */
1682                 if (free_pipe->plane_state &&
1683                         (free_pipe->plane_state->clip_rect.x >= free_pipe->stream->src.x + free_pipe->stream->src.width/2)) {
1684                         DC_LOG_SCALER("%s - ODM + window MPO(right). free_pipe:%d\n",
1685                                         __func__,
1686                                         free_pipe->pipe_idx);
1687                         break;
1688                 }
1689
1690                 head_pipe = head_pipe->next_odm_pipe;
1691         }
1692         /* assign new surfaces*/
1693         stream_status->plane_states[stream_status->plane_count] = plane_state;
1694
1695         stream_status->plane_count++;
1696
1697         return true;
1698 }
1699
1700 bool dc_remove_plane_from_context(
1701                 const struct dc *dc,
1702                 struct dc_stream_state *stream,
1703                 struct dc_plane_state *plane_state,
1704                 struct dc_state *context)
1705 {
1706         int i;
1707         struct dc_stream_status *stream_status = NULL;
1708         struct resource_pool *pool = dc->res_pool;
1709
1710         for (i = 0; i < context->stream_count; i++)
1711                 if (context->streams[i] == stream) {
1712                         stream_status = &context->stream_status[i];
1713                         break;
1714                 }
1715
1716         if (stream_status == NULL) {
1717                 dm_error("Existing stream not found; failed to remove plane.\n");
1718                 return false;
1719         }
1720
1721         /* release pipe for plane*/
1722         for (i = pool->pipe_count - 1; i >= 0; i--) {
1723                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1724
1725                 if (pipe_ctx->plane_state == plane_state) {
1726                         if (pipe_ctx->top_pipe)
1727                                 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
1728
1729                         /* Second condition is to avoid setting NULL to top pipe
1730                          * of tail pipe making it look like head pipe in subsequent
1731                          * deletes
1732                          */
1733                         if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe)
1734                                 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
1735
1736                         /*
1737                          * For head pipe detach surfaces from pipe for tail
1738                          * pipe just zero it out
1739                          */
1740                         if (!pipe_ctx->top_pipe)
1741                                 pipe_ctx->plane_state = NULL;
1742                         else
1743                                 memset(pipe_ctx, 0, sizeof(*pipe_ctx));
1744                 }
1745         }
1746
1747
1748         for (i = 0; i < stream_status->plane_count; i++) {
1749                 if (stream_status->plane_states[i] == plane_state) {
1750
1751                         dc_plane_state_release(stream_status->plane_states[i]);
1752                         break;
1753                 }
1754         }
1755
1756         if (i == stream_status->plane_count) {
1757                 dm_error("Existing plane_state not found; failed to detach it!\n");
1758                 return false;
1759         }
1760
1761         stream_status->plane_count--;
1762
1763         /* Start at the plane we've just released, and move all the planes one index forward to "trim" the array */
1764         for (; i < stream_status->plane_count; i++)
1765                 stream_status->plane_states[i] = stream_status->plane_states[i + 1];
1766
1767         stream_status->plane_states[stream_status->plane_count] = NULL;
1768
1769         return true;
1770 }
1771
1772 bool dc_rem_all_planes_for_stream(
1773                 const struct dc *dc,
1774                 struct dc_stream_state *stream,
1775                 struct dc_state *context)
1776 {
1777         int i, old_plane_count;
1778         struct dc_stream_status *stream_status = NULL;
1779         struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 };
1780
1781         for (i = 0; i < context->stream_count; i++)
1782                         if (context->streams[i] == stream) {
1783                                 stream_status = &context->stream_status[i];
1784                                 break;
1785                         }
1786
1787         if (stream_status == NULL) {
1788                 dm_error("Existing stream %p not found!\n", stream);
1789                 return false;
1790         }
1791
1792         old_plane_count = stream_status->plane_count;
1793
1794         for (i = 0; i < old_plane_count; i++)
1795                 del_planes[i] = stream_status->plane_states[i];
1796
1797         for (i = 0; i < old_plane_count; i++)
1798                 if (!dc_remove_plane_from_context(dc, stream, del_planes[i], context))
1799                         return false;
1800
1801         return true;
1802 }
1803
1804 static bool add_all_planes_for_stream(
1805                 const struct dc *dc,
1806                 struct dc_stream_state *stream,
1807                 const struct dc_validation_set set[],
1808                 int set_count,
1809                 struct dc_state *context)
1810 {
1811         int i, j;
1812
1813         for (i = 0; i < set_count; i++)
1814                 if (set[i].stream == stream)
1815                         break;
1816
1817         if (i == set_count) {
1818                 dm_error("Stream %p not found in set!\n", stream);
1819                 return false;
1820         }
1821
1822         for (j = 0; j < set[i].plane_count; j++)
1823                 if (!dc_add_plane_to_context(dc, stream, set[i].plane_states[j], context))
1824                         return false;
1825
1826         return true;
1827 }
1828
1829 bool dc_add_all_planes_for_stream(
1830                 const struct dc *dc,
1831                 struct dc_stream_state *stream,
1832                 struct dc_plane_state * const *plane_states,
1833                 int plane_count,
1834                 struct dc_state *context)
1835 {
1836         struct dc_validation_set set;
1837         int i;
1838
1839         set.stream = stream;
1840         set.plane_count = plane_count;
1841
1842         for (i = 0; i < plane_count; i++)
1843                 set.plane_states[i] = plane_states[i];
1844
1845         return add_all_planes_for_stream(dc, stream, &set, 1, context);
1846 }
1847
1848 bool is_timing_changed(struct dc_stream_state *cur_stream,
1849                        struct dc_stream_state *new_stream)
1850 {
1851         if (cur_stream == NULL)
1852                 return true;
1853
1854         /* If output color space is changed, need to reprogram info frames */
1855         if (cur_stream->output_color_space != new_stream->output_color_space)
1856                 return true;
1857
1858         return memcmp(
1859                 &cur_stream->timing,
1860                 &new_stream->timing,
1861                 sizeof(struct dc_crtc_timing)) != 0;
1862 }
1863
1864 static bool are_stream_backends_same(
1865         struct dc_stream_state *stream_a, struct dc_stream_state *stream_b)
1866 {
1867         if (stream_a == stream_b)
1868                 return true;
1869
1870         if (stream_a == NULL || stream_b == NULL)
1871                 return false;
1872
1873         if (is_timing_changed(stream_a, stream_b))
1874                 return false;
1875
1876         if (stream_a->signal != stream_b->signal)
1877                 return false;
1878
1879         if (stream_a->dpms_off != stream_b->dpms_off)
1880                 return false;
1881
1882         return true;
1883 }
1884
1885 /*
1886  * dc_is_stream_unchanged() - Compare two stream states for equivalence.
1887  *
1888  * Checks if there a difference between the two states
1889  * that would require a mode change.
1890  *
1891  * Does not compare cursor position or attributes.
1892  */
1893 bool dc_is_stream_unchanged(
1894         struct dc_stream_state *old_stream, struct dc_stream_state *stream)
1895 {
1896
1897         if (!are_stream_backends_same(old_stream, stream))
1898                 return false;
1899
1900         if (old_stream->ignore_msa_timing_param != stream->ignore_msa_timing_param)
1901                 return false;
1902
1903         /*compare audio info*/
1904         if (memcmp(&old_stream->audio_info, &stream->audio_info, sizeof(stream->audio_info)) != 0)
1905                 return false;
1906
1907         if (old_stream->odm_2to1_policy_applied != stream->odm_2to1_policy_applied)
1908                 return false;
1909
1910         return true;
1911 }
1912
1913 /*
1914  * dc_is_stream_scaling_unchanged() - Compare scaling rectangles of two streams.
1915  */
1916 bool dc_is_stream_scaling_unchanged(struct dc_stream_state *old_stream,
1917                                     struct dc_stream_state *stream)
1918 {
1919         if (old_stream == stream)
1920                 return true;
1921
1922         if (old_stream == NULL || stream == NULL)
1923                 return false;
1924
1925         if (memcmp(&old_stream->src,
1926                         &stream->src,
1927                         sizeof(struct rect)) != 0)
1928                 return false;
1929
1930         if (memcmp(&old_stream->dst,
1931                         &stream->dst,
1932                         sizeof(struct rect)) != 0)
1933                 return false;
1934
1935         return true;
1936 }
1937
1938 static void update_stream_engine_usage(
1939                 struct resource_context *res_ctx,
1940                 const struct resource_pool *pool,
1941                 struct stream_encoder *stream_enc,
1942                 bool acquired)
1943 {
1944         int i;
1945
1946         for (i = 0; i < pool->stream_enc_count; i++) {
1947                 if (pool->stream_enc[i] == stream_enc)
1948                         res_ctx->is_stream_enc_acquired[i] = acquired;
1949         }
1950 }
1951
1952 static void update_hpo_dp_stream_engine_usage(
1953                 struct resource_context *res_ctx,
1954                 const struct resource_pool *pool,
1955                 struct hpo_dp_stream_encoder *hpo_dp_stream_enc,
1956                 bool acquired)
1957 {
1958         int i;
1959
1960         for (i = 0; i < pool->hpo_dp_stream_enc_count; i++) {
1961                 if (pool->hpo_dp_stream_enc[i] == hpo_dp_stream_enc)
1962                         res_ctx->is_hpo_dp_stream_enc_acquired[i] = acquired;
1963         }
1964 }
1965
1966 static inline int find_acquired_hpo_dp_link_enc_for_link(
1967                 const struct resource_context *res_ctx,
1968                 const struct dc_link *link)
1969 {
1970         int i;
1971
1972         for (i = 0; i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_to_link_idx); i++)
1973                 if (res_ctx->hpo_dp_link_enc_ref_cnts[i] > 0 &&
1974                                 res_ctx->hpo_dp_link_enc_to_link_idx[i] == link->link_index)
1975                         return i;
1976
1977         return -1;
1978 }
1979
1980 static inline int find_free_hpo_dp_link_enc(const struct resource_context *res_ctx,
1981                 const struct resource_pool *pool)
1982 {
1983         int i;
1984
1985         for (i = 0; i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_ref_cnts); i++)
1986                 if (res_ctx->hpo_dp_link_enc_ref_cnts[i] == 0)
1987                         break;
1988
1989         return (i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_ref_cnts) &&
1990                         i < pool->hpo_dp_link_enc_count) ? i : -1;
1991 }
1992
1993 static inline void acquire_hpo_dp_link_enc(
1994                 struct resource_context *res_ctx,
1995                 unsigned int link_index,
1996                 int enc_index)
1997 {
1998         res_ctx->hpo_dp_link_enc_to_link_idx[enc_index] = link_index;
1999         res_ctx->hpo_dp_link_enc_ref_cnts[enc_index] = 1;
2000 }
2001
2002 static inline void retain_hpo_dp_link_enc(
2003                 struct resource_context *res_ctx,
2004                 int enc_index)
2005 {
2006         res_ctx->hpo_dp_link_enc_ref_cnts[enc_index]++;
2007 }
2008
2009 static inline void release_hpo_dp_link_enc(
2010                 struct resource_context *res_ctx,
2011                 int enc_index)
2012 {
2013         ASSERT(res_ctx->hpo_dp_link_enc_ref_cnts[enc_index] > 0);
2014         res_ctx->hpo_dp_link_enc_ref_cnts[enc_index]--;
2015 }
2016
2017 static bool add_hpo_dp_link_enc_to_ctx(struct resource_context *res_ctx,
2018                 const struct resource_pool *pool,
2019                 struct pipe_ctx *pipe_ctx,
2020                 struct dc_stream_state *stream)
2021 {
2022         int enc_index;
2023
2024         enc_index = find_acquired_hpo_dp_link_enc_for_link(res_ctx, stream->link);
2025
2026         if (enc_index >= 0) {
2027                 retain_hpo_dp_link_enc(res_ctx, enc_index);
2028         } else {
2029                 enc_index = find_free_hpo_dp_link_enc(res_ctx, pool);
2030                 if (enc_index >= 0)
2031                         acquire_hpo_dp_link_enc(res_ctx, stream->link->link_index, enc_index);
2032         }
2033
2034         if (enc_index >= 0)
2035                 pipe_ctx->link_res.hpo_dp_link_enc = pool->hpo_dp_link_enc[enc_index];
2036
2037         return pipe_ctx->link_res.hpo_dp_link_enc != NULL;
2038 }
2039
2040 static void remove_hpo_dp_link_enc_from_ctx(struct resource_context *res_ctx,
2041                 struct pipe_ctx *pipe_ctx,
2042                 struct dc_stream_state *stream)
2043 {
2044         int enc_index;
2045
2046         enc_index = find_acquired_hpo_dp_link_enc_for_link(res_ctx, stream->link);
2047
2048         if (enc_index >= 0) {
2049                 release_hpo_dp_link_enc(res_ctx, enc_index);
2050                 pipe_ctx->link_res.hpo_dp_link_enc = NULL;
2051         }
2052 }
2053
2054 /* TODO: release audio object */
2055 void update_audio_usage(
2056                 struct resource_context *res_ctx,
2057                 const struct resource_pool *pool,
2058                 struct audio *audio,
2059                 bool acquired)
2060 {
2061         int i;
2062         for (i = 0; i < pool->audio_count; i++) {
2063                 if (pool->audios[i] == audio)
2064                         res_ctx->is_audio_acquired[i] = acquired;
2065         }
2066 }
2067
2068 static int acquire_first_free_pipe(
2069                 struct resource_context *res_ctx,
2070                 const struct resource_pool *pool,
2071                 struct dc_stream_state *stream)
2072 {
2073         int i;
2074
2075         for (i = 0; i < pool->pipe_count; i++) {
2076                 if (!res_ctx->pipe_ctx[i].stream) {
2077                         struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
2078
2079                         pipe_ctx->stream_res.tg = pool->timing_generators[i];
2080                         pipe_ctx->plane_res.mi = pool->mis[i];
2081                         pipe_ctx->plane_res.hubp = pool->hubps[i];
2082                         pipe_ctx->plane_res.ipp = pool->ipps[i];
2083                         pipe_ctx->plane_res.xfm = pool->transforms[i];
2084                         pipe_ctx->plane_res.dpp = pool->dpps[i];
2085                         pipe_ctx->stream_res.opp = pool->opps[i];
2086                         if (pool->dpps[i])
2087                                 pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst;
2088                         pipe_ctx->pipe_idx = i;
2089
2090                         if (i >= pool->timing_generator_count) {
2091                                 int tg_inst = pool->timing_generator_count - 1;
2092
2093                                 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
2094                                 pipe_ctx->stream_res.opp = pool->opps[tg_inst];
2095                         }
2096
2097                         pipe_ctx->stream = stream;
2098                         return i;
2099                 }
2100         }
2101         return -1;
2102 }
2103
2104 static struct hpo_dp_stream_encoder *find_first_free_match_hpo_dp_stream_enc_for_link(
2105                 struct resource_context *res_ctx,
2106                 const struct resource_pool *pool,
2107                 struct dc_stream_state *stream)
2108 {
2109         int i;
2110
2111         for (i = 0; i < pool->hpo_dp_stream_enc_count; i++) {
2112                 if (!res_ctx->is_hpo_dp_stream_enc_acquired[i] &&
2113                                 pool->hpo_dp_stream_enc[i]) {
2114
2115                         return pool->hpo_dp_stream_enc[i];
2116                 }
2117         }
2118
2119         return NULL;
2120 }
2121
2122 static struct audio *find_first_free_audio(
2123                 struct resource_context *res_ctx,
2124                 const struct resource_pool *pool,
2125                 enum engine_id id,
2126                 enum dce_version dc_version)
2127 {
2128         int i, available_audio_count;
2129
2130         available_audio_count = pool->audio_count;
2131
2132         for (i = 0; i < available_audio_count; i++) {
2133                 if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) {
2134                         /*we have enough audio endpoint, find the matching inst*/
2135                         if (id != i)
2136                                 continue;
2137                         return pool->audios[i];
2138                 }
2139         }
2140
2141         /* use engine id to find free audio */
2142         if ((id < available_audio_count) && (res_ctx->is_audio_acquired[id] == false)) {
2143                 return pool->audios[id];
2144         }
2145         /*not found the matching one, first come first serve*/
2146         for (i = 0; i < available_audio_count; i++) {
2147                 if (res_ctx->is_audio_acquired[i] == false) {
2148                         return pool->audios[i];
2149                 }
2150         }
2151         return NULL;
2152 }
2153
2154 /*
2155  * dc_add_stream_to_ctx() - Add a new dc_stream_state to a dc_state.
2156  */
2157 enum dc_status dc_add_stream_to_ctx(
2158                 struct dc *dc,
2159                 struct dc_state *new_ctx,
2160                 struct dc_stream_state *stream)
2161 {
2162         enum dc_status res;
2163         DC_LOGGER_INIT(dc->ctx->logger);
2164
2165         if (new_ctx->stream_count >= dc->res_pool->timing_generator_count) {
2166                 DC_LOG_WARNING("Max streams reached, can't add stream %p !\n", stream);
2167                 return DC_ERROR_UNEXPECTED;
2168         }
2169
2170         new_ctx->streams[new_ctx->stream_count] = stream;
2171         dc_stream_retain(stream);
2172         new_ctx->stream_count++;
2173
2174         res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream);
2175         if (res != DC_OK)
2176                 DC_LOG_WARNING("Adding stream %p to context failed with err %d!\n", stream, res);
2177
2178         return res;
2179 }
2180
2181 /*
2182  * dc_remove_stream_from_ctx() - Remove a stream from a dc_state.
2183  */
2184 enum dc_status dc_remove_stream_from_ctx(
2185                         struct dc *dc,
2186                         struct dc_state *new_ctx,
2187                         struct dc_stream_state *stream)
2188 {
2189         int i;
2190         struct dc_context *dc_ctx = dc->ctx;
2191         struct pipe_ctx *del_pipe = resource_get_head_pipe_for_stream(&new_ctx->res_ctx, stream);
2192         struct pipe_ctx *odm_pipe;
2193
2194         if (!del_pipe) {
2195                 DC_ERROR("Pipe not found for stream %p !\n", stream);
2196                 return DC_ERROR_UNEXPECTED;
2197         }
2198
2199         odm_pipe = del_pipe->next_odm_pipe;
2200
2201         /* Release primary pipe */
2202         ASSERT(del_pipe->stream_res.stream_enc);
2203         update_stream_engine_usage(
2204                         &new_ctx->res_ctx,
2205                                 dc->res_pool,
2206                         del_pipe->stream_res.stream_enc,
2207                         false);
2208
2209         if (is_dp_128b_132b_signal(del_pipe)) {
2210                 update_hpo_dp_stream_engine_usage(
2211                         &new_ctx->res_ctx, dc->res_pool,
2212                         del_pipe->stream_res.hpo_dp_stream_enc,
2213                         false);
2214                 remove_hpo_dp_link_enc_from_ctx(&new_ctx->res_ctx, del_pipe, del_pipe->stream);
2215         }
2216
2217         if (del_pipe->stream_res.audio)
2218                 update_audio_usage(
2219                         &new_ctx->res_ctx,
2220                         dc->res_pool,
2221                         del_pipe->stream_res.audio,
2222                         false);
2223
2224         resource_unreference_clock_source(&new_ctx->res_ctx,
2225                                           dc->res_pool,
2226                                           del_pipe->clock_source);
2227
2228         if (dc->res_pool->funcs->remove_stream_from_ctx)
2229                 dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream);
2230
2231         while (odm_pipe) {
2232                 struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;
2233
2234                 memset(odm_pipe, 0, sizeof(*odm_pipe));
2235                 odm_pipe = next_odm_pipe;
2236         }
2237         memset(del_pipe, 0, sizeof(*del_pipe));
2238
2239         for (i = 0; i < new_ctx->stream_count; i++)
2240                 if (new_ctx->streams[i] == stream)
2241                         break;
2242
2243         if (new_ctx->streams[i] != stream) {
2244                 DC_ERROR("Context doesn't have stream %p !\n", stream);
2245                 return DC_ERROR_UNEXPECTED;
2246         }
2247
2248         dc_stream_release(new_ctx->streams[i]);
2249         new_ctx->stream_count--;
2250
2251         /* Trim back arrays */
2252         for (; i < new_ctx->stream_count; i++) {
2253                 new_ctx->streams[i] = new_ctx->streams[i + 1];
2254                 new_ctx->stream_status[i] = new_ctx->stream_status[i + 1];
2255         }
2256
2257         new_ctx->streams[new_ctx->stream_count] = NULL;
2258         memset(
2259                         &new_ctx->stream_status[new_ctx->stream_count],
2260                         0,
2261                         sizeof(new_ctx->stream_status[0]));
2262
2263         return DC_OK;
2264 }
2265
2266 static struct dc_stream_state *find_pll_sharable_stream(
2267                 struct dc_stream_state *stream_needs_pll,
2268                 struct dc_state *context)
2269 {
2270         int i;
2271
2272         for (i = 0; i < context->stream_count; i++) {
2273                 struct dc_stream_state *stream_has_pll = context->streams[i];
2274
2275                 /* We are looking for non dp, non virtual stream */
2276                 if (resource_are_streams_timing_synchronizable(
2277                         stream_needs_pll, stream_has_pll)
2278                         && !dc_is_dp_signal(stream_has_pll->signal)
2279                         && stream_has_pll->link->connector_signal
2280                         != SIGNAL_TYPE_VIRTUAL)
2281                         return stream_has_pll;
2282
2283         }
2284
2285         return NULL;
2286 }
2287
2288 static int get_norm_pix_clk(const struct dc_crtc_timing *timing)
2289 {
2290         uint32_t pix_clk = timing->pix_clk_100hz;
2291         uint32_t normalized_pix_clk = pix_clk;
2292
2293         if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2294                 pix_clk /= 2;
2295         if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
2296                 switch (timing->display_color_depth) {
2297                 case COLOR_DEPTH_666:
2298                 case COLOR_DEPTH_888:
2299                         normalized_pix_clk = pix_clk;
2300                         break;
2301                 case COLOR_DEPTH_101010:
2302                         normalized_pix_clk = (pix_clk * 30) / 24;
2303                         break;
2304                 case COLOR_DEPTH_121212:
2305                         normalized_pix_clk = (pix_clk * 36) / 24;
2306                 break;
2307                 case COLOR_DEPTH_161616:
2308                         normalized_pix_clk = (pix_clk * 48) / 24;
2309                 break;
2310                 default:
2311                         ASSERT(0);
2312                 break;
2313                 }
2314         }
2315         return normalized_pix_clk;
2316 }
2317
2318 static void calculate_phy_pix_clks(struct dc_stream_state *stream)
2319 {
2320         /* update actual pixel clock on all streams */
2321         if (dc_is_hdmi_signal(stream->signal))
2322                 stream->phy_pix_clk = get_norm_pix_clk(
2323                         &stream->timing) / 10;
2324         else
2325                 stream->phy_pix_clk =
2326                         stream->timing.pix_clk_100hz / 10;
2327
2328         if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
2329                 stream->phy_pix_clk *= 2;
2330 }
2331
2332 static int acquire_resource_from_hw_enabled_state(
2333                 struct resource_context *res_ctx,
2334                 const struct resource_pool *pool,
2335                 struct dc_stream_state *stream)
2336 {
2337         struct dc_link *link = stream->link;
2338         unsigned int i, inst, tg_inst = 0;
2339         uint32_t numPipes = 1;
2340         uint32_t id_src[4] = {0};
2341
2342         /* Check for enabled DIG to identify enabled display */
2343         if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
2344                 return -1;
2345
2346         inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
2347
2348         if (inst == ENGINE_ID_UNKNOWN)
2349                 return -1;
2350
2351         for (i = 0; i < pool->stream_enc_count; i++) {
2352                 if (pool->stream_enc[i]->id == inst) {
2353                         tg_inst = pool->stream_enc[i]->funcs->dig_source_otg(
2354                                 pool->stream_enc[i]);
2355                         break;
2356                 }
2357         }
2358
2359         // tg_inst not found
2360         if (i == pool->stream_enc_count)
2361                 return -1;
2362
2363         if (tg_inst >= pool->timing_generator_count)
2364                 return -1;
2365
2366         if (!res_ctx->pipe_ctx[tg_inst].stream) {
2367                 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst];
2368
2369                 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
2370                 id_src[0] = tg_inst;
2371
2372                 if (pipe_ctx->stream_res.tg->funcs->get_optc_source)
2373                         pipe_ctx->stream_res.tg->funcs->get_optc_source(pipe_ctx->stream_res.tg,
2374                                                 &numPipes, &id_src[0], &id_src[1]);
2375
2376                 if (id_src[0] == 0xf && id_src[1] == 0xf) {
2377                         id_src[0] = tg_inst;
2378                         numPipes = 1;
2379                 }
2380
2381                 for (i = 0; i < numPipes; i++) {
2382                         //Check if src id invalid
2383                         if (id_src[i] == 0xf)
2384                                 return -1;
2385
2386                         pipe_ctx = &res_ctx->pipe_ctx[id_src[i]];
2387
2388                         pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
2389                         pipe_ctx->plane_res.mi = pool->mis[id_src[i]];
2390                         pipe_ctx->plane_res.hubp = pool->hubps[id_src[i]];
2391                         pipe_ctx->plane_res.ipp = pool->ipps[id_src[i]];
2392                         pipe_ctx->plane_res.xfm = pool->transforms[id_src[i]];
2393                         pipe_ctx->plane_res.dpp = pool->dpps[id_src[i]];
2394                         pipe_ctx->stream_res.opp = pool->opps[id_src[i]];
2395
2396                         if (pool->dpps[id_src[i]]) {
2397                                 pipe_ctx->plane_res.mpcc_inst = pool->dpps[id_src[i]]->inst;
2398
2399                                 if (pool->mpc->funcs->read_mpcc_state) {
2400                                         struct mpcc_state s = {0};
2401
2402                                         pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s);
2403
2404                                         if (s.dpp_id < MAX_MPCC)
2405                                                 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id =
2406                                                                 s.dpp_id;
2407
2408                                         if (s.bot_mpcc_id < MAX_MPCC)
2409                                                 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot =
2410                                                                 &pool->mpc->mpcc_array[s.bot_mpcc_id];
2411
2412                                         if (s.opp_id < MAX_OPP)
2413                                                 pipe_ctx->stream_res.opp->mpc_tree_params.opp_id = s.opp_id;
2414                                 }
2415                         }
2416                         pipe_ctx->pipe_idx = id_src[i];
2417
2418                         if (id_src[i] >= pool->timing_generator_count) {
2419                                 id_src[i] = pool->timing_generator_count - 1;
2420
2421                                 pipe_ctx->stream_res.tg = pool->timing_generators[id_src[i]];
2422                                 pipe_ctx->stream_res.opp = pool->opps[id_src[i]];
2423                         }
2424
2425                         pipe_ctx->stream = stream;
2426                 }
2427
2428                 if (numPipes == 2) {
2429                         stream->apply_boot_odm_mode = dm_odm_combine_policy_2to1;
2430                         res_ctx->pipe_ctx[id_src[0]].next_odm_pipe = &res_ctx->pipe_ctx[id_src[1]];
2431                         res_ctx->pipe_ctx[id_src[0]].prev_odm_pipe = NULL;
2432                         res_ctx->pipe_ctx[id_src[1]].next_odm_pipe = NULL;
2433                         res_ctx->pipe_ctx[id_src[1]].prev_odm_pipe = &res_ctx->pipe_ctx[id_src[0]];
2434                 } else
2435                         stream->apply_boot_odm_mode = dm_odm_combine_mode_disabled;
2436
2437                 return id_src[0];
2438         }
2439
2440         return -1;
2441 }
2442
2443 static void mark_seamless_boot_stream(
2444                 const struct dc  *dc,
2445                 struct dc_stream_state *stream)
2446 {
2447         struct dc_bios *dcb = dc->ctx->dc_bios;
2448
2449         if (dc->config.allow_seamless_boot_optimization &&
2450                         !dcb->funcs->is_accelerated_mode(dcb)) {
2451                 if (dc_validate_boot_timing(dc, stream->sink, &stream->timing))
2452                         stream->apply_seamless_boot_optimization = true;
2453         }
2454 }
2455
2456 enum dc_status resource_map_pool_resources(
2457                 const struct dc  *dc,
2458                 struct dc_state *context,
2459                 struct dc_stream_state *stream)
2460 {
2461         const struct resource_pool *pool = dc->res_pool;
2462         int i;
2463         struct dc_context *dc_ctx = dc->ctx;
2464         struct pipe_ctx *pipe_ctx = NULL;
2465         int pipe_idx = -1;
2466
2467         calculate_phy_pix_clks(stream);
2468
2469         mark_seamless_boot_stream(dc, stream);
2470
2471         if (stream->apply_seamless_boot_optimization) {
2472                 pipe_idx = acquire_resource_from_hw_enabled_state(
2473                                 &context->res_ctx,
2474                                 pool,
2475                                 stream);
2476                 if (pipe_idx < 0)
2477                         /* hw resource was assigned to other stream */
2478                         stream->apply_seamless_boot_optimization = false;
2479         }
2480
2481         if (pipe_idx < 0)
2482                 /* acquire new resources */
2483                 pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
2484
2485         if (pipe_idx < 0)
2486                 pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
2487
2488         if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL)
2489                 return DC_NO_CONTROLLER_RESOURCE;
2490
2491         pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
2492
2493         pipe_ctx->stream_res.stream_enc =
2494                 dc->res_pool->funcs->find_first_free_match_stream_enc_for_link(
2495                         &context->res_ctx, pool, stream);
2496
2497         if (!pipe_ctx->stream_res.stream_enc)
2498                 return DC_NO_STREAM_ENC_RESOURCE;
2499
2500         update_stream_engine_usage(
2501                 &context->res_ctx, pool,
2502                 pipe_ctx->stream_res.stream_enc,
2503                 true);
2504
2505         /* Allocate DP HPO Stream Encoder based on signal, hw capabilities
2506          * and link settings
2507          */
2508         if (dc_is_dp_signal(stream->signal)) {
2509                 if (!decide_link_settings(stream, &pipe_ctx->link_config.dp_link_settings))
2510                         return DC_FAIL_DP_LINK_BANDWIDTH;
2511                 if (dp_get_link_encoding_format(&pipe_ctx->link_config.dp_link_settings) == DP_128b_132b_ENCODING) {
2512                         pipe_ctx->stream_res.hpo_dp_stream_enc =
2513                                         find_first_free_match_hpo_dp_stream_enc_for_link(
2514                                                         &context->res_ctx, pool, stream);
2515
2516                         if (!pipe_ctx->stream_res.hpo_dp_stream_enc)
2517                                 return DC_NO_STREAM_ENC_RESOURCE;
2518
2519                         update_hpo_dp_stream_engine_usage(
2520                                         &context->res_ctx, pool,
2521                                         pipe_ctx->stream_res.hpo_dp_stream_enc,
2522                                         true);
2523                         if (!add_hpo_dp_link_enc_to_ctx(&context->res_ctx, pool, pipe_ctx, stream))
2524                                 return DC_NO_LINK_ENC_RESOURCE;
2525                 }
2526         }
2527
2528         /* TODO: Add check if ASIC support and EDID audio */
2529         if (!stream->converter_disable_audio &&
2530             dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
2531             stream->audio_info.mode_count && stream->audio_info.flags.all) {
2532                 pipe_ctx->stream_res.audio = find_first_free_audio(
2533                 &context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id, dc_ctx->dce_version);
2534
2535                 /*
2536                  * Audio assigned in order first come first get.
2537                  * There are asics which has number of audio
2538                  * resources less then number of pipes
2539                  */
2540                 if (pipe_ctx->stream_res.audio)
2541                         update_audio_usage(&context->res_ctx, pool,
2542                                            pipe_ctx->stream_res.audio, true);
2543         }
2544
2545         /* Add ABM to the resource if on EDP */
2546         if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal)) {
2547                 if (pool->abm)
2548                         pipe_ctx->stream_res.abm = pool->abm;
2549                 else
2550                         pipe_ctx->stream_res.abm = pool->multiple_abms[pipe_ctx->stream_res.tg->inst];
2551         }
2552
2553         for (i = 0; i < context->stream_count; i++)
2554                 if (context->streams[i] == stream) {
2555                         context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;
2556                         context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->stream_enc_inst;
2557                         context->stream_status[i].audio_inst =
2558                                 pipe_ctx->stream_res.audio ? pipe_ctx->stream_res.audio->inst : -1;
2559
2560                         return DC_OK;
2561                 }
2562
2563         DC_ERROR("Stream %p not found in new ctx!\n", stream);
2564         return DC_ERROR_UNEXPECTED;
2565 }
2566
2567 /**
2568  * dc_resource_state_copy_construct_current() - Creates a new dc_state from existing state
2569  * Is a shallow copy.  Increments refcounts on existing streams and planes.
2570  * @dc: copy out of dc->current_state
2571  * @dst_ctx: copy into this
2572  */
2573 void dc_resource_state_copy_construct_current(
2574                 const struct dc *dc,
2575                 struct dc_state *dst_ctx)
2576 {
2577         dc_resource_state_copy_construct(dc->current_state, dst_ctx);
2578 }
2579
2580
2581 void dc_resource_state_construct(
2582                 const struct dc *dc,
2583                 struct dc_state *dst_ctx)
2584 {
2585         dst_ctx->clk_mgr = dc->clk_mgr;
2586
2587         /* Initialise DIG link encoder resource tracking variables. */
2588         link_enc_cfg_init(dc, dst_ctx);
2589 }
2590
2591
2592 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc)
2593 {
2594         if (dc->res_pool == NULL)
2595                 return false;
2596
2597         return dc->res_pool->res_cap->num_dsc > 0;
2598 }
2599
2600
2601 /**
2602  * dc_validate_global_state() - Determine if HW can support a given state
2603  * Checks HW resource availability and bandwidth requirement.
2604  * @dc: dc struct for this driver
2605  * @new_ctx: state to be validated
2606  * @fast_validate: set to true if only yes/no to support matters
2607  *
2608  * Return: DC_OK if the result can be programmed.  Otherwise, an error code.
2609  */
2610 enum dc_status dc_validate_global_state(
2611                 struct dc *dc,
2612                 struct dc_state *new_ctx,
2613                 bool fast_validate)
2614 {
2615         enum dc_status result = DC_ERROR_UNEXPECTED;
2616         int i, j;
2617
2618         if (!new_ctx)
2619                 return DC_ERROR_UNEXPECTED;
2620
2621         if (dc->res_pool->funcs->validate_global) {
2622                 result = dc->res_pool->funcs->validate_global(dc, new_ctx);
2623                 if (result != DC_OK)
2624                         return result;
2625         }
2626
2627         for (i = 0; i < new_ctx->stream_count; i++) {
2628                 struct dc_stream_state *stream = new_ctx->streams[i];
2629
2630                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2631                         struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j];
2632
2633                         if (pipe_ctx->stream != stream)
2634                                 continue;
2635
2636                         if (dc->res_pool->funcs->patch_unknown_plane_state &&
2637                                         pipe_ctx->plane_state &&
2638                                         pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) {
2639                                 result = dc->res_pool->funcs->patch_unknown_plane_state(pipe_ctx->plane_state);
2640                                 if (result != DC_OK)
2641                                         return result;
2642                         }
2643
2644                         /* Switch to dp clock source only if there is
2645                          * no non dp stream that shares the same timing
2646                          * with the dp stream.
2647                          */
2648                         if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
2649                                 !find_pll_sharable_stream(stream, new_ctx)) {
2650
2651                                 resource_unreference_clock_source(
2652                                                 &new_ctx->res_ctx,
2653                                                 dc->res_pool,
2654                                                 pipe_ctx->clock_source);
2655
2656                                 pipe_ctx->clock_source = dc->res_pool->dp_clock_source;
2657                                 resource_reference_clock_source(
2658                                                 &new_ctx->res_ctx,
2659                                                 dc->res_pool,
2660                                                  pipe_ctx->clock_source);
2661                         }
2662                 }
2663         }
2664
2665         result = resource_build_scaling_params_for_context(dc, new_ctx);
2666
2667         if (result == DC_OK)
2668                 if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx, fast_validate))
2669                         result = DC_FAIL_BANDWIDTH_VALIDATE;
2670
2671         /*
2672          * Only update link encoder to stream assignment after bandwidth validation passed.
2673          * TODO: Split out assignment and validation.
2674          */
2675         if (result == DC_OK && dc->res_pool->funcs->link_encs_assign && fast_validate == false)
2676                 dc->res_pool->funcs->link_encs_assign(
2677                         dc, new_ctx, new_ctx->streams, new_ctx->stream_count);
2678
2679         return result;
2680 }
2681
2682 static void patch_gamut_packet_checksum(
2683                 struct dc_info_packet *gamut_packet)
2684 {
2685         /* For gamut we recalc checksum */
2686         if (gamut_packet->valid) {
2687                 uint8_t chk_sum = 0;
2688                 uint8_t *ptr;
2689                 uint8_t i;
2690
2691                 /*start of the Gamut data. */
2692                 ptr = &gamut_packet->sb[3];
2693
2694                 for (i = 0; i <= gamut_packet->sb[1]; i++)
2695                         chk_sum += ptr[i];
2696
2697                 gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum);
2698         }
2699 }
2700
2701 static void set_avi_info_frame(
2702                 struct dc_info_packet *info_packet,
2703                 struct pipe_ctx *pipe_ctx)
2704 {
2705         struct dc_stream_state *stream = pipe_ctx->stream;
2706         enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
2707         uint32_t pixel_encoding = 0;
2708         enum scanning_type scan_type = SCANNING_TYPE_NODATA;
2709         enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
2710         bool itc = false;
2711         uint8_t itc_value = 0;
2712         uint8_t cn0_cn1 = 0;
2713         unsigned int cn0_cn1_value = 0;
2714         uint8_t *check_sum = NULL;
2715         uint8_t byte_index = 0;
2716         union hdmi_info_packet hdmi_info;
2717         union display_content_support support = {0};
2718         unsigned int vic = pipe_ctx->stream->timing.vic;
2719         unsigned int rid = pipe_ctx->stream->timing.rid;
2720         unsigned int fr_ind = pipe_ctx->stream->timing.fr_index;
2721         enum dc_timing_3d_format format;
2722
2723         memset(&hdmi_info, 0, sizeof(union hdmi_info_packet));
2724
2725         color_space = pipe_ctx->stream->output_color_space;
2726         if (color_space == COLOR_SPACE_UNKNOWN)
2727                 color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ?
2728                         COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709;
2729
2730         /* Initialize header */
2731         hdmi_info.bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
2732         /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
2733         * not be used in HDMI 2.0 (Section 10.1) */
2734         hdmi_info.bits.header.version = 2;
2735         hdmi_info.bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
2736
2737         /*
2738          * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
2739          * according to HDMI 2.0 spec (Section 10.1)
2740          */
2741
2742         switch (stream->timing.pixel_encoding) {
2743         case PIXEL_ENCODING_YCBCR422:
2744                 pixel_encoding = 1;
2745                 break;
2746
2747         case PIXEL_ENCODING_YCBCR444:
2748                 pixel_encoding = 2;
2749                 break;
2750         case PIXEL_ENCODING_YCBCR420:
2751                 pixel_encoding = 3;
2752                 break;
2753
2754         case PIXEL_ENCODING_RGB:
2755         default:
2756                 pixel_encoding = 0;
2757         }
2758
2759         /* Y0_Y1_Y2 : The pixel encoding */
2760         /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
2761         hdmi_info.bits.Y0_Y1_Y2 = pixel_encoding;
2762
2763         /* A0 = 1 Active Format Information valid */
2764         hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID;
2765
2766         /* B0, B1 = 3; Bar info data is valid */
2767         hdmi_info.bits.B0_B1 = BAR_INFO_BOTH_VALID;
2768
2769         hdmi_info.bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
2770
2771         /* S0, S1 : Underscan / Overscan */
2772         /* TODO: un-hardcode scan type */
2773         scan_type = SCANNING_TYPE_UNDERSCAN;
2774         hdmi_info.bits.S0_S1 = scan_type;
2775
2776         /* C0, C1 : Colorimetry */
2777         if (color_space == COLOR_SPACE_YCBCR709 ||
2778                         color_space == COLOR_SPACE_YCBCR709_LIMITED)
2779                 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709;
2780         else if (color_space == COLOR_SPACE_YCBCR601 ||
2781                         color_space == COLOR_SPACE_YCBCR601_LIMITED)
2782                 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU601;
2783         else {
2784                 hdmi_info.bits.C0_C1 = COLORIMETRY_NO_DATA;
2785         }
2786         if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
2787                         color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE ||
2788                         color_space == COLOR_SPACE_2020_YCBCR) {
2789                 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
2790                 hdmi_info.bits.C0_C1   = COLORIMETRY_EXTENDED;
2791         } else if (color_space == COLOR_SPACE_ADOBERGB) {
2792                 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
2793                 hdmi_info.bits.C0_C1   = COLORIMETRY_EXTENDED;
2794         }
2795
2796         /* TODO: un-hardcode aspect ratio */
2797         aspect = stream->timing.aspect_ratio;
2798
2799         switch (aspect) {
2800         case ASPECT_RATIO_4_3:
2801         case ASPECT_RATIO_16_9:
2802                 hdmi_info.bits.M0_M1 = aspect;
2803                 break;
2804
2805         case ASPECT_RATIO_NO_DATA:
2806         case ASPECT_RATIO_64_27:
2807         case ASPECT_RATIO_256_135:
2808         default:
2809                 hdmi_info.bits.M0_M1 = 0;
2810         }
2811
2812         /* Active Format Aspect ratio - same as Picture Aspect Ratio. */
2813         hdmi_info.bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
2814
2815         /* TODO: un-hardcode cn0_cn1 and itc */
2816
2817         cn0_cn1 = 0;
2818         cn0_cn1_value = 0;
2819
2820         itc = true;
2821         itc_value = 1;
2822
2823         support = stream->content_support;
2824
2825         if (itc) {
2826                 if (!support.bits.valid_content_type) {
2827                         cn0_cn1_value = 0;
2828                 } else {
2829                         if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GRAPHICS) {
2830                                 if (support.bits.graphics_content == 1) {
2831                                         cn0_cn1_value = 0;
2832                                 }
2833                         } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_PHOTO) {
2834                                 if (support.bits.photo_content == 1) {
2835                                         cn0_cn1_value = 1;
2836                                 } else {
2837                                         cn0_cn1_value = 0;
2838                                         itc_value = 0;
2839                                 }
2840                         } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_CINEMA) {
2841                                 if (support.bits.cinema_content == 1) {
2842                                         cn0_cn1_value = 2;
2843                                 } else {
2844                                         cn0_cn1_value = 0;
2845                                         itc_value = 0;
2846                                 }
2847                         } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GAME) {
2848                                 if (support.bits.game_content == 1) {
2849                                         cn0_cn1_value = 3;
2850                                 } else {
2851                                         cn0_cn1_value = 0;
2852                                         itc_value = 0;
2853                                 }
2854                         }
2855                 }
2856                 hdmi_info.bits.CN0_CN1 = cn0_cn1_value;
2857                 hdmi_info.bits.ITC = itc_value;
2858         }
2859
2860         if (stream->qs_bit == 1) {
2861                 if (color_space == COLOR_SPACE_SRGB ||
2862                         color_space == COLOR_SPACE_2020_RGB_FULLRANGE)
2863                         hdmi_info.bits.Q0_Q1   = RGB_QUANTIZATION_FULL_RANGE;
2864                 else if (color_space == COLOR_SPACE_SRGB_LIMITED ||
2865                                         color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE)
2866                         hdmi_info.bits.Q0_Q1   = RGB_QUANTIZATION_LIMITED_RANGE;
2867                 else
2868                         hdmi_info.bits.Q0_Q1   = RGB_QUANTIZATION_DEFAULT_RANGE;
2869         } else
2870                 hdmi_info.bits.Q0_Q1   = RGB_QUANTIZATION_DEFAULT_RANGE;
2871
2872         /* TODO : We should handle YCC quantization */
2873         /* but we do not have matrix calculation */
2874         hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
2875
2876         ///VIC
2877         if (pipe_ctx->stream->timing.hdmi_vic != 0)
2878                 vic = 0;
2879         format = stream->timing.timing_3d_format;
2880         /*todo, add 3DStereo support*/
2881         if (format != TIMING_3D_FORMAT_NONE) {
2882                 // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled
2883                 switch (pipe_ctx->stream->timing.hdmi_vic) {
2884                 case 1:
2885                         vic = 95;
2886                         break;
2887                 case 2:
2888                         vic = 94;
2889                         break;
2890                 case 3:
2891                         vic = 93;
2892                         break;
2893                 case 4:
2894                         vic = 98;
2895                         break;
2896                 default:
2897                         break;
2898                 }
2899         }
2900         /* If VIC >= 128, the Source shall use AVI InfoFrame Version 3*/
2901         hdmi_info.bits.VIC0_VIC7 = vic;
2902         if (vic >= 128)
2903                 hdmi_info.bits.header.version = 3;
2904         /* If (C1, C0)=(1, 1) and (EC2, EC1, EC0)=(1, 1, 1),
2905          * the Source shall use 20 AVI InfoFrame Version 4
2906          */
2907         if (hdmi_info.bits.C0_C1 == COLORIMETRY_EXTENDED &&
2908                         hdmi_info.bits.EC0_EC2 == COLORIMETRYEX_RESERVED) {
2909                 hdmi_info.bits.header.version = 4;
2910                 hdmi_info.bits.header.length = 14;
2911         }
2912
2913         if (rid != 0 && fr_ind != 0) {
2914                 hdmi_info.bits.header.version = 5;
2915                 hdmi_info.bits.header.length = 15;
2916
2917                 hdmi_info.bits.FR0_FR3 = fr_ind & 0xF;
2918                 hdmi_info.bits.FR4 = (fr_ind >> 4) & 0x1;
2919                 hdmi_info.bits.RID0_RID5 = rid;
2920         }
2921
2922         /* pixel repetition
2923          * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
2924          * repetition start from 1 */
2925         hdmi_info.bits.PR0_PR3 = 0;
2926
2927         /* Bar Info
2928          * barTop:    Line Number of End of Top Bar.
2929          * barBottom: Line Number of Start of Bottom Bar.
2930          * barLeft:   Pixel Number of End of Left Bar.
2931          * barRight:  Pixel Number of Start of Right Bar. */
2932         hdmi_info.bits.bar_top = stream->timing.v_border_top;
2933         hdmi_info.bits.bar_bottom = (stream->timing.v_total
2934                         - stream->timing.v_border_bottom + 1);
2935         hdmi_info.bits.bar_left  = stream->timing.h_border_left;
2936         hdmi_info.bits.bar_right = (stream->timing.h_total
2937                         - stream->timing.h_border_right + 1);
2938
2939     /* Additional Colorimetry Extension
2940      * Used in conduction with C0-C1 and EC0-EC2
2941      * 0 = DCI-P3 RGB (D65)
2942      * 1 = DCI-P3 RGB (theater)
2943      */
2944         hdmi_info.bits.ACE0_ACE3 = 0;
2945
2946         /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
2947         check_sum = &hdmi_info.packet_raw_data.sb[0];
2948
2949         *check_sum = HDMI_INFOFRAME_TYPE_AVI + hdmi_info.bits.header.length + hdmi_info.bits.header.version;
2950
2951         for (byte_index = 1; byte_index <= hdmi_info.bits.header.length; byte_index++)
2952                 *check_sum += hdmi_info.packet_raw_data.sb[byte_index];
2953
2954         /* one byte complement */
2955         *check_sum = (uint8_t) (0x100 - *check_sum);
2956
2957         /* Store in hw_path_mode */
2958         info_packet->hb0 = hdmi_info.packet_raw_data.hb0;
2959         info_packet->hb1 = hdmi_info.packet_raw_data.hb1;
2960         info_packet->hb2 = hdmi_info.packet_raw_data.hb2;
2961
2962         for (byte_index = 0; byte_index < sizeof(hdmi_info.packet_raw_data.sb); byte_index++)
2963                 info_packet->sb[byte_index] = hdmi_info.packet_raw_data.sb[byte_index];
2964
2965         info_packet->valid = true;
2966 }
2967
2968 static void set_vendor_info_packet(
2969                 struct dc_info_packet *info_packet,
2970                 struct dc_stream_state *stream)
2971 {
2972         /* SPD info packet for FreeSync */
2973
2974         /* Check if Freesync is supported. Return if false. If true,
2975          * set the corresponding bit in the info packet
2976          */
2977         if (!stream->vsp_infopacket.valid)
2978                 return;
2979
2980         *info_packet = stream->vsp_infopacket;
2981 }
2982
2983 static void set_spd_info_packet(
2984                 struct dc_info_packet *info_packet,
2985                 struct dc_stream_state *stream)
2986 {
2987         /* SPD info packet for FreeSync */
2988
2989         /* Check if Freesync is supported. Return if false. If true,
2990          * set the corresponding bit in the info packet
2991          */
2992         if (!stream->vrr_infopacket.valid)
2993                 return;
2994
2995         *info_packet = stream->vrr_infopacket;
2996 }
2997
2998 static void set_hdr_static_info_packet(
2999                 struct dc_info_packet *info_packet,
3000                 struct dc_stream_state *stream)
3001 {
3002         /* HDR Static Metadata info packet for HDR10 */
3003
3004         if (!stream->hdr_static_metadata.valid ||
3005                         stream->use_dynamic_meta)
3006                 return;
3007
3008         *info_packet = stream->hdr_static_metadata;
3009 }
3010
3011 static void set_vsc_info_packet(
3012                 struct dc_info_packet *info_packet,
3013                 struct dc_stream_state *stream)
3014 {
3015         if (!stream->vsc_infopacket.valid)
3016                 return;
3017
3018         *info_packet = stream->vsc_infopacket;
3019 }
3020 static void set_hfvs_info_packet(
3021                 struct dc_info_packet *info_packet,
3022                 struct dc_stream_state *stream)
3023 {
3024         if (!stream->hfvsif_infopacket.valid)
3025                 return;
3026
3027         *info_packet = stream->hfvsif_infopacket;
3028 }
3029
3030
3031 static void set_vtem_info_packet(
3032                 struct dc_info_packet *info_packet,
3033                 struct dc_stream_state *stream)
3034 {
3035         if (!stream->vtem_infopacket.valid)
3036                 return;
3037
3038         *info_packet = stream->vtem_infopacket;
3039 }
3040
3041 void dc_resource_state_destruct(struct dc_state *context)
3042 {
3043         int i, j;
3044
3045         for (i = 0; i < context->stream_count; i++) {
3046                 for (j = 0; j < context->stream_status[i].plane_count; j++)
3047                         dc_plane_state_release(
3048                                 context->stream_status[i].plane_states[j]);
3049
3050                 context->stream_status[i].plane_count = 0;
3051                 dc_stream_release(context->streams[i]);
3052                 context->streams[i] = NULL;
3053         }
3054         context->stream_count = 0;
3055 }
3056
3057 void dc_resource_state_copy_construct(
3058                 const struct dc_state *src_ctx,
3059                 struct dc_state *dst_ctx)
3060 {
3061         int i, j;
3062         struct kref refcount = dst_ctx->refcount;
3063
3064         *dst_ctx = *src_ctx;
3065
3066         for (i = 0; i < MAX_PIPES; i++) {
3067                 struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i];
3068
3069                 if (cur_pipe->top_pipe)
3070                         cur_pipe->top_pipe =  &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
3071
3072                 if (cur_pipe->bottom_pipe)
3073                         cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
3074
3075                 if (cur_pipe->next_odm_pipe)
3076                         cur_pipe->next_odm_pipe =  &dst_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];
3077
3078                 if (cur_pipe->prev_odm_pipe)
3079                         cur_pipe->prev_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];
3080         }
3081
3082         for (i = 0; i < dst_ctx->stream_count; i++) {
3083                 dc_stream_retain(dst_ctx->streams[i]);
3084                 for (j = 0; j < dst_ctx->stream_status[i].plane_count; j++)
3085                         dc_plane_state_retain(
3086                                 dst_ctx->stream_status[i].plane_states[j]);
3087         }
3088
3089         /* context refcount should not be overridden */
3090         dst_ctx->refcount = refcount;
3091
3092 }
3093
3094 struct clock_source *dc_resource_find_first_free_pll(
3095                 struct resource_context *res_ctx,
3096                 const struct resource_pool *pool)
3097 {
3098         int i;
3099
3100         for (i = 0; i < pool->clk_src_count; ++i) {
3101                 if (res_ctx->clock_source_ref_count[i] == 0)
3102                         return pool->clock_sources[i];
3103         }
3104
3105         return NULL;
3106 }
3107
3108 void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
3109 {
3110         enum signal_type signal = SIGNAL_TYPE_NONE;
3111         struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame;
3112
3113         /* default all packets to invalid */
3114         info->avi.valid = false;
3115         info->gamut.valid = false;
3116         info->vendor.valid = false;
3117         info->spd.valid = false;
3118         info->hdrsmd.valid = false;
3119         info->vsc.valid = false;
3120         info->hfvsif.valid = false;
3121         info->vtem.valid = false;
3122         signal = pipe_ctx->stream->signal;
3123
3124         /* HDMi and DP have different info packets*/
3125         if (dc_is_hdmi_signal(signal)) {
3126                 set_avi_info_frame(&info->avi, pipe_ctx);
3127
3128                 set_vendor_info_packet(&info->vendor, pipe_ctx->stream);
3129                 set_hfvs_info_packet(&info->hfvsif, pipe_ctx->stream);
3130                 set_vtem_info_packet(&info->vtem, pipe_ctx->stream);
3131
3132                 set_spd_info_packet(&info->spd, pipe_ctx->stream);
3133
3134                 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
3135
3136         } else if (dc_is_dp_signal(signal)) {
3137                 set_vsc_info_packet(&info->vsc, pipe_ctx->stream);
3138
3139                 set_spd_info_packet(&info->spd, pipe_ctx->stream);
3140
3141                 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
3142         }
3143
3144         patch_gamut_packet_checksum(&info->gamut);
3145 }
3146
3147 enum dc_status resource_map_clock_resources(
3148                 const struct dc  *dc,
3149                 struct dc_state *context,
3150                 struct dc_stream_state *stream)
3151 {
3152         /* acquire new resources */
3153         const struct resource_pool *pool = dc->res_pool;
3154         struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(
3155                                 &context->res_ctx, stream);
3156
3157         if (!pipe_ctx)
3158                 return DC_ERROR_UNEXPECTED;
3159
3160         if (dc_is_dp_signal(pipe_ctx->stream->signal)
3161                 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
3162                 pipe_ctx->clock_source = pool->dp_clock_source;
3163         else {
3164                 pipe_ctx->clock_source = NULL;
3165
3166                 if (!dc->config.disable_disp_pll_sharing)
3167                         pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing(
3168                                 &context->res_ctx,
3169                                 pipe_ctx);
3170
3171                 if (pipe_ctx->clock_source == NULL)
3172                         pipe_ctx->clock_source =
3173                                 dc_resource_find_first_free_pll(
3174                                         &context->res_ctx,
3175                                         pool);
3176         }
3177
3178         if (pipe_ctx->clock_source == NULL)
3179                 return DC_NO_CLOCK_SOURCE_RESOURCE;
3180
3181         resource_reference_clock_source(
3182                 &context->res_ctx, pool,
3183                 pipe_ctx->clock_source);
3184
3185         return DC_OK;
3186 }
3187
3188 /*
3189  * Note: We need to disable output if clock sources change,
3190  * since bios does optimization and doesn't apply if changing
3191  * PHY when not already disabled.
3192  */
3193 bool pipe_need_reprogram(
3194                 struct pipe_ctx *pipe_ctx_old,
3195                 struct pipe_ctx *pipe_ctx)
3196 {
3197         if (!pipe_ctx_old->stream)
3198                 return false;
3199
3200         if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)
3201                 return true;
3202
3203         if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal)
3204                 return true;
3205
3206         if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio)
3207                 return true;
3208
3209         if (pipe_ctx_old->clock_source != pipe_ctx->clock_source
3210                         && pipe_ctx_old->stream != pipe_ctx->stream)
3211                 return true;
3212
3213         if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc)
3214                 return true;
3215
3216         if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))
3217                 return true;
3218
3219         if (pipe_ctx_old->stream->dpms_off != pipe_ctx->stream->dpms_off)
3220                 return true;
3221
3222         if (false == pipe_ctx_old->stream->link->link_state_valid &&
3223                 false == pipe_ctx_old->stream->dpms_off)
3224                 return true;
3225
3226         if (pipe_ctx_old->stream_res.dsc != pipe_ctx->stream_res.dsc)
3227                 return true;
3228
3229         if (pipe_ctx_old->stream_res.hpo_dp_stream_enc != pipe_ctx->stream_res.hpo_dp_stream_enc)
3230                 return true;
3231         if (pipe_ctx_old->link_res.hpo_dp_link_enc != pipe_ctx->link_res.hpo_dp_link_enc)
3232                 return true;
3233
3234         /* DIG link encoder resource assignment for stream changed. */
3235         if (pipe_ctx_old->stream->ctx->dc->res_pool->funcs->link_encs_assign) {
3236                 bool need_reprogram = false;
3237                 struct dc *dc = pipe_ctx_old->stream->ctx->dc;
3238                 struct link_encoder *link_enc_prev =
3239                         link_enc_cfg_get_link_enc_used_by_stream_current(dc, pipe_ctx_old->stream);
3240
3241                 if (link_enc_prev != pipe_ctx->stream->link_enc)
3242                         need_reprogram = true;
3243
3244                 return need_reprogram;
3245         }
3246
3247         return false;
3248 }
3249
3250 void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
3251                 struct bit_depth_reduction_params *fmt_bit_depth)
3252 {
3253         enum dc_dither_option option = stream->dither_option;
3254         enum dc_pixel_encoding pixel_encoding =
3255                         stream->timing.pixel_encoding;
3256
3257         memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth));
3258
3259         if (option == DITHER_OPTION_DEFAULT) {
3260                 switch (stream->timing.display_color_depth) {
3261                 case COLOR_DEPTH_666:
3262                         option = DITHER_OPTION_SPATIAL6;
3263                         break;
3264                 case COLOR_DEPTH_888:
3265                         option = DITHER_OPTION_SPATIAL8;
3266                         break;
3267                 case COLOR_DEPTH_101010:
3268                         option = DITHER_OPTION_SPATIAL10;
3269                         break;
3270                 default:
3271                         option = DITHER_OPTION_DISABLE;
3272                 }
3273         }
3274
3275         if (option == DITHER_OPTION_DISABLE)
3276                 return;
3277
3278         if (option == DITHER_OPTION_TRUN6) {
3279                 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
3280                 fmt_bit_depth->flags.TRUNCATE_DEPTH = 0;
3281         } else if (option == DITHER_OPTION_TRUN8 ||
3282                         option == DITHER_OPTION_TRUN8_SPATIAL6 ||
3283                         option == DITHER_OPTION_TRUN8_FM6) {
3284                 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
3285                 fmt_bit_depth->flags.TRUNCATE_DEPTH = 1;
3286         } else if (option == DITHER_OPTION_TRUN10        ||
3287                         option == DITHER_OPTION_TRUN10_SPATIAL6   ||
3288                         option == DITHER_OPTION_TRUN10_SPATIAL8   ||
3289                         option == DITHER_OPTION_TRUN10_FM8     ||
3290                         option == DITHER_OPTION_TRUN10_FM6     ||
3291                         option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
3292                 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
3293                 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
3294         }
3295
3296         /* special case - Formatter can only reduce by 4 bits at most.
3297          * When reducing from 12 to 6 bits,
3298          * HW recommends we use trunc with round mode
3299          * (if we did nothing, trunc to 10 bits would be used)
3300          * note that any 12->10 bit reduction is ignored prior to DCE8,
3301          * as the input was 10 bits.
3302          */
3303         if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
3304                         option == DITHER_OPTION_SPATIAL6 ||
3305                         option == DITHER_OPTION_FM6) {
3306                 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
3307                 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
3308                 fmt_bit_depth->flags.TRUNCATE_MODE = 1;
3309         }
3310
3311         /* spatial dither
3312          * note that spatial modes 1-3 are never used
3313          */
3314         if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM            ||
3315                         option == DITHER_OPTION_SPATIAL6 ||
3316                         option == DITHER_OPTION_TRUN10_SPATIAL6      ||
3317                         option == DITHER_OPTION_TRUN8_SPATIAL6) {
3318                 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
3319                 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0;
3320                 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
3321                 fmt_bit_depth->flags.RGB_RANDOM =
3322                                 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
3323         } else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM            ||
3324                         option == DITHER_OPTION_SPATIAL8 ||
3325                         option == DITHER_OPTION_SPATIAL8_FM6        ||
3326                         option == DITHER_OPTION_TRUN10_SPATIAL8      ||
3327                         option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
3328                 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
3329                 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1;
3330                 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
3331                 fmt_bit_depth->flags.RGB_RANDOM =
3332                                 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
3333         } else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM ||
3334                         option == DITHER_OPTION_SPATIAL10 ||
3335                         option == DITHER_OPTION_SPATIAL10_FM8 ||
3336                         option == DITHER_OPTION_SPATIAL10_FM6) {
3337                 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
3338                 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2;
3339                 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
3340                 fmt_bit_depth->flags.RGB_RANDOM =
3341                                 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
3342         }
3343
3344         if (option == DITHER_OPTION_SPATIAL6 ||
3345                         option == DITHER_OPTION_SPATIAL8 ||
3346                         option == DITHER_OPTION_SPATIAL10) {
3347                 fmt_bit_depth->flags.FRAME_RANDOM = 0;
3348         } else {
3349                 fmt_bit_depth->flags.FRAME_RANDOM = 1;
3350         }
3351
3352         //////////////////////
3353         //// temporal dither
3354         //////////////////////
3355         if (option == DITHER_OPTION_FM6           ||
3356                         option == DITHER_OPTION_SPATIAL8_FM6     ||
3357                         option == DITHER_OPTION_SPATIAL10_FM6     ||
3358                         option == DITHER_OPTION_TRUN10_FM6     ||
3359                         option == DITHER_OPTION_TRUN8_FM6      ||
3360                         option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
3361                 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
3362                 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0;
3363         } else if (option == DITHER_OPTION_FM8        ||
3364                         option == DITHER_OPTION_SPATIAL10_FM8  ||
3365                         option == DITHER_OPTION_TRUN10_FM8) {
3366                 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
3367                 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1;
3368         } else if (option == DITHER_OPTION_FM10) {
3369                 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
3370                 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2;
3371         }
3372
3373         fmt_bit_depth->pixel_encoding = pixel_encoding;
3374 }
3375
3376 enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)
3377 {
3378         struct dc_link *link = stream->link;
3379         struct timing_generator *tg = dc->res_pool->timing_generators[0];
3380         enum dc_status res = DC_OK;
3381
3382         calculate_phy_pix_clks(stream);
3383
3384         if (!tg->funcs->validate_timing(tg, &stream->timing))
3385                 res = DC_FAIL_CONTROLLER_VALIDATE;
3386
3387         if (res == DC_OK) {
3388                 if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
3389                                 !link->link_enc->funcs->validate_output_with_stream(
3390                                                 link->link_enc, stream))
3391                         res = DC_FAIL_ENC_VALIDATE;
3392         }
3393
3394         /* TODO: validate audio ASIC caps, encoder */
3395
3396         if (res == DC_OK)
3397                 res = dc_link_validate_mode_timing(stream,
3398                       link,
3399                       &stream->timing);
3400
3401         return res;
3402 }
3403
3404 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state)
3405 {
3406         enum dc_status res = DC_OK;
3407
3408         /* check if surface has invalid dimensions */
3409         if (plane_state->src_rect.width == 0 || plane_state->src_rect.height == 0 ||
3410                 plane_state->dst_rect.width == 0 || plane_state->dst_rect.height == 0)
3411                 return DC_FAIL_SURFACE_VALIDATE;
3412
3413         /* TODO For now validates pixel format only */
3414         if (dc->res_pool->funcs->validate_plane)
3415                 return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps);
3416
3417         return res;
3418 }
3419
3420 unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format)
3421 {
3422         switch (format) {
3423         case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
3424                 return 8;
3425         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
3426         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
3427                 return 12;
3428         case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
3429         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
3430         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
3431         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
3432                 return 16;
3433         case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
3434         case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
3435         case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
3436         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
3437         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
3438         case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
3439         case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
3440                 return 32;
3441         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
3442         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
3443         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
3444         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
3445                 return 64;
3446         default:
3447                 ASSERT_CRITICAL(false);
3448                 return -1;
3449         }
3450 }
3451 static unsigned int get_max_audio_sample_rate(struct audio_mode *modes)
3452 {
3453         if (modes) {
3454                 if (modes->sample_rates.rate.RATE_192)
3455                         return 192000;
3456                 if (modes->sample_rates.rate.RATE_176_4)
3457                         return 176400;
3458                 if (modes->sample_rates.rate.RATE_96)
3459                         return 96000;
3460                 if (modes->sample_rates.rate.RATE_88_2)
3461                         return 88200;
3462                 if (modes->sample_rates.rate.RATE_48)
3463                         return 48000;
3464                 if (modes->sample_rates.rate.RATE_44_1)
3465                         return 44100;
3466                 if (modes->sample_rates.rate.RATE_32)
3467                         return 32000;
3468         }
3469         /*original logic when no audio info*/
3470         return 441000;
3471 }
3472
3473 void get_audio_check(struct audio_info *aud_modes,
3474         struct audio_check *audio_chk)
3475 {
3476         unsigned int i;
3477         unsigned int max_sample_rate = 0;
3478
3479         if (aud_modes) {
3480                 audio_chk->audio_packet_type = 0x2;/*audio sample packet AP = .25 for layout0, 1 for layout1*/
3481
3482                 audio_chk->max_audiosample_rate = 0;
3483                 for (i = 0; i < aud_modes->mode_count; i++) {
3484                         max_sample_rate = get_max_audio_sample_rate(&aud_modes->modes[i]);
3485                         if (audio_chk->max_audiosample_rate < max_sample_rate)
3486                                 audio_chk->max_audiosample_rate = max_sample_rate;
3487                         /*dts takes the same as type 2: AP = 0.25*/
3488                 }
3489                 /*check which one take more bandwidth*/
3490                 if (audio_chk->max_audiosample_rate > 192000)
3491                         audio_chk->audio_packet_type = 0x9;/*AP =1*/
3492                 audio_chk->acat = 0;/*not support*/
3493         }
3494 }
3495
3496 static struct hpo_dp_link_encoder *get_temp_hpo_dp_link_enc(
3497                 const struct resource_context *res_ctx,
3498                 const struct resource_pool *const pool,
3499                 const struct dc_link *link)
3500 {
3501         struct hpo_dp_link_encoder *hpo_dp_link_enc = NULL;
3502         int enc_index;
3503
3504         enc_index = find_acquired_hpo_dp_link_enc_for_link(res_ctx, link);
3505
3506         if (enc_index < 0)
3507                 enc_index = find_free_hpo_dp_link_enc(res_ctx, pool);
3508
3509         if (enc_index >= 0)
3510                 hpo_dp_link_enc = pool->hpo_dp_link_enc[enc_index];
3511
3512         return hpo_dp_link_enc;
3513 }
3514
3515 bool get_temp_dp_link_res(struct dc_link *link,
3516                 struct link_resource *link_res,
3517                 struct dc_link_settings *link_settings)
3518 {
3519         const struct dc *dc  = link->dc;
3520         const struct resource_context *res_ctx = &dc->current_state->res_ctx;
3521
3522         memset(link_res, 0, sizeof(*link_res));
3523
3524         if (dp_get_link_encoding_format(link_settings) == DP_128b_132b_ENCODING) {
3525                 link_res->hpo_dp_link_enc = get_temp_hpo_dp_link_enc(res_ctx,
3526                                 dc->res_pool, link);
3527                 if (!link_res->hpo_dp_link_enc)
3528                         return false;
3529         }
3530         return true;
3531 }
3532
3533 void reset_syncd_pipes_from_disabled_pipes(struct dc *dc,
3534                 struct dc_state *context)
3535 {
3536         int i, j;
3537         struct pipe_ctx *pipe_ctx_old, *pipe_ctx, *pipe_ctx_syncd;
3538
3539         /* If pipe backend is reset, need to reset pipe syncd status */
3540         for (i = 0; i < dc->res_pool->pipe_count; i++) {
3541                 pipe_ctx_old =  &dc->current_state->res_ctx.pipe_ctx[i];
3542                 pipe_ctx = &context->res_ctx.pipe_ctx[i];
3543
3544                 if (!pipe_ctx_old->stream)
3545                         continue;
3546
3547                 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe)
3548                         continue;
3549
3550                 if (!pipe_ctx->stream ||
3551                                 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
3552
3553                         /* Reset all the syncd pipes from the disabled pipe */
3554                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
3555                                 pipe_ctx_syncd = &context->res_ctx.pipe_ctx[j];
3556                                 if ((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx_syncd) == pipe_ctx_old->pipe_idx) ||
3557                                         !IS_PIPE_SYNCD_VALID(pipe_ctx_syncd))
3558                                         SET_PIPE_SYNCD_TO_PIPE(pipe_ctx_syncd, j);
3559                         }
3560                 }
3561         }
3562 }
3563
3564 void check_syncd_pipes_for_disabled_master_pipe(struct dc *dc,
3565         struct dc_state *context,
3566         uint8_t disabled_master_pipe_idx)
3567 {
3568         int i;
3569         struct pipe_ctx *pipe_ctx, *pipe_ctx_check;
3570
3571         pipe_ctx = &context->res_ctx.pipe_ctx[disabled_master_pipe_idx];
3572         if ((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx) != disabled_master_pipe_idx) ||
3573                 !IS_PIPE_SYNCD_VALID(pipe_ctx))
3574                 SET_PIPE_SYNCD_TO_PIPE(pipe_ctx, disabled_master_pipe_idx);
3575
3576         /* for the pipe disabled, check if any slave pipe exists and assert */
3577         for (i = 0; i < dc->res_pool->pipe_count; i++) {
3578                 pipe_ctx_check = &context->res_ctx.pipe_ctx[i];
3579
3580                 if ((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx_check) == disabled_master_pipe_idx) &&
3581                         IS_PIPE_SYNCD_VALID(pipe_ctx_check) && (i != disabled_master_pipe_idx))
3582                         DC_ERR("DC: Failure: pipe_idx[%d] syncd with disabled master pipe_idx[%d]\n",
3583                                 i, disabled_master_pipe_idx);
3584         }
3585 }
3586
3587 uint8_t resource_transmitter_to_phy_idx(const struct dc *dc, enum transmitter transmitter)
3588 {
3589         /* TODO - get transmitter to phy idx mapping from DMUB */
3590         uint8_t phy_idx = transmitter - TRANSMITTER_UNIPHY_A;
3591
3592         if (dc->ctx->dce_version == DCN_VERSION_3_1 &&
3593                         dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {
3594                 switch (transmitter) {
3595                 case TRANSMITTER_UNIPHY_A:
3596                         phy_idx = 0;
3597                         break;
3598                 case TRANSMITTER_UNIPHY_B:
3599                         phy_idx = 1;
3600                         break;
3601                 case TRANSMITTER_UNIPHY_C:
3602                         phy_idx = 5;
3603                         break;
3604                 case TRANSMITTER_UNIPHY_D:
3605                         phy_idx = 6;
3606                         break;
3607                 case TRANSMITTER_UNIPHY_E:
3608                         phy_idx = 4;
3609                         break;
3610                 default:
3611                         phy_idx = 0;
3612                         break;
3613                 }
3614         }
3615
3616         return phy_idx;
3617 }
3618
3619 const struct link_hwss *get_link_hwss(const struct dc_link *link,
3620                 const struct link_resource *link_res)
3621 {
3622         /* Link_hwss is only accessible by getter function instead of accessing
3623          * by pointers in dc with the intent to protect against breaking polymorphism.
3624          */
3625         if (can_use_hpo_dp_link_hwss(link, link_res))
3626                 /* TODO: some assumes that if decided link settings is 128b/132b
3627                  * channel coding format hpo_dp_link_enc should be used.
3628                  * Others believe that if hpo_dp_link_enc is available in link
3629                  * resource then hpo_dp_link_enc must be used. This bound between
3630                  * hpo_dp_link_enc != NULL and decided link settings is loosely coupled
3631                  * with a premise that both hpo_dp_link_enc pointer and decided link
3632                  * settings are determined based on single policy function like
3633                  * "decide_link_settings" from upper layer. This "convention"
3634                  * cannot be maintained and enforced at current level.
3635                  * Therefore a refactor is due so we can enforce a strong bound
3636                  * between those two parameters at this level.
3637                  *
3638                  * To put it simple, we want to make enforcement at low level so that
3639                  * we will not return link hwss if caller plans to do 8b/10b
3640                  * with an hpo encoder. Or we can return a very dummy one that doesn't
3641                  * do work for all functions
3642                  */
3643                 return get_hpo_dp_link_hwss();
3644         else if (can_use_dpia_link_hwss(link, link_res))
3645                 return get_dpia_link_hwss();
3646         else if (can_use_dio_link_hwss(link, link_res))
3647                 return get_dio_link_hwss();
3648         else
3649                 return get_virtual_link_hwss();
3650 }