drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

   1 /* Copyright 2015 Advanced Micro Devices, Inc. */
   2 #include "dm_services.h"
   3 #include "dc.h"
   4 #include "dc_link_dp.h"
   5 #include "dm_helpers.h"
   6 #include "opp.h"
   7 #include "dsc.h"
   8 #include "resource.h"
   9
  10 #include "inc/core_types.h"
  11 #include "link_hwss.h"
  12 #include "dc_link_ddc.h"
  13 #include "core_status.h"
  14 #include "dpcd_defs.h"
  15 #include "dc_dmub_srv.h"
  16 #include "dce/dmub_hw_lock_mgr.h"
  17 #include "inc/link_enc_cfg.h"
  18
  19 /*Travis*/
  20 static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
  21 /*Nutmeg*/
  22 static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
  23
  24 #define DC_LOGGER \
  25         link->ctx->logger
  26 #define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
  27
  28 #define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE   0x50
  29
  30         /* maximum pre emphasis level allowed for each voltage swing level*/
  31         static const enum dc_pre_emphasis
  32         voltage_swing_to_pre_emphasis[] = { PRE_EMPHASIS_LEVEL3,
  33                                             PRE_EMPHASIS_LEVEL2,
  34                                             PRE_EMPHASIS_LEVEL1,
  35                                             PRE_EMPHASIS_DISABLED };
  36
  37 enum {
  38         POST_LT_ADJ_REQ_LIMIT = 6,
  39         POST_LT_ADJ_REQ_TIMEOUT = 200
  40 };
  41
  42 enum {
  43         LINK_TRAINING_MAX_RETRY_COUNT = 5,
  44         /* to avoid infinite loop where-in the receiver
  45          * switches between different VS
  46          */
  47         LINK_TRAINING_MAX_CR_RETRY = 100
  48 };
  49
  50 static bool decide_fallback_link_setting(
  51                 struct dc_link_settings initial_link_settings,
  52                 struct dc_link_settings *current_link_setting,
  53                 enum link_training_result training_result);
  54 static struct dc_link_settings get_common_supported_link_settings(
  55                 struct dc_link_settings link_setting_a,
  56                 struct dc_link_settings link_setting_b);
  57
  58 static uint32_t get_cr_training_aux_rd_interval(struct dc_link *link,
  59                 const struct dc_link_settings *link_settings)
  60 {
  61         union training_aux_rd_interval training_rd_interval;
  62         uint32_t wait_in_micro_secs = 100;
  63
  64         memset(&training_rd_interval, 0, sizeof(training_rd_interval));
  65         core_link_read_dpcd(
  66                         link,
  67                         DP_TRAINING_AUX_RD_INTERVAL,
  68                         (uint8_t *)&training_rd_interval,
  69                         sizeof(training_rd_interval));
  70         if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
  71                 wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
  72         return wait_in_micro_secs;
  73 }
  74
  75 static uint32_t get_eq_training_aux_rd_interval(
  76         struct dc_link *link,
  77         const struct dc_link_settings *link_settings)
  78 {
  79         union training_aux_rd_interval training_rd_interval;
  80         uint32_t wait_in_micro_secs = 400;
  81
  82         memset(&training_rd_interval, 0, sizeof(training_rd_interval));
  83         /* overwrite the delay if rev > 1.1*/
  84         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
  85                 /* DP 1.2 or later - retrieve delay through
  86                  * "DPCD_ADDR_TRAINING_AUX_RD_INTERVAL" register */
  87                 core_link_read_dpcd(
  88                         link,
  89                         DP_TRAINING_AUX_RD_INTERVAL,
  90                         (uint8_t *)&training_rd_interval,
  91                         sizeof(training_rd_interval));
  92
  93                 if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
  94                         wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
  95         }
  96
  97         return wait_in_micro_secs;
  98 }
  99
 100 static void wait_for_training_aux_rd_interval(
 101         struct dc_link *link,
 102         uint32_t wait_in_micro_secs)
 103 {
 104         udelay(wait_in_micro_secs);
 105
 106         DC_LOG_HW_LINK_TRAINING("%s:\n wait = %d\n",
 107                 __func__,
 108                 wait_in_micro_secs);
 109 }
 110
 111 static enum dpcd_training_patterns
 112         dc_dp_training_pattern_to_dpcd_training_pattern(
 113         struct dc_link *link,
 114         enum dc_dp_training_pattern pattern)
 115 {
 116         enum dpcd_training_patterns dpcd_tr_pattern =
 117         DPCD_TRAINING_PATTERN_VIDEOIDLE;
 118
 119         switch (pattern) {
 120         case DP_TRAINING_PATTERN_SEQUENCE_1:
 121                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1;
 122                 break;
 123         case DP_TRAINING_PATTERN_SEQUENCE_2:
 124                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2;
 125                 break;
 126         case DP_TRAINING_PATTERN_SEQUENCE_3:
 127                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
 128                 break;
 129         case DP_TRAINING_PATTERN_SEQUENCE_4:
 130                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4;
 131                 break;
 132         case DP_TRAINING_PATTERN_VIDEOIDLE:
 133                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_VIDEOIDLE;
 134                 break;
 135         default:
 136                 ASSERT(0);
 137                 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
 138                         __func__, pattern);
 139                 break;
 140         }
 141
 142         return dpcd_tr_pattern;
 143 }
 144
 145 static void dpcd_set_training_pattern(
 146         struct dc_link *link,
 147         enum dc_dp_training_pattern training_pattern)
 148 {
 149         union dpcd_training_pattern dpcd_pattern = { {0} };
 150
 151         dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
 152                         dc_dp_training_pattern_to_dpcd_training_pattern(
 153                                         link, training_pattern);
 154
 155         core_link_write_dpcd(
 156                 link,
 157                 DP_TRAINING_PATTERN_SET,
 158                 &dpcd_pattern.raw,
 159                 1);
 160
 161         DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
 162                 __func__,
 163                 DP_TRAINING_PATTERN_SET,
 164                 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
 165 }
 166
 167 static enum dc_dp_training_pattern decide_cr_training_pattern(
 168                 const struct dc_link_settings *link_settings)
 169 {
 170         return DP_TRAINING_PATTERN_SEQUENCE_1;
 171 }
 172
 173 static enum dc_dp_training_pattern decide_eq_training_pattern(struct dc_link *link,
 174                 const struct dc_link_settings *link_settings)
 175 {
 176         struct link_encoder *link_enc;
 177         enum dc_dp_training_pattern highest_tp = DP_TRAINING_PATTERN_SEQUENCE_2;
 178         struct encoder_feature_support *features;
 179         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
 180
 181         /* Access link encoder capability based on whether it is statically
 182          * or dynamically assigned to a link.
 183          */
 184         if (link->is_dig_mapping_flexible &&
 185                         link->dc->res_pool->funcs->link_encs_assign)
 186                 link_enc = link_enc_cfg_get_link_enc_used_by_link(link->dc->current_state, link);
 187         else
 188                 link_enc = link->link_enc;
 189         ASSERT(link_enc);
 190         features = &link_enc->features;
 191
 192         if (features->flags.bits.IS_TPS3_CAPABLE)
 193                 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_3;
 194
 195         if (features->flags.bits.IS_TPS4_CAPABLE)
 196                 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_4;
 197
 198         if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED &&
 199                 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_4)
 200                 return DP_TRAINING_PATTERN_SEQUENCE_4;
 201
 202         if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED &&
 203                 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_3)
 204                 return DP_TRAINING_PATTERN_SEQUENCE_3;
 205
 206         return DP_TRAINING_PATTERN_SEQUENCE_2;
 207 }
 208
 209 static void dpcd_set_link_settings(
 210         struct dc_link *link,
 211         const struct link_training_settings *lt_settings)
 212 {
 213         uint8_t rate;
 214
 215         union down_spread_ctrl downspread = { {0} };
 216         union lane_count_set lane_count_set = { {0} };
 217
 218         downspread.raw = (uint8_t)
 219         (lt_settings->link_settings.link_spread);
 220
 221         lane_count_set.bits.LANE_COUNT_SET =
 222         lt_settings->link_settings.lane_count;
 223
 224         lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
 225         lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
 226
 227
 228         if (lt_settings->pattern_for_eq < DP_TRAINING_PATTERN_SEQUENCE_4) {
 229                 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
 230                                 link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
 231         }
 232
 233         core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
 234                 &downspread.raw, sizeof(downspread));
 235
 236         core_link_write_dpcd(link, DP_LANE_COUNT_SET,
 237                 &lane_count_set.raw, 1);
 238
 239         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
 240                         lt_settings->link_settings.use_link_rate_set == true) {
 241                 rate = 0;
 242                 /* WA for some MUX chips that will power down with eDP and lose supported
 243                  * link rate set for eDP 1.4. Source reads DPCD 0x010 again to ensure
 244                  * MUX chip gets link rate set back before link training.
 245                  */
 246                 if (link->connector_signal == SIGNAL_TYPE_EDP) {
 247                         uint8_t supported_link_rates[16];
 248
 249                         core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
 250                                         supported_link_rates, sizeof(supported_link_rates));
 251                 }
 252                 core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
 253                 core_link_write_dpcd(link, DP_LINK_RATE_SET,
 254                                 &lt_settings->link_settings.link_rate_set, 1);
 255         } else {
 256                 rate = (uint8_t) (lt_settings->link_settings.link_rate);
 257                 core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
 258         }
 259
 260         if (rate) {
 261                 DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
 262                         __func__,
 263                         DP_LINK_BW_SET,
 264                         lt_settings->link_settings.link_rate,
 265                         DP_LANE_COUNT_SET,
 266                         lt_settings->link_settings.lane_count,
 267                         lt_settings->enhanced_framing,
 268                         DP_DOWNSPREAD_CTRL,
 269                         lt_settings->link_settings.link_spread);
 270         } else {
 271                 DC_LOG_HW_LINK_TRAINING("%s\n %x rate set = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
 272                         __func__,
 273                         DP_LINK_RATE_SET,
 274                         lt_settings->link_settings.link_rate_set,
 275                         DP_LANE_COUNT_SET,
 276                         lt_settings->link_settings.lane_count,
 277                         lt_settings->enhanced_framing,
 278                         DP_DOWNSPREAD_CTRL,
 279                         lt_settings->link_settings.link_spread);
 280         }
 281 }
 282
 283 static uint8_t dc_dp_initialize_scrambling_data_symbols(
 284         struct dc_link *link,
 285         enum dc_dp_training_pattern pattern)
 286 {
 287         uint8_t disable_scrabled_data_symbols = 0;
 288
 289         switch (pattern) {
 290         case DP_TRAINING_PATTERN_SEQUENCE_1:
 291         case DP_TRAINING_PATTERN_SEQUENCE_2:
 292         case DP_TRAINING_PATTERN_SEQUENCE_3:
 293                 disable_scrabled_data_symbols = 1;
 294                 break;
 295         case DP_TRAINING_PATTERN_SEQUENCE_4:
 296                 disable_scrabled_data_symbols = 0;
 297                 break;
 298         default:
 299                 ASSERT(0);
 300                 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
 301                         __func__, pattern);
 302                 break;
 303         }
 304         return disable_scrabled_data_symbols;
 305 }
 306
 307 static inline bool is_repeater(struct dc_link *link, uint32_t offset)
 308 {
 309         return (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && (offset != 0);
 310 }
 311
 312 static void dpcd_set_lt_pattern_and_lane_settings(
 313         struct dc_link *link,
 314         const struct link_training_settings *lt_settings,
 315         enum dc_dp_training_pattern pattern,
 316         uint32_t offset)
 317 {
 318         union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = { { {0} } };
 319
 320         uint32_t dpcd_base_lt_offset;
 321
 322         uint8_t dpcd_lt_buffer[5] = {0};
 323         union dpcd_training_pattern dpcd_pattern = { {0} };
 324         uint32_t lane;
 325         uint32_t size_in_bytes;
 326         bool edp_workaround = false; /* TODO link_prop.INTERNAL */
 327         dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET;
 328
 329         if (is_repeater(link, offset))
 330                 dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
 331                         ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 332
 333         /*****************************************************************
 334         * DpcdAddress_TrainingPatternSet
 335         *****************************************************************/
 336         dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
 337                 dc_dp_training_pattern_to_dpcd_training_pattern(link, pattern);
 338
 339         dpcd_pattern.v1_4.SCRAMBLING_DISABLE =
 340                 dc_dp_initialize_scrambling_data_symbols(link, pattern);
 341
 342         dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - DP_TRAINING_PATTERN_SET]
 343                 = dpcd_pattern.raw;
 344
 345         if (is_repeater(link, offset)) {
 346                 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n 0x%X pattern = %x\n",
 347                         __func__,
 348                         offset,
 349                         dpcd_base_lt_offset,
 350                         dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
 351         } else {
 352                 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n",
 353                         __func__,
 354                         dpcd_base_lt_offset,
 355                         dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
 356         }
 357         /*****************************************************************
 358         * DpcdAddress_Lane0Set -> DpcdAddress_Lane3Set
 359         *****************************************************************/
 360         for (lane = 0; lane <
 361                 (uint32_t)(lt_settings->link_settings.lane_count); lane++) {
 362
 363                 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
 364                 (uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING);
 365                 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
 366                 (uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS);
 367
 368                 dpcd_lane[lane].bits.MAX_SWING_REACHED =
 369                 (lt_settings->lane_settings[lane].VOLTAGE_SWING ==
 370                 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
 371                 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
 372                 (lt_settings->lane_settings[lane].PRE_EMPHASIS ==
 373                 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
 374         }
 375
 376         /* concatenate everything into one buffer*/
 377
 378         size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]);
 379
 380          // 0x00103 - 0x00102
 381         memmove(
 382                 &dpcd_lt_buffer[DP_TRAINING_LANE0_SET - DP_TRAINING_PATTERN_SET],
 383                 dpcd_lane,
 384                 size_in_bytes);
 385
 386         if (is_repeater(link, offset)) {
 387                 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
 388                                 " 0x%X VS set = %x PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 389                         __func__,
 390                         offset,
 391                         dpcd_base_lt_offset,
 392                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 393                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 394                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 395                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 396         } else {
 397                 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 398                         __func__,
 399                         dpcd_base_lt_offset,
 400                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 401                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 402                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 403                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 404         }
 405         if (edp_workaround) {
 406                 /* for eDP write in 2 parts because the 5-byte burst is
 407                 * causing issues on some eDP panels (EPR#366724)
 408                 */
 409                 core_link_write_dpcd(
 410                         link,
 411                         DP_TRAINING_PATTERN_SET,
 412                         &dpcd_pattern.raw,
 413                         sizeof(dpcd_pattern.raw));
 414
 415                 core_link_write_dpcd(
 416                         link,
 417                         DP_TRAINING_LANE0_SET,
 418                         (uint8_t *)(dpcd_lane),
 419                         size_in_bytes);
 420
 421                 } else
 422                 /* write it all in (1 + number-of-lanes)-byte burst*/
 423                         core_link_write_dpcd(
 424                                 link,
 425                                 dpcd_base_lt_offset,
 426                                 dpcd_lt_buffer,
 427                                 size_in_bytes + sizeof(dpcd_pattern.raw));
 428
 429         link->cur_lane_setting = lt_settings->lane_settings[0];
 430 }
 431
 432 static bool is_cr_done(enum dc_lane_count ln_count,
 433         union lane_status *dpcd_lane_status)
 434 {
 435         uint32_t lane;
 436         /*LANEx_CR_DONE bits All 1's?*/
 437         for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
 438                 if (!dpcd_lane_status[lane].bits.CR_DONE_0)
 439                         return false;
 440         }
 441         return true;
 442 }
 443
 444 static bool is_ch_eq_done(enum dc_lane_count ln_count,
 445                 union lane_status *dpcd_lane_status)
 446 {
 447         bool done = true;
 448         uint32_t lane;
 449         for (lane = 0; lane < (uint32_t)(ln_count); lane++)
 450                 if (!dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0)
 451                         done = false;
 452         return done;
 453 }
 454
 455 static bool is_symbol_locked(enum dc_lane_count ln_count,
 456                 union lane_status *dpcd_lane_status)
 457 {
 458         bool locked = true;
 459         uint32_t lane;
 460         for (lane = 0; lane < (uint32_t)(ln_count); lane++)
 461                 if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0)
 462                         locked = false;
 463         return locked;
 464 }
 465
 466 static inline bool is_interlane_aligned(union lane_align_status_updated align_status)
 467 {
 468         return align_status.bits.INTERLANE_ALIGN_DONE == 1;
 469 }
 470
 471 static void update_drive_settings(
 472                 struct link_training_settings *dest,
 473                 struct link_training_settings src)
 474 {
 475         uint32_t lane;
 476         for (lane = 0; lane < src.link_settings.lane_count; lane++) {
 477                 if (dest->voltage_swing == NULL)
 478                         dest->lane_settings[lane].VOLTAGE_SWING = src.lane_settings[lane].VOLTAGE_SWING;
 479                 else
 480                         dest->lane_settings[lane].VOLTAGE_SWING = *dest->voltage_swing;
 481
 482                 if (dest->pre_emphasis == NULL)
 483                         dest->lane_settings[lane].PRE_EMPHASIS = src.lane_settings[lane].PRE_EMPHASIS;
 484                 else
 485                         dest->lane_settings[lane].PRE_EMPHASIS = *dest->pre_emphasis;
 486
 487                 if (dest->post_cursor2 == NULL)
 488                         dest->lane_settings[lane].POST_CURSOR2 = src.lane_settings[lane].POST_CURSOR2;
 489                 else
 490                         dest->lane_settings[lane].POST_CURSOR2 = *dest->post_cursor2;
 491         }
 492 }
 493
 494 static uint8_t get_nibble_at_index(const uint8_t *buf,
 495         uint32_t index)
 496 {
 497         uint8_t nibble;
 498         nibble = buf[index / 2];
 499
 500         if (index % 2)
 501                 nibble >>= 4;
 502         else
 503                 nibble &= 0x0F;
 504
 505         return nibble;
 506 }
 507
 508 static enum dc_pre_emphasis get_max_pre_emphasis_for_voltage_swing(
 509         enum dc_voltage_swing voltage)
 510 {
 511         enum dc_pre_emphasis pre_emphasis;
 512         pre_emphasis = PRE_EMPHASIS_MAX_LEVEL;
 513
 514         if (voltage <= VOLTAGE_SWING_MAX_LEVEL)
 515                 pre_emphasis = voltage_swing_to_pre_emphasis[voltage];
 516
 517         return pre_emphasis;
 518
 519 }
 520
 521 static void find_max_drive_settings(
 522         const struct link_training_settings *link_training_setting,
 523         struct link_training_settings *max_lt_setting)
 524 {
 525         uint32_t lane;
 526         struct dc_lane_settings max_requested;
 527
 528         max_requested.VOLTAGE_SWING =
 529                 link_training_setting->
 530                 lane_settings[0].VOLTAGE_SWING;
 531         max_requested.PRE_EMPHASIS =
 532                 link_training_setting->
 533                 lane_settings[0].PRE_EMPHASIS;
 534         /*max_requested.postCursor2 =
 535          * link_training_setting->laneSettings[0].postCursor2;*/
 536
 537         /* Determine what the maximum of the requested settings are*/
 538         for (lane = 1; lane < link_training_setting->link_settings.lane_count;
 539                         lane++) {
 540                 if (link_training_setting->lane_settings[lane].VOLTAGE_SWING >
 541                         max_requested.VOLTAGE_SWING)
 542
 543                         max_requested.VOLTAGE_SWING =
 544                         link_training_setting->
 545                         lane_settings[lane].VOLTAGE_SWING;
 546
 547                 if (link_training_setting->lane_settings[lane].PRE_EMPHASIS >
 548                                 max_requested.PRE_EMPHASIS)
 549                         max_requested.PRE_EMPHASIS =
 550                         link_training_setting->
 551                         lane_settings[lane].PRE_EMPHASIS;
 552
 553                 /*
 554                 if (link_training_setting->laneSettings[lane].postCursor2 >
 555                  max_requested.postCursor2)
 556                 {
 557                 max_requested.postCursor2 =
 558                 link_training_setting->laneSettings[lane].postCursor2;
 559                 }
 560                 */
 561         }
 562
 563         /* make sure the requested settings are
 564          * not higher than maximum settings*/
 565         if (max_requested.VOLTAGE_SWING > VOLTAGE_SWING_MAX_LEVEL)
 566                 max_requested.VOLTAGE_SWING = VOLTAGE_SWING_MAX_LEVEL;
 567
 568         if (max_requested.PRE_EMPHASIS > PRE_EMPHASIS_MAX_LEVEL)
 569                 max_requested.PRE_EMPHASIS = PRE_EMPHASIS_MAX_LEVEL;
 570         /*
 571         if (max_requested.postCursor2 > PostCursor2_MaxLevel)
 572         max_requested.postCursor2 = PostCursor2_MaxLevel;
 573         */
 574
 575         /* make sure the pre-emphasis matches the voltage swing*/
 576         if (max_requested.PRE_EMPHASIS >
 577                 get_max_pre_emphasis_for_voltage_swing(
 578                         max_requested.VOLTAGE_SWING))
 579                 max_requested.PRE_EMPHASIS =
 580                 get_max_pre_emphasis_for_voltage_swing(
 581                         max_requested.VOLTAGE_SWING);
 582
 583         /*
 584          * Post Cursor2 levels are completely independent from
 585          * pre-emphasis (Post Cursor1) levels. But Post Cursor2 levels
 586          * can only be applied to each allowable combination of voltage
 587          * swing and pre-emphasis levels */
 588          /* if ( max_requested.postCursor2 >
 589           *  getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing))
 590           *  max_requested.postCursor2 =
 591           *  getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing);
 592           */
 593
 594         max_lt_setting->link_settings.link_rate =
 595                 link_training_setting->link_settings.link_rate;
 596         max_lt_setting->link_settings.lane_count =
 597         link_training_setting->link_settings.lane_count;
 598         max_lt_setting->link_settings.link_spread =
 599                 link_training_setting->link_settings.link_spread;
 600
 601         for (lane = 0; lane <
 602                 link_training_setting->link_settings.lane_count;
 603                 lane++) {
 604                 max_lt_setting->lane_settings[lane].VOLTAGE_SWING =
 605                         max_requested.VOLTAGE_SWING;
 606                 max_lt_setting->lane_settings[lane].PRE_EMPHASIS =
 607                         max_requested.PRE_EMPHASIS;
 608                 /*max_lt_setting->laneSettings[lane].postCursor2 =
 609                  * max_requested.postCursor2;
 610                  */
 611         }
 612
 613 }
 614
 615 static void get_lane_status_and_drive_settings(
 616         struct dc_link *link,
 617         const struct link_training_settings *link_training_setting,
 618         union lane_status *ln_status,
 619         union lane_align_status_updated *ln_status_updated,
 620         struct link_training_settings *req_settings,
 621         uint32_t offset)
 622 {
 623         unsigned int lane01_status_address = DP_LANE0_1_STATUS;
 624         uint8_t lane_adjust_offset = 4;
 625         unsigned int lane01_adjust_address;
 626         uint8_t dpcd_buf[6] = {0};
 627         union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
 628         struct link_training_settings request_settings = { {0} };
 629         uint32_t lane;
 630
 631         memset(req_settings, '\0', sizeof(struct link_training_settings));
 632
 633         if (is_repeater(link, offset)) {
 634                 lane01_status_address =
 635                                 DP_LANE0_1_STATUS_PHY_REPEATER1 +
 636                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 637                 lane_adjust_offset = 3;
 638         }
 639
 640         core_link_read_dpcd(
 641                 link,
 642                 lane01_status_address,
 643                 (uint8_t *)(dpcd_buf),
 644                 sizeof(dpcd_buf));
 645
 646         for (lane = 0; lane <
 647                 (uint32_t)(link_training_setting->link_settings.lane_count);
 648                 lane++) {
 649
 650                 ln_status[lane].raw =
 651                         get_nibble_at_index(&dpcd_buf[0], lane);
 652                 dpcd_lane_adjust[lane].raw =
 653                         get_nibble_at_index(&dpcd_buf[lane_adjust_offset], lane);
 654         }
 655
 656         ln_status_updated->raw = dpcd_buf[2];
 657
 658         if (is_repeater(link, offset)) {
 659                 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
 660                                 " 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
 661                         __func__,
 662                         offset,
 663                         lane01_status_address, dpcd_buf[0],
 664                         lane01_status_address + 1, dpcd_buf[1]);
 665         } else {
 666                 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
 667                         __func__,
 668                         lane01_status_address, dpcd_buf[0],
 669                         lane01_status_address + 1, dpcd_buf[1]);
 670         }
 671         lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1;
 672
 673         if (is_repeater(link, offset))
 674                 lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 +
 675                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 676
 677         if (is_repeater(link, offset)) {
 678                 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
 679                                 " 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
 680                                         __func__,
 681                                         offset,
 682                                         lane01_adjust_address,
 683                                         dpcd_buf[lane_adjust_offset],
 684                                         lane01_adjust_address + 1,
 685                                         dpcd_buf[lane_adjust_offset + 1]);
 686         } else {
 687                 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
 688                         __func__,
 689                         lane01_adjust_address,
 690                         dpcd_buf[lane_adjust_offset],
 691                         lane01_adjust_address + 1,
 692                         dpcd_buf[lane_adjust_offset + 1]);
 693         }
 694
 695         /*copy to req_settings*/
 696         request_settings.link_settings.lane_count =
 697                 link_training_setting->link_settings.lane_count;
 698         request_settings.link_settings.link_rate =
 699                 link_training_setting->link_settings.link_rate;
 700         request_settings.link_settings.link_spread =
 701                 link_training_setting->link_settings.link_spread;
 702
 703         for (lane = 0; lane <
 704                 (uint32_t)(link_training_setting->link_settings.lane_count);
 705                 lane++) {
 706
 707                 request_settings.lane_settings[lane].VOLTAGE_SWING =
 708                         (enum dc_voltage_swing)(dpcd_lane_adjust[lane].bits.
 709                                 VOLTAGE_SWING_LANE);
 710                 request_settings.lane_settings[lane].PRE_EMPHASIS =
 711                         (enum dc_pre_emphasis)(dpcd_lane_adjust[lane].bits.
 712                                 PRE_EMPHASIS_LANE);
 713         }
 714
 715         /*Note: for postcursor2, read adjusted
 716          * postcursor2 settings from*/
 717         /*DpcdAddress_AdjustRequestPostCursor2 =
 718          *0x020C (not implemented yet)*/
 719
 720         /* we find the maximum of the requested settings across all lanes*/
 721         /* and set this maximum for all lanes*/
 722         find_max_drive_settings(&request_settings, req_settings);
 723
 724         /* if post cursor 2 is needed in the future,
 725          * read DpcdAddress_AdjustRequestPostCursor2 = 0x020C
 726          */
 727
 728 }
 729
 730 static void dpcd_set_lane_settings(
 731         struct dc_link *link,
 732         const struct link_training_settings *link_training_setting,
 733         uint32_t offset)
 734 {
 735         union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
 736         uint32_t lane;
 737         unsigned int lane0_set_address;
 738
 739         lane0_set_address = DP_TRAINING_LANE0_SET;
 740
 741         if (is_repeater(link, offset))
 742                 lane0_set_address = DP_TRAINING_LANE0_SET_PHY_REPEATER1 +
 743                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 744
 745         for (lane = 0; lane <
 746                 (uint32_t)(link_training_setting->
 747                 link_settings.lane_count);
 748                 lane++) {
 749                 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
 750                         (uint8_t)(link_training_setting->
 751                         lane_settings[lane].VOLTAGE_SWING);
 752                 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
 753                         (uint8_t)(link_training_setting->
 754                         lane_settings[lane].PRE_EMPHASIS);
 755                 dpcd_lane[lane].bits.MAX_SWING_REACHED =
 756                         (link_training_setting->
 757                         lane_settings[lane].VOLTAGE_SWING ==
 758                         VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
 759                 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
 760                         (link_training_setting->
 761                         lane_settings[lane].PRE_EMPHASIS ==
 762                         PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
 763         }
 764
 765         core_link_write_dpcd(link,
 766                 lane0_set_address,
 767                 (uint8_t *)(dpcd_lane),
 768                 link_training_setting->link_settings.lane_count);
 769
 770         /*
 771         if (LTSettings.link.rate == LinkRate_High2)
 772         {
 773                 DpcdTrainingLaneSet2 dpcd_lane2[lane_count_DPMax] = {0};
 774                 for ( uint32_t lane = 0;
 775                 lane < lane_count_DPMax; lane++)
 776                 {
 777                         dpcd_lane2[lane].bits.post_cursor2_set =
 778                         static_cast<unsigned char>(
 779                         LTSettings.laneSettings[lane].postCursor2);
 780                         dpcd_lane2[lane].bits.max_post_cursor2_reached = 0;
 781                 }
 782                 m_pDpcdAccessSrv->WriteDpcdData(
 783                 DpcdAddress_Lane0Set2,
 784                 reinterpret_cast<unsigned char*>(dpcd_lane2),
 785                 LTSettings.link.lanes);
 786         }
 787         */
 788
 789         if (is_repeater(link, offset)) {
 790                 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n"
 791                                 " 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 792                         __func__,
 793                         offset,
 794                         lane0_set_address,
 795                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 796                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 797                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 798                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 799
 800         } else {
 801                 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 802                         __func__,
 803                         lane0_set_address,
 804                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 805                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 806                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 807                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 808         }
 809         link->cur_lane_setting = link_training_setting->lane_settings[0];
 810
 811 }
 812
 813 static bool is_max_vs_reached(
 814         const struct link_training_settings *lt_settings)
 815 {
 816         uint32_t lane;
 817         for (lane = 0; lane <
 818                 (uint32_t)(lt_settings->link_settings.lane_count);
 819                 lane++) {
 820                 if (lt_settings->lane_settings[lane].VOLTAGE_SWING
 821                         == VOLTAGE_SWING_MAX_LEVEL)
 822                         return true;
 823         }
 824         return false;
 825
 826 }
 827
 828 static bool perform_post_lt_adj_req_sequence(
 829         struct dc_link *link,
 830         struct link_training_settings *lt_settings)
 831 {
 832         enum dc_lane_count lane_count =
 833         lt_settings->link_settings.lane_count;
 834
 835         uint32_t adj_req_count;
 836         uint32_t adj_req_timer;
 837         bool req_drv_setting_changed;
 838         uint32_t lane;
 839
 840         req_drv_setting_changed = false;
 841         for (adj_req_count = 0; adj_req_count < POST_LT_ADJ_REQ_LIMIT;
 842         adj_req_count++) {
 843
 844                 req_drv_setting_changed = false;
 845
 846                 for (adj_req_timer = 0;
 847                         adj_req_timer < POST_LT_ADJ_REQ_TIMEOUT;
 848                         adj_req_timer++) {
 849
 850                         struct link_training_settings req_settings;
 851                         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
 852                         union lane_align_status_updated
 853                                 dpcd_lane_status_updated;
 854
 855                         get_lane_status_and_drive_settings(
 856                         link,
 857                         lt_settings,
 858                         dpcd_lane_status,
 859                         &dpcd_lane_status_updated,
 860                         &req_settings,
 861                         DPRX);
 862
 863                         if (dpcd_lane_status_updated.bits.
 864                                         POST_LT_ADJ_REQ_IN_PROGRESS == 0)
 865                                 return true;
 866
 867                         if (!is_cr_done(lane_count, dpcd_lane_status))
 868                                 return false;
 869
 870                         if (!is_ch_eq_done(lane_count, dpcd_lane_status) ||
 871                                         !is_symbol_locked(lane_count, dpcd_lane_status) ||
 872                                         !is_interlane_aligned(dpcd_lane_status_updated))
 873                                 return false;
 874
 875                         for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
 876
 877                                 if (lt_settings->
 878                                 lane_settings[lane].VOLTAGE_SWING !=
 879                                 req_settings.lane_settings[lane].
 880                                 VOLTAGE_SWING ||
 881                                 lt_settings->lane_settings[lane].PRE_EMPHASIS !=
 882                                 req_settings.lane_settings[lane].PRE_EMPHASIS) {
 883
 884                                         req_drv_setting_changed = true;
 885                                         break;
 886                                 }
 887                         }
 888
 889                         if (req_drv_setting_changed) {
 890                                 update_drive_settings(
 891                                         lt_settings, req_settings);
 892
 893                                 dc_link_dp_set_drive_settings(link,
 894                                                 lt_settings);
 895                                 break;
 896                         }
 897
 898                         msleep(1);
 899                 }
 900
 901                 if (!req_drv_setting_changed) {
 902                         DC_LOG_WARNING("%s: Post Link Training Adjust Request Timed out\n",
 903                                 __func__);
 904
 905                         ASSERT(0);
 906                         return true;
 907                 }
 908         }
 909         DC_LOG_WARNING("%s: Post Link Training Adjust Request limit reached\n",
 910                 __func__);
 911
 912         ASSERT(0);
 913         return true;
 914
 915 }
 916
 917 /* Only used for channel equalization */
 918 static uint32_t translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval)
 919 {
 920         unsigned int aux_rd_interval_us = 400;
 921
 922         switch (dpcd_aux_read_interval) {
 923         case 0x01:
 924                 aux_rd_interval_us = 4000;
 925                 break;
 926         case 0x02:
 927                 aux_rd_interval_us = 8000;
 928                 break;
 929         case 0x03:
 930                 aux_rd_interval_us = 12000;
 931                 break;
 932         case 0x04:
 933                 aux_rd_interval_us = 16000;
 934                 break;
 935         default:
 936                 break;
 937         }
 938
 939         return aux_rd_interval_us;
 940 }
 941
 942 static enum link_training_result get_cr_failure(enum dc_lane_count ln_count,
 943                                         union lane_status *dpcd_lane_status)
 944 {
 945         enum link_training_result result = LINK_TRAINING_SUCCESS;
 946
 947         if (ln_count >= LANE_COUNT_ONE && !dpcd_lane_status[0].bits.CR_DONE_0)
 948                 result = LINK_TRAINING_CR_FAIL_LANE0;
 949         else if (ln_count >= LANE_COUNT_TWO && !dpcd_lane_status[1].bits.CR_DONE_0)
 950                 result = LINK_TRAINING_CR_FAIL_LANE1;
 951         else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[2].bits.CR_DONE_0)
 952                 result = LINK_TRAINING_CR_FAIL_LANE23;
 953         else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[3].bits.CR_DONE_0)
 954                 result = LINK_TRAINING_CR_FAIL_LANE23;
 955         return result;
 956 }
 957
 958 static enum link_training_result perform_channel_equalization_sequence(
 959         struct dc_link *link,
 960         struct link_training_settings *lt_settings,
 961         uint32_t offset)
 962 {
 963         struct link_training_settings req_settings;
 964         enum dc_dp_training_pattern tr_pattern;
 965         uint32_t retries_ch_eq;
 966         uint32_t wait_time_microsec;
 967         enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
 968         union lane_align_status_updated dpcd_lane_status_updated = { {0} };
 969         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
 970
 971         /* Note: also check that TPS4 is a supported feature*/
 972
 973         tr_pattern = lt_settings->pattern_for_eq;
 974
 975         if (is_repeater(link, offset))
 976                 tr_pattern = DP_TRAINING_PATTERN_SEQUENCE_4;
 977
 978         dp_set_hw_training_pattern(link, tr_pattern, offset);
 979
 980         for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT;
 981                 retries_ch_eq++) {
 982
 983                 dp_set_hw_lane_settings(link, lt_settings, offset);
 984
 985                 /* 2. update DPCD*/
 986                 if (!retries_ch_eq)
 987                         /* EPR #361076 - write as a 5-byte burst,
 988                          * but only for the 1-st iteration
 989                          */
 990
 991                         dpcd_set_lt_pattern_and_lane_settings(
 992                                 link,
 993                                 lt_settings,
 994                                 tr_pattern, offset);
 995                 else
 996                         dpcd_set_lane_settings(link, lt_settings, offset);
 997
 998                 /* 3. wait for receiver to lock-on*/
 999                 wait_time_microsec = lt_settings->eq_pattern_time;
1000
1001                 if (is_repeater(link, offset))
1002                         wait_time_microsec =
1003                                         translate_training_aux_read_interval(
1004                                                 link->dpcd_caps.lttpr_caps.aux_rd_interval[offset - 1]);
1005
1006                 wait_for_training_aux_rd_interval(
1007                                 link,
1008                                 wait_time_microsec);
1009
1010                 /* 4. Read lane status and requested
1011                  * drive settings as set by the sink*/
1012
1013                 get_lane_status_and_drive_settings(
1014                         link,
1015                         lt_settings,
1016                         dpcd_lane_status,
1017                         &dpcd_lane_status_updated,
1018                         &req_settings,
1019                         offset);
1020
1021                 /* 5. check CR done*/
1022                 if (!is_cr_done(lane_count, dpcd_lane_status))
1023                         return LINK_TRAINING_EQ_FAIL_CR;
1024
1025                 /* 6. check CHEQ done*/
1026                 if (is_ch_eq_done(lane_count, dpcd_lane_status) &&
1027                                 is_symbol_locked(lane_count, dpcd_lane_status) &&
1028                                 is_interlane_aligned(dpcd_lane_status_updated))
1029                         return LINK_TRAINING_SUCCESS;
1030
1031                 /* 7. update VS/PE/PC2 in lt_settings*/
1032                 update_drive_settings(lt_settings, req_settings);
1033         }
1034
1035         return LINK_TRAINING_EQ_FAIL_EQ;
1036
1037 }
1038 #define TRAINING_AUX_RD_INTERVAL 100 //us
1039
1040 static void start_clock_recovery_pattern_early(struct dc_link *link,
1041                 struct link_training_settings *lt_settings,
1042                 uint32_t offset)
1043 {
1044         DC_LOG_HW_LINK_TRAINING("%s\n GPU sends TPS1. Wait 400us.\n",
1045                         __func__);
1046         dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset);
1047         dp_set_hw_lane_settings(link, lt_settings, offset);
1048         udelay(400);
1049 }
1050
1051 static enum link_training_result perform_clock_recovery_sequence(
1052         struct dc_link *link,
1053         struct link_training_settings *lt_settings,
1054         uint32_t offset)
1055 {
1056         uint32_t retries_cr;
1057         uint32_t retry_count;
1058         uint32_t wait_time_microsec;
1059         struct link_training_settings req_settings;
1060         enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
1061         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
1062         union lane_align_status_updated dpcd_lane_status_updated;
1063
1064         retries_cr = 0;
1065         retry_count = 0;
1066
1067         if (!link->ctx->dc->work_arounds.lt_early_cr_pattern)
1068                 dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset);
1069
1070         /* najeeb - The synaptics MST hub can put the LT in
1071         * infinite loop by switching the VS
1072         */
1073         /* between level 0 and level 1 continuously, here
1074         * we try for CR lock for LinkTrainingMaxCRRetry count*/
1075         while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
1076                 (retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
1077
1078                 memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
1079                 memset(&dpcd_lane_status_updated, '\0',
1080                 sizeof(dpcd_lane_status_updated));
1081
1082                 /* 1. call HWSS to set lane settings*/
1083                 dp_set_hw_lane_settings(
1084                                 link,
1085                                 lt_settings,
1086                                 offset);
1087
1088                 /* 2. update DPCD of the receiver*/
1089                 if (!retry_count)
1090                         /* EPR #361076 - write as a 5-byte burst,
1091                          * but only for the 1-st iteration.*/
1092                         dpcd_set_lt_pattern_and_lane_settings(
1093                                         link,
1094                                         lt_settings,
1095                                         lt_settings->pattern_for_cr,
1096                                         offset);
1097                 else
1098                         dpcd_set_lane_settings(
1099                                         link,
1100                                         lt_settings,
1101                                         offset);
1102
1103                 /* 3. wait receiver to lock-on*/
1104                 wait_time_microsec = lt_settings->cr_pattern_time;
1105
1106                 if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
1107                         wait_time_microsec = TRAINING_AUX_RD_INTERVAL;
1108
1109                 wait_for_training_aux_rd_interval(
1110                                 link,
1111                                 wait_time_microsec);
1112
1113                 /* 4. Read lane status and requested drive
1114                 * settings as set by the sink
1115                 */
1116                 get_lane_status_and_drive_settings(
1117                                 link,
1118                                 lt_settings,
1119                                 dpcd_lane_status,
1120                                 &dpcd_lane_status_updated,
1121                                 &req_settings,
1122                                 offset);
1123
1124                 /* 5. check CR done*/
1125                 if (is_cr_done(lane_count, dpcd_lane_status))
1126                         return LINK_TRAINING_SUCCESS;
1127
1128                 /* 6. max VS reached*/
1129                 if (is_max_vs_reached(lt_settings))
1130                         break;
1131
1132                 /* 7. same lane settings*/
1133                 /* Note: settings are the same for all lanes,
1134                  * so comparing first lane is sufficient*/
1135                 if ((lt_settings->lane_settings[0].VOLTAGE_SWING ==
1136                         req_settings.lane_settings[0].VOLTAGE_SWING)
1137                         && (lt_settings->lane_settings[0].PRE_EMPHASIS ==
1138                                 req_settings.lane_settings[0].PRE_EMPHASIS))
1139                         retries_cr++;
1140                 else
1141                         retries_cr = 0;
1142
1143                 /* 8. update VS/PE/PC2 in lt_settings*/
1144                 update_drive_settings(lt_settings, req_settings);
1145
1146                 retry_count++;
1147         }
1148
1149         if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
1150                 ASSERT(0);
1151                 DC_LOG_ERROR("%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue",
1152                         __func__,
1153                         LINK_TRAINING_MAX_CR_RETRY);
1154
1155         }
1156
1157         return get_cr_failure(lane_count, dpcd_lane_status);
1158 }
1159
1160 static inline enum link_training_result dp_transition_to_video_idle(
1161         struct dc_link *link,
1162         struct link_training_settings *lt_settings,
1163         enum link_training_result status)
1164 {
1165         union lane_count_set lane_count_set = { {0} };
1166
1167         /* 4. mainlink output idle pattern*/
1168         dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1169
1170         /*
1171          * 5. post training adjust if required
1172          * If the upstream DPTX and downstream DPRX both support TPS4,
1173          * TPS4 must be used instead of POST_LT_ADJ_REQ.
1174          */
1175         if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||
1176                         lt_settings->pattern_for_eq == DP_TRAINING_PATTERN_SEQUENCE_4)
1177                 return status;
1178
1179         if (status == LINK_TRAINING_SUCCESS &&
1180                 perform_post_lt_adj_req_sequence(link, lt_settings) == false)
1181                 status = LINK_TRAINING_LQA_FAIL;
1182
1183         lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;
1184         lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
1185         lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
1186
1187         core_link_write_dpcd(
1188                 link,
1189                 DP_LANE_COUNT_SET,
1190                 &lane_count_set.raw,
1191                 sizeof(lane_count_set));
1192
1193         return status;
1194 }
1195
1196 enum link_training_result dp_check_link_loss_status(
1197         struct dc_link *link,
1198         const struct link_training_settings *link_training_setting)
1199 {
1200         enum link_training_result status = LINK_TRAINING_SUCCESS;
1201         union lane_status lane_status;
1202         uint8_t dpcd_buf[6] = {0};
1203         uint32_t lane;
1204
1205         core_link_read_dpcd(
1206                         link,
1207                         DP_SINK_COUNT,
1208                         (uint8_t *)(dpcd_buf),
1209                         sizeof(dpcd_buf));
1210
1211         /*parse lane status*/
1212         for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
1213                 /*
1214                  * check lanes status
1215                  */
1216                 lane_status.raw = get_nibble_at_index(&dpcd_buf[2], lane);
1217
1218                 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
1219                         !lane_status.bits.CR_DONE_0 ||
1220                         !lane_status.bits.SYMBOL_LOCKED_0) {
1221                         /* if one of the channel equalization, clock
1222                          * recovery or symbol lock is dropped
1223                          * consider it as (link has been
1224                          * dropped) dp sink status has changed
1225                          */
1226                         status = LINK_TRAINING_LINK_LOSS;
1227                         break;
1228                 }
1229         }
1230
1231         return status;
1232 }
1233
1234 static inline void decide_8b_10b_training_settings(
1235          struct dc_link *link,
1236         const struct dc_link_settings *link_setting,
1237         const struct dc_link_training_overrides *overrides,
1238         struct link_training_settings *lt_settings)
1239 {
1240         uint32_t lane;
1241
1242         memset(lt_settings, '\0', sizeof(struct link_training_settings));
1243
1244         /* Initialize link settings */
1245         lt_settings->link_settings.use_link_rate_set = link_setting->use_link_rate_set;
1246         lt_settings->link_settings.link_rate_set = link_setting->link_rate_set;
1247
1248         if (link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
1249                 lt_settings->link_settings.link_rate = link->preferred_link_setting.link_rate;
1250         else
1251                 lt_settings->link_settings.link_rate = link_setting->link_rate;
1252
1253         if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN)
1254                 lt_settings->link_settings.lane_count = link->preferred_link_setting.lane_count;
1255         else
1256                 lt_settings->link_settings.lane_count = link_setting->lane_count;
1257
1258         /*@todo[vdevulap] move SS to LS, should not be handled by displaypath*/
1259
1260         /* TODO hard coded to SS for now
1261          * lt_settings.link_settings.link_spread =
1262          * dal_display_path_is_ss_supported(
1263          * path_mode->display_path) ?
1264          * LINK_SPREAD_05_DOWNSPREAD_30KHZ :
1265          * LINK_SPREAD_DISABLED;
1266          */
1267         /* Initialize link spread */
1268         if (link->dp_ss_off)
1269                 lt_settings->link_settings.link_spread = LINK_SPREAD_DISABLED;
1270         else if (overrides->downspread != NULL)
1271                 lt_settings->link_settings.link_spread
1272                         = *overrides->downspread
1273                         ? LINK_SPREAD_05_DOWNSPREAD_30KHZ
1274                         : LINK_SPREAD_DISABLED;
1275         else
1276                 lt_settings->link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ;
1277
1278         lt_settings->lttpr_mode = link->lttpr_mode;
1279
1280         /* Initialize lane settings overrides */
1281         if (overrides->voltage_swing != NULL)
1282                 lt_settings->voltage_swing = overrides->voltage_swing;
1283
1284         if (overrides->pre_emphasis != NULL)
1285                 lt_settings->pre_emphasis = overrides->pre_emphasis;
1286
1287         if (overrides->post_cursor2 != NULL)
1288                 lt_settings->post_cursor2 = overrides->post_cursor2;
1289
1290         /* Initialize lane settings (VS/PE/PC2) */
1291         for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
1292                 lt_settings->lane_settings[lane].VOLTAGE_SWING =
1293                         lt_settings->voltage_swing != NULL ?
1294                         *lt_settings->voltage_swing :
1295                         VOLTAGE_SWING_LEVEL0;
1296                 lt_settings->lane_settings[lane].PRE_EMPHASIS =
1297                         lt_settings->pre_emphasis != NULL ?
1298                         *lt_settings->pre_emphasis
1299                         : PRE_EMPHASIS_DISABLED;
1300                 lt_settings->lane_settings[lane].POST_CURSOR2 =
1301                         lt_settings->post_cursor2 != NULL ?
1302                         *lt_settings->post_cursor2
1303                         : POST_CURSOR2_DISABLED;
1304         }
1305
1306         /* Initialize training timings */
1307         if (overrides->cr_pattern_time != NULL)
1308                 lt_settings->cr_pattern_time = *overrides->cr_pattern_time;
1309         else
1310                 lt_settings->cr_pattern_time = get_cr_training_aux_rd_interval(link, link_setting);
1311
1312         if (overrides->eq_pattern_time != NULL)
1313                 lt_settings->eq_pattern_time = *overrides->eq_pattern_time;
1314         else
1315                 lt_settings->eq_pattern_time = get_eq_training_aux_rd_interval(link, link_setting);
1316
1317         if (overrides->pattern_for_cr != NULL)
1318                 lt_settings->pattern_for_cr = *overrides->pattern_for_cr;
1319         else
1320                 lt_settings->pattern_for_cr = decide_cr_training_pattern(link_setting);
1321         if (overrides->pattern_for_eq != NULL)
1322                 lt_settings->pattern_for_eq = *overrides->pattern_for_eq;
1323         else
1324                 lt_settings->pattern_for_eq = decide_eq_training_pattern(link, link_setting);
1325
1326         if (overrides->enhanced_framing != NULL)
1327                 lt_settings->enhanced_framing = *overrides->enhanced_framing;
1328         else
1329                 lt_settings->enhanced_framing = 1;
1330 }
1331
1332 static void decide_training_settings(
1333                 struct dc_link *link,
1334                 const struct dc_link_settings *link_settings,
1335                 const struct dc_link_training_overrides *overrides,
1336                 struct link_training_settings *lt_settings)
1337 {
1338         if (dp_get_link_encoding_format(link_settings) == DP_8b_10b_ENCODING)
1339                 decide_8b_10b_training_settings(link, link_settings, overrides, lt_settings);
1340 }
1341
1342
1343 uint8_t dp_convert_to_count(uint8_t lttpr_repeater_count)
1344 {
1345         switch (lttpr_repeater_count) {
1346         case 0x80: // 1 lttpr repeater
1347                 return 1;
1348         case 0x40: // 2 lttpr repeaters
1349                 return 2;
1350         case 0x20: // 3 lttpr repeaters
1351                 return 3;
1352         case 0x10: // 4 lttpr repeaters
1353                 return 4;
1354         case 0x08: // 5 lttpr repeaters
1355                 return 5;
1356         case 0x04: // 6 lttpr repeaters
1357                 return 6;
1358         case 0x02: // 7 lttpr repeaters
1359                 return 7;
1360         case 0x01: // 8 lttpr repeaters
1361                 return 8;
1362         default:
1363                 break;
1364         }
1365         return 0; // invalid value
1366 }
1367
1368 static void configure_lttpr_mode_transparent(struct dc_link *link)
1369 {
1370         uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
1371
1372         DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
1373         core_link_write_dpcd(link,
1374                         DP_PHY_REPEATER_MODE,
1375                         (uint8_t *)&repeater_mode,
1376                         sizeof(repeater_mode));
1377 }
1378
1379 static void configure_lttpr_mode_non_transparent(
1380                 struct dc_link *link,
1381                 const struct link_training_settings *lt_settings)
1382 {
1383         /* aux timeout is already set to extended */
1384         /* RESET/SET lttpr mode to enable non transparent mode */
1385         uint8_t repeater_cnt;
1386         uint32_t aux_interval_address;
1387         uint8_t repeater_id;
1388         enum dc_status result = DC_ERROR_UNEXPECTED;
1389         uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
1390
1391         enum dp_link_encoding encoding = dp_get_link_encoding_format(&lt_settings->link_settings);
1392
1393         if (encoding == DP_8b_10b_ENCODING) {
1394                 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
1395                 result = core_link_write_dpcd(link,
1396                                 DP_PHY_REPEATER_MODE,
1397                                 (uint8_t *)&repeater_mode,
1398                                 sizeof(repeater_mode));
1399
1400         }
1401
1402         if (result == DC_OK) {
1403                 link->dpcd_caps.lttpr_caps.mode = repeater_mode;
1404         }
1405
1406         if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
1407
1408                 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Non Transparent Mode\n", __func__);
1409
1410                 repeater_mode = DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
1411                 result = core_link_write_dpcd(link,
1412                                 DP_PHY_REPEATER_MODE,
1413                                 (uint8_t *)&repeater_mode,
1414                                 sizeof(repeater_mode));
1415
1416                 if (result == DC_OK) {
1417                         link->dpcd_caps.lttpr_caps.mode = repeater_mode;
1418                 }
1419
1420                 if (encoding == DP_8b_10b_ENCODING) {
1421                         repeater_cnt = dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1422                         for (repeater_id = repeater_cnt; repeater_id > 0; repeater_id--) {
1423                                 aux_interval_address = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 +
1424                                                         ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (repeater_id - 1));
1425                                 core_link_read_dpcd(
1426                                         link,
1427                                         aux_interval_address,
1428                                         (uint8_t *)&link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1],
1429                                         sizeof(link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1]));
1430                                 link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1] &= 0x7F;
1431                         }
1432                 }
1433         }
1434 }
1435
1436 static void repeater_training_done(struct dc_link *link, uint32_t offset)
1437 {
1438         union dpcd_training_pattern dpcd_pattern = { {0} };
1439
1440         const uint32_t dpcd_base_lt_offset =
1441                         DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
1442                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
1443         /* Set training not in progress*/
1444         dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
1445
1446         core_link_write_dpcd(
1447                 link,
1448                 dpcd_base_lt_offset,
1449                 &dpcd_pattern.raw,
1450                 1);
1451
1452         DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Id: %d 0x%X pattern = %x\n",
1453                 __func__,
1454                 offset,
1455                 dpcd_base_lt_offset,
1456                 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
1457 }
1458
1459 static void print_status_message(
1460         struct dc_link *link,
1461         const struct link_training_settings *lt_settings,
1462         enum link_training_result status)
1463 {
1464         char *link_rate = "Unknown";
1465         char *lt_result = "Unknown";
1466         char *lt_spread = "Disabled";
1467
1468         switch (lt_settings->link_settings.link_rate) {
1469         case LINK_RATE_LOW:
1470                 link_rate = "RBR";
1471                 break;
1472         case LINK_RATE_RATE_2:
1473                 link_rate = "R2";
1474                 break;
1475         case LINK_RATE_RATE_3:
1476                 link_rate = "R3";
1477                 break;
1478         case LINK_RATE_HIGH:
1479                 link_rate = "HBR";
1480                 break;
1481         case LINK_RATE_RBR2:
1482                 link_rate = "RBR2";
1483                 break;
1484         case LINK_RATE_RATE_6:
1485                 link_rate = "R6";
1486                 break;
1487         case LINK_RATE_HIGH2:
1488                 link_rate = "HBR2";
1489                 break;
1490         case LINK_RATE_HIGH3:
1491                 link_rate = "HBR3";
1492                 break;
1493         default:
1494                 break;
1495         }
1496
1497         switch (status) {
1498         case LINK_TRAINING_SUCCESS:
1499                 lt_result = "pass";
1500                 break;
1501         case LINK_TRAINING_CR_FAIL_LANE0:
1502                 lt_result = "CR failed lane0";
1503                 break;
1504         case LINK_TRAINING_CR_FAIL_LANE1:
1505                 lt_result = "CR failed lane1";
1506                 break;
1507         case LINK_TRAINING_CR_FAIL_LANE23:
1508                 lt_result = "CR failed lane23";
1509                 break;
1510         case LINK_TRAINING_EQ_FAIL_CR:
1511                 lt_result = "CR failed in EQ";
1512                 break;
1513         case LINK_TRAINING_EQ_FAIL_EQ:
1514                 lt_result = "EQ failed";
1515                 break;
1516         case LINK_TRAINING_LQA_FAIL:
1517                 lt_result = "LQA failed";
1518                 break;
1519         case LINK_TRAINING_LINK_LOSS:
1520                 lt_result = "Link loss";
1521                 break;
1522         default:
1523                 break;
1524         }
1525
1526         switch (lt_settings->link_settings.link_spread) {
1527         case LINK_SPREAD_DISABLED:
1528                 lt_spread = "Disabled";
1529                 break;
1530         case LINK_SPREAD_05_DOWNSPREAD_30KHZ:
1531                 lt_spread = "0.5% 30KHz";
1532                 break;
1533         case LINK_SPREAD_05_DOWNSPREAD_33KHZ:
1534                 lt_spread = "0.5% 33KHz";
1535                 break;
1536         default:
1537                 break;
1538         }
1539
1540         /* Connectivity log: link training */
1541         CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d, DS=%s",
1542                                 link_rate,
1543                                 lt_settings->link_settings.lane_count,
1544                                 lt_result,
1545                                 lt_settings->lane_settings[0].VOLTAGE_SWING,
1546                                 lt_settings->lane_settings[0].PRE_EMPHASIS,
1547                                 lt_spread);
1548 }
1549
1550 void dc_link_dp_set_drive_settings(
1551         struct dc_link *link,
1552         struct link_training_settings *lt_settings)
1553 {
1554         /* program ASIC PHY settings*/
1555         dp_set_hw_lane_settings(link, lt_settings, DPRX);
1556
1557         /* Notify DP sink the PHY settings from source */
1558         dpcd_set_lane_settings(link, lt_settings, DPRX);
1559 }
1560
1561 bool dc_link_dp_perform_link_training_skip_aux(
1562         struct dc_link *link,
1563         const struct dc_link_settings *link_setting)
1564 {
1565         struct link_training_settings lt_settings;
1566
1567         decide_training_settings(
1568                         link,
1569                         link_setting,
1570                         &link->preferred_training_settings,
1571                         &lt_settings);
1572
1573         /* 1. Perform_clock_recovery_sequence. */
1574
1575         /* transmit training pattern for clock recovery */
1576         dp_set_hw_training_pattern(link, lt_settings.pattern_for_cr, DPRX);
1577
1578         /* call HWSS to set lane settings*/
1579         dp_set_hw_lane_settings(link, &lt_settings, DPRX);
1580
1581         /* wait receiver to lock-on*/
1582         wait_for_training_aux_rd_interval(link, lt_settings.cr_pattern_time);
1583
1584         /* 2. Perform_channel_equalization_sequence. */
1585
1586         /* transmit training pattern for channel equalization. */
1587         dp_set_hw_training_pattern(link, lt_settings.pattern_for_eq, DPRX);
1588
1589         /* call HWSS to set lane settings*/
1590         dp_set_hw_lane_settings(link, &lt_settings, DPRX);
1591
1592         /* wait receiver to lock-on. */
1593         wait_for_training_aux_rd_interval(link, lt_settings.eq_pattern_time);
1594
1595         /* 3. Perform_link_training_int. */
1596
1597         /* Mainlink output idle pattern. */
1598         dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1599
1600         print_status_message(link, &lt_settings, LINK_TRAINING_SUCCESS);
1601
1602         return true;
1603 }
1604
1605 enum link_training_result dc_link_dp_perform_link_training(
1606         struct dc_link *link,
1607         const struct dc_link_settings *link_setting,
1608         bool skip_video_pattern)
1609 {
1610         enum link_training_result status = LINK_TRAINING_SUCCESS;
1611         struct link_training_settings lt_settings;
1612
1613         bool fec_enable;
1614         uint8_t repeater_cnt;
1615         uint8_t repeater_id;
1616
1617         decide_training_settings(
1618                         link,
1619                         link_setting,
1620                         &link->preferred_training_settings,
1621                         &lt_settings);
1622
1623         /* Configure lttpr mode */
1624         if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
1625                 configure_lttpr_mode_non_transparent(link, &lt_settings);
1626         else if (link->lttpr_mode == LTTPR_MODE_TRANSPARENT)
1627                 configure_lttpr_mode_transparent(link);
1628
1629         if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
1630                 start_clock_recovery_pattern_early(link, &lt_settings, DPRX);
1631
1632         /* 1. set link rate, lane count and spread. */
1633         dpcd_set_link_settings(link, &lt_settings);
1634
1635         if (link->preferred_training_settings.fec_enable != NULL)
1636                 fec_enable = *link->preferred_training_settings.fec_enable;
1637         else
1638                 fec_enable = true;
1639
1640         dp_set_fec_ready(link, fec_enable);
1641
1642         if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
1643
1644                 /* 2. perform link training (set link training done
1645                  *  to false is done as well)
1646                  */
1647                 repeater_cnt = dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1648
1649                 for (repeater_id = repeater_cnt; (repeater_id > 0 && status == LINK_TRAINING_SUCCESS);
1650                                 repeater_id--) {
1651                         status = perform_clock_recovery_sequence(link, &lt_settings, repeater_id);
1652
1653                         if (status != LINK_TRAINING_SUCCESS)
1654                                 break;
1655
1656                         status = perform_channel_equalization_sequence(link,
1657                                         &lt_settings,
1658                                         repeater_id);
1659
1660                         if (status != LINK_TRAINING_SUCCESS)
1661                                 break;
1662
1663                         repeater_training_done(link, repeater_id);
1664                 }
1665         }
1666
1667         if (status == LINK_TRAINING_SUCCESS) {
1668                 status = perform_clock_recovery_sequence(link, &lt_settings, DPRX);
1669         if (status == LINK_TRAINING_SUCCESS) {
1670                 status = perform_channel_equalization_sequence(link,
1671                                         &lt_settings,
1672                                         DPRX);
1673                 }
1674         }
1675
1676         /* 3. set training not in progress*/
1677         dpcd_set_training_pattern(link, DP_TRAINING_PATTERN_VIDEOIDLE);
1678         if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern) {
1679                 status = dp_transition_to_video_idle(link,
1680                                 &lt_settings,
1681                                 status);
1682         }
1683
1684         /* delay 5ms after Main Link output idle pattern and then check
1685          * DPCD 0202h.
1686          */
1687         if (link->connector_signal != SIGNAL_TYPE_EDP && status == LINK_TRAINING_SUCCESS) {
1688                 msleep(5);
1689                 status = dp_check_link_loss_status(link, &lt_settings);
1690         }
1691
1692         /* 6. print status message*/
1693         print_status_message(link, &lt_settings, status);
1694
1695         if (status != LINK_TRAINING_SUCCESS)
1696                 link->ctx->dc->debug_data.ltFailCount++;
1697
1698         return status;
1699 }
1700
1701 static enum dp_panel_mode try_enable_assr(struct dc_stream_state *stream)
1702 {
1703         struct dc_link *link = stream->link;
1704         enum dp_panel_mode panel_mode = dp_get_panel_mode(link);
1705 #ifdef CONFIG_DRM_AMD_DC_HDCP
1706         struct cp_psp *cp_psp = &stream->ctx->cp_psp;
1707 #endif
1708
1709         /* ASSR must be supported on the panel */
1710         if (panel_mode == DP_PANEL_MODE_DEFAULT)
1711                 return panel_mode;
1712
1713         /* eDP or internal DP only */
1714         if (link->connector_signal != SIGNAL_TYPE_EDP &&
1715                 !(link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
1716                  link->is_internal_display))
1717                 return DP_PANEL_MODE_DEFAULT;
1718
1719 #ifdef CONFIG_DRM_AMD_DC_HDCP
1720         if (cp_psp && cp_psp->funcs.enable_assr) {
1721                 if (!cp_psp->funcs.enable_assr(cp_psp->handle, link)) {
1722                         /* since eDP implies ASSR on, change panel
1723                          * mode to disable ASSR
1724                          */
1725                         panel_mode = DP_PANEL_MODE_DEFAULT;
1726                 }
1727         } else
1728                 panel_mode = DP_PANEL_MODE_DEFAULT;
1729
1730 #else
1731         /* turn off ASSR if the implementation is not compiled in */
1732         panel_mode = DP_PANEL_MODE_DEFAULT;
1733 #endif
1734         return panel_mode;
1735 }
1736
1737 bool perform_link_training_with_retries(
1738         const struct dc_link_settings *link_setting,
1739         bool skip_video_pattern,
1740         int attempts,
1741         struct pipe_ctx *pipe_ctx,
1742         enum signal_type signal,
1743         bool do_fallback)
1744 {
1745         uint8_t j;
1746         uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
1747         struct dc_stream_state *stream = pipe_ctx->stream;
1748         struct dc_link *link = stream->link;
1749         enum dp_panel_mode panel_mode;
1750         struct link_encoder *link_enc;
1751         enum link_training_result status = LINK_TRAINING_CR_FAIL_LANE0;
1752         struct dc_link_settings currnet_setting = *link_setting;
1753
1754         /* Dynamically assigned link encoders associated with stream rather than
1755          * link.
1756          */
1757         if (link->dc->res_pool->funcs->link_encs_assign)
1758                 link_enc = stream->link_enc;
1759         else
1760                 link_enc = link->link_enc;
1761         ASSERT(link_enc);
1762
1763         /* We need to do this before the link training to ensure the idle pattern in SST
1764          * mode will be sent right after the link training
1765          */
1766         link_enc->funcs->connect_dig_be_to_fe(link_enc,
1767                                                         pipe_ctx->stream_res.stream_enc->id, true);
1768
1769         for (j = 0; j < attempts; ++j) {
1770
1771                 DC_LOG_HW_LINK_TRAINING("%s: Beginning link training attempt %u of %d\n",
1772                         __func__, (unsigned int)j + 1, attempts);
1773
1774                 dp_enable_link_phy(
1775                         link,
1776                         signal,
1777                         pipe_ctx->clock_source->id,
1778                         &currnet_setting);
1779
1780                 if (stream->sink_patches.dppowerup_delay > 0) {
1781                         int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay;
1782
1783                         msleep(delay_dp_power_up_in_ms);
1784                 }
1785
1786                 panel_mode = try_enable_assr(stream);
1787                 dp_set_panel_mode(link, panel_mode);
1788                 DC_LOG_DETECTION_DP_CAPS("Link: %d ASSR enabled: %d\n",
1789                          link->link_index,
1790                          panel_mode != DP_PANEL_MODE_DEFAULT);
1791
1792                 if (link->aux_access_disabled) {
1793                         dc_link_dp_perform_link_training_skip_aux(link, &currnet_setting);
1794                         return true;
1795                 } else {
1796                                 status = dc_link_dp_perform_link_training(
1797                                                                                 link,
1798                                                                                 &currnet_setting,
1799                                                                                 skip_video_pattern);
1800                         if (status == LINK_TRAINING_SUCCESS)
1801                                 return true;
1802                 }
1803
1804                 /* latest link training still fail, skip delay and keep PHY on
1805                  */
1806                 if (j == (attempts - 1) && link->ep_type == DISPLAY_ENDPOINT_PHY)
1807                         break;
1808
1809                 DC_LOG_WARNING("%s: Link training attempt %u of %d failed\n",
1810                         __func__, (unsigned int)j + 1, attempts);
1811
1812                 dp_disable_link_phy(link, signal);
1813
1814                 /* Abort link training if failure due to sink being unplugged. */
1815                 if (status == LINK_TRAINING_ABORT)
1816                         break;
1817                 else if (do_fallback) {
1818                         decide_fallback_link_setting(*link_setting, &currnet_setting, status);
1819                         /* Fail link training if reduced link bandwidth no longer meets
1820                          * stream requirements.
1821                          */
1822                         if (dc_bandwidth_in_kbps_from_timing(&stream->timing) <
1823                                         dc_link_bandwidth_kbps(link, &currnet_setting))
1824                                 break;
1825                 }
1826
1827                 msleep(delay_between_attempts);
1828
1829                 delay_between_attempts += LINK_TRAINING_RETRY_DELAY;
1830         }
1831
1832         return false;
1833 }
1834
1835 static enum clock_source_id get_clock_source_id(struct dc_link *link)
1836 {
1837         enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_UNDEFINED;
1838         struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source;
1839
1840         if (dp_cs != NULL) {
1841                 dp_cs_id = dp_cs->id;
1842         } else {
1843                 /*
1844                  * dp clock source is not initialized for some reason.
1845                  * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
1846                  */
1847                 ASSERT(dp_cs);
1848         }
1849
1850         return dp_cs_id;
1851 }
1852
1853 static void set_dp_mst_mode(struct dc_link *link, bool mst_enable)
1854 {
1855         if (mst_enable == false &&
1856                 link->type == dc_connection_mst_branch) {
1857                 /* Disable MST on link. Use only local sink. */
1858                 dp_disable_link_phy_mst(link, link->connector_signal);
1859
1860                 link->type = dc_connection_single;
1861                 link->local_sink = link->remote_sinks[0];
1862                 link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT;
1863         } else if (mst_enable == true &&
1864                         link->type == dc_connection_single &&
1865                         link->remote_sinks[0] != NULL) {
1866                 /* Re-enable MST on link. */
1867                 dp_disable_link_phy(link, link->connector_signal);
1868                 dp_enable_mst_on_sink(link, true);
1869
1870                 link->type = dc_connection_mst_branch;
1871                 link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
1872         }
1873 }
1874
1875 bool dc_link_dp_sync_lt_begin(struct dc_link *link)
1876 {
1877         /* Begin Sync LT. During this time,
1878          * DPCD:600h must not be powered down.
1879          */
1880         link->sync_lt_in_progress = true;
1881
1882         /*Clear any existing preferred settings.*/
1883         memset(&link->preferred_training_settings, 0,
1884                 sizeof(struct dc_link_training_overrides));
1885         memset(&link->preferred_link_setting, 0,
1886                 sizeof(struct dc_link_settings));
1887
1888         return true;
1889 }
1890
1891 enum link_training_result dc_link_dp_sync_lt_attempt(
1892     struct dc_link *link,
1893     struct dc_link_settings *link_settings,
1894     struct dc_link_training_overrides *lt_overrides)
1895 {
1896         struct link_training_settings lt_settings;
1897         enum link_training_result lt_status = LINK_TRAINING_SUCCESS;
1898         enum dp_panel_mode panel_mode = DP_PANEL_MODE_DEFAULT;
1899         enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
1900         bool fec_enable = false;
1901
1902         decide_training_settings(
1903                 link,
1904                 link_settings,
1905                 lt_overrides,
1906                 &lt_settings);
1907
1908         /* Setup MST Mode */
1909         if (lt_overrides->mst_enable)
1910                 set_dp_mst_mode(link, *lt_overrides->mst_enable);
1911
1912         /* Disable link */
1913         dp_disable_link_phy(link, link->connector_signal);
1914
1915         /* Enable link */
1916         dp_cs_id = get_clock_source_id(link);
1917         dp_enable_link_phy(link, link->connector_signal,
1918                 dp_cs_id, link_settings);
1919
1920         /* Set FEC enable */
1921         fec_enable = lt_overrides->fec_enable && *lt_overrides->fec_enable;
1922         dp_set_fec_ready(link, fec_enable);
1923
1924         if (lt_overrides->alternate_scrambler_reset) {
1925                 if (*lt_overrides->alternate_scrambler_reset)
1926                         panel_mode = DP_PANEL_MODE_EDP;
1927                 else
1928                         panel_mode = DP_PANEL_MODE_DEFAULT;
1929         } else
1930                 panel_mode = dp_get_panel_mode(link);
1931
1932         dp_set_panel_mode(link, panel_mode);
1933
1934         /* Attempt to train with given link training settings */
1935         if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
1936                 start_clock_recovery_pattern_early(link, &lt_settings, DPRX);
1937
1938         /* Set link rate, lane count and spread. */
1939         dpcd_set_link_settings(link, &lt_settings);
1940
1941         /* 2. perform link training (set link training done
1942          *  to false is done as well)
1943          */
1944         lt_status = perform_clock_recovery_sequence(link, &lt_settings, DPRX);
1945         if (lt_status == LINK_TRAINING_SUCCESS) {
1946                 lt_status = perform_channel_equalization_sequence(link,
1947                                                 &lt_settings,
1948                                                 DPRX);
1949         }
1950
1951         /* 3. Sync LT must skip TRAINING_PATTERN_SET:0 (video pattern)*/
1952         /* 4. print status message*/
1953         print_status_message(link, &lt_settings, lt_status);
1954
1955         return lt_status;
1956 }
1957
1958 bool dc_link_dp_sync_lt_end(struct dc_link *link, bool link_down)
1959 {
1960         /* If input parameter is set, shut down phy.
1961          * Still shouldn't turn off dp_receiver (DPCD:600h)
1962          */
1963         if (link_down == true) {
1964                 dp_disable_link_phy(link, link->connector_signal);
1965                 dp_set_fec_ready(link, false);
1966         }
1967
1968         link->sync_lt_in_progress = false;
1969         return true;
1970 }
1971
1972 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, struct dc_link_settings *max_link_enc_cap)
1973 {
1974         if (!max_link_enc_cap) {
1975                 DC_LOG_ERROR("%s: Could not return max link encoder caps", __func__);
1976                 return false;
1977         }
1978
1979         if (link->link_enc->funcs->get_max_link_cap) {
1980                 link->link_enc->funcs->get_max_link_cap(link->link_enc, max_link_enc_cap);
1981                 return true;
1982         }
1983
1984         DC_LOG_ERROR("%s: Max link encoder caps unknown", __func__);
1985         max_link_enc_cap->lane_count = 1;
1986         max_link_enc_cap->link_rate = 6;
1987         return false;
1988 }
1989
1990 static struct dc_link_settings get_max_link_cap(struct dc_link *link)
1991 {
1992         struct dc_link_settings max_link_cap = {0};
1993
1994         /* get max link encoder capability */
1995         link->link_enc->funcs->get_max_link_cap(link->link_enc, &max_link_cap);
1996
1997         /* Lower link settings based on sink's link cap */
1998         if (link->reported_link_cap.lane_count < max_link_cap.lane_count)
1999                 max_link_cap.lane_count =
2000                                 link->reported_link_cap.lane_count;
2001         if (link->reported_link_cap.link_rate < max_link_cap.link_rate)
2002                 max_link_cap.link_rate =
2003                                 link->reported_link_cap.link_rate;
2004         if (link->reported_link_cap.link_spread <
2005                         max_link_cap.link_spread)
2006                 max_link_cap.link_spread =
2007                                 link->reported_link_cap.link_spread;
2008         /*
2009          * account for lttpr repeaters cap
2010          * notes: repeaters do not snoop in the DPRX Capabilities addresses (3.6.3).
2011          */
2012         if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
2013                 if (link->dpcd_caps.lttpr_caps.max_lane_count < max_link_cap.lane_count)
2014                         max_link_cap.lane_count = link->dpcd_caps.lttpr_caps.max_lane_count;
2015
2016                 if (link->dpcd_caps.lttpr_caps.max_link_rate < max_link_cap.link_rate)
2017                         max_link_cap.link_rate = link->dpcd_caps.lttpr_caps.max_link_rate;
2018
2019                 DC_LOG_HW_LINK_TRAINING("%s\n Training with LTTPR,  max_lane count %d max_link rate %d \n",
2020                                                 __func__,
2021                                                 max_link_cap.lane_count,
2022                                                 max_link_cap.link_rate);
2023         }
2024         return max_link_cap;
2025 }
2026
2027 enum dc_status read_hpd_rx_irq_data(
2028         struct dc_link *link,
2029         union hpd_irq_data *irq_data)
2030 {
2031         static enum dc_status retval;
2032
2033         /* The HW reads 16 bytes from 200h on HPD,
2034          * but if we get an AUX_DEFER, the HW cannot retry
2035          * and this causes the CTS tests 4.3.2.1 - 3.2.4 to
2036          * fail, so we now explicitly read 6 bytes which is
2037          * the req from the above mentioned test cases.
2038          *
2039          * For DP 1.4 we need to read those from 2002h range.
2040          */
2041         if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14)
2042                 retval = core_link_read_dpcd(
2043                         link,
2044                         DP_SINK_COUNT,
2045                         irq_data->raw,
2046                         sizeof(union hpd_irq_data));
2047         else {
2048                 /* Read 14 bytes in a single read and then copy only the required fields.
2049                  * This is more efficient than doing it in two separate AUX reads. */
2050
2051                 uint8_t tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI + 1];
2052
2053                 retval = core_link_read_dpcd(
2054                         link,
2055                         DP_SINK_COUNT_ESI,
2056                         tmp,
2057                         sizeof(tmp));
2058
2059                 if (retval != DC_OK)
2060                         return retval;
2061
2062                 irq_data->bytes.sink_cnt.raw = tmp[DP_SINK_COUNT_ESI - DP_SINK_COUNT_ESI];
2063                 irq_data->bytes.device_service_irq.raw = tmp[DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 - DP_SINK_COUNT_ESI];
2064                 irq_data->bytes.lane01_status.raw = tmp[DP_LANE0_1_STATUS_ESI - DP_SINK_COUNT_ESI];
2065                 irq_data->bytes.lane23_status.raw = tmp[DP_LANE2_3_STATUS_ESI - DP_SINK_COUNT_ESI];
2066                 irq_data->bytes.lane_status_updated.raw = tmp[DP_LANE_ALIGN_STATUS_UPDATED_ESI - DP_SINK_COUNT_ESI];
2067                 irq_data->bytes.sink_status.raw = tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI];
2068         }
2069
2070         return retval;
2071 }
2072
2073 static bool hpd_rx_irq_check_link_loss_status(
2074         struct dc_link *link,
2075         union hpd_irq_data *hpd_irq_dpcd_data)
2076 {
2077         uint8_t irq_reg_rx_power_state = 0;
2078         enum dc_status dpcd_result = DC_ERROR_UNEXPECTED;
2079         union lane_status lane_status;
2080         uint32_t lane;
2081         bool sink_status_changed;
2082         bool return_code;
2083
2084         sink_status_changed = false;
2085         return_code = false;
2086
2087         if (link->cur_link_settings.lane_count == 0)
2088                 return return_code;
2089
2090         /*1. Check that Link Status changed, before re-training.*/
2091
2092         /*parse lane status*/
2093         for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
2094                 /* check status of lanes 0,1
2095                  * changed DpcdAddress_Lane01Status (0x202)
2096                  */
2097                 lane_status.raw = get_nibble_at_index(
2098                         &hpd_irq_dpcd_data->bytes.lane01_status.raw,
2099                         lane);
2100
2101                 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
2102                         !lane_status.bits.CR_DONE_0 ||
2103                         !lane_status.bits.SYMBOL_LOCKED_0) {
2104                         /* if one of the channel equalization, clock
2105                          * recovery or symbol lock is dropped
2106                          * consider it as (link has been
2107                          * dropped) dp sink status has changed
2108                          */
2109                         sink_status_changed = true;
2110                         break;
2111                 }
2112         }
2113
2114         /* Check interlane align.*/
2115         if (sink_status_changed ||
2116                 !hpd_irq_dpcd_data->bytes.lane_status_updated.bits.INTERLANE_ALIGN_DONE) {
2117
2118                 DC_LOG_HW_HPD_IRQ("%s: Link Status changed.\n", __func__);
2119
2120                 return_code = true;
2121
2122                 /*2. Check that we can handle interrupt: Not in FS DOS,
2123                  *  Not in "Display Timeout" state, Link is trained.
2124                  */
2125                 dpcd_result = core_link_read_dpcd(link,
2126                         DP_SET_POWER,
2127                         &irq_reg_rx_power_state,
2128                         sizeof(irq_reg_rx_power_state));
2129
2130                 if (dpcd_result != DC_OK) {
2131                         DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain power state.\n",
2132                                 __func__);
2133                 } else {
2134                         if (irq_reg_rx_power_state != DP_SET_POWER_D0)
2135                                 return_code = false;
2136                 }
2137         }
2138
2139         return return_code;
2140 }
2141
2142 bool dp_verify_link_cap(
2143         struct dc_link *link,
2144         struct dc_link_settings *known_limit_link_setting,
2145         int *fail_count)
2146 {
2147         struct dc_link_settings max_link_cap = {0};
2148         struct dc_link_settings cur_link_setting = {0};
2149         struct dc_link_settings *cur = &cur_link_setting;
2150         struct dc_link_settings initial_link_settings = {0};
2151         bool success;
2152         bool skip_link_training;
2153         bool skip_video_pattern;
2154         enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
2155         enum link_training_result status;
2156         union hpd_irq_data irq_data;
2157
2158         if (link->dc->debug.skip_detection_link_training) {
2159                 link->verified_link_cap = *known_limit_link_setting;
2160                 return true;
2161         }
2162
2163         memset(&irq_data, 0, sizeof(irq_data));
2164         success = false;
2165         skip_link_training = false;
2166
2167         max_link_cap = get_max_link_cap(link);
2168
2169         /* Grant extended timeout request */
2170         if ((link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && (link->dpcd_caps.lttpr_caps.max_ext_timeout > 0)) {
2171                 uint8_t grant = link->dpcd_caps.lttpr_caps.max_ext_timeout & 0x80;
2172
2173                 core_link_write_dpcd(link, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, &grant, sizeof(grant));
2174         }
2175
2176         /* TODO implement override and monitor patch later */
2177
2178         /* try to train the link from high to low to
2179          * find the physical link capability
2180          */
2181         /* disable PHY done possible by BIOS, will be done by driver itself */
2182         dp_disable_link_phy(link, link->connector_signal);
2183
2184         dp_cs_id = get_clock_source_id(link);
2185
2186         /* link training starts with the maximum common settings
2187          * supported by both sink and ASIC.
2188          */
2189         initial_link_settings = get_common_supported_link_settings(
2190                         *known_limit_link_setting,
2191                         max_link_cap);
2192         cur_link_setting = initial_link_settings;
2193
2194         /* Temporary Renoir-specific workaround for SWDEV-215184;
2195          * PHY will sometimes be in bad state on hotplugging display from certain USB-C dongle,
2196          * so add extra cycle of enabling and disabling the PHY before first link training.
2197          */
2198         if (link->link_enc->features.flags.bits.DP_IS_USB_C &&
2199                         link->dc->debug.usbc_combo_phy_reset_wa) {
2200                 dp_enable_link_phy(link, link->connector_signal, dp_cs_id, cur);
2201                 dp_disable_link_phy(link, link->connector_signal);
2202         }
2203
2204         do {
2205                 skip_video_pattern = true;
2206
2207                 if (cur->link_rate == LINK_RATE_LOW)
2208                         skip_video_pattern = false;
2209
2210                 dp_enable_link_phy(
2211                                 link,
2212                                 link->connector_signal,
2213                                 dp_cs_id,
2214                                 cur);
2215
2216
2217                 if (skip_link_training)
2218                         success = true;
2219                 else {
2220                         status = dc_link_dp_perform_link_training(
2221                                                         link,
2222                                                         cur,
2223                                                         skip_video_pattern);
2224                         if (status == LINK_TRAINING_SUCCESS)
2225                                 success = true;
2226                         else
2227                                 (*fail_count)++;
2228                 }
2229
2230                 if (success) {
2231                         link->verified_link_cap = *cur;
2232                         udelay(1000);
2233                         if (read_hpd_rx_irq_data(link, &irq_data) == DC_OK)
2234                                 if (hpd_rx_irq_check_link_loss_status(
2235                                                 link,
2236                                                 &irq_data))
2237                                         (*fail_count)++;
2238                 }
2239                 /* always disable the link before trying another
2240                  * setting or before returning we'll enable it later
2241                  * based on the actual mode we're driving
2242                  */
2243                 dp_disable_link_phy(link, link->connector_signal);
2244         } while (!success && decide_fallback_link_setting(
2245                         initial_link_settings, cur, status));
2246
2247         /* Link Training failed for all Link Settings
2248          *  (Lane Count is still unknown)
2249          */
2250         if (!success) {
2251                 /* If all LT fails for all settings,
2252                  * set verified = failed safe (1 lane low)
2253                  */
2254                 link->verified_link_cap.lane_count = LANE_COUNT_ONE;
2255                 link->verified_link_cap.link_rate = LINK_RATE_LOW;
2256
2257                 link->verified_link_cap.link_spread =
2258                 LINK_SPREAD_DISABLED;
2259         }
2260
2261
2262         return success;
2263 }
2264
2265 bool dp_verify_link_cap_with_retries(
2266         struct dc_link *link,
2267         struct dc_link_settings *known_limit_link_setting,
2268         int attempts)
2269 {
2270         uint8_t i = 0;
2271         bool success = false;
2272
2273         for (i = 0; i < attempts; i++) {
2274                 int fail_count = 0;
2275                 enum dc_connection_type type = dc_connection_none;
2276
2277                 memset(&link->verified_link_cap, 0,
2278                                 sizeof(struct dc_link_settings));
2279                 if (!dc_link_detect_sink(link, &type) || type == dc_connection_none) {
2280                         link->verified_link_cap.lane_count = LANE_COUNT_ONE;
2281                         link->verified_link_cap.link_rate = LINK_RATE_LOW;
2282                         link->verified_link_cap.link_spread = LINK_SPREAD_DISABLED;
2283                         break;
2284                 } else if (dp_verify_link_cap(link,
2285                                 &link->reported_link_cap,
2286                                 &fail_count) && fail_count == 0) {
2287                         success = true;
2288                         break;
2289                 }
2290                 msleep(10);
2291         }
2292         return success;
2293 }
2294
2295 bool dp_verify_mst_link_cap(
2296         struct dc_link *link)
2297 {
2298         struct dc_link_settings max_link_cap = {0};
2299
2300         max_link_cap = get_max_link_cap(link);
2301         link->verified_link_cap = get_common_supported_link_settings(
2302                 link->reported_link_cap,
2303                 max_link_cap);
2304
2305         return true;
2306 }
2307
2308 static struct dc_link_settings get_common_supported_link_settings(
2309                 struct dc_link_settings link_setting_a,
2310                 struct dc_link_settings link_setting_b)
2311 {
2312         struct dc_link_settings link_settings = {0};
2313
2314         link_settings.lane_count =
2315                 (link_setting_a.lane_count <=
2316                         link_setting_b.lane_count) ?
2317                         link_setting_a.lane_count :
2318                         link_setting_b.lane_count;
2319         link_settings.link_rate =
2320                 (link_setting_a.link_rate <=
2321                         link_setting_b.link_rate) ?
2322                         link_setting_a.link_rate :
2323                         link_setting_b.link_rate;
2324         link_settings.link_spread = LINK_SPREAD_DISABLED;
2325
2326         /* in DP compliance test, DPR-120 may have
2327          * a random value in its MAX_LINK_BW dpcd field.
2328          * We map it to the maximum supported link rate that
2329          * is smaller than MAX_LINK_BW in this case.
2330          */
2331         if (link_settings.link_rate > LINK_RATE_HIGH3) {
2332                 link_settings.link_rate = LINK_RATE_HIGH3;
2333         } else if (link_settings.link_rate < LINK_RATE_HIGH3
2334                         && link_settings.link_rate > LINK_RATE_HIGH2) {
2335                 link_settings.link_rate = LINK_RATE_HIGH2;
2336         } else if (link_settings.link_rate < LINK_RATE_HIGH2
2337                         && link_settings.link_rate > LINK_RATE_HIGH) {
2338                 link_settings.link_rate = LINK_RATE_HIGH;
2339         } else if (link_settings.link_rate < LINK_RATE_HIGH
2340                         && link_settings.link_rate > LINK_RATE_LOW) {
2341                 link_settings.link_rate = LINK_RATE_LOW;
2342         } else if (link_settings.link_rate < LINK_RATE_LOW) {
2343                 link_settings.link_rate = LINK_RATE_UNKNOWN;
2344         }
2345
2346         return link_settings;
2347 }
2348
2349 static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count)
2350 {
2351         return lane_count <= LANE_COUNT_ONE;
2352 }
2353
2354 static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate)
2355 {
2356         return link_rate <= LINK_RATE_LOW;
2357 }
2358
2359 static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count)
2360 {
2361         switch (lane_count) {
2362         case LANE_COUNT_FOUR:
2363                 return LANE_COUNT_TWO;
2364         case LANE_COUNT_TWO:
2365                 return LANE_COUNT_ONE;
2366         case LANE_COUNT_ONE:
2367                 return LANE_COUNT_UNKNOWN;
2368         default:
2369                 return LANE_COUNT_UNKNOWN;
2370         }
2371 }
2372
2373 static enum dc_link_rate reduce_link_rate(enum dc_link_rate link_rate)
2374 {
2375         switch (link_rate) {
2376         case LINK_RATE_HIGH3:
2377                 return LINK_RATE_HIGH2;
2378         case LINK_RATE_HIGH2:
2379                 return LINK_RATE_HIGH;
2380         case LINK_RATE_HIGH:
2381                 return LINK_RATE_LOW;
2382         case LINK_RATE_LOW:
2383                 return LINK_RATE_UNKNOWN;
2384         default:
2385                 return LINK_RATE_UNKNOWN;
2386         }
2387 }
2388
2389 static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count)
2390 {
2391         switch (lane_count) {
2392         case LANE_COUNT_ONE:
2393                 return LANE_COUNT_TWO;
2394         case LANE_COUNT_TWO:
2395                 return LANE_COUNT_FOUR;
2396         default:
2397                 return LANE_COUNT_UNKNOWN;
2398         }
2399 }
2400
2401 static enum dc_link_rate increase_link_rate(enum dc_link_rate link_rate)
2402 {
2403         switch (link_rate) {
2404         case LINK_RATE_LOW:
2405                 return LINK_RATE_HIGH;
2406         case LINK_RATE_HIGH:
2407                 return LINK_RATE_HIGH2;
2408         case LINK_RATE_HIGH2:
2409                 return LINK_RATE_HIGH3;
2410         default:
2411                 return LINK_RATE_UNKNOWN;
2412         }
2413 }
2414
2415 /*
2416  * function: set link rate and lane count fallback based
2417  * on current link setting and last link training result
2418  * return value:
2419  *                      true - link setting could be set
2420  *                      false - has reached minimum setting
2421  *                                      and no further fallback could be done
2422  */
2423 static bool decide_fallback_link_setting(
2424                 struct dc_link_settings initial_link_settings,
2425                 struct dc_link_settings *current_link_setting,
2426                 enum link_training_result training_result)
2427 {
2428         if (!current_link_setting)
2429                 return false;
2430
2431         switch (training_result) {
2432         case LINK_TRAINING_CR_FAIL_LANE0:
2433         case LINK_TRAINING_CR_FAIL_LANE1:
2434         case LINK_TRAINING_CR_FAIL_LANE23:
2435         case LINK_TRAINING_LQA_FAIL:
2436         {
2437                 if (!reached_minimum_link_rate
2438                                 (current_link_setting->link_rate)) {
2439                         current_link_setting->link_rate =
2440                                 reduce_link_rate(
2441                                         current_link_setting->link_rate);
2442                 } else if (!reached_minimum_lane_count
2443                                 (current_link_setting->lane_count)) {
2444                         current_link_setting->link_rate =
2445                                 initial_link_settings.link_rate;
2446                         if (training_result == LINK_TRAINING_CR_FAIL_LANE0)
2447                                 return false;
2448                         else if (training_result == LINK_TRAINING_CR_FAIL_LANE1)
2449                                 current_link_setting->lane_count =
2450                                                 LANE_COUNT_ONE;
2451                         else if (training_result ==
2452                                         LINK_TRAINING_CR_FAIL_LANE23)
2453                                 current_link_setting->lane_count =
2454                                                 LANE_COUNT_TWO;
2455                         else
2456                                 current_link_setting->lane_count =
2457                                         reduce_lane_count(
2458                                         current_link_setting->lane_count);
2459                 } else {
2460                         return false;
2461                 }
2462                 break;
2463         }
2464         case LINK_TRAINING_EQ_FAIL_EQ:
2465         {
2466                 if (!reached_minimum_lane_count
2467                                 (current_link_setting->lane_count)) {
2468                         current_link_setting->lane_count =
2469                                 reduce_lane_count(
2470                                         current_link_setting->lane_count);
2471                 } else if (!reached_minimum_link_rate
2472                                 (current_link_setting->link_rate)) {
2473                         current_link_setting->link_rate =
2474                                 reduce_link_rate(
2475                                         current_link_setting->link_rate);
2476                 } else {
2477                         return false;
2478                 }
2479                 break;
2480         }
2481         case LINK_TRAINING_EQ_FAIL_CR:
2482         {
2483                 if (!reached_minimum_link_rate
2484                                 (current_link_setting->link_rate)) {
2485                         current_link_setting->link_rate =
2486                                 reduce_link_rate(
2487                                         current_link_setting->link_rate);
2488                 } else {
2489                         return false;
2490                 }
2491                 break;
2492         }
2493         default:
2494                 return false;
2495         }
2496         return true;
2497 }
2498
2499 bool dp_validate_mode_timing(
2500         struct dc_link *link,
2501         const struct dc_crtc_timing *timing)
2502 {
2503         uint32_t req_bw;
2504         uint32_t max_bw;
2505
2506         const struct dc_link_settings *link_setting;
2507
2508         /* According to spec, VSC SDP should be used if pixel format is YCbCr420 */
2509         if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 &&
2510                         !link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED &&
2511                         dal_graphics_object_id_get_connector_id(link->link_id) != CONNECTOR_ID_VIRTUAL)
2512                 return false;
2513
2514         /*always DP fail safe mode*/
2515         if ((timing->pix_clk_100hz / 10) == (uint32_t) 25175 &&
2516                 timing->h_addressable == (uint32_t) 640 &&
2517                 timing->v_addressable == (uint32_t) 480)
2518                 return true;
2519
2520         link_setting = dc_link_get_link_cap(link);
2521
2522         /* TODO: DYNAMIC_VALIDATION needs to be implemented */
2523         /*if (flags.DYNAMIC_VALIDATION == 1 &&
2524                 link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN)
2525                 link_setting = &link->verified_link_cap;
2526         */
2527
2528         req_bw = dc_bandwidth_in_kbps_from_timing(timing);
2529         max_bw = dc_link_bandwidth_kbps(link, link_setting);
2530
2531         if (req_bw <= max_bw) {
2532                 /* remember the biggest mode here, during
2533                  * initial link training (to get
2534                  * verified_link_cap), LS sends event about
2535                  * cannot train at reported cap to upper
2536                  * layer and upper layer will re-enumerate modes.
2537                  * this is not necessary if the lower
2538                  * verified_link_cap is enough to drive
2539                  * all the modes */
2540
2541                 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
2542                 /* if (flags.DYNAMIC_VALIDATION == 1)
2543                         dpsst->max_req_bw_for_verified_linkcap = dal_max(
2544                                 dpsst->max_req_bw_for_verified_linkcap, req_bw); */
2545                 return true;
2546         } else
2547                 return false;
2548 }
2549
2550 static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
2551 {
2552         struct dc_link_settings initial_link_setting = {
2553                 LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED, false, 0};
2554         struct dc_link_settings current_link_setting =
2555                         initial_link_setting;
2556         uint32_t link_bw;
2557
2558         if (req_bw > dc_link_bandwidth_kbps(link, &link->verified_link_cap))
2559                 return false;
2560
2561         /* search for the minimum link setting that:
2562          * 1. is supported according to the link training result
2563          * 2. could support the b/w requested by the timing
2564          */
2565         while (current_link_setting.link_rate <=
2566                         link->verified_link_cap.link_rate) {
2567                 link_bw = dc_link_bandwidth_kbps(
2568                                 link,
2569                                 &current_link_setting);
2570                 if (req_bw <= link_bw) {
2571                         *link_setting = current_link_setting;
2572                         return true;
2573                 }
2574
2575                 if (current_link_setting.lane_count <
2576                                 link->verified_link_cap.lane_count) {
2577                         current_link_setting.lane_count =
2578                                         increase_lane_count(
2579                                                         current_link_setting.lane_count);
2580                 } else {
2581                         current_link_setting.link_rate =
2582                                         increase_link_rate(
2583                                                         current_link_setting.link_rate);
2584                         current_link_setting.lane_count =
2585                                         initial_link_setting.lane_count;
2586                 }
2587         }
2588
2589         return false;
2590 }
2591
2592 bool decide_edp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
2593 {
2594         struct dc_link_settings initial_link_setting;
2595         struct dc_link_settings current_link_setting;
2596         uint32_t link_bw;
2597
2598         /*
2599          * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
2600          * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
2601          */
2602         if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_13 ||
2603                         link->dpcd_caps.edp_supported_link_rates_count == 0) {
2604                 *link_setting = link->verified_link_cap;
2605                 return true;
2606         }
2607
2608         memset(&initial_link_setting, 0, sizeof(initial_link_setting));
2609         initial_link_setting.lane_count = LANE_COUNT_ONE;
2610         initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0];
2611         initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
2612         initial_link_setting.use_link_rate_set = true;
2613         initial_link_setting.link_rate_set = 0;
2614         current_link_setting = initial_link_setting;
2615
2616         /* search for the minimum link setting that:
2617          * 1. is supported according to the link training result
2618          * 2. could support the b/w requested by the timing
2619          */
2620         while (current_link_setting.link_rate <=
2621                         link->verified_link_cap.link_rate) {
2622                 link_bw = dc_link_bandwidth_kbps(
2623                                 link,
2624                                 &current_link_setting);
2625                 if (req_bw <= link_bw) {
2626                         *link_setting = current_link_setting;
2627                         return true;
2628                 }
2629
2630                 if (current_link_setting.lane_count <
2631                                 link->verified_link_cap.lane_count) {
2632                         current_link_setting.lane_count =
2633                                         increase_lane_count(
2634                                                         current_link_setting.lane_count);
2635                 } else {
2636                         if (current_link_setting.link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
2637                                 current_link_setting.link_rate_set++;
2638                                 current_link_setting.link_rate =
2639                                         link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
2640                                 current_link_setting.lane_count =
2641                                                                         initial_link_setting.lane_count;
2642                         } else
2643                                 break;
2644                 }
2645         }
2646         return false;
2647 }
2648
2649 static bool decide_mst_link_settings(const struct dc_link *link, struct dc_link_settings *link_setting)
2650 {
2651         *link_setting = link->verified_link_cap;
2652         return true;
2653 }
2654
2655 void decide_link_settings(struct dc_stream_state *stream,
2656         struct dc_link_settings *link_setting)
2657 {
2658         struct dc_link *link;
2659         uint32_t req_bw;
2660
2661         req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing);
2662
2663         link = stream->link;
2664
2665         /* if preferred is specified through AMDDP, use it, if it's enough
2666          * to drive the mode
2667          */
2668         if (link->preferred_link_setting.lane_count !=
2669                         LANE_COUNT_UNKNOWN &&
2670                         link->preferred_link_setting.link_rate !=
2671                                         LINK_RATE_UNKNOWN) {
2672                 *link_setting =  link->preferred_link_setting;
2673                 return;
2674         }
2675
2676         /* MST doesn't perform link training for now
2677          * TODO: add MST specific link training routine
2678          */
2679         if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2680                 if (decide_mst_link_settings(link, link_setting))
2681                         return;
2682         } else if (link->connector_signal == SIGNAL_TYPE_EDP) {
2683                 if (decide_edp_link_settings(link, link_setting, req_bw))
2684                         return;
2685         } else if (decide_dp_link_settings(link, link_setting, req_bw))
2686                 return;
2687
2688         BREAK_TO_DEBUGGER();
2689         ASSERT(link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN);
2690
2691         *link_setting = link->verified_link_cap;
2692 }
2693
2694 /*************************Short Pulse IRQ***************************/
2695 static bool allow_hpd_rx_irq(const struct dc_link *link)
2696 {
2697         /*
2698          * Don't handle RX IRQ unless one of following is met:
2699          * 1) The link is established (cur_link_settings != unknown)
2700          * 2) We know we're dealing with a branch device, SST or MST
2701          */
2702
2703         if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
2704                 is_dp_branch_device(link))
2705                 return true;
2706
2707         return false;
2708 }
2709
2710 static bool handle_hpd_irq_psr_sink(struct dc_link *link)
2711 {
2712         union dpcd_psr_configuration psr_configuration;
2713
2714         if (!link->psr_settings.psr_feature_enabled)
2715                 return false;
2716
2717         dm_helpers_dp_read_dpcd(
2718                 link->ctx,
2719                 link,
2720                 368,/*DpcdAddress_PSR_Enable_Cfg*/
2721                 &psr_configuration.raw,
2722                 sizeof(psr_configuration.raw));
2723
2724
2725         if (psr_configuration.bits.ENABLE) {
2726                 unsigned char dpcdbuf[3] = {0};
2727                 union psr_error_status psr_error_status;
2728                 union psr_sink_psr_status psr_sink_psr_status;
2729
2730                 dm_helpers_dp_read_dpcd(
2731                         link->ctx,
2732                         link,
2733                         0x2006, /*DpcdAddress_PSR_Error_Status*/
2734                         (unsigned char *) dpcdbuf,
2735                         sizeof(dpcdbuf));
2736
2737                 /*DPCD 2006h   ERROR STATUS*/
2738                 psr_error_status.raw = dpcdbuf[0];
2739                 /*DPCD 2008h   SINK PANEL SELF REFRESH STATUS*/
2740                 psr_sink_psr_status.raw = dpcdbuf[2];
2741
2742                 if (psr_error_status.bits.LINK_CRC_ERROR ||
2743                                 psr_error_status.bits.RFB_STORAGE_ERROR ||
2744                                 psr_error_status.bits.VSC_SDP_ERROR) {
2745                         /* Acknowledge and clear error bits */
2746                         dm_helpers_dp_write_dpcd(
2747                                 link->ctx,
2748                                 link,
2749                                 8198,/*DpcdAddress_PSR_Error_Status*/
2750                                 &psr_error_status.raw,
2751                                 sizeof(psr_error_status.raw));
2752
2753                         /* PSR error, disable and re-enable PSR */
2754                         dc_link_set_psr_allow_active(link, false, true, false);
2755                         dc_link_set_psr_allow_active(link, true, true, false);
2756
2757                         return true;
2758                 } else if (psr_sink_psr_status.bits.SINK_SELF_REFRESH_STATUS ==
2759                                 PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB){
2760                         /* No error is detect, PSR is active.
2761                          * We should return with IRQ_HPD handled without
2762                          * checking for loss of sync since PSR would have
2763                          * powered down main link.
2764                          */
2765                         return true;
2766                 }
2767         }
2768         return false;
2769 }
2770
2771 static void dp_test_send_link_training(struct dc_link *link)
2772 {
2773         struct dc_link_settings link_settings = {0};
2774
2775         core_link_read_dpcd(
2776                         link,
2777                         DP_TEST_LANE_COUNT,
2778                         (unsigned char *)(&link_settings.lane_count),
2779                         1);
2780         core_link_read_dpcd(
2781                         link,
2782                         DP_TEST_LINK_RATE,
2783                         (unsigned char *)(&link_settings.link_rate),
2784                         1);
2785
2786         /* Set preferred link settings */
2787         link->verified_link_cap.lane_count = link_settings.lane_count;
2788         link->verified_link_cap.link_rate = link_settings.link_rate;
2789
2790         dp_retrain_link_dp_test(link, &link_settings, false);
2791 }
2792
2793 /* TODO Raven hbr2 compliance eye output is unstable
2794  * (toggling on and off) with debugger break
2795  * This caueses intermittent PHY automation failure
2796  * Need to look into the root cause */
2797 static void dp_test_send_phy_test_pattern(struct dc_link *link)
2798 {
2799         union phy_test_pattern dpcd_test_pattern;
2800         union lane_adjust dpcd_lane_adjustment[2];
2801         unsigned char dpcd_post_cursor_2_adjustment = 0;
2802         unsigned char test_pattern_buffer[
2803                         (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2804                         DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1] = {0};
2805         unsigned int test_pattern_size = 0;
2806         enum dp_test_pattern test_pattern;
2807         struct dc_link_training_settings link_settings;
2808         union lane_adjust dpcd_lane_adjust;
2809         unsigned int lane;
2810         struct link_training_settings link_training_settings;
2811         int i = 0;
2812
2813         dpcd_test_pattern.raw = 0;
2814         memset(dpcd_lane_adjustment, 0, sizeof(dpcd_lane_adjustment));
2815         memset(&link_settings, 0, sizeof(link_settings));
2816
2817         /* get phy test pattern and pattern parameters from DP receiver */
2818         core_link_read_dpcd(
2819                         link,
2820                         DP_PHY_TEST_PATTERN,
2821                         &dpcd_test_pattern.raw,
2822                         sizeof(dpcd_test_pattern));
2823         core_link_read_dpcd(
2824                         link,
2825                         DP_ADJUST_REQUEST_LANE0_1,
2826                         &dpcd_lane_adjustment[0].raw,
2827                         sizeof(dpcd_lane_adjustment));
2828
2829         /*get post cursor 2 parameters
2830          * For DP 1.1a or eariler, this DPCD register's value is 0
2831          * For DP 1.2 or later:
2832          * Bits 1:0 = POST_CURSOR2_LANE0; Bits 3:2 = POST_CURSOR2_LANE1
2833          * Bits 5:4 = POST_CURSOR2_LANE2; Bits 7:6 = POST_CURSOR2_LANE3
2834          */
2835         core_link_read_dpcd(
2836                         link,
2837                         DP_ADJUST_REQUEST_POST_CURSOR2,
2838                         &dpcd_post_cursor_2_adjustment,
2839                         sizeof(dpcd_post_cursor_2_adjustment));
2840
2841         /* translate request */
2842         switch (dpcd_test_pattern.bits.PATTERN) {
2843         case PHY_TEST_PATTERN_D10_2:
2844                 test_pattern = DP_TEST_PATTERN_D102;
2845                 break;
2846         case PHY_TEST_PATTERN_SYMBOL_ERROR:
2847                 test_pattern = DP_TEST_PATTERN_SYMBOL_ERROR;
2848                 break;
2849         case PHY_TEST_PATTERN_PRBS7:
2850                 test_pattern = DP_TEST_PATTERN_PRBS7;
2851                 break;
2852         case PHY_TEST_PATTERN_80BIT_CUSTOM:
2853                 test_pattern = DP_TEST_PATTERN_80BIT_CUSTOM;
2854                 break;
2855         case PHY_TEST_PATTERN_CP2520_1:
2856                 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
2857                 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
2858                                 DP_TEST_PATTERN_TRAINING_PATTERN4 :
2859                                 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
2860                 break;
2861         case PHY_TEST_PATTERN_CP2520_2:
2862                 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
2863                 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
2864                                 DP_TEST_PATTERN_TRAINING_PATTERN4 :
2865                                 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
2866                 break;
2867         case PHY_TEST_PATTERN_CP2520_3:
2868                 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4;
2869                 break;
2870         default:
2871                 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
2872         break;
2873         }
2874
2875         if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) {
2876                 test_pattern_size = (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2877                                 DP_TEST_80BIT_CUSTOM_PATTERN_7_0) + 1;
2878                 core_link_read_dpcd(
2879                                 link,
2880                                 DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
2881                                 test_pattern_buffer,
2882                                 test_pattern_size);
2883         }
2884
2885         /* prepare link training settings */
2886         link_settings.link = link->cur_link_settings;
2887
2888         for (lane = 0; lane <
2889                 (unsigned int)(link->cur_link_settings.lane_count);
2890                 lane++) {
2891                 dpcd_lane_adjust.raw =
2892                         get_nibble_at_index(&dpcd_lane_adjustment[0].raw, lane);
2893                 link_settings.lane_settings[lane].VOLTAGE_SWING =
2894                         (enum dc_voltage_swing)
2895                         (dpcd_lane_adjust.bits.VOLTAGE_SWING_LANE);
2896                 link_settings.lane_settings[lane].PRE_EMPHASIS =
2897                         (enum dc_pre_emphasis)
2898                         (dpcd_lane_adjust.bits.PRE_EMPHASIS_LANE);
2899                 link_settings.lane_settings[lane].POST_CURSOR2 =
2900                         (enum dc_post_cursor2)
2901                         ((dpcd_post_cursor_2_adjustment >> (lane * 2)) & 0x03);
2902         }
2903
2904         for (i = 0; i < 4; i++)
2905                 link_training_settings.lane_settings[i] =
2906                                 link_settings.lane_settings[i];
2907         link_training_settings.link_settings = link_settings.link;
2908         link_training_settings.allow_invalid_msa_timing_param = false;
2909         /*Usage: Measure DP physical lane signal
2910          * by DP SI test equipment automatically.
2911          * PHY test pattern request is generated by equipment via HPD interrupt.
2912          * HPD needs to be active all the time. HPD should be active
2913          * all the time. Do not touch it.
2914          * forward request to DS
2915          */
2916         dc_link_dp_set_test_pattern(
2917                 link,
2918                 test_pattern,
2919                 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED,
2920                 &link_training_settings,
2921                 test_pattern_buffer,
2922                 test_pattern_size);
2923 }
2924
2925 static void dp_test_send_link_test_pattern(struct dc_link *link)
2926 {
2927         union link_test_pattern dpcd_test_pattern;
2928         union test_misc dpcd_test_params;
2929         enum dp_test_pattern test_pattern;
2930         enum dp_test_pattern_color_space test_pattern_color_space =
2931                         DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED;
2932         enum dc_color_depth requestColorDepth = COLOR_DEPTH_UNDEFINED;
2933         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
2934         struct pipe_ctx *pipe_ctx = NULL;
2935         int i;
2936
2937         memset(&dpcd_test_pattern, 0, sizeof(dpcd_test_pattern));
2938         memset(&dpcd_test_params, 0, sizeof(dpcd_test_params));
2939
2940         for (i = 0; i < MAX_PIPES; i++) {
2941                 if (pipes[i].stream == NULL)
2942                         continue;
2943
2944                 if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
2945                         pipe_ctx = &pipes[i];
2946                         break;
2947                 }
2948         }
2949
2950         if (pipe_ctx == NULL)
2951                 return;
2952
2953         /* get link test pattern and pattern parameters */
2954         core_link_read_dpcd(
2955                         link,
2956                         DP_TEST_PATTERN,
2957                         &dpcd_test_pattern.raw,
2958                         sizeof(dpcd_test_pattern));
2959         core_link_read_dpcd(
2960                         link,
2961                         DP_TEST_MISC0,
2962                         &dpcd_test_params.raw,
2963                         sizeof(dpcd_test_params));
2964
2965         switch (dpcd_test_pattern.bits.PATTERN) {
2966         case LINK_TEST_PATTERN_COLOR_RAMP:
2967                 test_pattern = DP_TEST_PATTERN_COLOR_RAMP;
2968         break;
2969         case LINK_TEST_PATTERN_VERTICAL_BARS:
2970                 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;
2971         break; /* black and white */
2972         case LINK_TEST_PATTERN_COLOR_SQUARES:
2973                 test_pattern = (dpcd_test_params.bits.DYN_RANGE ==
2974                                 TEST_DYN_RANGE_VESA ?
2975                                 DP_TEST_PATTERN_COLOR_SQUARES :
2976                                 DP_TEST_PATTERN_COLOR_SQUARES_CEA);
2977         break;
2978         default:
2979                 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
2980         break;
2981         }
2982
2983         if (dpcd_test_params.bits.CLR_FORMAT == 0)
2984                 test_pattern_color_space = DP_TEST_PATTERN_COLOR_SPACE_RGB;
2985         else
2986                 test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ?
2987                                 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 :
2988                                 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601;
2989
2990         switch (dpcd_test_params.bits.BPC) {
2991         case 0: // 6 bits
2992                 requestColorDepth = COLOR_DEPTH_666;
2993                 break;
2994         case 1: // 8 bits
2995                 requestColorDepth = COLOR_DEPTH_888;
2996                 break;
2997         case 2: // 10 bits
2998                 requestColorDepth = COLOR_DEPTH_101010;
2999                 break;
3000         case 3: // 12 bits
3001                 requestColorDepth = COLOR_DEPTH_121212;
3002                 break;
3003         default:
3004                 break;
3005         }
3006
3007         switch (dpcd_test_params.bits.CLR_FORMAT) {
3008         case 0:
3009                 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_RGB;
3010                 break;
3011         case 1:
3012                 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_YCBCR422;
3013                 break;
3014         case 2:
3015                 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_YCBCR444;
3016                 break;
3017         default:
3018                 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_RGB;
3019                 break;
3020         }
3021
3022
3023         if (requestColorDepth != COLOR_DEPTH_UNDEFINED
3024                         && pipe_ctx->stream->timing.display_color_depth != requestColorDepth) {
3025                 DC_LOG_DEBUG("%s: original bpc %d, changing to %d\n",
3026                                 __func__,
3027                                 pipe_ctx->stream->timing.display_color_depth,
3028                                 requestColorDepth);
3029                 pipe_ctx->stream->timing.display_color_depth = requestColorDepth;
3030         }
3031
3032         dp_update_dsc_config(pipe_ctx);
3033
3034         dc_link_dp_set_test_pattern(
3035                         link,
3036                         test_pattern,
3037                         test_pattern_color_space,
3038                         NULL,
3039                         NULL,
3040                         0);
3041 }
3042
3043 static void dp_test_get_audio_test_data(struct dc_link *link, bool disable_video)
3044 {
3045         union audio_test_mode            dpcd_test_mode = {0};
3046         struct audio_test_pattern_type   dpcd_pattern_type = {0};
3047         union audio_test_pattern_period  dpcd_pattern_period[AUDIO_CHANNELS_COUNT] = {0};
3048         enum dp_test_pattern test_pattern = DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
3049
3050         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
3051         struct pipe_ctx *pipe_ctx = &pipes[0];
3052         unsigned int channel_count;
3053         unsigned int channel = 0;
3054         unsigned int modes = 0;
3055         unsigned int sampling_rate_in_hz = 0;
3056
3057         // get audio test mode and test pattern parameters
3058         core_link_read_dpcd(
3059                 link,
3060                 DP_TEST_AUDIO_MODE,
3061                 &dpcd_test_mode.raw,
3062                 sizeof(dpcd_test_mode));
3063
3064         core_link_read_dpcd(
3065                 link,
3066                 DP_TEST_AUDIO_PATTERN_TYPE,
3067                 &dpcd_pattern_type.value,
3068                 sizeof(dpcd_pattern_type));
3069
3070         channel_count = dpcd_test_mode.bits.channel_count + 1;
3071
3072         // read pattern periods for requested channels when sawTooth pattern is requested
3073         if (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH ||
3074                         dpcd_pattern_type.value == AUDIO_TEST_PATTERN_OPERATOR_DEFINED) {
3075
3076                 test_pattern = (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH) ?
3077                                 DP_TEST_PATTERN_AUDIO_SAWTOOTH : DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
3078                 // read period for each channel
3079                 for (channel = 0; channel < channel_count; channel++) {
3080                         core_link_read_dpcd(
3081                                                         link,
3082                                                         DP_TEST_AUDIO_PERIOD_CH1 + channel,
3083                                                         &dpcd_pattern_period[channel].raw,
3084                                                         sizeof(dpcd_pattern_period[channel]));
3085                 }
3086         }
3087
3088         // translate sampling rate
3089         switch (dpcd_test_mode.bits.sampling_rate) {
3090         case AUDIO_SAMPLING_RATE_32KHZ:
3091                 sampling_rate_in_hz = 32000;
3092                 break;
3093         case AUDIO_SAMPLING_RATE_44_1KHZ:
3094                 sampling_rate_in_hz = 44100;
3095                 break;
3096         case AUDIO_SAMPLING_RATE_48KHZ:
3097                 sampling_rate_in_hz = 48000;
3098                 break;
3099         case AUDIO_SAMPLING_RATE_88_2KHZ:
3100                 sampling_rate_in_hz = 88200;
3101                 break;
3102         case AUDIO_SAMPLING_RATE_96KHZ:
3103                 sampling_rate_in_hz = 96000;
3104                 break;
3105         case AUDIO_SAMPLING_RATE_176_4KHZ:
3106                 sampling_rate_in_hz = 176400;
3107                 break;
3108         case AUDIO_SAMPLING_RATE_192KHZ:
3109                 sampling_rate_in_hz = 192000;
3110                 break;
3111         default:
3112                 sampling_rate_in_hz = 0;
3113                 break;
3114         }
3115
3116         link->audio_test_data.flags.test_requested = 1;
3117         link->audio_test_data.flags.disable_video = disable_video;
3118         link->audio_test_data.sampling_rate = sampling_rate_in_hz;
3119         link->audio_test_data.channel_count = channel_count;
3120         link->audio_test_data.pattern_type = test_pattern;
3121
3122         if (test_pattern == DP_TEST_PATTERN_AUDIO_SAWTOOTH) {
3123                 for (modes = 0; modes < pipe_ctx->stream->audio_info.mode_count; modes++) {
3124                         link->audio_test_data.pattern_period[modes] = dpcd_pattern_period[modes].bits.pattern_period;
3125                 }
3126         }
3127 }
3128
3129 static void handle_automated_test(struct dc_link *link)
3130 {
3131         union test_request test_request;
3132         union test_response test_response;
3133
3134         memset(&test_request, 0, sizeof(test_request));
3135         memset(&test_response, 0, sizeof(test_response));
3136
3137         core_link_read_dpcd(
3138                 link,
3139                 DP_TEST_REQUEST,
3140                 &test_request.raw,
3141                 sizeof(union test_request));
3142         if (test_request.bits.LINK_TRAINING) {
3143                 /* ACK first to let DP RX test box monitor LT sequence */
3144                 test_response.bits.ACK = 1;
3145                 core_link_write_dpcd(
3146                         link,
3147                         DP_TEST_RESPONSE,
3148                         &test_response.raw,
3149                         sizeof(test_response));
3150                 dp_test_send_link_training(link);
3151                 /* no acknowledge request is needed again */
3152                 test_response.bits.ACK = 0;
3153         }
3154         if (test_request.bits.LINK_TEST_PATTRN) {
3155                 dp_test_send_link_test_pattern(link);
3156                 test_response.bits.ACK = 1;
3157         }
3158
3159         if (test_request.bits.AUDIO_TEST_PATTERN) {
3160                 dp_test_get_audio_test_data(link, test_request.bits.TEST_AUDIO_DISABLED_VIDEO);
3161                 test_response.bits.ACK = 1;
3162         }
3163
3164         if (test_request.bits.PHY_TEST_PATTERN) {
3165                 dp_test_send_phy_test_pattern(link);
3166                 test_response.bits.ACK = 1;
3167         }
3168
3169         /* send request acknowledgment */
3170         if (test_response.bits.ACK)
3171                 core_link_write_dpcd(
3172                         link,
3173                         DP_TEST_RESPONSE,
3174                         &test_response.raw,
3175                         sizeof(test_response));
3176 }
3177
3178 bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd_irq_dpcd_data, bool *out_link_loss)
3179 {
3180         union hpd_irq_data hpd_irq_dpcd_data = { { { {0} } } };
3181         union device_service_irq device_service_clear = { { 0 } };
3182         enum dc_status result;
3183         bool status = false;
3184         struct pipe_ctx *pipe_ctx;
3185         int i;
3186
3187         if (out_link_loss)
3188                 *out_link_loss = false;
3189         /* For use cases related to down stream connection status change,
3190          * PSR and device auto test, refer to function handle_sst_hpd_irq
3191          * in DAL2.1*/
3192
3193         DC_LOG_HW_HPD_IRQ("%s: Got short pulse HPD on link %d\n",
3194                 __func__, link->link_index);
3195
3196
3197          /* All the "handle_hpd_irq_xxx()" methods
3198                  * should be called only after
3199                  * dal_dpsst_ls_read_hpd_irq_data
3200                  * Order of calls is important too
3201                  */
3202         result = read_hpd_rx_irq_data(link, &hpd_irq_dpcd_data);
3203         if (out_hpd_irq_dpcd_data)
3204                 *out_hpd_irq_dpcd_data = hpd_irq_dpcd_data;
3205
3206         if (result != DC_OK) {
3207                 DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain irq data\n",
3208                         __func__);
3209                 return false;
3210         }
3211
3212         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3213                 device_service_clear.bits.AUTOMATED_TEST = 1;
3214                 core_link_write_dpcd(
3215                         link,
3216                         DP_DEVICE_SERVICE_IRQ_VECTOR,
3217                         &device_service_clear.raw,
3218                         sizeof(device_service_clear.raw));
3219                 device_service_clear.raw = 0;
3220                 handle_automated_test(link);
3221                 return false;
3222         }
3223
3224         if (!allow_hpd_rx_irq(link)) {
3225                 DC_LOG_HW_HPD_IRQ("%s: skipping HPD handling on %d\n",
3226                         __func__, link->link_index);
3227                 return false;
3228         }
3229
3230         if (handle_hpd_irq_psr_sink(link))
3231                 /* PSR-related error was detected and handled */
3232                 return true;
3233
3234         /* If PSR-related error handled, Main link may be off,
3235          * so do not handle as a normal sink status change interrupt.
3236          */
3237
3238         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY)
3239                 return true;
3240
3241         /* check if we have MST msg and return since we poll for it */
3242         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY)
3243                 return false;
3244
3245         /* For now we only handle 'Downstream port status' case.
3246          * If we got sink count changed it means
3247          * Downstream port status changed,
3248          * then DM should call DC to do the detection.
3249          * NOTE: Do not handle link loss on eDP since it is internal link*/
3250         if ((link->connector_signal != SIGNAL_TYPE_EDP) &&
3251                 hpd_rx_irq_check_link_loss_status(
3252                         link,
3253                         &hpd_irq_dpcd_data)) {
3254                 /* Connectivity log: link loss */
3255                 CONN_DATA_LINK_LOSS(link,
3256                                         hpd_irq_dpcd_data.raw,
3257                                         sizeof(hpd_irq_dpcd_data),
3258                                         "Status: ");
3259
3260                 for (i = 0; i < MAX_PIPES; i++) {
3261                         pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3262                         if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link)
3263                                 break;
3264                 }
3265
3266                 if (pipe_ctx == NULL || pipe_ctx->stream == NULL)
3267                         return false;
3268
3269
3270                 for (i = 0; i < MAX_PIPES; i++) {
3271                         pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3272                         if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
3273                                         pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe)
3274                                 core_link_disable_stream(pipe_ctx);
3275                 }
3276
3277                 for (i = 0; i < MAX_PIPES; i++) {
3278                         pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3279                         if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
3280                                         pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe)
3281                                 core_link_enable_stream(link->dc->current_state, pipe_ctx);
3282                 }
3283
3284                 status = false;
3285                 if (out_link_loss)
3286                         *out_link_loss = true;
3287         }
3288
3289         if (link->type == dc_connection_sst_branch &&
3290                 hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT
3291                         != link->dpcd_sink_count)
3292                 status = true;
3293
3294         /* reasons for HPD RX:
3295          * 1. Link Loss - ie Re-train the Link
3296          * 2. MST sideband message
3297          * 3. Automated Test - ie. Internal Commit
3298          * 4. CP (copy protection) - (not interesting for DM???)
3299          * 5. DRR
3300          * 6. Downstream Port status changed
3301          * -ie. Detect - this the only one
3302          * which is interesting for DM because
3303          * it must call dc_link_detect.
3304          */
3305         return status;
3306 }
3307
3308 /*query dpcd for version and mst cap addresses*/
3309 bool is_mst_supported(struct dc_link *link)
3310 {
3311         bool mst          = false;
3312         enum dc_status st = DC_OK;
3313         union dpcd_rev rev;
3314         union mstm_cap cap;
3315
3316         if (link->preferred_training_settings.mst_enable &&
3317                 *link->preferred_training_settings.mst_enable == false) {
3318                 return false;
3319         }
3320
3321         rev.raw  = 0;
3322         cap.raw  = 0;
3323
3324         st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw,
3325                         sizeof(rev));
3326
3327         if (st == DC_OK && rev.raw >= DPCD_REV_12) {
3328
3329                 st = core_link_read_dpcd(link, DP_MSTM_CAP,
3330                                 &cap.raw, sizeof(cap));
3331                 if (st == DC_OK && cap.bits.MST_CAP == 1)
3332                         mst = true;
3333         }
3334         return mst;
3335
3336 }
3337
3338 bool is_dp_active_dongle(const struct dc_link *link)
3339 {
3340         return (link->dpcd_caps.dongle_type >= DISPLAY_DONGLE_DP_VGA_CONVERTER) &&
3341                                 (link->dpcd_caps.dongle_type <= DISPLAY_DONGLE_DP_HDMI_CONVERTER);
3342 }
3343
3344 bool is_dp_branch_device(const struct dc_link *link)
3345 {
3346         return link->dpcd_caps.is_branch_dev;
3347 }
3348
3349 static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)
3350 {
3351         switch (bpc) {
3352         case DOWN_STREAM_MAX_8BPC:
3353                 return 8;
3354         case DOWN_STREAM_MAX_10BPC:
3355                 return 10;
3356         case DOWN_STREAM_MAX_12BPC:
3357                 return 12;
3358         case DOWN_STREAM_MAX_16BPC:
3359                 return 16;
3360         default:
3361                 break;
3362         }
3363
3364         return -1;
3365 }
3366
3367 static void read_dp_device_vendor_id(struct dc_link *link)
3368 {
3369         struct dp_device_vendor_id dp_id;
3370
3371         /* read IEEE branch device id */
3372         core_link_read_dpcd(
3373                 link,
3374                 DP_BRANCH_OUI,
3375                 (uint8_t *)&dp_id,
3376                 sizeof(dp_id));
3377
3378         link->dpcd_caps.branch_dev_id =
3379                 (dp_id.ieee_oui[0] << 16) +
3380                 (dp_id.ieee_oui[1] << 8) +
3381                 dp_id.ieee_oui[2];
3382
3383         memmove(
3384                 link->dpcd_caps.branch_dev_name,
3385                 dp_id.ieee_device_id,
3386                 sizeof(dp_id.ieee_device_id));
3387 }
3388
3389
3390
3391 static void get_active_converter_info(
3392         uint8_t data, struct dc_link *link)
3393 {
3394         union dp_downstream_port_present ds_port = { .byte = data };
3395         memset(&link->dpcd_caps.dongle_caps, 0, sizeof(link->dpcd_caps.dongle_caps));
3396
3397         /* decode converter info*/
3398         if (!ds_port.fields.PORT_PRESENT) {
3399                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3400                 ddc_service_set_dongle_type(link->ddc,
3401                                 link->dpcd_caps.dongle_type);
3402                 link->dpcd_caps.is_branch_dev = false;
3403                 return;
3404         }
3405
3406         /* DPCD 0x5 bit 0 = 1, it indicate it's branch device */
3407         link->dpcd_caps.is_branch_dev = ds_port.fields.PORT_PRESENT;
3408
3409         switch (ds_port.fields.PORT_TYPE) {
3410         case DOWNSTREAM_VGA:
3411                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER;
3412                 break;
3413         case DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS:
3414                 /* At this point we don't know is it DVI or HDMI or DP++,
3415                  * assume DVI.*/
3416                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER;
3417                 break;
3418         default:
3419                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3420                 break;
3421         }
3422
3423         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) {
3424                 uint8_t det_caps[16]; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/
3425                 union dwnstream_port_caps_byte0 *port_caps =
3426                         (union dwnstream_port_caps_byte0 *)det_caps;
3427                 if (core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0,
3428                                 det_caps, sizeof(det_caps)) == DC_OK) {
3429
3430                         switch (port_caps->bits.DWN_STRM_PORTX_TYPE) {
3431                         /*Handle DP case as DONGLE_NONE*/
3432                         case DOWN_STREAM_DETAILED_DP:
3433                                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3434                                 break;
3435                         case DOWN_STREAM_DETAILED_VGA:
3436                                 link->dpcd_caps.dongle_type =
3437                                         DISPLAY_DONGLE_DP_VGA_CONVERTER;
3438                                 break;
3439                         case DOWN_STREAM_DETAILED_DVI:
3440                                 link->dpcd_caps.dongle_type =
3441                                         DISPLAY_DONGLE_DP_DVI_CONVERTER;
3442                                 break;
3443                         case DOWN_STREAM_DETAILED_HDMI:
3444                         case DOWN_STREAM_DETAILED_DP_PLUS_PLUS:
3445                                 /*Handle DP++ active converter case, process DP++ case as HDMI case according DP1.4 spec*/
3446                                 link->dpcd_caps.dongle_type =
3447                                         DISPLAY_DONGLE_DP_HDMI_CONVERTER;
3448
3449                                 link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type;
3450                                 if (ds_port.fields.DETAILED_CAPS) {
3451
3452                                         union dwnstream_port_caps_byte3_hdmi
3453                                                 hdmi_caps = {.raw = det_caps[3] };
3454                                         union dwnstream_port_caps_byte2
3455                                                 hdmi_color_caps = {.raw = det_caps[2] };
3456                                         link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz =
3457                                                 det_caps[1] * 2500;
3458
3459                                         link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter =
3460                                                 hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK;
3461                                         /*YCBCR capability only for HDMI case*/
3462                                         if (port_caps->bits.DWN_STRM_PORTX_TYPE
3463                                                         == DOWN_STREAM_DETAILED_HDMI) {
3464                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through =
3465                                                                 hdmi_caps.bits.YCrCr422_PASS_THROUGH;
3466                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through =
3467                                                                 hdmi_caps.bits.YCrCr420_PASS_THROUGH;
3468                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter =
3469                                                                 hdmi_caps.bits.YCrCr422_CONVERSION;
3470                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter =
3471                                                                 hdmi_caps.bits.YCrCr420_CONVERSION;
3472                                         }
3473
3474                                         link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc =
3475                                                 translate_dpcd_max_bpc(
3476                                                         hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT);
3477
3478                                         if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz != 0)
3479                                                 link->dpcd_caps.dongle_caps.extendedCapValid = true;
3480                                 }
3481
3482                                 break;
3483                         }
3484                 }
3485         }
3486
3487         ddc_service_set_dongle_type(link->ddc, link->dpcd_caps.dongle_type);
3488
3489         {
3490                 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
3491
3492                 core_link_read_dpcd(
3493                         link,
3494                         DP_BRANCH_REVISION_START,
3495                         (uint8_t *)&dp_hw_fw_revision,
3496                         sizeof(dp_hw_fw_revision));
3497
3498                 link->dpcd_caps.branch_hw_revision =
3499                         dp_hw_fw_revision.ieee_hw_rev;
3500
3501                 memmove(
3502                         link->dpcd_caps.branch_fw_revision,
3503                         dp_hw_fw_revision.ieee_fw_rev,
3504                         sizeof(dp_hw_fw_revision.ieee_fw_rev));
3505         }
3506 }
3507
3508 static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
3509                 int length)
3510 {
3511         int retry = 0;
3512
3513         if (!link->dpcd_caps.dpcd_rev.raw) {
3514                 do {
3515                         dp_receiver_power_ctrl(link, true);
3516                         core_link_read_dpcd(link, DP_DPCD_REV,
3517                                                         dpcd_data, length);
3518                         link->dpcd_caps.dpcd_rev.raw = dpcd_data[
3519                                 DP_DPCD_REV -
3520                                 DP_DPCD_REV];
3521                 } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
3522         }
3523
3524         if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
3525                 switch (link->dpcd_caps.branch_dev_id) {
3526                 /* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power down
3527                  * all internal circuits including AUX communication preventing
3528                  * reading DPCD table and EDID (spec violation).
3529                  * Encoder will skip DP RX power down on disable_output to
3530                  * keep receiver powered all the time.*/
3531                 case DP_BRANCH_DEVICE_ID_0010FA:
3532                 case DP_BRANCH_DEVICE_ID_0080E1:
3533                 case DP_BRANCH_DEVICE_ID_00E04C:
3534                         link->wa_flags.dp_keep_receiver_powered = true;
3535                         break;
3536
3537                 /* TODO: May need work around for other dongles. */
3538                 default:
3539                         link->wa_flags.dp_keep_receiver_powered = false;
3540                         break;
3541                 }
3542         } else
3543                 link->wa_flags.dp_keep_receiver_powered = false;
3544 }
3545
3546 /* Read additional sink caps defined in source specific DPCD area
3547  * This function currently only reads from SinkCapability address (DP_SOURCE_SINK_CAP)
3548  */
3549 static bool dpcd_read_sink_ext_caps(struct dc_link *link)
3550 {
3551         uint8_t dpcd_data;
3552
3553         if (!link)
3554                 return false;
3555
3556         if (core_link_read_dpcd(link, DP_SOURCE_SINK_CAP, &dpcd_data, 1) != DC_OK)
3557                 return false;
3558
3559         link->dpcd_sink_ext_caps.raw = dpcd_data;
3560         return true;
3561 }
3562
3563 static bool retrieve_link_cap(struct dc_link *link)
3564 {
3565         /* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16,
3566          * which means size 16 will be good for both of those DPCD register block reads
3567          */
3568         uint8_t dpcd_data[16];
3569         uint8_t lttpr_dpcd_data[6];
3570
3571         /*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST.
3572          */
3573         uint8_t dpcd_dprx_data = '\0';
3574         uint8_t dpcd_power_state = '\0';
3575
3576         struct dp_device_vendor_id sink_id;
3577         union down_stream_port_count down_strm_port_count;
3578         union edp_configuration_cap edp_config_cap;
3579         union dp_downstream_port_present ds_port = { 0 };
3580         enum dc_status status = DC_ERROR_UNEXPECTED;
3581         uint32_t read_dpcd_retry_cnt = 3;
3582         int i;
3583         struct dp_sink_hw_fw_revision dp_hw_fw_revision;
3584         bool is_lttpr_present = false;
3585         const uint32_t post_oui_delay = 30; // 30ms
3586         bool vbios_lttpr_enable = false;
3587         bool vbios_lttpr_interop = false;
3588         struct dc_bios *bios = link->dc->ctx->dc_bios;
3589
3590         memset(dpcd_data, '\0', sizeof(dpcd_data));
3591         memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data));
3592         memset(&down_strm_port_count,
3593                 '\0', sizeof(union down_stream_port_count));
3594         memset(&edp_config_cap, '\0',
3595                 sizeof(union edp_configuration_cap));
3596
3597         /* if extended timeout is supported in hardware,
3598          * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
3599          * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
3600          */
3601         dc_link_aux_try_to_configure_timeout(link->ddc,
3602                         LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
3603
3604         status = core_link_read_dpcd(link, DP_SET_POWER,
3605                                 &dpcd_power_state, sizeof(dpcd_power_state));
3606
3607         /* Delay 1 ms if AUX CH is in power down state. Based on spec
3608          * section 2.3.1.2, if AUX CH may be powered down due to
3609          * write to DPCD 600h = 2. Sink AUX CH is monitoring differential
3610          * signal and may need up to 1 ms before being able to reply.
3611          */
3612         if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3)
3613                 udelay(1000);
3614
3615         dpcd_set_source_specific_data(link);
3616         /* Sink may need to configure internals based on vendor, so allow some
3617          * time before proceeding with possibly vendor specific transactions
3618          */
3619         msleep(post_oui_delay);
3620
3621         for (i = 0; i < read_dpcd_retry_cnt; i++) {
3622                 status = core_link_read_dpcd(
3623                                 link,
3624                                 DP_DPCD_REV,
3625                                 dpcd_data,
3626                                 sizeof(dpcd_data));
3627                 if (status == DC_OK)
3628                         break;
3629         }
3630
3631         if (status != DC_OK) {
3632                 dm_error("%s: Read dpcd data failed.\n", __func__);
3633                 return false;
3634         }
3635
3636         /* Query BIOS to determine if LTTPR functionality is forced on by system */
3637         if (bios->funcs->get_lttpr_caps) {
3638                 enum bp_result bp_query_result;
3639                 uint8_t is_vbios_lttpr_enable = 0;
3640
3641                 bp_query_result = bios->funcs->get_lttpr_caps(bios, &is_vbios_lttpr_enable);
3642                 vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
3643         }
3644
3645         if (bios->funcs->get_lttpr_interop) {
3646                 enum bp_result bp_query_result;
3647                 uint8_t is_vbios_interop_enabled = 0;
3648
3649                 bp_query_result = bios->funcs->get_lttpr_interop(bios, &is_vbios_interop_enabled);
3650                 vbios_lttpr_interop = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
3651         }
3652
3653         /*
3654          * Logic to determine LTTPR mode
3655          */
3656         link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
3657         if (vbios_lttpr_enable && vbios_lttpr_interop)
3658                 link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
3659         else if (!vbios_lttpr_enable && vbios_lttpr_interop) {
3660                 if (link->dc->config.allow_lttpr_non_transparent_mode)
3661                         link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
3662                 else
3663                         link->lttpr_mode = LTTPR_MODE_TRANSPARENT;
3664         } else if (!vbios_lttpr_enable && !vbios_lttpr_interop) {
3665                 if (!link->dc->config.allow_lttpr_non_transparent_mode
3666                         || !link->dc->caps.extended_aux_timeout_support)
3667                         link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
3668                 else
3669                         link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
3670         }
3671
3672         if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT || link->lttpr_mode == LTTPR_MODE_TRANSPARENT) {
3673                 /* By reading LTTPR capability, RX assumes that we will enable
3674                  * LTTPR extended aux timeout if LTTPR is present.
3675                  */
3676                 status = core_link_read_dpcd(
3677                                 link,
3678                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
3679                                 lttpr_dpcd_data,
3680                                 sizeof(lttpr_dpcd_data));
3681
3682                 link->dpcd_caps.lttpr_caps.revision.raw =
3683                                 lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV -
3684                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3685
3686                 link->dpcd_caps.lttpr_caps.max_link_rate =
3687                                 lttpr_dpcd_data[DP_MAX_LINK_RATE_PHY_REPEATER -
3688                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3689
3690                 link->dpcd_caps.lttpr_caps.phy_repeater_cnt =
3691                                 lttpr_dpcd_data[DP_PHY_REPEATER_CNT -
3692                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3693
3694                 link->dpcd_caps.lttpr_caps.max_lane_count =
3695                                 lttpr_dpcd_data[DP_MAX_LANE_COUNT_PHY_REPEATER -
3696                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3697
3698                 link->dpcd_caps.lttpr_caps.mode =
3699                                 lttpr_dpcd_data[DP_PHY_REPEATER_MODE -
3700                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3701
3702                 link->dpcd_caps.lttpr_caps.max_ext_timeout =
3703                                 lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT -
3704                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3705
3706                 /* Attempt to train in LTTPR transparent mode if repeater count exceeds 8. */
3707                 is_lttpr_present = (link->dpcd_caps.lttpr_caps.phy_repeater_cnt > 0 &&
3708                                 link->dpcd_caps.lttpr_caps.phy_repeater_cnt < 0xff &&
3709                                 link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&
3710                                 link->dpcd_caps.lttpr_caps.max_lane_count <= 4 &&
3711                                 link->dpcd_caps.lttpr_caps.revision.raw >= 0x14);
3712                 if (is_lttpr_present)
3713                         CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: ");
3714                 else
3715                         link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
3716         }
3717
3718         if (!is_lttpr_present)
3719                 dc_link_aux_try_to_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
3720
3721
3722         {
3723                 union training_aux_rd_interval aux_rd_interval;
3724
3725                 aux_rd_interval.raw =
3726                         dpcd_data[DP_TRAINING_AUX_RD_INTERVAL];
3727
3728                 link->dpcd_caps.ext_receiver_cap_field_present =
3729                                 aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1;
3730
3731                 if (aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1) {
3732                         uint8_t ext_cap_data[16];
3733
3734                         memset(ext_cap_data, '\0', sizeof(ext_cap_data));
3735                         for (i = 0; i < read_dpcd_retry_cnt; i++) {
3736                                 status = core_link_read_dpcd(
3737                                 link,
3738                                 DP_DP13_DPCD_REV,
3739                                 ext_cap_data,
3740                                 sizeof(ext_cap_data));
3741                                 if (status == DC_OK) {
3742                                         memcpy(dpcd_data, ext_cap_data, sizeof(dpcd_data));
3743                                         break;
3744                                 }
3745                         }
3746                         if (status != DC_OK)
3747                                 dm_error("%s: Read extend caps data failed, use cap from dpcd 0.\n", __func__);
3748                 }
3749         }
3750
3751         link->dpcd_caps.dpcd_rev.raw =
3752                         dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
3753
3754         if (link->dpcd_caps.ext_receiver_cap_field_present) {
3755                 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3756                         status = core_link_read_dpcd(
3757                                         link,
3758                                         DP_DPRX_FEATURE_ENUMERATION_LIST,
3759                                         &dpcd_dprx_data,
3760                                         sizeof(dpcd_dprx_data));
3761                         if (status == DC_OK)
3762                                 break;
3763                 }
3764
3765                 link->dpcd_caps.dprx_feature.raw = dpcd_dprx_data;
3766
3767                 if (status != DC_OK)
3768                         dm_error("%s: Read DPRX caps data failed.\n", __func__);
3769         }
3770
3771         else {
3772                 link->dpcd_caps.dprx_feature.raw = 0;
3773         }
3774
3775
3776         /* Error condition checking...
3777          * It is impossible for Sink to report Max Lane Count = 0.
3778          * It is possible for Sink to report Max Link Rate = 0, if it is
3779          * an eDP device that is reporting specialized link rates in the
3780          * SUPPORTED_LINK_RATE table.
3781          */
3782         if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
3783                 return false;
3784
3785         ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
3786                                  DP_DPCD_REV];
3787
3788         read_dp_device_vendor_id(link);
3789
3790         get_active_converter_info(ds_port.byte, link);
3791
3792         dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data));
3793
3794         down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
3795                                  DP_DPCD_REV];
3796
3797         link->dpcd_caps.allow_invalid_MSA_timing_param =
3798                 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
3799
3800         link->dpcd_caps.max_ln_count.raw = dpcd_data[
3801                 DP_MAX_LANE_COUNT - DP_DPCD_REV];
3802
3803         link->dpcd_caps.max_down_spread.raw = dpcd_data[
3804                 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
3805
3806         link->reported_link_cap.lane_count =
3807                 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
3808         link->reported_link_cap.link_rate = dpcd_data[
3809                 DP_MAX_LINK_RATE - DP_DPCD_REV];
3810         link->reported_link_cap.link_spread =
3811                 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
3812                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
3813
3814         edp_config_cap.raw = dpcd_data[
3815                 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
3816         link->dpcd_caps.panel_mode_edp =
3817                 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
3818         link->dpcd_caps.dpcd_display_control_capable =
3819                 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
3820
3821         link->test_pattern_enabled = false;
3822         link->compliance_test_state.raw = 0;
3823
3824         /* read sink count */
3825         core_link_read_dpcd(link,
3826                         DP_SINK_COUNT,
3827                         &link->dpcd_caps.sink_count.raw,
3828                         sizeof(link->dpcd_caps.sink_count.raw));
3829
3830         /* read sink ieee oui */
3831         core_link_read_dpcd(link,
3832                         DP_SINK_OUI,
3833                         (uint8_t *)(&sink_id),
3834                         sizeof(sink_id));
3835
3836         link->dpcd_caps.sink_dev_id =
3837                         (sink_id.ieee_oui[0] << 16) +
3838                         (sink_id.ieee_oui[1] << 8) +
3839                         (sink_id.ieee_oui[2]);
3840
3841         memmove(
3842                 link->dpcd_caps.sink_dev_id_str,
3843                 sink_id.ieee_device_id,
3844                 sizeof(sink_id.ieee_device_id));
3845
3846         /* Quirk Apple MBP 2017 15" Retina panel: Wrong DP_MAX_LINK_RATE */
3847         {
3848                 uint8_t str_mbp_2017[] = { 101, 68, 21, 101, 98, 97 };
3849
3850                 if ((link->dpcd_caps.sink_dev_id == 0x0010fa) &&
3851                     !memcmp(link->dpcd_caps.sink_dev_id_str, str_mbp_2017,
3852                             sizeof(str_mbp_2017))) {
3853                         link->reported_link_cap.link_rate = 0x0c;
3854                 }
3855         }
3856
3857         core_link_read_dpcd(
3858                 link,
3859                 DP_SINK_HW_REVISION_START,
3860                 (uint8_t *)&dp_hw_fw_revision,
3861                 sizeof(dp_hw_fw_revision));
3862
3863         link->dpcd_caps.sink_hw_revision =
3864                 dp_hw_fw_revision.ieee_hw_rev;
3865
3866         memmove(
3867                 link->dpcd_caps.sink_fw_revision,
3868                 dp_hw_fw_revision.ieee_fw_rev,
3869                 sizeof(dp_hw_fw_revision.ieee_fw_rev));
3870
3871         memset(&link->dpcd_caps.dsc_caps, '\0',
3872                         sizeof(link->dpcd_caps.dsc_caps));
3873         memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));
3874         /* Read DSC and FEC sink capabilities if DP revision is 1.4 and up */
3875         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14) {
3876                 status = core_link_read_dpcd(
3877                                 link,
3878                                 DP_FEC_CAPABILITY,
3879                                 &link->dpcd_caps.fec_cap.raw,
3880                                 sizeof(link->dpcd_caps.fec_cap.raw));
3881                 status = core_link_read_dpcd(
3882                                 link,
3883                                 DP_DSC_SUPPORT,
3884                                 link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
3885                                 sizeof(link->dpcd_caps.dsc_caps.dsc_basic_caps.raw));
3886                 status = core_link_read_dpcd(
3887                                 link,
3888                                 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0,
3889                                 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
3890                                 sizeof(link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw));
3891         }
3892
3893         if (!dpcd_read_sink_ext_caps(link))
3894                 link->dpcd_sink_ext_caps.raw = 0;
3895
3896         /* Connectivity log: detection */
3897         CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
3898
3899         return true;
3900 }
3901
3902 bool dp_overwrite_extended_receiver_cap(struct dc_link *link)
3903 {
3904         uint8_t dpcd_data[16];
3905         uint32_t read_dpcd_retry_cnt = 3;
3906         enum dc_status status = DC_ERROR_UNEXPECTED;
3907         union dp_downstream_port_present ds_port = { 0 };
3908         union down_stream_port_count down_strm_port_count;
3909         union edp_configuration_cap edp_config_cap;
3910
3911         int i;
3912
3913         for (i = 0; i < read_dpcd_retry_cnt; i++) {
3914                 status = core_link_read_dpcd(
3915                                 link,
3916                                 DP_DPCD_REV,
3917                                 dpcd_data,
3918                                 sizeof(dpcd_data));
3919                 if (status == DC_OK)
3920                         break;
3921         }
3922
3923         link->dpcd_caps.dpcd_rev.raw =
3924                 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
3925
3926         if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
3927                 return false;
3928
3929         ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
3930                         DP_DPCD_REV];
3931
3932         get_active_converter_info(ds_port.byte, link);
3933
3934         down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
3935                         DP_DPCD_REV];
3936
3937         link->dpcd_caps.allow_invalid_MSA_timing_param =
3938                 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
3939
3940         link->dpcd_caps.max_ln_count.raw = dpcd_data[
3941                 DP_MAX_LANE_COUNT - DP_DPCD_REV];
3942
3943         link->dpcd_caps.max_down_spread.raw = dpcd_data[
3944                 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
3945
3946         link->reported_link_cap.lane_count =
3947                 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
3948         link->reported_link_cap.link_rate = dpcd_data[
3949                 DP_MAX_LINK_RATE - DP_DPCD_REV];
3950         link->reported_link_cap.link_spread =
3951                 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
3952                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
3953
3954         edp_config_cap.raw = dpcd_data[
3955                 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
3956         link->dpcd_caps.panel_mode_edp =
3957                 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
3958         link->dpcd_caps.dpcd_display_control_capable =
3959                 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
3960
3961         return true;
3962 }
3963
3964 bool detect_dp_sink_caps(struct dc_link *link)
3965 {
3966         return retrieve_link_cap(link);
3967
3968         /* dc init_hw has power encoder using default
3969          * signal for connector. For native DP, no
3970          * need to power up encoder again. If not native
3971          * DP, hw_init may need check signal or power up
3972          * encoder here.
3973          */
3974         /* TODO save sink caps in link->sink */
3975 }
3976
3977 static enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz)
3978 {
3979         enum dc_link_rate link_rate;
3980         // LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation.
3981         switch (link_rate_in_khz) {
3982         case 1620000:
3983                 link_rate = LINK_RATE_LOW;              // Rate_1 (RBR)         - 1.62 Gbps/Lane
3984                 break;
3985         case 2160000:
3986                 link_rate = LINK_RATE_RATE_2;   // Rate_2                       - 2.16 Gbps/Lane
3987                 break;
3988         case 2430000:
3989                 link_rate = LINK_RATE_RATE_3;   // Rate_3                       - 2.43 Gbps/Lane
3990                 break;
3991         case 2700000:
3992                 link_rate = LINK_RATE_HIGH;             // Rate_4 (HBR)         - 2.70 Gbps/Lane
3993                 break;
3994         case 3240000:
3995                 link_rate = LINK_RATE_RBR2;             // Rate_5 (RBR2)        - 3.24 Gbps/Lane
3996                 break;
3997         case 4320000:
3998                 link_rate = LINK_RATE_RATE_6;   // Rate_6                       - 4.32 Gbps/Lane
3999                 break;
4000         case 5400000:
4001                 link_rate = LINK_RATE_HIGH2;    // Rate_7 (HBR2)        - 5.40 Gbps/Lane
4002                 break;
4003         case 8100000:
4004                 link_rate = LINK_RATE_HIGH3;    // Rate_8 (HBR3)        - 8.10 Gbps/Lane
4005                 break;
4006         default:
4007                 link_rate = LINK_RATE_UNKNOWN;
4008                 break;
4009         }
4010         return link_rate;
4011 }
4012
4013 void detect_edp_sink_caps(struct dc_link *link)
4014 {
4015         uint8_t supported_link_rates[16];
4016         uint32_t entry;
4017         uint32_t link_rate_in_khz;
4018         enum dc_link_rate link_rate = LINK_RATE_UNKNOWN;
4019         uint8_t backlight_adj_cap;
4020
4021         retrieve_link_cap(link);
4022         link->dpcd_caps.edp_supported_link_rates_count = 0;
4023         memset(supported_link_rates, 0, sizeof(supported_link_rates));
4024
4025         /*
4026          * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
4027          * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
4028          */
4029         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_13 &&
4030                         (link->dc->debug.optimize_edp_link_rate ||
4031                         link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)) {
4032                 // Read DPCD 00010h - 0001Fh 16 bytes at one shot
4033                 core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
4034                                                         supported_link_rates, sizeof(supported_link_rates));
4035
4036                 for (entry = 0; entry < 16; entry += 2) {
4037                         // DPCD register reports per-lane link rate = 16-bit link rate capability
4038                         // value X 200 kHz. Need multiplier to find link rate in kHz.
4039                         link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
4040                                                                                 supported_link_rates[entry]) * 200;
4041
4042                         if (link_rate_in_khz != 0) {
4043                                 link_rate = linkRateInKHzToLinkRateMultiplier(link_rate_in_khz);
4044                                 link->dpcd_caps.edp_supported_link_rates[link->dpcd_caps.edp_supported_link_rates_count] = link_rate;
4045                                 link->dpcd_caps.edp_supported_link_rates_count++;
4046
4047                                 if (link->reported_link_cap.link_rate < link_rate)
4048                                         link->reported_link_cap.link_rate = link_rate;
4049                         }
4050                 }
4051         }
4052         link->verified_link_cap = link->reported_link_cap;
4053
4054         core_link_read_dpcd(link, DP_EDP_BACKLIGHT_ADJUSTMENT_CAP,
4055                                                 &backlight_adj_cap, sizeof(backlight_adj_cap));
4056
4057         link->dpcd_caps.dynamic_backlight_capable_edp =
4058                                 (backlight_adj_cap & DP_EDP_DYNAMIC_BACKLIGHT_CAP) ? true:false;
4059
4060         dc_link_set_default_brightness_aux(link);
4061 }
4062
4063 void dc_link_dp_enable_hpd(const struct dc_link *link)
4064 {
4065         struct link_encoder *encoder = link->link_enc;
4066
4067         if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
4068                 encoder->funcs->enable_hpd(encoder);
4069 }
4070
4071 void dc_link_dp_disable_hpd(const struct dc_link *link)
4072 {
4073         struct link_encoder *encoder = link->link_enc;
4074
4075         if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
4076                 encoder->funcs->disable_hpd(encoder);
4077 }
4078
4079 static bool is_dp_phy_pattern(enum dp_test_pattern test_pattern)
4080 {
4081         if ((DP_TEST_PATTERN_PHY_PATTERN_BEGIN <= test_pattern &&
4082                         test_pattern <= DP_TEST_PATTERN_PHY_PATTERN_END) ||
4083                         test_pattern == DP_TEST_PATTERN_VIDEO_MODE)
4084                 return true;
4085         else
4086                 return false;
4087 }
4088
4089 static void set_crtc_test_pattern(struct dc_link *link,
4090                                 struct pipe_ctx *pipe_ctx,
4091                                 enum dp_test_pattern test_pattern,
4092                                 enum dp_test_pattern_color_space test_pattern_color_space)
4093 {
4094         enum controller_dp_test_pattern controller_test_pattern;
4095         enum dc_color_depth color_depth = pipe_ctx->
4096                 stream->timing.display_color_depth;
4097         struct bit_depth_reduction_params params;
4098         struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;
4099         int width = pipe_ctx->stream->timing.h_addressable +
4100                 pipe_ctx->stream->timing.h_border_left +
4101                 pipe_ctx->stream->timing.h_border_right;
4102         int height = pipe_ctx->stream->timing.v_addressable +
4103                 pipe_ctx->stream->timing.v_border_bottom +
4104                 pipe_ctx->stream->timing.v_border_top;
4105
4106         memset(&params, 0, sizeof(params));
4107
4108         switch (test_pattern) {
4109         case DP_TEST_PATTERN_COLOR_SQUARES:
4110                 controller_test_pattern =
4111                                 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
4112         break;
4113         case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
4114                 controller_test_pattern =
4115                                 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA;
4116         break;
4117         case DP_TEST_PATTERN_VERTICAL_BARS:
4118                 controller_test_pattern =
4119                                 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS;
4120         break;
4121         case DP_TEST_PATTERN_HORIZONTAL_BARS:
4122                 controller_test_pattern =
4123                                 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS;
4124         break;
4125         case DP_TEST_PATTERN_COLOR_RAMP:
4126                 controller_test_pattern =
4127                                 CONTROLLER_DP_TEST_PATTERN_COLORRAMP;
4128         break;
4129         default:
4130                 controller_test_pattern =
4131                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
4132         break;
4133         }
4134
4135         switch (test_pattern) {
4136         case DP_TEST_PATTERN_COLOR_SQUARES:
4137         case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
4138         case DP_TEST_PATTERN_VERTICAL_BARS:
4139         case DP_TEST_PATTERN_HORIZONTAL_BARS:
4140         case DP_TEST_PATTERN_COLOR_RAMP:
4141         {
4142                 /* disable bit depth reduction */
4143                 pipe_ctx->stream->bit_depth_params = params;
4144                 opp->funcs->opp_program_bit_depth_reduction(opp, &params);
4145                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
4146                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4147                                 controller_test_pattern, color_depth);
4148                 else if (link->dc->hwss.set_disp_pattern_generator) {
4149                         struct pipe_ctx *odm_pipe;
4150                         enum controller_dp_color_space controller_color_space;
4151                         int opp_cnt = 1;
4152                         int offset = 0;
4153                         int dpg_width = width;
4154
4155                         switch (test_pattern_color_space) {
4156                         case DP_TEST_PATTERN_COLOR_SPACE_RGB:
4157                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
4158                                 break;
4159                         case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
4160                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR601;
4161                                 break;
4162                         case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
4163                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR709;
4164                                 break;
4165                         case DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED:
4166                         default:
4167                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
4168                                 DC_LOG_ERROR("%s: Color space must be defined for test pattern", __func__);
4169                                 ASSERT(0);
4170                                 break;
4171                         }
4172
4173                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
4174                                 opp_cnt++;
4175                         dpg_width = width / opp_cnt;
4176                         offset = dpg_width;
4177
4178                         link->dc->hwss.set_disp_pattern_generator(link->dc,
4179                                         pipe_ctx,
4180                                         controller_test_pattern,
4181                                         controller_color_space,
4182                                         color_depth,
4183                                         NULL,
4184                                         dpg_width,
4185                                         height,
4186                                         0);
4187
4188                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
4189                                 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
4190
4191                                 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
4192                                 link->dc->hwss.set_disp_pattern_generator(link->dc,
4193                                                 odm_pipe,
4194                                                 controller_test_pattern,
4195                                                 controller_color_space,
4196                                                 color_depth,
4197                                                 NULL,
4198                                                 dpg_width,
4199                                                 height,
4200                                                 offset);
4201                                 offset += offset;
4202                         }
4203                 }
4204         }
4205         break;
4206         case DP_TEST_PATTERN_VIDEO_MODE:
4207         {
4208                 /* restore bitdepth reduction */
4209                 resource_build_bit_depth_reduction_params(pipe_ctx->stream, &params);
4210                 pipe_ctx->stream->bit_depth_params = params;
4211                 opp->funcs->opp_program_bit_depth_reduction(opp, &params);
4212                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
4213                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4214                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4215                                 color_depth);
4216                 else if (link->dc->hwss.set_disp_pattern_generator) {
4217                         struct pipe_ctx *odm_pipe;
4218                         int opp_cnt = 1;
4219                         int dpg_width = width;
4220
4221                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
4222                                 opp_cnt++;
4223
4224                         dpg_width = width / opp_cnt;
4225                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
4226                                 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
4227
4228                                 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
4229                                 link->dc->hwss.set_disp_pattern_generator(link->dc,
4230                                                 odm_pipe,
4231                                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4232                                                 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
4233                                                 color_depth,
4234                                                 NULL,
4235                                                 dpg_width,
4236                                                 height,
4237                                                 0);
4238                         }
4239                         link->dc->hwss.set_disp_pattern_generator(link->dc,
4240                                         pipe_ctx,
4241                                         CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4242                                         CONTROLLER_DP_COLOR_SPACE_UDEFINED,
4243                                         color_depth,
4244                                         NULL,
4245                                         dpg_width,
4246                                         height,
4247                                         0);
4248                 }
4249         }
4250         break;
4251
4252         default:
4253         break;
4254         }
4255 }
4256
4257 bool dc_link_dp_set_test_pattern(
4258         struct dc_link *link,
4259         enum dp_test_pattern test_pattern,
4260         enum dp_test_pattern_color_space test_pattern_color_space,
4261         const struct link_training_settings *p_link_settings,
4262         const unsigned char *p_custom_pattern,
4263         unsigned int cust_pattern_size)
4264 {
4265         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
4266         struct pipe_ctx *pipe_ctx = NULL;
4267         unsigned int lane;
4268         unsigned int i;
4269         unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0};
4270         union dpcd_training_pattern training_pattern;
4271         enum dpcd_phy_test_patterns pattern;
4272
4273         memset(&training_pattern, 0, sizeof(training_pattern));
4274
4275         for (i = 0; i < MAX_PIPES; i++) {
4276                 if (pipes[i].stream == NULL)
4277                         continue;
4278
4279                 if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
4280                         pipe_ctx = &pipes[i];
4281                         break;
4282                 }
4283         }
4284
4285         if (pipe_ctx == NULL)
4286                 return false;
4287
4288         /* Reset CRTC Test Pattern if it is currently running and request is VideoMode */
4289         if (link->test_pattern_enabled && test_pattern ==
4290                         DP_TEST_PATTERN_VIDEO_MODE) {
4291                 /* Set CRTC Test Pattern */
4292                 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
4293                 dp_set_hw_test_pattern(link, test_pattern,
4294                                 (uint8_t *)p_custom_pattern,
4295                                 (uint32_t)cust_pattern_size);
4296
4297                 /* Unblank Stream */
4298                 link->dc->hwss.unblank_stream(
4299                         pipe_ctx,
4300                         &link->verified_link_cap);
4301                 /* TODO:m_pHwss->MuteAudioEndpoint
4302                  * (pPathMode->pDisplayPath, false);
4303                  */
4304
4305                 /* Reset Test Pattern state */
4306                 link->test_pattern_enabled = false;
4307
4308                 return true;
4309         }
4310
4311         /* Check for PHY Test Patterns */
4312         if (is_dp_phy_pattern(test_pattern)) {
4313                 /* Set DPCD Lane Settings before running test pattern */
4314                 if (p_link_settings != NULL) {
4315                         dp_set_hw_lane_settings(link, p_link_settings, DPRX);
4316                         dpcd_set_lane_settings(link, p_link_settings, DPRX);
4317                 }
4318
4319                 /* Blank stream if running test pattern */
4320                 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
4321                         /*TODO:
4322                          * m_pHwss->
4323                          * MuteAudioEndpoint(pPathMode->pDisplayPath, true);
4324                          */
4325                         /* Blank stream */
4326                         pipes->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
4327                 }
4328
4329                 dp_set_hw_test_pattern(link, test_pattern,
4330                                 (uint8_t *)p_custom_pattern,
4331                                 (uint32_t)cust_pattern_size);
4332
4333                 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
4334                         /* Set Test Pattern state */
4335                         link->test_pattern_enabled = true;
4336                         if (p_link_settings != NULL)
4337                                 dpcd_set_link_settings(link,
4338                                                 p_link_settings);
4339                 }
4340
4341                 switch (test_pattern) {
4342                 case DP_TEST_PATTERN_VIDEO_MODE:
4343                         pattern = PHY_TEST_PATTERN_NONE;
4344                         break;
4345                 case DP_TEST_PATTERN_D102:
4346                         pattern = PHY_TEST_PATTERN_D10_2;
4347                         break;
4348                 case DP_TEST_PATTERN_SYMBOL_ERROR:
4349                         pattern = PHY_TEST_PATTERN_SYMBOL_ERROR;
4350                         break;
4351                 case DP_TEST_PATTERN_PRBS7:
4352                         pattern = PHY_TEST_PATTERN_PRBS7;
4353                         break;
4354                 case DP_TEST_PATTERN_80BIT_CUSTOM:
4355                         pattern = PHY_TEST_PATTERN_80BIT_CUSTOM;
4356                         break;
4357                 case DP_TEST_PATTERN_CP2520_1:
4358                         pattern = PHY_TEST_PATTERN_CP2520_1;
4359                         break;
4360                 case DP_TEST_PATTERN_CP2520_2:
4361                         pattern = PHY_TEST_PATTERN_CP2520_2;
4362                         break;
4363                 case DP_TEST_PATTERN_CP2520_3:
4364                         pattern = PHY_TEST_PATTERN_CP2520_3;
4365                         break;
4366                 default:
4367                         return false;
4368                 }
4369
4370                 if (test_pattern == DP_TEST_PATTERN_VIDEO_MODE
4371                 /*TODO:&& !pPathMode->pDisplayPath->IsTargetPoweredOn()*/)
4372                         return false;
4373
4374                 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
4375                         /* tell receiver that we are sending qualification
4376                          * pattern DP 1.2 or later - DP receiver's link quality
4377                          * pattern is set using DPCD LINK_QUAL_LANEx_SET
4378                          * register (0x10B~0x10E)\
4379                          */
4380                         for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++)
4381                                 link_qual_pattern[lane] =
4382                                                 (unsigned char)(pattern);
4383
4384                         core_link_write_dpcd(link,
4385                                         DP_LINK_QUAL_LANE0_SET,
4386                                         link_qual_pattern,
4387                                         sizeof(link_qual_pattern));
4388                 } else if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_10 ||
4389                            link->dpcd_caps.dpcd_rev.raw == 0) {
4390                         /* tell receiver that we are sending qualification
4391                          * pattern DP 1.1a or earlier - DP receiver's link
4392                          * quality pattern is set using
4393                          * DPCD TRAINING_PATTERN_SET -> LINK_QUAL_PATTERN_SET
4394                          * register (0x102). We will use v_1.3 when we are
4395                          * setting test pattern for DP 1.1.
4396                          */
4397                         core_link_read_dpcd(link, DP_TRAINING_PATTERN_SET,
4398                                             &training_pattern.raw,
4399                                             sizeof(training_pattern));
4400                         training_pattern.v1_3.LINK_QUAL_PATTERN_SET = pattern;
4401                         core_link_write_dpcd(link, DP_TRAINING_PATTERN_SET,
4402                                              &training_pattern.raw,
4403                                              sizeof(training_pattern));
4404                 }
4405         } else {
4406                 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
4407
4408                 switch (test_pattern_color_space) {
4409                 case DP_TEST_PATTERN_COLOR_SPACE_RGB:
4410                         color_space = COLOR_SPACE_SRGB;
4411                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4412                                 color_space = COLOR_SPACE_SRGB_LIMITED;
4413                         break;
4414
4415                 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
4416                         color_space = COLOR_SPACE_YCBCR601;
4417                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4418                                 color_space = COLOR_SPACE_YCBCR601_LIMITED;
4419                         break;
4420                 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
4421                         color_space = COLOR_SPACE_YCBCR709;
4422                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4423                                 color_space = COLOR_SPACE_YCBCR709_LIMITED;
4424                         break;
4425                 default:
4426                         break;
4427                 }
4428
4429                 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable) {
4430                         if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) {
4431                                 union dmub_hw_lock_flags hw_locks = { 0 };
4432                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
4433
4434                                 hw_locks.bits.lock_dig = 1;
4435                                 inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;
4436
4437                                 dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,
4438                                                         true,
4439                                                         &hw_locks,
4440                                                         &inst_flags);
4441                         } else
4442                                 pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable(
4443                                                 pipe_ctx->stream_res.tg);
4444                 }
4445
4446                 pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
4447                 /* update MSA to requested color space */
4448                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(pipe_ctx->stream_res.stream_enc,
4449                                 &pipe_ctx->stream->timing,
4450                                 color_space,
4451                                 pipe_ctx->stream->use_vsc_sdp_for_colorimetry,
4452                                 link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
4453
4454                 if (pipe_ctx->stream->use_vsc_sdp_for_colorimetry) {
4455                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4456                                 pipe_ctx->stream->vsc_infopacket.sb[17] |= (1 << 7); // sb17 bit 7 Dynamic Range: 0 = VESA range, 1 = CTA range
4457                         else
4458                                 pipe_ctx->stream->vsc_infopacket.sb[17] &= ~(1 << 7);
4459                         resource_build_info_frame(pipe_ctx);
4460                         link->dc->hwss.update_info_frame(pipe_ctx);
4461                 }
4462
4463                 /* CRTC Patterns */
4464                 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
4465                 pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg);
4466                 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4467                                 CRTC_STATE_VACTIVE);
4468                 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4469                                 CRTC_STATE_VBLANK);
4470                 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4471                                 CRTC_STATE_VACTIVE);
4472
4473                 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable) {
4474                         if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) {
4475                                 union dmub_hw_lock_flags hw_locks = { 0 };
4476                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
4477
4478                                 hw_locks.bits.lock_dig = 1;
4479                                 inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;
4480
4481                                 dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,
4482                                                         false,
4483                                                         &hw_locks,
4484                                                         &inst_flags);
4485                         } else
4486                                 pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable(
4487                                                 pipe_ctx->stream_res.tg);
4488                 }
4489
4490                 /* Set Test Pattern state */
4491                 link->test_pattern_enabled = true;
4492         }
4493
4494         return true;
4495 }
4496
4497 void dp_enable_mst_on_sink(struct dc_link *link, bool enable)
4498 {
4499         unsigned char mstmCntl;
4500
4501         core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
4502         if (enable)
4503                 mstmCntl |= DP_MST_EN;
4504         else
4505                 mstmCntl &= (~DP_MST_EN);
4506
4507         core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
4508 }
4509
4510 void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode)
4511 {
4512         union dpcd_edp_config edp_config_set;
4513         bool panel_mode_edp = false;
4514
4515         memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
4516
4517         if (panel_mode != DP_PANEL_MODE_DEFAULT) {
4518
4519                 switch (panel_mode) {
4520                 case DP_PANEL_MODE_EDP:
4521                 case DP_PANEL_MODE_SPECIAL:
4522                         panel_mode_edp = true;
4523                         break;
4524
4525                 default:
4526                                 break;
4527                 }
4528
4529                 /*set edp panel mode in receiver*/
4530                 core_link_read_dpcd(
4531                         link,
4532                         DP_EDP_CONFIGURATION_SET,
4533                         &edp_config_set.raw,
4534                         sizeof(edp_config_set.raw));
4535
4536                 if (edp_config_set.bits.PANEL_MODE_EDP
4537                         != panel_mode_edp) {
4538                         enum dc_status result;
4539
4540                         edp_config_set.bits.PANEL_MODE_EDP =
4541                         panel_mode_edp;
4542                         result = core_link_write_dpcd(
4543                                 link,
4544                                 DP_EDP_CONFIGURATION_SET,
4545                                 &edp_config_set.raw,
4546                                 sizeof(edp_config_set.raw));
4547
4548                         ASSERT(result == DC_OK);
4549                 }
4550         }
4551         DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d "
4552                  "eDP panel mode enabled: %d \n",
4553                  link->link_index,
4554                  link->dpcd_caps.panel_mode_edp,
4555                  panel_mode_edp);
4556 }
4557
4558 enum dp_panel_mode dp_get_panel_mode(struct dc_link *link)
4559 {
4560         /* We need to explicitly check that connector
4561          * is not DP. Some Travis_VGA get reported
4562          * by video bios as DP.
4563          */
4564         if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) {
4565
4566                 switch (link->dpcd_caps.branch_dev_id) {
4567                 case DP_BRANCH_DEVICE_ID_0022B9:
4568                         /* alternate scrambler reset is required for Travis
4569                          * for the case when external chip does not
4570                          * provide sink device id, alternate scrambler
4571                          * scheme will  be overriden later by querying
4572                          * Encoder features
4573                          */
4574                         if (strncmp(
4575                                 link->dpcd_caps.branch_dev_name,
4576                                 DP_VGA_LVDS_CONVERTER_ID_2,
4577                                 sizeof(
4578                                 link->dpcd_caps.
4579                                 branch_dev_name)) == 0) {
4580                                         return DP_PANEL_MODE_SPECIAL;
4581                         }
4582                         break;
4583                 case DP_BRANCH_DEVICE_ID_00001A:
4584                         /* alternate scrambler reset is required for Travis
4585                          * for the case when external chip does not provide
4586                          * sink device id, alternate scrambler scheme will
4587                          * be overriden later by querying Encoder feature
4588                          */
4589                         if (strncmp(link->dpcd_caps.branch_dev_name,
4590                                 DP_VGA_LVDS_CONVERTER_ID_3,
4591                                 sizeof(
4592                                 link->dpcd_caps.
4593                                 branch_dev_name)) == 0) {
4594                                         return DP_PANEL_MODE_SPECIAL;
4595                         }
4596                         break;
4597                 default:
4598                         break;
4599                 }
4600         }
4601
4602         if (link->dpcd_caps.panel_mode_edp) {
4603                 return DP_PANEL_MODE_EDP;
4604         }
4605
4606         return DP_PANEL_MODE_DEFAULT;
4607 }
4608
4609 void dp_set_fec_ready(struct dc_link *link, bool ready)
4610 {
4611         /* FEC has to be "set ready" before the link training.
4612          * The policy is to always train with FEC
4613          * if the sink supports it and leave it enabled on link.
4614          * If FEC is not supported, disable it.
4615          */
4616         struct link_encoder *link_enc = link->link_enc;
4617         uint8_t fec_config = 0;
4618
4619         if (!dc_link_should_enable_fec(link))
4620                 return;
4621
4622         if (link_enc->funcs->fec_set_ready &&
4623                         link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
4624                 if (ready) {
4625                         fec_config = 1;
4626                         if (core_link_write_dpcd(link,
4627                                         DP_FEC_CONFIGURATION,
4628                                         &fec_config,
4629                                         sizeof(fec_config)) == DC_OK) {
4630                                 link_enc->funcs->fec_set_ready(link_enc, true);
4631                                 link->fec_state = dc_link_fec_ready;
4632                         } else {
4633                                 link->link_enc->funcs->fec_set_ready(link->link_enc, false);
4634                                 link->fec_state = dc_link_fec_not_ready;
4635                                 dm_error("dpcd write failed to set fec_ready");
4636                         }
4637                 } else if (link->fec_state == dc_link_fec_ready) {
4638                         fec_config = 0;
4639                         core_link_write_dpcd(link,
4640                                         DP_FEC_CONFIGURATION,
4641                                         &fec_config,
4642                                         sizeof(fec_config));
4643                         link->link_enc->funcs->fec_set_ready(
4644                                         link->link_enc, false);
4645                         link->fec_state = dc_link_fec_not_ready;
4646                 }
4647         }
4648 }
4649
4650 void dp_set_fec_enable(struct dc_link *link, bool enable)
4651 {
4652         struct link_encoder *link_enc = link->link_enc;
4653
4654         if (!dc_link_should_enable_fec(link))
4655                 return;
4656
4657         if (link_enc->funcs->fec_set_enable &&
4658                         link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
4659                 if (link->fec_state == dc_link_fec_ready && enable) {
4660                         /* Accord to DP spec, FEC enable sequence can first
4661                          * be transmitted anytime after 1000 LL codes have
4662                          * been transmitted on the link after link training
4663                          * completion. Using 1 lane RBR should have the maximum
4664                          * time for transmitting 1000 LL codes which is 6.173 us.
4665                          * So use 7 microseconds delay instead.
4666                          */
4667                         udelay(7);
4668                         link_enc->funcs->fec_set_enable(link_enc, true);
4669                         link->fec_state = dc_link_fec_enabled;
4670                 } else if (link->fec_state == dc_link_fec_enabled && !enable) {
4671                         link_enc->funcs->fec_set_enable(link_enc, false);
4672                         link->fec_state = dc_link_fec_ready;
4673                 }
4674         }
4675 }
4676
4677 void dpcd_set_source_specific_data(struct dc_link *link)
4678 {
4679         if (!link->dc->vendor_signature.is_valid) {
4680                 enum dc_status __maybe_unused result_write_min_hblank = DC_NOT_SUPPORTED;
4681                 struct dpcd_amd_signature amd_signature = {0};
4682                 struct dpcd_amd_device_id amd_device_id = {0};
4683
4684                 amd_device_id.device_id_byte1 =
4685                                 (uint8_t)(link->ctx->asic_id.chip_id);
4686                 amd_device_id.device_id_byte2 =
4687                                 (uint8_t)(link->ctx->asic_id.chip_id >> 8);
4688                 amd_device_id.dce_version =
4689                                 (uint8_t)(link->ctx->dce_version);
4690                 amd_device_id.dal_version_byte1 = 0x0; // needed? where to get?
4691                 amd_device_id.dal_version_byte2 = 0x0; // needed? where to get?
4692
4693                 core_link_read_dpcd(link, DP_SOURCE_OUI,
4694                                 (uint8_t *)(&amd_signature),
4695                                 sizeof(amd_signature));
4696
4697                 if (!((amd_signature.AMD_IEEE_TxSignature_byte1 == 0x0) &&
4698                         (amd_signature.AMD_IEEE_TxSignature_byte2 == 0x0) &&
4699                         (amd_signature.AMD_IEEE_TxSignature_byte3 == 0x1A))) {
4700
4701                         amd_signature.AMD_IEEE_TxSignature_byte1 = 0x0;
4702                         amd_signature.AMD_IEEE_TxSignature_byte2 = 0x0;
4703                         amd_signature.AMD_IEEE_TxSignature_byte3 = 0x1A;
4704
4705                         core_link_write_dpcd(link, DP_SOURCE_OUI,
4706                                 (uint8_t *)(&amd_signature),
4707                                 sizeof(amd_signature));
4708                 }
4709
4710                 core_link_write_dpcd(link, DP_SOURCE_OUI+0x03,
4711                                 (uint8_t *)(&amd_device_id),
4712                                 sizeof(amd_device_id));
4713
4714                 if (link->ctx->dce_version >= DCN_VERSION_2_0 &&
4715                         link->dc->caps.min_horizontal_blanking_period != 0) {
4716
4717                         uint8_t hblank_size = (uint8_t)link->dc->caps.min_horizontal_blanking_period;
4718
4719                         result_write_min_hblank = core_link_write_dpcd(link,
4720                                 DP_SOURCE_MINIMUM_HBLANK_SUPPORTED, (uint8_t *)(&hblank_size),
4721                                 sizeof(hblank_size));
4722                 }
4723                 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
4724                                                         WPP_BIT_FLAG_DC_DETECTION_DP_CAPS,
4725                                                         "result=%u link_index=%u enum dce_version=%d DPCD=0x%04X min_hblank=%u branch_dev_id=0x%x branch_dev_name='%c%c%c%c%c%c'",
4726                                                         result_write_min_hblank,
4727                                                         link->link_index,
4728                                                         link->ctx->dce_version,
4729                                                         DP_SOURCE_MINIMUM_HBLANK_SUPPORTED,
4730                                                         link->dc->caps.min_horizontal_blanking_period,
4731                                                         link->dpcd_caps.branch_dev_id,
4732                                                         link->dpcd_caps.branch_dev_name[0],
4733                                                         link->dpcd_caps.branch_dev_name[1],
4734                                                         link->dpcd_caps.branch_dev_name[2],
4735                                                         link->dpcd_caps.branch_dev_name[3],
4736                                                         link->dpcd_caps.branch_dev_name[4],
4737                                                         link->dpcd_caps.branch_dev_name[5]);
4738         } else {
4739                 core_link_write_dpcd(link, DP_SOURCE_OUI,
4740                                 link->dc->vendor_signature.data.raw,
4741                                 sizeof(link->dc->vendor_signature.data.raw));
4742         }
4743 }
4744
4745 bool dc_link_set_backlight_level_nits(struct dc_link *link,
4746                 bool isHDR,
4747                 uint32_t backlight_millinits,
4748                 uint32_t transition_time_in_ms)
4749 {
4750         struct dpcd_source_backlight_set dpcd_backlight_set;
4751         uint8_t backlight_control = isHDR ? 1 : 0;
4752
4753         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4754                         link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4755                 return false;
4756
4757         // OLEDs have no PWM, they can only use AUX
4758         if (link->dpcd_sink_ext_caps.bits.oled == 1)
4759                 backlight_control = 1;
4760
4761         *(uint32_t *)&dpcd_backlight_set.backlight_level_millinits = backlight_millinits;
4762         *(uint16_t *)&dpcd_backlight_set.backlight_transition_time_ms = (uint16_t)transition_time_in_ms;
4763
4764
4765         if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
4766                         (uint8_t *)(&dpcd_backlight_set),
4767                         sizeof(dpcd_backlight_set)) != DC_OK)
4768                 return false;
4769
4770         if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_CONTROL,
4771                         &backlight_control, 1) != DC_OK)
4772                 return false;
4773
4774         return true;
4775 }
4776
4777 bool dc_link_get_backlight_level_nits(struct dc_link *link,
4778                 uint32_t *backlight_millinits_avg,
4779                 uint32_t *backlight_millinits_peak)
4780 {
4781         union dpcd_source_backlight_get dpcd_backlight_get;
4782
4783         memset(&dpcd_backlight_get, 0, sizeof(union dpcd_source_backlight_get));
4784
4785         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4786                         link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4787                 return false;
4788
4789         if (core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_CURRENT_PEAK,
4790                         dpcd_backlight_get.raw,
4791                         sizeof(union dpcd_source_backlight_get)) != DC_OK)
4792                 return false;
4793
4794         *backlight_millinits_avg =
4795                 dpcd_backlight_get.bytes.backlight_millinits_avg;
4796         *backlight_millinits_peak =
4797                 dpcd_backlight_get.bytes.backlight_millinits_peak;
4798
4799         /* On non-supported panels dpcd_read usually succeeds with 0 returned */
4800         if (*backlight_millinits_avg == 0 ||
4801                         *backlight_millinits_avg > *backlight_millinits_peak)
4802                 return false;
4803
4804         return true;
4805 }
4806
4807 bool dc_link_backlight_enable_aux(struct dc_link *link, bool enable)
4808 {
4809         uint8_t backlight_enable = enable ? 1 : 0;
4810
4811         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4812                 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4813                 return false;
4814
4815         if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_ENABLE,
4816                 &backlight_enable, 1) != DC_OK)
4817                 return false;
4818
4819         return true;
4820 }
4821
4822 // we read default from 0x320 because we expect BIOS wrote it there
4823 // regular get_backlight_nit reads from panel set at 0x326
4824 bool dc_link_read_default_bl_aux(struct dc_link *link, uint32_t *backlight_millinits)
4825 {
4826         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4827                 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4828                 return false;
4829
4830         if (core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
4831                 (uint8_t *) backlight_millinits,
4832                 sizeof(uint32_t)) != DC_OK)
4833                 return false;
4834
4835         return true;
4836 }
4837
4838 bool dc_link_set_default_brightness_aux(struct dc_link *link)
4839 {
4840         uint32_t default_backlight;
4841
4842         if (link &&
4843                 (link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||
4844                 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)) {
4845                 if (!dc_link_read_default_bl_aux(link, &default_backlight))
4846                         default_backlight = 150000;
4847                 // if < 5 nits or > 5000, it might be wrong readback
4848                 if (default_backlight < 5000 || default_backlight > 5000000)
4849                         default_backlight = 150000; //
4850
4851                 return dc_link_set_backlight_level_nits(link, true,
4852                                 default_backlight, 0);
4853         }
4854         return false;
4855 }
4856
4857 bool is_edp_ilr_optimization_required(struct dc_link *link, struct dc_crtc_timing *crtc_timing)
4858 {
4859         struct dc_link_settings link_setting;
4860         uint8_t link_bw_set;
4861         uint8_t link_rate_set;
4862         uint32_t req_bw;
4863         union lane_count_set lane_count_set = { {0} };
4864
4865         ASSERT(link || crtc_timing); // invalid input
4866
4867         if (link->dpcd_caps.edp_supported_link_rates_count == 0 ||
4868                         !link->dc->debug.optimize_edp_link_rate)
4869                 return false;
4870
4871
4872         // Read DPCD 00100h to find if standard link rates are set
4873         core_link_read_dpcd(link, DP_LINK_BW_SET,
4874                                 &link_bw_set, sizeof(link_bw_set));
4875
4876         if (link_bw_set) {
4877                 DC_LOG_EVENT_LINK_TRAINING("eDP ILR: Optimization required, VBIOS used link_bw_set\n");
4878                 return true;
4879         }
4880
4881         // Read DPCD 00115h to find the edp link rate set used
4882         core_link_read_dpcd(link, DP_LINK_RATE_SET,
4883                             &link_rate_set, sizeof(link_rate_set));
4884
4885         // Read DPCD 00101h to find out the number of lanes currently set
4886         core_link_read_dpcd(link, DP_LANE_COUNT_SET,
4887                                 &lane_count_set.raw, sizeof(lane_count_set));
4888
4889         req_bw = dc_bandwidth_in_kbps_from_timing(crtc_timing);
4890
4891         decide_edp_link_settings(link, &link_setting, req_bw);
4892
4893         if (link->dpcd_caps.edp_supported_link_rates[link_rate_set] != link_setting.link_rate ||
4894                         lane_count_set.bits.LANE_COUNT_SET != link_setting.lane_count) {
4895                 DC_LOG_EVENT_LINK_TRAINING("eDP ILR: Optimization required, VBIOS link_rate_set not optimal\n");
4896                 return true;
4897         }
4898
4899         DC_LOG_EVENT_LINK_TRAINING("eDP ILR: No optimization required, VBIOS set optimal link_rate_set\n");
4900         return false;
4901 }
4902
4903 enum dp_link_encoding dp_get_link_encoding_format(const struct dc_link_settings *link_settings)
4904 {
4905         if ((link_settings->link_rate >= LINK_RATE_LOW) &&
4906                         (link_settings->link_rate <= LINK_RATE_HIGH3))
4907                 return DP_8b_10b_ENCODING;
4908         return DP_UNKNOWN_ENCODING;
4909 }
4910