drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  */
  24 #include "dm_services.h"
  25 #include "dc.h"
  26 #include "dc_link_dp.h"
  27 #include "dm_helpers.h"
  28 #include "opp.h"
  29 #include "dsc.h"
  30 #include "resource.h"
  31
  32 #include "inc/core_types.h"
  33 #include "link_hwss.h"
  34 #include "dc_link_ddc.h"
  35 #include "core_status.h"
  36 #include "dpcd_defs.h"
  37 #include "dc_dmub_srv.h"
  38 #include "dce/dmub_hw_lock_mgr.h"
  39 #include "inc/link_enc_cfg.h"
  40
  41 /*Travis*/
  42 static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
  43 /*Nutmeg*/
  44 static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
  45
  46 #define DC_LOGGER \
  47         link->ctx->logger
  48 #define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
  49
  50 #include "link_dpcd.h"
  51
  52         /* maximum pre emphasis level allowed for each voltage swing level*/
  53         static const enum dc_pre_emphasis
  54         voltage_swing_to_pre_emphasis[] = { PRE_EMPHASIS_LEVEL3,
  55                                             PRE_EMPHASIS_LEVEL2,
  56                                             PRE_EMPHASIS_LEVEL1,
  57                                             PRE_EMPHASIS_DISABLED };
  58
  59 enum {
  60         POST_LT_ADJ_REQ_LIMIT = 6,
  61         POST_LT_ADJ_REQ_TIMEOUT = 200
  62 };
  63
  64 static bool decide_fallback_link_setting(
  65                 struct dc_link_settings initial_link_settings,
  66                 struct dc_link_settings *current_link_setting,
  67                 enum link_training_result training_result);
  68 static struct dc_link_settings get_common_supported_link_settings(
  69                 struct dc_link_settings link_setting_a,
  70                 struct dc_link_settings link_setting_b);
  71
  72 static uint32_t get_cr_training_aux_rd_interval(struct dc_link *link,
  73                 const struct dc_link_settings *link_settings)
  74 {
  75         union training_aux_rd_interval training_rd_interval;
  76         uint32_t wait_in_micro_secs = 100;
  77
  78         memset(&training_rd_interval, 0, sizeof(training_rd_interval));
  79         core_link_read_dpcd(
  80                         link,
  81                         DP_TRAINING_AUX_RD_INTERVAL,
  82                         (uint8_t *)&training_rd_interval,
  83                         sizeof(training_rd_interval));
  84         if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
  85                 wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
  86         return wait_in_micro_secs;
  87 }
  88
  89 static uint32_t get_eq_training_aux_rd_interval(
  90         struct dc_link *link,
  91         const struct dc_link_settings *link_settings)
  92 {
  93         union training_aux_rd_interval training_rd_interval;
  94         uint32_t wait_in_micro_secs = 400;
  95
  96         memset(&training_rd_interval, 0, sizeof(training_rd_interval));
  97         /* overwrite the delay if rev > 1.1*/
  98         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
  99                 /* DP 1.2 or later - retrieve delay through
 100                  * "DPCD_ADDR_TRAINING_AUX_RD_INTERVAL" register */
 101                 core_link_read_dpcd(
 102                         link,
 103                         DP_TRAINING_AUX_RD_INTERVAL,
 104                         (uint8_t *)&training_rd_interval,
 105                         sizeof(training_rd_interval));
 106
 107                 if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
 108                         wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
 109         }
 110
 111         return wait_in_micro_secs;
 112 }
 113
 114 void dp_wait_for_training_aux_rd_interval(
 115         struct dc_link *link,
 116         uint32_t wait_in_micro_secs)
 117 {
 118         udelay(wait_in_micro_secs);
 119
 120         DC_LOG_HW_LINK_TRAINING("%s:\n wait = %d\n",
 121                 __func__,
 122                 wait_in_micro_secs);
 123 }
 124
 125 enum dpcd_training_patterns
 126         dc_dp_training_pattern_to_dpcd_training_pattern(
 127         struct dc_link *link,
 128         enum dc_dp_training_pattern pattern)
 129 {
 130         enum dpcd_training_patterns dpcd_tr_pattern =
 131         DPCD_TRAINING_PATTERN_VIDEOIDLE;
 132
 133         switch (pattern) {
 134         case DP_TRAINING_PATTERN_SEQUENCE_1:
 135                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1;
 136                 break;
 137         case DP_TRAINING_PATTERN_SEQUENCE_2:
 138                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2;
 139                 break;
 140         case DP_TRAINING_PATTERN_SEQUENCE_3:
 141                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
 142                 break;
 143         case DP_TRAINING_PATTERN_SEQUENCE_4:
 144                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4;
 145                 break;
 146         case DP_TRAINING_PATTERN_VIDEOIDLE:
 147                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_VIDEOIDLE;
 148                 break;
 149         default:
 150                 ASSERT(0);
 151                 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
 152                         __func__, pattern);
 153                 break;
 154         }
 155
 156         return dpcd_tr_pattern;
 157 }
 158
 159 static void dpcd_set_training_pattern(
 160         struct dc_link *link,
 161         enum dc_dp_training_pattern training_pattern)
 162 {
 163         union dpcd_training_pattern dpcd_pattern = { {0} };
 164
 165         dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
 166                         dc_dp_training_pattern_to_dpcd_training_pattern(
 167                                         link, training_pattern);
 168
 169         core_link_write_dpcd(
 170                 link,
 171                 DP_TRAINING_PATTERN_SET,
 172                 &dpcd_pattern.raw,
 173                 1);
 174
 175         DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
 176                 __func__,
 177                 DP_TRAINING_PATTERN_SET,
 178                 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
 179 }
 180
 181 static enum dc_dp_training_pattern decide_cr_training_pattern(
 182                 const struct dc_link_settings *link_settings)
 183 {
 184         return DP_TRAINING_PATTERN_SEQUENCE_1;
 185 }
 186
 187 static enum dc_dp_training_pattern decide_eq_training_pattern(struct dc_link *link,
 188                 const struct dc_link_settings *link_settings)
 189 {
 190         struct link_encoder *link_enc;
 191         enum dc_dp_training_pattern highest_tp = DP_TRAINING_PATTERN_SEQUENCE_2;
 192         struct encoder_feature_support *features;
 193         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
 194
 195         /* Access link encoder capability based on whether it is statically
 196          * or dynamically assigned to a link.
 197          */
 198         if (link->is_dig_mapping_flexible &&
 199                         link->dc->res_pool->funcs->link_encs_assign)
 200                 link_enc = link_enc_cfg_get_link_enc_used_by_link(link->dc->current_state, link);
 201         else
 202                 link_enc = link->link_enc;
 203         ASSERT(link_enc);
 204         features = &link_enc->features;
 205
 206         if (features->flags.bits.IS_TPS3_CAPABLE)
 207                 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_3;
 208
 209         if (features->flags.bits.IS_TPS4_CAPABLE)
 210                 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_4;
 211
 212         if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED &&
 213                 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_4)
 214                 return DP_TRAINING_PATTERN_SEQUENCE_4;
 215
 216         if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED &&
 217                 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_3)
 218                 return DP_TRAINING_PATTERN_SEQUENCE_3;
 219
 220         return DP_TRAINING_PATTERN_SEQUENCE_2;
 221 }
 222
 223 enum dc_status dpcd_set_link_settings(
 224         struct dc_link *link,
 225         const struct link_training_settings *lt_settings)
 226 {
 227         uint8_t rate;
 228         enum dc_status status;
 229
 230         union down_spread_ctrl downspread = { {0} };
 231         union lane_count_set lane_count_set = { {0} };
 232
 233         downspread.raw = (uint8_t)
 234         (lt_settings->link_settings.link_spread);
 235
 236         lane_count_set.bits.LANE_COUNT_SET =
 237         lt_settings->link_settings.lane_count;
 238
 239         lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
 240         lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
 241
 242
 243         if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
 244                         lt_settings->pattern_for_eq < DP_TRAINING_PATTERN_SEQUENCE_4) {
 245                 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
 246                                 link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
 247         }
 248
 249         status = core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
 250                 &downspread.raw, sizeof(downspread));
 251
 252         status = core_link_write_dpcd(link, DP_LANE_COUNT_SET,
 253                 &lane_count_set.raw, 1);
 254
 255         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
 256                         lt_settings->link_settings.use_link_rate_set == true) {
 257                 rate = 0;
 258                 /* WA for some MUX chips that will power down with eDP and lose supported
 259                  * link rate set for eDP 1.4. Source reads DPCD 0x010 again to ensure
 260                  * MUX chip gets link rate set back before link training.
 261                  */
 262                 if (link->connector_signal == SIGNAL_TYPE_EDP) {
 263                         uint8_t supported_link_rates[16];
 264
 265                         core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
 266                                         supported_link_rates, sizeof(supported_link_rates));
 267                 }
 268                 status = core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
 269                 status = core_link_write_dpcd(link, DP_LINK_RATE_SET,
 270                                 &lt_settings->link_settings.link_rate_set, 1);
 271         } else {
 272                 rate = (uint8_t) (lt_settings->link_settings.link_rate);
 273                 status = core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
 274         }
 275
 276         if (rate) {
 277                 DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
 278                         __func__,
 279                         DP_LINK_BW_SET,
 280                         lt_settings->link_settings.link_rate,
 281                         DP_LANE_COUNT_SET,
 282                         lt_settings->link_settings.lane_count,
 283                         lt_settings->enhanced_framing,
 284                         DP_DOWNSPREAD_CTRL,
 285                         lt_settings->link_settings.link_spread);
 286         } else {
 287                 DC_LOG_HW_LINK_TRAINING("%s\n %x rate set = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
 288                         __func__,
 289                         DP_LINK_RATE_SET,
 290                         lt_settings->link_settings.link_rate_set,
 291                         DP_LANE_COUNT_SET,
 292                         lt_settings->link_settings.lane_count,
 293                         lt_settings->enhanced_framing,
 294                         DP_DOWNSPREAD_CTRL,
 295                         lt_settings->link_settings.link_spread);
 296         }
 297
 298         return status;
 299 }
 300
 301 uint8_t dc_dp_initialize_scrambling_data_symbols(
 302         struct dc_link *link,
 303         enum dc_dp_training_pattern pattern)
 304 {
 305         uint8_t disable_scrabled_data_symbols = 0;
 306
 307         switch (pattern) {
 308         case DP_TRAINING_PATTERN_SEQUENCE_1:
 309         case DP_TRAINING_PATTERN_SEQUENCE_2:
 310         case DP_TRAINING_PATTERN_SEQUENCE_3:
 311                 disable_scrabled_data_symbols = 1;
 312                 break;
 313         case DP_TRAINING_PATTERN_SEQUENCE_4:
 314                 disable_scrabled_data_symbols = 0;
 315                 break;
 316         default:
 317                 ASSERT(0);
 318                 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
 319                         __func__, pattern);
 320                 break;
 321         }
 322         return disable_scrabled_data_symbols;
 323 }
 324
 325 static inline bool is_repeater(struct dc_link *link, uint32_t offset)
 326 {
 327         return (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && (offset != 0);
 328 }
 329
 330 static void dpcd_set_lt_pattern_and_lane_settings(
 331         struct dc_link *link,
 332         const struct link_training_settings *lt_settings,
 333         enum dc_dp_training_pattern pattern,
 334         uint32_t offset)
 335 {
 336         union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = { { {0} } };
 337
 338         uint32_t dpcd_base_lt_offset;
 339
 340         uint8_t dpcd_lt_buffer[5] = {0};
 341         union dpcd_training_pattern dpcd_pattern = { {0} };
 342         uint32_t lane;
 343         uint32_t size_in_bytes;
 344         bool edp_workaround = false; /* TODO link_prop.INTERNAL */
 345         dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET;
 346
 347         if (is_repeater(link, offset))
 348                 dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
 349                         ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 350
 351         /*****************************************************************
 352         * DpcdAddress_TrainingPatternSet
 353         *****************************************************************/
 354         dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
 355                 dc_dp_training_pattern_to_dpcd_training_pattern(link, pattern);
 356
 357         dpcd_pattern.v1_4.SCRAMBLING_DISABLE =
 358                 dc_dp_initialize_scrambling_data_symbols(link, pattern);
 359
 360         dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - DP_TRAINING_PATTERN_SET]
 361                 = dpcd_pattern.raw;
 362
 363         if (is_repeater(link, offset)) {
 364                 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n 0x%X pattern = %x\n",
 365                         __func__,
 366                         offset,
 367                         dpcd_base_lt_offset,
 368                         dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
 369         } else {
 370                 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n",
 371                         __func__,
 372                         dpcd_base_lt_offset,
 373                         dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
 374         }
 375         /*****************************************************************
 376         * DpcdAddress_Lane0Set -> DpcdAddress_Lane3Set
 377         *****************************************************************/
 378         for (lane = 0; lane <
 379                 (uint32_t)(lt_settings->link_settings.lane_count); lane++) {
 380
 381                 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
 382                 (uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING);
 383                 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
 384                 (uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS);
 385
 386                 dpcd_lane[lane].bits.MAX_SWING_REACHED =
 387                 (lt_settings->lane_settings[lane].VOLTAGE_SWING ==
 388                 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
 389                 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
 390                 (lt_settings->lane_settings[lane].PRE_EMPHASIS ==
 391                 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
 392         }
 393
 394         /* concatenate everything into one buffer*/
 395
 396         size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]);
 397
 398          // 0x00103 - 0x00102
 399         memmove(
 400                 &dpcd_lt_buffer[DP_TRAINING_LANE0_SET - DP_TRAINING_PATTERN_SET],
 401                 dpcd_lane,
 402                 size_in_bytes);
 403
 404         if (is_repeater(link, offset)) {
 405                 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
 406                                 " 0x%X VS set = %x PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 407                         __func__,
 408                         offset,
 409                         dpcd_base_lt_offset,
 410                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 411                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 412                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 413                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 414         } else {
 415                 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 416                         __func__,
 417                         dpcd_base_lt_offset,
 418                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 419                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 420                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 421                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 422         }
 423         if (edp_workaround) {
 424                 /* for eDP write in 2 parts because the 5-byte burst is
 425                 * causing issues on some eDP panels (EPR#366724)
 426                 */
 427                 core_link_write_dpcd(
 428                         link,
 429                         DP_TRAINING_PATTERN_SET,
 430                         &dpcd_pattern.raw,
 431                         sizeof(dpcd_pattern.raw));
 432
 433                 core_link_write_dpcd(
 434                         link,
 435                         DP_TRAINING_LANE0_SET,
 436                         (uint8_t *)(dpcd_lane),
 437                         size_in_bytes);
 438
 439                 } else
 440                 /* write it all in (1 + number-of-lanes)-byte burst*/
 441                         core_link_write_dpcd(
 442                                 link,
 443                                 dpcd_base_lt_offset,
 444                                 dpcd_lt_buffer,
 445                                 size_in_bytes + sizeof(dpcd_pattern.raw));
 446
 447         link->cur_lane_setting = lt_settings->lane_settings[0];
 448 }
 449
 450 bool dp_is_cr_done(enum dc_lane_count ln_count,
 451         union lane_status *dpcd_lane_status)
 452 {
 453         uint32_t lane;
 454         /*LANEx_CR_DONE bits All 1's?*/
 455         for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
 456                 if (!dpcd_lane_status[lane].bits.CR_DONE_0)
 457                         return false;
 458         }
 459         return true;
 460 }
 461
 462 bool dp_is_ch_eq_done(enum dc_lane_count ln_count,
 463                 union lane_status *dpcd_lane_status)
 464 {
 465         bool done = true;
 466         uint32_t lane;
 467         for (lane = 0; lane < (uint32_t)(ln_count); lane++)
 468                 if (!dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0)
 469                         done = false;
 470         return done;
 471 }
 472
 473 bool dp_is_symbol_locked(enum dc_lane_count ln_count,
 474                 union lane_status *dpcd_lane_status)
 475 {
 476         bool locked = true;
 477         uint32_t lane;
 478         for (lane = 0; lane < (uint32_t)(ln_count); lane++)
 479                 if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0)
 480                         locked = false;
 481         return locked;
 482 }
 483
 484 bool dp_is_interlane_aligned(union lane_align_status_updated align_status)
 485 {
 486         return align_status.bits.INTERLANE_ALIGN_DONE == 1;
 487 }
 488
 489 void dp_update_drive_settings(
 490                 struct link_training_settings *dest,
 491                 struct link_training_settings src)
 492 {
 493         uint32_t lane;
 494         for (lane = 0; lane < src.link_settings.lane_count; lane++) {
 495                 if (dest->voltage_swing == NULL)
 496                         dest->lane_settings[lane].VOLTAGE_SWING = src.lane_settings[lane].VOLTAGE_SWING;
 497                 else
 498                         dest->lane_settings[lane].VOLTAGE_SWING = *dest->voltage_swing;
 499
 500                 if (dest->pre_emphasis == NULL)
 501                         dest->lane_settings[lane].PRE_EMPHASIS = src.lane_settings[lane].PRE_EMPHASIS;
 502                 else
 503                         dest->lane_settings[lane].PRE_EMPHASIS = *dest->pre_emphasis;
 504
 505                 if (dest->post_cursor2 == NULL)
 506                         dest->lane_settings[lane].POST_CURSOR2 = src.lane_settings[lane].POST_CURSOR2;
 507                 else
 508                         dest->lane_settings[lane].POST_CURSOR2 = *dest->post_cursor2;
 509         }
 510 }
 511
 512 static uint8_t get_nibble_at_index(const uint8_t *buf,
 513         uint32_t index)
 514 {
 515         uint8_t nibble;
 516         nibble = buf[index / 2];
 517
 518         if (index % 2)
 519                 nibble >>= 4;
 520         else
 521                 nibble &= 0x0F;
 522
 523         return nibble;
 524 }
 525
 526 static enum dc_pre_emphasis get_max_pre_emphasis_for_voltage_swing(
 527         enum dc_voltage_swing voltage)
 528 {
 529         enum dc_pre_emphasis pre_emphasis;
 530         pre_emphasis = PRE_EMPHASIS_MAX_LEVEL;
 531
 532         if (voltage <= VOLTAGE_SWING_MAX_LEVEL)
 533                 pre_emphasis = voltage_swing_to_pre_emphasis[voltage];
 534
 535         return pre_emphasis;
 536
 537 }
 538
 539 static void find_max_drive_settings(
 540         const struct link_training_settings *link_training_setting,
 541         struct link_training_settings *max_lt_setting)
 542 {
 543         uint32_t lane;
 544         struct dc_lane_settings max_requested;
 545
 546         max_requested.VOLTAGE_SWING =
 547                 link_training_setting->
 548                 lane_settings[0].VOLTAGE_SWING;
 549         max_requested.PRE_EMPHASIS =
 550                 link_training_setting->
 551                 lane_settings[0].PRE_EMPHASIS;
 552         /*max_requested.postCursor2 =
 553          * link_training_setting->laneSettings[0].postCursor2;*/
 554
 555         /* Determine what the maximum of the requested settings are*/
 556         for (lane = 1; lane < link_training_setting->link_settings.lane_count;
 557                         lane++) {
 558                 if (link_training_setting->lane_settings[lane].VOLTAGE_SWING >
 559                         max_requested.VOLTAGE_SWING)
 560
 561                         max_requested.VOLTAGE_SWING =
 562                         link_training_setting->
 563                         lane_settings[lane].VOLTAGE_SWING;
 564
 565                 if (link_training_setting->lane_settings[lane].PRE_EMPHASIS >
 566                                 max_requested.PRE_EMPHASIS)
 567                         max_requested.PRE_EMPHASIS =
 568                         link_training_setting->
 569                         lane_settings[lane].PRE_EMPHASIS;
 570
 571                 /*
 572                 if (link_training_setting->laneSettings[lane].postCursor2 >
 573                  max_requested.postCursor2)
 574                 {
 575                 max_requested.postCursor2 =
 576                 link_training_setting->laneSettings[lane].postCursor2;
 577                 }
 578                 */
 579         }
 580
 581         /* make sure the requested settings are
 582          * not higher than maximum settings*/
 583         if (max_requested.VOLTAGE_SWING > VOLTAGE_SWING_MAX_LEVEL)
 584                 max_requested.VOLTAGE_SWING = VOLTAGE_SWING_MAX_LEVEL;
 585
 586         if (max_requested.PRE_EMPHASIS > PRE_EMPHASIS_MAX_LEVEL)
 587                 max_requested.PRE_EMPHASIS = PRE_EMPHASIS_MAX_LEVEL;
 588         /*
 589         if (max_requested.postCursor2 > PostCursor2_MaxLevel)
 590         max_requested.postCursor2 = PostCursor2_MaxLevel;
 591         */
 592
 593         /* make sure the pre-emphasis matches the voltage swing*/
 594         if (max_requested.PRE_EMPHASIS >
 595                 get_max_pre_emphasis_for_voltage_swing(
 596                         max_requested.VOLTAGE_SWING))
 597                 max_requested.PRE_EMPHASIS =
 598                 get_max_pre_emphasis_for_voltage_swing(
 599                         max_requested.VOLTAGE_SWING);
 600
 601         /*
 602          * Post Cursor2 levels are completely independent from
 603          * pre-emphasis (Post Cursor1) levels. But Post Cursor2 levels
 604          * can only be applied to each allowable combination of voltage
 605          * swing and pre-emphasis levels */
 606          /* if ( max_requested.postCursor2 >
 607           *  getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing))
 608           *  max_requested.postCursor2 =
 609           *  getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing);
 610           */
 611
 612         max_lt_setting->link_settings.link_rate =
 613                 link_training_setting->link_settings.link_rate;
 614         max_lt_setting->link_settings.lane_count =
 615         link_training_setting->link_settings.lane_count;
 616         max_lt_setting->link_settings.link_spread =
 617                 link_training_setting->link_settings.link_spread;
 618
 619         for (lane = 0; lane <
 620                 link_training_setting->link_settings.lane_count;
 621                 lane++) {
 622                 max_lt_setting->lane_settings[lane].VOLTAGE_SWING =
 623                         max_requested.VOLTAGE_SWING;
 624                 max_lt_setting->lane_settings[lane].PRE_EMPHASIS =
 625                         max_requested.PRE_EMPHASIS;
 626                 /*max_lt_setting->laneSettings[lane].postCursor2 =
 627                  * max_requested.postCursor2;
 628                  */
 629         }
 630
 631 }
 632
 633 enum dc_status dp_get_lane_status_and_drive_settings(
 634         struct dc_link *link,
 635         const struct link_training_settings *link_training_setting,
 636         union lane_status *ln_status,
 637         union lane_align_status_updated *ln_status_updated,
 638         struct link_training_settings *req_settings,
 639         uint32_t offset)
 640 {
 641         unsigned int lane01_status_address = DP_LANE0_1_STATUS;
 642         uint8_t lane_adjust_offset = 4;
 643         unsigned int lane01_adjust_address;
 644         uint8_t dpcd_buf[6] = {0};
 645         union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
 646         struct link_training_settings request_settings = { {0} };
 647         uint32_t lane;
 648         enum dc_status status;
 649
 650         memset(req_settings, '\0', sizeof(struct link_training_settings));
 651
 652         if (is_repeater(link, offset)) {
 653                 lane01_status_address =
 654                                 DP_LANE0_1_STATUS_PHY_REPEATER1 +
 655                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 656                 lane_adjust_offset = 3;
 657         }
 658
 659         status = core_link_read_dpcd(
 660                 link,
 661                 lane01_status_address,
 662                 (uint8_t *)(dpcd_buf),
 663                 sizeof(dpcd_buf));
 664
 665         for (lane = 0; lane <
 666                 (uint32_t)(link_training_setting->link_settings.lane_count);
 667                 lane++) {
 668
 669                 ln_status[lane].raw =
 670                         get_nibble_at_index(&dpcd_buf[0], lane);
 671                 dpcd_lane_adjust[lane].raw =
 672                         get_nibble_at_index(&dpcd_buf[lane_adjust_offset], lane);
 673         }
 674
 675         ln_status_updated->raw = dpcd_buf[2];
 676
 677         if (is_repeater(link, offset)) {
 678                 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
 679                                 " 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
 680                         __func__,
 681                         offset,
 682                         lane01_status_address, dpcd_buf[0],
 683                         lane01_status_address + 1, dpcd_buf[1]);
 684         } else {
 685                 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
 686                         __func__,
 687                         lane01_status_address, dpcd_buf[0],
 688                         lane01_status_address + 1, dpcd_buf[1]);
 689         }
 690         lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1;
 691
 692         if (is_repeater(link, offset))
 693                 lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 +
 694                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 695
 696         if (is_repeater(link, offset)) {
 697                 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
 698                                 " 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
 699                                         __func__,
 700                                         offset,
 701                                         lane01_adjust_address,
 702                                         dpcd_buf[lane_adjust_offset],
 703                                         lane01_adjust_address + 1,
 704                                         dpcd_buf[lane_adjust_offset + 1]);
 705         } else {
 706                 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
 707                         __func__,
 708                         lane01_adjust_address,
 709                         dpcd_buf[lane_adjust_offset],
 710                         lane01_adjust_address + 1,
 711                         dpcd_buf[lane_adjust_offset + 1]);
 712         }
 713
 714         /*copy to req_settings*/
 715         request_settings.link_settings.lane_count =
 716                 link_training_setting->link_settings.lane_count;
 717         request_settings.link_settings.link_rate =
 718                 link_training_setting->link_settings.link_rate;
 719         request_settings.link_settings.link_spread =
 720                 link_training_setting->link_settings.link_spread;
 721
 722         for (lane = 0; lane <
 723                 (uint32_t)(link_training_setting->link_settings.lane_count);
 724                 lane++) {
 725
 726                 request_settings.lane_settings[lane].VOLTAGE_SWING =
 727                         (enum dc_voltage_swing)(dpcd_lane_adjust[lane].bits.
 728                                 VOLTAGE_SWING_LANE);
 729                 request_settings.lane_settings[lane].PRE_EMPHASIS =
 730                         (enum dc_pre_emphasis)(dpcd_lane_adjust[lane].bits.
 731                                 PRE_EMPHASIS_LANE);
 732         }
 733
 734         /*Note: for postcursor2, read adjusted
 735          * postcursor2 settings from*/
 736         /*DpcdAddress_AdjustRequestPostCursor2 =
 737          *0x020C (not implemented yet)*/
 738
 739         /* we find the maximum of the requested settings across all lanes*/
 740         /* and set this maximum for all lanes*/
 741         find_max_drive_settings(&request_settings, req_settings);
 742
 743         /* if post cursor 2 is needed in the future,
 744          * read DpcdAddress_AdjustRequestPostCursor2 = 0x020C
 745          */
 746
 747         return status;
 748 }
 749
 750 enum dc_status dpcd_set_lane_settings(
 751         struct dc_link *link,
 752         const struct link_training_settings *link_training_setting,
 753         uint32_t offset)
 754 {
 755         union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
 756         uint32_t lane;
 757         unsigned int lane0_set_address;
 758         enum dc_status status;
 759
 760         lane0_set_address = DP_TRAINING_LANE0_SET;
 761
 762         if (is_repeater(link, offset))
 763                 lane0_set_address = DP_TRAINING_LANE0_SET_PHY_REPEATER1 +
 764                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 765
 766         for (lane = 0; lane <
 767                 (uint32_t)(link_training_setting->
 768                 link_settings.lane_count);
 769                 lane++) {
 770                 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
 771                         (uint8_t)(link_training_setting->
 772                         lane_settings[lane].VOLTAGE_SWING);
 773                 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
 774                         (uint8_t)(link_training_setting->
 775                         lane_settings[lane].PRE_EMPHASIS);
 776                 dpcd_lane[lane].bits.MAX_SWING_REACHED =
 777                         (link_training_setting->
 778                         lane_settings[lane].VOLTAGE_SWING ==
 779                         VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
 780                 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
 781                         (link_training_setting->
 782                         lane_settings[lane].PRE_EMPHASIS ==
 783                         PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
 784         }
 785
 786         status = core_link_write_dpcd(link,
 787                 lane0_set_address,
 788                 (uint8_t *)(dpcd_lane),
 789                 link_training_setting->link_settings.lane_count);
 790
 791         /*
 792         if (LTSettings.link.rate == LinkRate_High2)
 793         {
 794                 DpcdTrainingLaneSet2 dpcd_lane2[lane_count_DPMax] = {0};
 795                 for ( uint32_t lane = 0;
 796                 lane < lane_count_DPMax; lane++)
 797                 {
 798                         dpcd_lane2[lane].bits.post_cursor2_set =
 799                         static_cast<unsigned char>(
 800                         LTSettings.laneSettings[lane].postCursor2);
 801                         dpcd_lane2[lane].bits.max_post_cursor2_reached = 0;
 802                 }
 803                 m_pDpcdAccessSrv->WriteDpcdData(
 804                 DpcdAddress_Lane0Set2,
 805                 reinterpret_cast<unsigned char*>(dpcd_lane2),
 806                 LTSettings.link.lanes);
 807         }
 808         */
 809
 810         if (is_repeater(link, offset)) {
 811                 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n"
 812                                 " 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 813                         __func__,
 814                         offset,
 815                         lane0_set_address,
 816                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 817                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 818                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 819                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 820
 821         } else {
 822                 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 823                         __func__,
 824                         lane0_set_address,
 825                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 826                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 827                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 828                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 829         }
 830         link->cur_lane_setting = link_training_setting->lane_settings[0];
 831
 832         return status;
 833 }
 834
 835 bool dp_is_max_vs_reached(
 836         const struct link_training_settings *lt_settings)
 837 {
 838         uint32_t lane;
 839         for (lane = 0; lane <
 840                 (uint32_t)(lt_settings->link_settings.lane_count);
 841                 lane++) {
 842                 if (lt_settings->lane_settings[lane].VOLTAGE_SWING
 843                         == VOLTAGE_SWING_MAX_LEVEL)
 844                         return true;
 845         }
 846         return false;
 847
 848 }
 849
 850 static bool perform_post_lt_adj_req_sequence(
 851         struct dc_link *link,
 852         struct link_training_settings *lt_settings)
 853 {
 854         enum dc_lane_count lane_count =
 855         lt_settings->link_settings.lane_count;
 856
 857         uint32_t adj_req_count;
 858         uint32_t adj_req_timer;
 859         bool req_drv_setting_changed;
 860         uint32_t lane;
 861
 862         req_drv_setting_changed = false;
 863         for (adj_req_count = 0; adj_req_count < POST_LT_ADJ_REQ_LIMIT;
 864         adj_req_count++) {
 865
 866                 req_drv_setting_changed = false;
 867
 868                 for (adj_req_timer = 0;
 869                         adj_req_timer < POST_LT_ADJ_REQ_TIMEOUT;
 870                         adj_req_timer++) {
 871
 872                         struct link_training_settings req_settings;
 873                         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
 874                         union lane_align_status_updated
 875                                 dpcd_lane_status_updated;
 876
 877                         dp_get_lane_status_and_drive_settings(
 878                                 link,
 879                                 lt_settings,
 880                                 dpcd_lane_status,
 881                                 &dpcd_lane_status_updated,
 882                                 &req_settings,
 883                                 DPRX);
 884
 885                         if (dpcd_lane_status_updated.bits.
 886                                         POST_LT_ADJ_REQ_IN_PROGRESS == 0)
 887                                 return true;
 888
 889                         if (!dp_is_cr_done(lane_count, dpcd_lane_status))
 890                                 return false;
 891
 892                         if (!dp_is_ch_eq_done(lane_count, dpcd_lane_status) ||
 893                                         !dp_is_symbol_locked(lane_count, dpcd_lane_status) ||
 894                                         !dp_is_interlane_aligned(dpcd_lane_status_updated))
 895                                 return false;
 896
 897                         for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
 898
 899                                 if (lt_settings->
 900                                 lane_settings[lane].VOLTAGE_SWING !=
 901                                 req_settings.lane_settings[lane].
 902                                 VOLTAGE_SWING ||
 903                                 lt_settings->lane_settings[lane].PRE_EMPHASIS !=
 904                                 req_settings.lane_settings[lane].PRE_EMPHASIS) {
 905
 906                                         req_drv_setting_changed = true;
 907                                         break;
 908                                 }
 909                         }
 910
 911                         if (req_drv_setting_changed) {
 912                                 dp_update_drive_settings(
 913                                         lt_settings, req_settings);
 914
 915                                 dc_link_dp_set_drive_settings(link,
 916                                                 lt_settings);
 917                                 break;
 918                         }
 919
 920                         msleep(1);
 921                 }
 922
 923                 if (!req_drv_setting_changed) {
 924                         DC_LOG_WARNING("%s: Post Link Training Adjust Request Timed out\n",
 925                                 __func__);
 926
 927                         ASSERT(0);
 928                         return true;
 929                 }
 930         }
 931         DC_LOG_WARNING("%s: Post Link Training Adjust Request limit reached\n",
 932                 __func__);
 933
 934         ASSERT(0);
 935         return true;
 936
 937 }
 938
 939 /* Only used for channel equalization */
 940 uint32_t dp_translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval)
 941 {
 942         unsigned int aux_rd_interval_us = 400;
 943
 944         switch (dpcd_aux_read_interval) {
 945         case 0x01:
 946                 aux_rd_interval_us = 4000;
 947                 break;
 948         case 0x02:
 949                 aux_rd_interval_us = 8000;
 950                 break;
 951         case 0x03:
 952                 aux_rd_interval_us = 12000;
 953                 break;
 954         case 0x04:
 955                 aux_rd_interval_us = 16000;
 956                 break;
 957         default:
 958                 break;
 959         }
 960
 961         return aux_rd_interval_us;
 962 }
 963
 964 enum link_training_result dp_get_cr_failure(enum dc_lane_count ln_count,
 965                                         union lane_status *dpcd_lane_status)
 966 {
 967         enum link_training_result result = LINK_TRAINING_SUCCESS;
 968
 969         if (ln_count >= LANE_COUNT_ONE && !dpcd_lane_status[0].bits.CR_DONE_0)
 970                 result = LINK_TRAINING_CR_FAIL_LANE0;
 971         else if (ln_count >= LANE_COUNT_TWO && !dpcd_lane_status[1].bits.CR_DONE_0)
 972                 result = LINK_TRAINING_CR_FAIL_LANE1;
 973         else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[2].bits.CR_DONE_0)
 974                 result = LINK_TRAINING_CR_FAIL_LANE23;
 975         else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[3].bits.CR_DONE_0)
 976                 result = LINK_TRAINING_CR_FAIL_LANE23;
 977         return result;
 978 }
 979
 980 static enum link_training_result perform_channel_equalization_sequence(
 981         struct dc_link *link,
 982         struct link_training_settings *lt_settings,
 983         uint32_t offset)
 984 {
 985         struct link_training_settings req_settings;
 986         enum dc_dp_training_pattern tr_pattern;
 987         uint32_t retries_ch_eq;
 988         uint32_t wait_time_microsec;
 989         enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
 990         union lane_align_status_updated dpcd_lane_status_updated = { {0} };
 991         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
 992
 993         /* Note: also check that TPS4 is a supported feature*/
 994
 995         tr_pattern = lt_settings->pattern_for_eq;
 996
 997         if (is_repeater(link, offset))
 998                 tr_pattern = DP_TRAINING_PATTERN_SEQUENCE_4;
 999
1000         dp_set_hw_training_pattern(link, tr_pattern, offset);
1001
1002         for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT;
1003                 retries_ch_eq++) {
1004
1005                 dp_set_hw_lane_settings(link, lt_settings, offset);
1006
1007                 /* 2. update DPCD*/
1008                 if (!retries_ch_eq)
1009                         /* EPR #361076 - write as a 5-byte burst,
1010                          * but only for the 1-st iteration
1011                          */
1012
1013                         dpcd_set_lt_pattern_and_lane_settings(
1014                                 link,
1015                                 lt_settings,
1016                                 tr_pattern, offset);
1017                 else
1018                         dpcd_set_lane_settings(link, lt_settings, offset);
1019
1020                 /* 3. wait for receiver to lock-on*/
1021                 wait_time_microsec = lt_settings->eq_pattern_time;
1022
1023                 if (is_repeater(link, offset))
1024                         wait_time_microsec =
1025                                         dp_translate_training_aux_read_interval(
1026                                                 link->dpcd_caps.lttpr_caps.aux_rd_interval[offset - 1]);
1027
1028                 dp_wait_for_training_aux_rd_interval(
1029                                 link,
1030                                 wait_time_microsec);
1031
1032                 /* 4. Read lane status and requested
1033                  * drive settings as set by the sink*/
1034
1035                 dp_get_lane_status_and_drive_settings(
1036                         link,
1037                         lt_settings,
1038                         dpcd_lane_status,
1039                         &dpcd_lane_status_updated,
1040                         &req_settings,
1041                         offset);
1042
1043                 /* 5. check CR done*/
1044                 if (!dp_is_cr_done(lane_count, dpcd_lane_status))
1045                         return LINK_TRAINING_EQ_FAIL_CR;
1046
1047                 /* 6. check CHEQ done*/
1048                 if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) &&
1049                                 dp_is_symbol_locked(lane_count, dpcd_lane_status) &&
1050                                 dp_is_interlane_aligned(dpcd_lane_status_updated))
1051                         return LINK_TRAINING_SUCCESS;
1052
1053                 /* 7. update VS/PE/PC2 in lt_settings*/
1054                 dp_update_drive_settings(lt_settings, req_settings);
1055         }
1056
1057         return LINK_TRAINING_EQ_FAIL_EQ;
1058
1059 }
1060
1061 static void start_clock_recovery_pattern_early(struct dc_link *link,
1062                 struct link_training_settings *lt_settings,
1063                 uint32_t offset)
1064 {
1065         DC_LOG_HW_LINK_TRAINING("%s\n GPU sends TPS1. Wait 400us.\n",
1066                         __func__);
1067         dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset);
1068         dp_set_hw_lane_settings(link, lt_settings, offset);
1069         udelay(400);
1070 }
1071
1072 static enum link_training_result perform_clock_recovery_sequence(
1073         struct dc_link *link,
1074         struct link_training_settings *lt_settings,
1075         uint32_t offset)
1076 {
1077         uint32_t retries_cr;
1078         uint32_t retry_count;
1079         uint32_t wait_time_microsec;
1080         struct link_training_settings req_settings;
1081         enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
1082         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
1083         union lane_align_status_updated dpcd_lane_status_updated;
1084
1085         retries_cr = 0;
1086         retry_count = 0;
1087
1088         if (!link->ctx->dc->work_arounds.lt_early_cr_pattern)
1089                 dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset);
1090
1091         /* najeeb - The synaptics MST hub can put the LT in
1092         * infinite loop by switching the VS
1093         */
1094         /* between level 0 and level 1 continuously, here
1095         * we try for CR lock for LinkTrainingMaxCRRetry count*/
1096         while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
1097                 (retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
1098
1099                 memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
1100                 memset(&dpcd_lane_status_updated, '\0',
1101                 sizeof(dpcd_lane_status_updated));
1102
1103                 /* 1. call HWSS to set lane settings*/
1104                 dp_set_hw_lane_settings(
1105                                 link,
1106                                 lt_settings,
1107                                 offset);
1108
1109                 /* 2. update DPCD of the receiver*/
1110                 if (!retry_count)
1111                         /* EPR #361076 - write as a 5-byte burst,
1112                          * but only for the 1-st iteration.*/
1113                         dpcd_set_lt_pattern_and_lane_settings(
1114                                         link,
1115                                         lt_settings,
1116                                         lt_settings->pattern_for_cr,
1117                                         offset);
1118                 else
1119                         dpcd_set_lane_settings(
1120                                         link,
1121                                         lt_settings,
1122                                         offset);
1123
1124                 /* 3. wait receiver to lock-on*/
1125                 wait_time_microsec = lt_settings->cr_pattern_time;
1126
1127                 if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
1128                         wait_time_microsec = TRAINING_AUX_RD_INTERVAL;
1129
1130                 dp_wait_for_training_aux_rd_interval(
1131                                 link,
1132                                 wait_time_microsec);
1133
1134                 /* 4. Read lane status and requested drive
1135                 * settings as set by the sink
1136                 */
1137                 dp_get_lane_status_and_drive_settings(
1138                                 link,
1139                                 lt_settings,
1140                                 dpcd_lane_status,
1141                                 &dpcd_lane_status_updated,
1142                                 &req_settings,
1143                                 offset);
1144
1145                 /* 5. check CR done*/
1146                 if (dp_is_cr_done(lane_count, dpcd_lane_status))
1147                         return LINK_TRAINING_SUCCESS;
1148
1149                 /* 6. max VS reached*/
1150                 if (dp_is_max_vs_reached(lt_settings))
1151                         break;
1152
1153                 /* 7. same lane settings*/
1154                 /* Note: settings are the same for all lanes,
1155                  * so comparing first lane is sufficient*/
1156                 if ((lt_settings->lane_settings[0].VOLTAGE_SWING ==
1157                         req_settings.lane_settings[0].VOLTAGE_SWING)
1158                         && (lt_settings->lane_settings[0].PRE_EMPHASIS ==
1159                                 req_settings.lane_settings[0].PRE_EMPHASIS))
1160                         retries_cr++;
1161                 else
1162                         retries_cr = 0;
1163
1164                 /* 8. update VS/PE/PC2 in lt_settings*/
1165                 dp_update_drive_settings(lt_settings, req_settings);
1166
1167                 retry_count++;
1168         }
1169
1170         if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
1171                 ASSERT(0);
1172                 DC_LOG_ERROR("%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue",
1173                         __func__,
1174                         LINK_TRAINING_MAX_CR_RETRY);
1175
1176         }
1177
1178         return dp_get_cr_failure(lane_count, dpcd_lane_status);
1179 }
1180
1181 static inline enum link_training_result dp_transition_to_video_idle(
1182         struct dc_link *link,
1183         struct link_training_settings *lt_settings,
1184         enum link_training_result status)
1185 {
1186         union lane_count_set lane_count_set = { {0} };
1187
1188         /* 4. mainlink output idle pattern*/
1189         dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1190
1191         /*
1192          * 5. post training adjust if required
1193          * If the upstream DPTX and downstream DPRX both support TPS4,
1194          * TPS4 must be used instead of POST_LT_ADJ_REQ.
1195          */
1196         if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||
1197                         lt_settings->pattern_for_eq == DP_TRAINING_PATTERN_SEQUENCE_4) {
1198                 /* delay 5ms after Main Link output idle pattern and then check
1199                  * DPCD 0202h.
1200                  */
1201                 if (link->connector_signal != SIGNAL_TYPE_EDP && status == LINK_TRAINING_SUCCESS) {
1202                         msleep(5);
1203                         status = dp_check_link_loss_status(link, lt_settings);
1204                 }
1205                 return status;
1206         }
1207
1208         if (status == LINK_TRAINING_SUCCESS &&
1209                 perform_post_lt_adj_req_sequence(link, lt_settings) == false)
1210                 status = LINK_TRAINING_LQA_FAIL;
1211
1212         lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;
1213         lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
1214         lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
1215
1216         core_link_write_dpcd(
1217                 link,
1218                 DP_LANE_COUNT_SET,
1219                 &lane_count_set.raw,
1220                 sizeof(lane_count_set));
1221
1222         return status;
1223 }
1224
1225 enum link_training_result dp_check_link_loss_status(
1226         struct dc_link *link,
1227         const struct link_training_settings *link_training_setting)
1228 {
1229         enum link_training_result status = LINK_TRAINING_SUCCESS;
1230         union lane_status lane_status;
1231         uint8_t dpcd_buf[6] = {0};
1232         uint32_t lane;
1233
1234         core_link_read_dpcd(
1235                         link,
1236                         DP_SINK_COUNT,
1237                         (uint8_t *)(dpcd_buf),
1238                         sizeof(dpcd_buf));
1239
1240         /*parse lane status*/
1241         for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
1242                 /*
1243                  * check lanes status
1244                  */
1245                 lane_status.raw = get_nibble_at_index(&dpcd_buf[2], lane);
1246
1247                 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
1248                         !lane_status.bits.CR_DONE_0 ||
1249                         !lane_status.bits.SYMBOL_LOCKED_0) {
1250                         /* if one of the channel equalization, clock
1251                          * recovery or symbol lock is dropped
1252                          * consider it as (link has been
1253                          * dropped) dp sink status has changed
1254                          */
1255                         status = LINK_TRAINING_LINK_LOSS;
1256                         break;
1257                 }
1258         }
1259
1260         return status;
1261 }
1262
1263 static inline void decide_8b_10b_training_settings(
1264          struct dc_link *link,
1265         const struct dc_link_settings *link_setting,
1266         struct link_training_settings *lt_settings)
1267 {
1268         memset(lt_settings, '\0', sizeof(struct link_training_settings));
1269
1270         /* Initialize link settings */
1271         lt_settings->link_settings.use_link_rate_set = link_setting->use_link_rate_set;
1272         lt_settings->link_settings.link_rate_set = link_setting->link_rate_set;
1273         lt_settings->link_settings.link_rate = link_setting->link_rate;
1274         lt_settings->link_settings.lane_count = link_setting->lane_count;
1275         /* TODO hard coded to SS for now
1276          * lt_settings.link_settings.link_spread =
1277          * dal_display_path_is_ss_supported(
1278          * path_mode->display_path) ?
1279          * LINK_SPREAD_05_DOWNSPREAD_30KHZ :
1280          * LINK_SPREAD_DISABLED;
1281          */
1282         lt_settings->link_settings.link_spread = link->dp_ss_off ?
1283                         LINK_SPREAD_DISABLED : LINK_SPREAD_05_DOWNSPREAD_30KHZ;
1284         lt_settings->lttpr_mode = link->lttpr_mode;
1285         lt_settings->cr_pattern_time = get_cr_training_aux_rd_interval(link, link_setting);
1286         lt_settings->eq_pattern_time = get_eq_training_aux_rd_interval(link, link_setting);
1287         lt_settings->pattern_for_cr = decide_cr_training_pattern(link_setting);
1288         lt_settings->pattern_for_eq = decide_eq_training_pattern(link, link_setting);
1289         lt_settings->enhanced_framing = 1;
1290         lt_settings->should_set_fec_ready = true;
1291 }
1292
1293 void dp_decide_training_settings(
1294                 struct dc_link *link,
1295                 const struct dc_link_settings *link_settings,
1296                 struct link_training_settings *lt_settings)
1297 {
1298         if (dp_get_link_encoding_format(link_settings) == DP_8b_10b_ENCODING)
1299                 decide_8b_10b_training_settings(link, link_settings, lt_settings);
1300 }
1301
1302 static void override_training_settings(
1303                 struct dc_link *link,
1304                 const struct dc_link_training_overrides *overrides,
1305                 struct link_training_settings *lt_settings)
1306 {
1307         uint32_t lane;
1308
1309         /* Override link settings */
1310         if (link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
1311                 lt_settings->link_settings.link_rate = link->preferred_link_setting.link_rate;
1312         if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN)
1313                 lt_settings->link_settings.lane_count = link->preferred_link_setting.lane_count;
1314
1315         /* Override link spread */
1316         if (!link->dp_ss_off && overrides->downspread != NULL)
1317                 lt_settings->link_settings.link_spread = *overrides->downspread ?
1318                                 LINK_SPREAD_05_DOWNSPREAD_30KHZ
1319                                 : LINK_SPREAD_DISABLED;
1320
1321         /* Override lane settings */
1322         if (overrides->voltage_swing != NULL)
1323                 lt_settings->voltage_swing = overrides->voltage_swing;
1324         if (overrides->pre_emphasis != NULL)
1325                 lt_settings->pre_emphasis = overrides->pre_emphasis;
1326         if (overrides->post_cursor2 != NULL)
1327                 lt_settings->post_cursor2 = overrides->post_cursor2;
1328         for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
1329                 lt_settings->lane_settings[lane].VOLTAGE_SWING =
1330                         lt_settings->voltage_swing != NULL ?
1331                         *lt_settings->voltage_swing :
1332                         VOLTAGE_SWING_LEVEL0;
1333                 lt_settings->lane_settings[lane].PRE_EMPHASIS =
1334                         lt_settings->pre_emphasis != NULL ?
1335                         *lt_settings->pre_emphasis
1336                         : PRE_EMPHASIS_DISABLED;
1337                 lt_settings->lane_settings[lane].POST_CURSOR2 =
1338                         lt_settings->post_cursor2 != NULL ?
1339                         *lt_settings->post_cursor2
1340                         : POST_CURSOR2_DISABLED;
1341         }
1342
1343         /* Initialize training timings */
1344         if (overrides->cr_pattern_time != NULL)
1345                 lt_settings->cr_pattern_time = *overrides->cr_pattern_time;
1346
1347         if (overrides->eq_pattern_time != NULL)
1348                 lt_settings->eq_pattern_time = *overrides->eq_pattern_time;
1349
1350         if (overrides->pattern_for_cr != NULL)
1351                 lt_settings->pattern_for_cr = *overrides->pattern_for_cr;
1352         if (overrides->pattern_for_eq != NULL)
1353                 lt_settings->pattern_for_eq = *overrides->pattern_for_eq;
1354
1355         if (overrides->enhanced_framing != NULL)
1356                 lt_settings->enhanced_framing = *overrides->enhanced_framing;
1357
1358         if (link->preferred_training_settings.fec_enable != NULL)
1359                 lt_settings->should_set_fec_ready = *link->preferred_training_settings.fec_enable;
1360 }
1361
1362 uint8_t dp_convert_to_count(uint8_t lttpr_repeater_count)
1363 {
1364         switch (lttpr_repeater_count) {
1365         case 0x80: // 1 lttpr repeater
1366                 return 1;
1367         case 0x40: // 2 lttpr repeaters
1368                 return 2;
1369         case 0x20: // 3 lttpr repeaters
1370                 return 3;
1371         case 0x10: // 4 lttpr repeaters
1372                 return 4;
1373         case 0x08: // 5 lttpr repeaters
1374                 return 5;
1375         case 0x04: // 6 lttpr repeaters
1376                 return 6;
1377         case 0x02: // 7 lttpr repeaters
1378                 return 7;
1379         case 0x01: // 8 lttpr repeaters
1380                 return 8;
1381         default:
1382                 break;
1383         }
1384         return 0; // invalid value
1385 }
1386
1387 enum dc_status configure_lttpr_mode_transparent(struct dc_link *link)
1388 {
1389         uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
1390
1391         DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
1392         return core_link_write_dpcd(link,
1393                         DP_PHY_REPEATER_MODE,
1394                         (uint8_t *)&repeater_mode,
1395                         sizeof(repeater_mode));
1396 }
1397
1398 enum dc_status configure_lttpr_mode_non_transparent(
1399                 struct dc_link *link,
1400                 const struct link_training_settings *lt_settings)
1401 {
1402         /* aux timeout is already set to extended */
1403         /* RESET/SET lttpr mode to enable non transparent mode */
1404         uint8_t repeater_cnt;
1405         uint32_t aux_interval_address;
1406         uint8_t repeater_id;
1407         enum dc_status result = DC_ERROR_UNEXPECTED;
1408         uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
1409
1410         enum dp_link_encoding encoding = dp_get_link_encoding_format(&lt_settings->link_settings);
1411
1412         if (encoding == DP_8b_10b_ENCODING) {
1413                 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
1414                 result = core_link_write_dpcd(link,
1415                                 DP_PHY_REPEATER_MODE,
1416                                 (uint8_t *)&repeater_mode,
1417                                 sizeof(repeater_mode));
1418
1419         }
1420
1421         if (result == DC_OK) {
1422                 link->dpcd_caps.lttpr_caps.mode = repeater_mode;
1423         }
1424
1425         if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
1426
1427                 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Non Transparent Mode\n", __func__);
1428
1429                 repeater_mode = DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
1430                 result = core_link_write_dpcd(link,
1431                                 DP_PHY_REPEATER_MODE,
1432                                 (uint8_t *)&repeater_mode,
1433                                 sizeof(repeater_mode));
1434
1435                 if (result == DC_OK) {
1436                         link->dpcd_caps.lttpr_caps.mode = repeater_mode;
1437                 }
1438
1439                 if (encoding == DP_8b_10b_ENCODING) {
1440                         repeater_cnt = dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1441                         for (repeater_id = repeater_cnt; repeater_id > 0; repeater_id--) {
1442                                 aux_interval_address = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 +
1443                                                         ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (repeater_id - 1));
1444                                 core_link_read_dpcd(
1445                                         link,
1446                                         aux_interval_address,
1447                                         (uint8_t *)&link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1],
1448                                         sizeof(link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1]));
1449                                 link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1] &= 0x7F;
1450                         }
1451                 }
1452         }
1453
1454         return result;
1455 }
1456
1457 static void repeater_training_done(struct dc_link *link, uint32_t offset)
1458 {
1459         union dpcd_training_pattern dpcd_pattern = { {0} };
1460
1461         const uint32_t dpcd_base_lt_offset =
1462                         DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
1463                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
1464         /* Set training not in progress*/
1465         dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
1466
1467         core_link_write_dpcd(
1468                 link,
1469                 dpcd_base_lt_offset,
1470                 &dpcd_pattern.raw,
1471                 1);
1472
1473         DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Id: %d 0x%X pattern = %x\n",
1474                 __func__,
1475                 offset,
1476                 dpcd_base_lt_offset,
1477                 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
1478 }
1479
1480 static void print_status_message(
1481         struct dc_link *link,
1482         const struct link_training_settings *lt_settings,
1483         enum link_training_result status)
1484 {
1485         char *link_rate = "Unknown";
1486         char *lt_result = "Unknown";
1487         char *lt_spread = "Disabled";
1488
1489         switch (lt_settings->link_settings.link_rate) {
1490         case LINK_RATE_LOW:
1491                 link_rate = "RBR";
1492                 break;
1493         case LINK_RATE_RATE_2:
1494                 link_rate = "R2";
1495                 break;
1496         case LINK_RATE_RATE_3:
1497                 link_rate = "R3";
1498                 break;
1499         case LINK_RATE_HIGH:
1500                 link_rate = "HBR";
1501                 break;
1502         case LINK_RATE_RBR2:
1503                 link_rate = "RBR2";
1504                 break;
1505         case LINK_RATE_RATE_6:
1506                 link_rate = "R6";
1507                 break;
1508         case LINK_RATE_HIGH2:
1509                 link_rate = "HBR2";
1510                 break;
1511         case LINK_RATE_HIGH3:
1512                 link_rate = "HBR3";
1513                 break;
1514         default:
1515                 break;
1516         }
1517
1518         switch (status) {
1519         case LINK_TRAINING_SUCCESS:
1520                 lt_result = "pass";
1521                 break;
1522         case LINK_TRAINING_CR_FAIL_LANE0:
1523                 lt_result = "CR failed lane0";
1524                 break;
1525         case LINK_TRAINING_CR_FAIL_LANE1:
1526                 lt_result = "CR failed lane1";
1527                 break;
1528         case LINK_TRAINING_CR_FAIL_LANE23:
1529                 lt_result = "CR failed lane23";
1530                 break;
1531         case LINK_TRAINING_EQ_FAIL_CR:
1532                 lt_result = "CR failed in EQ";
1533                 break;
1534         case LINK_TRAINING_EQ_FAIL_EQ:
1535                 lt_result = "EQ failed";
1536                 break;
1537         case LINK_TRAINING_LQA_FAIL:
1538                 lt_result = "LQA failed";
1539                 break;
1540         case LINK_TRAINING_LINK_LOSS:
1541                 lt_result = "Link loss";
1542                 break;
1543         default:
1544                 break;
1545         }
1546
1547         switch (lt_settings->link_settings.link_spread) {
1548         case LINK_SPREAD_DISABLED:
1549                 lt_spread = "Disabled";
1550                 break;
1551         case LINK_SPREAD_05_DOWNSPREAD_30KHZ:
1552                 lt_spread = "0.5% 30KHz";
1553                 break;
1554         case LINK_SPREAD_05_DOWNSPREAD_33KHZ:
1555                 lt_spread = "0.5% 33KHz";
1556                 break;
1557         default:
1558                 break;
1559         }
1560
1561         /* Connectivity log: link training */
1562         CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d, DS=%s",
1563                                 link_rate,
1564                                 lt_settings->link_settings.lane_count,
1565                                 lt_result,
1566                                 lt_settings->lane_settings[0].VOLTAGE_SWING,
1567                                 lt_settings->lane_settings[0].PRE_EMPHASIS,
1568                                 lt_spread);
1569 }
1570
1571 void dc_link_dp_set_drive_settings(
1572         struct dc_link *link,
1573         struct link_training_settings *lt_settings)
1574 {
1575         /* program ASIC PHY settings*/
1576         dp_set_hw_lane_settings(link, lt_settings, DPRX);
1577
1578         /* Notify DP sink the PHY settings from source */
1579         dpcd_set_lane_settings(link, lt_settings, DPRX);
1580 }
1581
1582 bool dc_link_dp_perform_link_training_skip_aux(
1583         struct dc_link *link,
1584         const struct dc_link_settings *link_setting)
1585 {
1586         struct link_training_settings lt_settings = {0};
1587
1588         dp_decide_training_settings(
1589                         link,
1590                         link_setting,
1591                         &lt_settings);
1592         override_training_settings(
1593                         link,
1594                         &link->preferred_training_settings,
1595                         &lt_settings);
1596
1597         /* 1. Perform_clock_recovery_sequence. */
1598
1599         /* transmit training pattern for clock recovery */
1600         dp_set_hw_training_pattern(link, lt_settings.pattern_for_cr, DPRX);
1601
1602         /* call HWSS to set lane settings*/
1603         dp_set_hw_lane_settings(link, &lt_settings, DPRX);
1604
1605         /* wait receiver to lock-on*/
1606         dp_wait_for_training_aux_rd_interval(link, lt_settings.cr_pattern_time);
1607
1608         /* 2. Perform_channel_equalization_sequence. */
1609
1610         /* transmit training pattern for channel equalization. */
1611         dp_set_hw_training_pattern(link, lt_settings.pattern_for_eq, DPRX);
1612
1613         /* call HWSS to set lane settings*/
1614         dp_set_hw_lane_settings(link, &lt_settings, DPRX);
1615
1616         /* wait receiver to lock-on. */
1617         dp_wait_for_training_aux_rd_interval(link, lt_settings.eq_pattern_time);
1618
1619         /* 3. Perform_link_training_int. */
1620
1621         /* Mainlink output idle pattern. */
1622         dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1623
1624         print_status_message(link, &lt_settings, LINK_TRAINING_SUCCESS);
1625
1626         return true;
1627 }
1628
1629 enum dc_status dpcd_configure_lttpr_mode(struct dc_link *link, struct link_training_settings *lt_settings)
1630 {
1631         enum dc_status status = DC_OK;
1632
1633         if (lt_settings->lttpr_mode == LTTPR_MODE_TRANSPARENT)
1634                 status = configure_lttpr_mode_transparent(link);
1635
1636         else if (lt_settings->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
1637                 status = configure_lttpr_mode_non_transparent(link, lt_settings);
1638
1639         return status;
1640 }
1641
1642 static void dpcd_exit_training_mode(struct dc_link *link)
1643 {
1644
1645         /* clear training pattern set */
1646         dpcd_set_training_pattern(link, DP_TRAINING_PATTERN_VIDEOIDLE);
1647 }
1648
1649 enum dc_status dpcd_configure_channel_coding(struct dc_link *link,
1650                 struct link_training_settings *lt_settings)
1651 {
1652         enum dp_link_encoding encoding =
1653                         dp_get_link_encoding_format(
1654                                         &lt_settings->link_settings);
1655         enum dc_status status;
1656
1657         status = core_link_write_dpcd(
1658                         link,
1659                         DP_MAIN_LINK_CHANNEL_CODING_SET,
1660                         (uint8_t *) &encoding,
1661                         1);
1662         DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X MAIN_LINK_CHANNEL_CODING_SET = %x\n",
1663                                         __func__,
1664                                         DP_MAIN_LINK_CHANNEL_CODING_SET,
1665                                         encoding);
1666
1667         return status;
1668 }
1669
1670 static enum link_training_result dp_perform_8b_10b_link_training(
1671                 struct dc_link *link,
1672                 struct link_training_settings *lt_settings)
1673 {
1674         enum link_training_result status = LINK_TRAINING_SUCCESS;
1675
1676         uint8_t repeater_cnt;
1677         uint8_t repeater_id;
1678         uint8_t lane = 0;
1679
1680         if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
1681                 start_clock_recovery_pattern_early(link, lt_settings, DPRX);
1682
1683         /* 1. set link rate, lane count and spread. */
1684         dpcd_set_link_settings(link, lt_settings);
1685
1686         if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
1687
1688                 /* 2. perform link training (set link training done
1689                  *  to false is done as well)
1690                  */
1691                 repeater_cnt = dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1692
1693                 for (repeater_id = repeater_cnt; (repeater_id > 0 && status == LINK_TRAINING_SUCCESS);
1694                                 repeater_id--) {
1695                         status = perform_clock_recovery_sequence(link, lt_settings, repeater_id);
1696
1697                         if (status != LINK_TRAINING_SUCCESS)
1698                                 break;
1699
1700                         status = perform_channel_equalization_sequence(link,
1701                                         lt_settings,
1702                                         repeater_id);
1703
1704                         if (status != LINK_TRAINING_SUCCESS)
1705                                 break;
1706
1707                         repeater_training_done(link, repeater_id);
1708                 }
1709
1710                 for (lane = 0; lane < (uint8_t)lt_settings->link_settings.lane_count; lane++)
1711                         lt_settings->lane_settings[lane].VOLTAGE_SWING = VOLTAGE_SWING_LEVEL0;
1712         }
1713
1714         if (status == LINK_TRAINING_SUCCESS) {
1715                 status = perform_clock_recovery_sequence(link, lt_settings, DPRX);
1716         if (status == LINK_TRAINING_SUCCESS) {
1717                 status = perform_channel_equalization_sequence(link,
1718                                         lt_settings,
1719                                         DPRX);
1720                 }
1721         }
1722
1723         return status;
1724 }
1725
1726 enum link_training_result dc_link_dp_perform_link_training(
1727         struct dc_link *link,
1728         const struct dc_link_settings *link_settings,
1729         bool skip_video_pattern)
1730 {
1731         enum link_training_result status = LINK_TRAINING_SUCCESS;
1732         struct link_training_settings lt_settings = {0};
1733         enum dp_link_encoding encoding =
1734                         dp_get_link_encoding_format(link_settings);
1735
1736         /* decide training settings */
1737         dp_decide_training_settings(
1738                         link,
1739                         link_settings,
1740                         &lt_settings);
1741         override_training_settings(
1742                         link,
1743                         &link->preferred_training_settings,
1744                         &lt_settings);
1745
1746         /* reset previous training states */
1747         dpcd_exit_training_mode(link);
1748
1749         /* configure link prior to entering training mode */
1750         dpcd_configure_lttpr_mode(link, &lt_settings);
1751         dp_set_fec_ready(link, lt_settings.should_set_fec_ready);
1752         dpcd_configure_channel_coding(link, &lt_settings);
1753
1754         /* enter training mode:
1755          * Per DP specs starting from here, DPTX device shall not issue
1756          * Non-LT AUX transactions inside training mode.
1757          */
1758         if (encoding == DP_8b_10b_ENCODING)
1759                 status = dp_perform_8b_10b_link_training(link, &lt_settings);
1760         else
1761                 ASSERT(0);
1762
1763         /* exit training mode and switch to video idle */
1764         dpcd_exit_training_mode(link);
1765         if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern)
1766                 status = dp_transition_to_video_idle(link,
1767                                 &lt_settings,
1768                                 status);
1769
1770         /* dump debug data */
1771         print_status_message(link, &lt_settings, status);
1772         if (status != LINK_TRAINING_SUCCESS)
1773                 link->ctx->dc->debug_data.ltFailCount++;
1774         return status;
1775 }
1776
1777 bool perform_link_training_with_retries(
1778         const struct dc_link_settings *link_setting,
1779         bool skip_video_pattern,
1780         int attempts,
1781         struct pipe_ctx *pipe_ctx,
1782         enum signal_type signal,
1783         bool do_fallback)
1784 {
1785         int j;
1786         uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
1787         struct dc_stream_state *stream = pipe_ctx->stream;
1788         struct dc_link *link = stream->link;
1789         enum dp_panel_mode panel_mode = dp_get_panel_mode(link);
1790         struct link_encoder *link_enc;
1791         enum link_training_result status = LINK_TRAINING_CR_FAIL_LANE0;
1792         struct dc_link_settings current_setting = *link_setting;
1793
1794         /* Dynamically assigned link encoders associated with stream rather than
1795          * link.
1796          */
1797         if (link->dc->res_pool->funcs->link_encs_assign)
1798                 link_enc = stream->link_enc;
1799         else
1800                 link_enc = link->link_enc;
1801
1802         /* We need to do this before the link training to ensure the idle pattern in SST
1803          * mode will be sent right after the link training
1804          */
1805         link_enc->funcs->connect_dig_be_to_fe(link_enc,
1806                                                         pipe_ctx->stream_res.stream_enc->id, true);
1807
1808         for (j = 0; j < attempts; ++j) {
1809
1810                 DC_LOG_HW_LINK_TRAINING("%s: Beginning link training attempt %u of %d\n",
1811                         __func__, (unsigned int)j + 1, attempts);
1812
1813                 dp_enable_link_phy(
1814                         link,
1815                         signal,
1816                         pipe_ctx->clock_source->id,
1817                         &current_setting);
1818
1819                 if (stream->sink_patches.dppowerup_delay > 0) {
1820                         int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay;
1821
1822                         msleep(delay_dp_power_up_in_ms);
1823                 }
1824
1825 #ifdef CONFIG_DRM_AMD_DC_HDCP
1826                 if (panel_mode == DP_PANEL_MODE_EDP) {
1827                         struct cp_psp *cp_psp = &stream->ctx->cp_psp;
1828
1829                         if (cp_psp && cp_psp->funcs.enable_assr)
1830                                 /* ASSR is bound to fail with unsigned PSP
1831                                  * verstage used during devlopment phase.
1832                                  * Report and continue with eDP panel mode to
1833                                  * perform eDP link training with right settings
1834                                  */
1835                                 cp_psp->funcs.enable_assr(cp_psp->handle, link);
1836                 }
1837 #endif
1838
1839                 dp_set_panel_mode(link, panel_mode);
1840
1841                 if (link->aux_access_disabled) {
1842                         dc_link_dp_perform_link_training_skip_aux(link, &current_setting);
1843                         return true;
1844                 } else {
1845                                 status = dc_link_dp_perform_link_training(
1846                                                                                 link,
1847                                                                                 &current_setting,
1848                                                                                 skip_video_pattern);
1849                         if (status == LINK_TRAINING_SUCCESS)
1850                                 return true;
1851                 }
1852
1853                 /* latest link training still fail, skip delay and keep PHY on
1854                  */
1855                 if (j == (attempts - 1) && link->ep_type == DISPLAY_ENDPOINT_PHY)
1856                         break;
1857
1858                 DC_LOG_WARNING("%s: Link training attempt %u of %d failed\n",
1859                         __func__, (unsigned int)j + 1, attempts);
1860
1861                 dp_disable_link_phy(link, signal);
1862
1863                 /* Abort link training if failure due to sink being unplugged. */
1864                 if (status == LINK_TRAINING_ABORT) {
1865                         enum dc_connection_type type = dc_connection_none;
1866
1867                         dc_link_detect_sink(link, &type);
1868                         if (type == dc_connection_none)
1869                                 break;
1870                 } else if (do_fallback) {
1871                         decide_fallback_link_setting(*link_setting, &current_setting, status);
1872                         /* Fail link training if reduced link bandwidth no longer meets
1873                          * stream requirements.
1874                          */
1875                         if (dc_bandwidth_in_kbps_from_timing(&stream->timing) <
1876                                         dc_link_bandwidth_kbps(link, &current_setting))
1877                                 break;
1878                 }
1879
1880                 msleep(delay_between_attempts);
1881
1882                 delay_between_attempts += LINK_TRAINING_RETRY_DELAY;
1883         }
1884
1885         return false;
1886 }
1887
1888 static enum clock_source_id get_clock_source_id(struct dc_link *link)
1889 {
1890         enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_UNDEFINED;
1891         struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source;
1892
1893         if (dp_cs != NULL) {
1894                 dp_cs_id = dp_cs->id;
1895         } else {
1896                 /*
1897                  * dp clock source is not initialized for some reason.
1898                  * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
1899                  */
1900                 ASSERT(dp_cs);
1901         }
1902
1903         return dp_cs_id;
1904 }
1905
1906 static void set_dp_mst_mode(struct dc_link *link, bool mst_enable)
1907 {
1908         if (mst_enable == false &&
1909                 link->type == dc_connection_mst_branch) {
1910                 /* Disable MST on link. Use only local sink. */
1911                 dp_disable_link_phy_mst(link, link->connector_signal);
1912
1913                 link->type = dc_connection_single;
1914                 link->local_sink = link->remote_sinks[0];
1915                 link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT;
1916                 dc_sink_retain(link->local_sink);
1917                 dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
1918         } else if (mst_enable == true &&
1919                         link->type == dc_connection_single &&
1920                         link->remote_sinks[0] != NULL) {
1921                 /* Re-enable MST on link. */
1922                 dp_disable_link_phy(link, link->connector_signal);
1923                 dp_enable_mst_on_sink(link, true);
1924
1925                 link->type = dc_connection_mst_branch;
1926                 link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
1927         }
1928 }
1929
1930 bool dc_link_dp_sync_lt_begin(struct dc_link *link)
1931 {
1932         /* Begin Sync LT. During this time,
1933          * DPCD:600h must not be powered down.
1934          */
1935         link->sync_lt_in_progress = true;
1936
1937         /*Clear any existing preferred settings.*/
1938         memset(&link->preferred_training_settings, 0,
1939                 sizeof(struct dc_link_training_overrides));
1940         memset(&link->preferred_link_setting, 0,
1941                 sizeof(struct dc_link_settings));
1942
1943         return true;
1944 }
1945
1946 enum link_training_result dc_link_dp_sync_lt_attempt(
1947     struct dc_link *link,
1948     struct dc_link_settings *link_settings,
1949     struct dc_link_training_overrides *lt_overrides)
1950 {
1951         struct link_training_settings lt_settings = {0};
1952         enum link_training_result lt_status = LINK_TRAINING_SUCCESS;
1953         enum dp_panel_mode panel_mode = DP_PANEL_MODE_DEFAULT;
1954         enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
1955         bool fec_enable = false;
1956
1957         dp_decide_training_settings(
1958                         link,
1959                         link_settings,
1960                         &lt_settings);
1961         override_training_settings(
1962                         link,
1963                         lt_overrides,
1964                         &lt_settings);
1965         /* Setup MST Mode */
1966         if (lt_overrides->mst_enable)
1967                 set_dp_mst_mode(link, *lt_overrides->mst_enable);
1968
1969         /* Disable link */
1970         dp_disable_link_phy(link, link->connector_signal);
1971
1972         /* Enable link */
1973         dp_cs_id = get_clock_source_id(link);
1974         dp_enable_link_phy(link, link->connector_signal,
1975                 dp_cs_id, link_settings);
1976
1977         /* Set FEC enable */
1978         fec_enable = lt_overrides->fec_enable && *lt_overrides->fec_enable;
1979         dp_set_fec_ready(link, fec_enable);
1980
1981         if (lt_overrides->alternate_scrambler_reset) {
1982                 if (*lt_overrides->alternate_scrambler_reset)
1983                         panel_mode = DP_PANEL_MODE_EDP;
1984                 else
1985                         panel_mode = DP_PANEL_MODE_DEFAULT;
1986         } else
1987                 panel_mode = dp_get_panel_mode(link);
1988
1989         dp_set_panel_mode(link, panel_mode);
1990
1991         /* Attempt to train with given link training settings */
1992         if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
1993                 start_clock_recovery_pattern_early(link, &lt_settings, DPRX);
1994
1995         /* Set link rate, lane count and spread. */
1996         dpcd_set_link_settings(link, &lt_settings);
1997
1998         /* 2. perform link training (set link training done
1999          *  to false is done as well)
2000          */
2001         lt_status = perform_clock_recovery_sequence(link, &lt_settings, DPRX);
2002         if (lt_status == LINK_TRAINING_SUCCESS) {
2003                 lt_status = perform_channel_equalization_sequence(link,
2004                                                 &lt_settings,
2005                                                 DPRX);
2006         }
2007
2008         /* 3. Sync LT must skip TRAINING_PATTERN_SET:0 (video pattern)*/
2009         /* 4. print status message*/
2010         print_status_message(link, &lt_settings, lt_status);
2011
2012         return lt_status;
2013 }
2014
2015 bool dc_link_dp_sync_lt_end(struct dc_link *link, bool link_down)
2016 {
2017         /* If input parameter is set, shut down phy.
2018          * Still shouldn't turn off dp_receiver (DPCD:600h)
2019          */
2020         if (link_down == true) {
2021                 dp_disable_link_phy(link, link->connector_signal);
2022                 dp_set_fec_ready(link, false);
2023         }
2024
2025         link->sync_lt_in_progress = false;
2026         return true;
2027 }
2028
2029 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, struct dc_link_settings *max_link_enc_cap)
2030 {
2031         if (!max_link_enc_cap) {
2032                 DC_LOG_ERROR("%s: Could not return max link encoder caps", __func__);
2033                 return false;
2034         }
2035
2036         if (link->link_enc->funcs->get_max_link_cap) {
2037                 link->link_enc->funcs->get_max_link_cap(link->link_enc, max_link_enc_cap);
2038                 return true;
2039         }
2040
2041         DC_LOG_ERROR("%s: Max link encoder caps unknown", __func__);
2042         max_link_enc_cap->lane_count = 1;
2043         max_link_enc_cap->link_rate = 6;
2044         return false;
2045 }
2046
2047 static struct dc_link_settings get_max_link_cap(struct dc_link *link)
2048 {
2049         struct dc_link_settings max_link_cap = {0};
2050
2051         /* get max link encoder capability */
2052         link->link_enc->funcs->get_max_link_cap(link->link_enc, &max_link_cap);
2053
2054         /* Lower link settings based on sink's link cap */
2055         if (link->reported_link_cap.lane_count < max_link_cap.lane_count)
2056                 max_link_cap.lane_count =
2057                                 link->reported_link_cap.lane_count;
2058         if (link->reported_link_cap.link_rate < max_link_cap.link_rate)
2059                 max_link_cap.link_rate =
2060                                 link->reported_link_cap.link_rate;
2061         if (link->reported_link_cap.link_spread <
2062                         max_link_cap.link_spread)
2063                 max_link_cap.link_spread =
2064                                 link->reported_link_cap.link_spread;
2065         /*
2066          * account for lttpr repeaters cap
2067          * notes: repeaters do not snoop in the DPRX Capabilities addresses (3.6.3).
2068          */
2069         if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
2070                 if (link->dpcd_caps.lttpr_caps.max_lane_count < max_link_cap.lane_count)
2071                         max_link_cap.lane_count = link->dpcd_caps.lttpr_caps.max_lane_count;
2072
2073                 if (link->dpcd_caps.lttpr_caps.max_link_rate < max_link_cap.link_rate)
2074                         max_link_cap.link_rate = link->dpcd_caps.lttpr_caps.max_link_rate;
2075
2076                 DC_LOG_HW_LINK_TRAINING("%s\n Training with LTTPR,  max_lane count %d max_link rate %d \n",
2077                                                 __func__,
2078                                                 max_link_cap.lane_count,
2079                                                 max_link_cap.link_rate);
2080         }
2081         return max_link_cap;
2082 }
2083
2084 enum dc_status read_hpd_rx_irq_data(
2085         struct dc_link *link,
2086         union hpd_irq_data *irq_data)
2087 {
2088         static enum dc_status retval;
2089
2090         /* The HW reads 16 bytes from 200h on HPD,
2091          * but if we get an AUX_DEFER, the HW cannot retry
2092          * and this causes the CTS tests 4.3.2.1 - 3.2.4 to
2093          * fail, so we now explicitly read 6 bytes which is
2094          * the req from the above mentioned test cases.
2095          *
2096          * For DP 1.4 we need to read those from 2002h range.
2097          */
2098         if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14)
2099                 retval = core_link_read_dpcd(
2100                         link,
2101                         DP_SINK_COUNT,
2102                         irq_data->raw,
2103                         sizeof(union hpd_irq_data));
2104         else {
2105                 /* Read 14 bytes in a single read and then copy only the required fields.
2106                  * This is more efficient than doing it in two separate AUX reads. */
2107
2108                 uint8_t tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI + 1];
2109
2110                 retval = core_link_read_dpcd(
2111                         link,
2112                         DP_SINK_COUNT_ESI,
2113                         tmp,
2114                         sizeof(tmp));
2115
2116                 if (retval != DC_OK)
2117                         return retval;
2118
2119                 irq_data->bytes.sink_cnt.raw = tmp[DP_SINK_COUNT_ESI - DP_SINK_COUNT_ESI];
2120                 irq_data->bytes.device_service_irq.raw = tmp[DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 - DP_SINK_COUNT_ESI];
2121                 irq_data->bytes.lane01_status.raw = tmp[DP_LANE0_1_STATUS_ESI - DP_SINK_COUNT_ESI];
2122                 irq_data->bytes.lane23_status.raw = tmp[DP_LANE2_3_STATUS_ESI - DP_SINK_COUNT_ESI];
2123                 irq_data->bytes.lane_status_updated.raw = tmp[DP_LANE_ALIGN_STATUS_UPDATED_ESI - DP_SINK_COUNT_ESI];
2124                 irq_data->bytes.sink_status.raw = tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI];
2125         }
2126
2127         return retval;
2128 }
2129
2130 bool hpd_rx_irq_check_link_loss_status(
2131         struct dc_link *link,
2132         union hpd_irq_data *hpd_irq_dpcd_data)
2133 {
2134         uint8_t irq_reg_rx_power_state = 0;
2135         enum dc_status dpcd_result = DC_ERROR_UNEXPECTED;
2136         union lane_status lane_status;
2137         uint32_t lane;
2138         bool sink_status_changed;
2139         bool return_code;
2140
2141         sink_status_changed = false;
2142         return_code = false;
2143
2144         if (link->cur_link_settings.lane_count == 0)
2145                 return return_code;
2146
2147         /*1. Check that Link Status changed, before re-training.*/
2148
2149         /*parse lane status*/
2150         for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
2151                 /* check status of lanes 0,1
2152                  * changed DpcdAddress_Lane01Status (0x202)
2153                  */
2154                 lane_status.raw = get_nibble_at_index(
2155                         &hpd_irq_dpcd_data->bytes.lane01_status.raw,
2156                         lane);
2157
2158                 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
2159                         !lane_status.bits.CR_DONE_0 ||
2160                         !lane_status.bits.SYMBOL_LOCKED_0) {
2161                         /* if one of the channel equalization, clock
2162                          * recovery or symbol lock is dropped
2163                          * consider it as (link has been
2164                          * dropped) dp sink status has changed
2165                          */
2166                         sink_status_changed = true;
2167                         break;
2168                 }
2169         }
2170
2171         /* Check interlane align.*/
2172         if (sink_status_changed ||
2173                 !hpd_irq_dpcd_data->bytes.lane_status_updated.bits.INTERLANE_ALIGN_DONE) {
2174
2175                 DC_LOG_HW_HPD_IRQ("%s: Link Status changed.\n", __func__);
2176
2177                 return_code = true;
2178
2179                 /*2. Check that we can handle interrupt: Not in FS DOS,
2180                  *  Not in "Display Timeout" state, Link is trained.
2181                  */
2182                 dpcd_result = core_link_read_dpcd(link,
2183                         DP_SET_POWER,
2184                         &irq_reg_rx_power_state,
2185                         sizeof(irq_reg_rx_power_state));
2186
2187                 if (dpcd_result != DC_OK) {
2188                         DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain power state.\n",
2189                                 __func__);
2190                 } else {
2191                         if (irq_reg_rx_power_state != DP_SET_POWER_D0)
2192                                 return_code = false;
2193                 }
2194         }
2195
2196         return return_code;
2197 }
2198
2199 bool dp_verify_link_cap(
2200         struct dc_link *link,
2201         struct dc_link_settings *known_limit_link_setting,
2202         int *fail_count)
2203 {
2204         struct dc_link_settings max_link_cap = {0};
2205         struct dc_link_settings cur_link_setting = {0};
2206         struct dc_link_settings *cur = &cur_link_setting;
2207         struct dc_link_settings initial_link_settings = {0};
2208         bool success;
2209         bool skip_link_training;
2210         bool skip_video_pattern;
2211         enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
2212         enum link_training_result status;
2213         union hpd_irq_data irq_data;
2214
2215         if (link->dc->debug.skip_detection_link_training) {
2216                 link->verified_link_cap = *known_limit_link_setting;
2217                 return true;
2218         }
2219
2220         memset(&irq_data, 0, sizeof(irq_data));
2221         success = false;
2222         skip_link_training = false;
2223
2224         max_link_cap = get_max_link_cap(link);
2225
2226         /* Grant extended timeout request */
2227         if ((link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && (link->dpcd_caps.lttpr_caps.max_ext_timeout > 0)) {
2228                 uint8_t grant = link->dpcd_caps.lttpr_caps.max_ext_timeout & 0x80;
2229
2230                 core_link_write_dpcd(link, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, &grant, sizeof(grant));
2231         }
2232
2233         /* TODO implement override and monitor patch later */
2234
2235         /* try to train the link from high to low to
2236          * find the physical link capability
2237          */
2238         /* disable PHY done possible by BIOS, will be done by driver itself */
2239         dp_disable_link_phy(link, link->connector_signal);
2240
2241         dp_cs_id = get_clock_source_id(link);
2242
2243         /* link training starts with the maximum common settings
2244          * supported by both sink and ASIC.
2245          */
2246         initial_link_settings = get_common_supported_link_settings(
2247                         *known_limit_link_setting,
2248                         max_link_cap);
2249         cur_link_setting = initial_link_settings;
2250
2251         /* Temporary Renoir-specific workaround for SWDEV-215184;
2252          * PHY will sometimes be in bad state on hotplugging display from certain USB-C dongle,
2253          * so add extra cycle of enabling and disabling the PHY before first link training.
2254          */
2255         if (link->link_enc->features.flags.bits.DP_IS_USB_C &&
2256                         link->dc->debug.usbc_combo_phy_reset_wa) {
2257                 dp_enable_link_phy(link, link->connector_signal, dp_cs_id, cur);
2258                 dp_disable_link_phy(link, link->connector_signal);
2259         }
2260
2261         do {
2262                 skip_video_pattern = true;
2263
2264                 if (cur->link_rate == LINK_RATE_LOW)
2265                         skip_video_pattern = false;
2266
2267                 dp_enable_link_phy(
2268                                 link,
2269                                 link->connector_signal,
2270                                 dp_cs_id,
2271                                 cur);
2272
2273
2274                 if (skip_link_training)
2275                         success = true;
2276                 else {
2277                         status = dc_link_dp_perform_link_training(
2278                                                         link,
2279                                                         cur,
2280                                                         skip_video_pattern);
2281                         if (status == LINK_TRAINING_SUCCESS)
2282                                 success = true;
2283                         else
2284                                 (*fail_count)++;
2285                 }
2286
2287                 if (success) {
2288                         link->verified_link_cap = *cur;
2289                         udelay(1000);
2290                         if (read_hpd_rx_irq_data(link, &irq_data) == DC_OK)
2291                                 if (hpd_rx_irq_check_link_loss_status(
2292                                                 link,
2293                                                 &irq_data))
2294                                         (*fail_count)++;
2295                 }
2296                 /* always disable the link before trying another
2297                  * setting or before returning we'll enable it later
2298                  * based on the actual mode we're driving
2299                  */
2300                 dp_disable_link_phy(link, link->connector_signal);
2301         } while (!success && decide_fallback_link_setting(
2302                         initial_link_settings, cur, status));
2303
2304         /* Link Training failed for all Link Settings
2305          *  (Lane Count is still unknown)
2306          */
2307         if (!success) {
2308                 /* If all LT fails for all settings,
2309                  * set verified = failed safe (1 lane low)
2310                  */
2311                 link->verified_link_cap.lane_count = LANE_COUNT_ONE;
2312                 link->verified_link_cap.link_rate = LINK_RATE_LOW;
2313
2314                 link->verified_link_cap.link_spread =
2315                 LINK_SPREAD_DISABLED;
2316         }
2317
2318
2319         return success;
2320 }
2321
2322 bool dp_verify_link_cap_with_retries(
2323         struct dc_link *link,
2324         struct dc_link_settings *known_limit_link_setting,
2325         int attempts)
2326 {
2327         int i = 0;
2328         bool success = false;
2329
2330         for (i = 0; i < attempts; i++) {
2331                 int fail_count = 0;
2332                 enum dc_connection_type type = dc_connection_none;
2333
2334                 memset(&link->verified_link_cap, 0,
2335                                 sizeof(struct dc_link_settings));
2336                 if (!dc_link_detect_sink(link, &type) || type == dc_connection_none) {
2337                         link->verified_link_cap.lane_count = LANE_COUNT_ONE;
2338                         link->verified_link_cap.link_rate = LINK_RATE_LOW;
2339                         link->verified_link_cap.link_spread = LINK_SPREAD_DISABLED;
2340                         break;
2341                 } else if (dp_verify_link_cap(link,
2342                                 &link->reported_link_cap,
2343                                 &fail_count) && fail_count == 0) {
2344                         success = true;
2345                         break;
2346                 }
2347                 msleep(10);
2348         }
2349         return success;
2350 }
2351
2352 bool dp_verify_mst_link_cap(
2353         struct dc_link *link)
2354 {
2355         struct dc_link_settings max_link_cap = {0};
2356
2357         max_link_cap = get_max_link_cap(link);
2358         link->verified_link_cap = get_common_supported_link_settings(
2359                 link->reported_link_cap,
2360                 max_link_cap);
2361
2362         return true;
2363 }
2364
2365 static struct dc_link_settings get_common_supported_link_settings(
2366                 struct dc_link_settings link_setting_a,
2367                 struct dc_link_settings link_setting_b)
2368 {
2369         struct dc_link_settings link_settings = {0};
2370
2371         link_settings.lane_count =
2372                 (link_setting_a.lane_count <=
2373                         link_setting_b.lane_count) ?
2374                         link_setting_a.lane_count :
2375                         link_setting_b.lane_count;
2376         link_settings.link_rate =
2377                 (link_setting_a.link_rate <=
2378                         link_setting_b.link_rate) ?
2379                         link_setting_a.link_rate :
2380                         link_setting_b.link_rate;
2381         link_settings.link_spread = LINK_SPREAD_DISABLED;
2382
2383         /* in DP compliance test, DPR-120 may have
2384          * a random value in its MAX_LINK_BW dpcd field.
2385          * We map it to the maximum supported link rate that
2386          * is smaller than MAX_LINK_BW in this case.
2387          */
2388         if (link_settings.link_rate > LINK_RATE_HIGH3) {
2389                 link_settings.link_rate = LINK_RATE_HIGH3;
2390         } else if (link_settings.link_rate < LINK_RATE_HIGH3
2391                         && link_settings.link_rate > LINK_RATE_HIGH2) {
2392                 link_settings.link_rate = LINK_RATE_HIGH2;
2393         } else if (link_settings.link_rate < LINK_RATE_HIGH2
2394                         && link_settings.link_rate > LINK_RATE_HIGH) {
2395                 link_settings.link_rate = LINK_RATE_HIGH;
2396         } else if (link_settings.link_rate < LINK_RATE_HIGH
2397                         && link_settings.link_rate > LINK_RATE_LOW) {
2398                 link_settings.link_rate = LINK_RATE_LOW;
2399         } else if (link_settings.link_rate < LINK_RATE_LOW) {
2400                 link_settings.link_rate = LINK_RATE_UNKNOWN;
2401         }
2402
2403         return link_settings;
2404 }
2405
2406 static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count)
2407 {
2408         return lane_count <= LANE_COUNT_ONE;
2409 }
2410
2411 static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate)
2412 {
2413         return link_rate <= LINK_RATE_LOW;
2414 }
2415
2416 static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count)
2417 {
2418         switch (lane_count) {
2419         case LANE_COUNT_FOUR:
2420                 return LANE_COUNT_TWO;
2421         case LANE_COUNT_TWO:
2422                 return LANE_COUNT_ONE;
2423         case LANE_COUNT_ONE:
2424                 return LANE_COUNT_UNKNOWN;
2425         default:
2426                 return LANE_COUNT_UNKNOWN;
2427         }
2428 }
2429
2430 static enum dc_link_rate reduce_link_rate(enum dc_link_rate link_rate)
2431 {
2432         switch (link_rate) {
2433         case LINK_RATE_HIGH3:
2434                 return LINK_RATE_HIGH2;
2435         case LINK_RATE_HIGH2:
2436                 return LINK_RATE_HIGH;
2437         case LINK_RATE_HIGH:
2438                 return LINK_RATE_LOW;
2439         case LINK_RATE_LOW:
2440                 return LINK_RATE_UNKNOWN;
2441         default:
2442                 return LINK_RATE_UNKNOWN;
2443         }
2444 }
2445
2446 static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count)
2447 {
2448         switch (lane_count) {
2449         case LANE_COUNT_ONE:
2450                 return LANE_COUNT_TWO;
2451         case LANE_COUNT_TWO:
2452                 return LANE_COUNT_FOUR;
2453         default:
2454                 return LANE_COUNT_UNKNOWN;
2455         }
2456 }
2457
2458 static enum dc_link_rate increase_link_rate(enum dc_link_rate link_rate)
2459 {
2460         switch (link_rate) {
2461         case LINK_RATE_LOW:
2462                 return LINK_RATE_HIGH;
2463         case LINK_RATE_HIGH:
2464                 return LINK_RATE_HIGH2;
2465         case LINK_RATE_HIGH2:
2466                 return LINK_RATE_HIGH3;
2467         default:
2468                 return LINK_RATE_UNKNOWN;
2469         }
2470 }
2471
2472 /*
2473  * function: set link rate and lane count fallback based
2474  * on current link setting and last link training result
2475  * return value:
2476  *                      true - link setting could be set
2477  *                      false - has reached minimum setting
2478  *                                      and no further fallback could be done
2479  */
2480 static bool decide_fallback_link_setting(
2481                 struct dc_link_settings initial_link_settings,
2482                 struct dc_link_settings *current_link_setting,
2483                 enum link_training_result training_result)
2484 {
2485         if (!current_link_setting)
2486                 return false;
2487
2488         switch (training_result) {
2489         case LINK_TRAINING_CR_FAIL_LANE0:
2490         case LINK_TRAINING_CR_FAIL_LANE1:
2491         case LINK_TRAINING_CR_FAIL_LANE23:
2492         case LINK_TRAINING_LQA_FAIL:
2493         {
2494                 if (!reached_minimum_link_rate
2495                                 (current_link_setting->link_rate)) {
2496                         current_link_setting->link_rate =
2497                                 reduce_link_rate(
2498                                         current_link_setting->link_rate);
2499                 } else if (!reached_minimum_lane_count
2500                                 (current_link_setting->lane_count)) {
2501                         current_link_setting->link_rate =
2502                                 initial_link_settings.link_rate;
2503                         if (training_result == LINK_TRAINING_CR_FAIL_LANE0)
2504                                 return false;
2505                         else if (training_result == LINK_TRAINING_CR_FAIL_LANE1)
2506                                 current_link_setting->lane_count =
2507                                                 LANE_COUNT_ONE;
2508                         else if (training_result ==
2509                                         LINK_TRAINING_CR_FAIL_LANE23)
2510                                 current_link_setting->lane_count =
2511                                                 LANE_COUNT_TWO;
2512                         else
2513                                 current_link_setting->lane_count =
2514                                         reduce_lane_count(
2515                                         current_link_setting->lane_count);
2516                 } else {
2517                         return false;
2518                 }
2519                 break;
2520         }
2521         case LINK_TRAINING_EQ_FAIL_EQ:
2522         {
2523                 if (!reached_minimum_lane_count
2524                                 (current_link_setting->lane_count)) {
2525                         current_link_setting->lane_count =
2526                                 reduce_lane_count(
2527                                         current_link_setting->lane_count);
2528                 } else if (!reached_minimum_link_rate
2529                                 (current_link_setting->link_rate)) {
2530                         current_link_setting->link_rate =
2531                                 reduce_link_rate(
2532                                         current_link_setting->link_rate);
2533                 } else {
2534                         return false;
2535                 }
2536                 break;
2537         }
2538         case LINK_TRAINING_EQ_FAIL_CR:
2539         {
2540                 if (!reached_minimum_link_rate
2541                                 (current_link_setting->link_rate)) {
2542                         current_link_setting->link_rate =
2543                                 reduce_link_rate(
2544                                         current_link_setting->link_rate);
2545                 } else {
2546                         return false;
2547                 }
2548                 break;
2549         }
2550         default:
2551                 return false;
2552         }
2553         return true;
2554 }
2555
2556 bool dp_validate_mode_timing(
2557         struct dc_link *link,
2558         const struct dc_crtc_timing *timing)
2559 {
2560         uint32_t req_bw;
2561         uint32_t max_bw;
2562
2563         const struct dc_link_settings *link_setting;
2564
2565         /* According to spec, VSC SDP should be used if pixel format is YCbCr420 */
2566         if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 &&
2567                         !link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED &&
2568                         dal_graphics_object_id_get_connector_id(link->link_id) != CONNECTOR_ID_VIRTUAL)
2569                 return false;
2570
2571         /*always DP fail safe mode*/
2572         if ((timing->pix_clk_100hz / 10) == (uint32_t) 25175 &&
2573                 timing->h_addressable == (uint32_t) 640 &&
2574                 timing->v_addressable == (uint32_t) 480)
2575                 return true;
2576
2577         link_setting = dc_link_get_link_cap(link);
2578
2579         /* TODO: DYNAMIC_VALIDATION needs to be implemented */
2580         /*if (flags.DYNAMIC_VALIDATION == 1 &&
2581                 link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN)
2582                 link_setting = &link->verified_link_cap;
2583         */
2584
2585         req_bw = dc_bandwidth_in_kbps_from_timing(timing);
2586         max_bw = dc_link_bandwidth_kbps(link, link_setting);
2587
2588         if (req_bw <= max_bw) {
2589                 /* remember the biggest mode here, during
2590                  * initial link training (to get
2591                  * verified_link_cap), LS sends event about
2592                  * cannot train at reported cap to upper
2593                  * layer and upper layer will re-enumerate modes.
2594                  * this is not necessary if the lower
2595                  * verified_link_cap is enough to drive
2596                  * all the modes */
2597
2598                 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
2599                 /* if (flags.DYNAMIC_VALIDATION == 1)
2600                         dpsst->max_req_bw_for_verified_linkcap = dal_max(
2601                                 dpsst->max_req_bw_for_verified_linkcap, req_bw); */
2602                 return true;
2603         } else
2604                 return false;
2605 }
2606
2607 static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
2608 {
2609         struct dc_link_settings initial_link_setting = {
2610                 LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED, false, 0};
2611         struct dc_link_settings current_link_setting =
2612                         initial_link_setting;
2613         uint32_t link_bw;
2614
2615         if (req_bw > dc_link_bandwidth_kbps(link, &link->verified_link_cap))
2616                 return false;
2617
2618         /* search for the minimum link setting that:
2619          * 1. is supported according to the link training result
2620          * 2. could support the b/w requested by the timing
2621          */
2622         while (current_link_setting.link_rate <=
2623                         link->verified_link_cap.link_rate) {
2624                 link_bw = dc_link_bandwidth_kbps(
2625                                 link,
2626                                 &current_link_setting);
2627                 if (req_bw <= link_bw) {
2628                         *link_setting = current_link_setting;
2629                         return true;
2630                 }
2631
2632                 if (current_link_setting.lane_count <
2633                                 link->verified_link_cap.lane_count) {
2634                         current_link_setting.lane_count =
2635                                         increase_lane_count(
2636                                                         current_link_setting.lane_count);
2637                 } else {
2638                         current_link_setting.link_rate =
2639                                         increase_link_rate(
2640                                                         current_link_setting.link_rate);
2641                         current_link_setting.lane_count =
2642                                         initial_link_setting.lane_count;
2643                 }
2644         }
2645
2646         return false;
2647 }
2648
2649 bool decide_edp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
2650 {
2651         struct dc_link_settings initial_link_setting;
2652         struct dc_link_settings current_link_setting;
2653         uint32_t link_bw;
2654
2655         /*
2656          * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
2657          * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
2658          */
2659         if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_13 ||
2660                         link->dpcd_caps.edp_supported_link_rates_count == 0) {
2661                 *link_setting = link->verified_link_cap;
2662                 return true;
2663         }
2664
2665         memset(&initial_link_setting, 0, sizeof(initial_link_setting));
2666         initial_link_setting.lane_count = LANE_COUNT_ONE;
2667         initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0];
2668         initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
2669         initial_link_setting.use_link_rate_set = true;
2670         initial_link_setting.link_rate_set = 0;
2671         current_link_setting = initial_link_setting;
2672
2673         /* search for the minimum link setting that:
2674          * 1. is supported according to the link training result
2675          * 2. could support the b/w requested by the timing
2676          */
2677         while (current_link_setting.link_rate <=
2678                         link->verified_link_cap.link_rate) {
2679                 link_bw = dc_link_bandwidth_kbps(
2680                                 link,
2681                                 &current_link_setting);
2682                 if (req_bw <= link_bw) {
2683                         *link_setting = current_link_setting;
2684                         return true;
2685                 }
2686
2687                 if (current_link_setting.lane_count <
2688                                 link->verified_link_cap.lane_count) {
2689                         current_link_setting.lane_count =
2690                                         increase_lane_count(
2691                                                         current_link_setting.lane_count);
2692                 } else {
2693                         if (current_link_setting.link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
2694                                 current_link_setting.link_rate_set++;
2695                                 current_link_setting.link_rate =
2696                                         link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
2697                                 current_link_setting.lane_count =
2698                                                                         initial_link_setting.lane_count;
2699                         } else
2700                                 break;
2701                 }
2702         }
2703         return false;
2704 }
2705
2706 static bool decide_mst_link_settings(const struct dc_link *link, struct dc_link_settings *link_setting)
2707 {
2708         *link_setting = link->verified_link_cap;
2709         return true;
2710 }
2711
2712 void decide_link_settings(struct dc_stream_state *stream,
2713         struct dc_link_settings *link_setting)
2714 {
2715         struct dc_link *link;
2716         uint32_t req_bw;
2717
2718         req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing);
2719
2720         link = stream->link;
2721
2722         /* if preferred is specified through AMDDP, use it, if it's enough
2723          * to drive the mode
2724          */
2725         if (link->preferred_link_setting.lane_count !=
2726                         LANE_COUNT_UNKNOWN &&
2727                         link->preferred_link_setting.link_rate !=
2728                                         LINK_RATE_UNKNOWN) {
2729                 *link_setting =  link->preferred_link_setting;
2730                 return;
2731         }
2732
2733         /* MST doesn't perform link training for now
2734          * TODO: add MST specific link training routine
2735          */
2736         if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2737                 if (decide_mst_link_settings(link, link_setting))
2738                         return;
2739         } else if (link->connector_signal == SIGNAL_TYPE_EDP) {
2740                 if (decide_edp_link_settings(link, link_setting, req_bw))
2741                         return;
2742         } else if (decide_dp_link_settings(link, link_setting, req_bw))
2743                 return;
2744
2745         BREAK_TO_DEBUGGER();
2746         ASSERT(link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN);
2747
2748         *link_setting = link->verified_link_cap;
2749 }
2750
2751 /*************************Short Pulse IRQ***************************/
2752 static bool allow_hpd_rx_irq(const struct dc_link *link)
2753 {
2754         /*
2755          * Don't handle RX IRQ unless one of following is met:
2756          * 1) The link is established (cur_link_settings != unknown)
2757          * 2) We know we're dealing with a branch device, SST or MST
2758          */
2759
2760         if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
2761                 is_dp_branch_device(link))
2762                 return true;
2763
2764         return false;
2765 }
2766
2767 static bool handle_hpd_irq_psr_sink(struct dc_link *link)
2768 {
2769         union dpcd_psr_configuration psr_configuration;
2770
2771         if (!link->psr_settings.psr_feature_enabled)
2772                 return false;
2773
2774         dm_helpers_dp_read_dpcd(
2775                 link->ctx,
2776                 link,
2777                 368,/*DpcdAddress_PSR_Enable_Cfg*/
2778                 &psr_configuration.raw,
2779                 sizeof(psr_configuration.raw));
2780
2781
2782         if (psr_configuration.bits.ENABLE) {
2783                 unsigned char dpcdbuf[3] = {0};
2784                 union psr_error_status psr_error_status;
2785                 union psr_sink_psr_status psr_sink_psr_status;
2786
2787                 dm_helpers_dp_read_dpcd(
2788                         link->ctx,
2789                         link,
2790                         0x2006, /*DpcdAddress_PSR_Error_Status*/
2791                         (unsigned char *) dpcdbuf,
2792                         sizeof(dpcdbuf));
2793
2794                 /*DPCD 2006h   ERROR STATUS*/
2795                 psr_error_status.raw = dpcdbuf[0];
2796                 /*DPCD 2008h   SINK PANEL SELF REFRESH STATUS*/
2797                 psr_sink_psr_status.raw = dpcdbuf[2];
2798
2799                 if (psr_error_status.bits.LINK_CRC_ERROR ||
2800                                 psr_error_status.bits.RFB_STORAGE_ERROR ||
2801                                 psr_error_status.bits.VSC_SDP_ERROR) {
2802                         /* Acknowledge and clear error bits */
2803                         dm_helpers_dp_write_dpcd(
2804                                 link->ctx,
2805                                 link,
2806                                 8198,/*DpcdAddress_PSR_Error_Status*/
2807                                 &psr_error_status.raw,
2808                                 sizeof(psr_error_status.raw));
2809
2810                         /* PSR error, disable and re-enable PSR */
2811                         dc_link_set_psr_allow_active(link, false, true, false);
2812                         dc_link_set_psr_allow_active(link, true, true, false);
2813
2814                         return true;
2815                 } else if (psr_sink_psr_status.bits.SINK_SELF_REFRESH_STATUS ==
2816                                 PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB){
2817                         /* No error is detect, PSR is active.
2818                          * We should return with IRQ_HPD handled without
2819                          * checking for loss of sync since PSR would have
2820                          * powered down main link.
2821                          */
2822                         return true;
2823                 }
2824         }
2825         return false;
2826 }
2827
2828 static void dp_test_send_link_training(struct dc_link *link)
2829 {
2830         struct dc_link_settings link_settings = {0};
2831
2832         core_link_read_dpcd(
2833                         link,
2834                         DP_TEST_LANE_COUNT,
2835                         (unsigned char *)(&link_settings.lane_count),
2836                         1);
2837         core_link_read_dpcd(
2838                         link,
2839                         DP_TEST_LINK_RATE,
2840                         (unsigned char *)(&link_settings.link_rate),
2841                         1);
2842
2843         /* Set preferred link settings */
2844         link->verified_link_cap.lane_count = link_settings.lane_count;
2845         link->verified_link_cap.link_rate = link_settings.link_rate;
2846
2847         dp_retrain_link_dp_test(link, &link_settings, false);
2848 }
2849
2850 /* TODO Raven hbr2 compliance eye output is unstable
2851  * (toggling on and off) with debugger break
2852  * This caueses intermittent PHY automation failure
2853  * Need to look into the root cause */
2854 static void dp_test_send_phy_test_pattern(struct dc_link *link)
2855 {
2856         union phy_test_pattern dpcd_test_pattern;
2857         union lane_adjust dpcd_lane_adjustment[2];
2858         unsigned char dpcd_post_cursor_2_adjustment = 0;
2859         unsigned char test_pattern_buffer[
2860                         (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2861                         DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1] = {0};
2862         unsigned int test_pattern_size = 0;
2863         enum dp_test_pattern test_pattern;
2864         struct dc_link_training_settings link_settings;
2865         union lane_adjust dpcd_lane_adjust;
2866         unsigned int lane;
2867         struct link_training_settings link_training_settings;
2868         int i = 0;
2869
2870         dpcd_test_pattern.raw = 0;
2871         memset(dpcd_lane_adjustment, 0, sizeof(dpcd_lane_adjustment));
2872         memset(&link_settings, 0, sizeof(link_settings));
2873
2874         /* get phy test pattern and pattern parameters from DP receiver */
2875         core_link_read_dpcd(
2876                         link,
2877                         DP_PHY_TEST_PATTERN,
2878                         &dpcd_test_pattern.raw,
2879                         sizeof(dpcd_test_pattern));
2880         core_link_read_dpcd(
2881                         link,
2882                         DP_ADJUST_REQUEST_LANE0_1,
2883                         &dpcd_lane_adjustment[0].raw,
2884                         sizeof(dpcd_lane_adjustment));
2885
2886         /*get post cursor 2 parameters
2887          * For DP 1.1a or eariler, this DPCD register's value is 0
2888          * For DP 1.2 or later:
2889          * Bits 1:0 = POST_CURSOR2_LANE0; Bits 3:2 = POST_CURSOR2_LANE1
2890          * Bits 5:4 = POST_CURSOR2_LANE2; Bits 7:6 = POST_CURSOR2_LANE3
2891          */
2892         core_link_read_dpcd(
2893                         link,
2894                         DP_ADJUST_REQUEST_POST_CURSOR2,
2895                         &dpcd_post_cursor_2_adjustment,
2896                         sizeof(dpcd_post_cursor_2_adjustment));
2897
2898         /* translate request */
2899         switch (dpcd_test_pattern.bits.PATTERN) {
2900         case PHY_TEST_PATTERN_D10_2:
2901                 test_pattern = DP_TEST_PATTERN_D102;
2902                 break;
2903         case PHY_TEST_PATTERN_SYMBOL_ERROR:
2904                 test_pattern = DP_TEST_PATTERN_SYMBOL_ERROR;
2905                 break;
2906         case PHY_TEST_PATTERN_PRBS7:
2907                 test_pattern = DP_TEST_PATTERN_PRBS7;
2908                 break;
2909         case PHY_TEST_PATTERN_80BIT_CUSTOM:
2910                 test_pattern = DP_TEST_PATTERN_80BIT_CUSTOM;
2911                 break;
2912         case PHY_TEST_PATTERN_CP2520_1:
2913                 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
2914                 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
2915                                 DP_TEST_PATTERN_TRAINING_PATTERN4 :
2916                                 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
2917                 break;
2918         case PHY_TEST_PATTERN_CP2520_2:
2919                 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
2920                 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
2921                                 DP_TEST_PATTERN_TRAINING_PATTERN4 :
2922                                 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
2923                 break;
2924         case PHY_TEST_PATTERN_CP2520_3:
2925                 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4;
2926                 break;
2927         default:
2928                 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
2929         break;
2930         }
2931
2932         if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) {
2933                 test_pattern_size = (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2934                                 DP_TEST_80BIT_CUSTOM_PATTERN_7_0) + 1;
2935                 core_link_read_dpcd(
2936                                 link,
2937                                 DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
2938                                 test_pattern_buffer,
2939                                 test_pattern_size);
2940         }
2941
2942         /* prepare link training settings */
2943         link_settings.link = link->cur_link_settings;
2944
2945         for (lane = 0; lane <
2946                 (unsigned int)(link->cur_link_settings.lane_count);
2947                 lane++) {
2948                 dpcd_lane_adjust.raw =
2949                         get_nibble_at_index(&dpcd_lane_adjustment[0].raw, lane);
2950                 link_settings.lane_settings[lane].VOLTAGE_SWING =
2951                         (enum dc_voltage_swing)
2952                         (dpcd_lane_adjust.bits.VOLTAGE_SWING_LANE);
2953                 link_settings.lane_settings[lane].PRE_EMPHASIS =
2954                         (enum dc_pre_emphasis)
2955                         (dpcd_lane_adjust.bits.PRE_EMPHASIS_LANE);
2956                 link_settings.lane_settings[lane].POST_CURSOR2 =
2957                         (enum dc_post_cursor2)
2958                         ((dpcd_post_cursor_2_adjustment >> (lane * 2)) & 0x03);
2959         }
2960
2961         for (i = 0; i < 4; i++)
2962                 link_training_settings.lane_settings[i] =
2963                                 link_settings.lane_settings[i];
2964         link_training_settings.link_settings = link_settings.link;
2965         link_training_settings.allow_invalid_msa_timing_param = false;
2966         /*Usage: Measure DP physical lane signal
2967          * by DP SI test equipment automatically.
2968          * PHY test pattern request is generated by equipment via HPD interrupt.
2969          * HPD needs to be active all the time. HPD should be active
2970          * all the time. Do not touch it.
2971          * forward request to DS
2972          */
2973         dc_link_dp_set_test_pattern(
2974                 link,
2975                 test_pattern,
2976                 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED,
2977                 &link_training_settings,
2978                 test_pattern_buffer,
2979                 test_pattern_size);
2980 }
2981
2982 static void dp_test_send_link_test_pattern(struct dc_link *link)
2983 {
2984         union link_test_pattern dpcd_test_pattern;
2985         union test_misc dpcd_test_params;
2986         enum dp_test_pattern test_pattern;
2987         enum dp_test_pattern_color_space test_pattern_color_space =
2988                         DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED;
2989         enum dc_color_depth requestColorDepth = COLOR_DEPTH_UNDEFINED;
2990         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
2991         struct pipe_ctx *pipe_ctx = NULL;
2992         int i;
2993
2994         memset(&dpcd_test_pattern, 0, sizeof(dpcd_test_pattern));
2995         memset(&dpcd_test_params, 0, sizeof(dpcd_test_params));
2996
2997         for (i = 0; i < MAX_PIPES; i++) {
2998                 if (pipes[i].stream == NULL)
2999                         continue;
3000
3001                 if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
3002                         pipe_ctx = &pipes[i];
3003                         break;
3004                 }
3005         }
3006
3007         if (pipe_ctx == NULL)
3008                 return;
3009
3010         /* get link test pattern and pattern parameters */
3011         core_link_read_dpcd(
3012                         link,
3013                         DP_TEST_PATTERN,
3014                         &dpcd_test_pattern.raw,
3015                         sizeof(dpcd_test_pattern));
3016         core_link_read_dpcd(
3017                         link,
3018                         DP_TEST_MISC0,
3019                         &dpcd_test_params.raw,
3020                         sizeof(dpcd_test_params));
3021
3022         switch (dpcd_test_pattern.bits.PATTERN) {
3023         case LINK_TEST_PATTERN_COLOR_RAMP:
3024                 test_pattern = DP_TEST_PATTERN_COLOR_RAMP;
3025         break;
3026         case LINK_TEST_PATTERN_VERTICAL_BARS:
3027                 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;
3028         break; /* black and white */
3029         case LINK_TEST_PATTERN_COLOR_SQUARES:
3030                 test_pattern = (dpcd_test_params.bits.DYN_RANGE ==
3031                                 TEST_DYN_RANGE_VESA ?
3032                                 DP_TEST_PATTERN_COLOR_SQUARES :
3033                                 DP_TEST_PATTERN_COLOR_SQUARES_CEA);
3034         break;
3035         default:
3036                 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
3037         break;
3038         }
3039
3040         if (dpcd_test_params.bits.CLR_FORMAT == 0)
3041                 test_pattern_color_space = DP_TEST_PATTERN_COLOR_SPACE_RGB;
3042         else
3043                 test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ?
3044                                 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 :
3045                                 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601;
3046
3047         switch (dpcd_test_params.bits.BPC) {
3048         case 0: // 6 bits
3049                 requestColorDepth = COLOR_DEPTH_666;
3050                 break;
3051         case 1: // 8 bits
3052                 requestColorDepth = COLOR_DEPTH_888;
3053                 break;
3054         case 2: // 10 bits
3055                 requestColorDepth = COLOR_DEPTH_101010;
3056                 break;
3057         case 3: // 12 bits
3058                 requestColorDepth = COLOR_DEPTH_121212;
3059                 break;
3060         default:
3061                 break;
3062         }
3063
3064         switch (dpcd_test_params.bits.CLR_FORMAT) {
3065         case 0:
3066                 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_RGB;
3067                 break;
3068         case 1:
3069                 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_YCBCR422;
3070                 break;
3071         case 2:
3072                 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_YCBCR444;
3073                 break;
3074         default:
3075                 pipe_ctx->stream->timing.pixel_encoding = PIXEL_ENCODING_RGB;
3076                 break;
3077         }
3078
3079
3080         if (requestColorDepth != COLOR_DEPTH_UNDEFINED
3081                         && pipe_ctx->stream->timing.display_color_depth != requestColorDepth) {
3082                 DC_LOG_DEBUG("%s: original bpc %d, changing to %d\n",
3083                                 __func__,
3084                                 pipe_ctx->stream->timing.display_color_depth,
3085                                 requestColorDepth);
3086                 pipe_ctx->stream->timing.display_color_depth = requestColorDepth;
3087         }
3088
3089         dp_update_dsc_config(pipe_ctx);
3090
3091         dc_link_dp_set_test_pattern(
3092                         link,
3093                         test_pattern,
3094                         test_pattern_color_space,
3095                         NULL,
3096                         NULL,
3097                         0);
3098 }
3099
3100 static void dp_test_get_audio_test_data(struct dc_link *link, bool disable_video)
3101 {
3102         union audio_test_mode            dpcd_test_mode = {0};
3103         struct audio_test_pattern_type   dpcd_pattern_type = {0};
3104         union audio_test_pattern_period  dpcd_pattern_period[AUDIO_CHANNELS_COUNT] = {0};
3105         enum dp_test_pattern test_pattern = DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
3106
3107         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
3108         struct pipe_ctx *pipe_ctx = &pipes[0];
3109         unsigned int channel_count;
3110         unsigned int channel = 0;
3111         unsigned int modes = 0;
3112         unsigned int sampling_rate_in_hz = 0;
3113
3114         // get audio test mode and test pattern parameters
3115         core_link_read_dpcd(
3116                 link,
3117                 DP_TEST_AUDIO_MODE,
3118                 &dpcd_test_mode.raw,
3119                 sizeof(dpcd_test_mode));
3120
3121         core_link_read_dpcd(
3122                 link,
3123                 DP_TEST_AUDIO_PATTERN_TYPE,
3124                 &dpcd_pattern_type.value,
3125                 sizeof(dpcd_pattern_type));
3126
3127         channel_count = dpcd_test_mode.bits.channel_count + 1;
3128
3129         // read pattern periods for requested channels when sawTooth pattern is requested
3130         if (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH ||
3131                         dpcd_pattern_type.value == AUDIO_TEST_PATTERN_OPERATOR_DEFINED) {
3132
3133                 test_pattern = (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH) ?
3134                                 DP_TEST_PATTERN_AUDIO_SAWTOOTH : DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
3135                 // read period for each channel
3136                 for (channel = 0; channel < channel_count; channel++) {
3137                         core_link_read_dpcd(
3138                                                         link,
3139                                                         DP_TEST_AUDIO_PERIOD_CH1 + channel,
3140                                                         &dpcd_pattern_period[channel].raw,
3141                                                         sizeof(dpcd_pattern_period[channel]));
3142                 }
3143         }
3144
3145         // translate sampling rate
3146         switch (dpcd_test_mode.bits.sampling_rate) {
3147         case AUDIO_SAMPLING_RATE_32KHZ:
3148                 sampling_rate_in_hz = 32000;
3149                 break;
3150         case AUDIO_SAMPLING_RATE_44_1KHZ:
3151                 sampling_rate_in_hz = 44100;
3152                 break;
3153         case AUDIO_SAMPLING_RATE_48KHZ:
3154                 sampling_rate_in_hz = 48000;
3155                 break;
3156         case AUDIO_SAMPLING_RATE_88_2KHZ:
3157                 sampling_rate_in_hz = 88200;
3158                 break;
3159         case AUDIO_SAMPLING_RATE_96KHZ:
3160                 sampling_rate_in_hz = 96000;
3161                 break;
3162         case AUDIO_SAMPLING_RATE_176_4KHZ:
3163                 sampling_rate_in_hz = 176400;
3164                 break;
3165         case AUDIO_SAMPLING_RATE_192KHZ:
3166                 sampling_rate_in_hz = 192000;
3167                 break;
3168         default:
3169                 sampling_rate_in_hz = 0;
3170                 break;
3171         }
3172
3173         link->audio_test_data.flags.test_requested = 1;
3174         link->audio_test_data.flags.disable_video = disable_video;
3175         link->audio_test_data.sampling_rate = sampling_rate_in_hz;
3176         link->audio_test_data.channel_count = channel_count;
3177         link->audio_test_data.pattern_type = test_pattern;
3178
3179         if (test_pattern == DP_TEST_PATTERN_AUDIO_SAWTOOTH) {
3180                 for (modes = 0; modes < pipe_ctx->stream->audio_info.mode_count; modes++) {
3181                         link->audio_test_data.pattern_period[modes] = dpcd_pattern_period[modes].bits.pattern_period;
3182                 }
3183         }
3184 }
3185
3186 static void handle_automated_test(struct dc_link *link)
3187 {
3188         union test_request test_request;
3189         union test_response test_response;
3190
3191         memset(&test_request, 0, sizeof(test_request));
3192         memset(&test_response, 0, sizeof(test_response));
3193
3194         core_link_read_dpcd(
3195                 link,
3196                 DP_TEST_REQUEST,
3197                 &test_request.raw,
3198                 sizeof(union test_request));
3199         if (test_request.bits.LINK_TRAINING) {
3200                 /* ACK first to let DP RX test box monitor LT sequence */
3201                 test_response.bits.ACK = 1;
3202                 core_link_write_dpcd(
3203                         link,
3204                         DP_TEST_RESPONSE,
3205                         &test_response.raw,
3206                         sizeof(test_response));
3207                 dp_test_send_link_training(link);
3208                 /* no acknowledge request is needed again */
3209                 test_response.bits.ACK = 0;
3210         }
3211         if (test_request.bits.LINK_TEST_PATTRN) {
3212                 dp_test_send_link_test_pattern(link);
3213                 test_response.bits.ACK = 1;
3214         }
3215
3216         if (test_request.bits.AUDIO_TEST_PATTERN) {
3217                 dp_test_get_audio_test_data(link, test_request.bits.TEST_AUDIO_DISABLED_VIDEO);
3218                 test_response.bits.ACK = 1;
3219         }
3220
3221         if (test_request.bits.PHY_TEST_PATTERN) {
3222                 dp_test_send_phy_test_pattern(link);
3223                 test_response.bits.ACK = 1;
3224         }
3225
3226         /* send request acknowledgment */
3227         if (test_response.bits.ACK)
3228                 core_link_write_dpcd(
3229                         link,
3230                         DP_TEST_RESPONSE,
3231                         &test_response.raw,
3232                         sizeof(test_response));
3233 }
3234
3235 bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd_irq_dpcd_data, bool *out_link_loss)
3236 {
3237         union hpd_irq_data hpd_irq_dpcd_data = { { { {0} } } };
3238         union device_service_irq device_service_clear = { { 0 } };
3239         enum dc_status result;
3240         bool status = false;
3241         struct pipe_ctx *pipe_ctx;
3242         int i;
3243
3244         if (out_link_loss)
3245                 *out_link_loss = false;
3246         /* For use cases related to down stream connection status change,
3247          * PSR and device auto test, refer to function handle_sst_hpd_irq
3248          * in DAL2.1*/
3249
3250         DC_LOG_HW_HPD_IRQ("%s: Got short pulse HPD on link %d\n",
3251                 __func__, link->link_index);
3252
3253
3254          /* All the "handle_hpd_irq_xxx()" methods
3255                  * should be called only after
3256                  * dal_dpsst_ls_read_hpd_irq_data
3257                  * Order of calls is important too
3258                  */
3259         result = read_hpd_rx_irq_data(link, &hpd_irq_dpcd_data);
3260         if (out_hpd_irq_dpcd_data)
3261                 *out_hpd_irq_dpcd_data = hpd_irq_dpcd_data;
3262
3263         if (result != DC_OK) {
3264                 DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain irq data\n",
3265                         __func__);
3266                 return false;
3267         }
3268
3269         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3270                 device_service_clear.bits.AUTOMATED_TEST = 1;
3271                 core_link_write_dpcd(
3272                         link,
3273                         DP_DEVICE_SERVICE_IRQ_VECTOR,
3274                         &device_service_clear.raw,
3275                         sizeof(device_service_clear.raw));
3276                 device_service_clear.raw = 0;
3277                 handle_automated_test(link);
3278                 return false;
3279         }
3280
3281         if (!allow_hpd_rx_irq(link)) {
3282                 DC_LOG_HW_HPD_IRQ("%s: skipping HPD handling on %d\n",
3283                         __func__, link->link_index);
3284                 return false;
3285         }
3286
3287         if (handle_hpd_irq_psr_sink(link))
3288                 /* PSR-related error was detected and handled */
3289                 return true;
3290
3291         /* If PSR-related error handled, Main link may be off,
3292          * so do not handle as a normal sink status change interrupt.
3293          */
3294
3295         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY)
3296                 return true;
3297
3298         /* check if we have MST msg and return since we poll for it */
3299         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY)
3300                 return false;
3301
3302         /* For now we only handle 'Downstream port status' case.
3303          * If we got sink count changed it means
3304          * Downstream port status changed,
3305          * then DM should call DC to do the detection.
3306          * NOTE: Do not handle link loss on eDP since it is internal link*/
3307         if ((link->connector_signal != SIGNAL_TYPE_EDP) &&
3308                 hpd_rx_irq_check_link_loss_status(
3309                         link,
3310                         &hpd_irq_dpcd_data)) {
3311                 /* Connectivity log: link loss */
3312                 CONN_DATA_LINK_LOSS(link,
3313                                         hpd_irq_dpcd_data.raw,
3314                                         sizeof(hpd_irq_dpcd_data),
3315                                         "Status: ");
3316
3317                 for (i = 0; i < MAX_PIPES; i++) {
3318                         pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3319                         if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link)
3320                                 break;
3321                 }
3322
3323                 if (pipe_ctx == NULL || pipe_ctx->stream == NULL)
3324                         return false;
3325
3326
3327                 for (i = 0; i < MAX_PIPES; i++) {
3328                         pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3329                         if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
3330                                         pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe)
3331                                 core_link_disable_stream(pipe_ctx);
3332                 }
3333
3334                 for (i = 0; i < MAX_PIPES; i++) {
3335                         pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
3336                         if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
3337                                         pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe)
3338                                 core_link_enable_stream(link->dc->current_state, pipe_ctx);
3339                 }
3340
3341                 status = false;
3342                 if (out_link_loss)
3343                         *out_link_loss = true;
3344         }
3345
3346         if (link->type == dc_connection_sst_branch &&
3347                 hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT
3348                         != link->dpcd_sink_count)
3349                 status = true;
3350
3351         /* reasons for HPD RX:
3352          * 1. Link Loss - ie Re-train the Link
3353          * 2. MST sideband message
3354          * 3. Automated Test - ie. Internal Commit
3355          * 4. CP (copy protection) - (not interesting for DM???)
3356          * 5. DRR
3357          * 6. Downstream Port status changed
3358          * -ie. Detect - this the only one
3359          * which is interesting for DM because
3360          * it must call dc_link_detect.
3361          */
3362         return status;
3363 }
3364
3365 /*query dpcd for version and mst cap addresses*/
3366 bool is_mst_supported(struct dc_link *link)
3367 {
3368         bool mst          = false;
3369         enum dc_status st = DC_OK;
3370         union dpcd_rev rev;
3371         union mstm_cap cap;
3372
3373         if (link->preferred_training_settings.mst_enable &&
3374                 *link->preferred_training_settings.mst_enable == false) {
3375                 return false;
3376         }
3377
3378         rev.raw  = 0;
3379         cap.raw  = 0;
3380
3381         st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw,
3382                         sizeof(rev));
3383
3384         if (st == DC_OK && rev.raw >= DPCD_REV_12) {
3385
3386                 st = core_link_read_dpcd(link, DP_MSTM_CAP,
3387                                 &cap.raw, sizeof(cap));
3388                 if (st == DC_OK && cap.bits.MST_CAP == 1)
3389                         mst = true;
3390         }
3391         return mst;
3392
3393 }
3394
3395 bool is_dp_active_dongle(const struct dc_link *link)
3396 {
3397         return (link->dpcd_caps.dongle_type >= DISPLAY_DONGLE_DP_VGA_CONVERTER) &&
3398                                 (link->dpcd_caps.dongle_type <= DISPLAY_DONGLE_DP_HDMI_CONVERTER);
3399 }
3400
3401 bool is_dp_branch_device(const struct dc_link *link)
3402 {
3403         return link->dpcd_caps.is_branch_dev;
3404 }
3405
3406 static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)
3407 {
3408         switch (bpc) {
3409         case DOWN_STREAM_MAX_8BPC:
3410                 return 8;
3411         case DOWN_STREAM_MAX_10BPC:
3412                 return 10;
3413         case DOWN_STREAM_MAX_12BPC:
3414                 return 12;
3415         case DOWN_STREAM_MAX_16BPC:
3416                 return 16;
3417         default:
3418                 break;
3419         }
3420
3421         return -1;
3422 }
3423
3424 static void read_dp_device_vendor_id(struct dc_link *link)
3425 {
3426         struct dp_device_vendor_id dp_id;
3427
3428         /* read IEEE branch device id */
3429         core_link_read_dpcd(
3430                 link,
3431                 DP_BRANCH_OUI,
3432                 (uint8_t *)&dp_id,
3433                 sizeof(dp_id));
3434
3435         link->dpcd_caps.branch_dev_id =
3436                 (dp_id.ieee_oui[0] << 16) +
3437                 (dp_id.ieee_oui[1] << 8) +
3438                 dp_id.ieee_oui[2];
3439
3440         memmove(
3441                 link->dpcd_caps.branch_dev_name,
3442                 dp_id.ieee_device_id,
3443                 sizeof(dp_id.ieee_device_id));
3444 }
3445
3446
3447
3448 static void get_active_converter_info(
3449         uint8_t data, struct dc_link *link)
3450 {
3451         union dp_downstream_port_present ds_port = { .byte = data };
3452         memset(&link->dpcd_caps.dongle_caps, 0, sizeof(link->dpcd_caps.dongle_caps));
3453
3454         /* decode converter info*/
3455         if (!ds_port.fields.PORT_PRESENT) {
3456                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3457                 ddc_service_set_dongle_type(link->ddc,
3458                                 link->dpcd_caps.dongle_type);
3459                 link->dpcd_caps.is_branch_dev = false;
3460                 return;
3461         }
3462
3463         /* DPCD 0x5 bit 0 = 1, it indicate it's branch device */
3464         link->dpcd_caps.is_branch_dev = ds_port.fields.PORT_PRESENT;
3465
3466         switch (ds_port.fields.PORT_TYPE) {
3467         case DOWNSTREAM_VGA:
3468                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER;
3469                 break;
3470         case DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS:
3471                 /* At this point we don't know is it DVI or HDMI or DP++,
3472                  * assume DVI.*/
3473                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER;
3474                 break;
3475         default:
3476                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3477                 break;
3478         }
3479
3480         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) {
3481                 uint8_t det_caps[16]; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/
3482                 union dwnstream_port_caps_byte0 *port_caps =
3483                         (union dwnstream_port_caps_byte0 *)det_caps;
3484                 if (core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0,
3485                                 det_caps, sizeof(det_caps)) == DC_OK) {
3486
3487                         switch (port_caps->bits.DWN_STRM_PORTX_TYPE) {
3488                         /*Handle DP case as DONGLE_NONE*/
3489                         case DOWN_STREAM_DETAILED_DP:
3490                                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3491                                 break;
3492                         case DOWN_STREAM_DETAILED_VGA:
3493                                 link->dpcd_caps.dongle_type =
3494                                         DISPLAY_DONGLE_DP_VGA_CONVERTER;
3495                                 break;
3496                         case DOWN_STREAM_DETAILED_DVI:
3497                                 link->dpcd_caps.dongle_type =
3498                                         DISPLAY_DONGLE_DP_DVI_CONVERTER;
3499                                 break;
3500                         case DOWN_STREAM_DETAILED_HDMI:
3501                         case DOWN_STREAM_DETAILED_DP_PLUS_PLUS:
3502                                 /*Handle DP++ active converter case, process DP++ case as HDMI case according DP1.4 spec*/
3503                                 link->dpcd_caps.dongle_type =
3504                                         DISPLAY_DONGLE_DP_HDMI_CONVERTER;
3505
3506                                 link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type;
3507                                 if (ds_port.fields.DETAILED_CAPS) {
3508
3509                                         union dwnstream_port_caps_byte3_hdmi
3510                                                 hdmi_caps = {.raw = det_caps[3] };
3511                                         union dwnstream_port_caps_byte2
3512                                                 hdmi_color_caps = {.raw = det_caps[2] };
3513                                         link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz =
3514                                                 det_caps[1] * 2500;
3515
3516                                         link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter =
3517                                                 hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK;
3518                                         /*YCBCR capability only for HDMI case*/
3519                                         if (port_caps->bits.DWN_STRM_PORTX_TYPE
3520                                                         == DOWN_STREAM_DETAILED_HDMI) {
3521                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through =
3522                                                                 hdmi_caps.bits.YCrCr422_PASS_THROUGH;
3523                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through =
3524                                                                 hdmi_caps.bits.YCrCr420_PASS_THROUGH;
3525                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter =
3526                                                                 hdmi_caps.bits.YCrCr422_CONVERSION;
3527                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter =
3528                                                                 hdmi_caps.bits.YCrCr420_CONVERSION;
3529                                         }
3530
3531                                         link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc =
3532                                                 translate_dpcd_max_bpc(
3533                                                         hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT);
3534
3535                                         if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz != 0)
3536                                                 link->dpcd_caps.dongle_caps.extendedCapValid = true;
3537                                 }
3538
3539                                 break;
3540                         }
3541                 }
3542         }
3543
3544         ddc_service_set_dongle_type(link->ddc, link->dpcd_caps.dongle_type);
3545
3546         {
3547                 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
3548
3549                 core_link_read_dpcd(
3550                         link,
3551                         DP_BRANCH_REVISION_START,
3552                         (uint8_t *)&dp_hw_fw_revision,
3553                         sizeof(dp_hw_fw_revision));
3554
3555                 link->dpcd_caps.branch_hw_revision =
3556                         dp_hw_fw_revision.ieee_hw_rev;
3557
3558                 memmove(
3559                         link->dpcd_caps.branch_fw_revision,
3560                         dp_hw_fw_revision.ieee_fw_rev,
3561                         sizeof(dp_hw_fw_revision.ieee_fw_rev));
3562         }
3563 }
3564
3565 static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
3566                 int length)
3567 {
3568         int retry = 0;
3569
3570         if (!link->dpcd_caps.dpcd_rev.raw) {
3571                 do {
3572                         dp_receiver_power_ctrl(link, true);
3573                         core_link_read_dpcd(link, DP_DPCD_REV,
3574                                                         dpcd_data, length);
3575                         link->dpcd_caps.dpcd_rev.raw = dpcd_data[
3576                                 DP_DPCD_REV -
3577                                 DP_DPCD_REV];
3578                 } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
3579         }
3580
3581         if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
3582                 switch (link->dpcd_caps.branch_dev_id) {
3583                 /* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power down
3584                  * all internal circuits including AUX communication preventing
3585                  * reading DPCD table and EDID (spec violation).
3586                  * Encoder will skip DP RX power down on disable_output to
3587                  * keep receiver powered all the time.*/
3588                 case DP_BRANCH_DEVICE_ID_0010FA:
3589                 case DP_BRANCH_DEVICE_ID_0080E1:
3590                 case DP_BRANCH_DEVICE_ID_00E04C:
3591                         link->wa_flags.dp_keep_receiver_powered = true;
3592                         break;
3593
3594                 /* TODO: May need work around for other dongles. */
3595                 default:
3596                         link->wa_flags.dp_keep_receiver_powered = false;
3597                         break;
3598                 }
3599         } else
3600                 link->wa_flags.dp_keep_receiver_powered = false;
3601 }
3602
3603 /* Read additional sink caps defined in source specific DPCD area
3604  * This function currently only reads from SinkCapability address (DP_SOURCE_SINK_CAP)
3605  */
3606 static bool dpcd_read_sink_ext_caps(struct dc_link *link)
3607 {
3608         uint8_t dpcd_data;
3609
3610         if (!link)
3611                 return false;
3612
3613         if (core_link_read_dpcd(link, DP_SOURCE_SINK_CAP, &dpcd_data, 1) != DC_OK)
3614                 return false;
3615
3616         link->dpcd_sink_ext_caps.raw = dpcd_data;
3617         return true;
3618 }
3619
3620 bool dp_retrieve_lttpr_cap(struct dc_link *link)
3621 {
3622         uint8_t lttpr_dpcd_data[6];
3623         bool vbios_lttpr_enable = link->dc->caps.vbios_lttpr_enable;
3624         bool vbios_lttpr_interop = link->dc->caps.vbios_lttpr_aware;
3625         enum dc_status status = DC_ERROR_UNEXPECTED;
3626         bool is_lttpr_present = false;
3627
3628         memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data));
3629
3630         /*
3631          * Logic to determine LTTPR mode
3632          */
3633         link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
3634         if (vbios_lttpr_enable && vbios_lttpr_interop)
3635                 link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
3636         else if (!vbios_lttpr_enable && vbios_lttpr_interop) {
3637                 if (link->dc->config.allow_lttpr_non_transparent_mode)
3638                         link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
3639                 else
3640                         link->lttpr_mode = LTTPR_MODE_TRANSPARENT;
3641         } else if (!vbios_lttpr_enable && !vbios_lttpr_interop) {
3642                 if (!link->dc->config.allow_lttpr_non_transparent_mode
3643                         || !link->dc->caps.extended_aux_timeout_support)
3644                         link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
3645                 else
3646                         link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT;
3647         }
3648
3649         if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT || link->lttpr_mode == LTTPR_MODE_TRANSPARENT) {
3650                 /* By reading LTTPR capability, RX assumes that we will enable
3651                  * LTTPR extended aux timeout if LTTPR is present.
3652                  */
3653                 status = core_link_read_dpcd(
3654                                 link,
3655                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
3656                                 lttpr_dpcd_data,
3657                                 sizeof(lttpr_dpcd_data));
3658                 if (status != DC_OK) {
3659                         dm_error("%s: Read LTTPR caps data failed.\n", __func__);
3660                         return false;
3661                 }
3662
3663                 link->dpcd_caps.lttpr_caps.revision.raw =
3664                                 lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV -
3665                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3666
3667                 link->dpcd_caps.lttpr_caps.max_link_rate =
3668                                 lttpr_dpcd_data[DP_MAX_LINK_RATE_PHY_REPEATER -
3669                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3670
3671                 link->dpcd_caps.lttpr_caps.phy_repeater_cnt =
3672                                 lttpr_dpcd_data[DP_PHY_REPEATER_CNT -
3673                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3674
3675                 link->dpcd_caps.lttpr_caps.max_lane_count =
3676                                 lttpr_dpcd_data[DP_MAX_LANE_COUNT_PHY_REPEATER -
3677                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3678
3679                 link->dpcd_caps.lttpr_caps.mode =
3680                                 lttpr_dpcd_data[DP_PHY_REPEATER_MODE -
3681                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3682
3683                 link->dpcd_caps.lttpr_caps.max_ext_timeout =
3684                                 lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT -
3685                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3686
3687                 /* Attempt to train in LTTPR transparent mode if repeater count exceeds 8. */
3688                 is_lttpr_present = (dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) != 0 &&
3689                                 link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&
3690                                 link->dpcd_caps.lttpr_caps.max_lane_count <= 4 &&
3691                                 link->dpcd_caps.lttpr_caps.revision.raw >= 0x14);
3692                 if (is_lttpr_present) {
3693                         CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: ");
3694                         configure_lttpr_mode_transparent(link);
3695                 } else
3696                         link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
3697         }
3698         return is_lttpr_present;
3699 }
3700
3701 static bool retrieve_link_cap(struct dc_link *link)
3702 {
3703         /* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16,
3704          * which means size 16 will be good for both of those DPCD register block reads
3705          */
3706         uint8_t dpcd_data[16];
3707         /*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST.
3708          */
3709         uint8_t dpcd_dprx_data = '\0';
3710         uint8_t dpcd_power_state = '\0';
3711
3712         struct dp_device_vendor_id sink_id;
3713         union down_stream_port_count down_strm_port_count;
3714         union edp_configuration_cap edp_config_cap;
3715         union dp_downstream_port_present ds_port = { 0 };
3716         enum dc_status status = DC_ERROR_UNEXPECTED;
3717         uint32_t read_dpcd_retry_cnt = 3;
3718         int i;
3719         struct dp_sink_hw_fw_revision dp_hw_fw_revision;
3720         const uint32_t post_oui_delay = 30; // 30ms
3721         bool is_lttpr_present = false;
3722
3723         memset(dpcd_data, '\0', sizeof(dpcd_data));
3724         memset(&down_strm_port_count,
3725                 '\0', sizeof(union down_stream_port_count));
3726         memset(&edp_config_cap, '\0',
3727                 sizeof(union edp_configuration_cap));
3728
3729         /* if extended timeout is supported in hardware,
3730          * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
3731          * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
3732          */
3733         dc_link_aux_try_to_configure_timeout(link->ddc,
3734                         LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
3735
3736         is_lttpr_present = dp_retrieve_lttpr_cap(link);
3737
3738         status = core_link_read_dpcd(link, DP_SET_POWER,
3739                         &dpcd_power_state, sizeof(dpcd_power_state));
3740
3741         /* Delay 1 ms if AUX CH is in power down state. Based on spec
3742          * section 2.3.1.2, if AUX CH may be powered down due to
3743          * write to DPCD 600h = 2. Sink AUX CH is monitoring differential
3744          * signal and may need up to 1 ms before being able to reply.
3745          */
3746         if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3)
3747                 udelay(1000);
3748
3749         dpcd_set_source_specific_data(link);
3750         /* Sink may need to configure internals based on vendor, so allow some
3751          * time before proceeding with possibly vendor specific transactions
3752          */
3753         msleep(post_oui_delay);
3754
3755         for (i = 0; i < read_dpcd_retry_cnt; i++) {
3756                 status = core_link_read_dpcd(
3757                                 link,
3758                                 DP_DPCD_REV,
3759                                 dpcd_data,
3760                                 sizeof(dpcd_data));
3761                 if (status == DC_OK)
3762                         break;
3763         }
3764
3765         if (status != DC_OK) {
3766                 dm_error("%s: Read receiver caps dpcd data failed.\n", __func__);
3767                 return false;
3768         }
3769
3770         if (!is_lttpr_present)
3771                 dc_link_aux_try_to_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
3772
3773         {
3774                 union training_aux_rd_interval aux_rd_interval;
3775
3776                 aux_rd_interval.raw =
3777                         dpcd_data[DP_TRAINING_AUX_RD_INTERVAL];
3778
3779                 link->dpcd_caps.ext_receiver_cap_field_present =
3780                                 aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1;
3781
3782                 if (aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1) {
3783                         uint8_t ext_cap_data[16];
3784
3785                         memset(ext_cap_data, '\0', sizeof(ext_cap_data));
3786                         for (i = 0; i < read_dpcd_retry_cnt; i++) {
3787                                 status = core_link_read_dpcd(
3788                                 link,
3789                                 DP_DP13_DPCD_REV,
3790                                 ext_cap_data,
3791                                 sizeof(ext_cap_data));
3792                                 if (status == DC_OK) {
3793                                         memcpy(dpcd_data, ext_cap_data, sizeof(dpcd_data));
3794                                         break;
3795                                 }
3796                         }
3797                         if (status != DC_OK)
3798                                 dm_error("%s: Read extend caps data failed, use cap from dpcd 0.\n", __func__);
3799                 }
3800         }
3801
3802         link->dpcd_caps.dpcd_rev.raw =
3803                         dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
3804
3805         if (link->dpcd_caps.ext_receiver_cap_field_present) {
3806                 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3807                         status = core_link_read_dpcd(
3808                                         link,
3809                                         DP_DPRX_FEATURE_ENUMERATION_LIST,
3810                                         &dpcd_dprx_data,
3811                                         sizeof(dpcd_dprx_data));
3812                         if (status == DC_OK)
3813                                 break;
3814                 }
3815
3816                 link->dpcd_caps.dprx_feature.raw = dpcd_dprx_data;
3817
3818                 if (status != DC_OK)
3819                         dm_error("%s: Read DPRX caps data failed.\n", __func__);
3820         }
3821
3822         else {
3823                 link->dpcd_caps.dprx_feature.raw = 0;
3824         }
3825
3826
3827         /* Error condition checking...
3828          * It is impossible for Sink to report Max Lane Count = 0.
3829          * It is possible for Sink to report Max Link Rate = 0, if it is
3830          * an eDP device that is reporting specialized link rates in the
3831          * SUPPORTED_LINK_RATE table.
3832          */
3833         if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
3834                 return false;
3835
3836         ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
3837                                  DP_DPCD_REV];
3838
3839         read_dp_device_vendor_id(link);
3840
3841         get_active_converter_info(ds_port.byte, link);
3842
3843         dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data));
3844
3845         down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
3846                                  DP_DPCD_REV];
3847
3848         link->dpcd_caps.allow_invalid_MSA_timing_param =
3849                 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
3850
3851         link->dpcd_caps.max_ln_count.raw = dpcd_data[
3852                 DP_MAX_LANE_COUNT - DP_DPCD_REV];
3853
3854         link->dpcd_caps.max_down_spread.raw = dpcd_data[
3855                 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
3856
3857         link->reported_link_cap.lane_count =
3858                 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
3859         link->reported_link_cap.link_rate = dpcd_data[
3860                 DP_MAX_LINK_RATE - DP_DPCD_REV];
3861         link->reported_link_cap.link_spread =
3862                 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
3863                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
3864
3865         edp_config_cap.raw = dpcd_data[
3866                 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
3867         link->dpcd_caps.panel_mode_edp =
3868                 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
3869         link->dpcd_caps.dpcd_display_control_capable =
3870                 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
3871
3872         link->test_pattern_enabled = false;
3873         link->compliance_test_state.raw = 0;
3874
3875         /* read sink count */
3876         core_link_read_dpcd(link,
3877                         DP_SINK_COUNT,
3878                         &link->dpcd_caps.sink_count.raw,
3879                         sizeof(link->dpcd_caps.sink_count.raw));
3880
3881         /* read sink ieee oui */
3882         core_link_read_dpcd(link,
3883                         DP_SINK_OUI,
3884                         (uint8_t *)(&sink_id),
3885                         sizeof(sink_id));
3886
3887         link->dpcd_caps.sink_dev_id =
3888                         (sink_id.ieee_oui[0] << 16) +
3889                         (sink_id.ieee_oui[1] << 8) +
3890                         (sink_id.ieee_oui[2]);
3891
3892         memmove(
3893                 link->dpcd_caps.sink_dev_id_str,
3894                 sink_id.ieee_device_id,
3895                 sizeof(sink_id.ieee_device_id));
3896
3897         /* Quirk Apple MBP 2017 15" Retina panel: Wrong DP_MAX_LINK_RATE */
3898         {
3899                 uint8_t str_mbp_2017[] = { 101, 68, 21, 101, 98, 97 };
3900
3901                 if ((link->dpcd_caps.sink_dev_id == 0x0010fa) &&
3902                     !memcmp(link->dpcd_caps.sink_dev_id_str, str_mbp_2017,
3903                             sizeof(str_mbp_2017))) {
3904                         link->reported_link_cap.link_rate = 0x0c;
3905                 }
3906         }
3907
3908         core_link_read_dpcd(
3909                 link,
3910                 DP_SINK_HW_REVISION_START,
3911                 (uint8_t *)&dp_hw_fw_revision,
3912                 sizeof(dp_hw_fw_revision));
3913
3914         link->dpcd_caps.sink_hw_revision =
3915                 dp_hw_fw_revision.ieee_hw_rev;
3916
3917         memmove(
3918                 link->dpcd_caps.sink_fw_revision,
3919                 dp_hw_fw_revision.ieee_fw_rev,
3920                 sizeof(dp_hw_fw_revision.ieee_fw_rev));
3921
3922         memset(&link->dpcd_caps.dsc_caps, '\0',
3923                         sizeof(link->dpcd_caps.dsc_caps));
3924         memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));
3925         /* Read DSC and FEC sink capabilities if DP revision is 1.4 and up */
3926         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14) {
3927                 status = core_link_read_dpcd(
3928                                 link,
3929                                 DP_FEC_CAPABILITY,
3930                                 &link->dpcd_caps.fec_cap.raw,
3931                                 sizeof(link->dpcd_caps.fec_cap.raw));
3932                 status = core_link_read_dpcd(
3933                                 link,
3934                                 DP_DSC_SUPPORT,
3935                                 link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
3936                                 sizeof(link->dpcd_caps.dsc_caps.dsc_basic_caps.raw));
3937                 status = core_link_read_dpcd(
3938                                 link,
3939                                 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0,
3940                                 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
3941                                 sizeof(link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw));
3942         }
3943
3944         if (!dpcd_read_sink_ext_caps(link))
3945                 link->dpcd_sink_ext_caps.raw = 0;
3946
3947         /* Connectivity log: detection */
3948         CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
3949
3950         return true;
3951 }
3952
3953 bool dp_overwrite_extended_receiver_cap(struct dc_link *link)
3954 {
3955         uint8_t dpcd_data[16];
3956         uint32_t read_dpcd_retry_cnt = 3;
3957         enum dc_status status = DC_ERROR_UNEXPECTED;
3958         union dp_downstream_port_present ds_port = { 0 };
3959         union down_stream_port_count down_strm_port_count;
3960         union edp_configuration_cap edp_config_cap;
3961
3962         int i;
3963
3964         for (i = 0; i < read_dpcd_retry_cnt; i++) {
3965                 status = core_link_read_dpcd(
3966                                 link,
3967                                 DP_DPCD_REV,
3968                                 dpcd_data,
3969                                 sizeof(dpcd_data));
3970                 if (status == DC_OK)
3971                         break;
3972         }
3973
3974         link->dpcd_caps.dpcd_rev.raw =
3975                 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
3976
3977         if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
3978                 return false;
3979
3980         ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
3981                         DP_DPCD_REV];
3982
3983         get_active_converter_info(ds_port.byte, link);
3984
3985         down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
3986                         DP_DPCD_REV];
3987
3988         link->dpcd_caps.allow_invalid_MSA_timing_param =
3989                 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
3990
3991         link->dpcd_caps.max_ln_count.raw = dpcd_data[
3992                 DP_MAX_LANE_COUNT - DP_DPCD_REV];
3993
3994         link->dpcd_caps.max_down_spread.raw = dpcd_data[
3995                 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
3996
3997         link->reported_link_cap.lane_count =
3998                 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
3999         link->reported_link_cap.link_rate = dpcd_data[
4000                 DP_MAX_LINK_RATE - DP_DPCD_REV];
4001         link->reported_link_cap.link_spread =
4002                 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
4003                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
4004
4005         edp_config_cap.raw = dpcd_data[
4006                 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
4007         link->dpcd_caps.panel_mode_edp =
4008                 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
4009         link->dpcd_caps.dpcd_display_control_capable =
4010                 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
4011
4012         return true;
4013 }
4014
4015 bool detect_dp_sink_caps(struct dc_link *link)
4016 {
4017         return retrieve_link_cap(link);
4018
4019         /* dc init_hw has power encoder using default
4020          * signal for connector. For native DP, no
4021          * need to power up encoder again. If not native
4022          * DP, hw_init may need check signal or power up
4023          * encoder here.
4024          */
4025         /* TODO save sink caps in link->sink */
4026 }
4027
4028 static enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz)
4029 {
4030         enum dc_link_rate link_rate;
4031         // LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation.
4032         switch (link_rate_in_khz) {
4033         case 1620000:
4034                 link_rate = LINK_RATE_LOW;              // Rate_1 (RBR)         - 1.62 Gbps/Lane
4035                 break;
4036         case 2160000:
4037                 link_rate = LINK_RATE_RATE_2;   // Rate_2                       - 2.16 Gbps/Lane
4038                 break;
4039         case 2430000:
4040                 link_rate = LINK_RATE_RATE_3;   // Rate_3                       - 2.43 Gbps/Lane
4041                 break;
4042         case 2700000:
4043                 link_rate = LINK_RATE_HIGH;             // Rate_4 (HBR)         - 2.70 Gbps/Lane
4044                 break;
4045         case 3240000:
4046                 link_rate = LINK_RATE_RBR2;             // Rate_5 (RBR2)        - 3.24 Gbps/Lane
4047                 break;
4048         case 4320000:
4049                 link_rate = LINK_RATE_RATE_6;   // Rate_6                       - 4.32 Gbps/Lane
4050                 break;
4051         case 5400000:
4052                 link_rate = LINK_RATE_HIGH2;    // Rate_7 (HBR2)        - 5.40 Gbps/Lane
4053                 break;
4054         case 8100000:
4055                 link_rate = LINK_RATE_HIGH3;    // Rate_8 (HBR3)        - 8.10 Gbps/Lane
4056                 break;
4057         default:
4058                 link_rate = LINK_RATE_UNKNOWN;
4059                 break;
4060         }
4061         return link_rate;
4062 }
4063
4064 void detect_edp_sink_caps(struct dc_link *link)
4065 {
4066         uint8_t supported_link_rates[16];
4067         uint32_t entry;
4068         uint32_t link_rate_in_khz;
4069         enum dc_link_rate link_rate = LINK_RATE_UNKNOWN;
4070         uint8_t backlight_adj_cap;
4071
4072         retrieve_link_cap(link);
4073         link->dpcd_caps.edp_supported_link_rates_count = 0;
4074         memset(supported_link_rates, 0, sizeof(supported_link_rates));
4075
4076         /*
4077          * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
4078          * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
4079          */
4080         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_13 &&
4081                         (link->dc->debug.optimize_edp_link_rate ||
4082                         link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)) {
4083                 // Read DPCD 00010h - 0001Fh 16 bytes at one shot
4084                 core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
4085                                                         supported_link_rates, sizeof(supported_link_rates));
4086
4087                 for (entry = 0; entry < 16; entry += 2) {
4088                         // DPCD register reports per-lane link rate = 16-bit link rate capability
4089                         // value X 200 kHz. Need multiplier to find link rate in kHz.
4090                         link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
4091                                                                                 supported_link_rates[entry]) * 200;
4092
4093                         if (link_rate_in_khz != 0) {
4094                                 link_rate = linkRateInKHzToLinkRateMultiplier(link_rate_in_khz);
4095                                 link->dpcd_caps.edp_supported_link_rates[link->dpcd_caps.edp_supported_link_rates_count] = link_rate;
4096                                 link->dpcd_caps.edp_supported_link_rates_count++;
4097
4098                                 if (link->reported_link_cap.link_rate < link_rate)
4099                                         link->reported_link_cap.link_rate = link_rate;
4100                         }
4101                 }
4102         }
4103         link->verified_link_cap = link->reported_link_cap;
4104
4105         core_link_read_dpcd(link, DP_EDP_BACKLIGHT_ADJUSTMENT_CAP,
4106                                                 &backlight_adj_cap, sizeof(backlight_adj_cap));
4107
4108         link->dpcd_caps.dynamic_backlight_capable_edp =
4109                                 (backlight_adj_cap & DP_EDP_DYNAMIC_BACKLIGHT_CAP) ? true:false;
4110
4111         dc_link_set_default_brightness_aux(link);
4112 }
4113
4114 void dc_link_dp_enable_hpd(const struct dc_link *link)
4115 {
4116         struct link_encoder *encoder = link->link_enc;
4117
4118         if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
4119                 encoder->funcs->enable_hpd(encoder);
4120 }
4121
4122 void dc_link_dp_disable_hpd(const struct dc_link *link)
4123 {
4124         struct link_encoder *encoder = link->link_enc;
4125
4126         if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
4127                 encoder->funcs->disable_hpd(encoder);
4128 }
4129
4130 static bool is_dp_phy_pattern(enum dp_test_pattern test_pattern)
4131 {
4132         if ((DP_TEST_PATTERN_PHY_PATTERN_BEGIN <= test_pattern &&
4133                         test_pattern <= DP_TEST_PATTERN_PHY_PATTERN_END) ||
4134                         test_pattern == DP_TEST_PATTERN_VIDEO_MODE)
4135                 return true;
4136         else
4137                 return false;
4138 }
4139
4140 static void set_crtc_test_pattern(struct dc_link *link,
4141                                 struct pipe_ctx *pipe_ctx,
4142                                 enum dp_test_pattern test_pattern,
4143                                 enum dp_test_pattern_color_space test_pattern_color_space)
4144 {
4145         enum controller_dp_test_pattern controller_test_pattern;
4146         enum dc_color_depth color_depth = pipe_ctx->
4147                 stream->timing.display_color_depth;
4148         struct bit_depth_reduction_params params;
4149         struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;
4150         int width = pipe_ctx->stream->timing.h_addressable +
4151                 pipe_ctx->stream->timing.h_border_left +
4152                 pipe_ctx->stream->timing.h_border_right;
4153         int height = pipe_ctx->stream->timing.v_addressable +
4154                 pipe_ctx->stream->timing.v_border_bottom +
4155                 pipe_ctx->stream->timing.v_border_top;
4156
4157         memset(&params, 0, sizeof(params));
4158
4159         switch (test_pattern) {
4160         case DP_TEST_PATTERN_COLOR_SQUARES:
4161                 controller_test_pattern =
4162                                 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
4163         break;
4164         case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
4165                 controller_test_pattern =
4166                                 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA;
4167         break;
4168         case DP_TEST_PATTERN_VERTICAL_BARS:
4169                 controller_test_pattern =
4170                                 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS;
4171         break;
4172         case DP_TEST_PATTERN_HORIZONTAL_BARS:
4173                 controller_test_pattern =
4174                                 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS;
4175         break;
4176         case DP_TEST_PATTERN_COLOR_RAMP:
4177                 controller_test_pattern =
4178                                 CONTROLLER_DP_TEST_PATTERN_COLORRAMP;
4179         break;
4180         default:
4181                 controller_test_pattern =
4182                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
4183         break;
4184         }
4185
4186         switch (test_pattern) {
4187         case DP_TEST_PATTERN_COLOR_SQUARES:
4188         case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
4189         case DP_TEST_PATTERN_VERTICAL_BARS:
4190         case DP_TEST_PATTERN_HORIZONTAL_BARS:
4191         case DP_TEST_PATTERN_COLOR_RAMP:
4192         {
4193                 /* disable bit depth reduction */
4194                 pipe_ctx->stream->bit_depth_params = params;
4195                 opp->funcs->opp_program_bit_depth_reduction(opp, &params);
4196                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
4197                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4198                                 controller_test_pattern, color_depth);
4199                 else if (link->dc->hwss.set_disp_pattern_generator) {
4200                         struct pipe_ctx *odm_pipe;
4201                         enum controller_dp_color_space controller_color_space;
4202                         int opp_cnt = 1;
4203                         int offset = 0;
4204                         int dpg_width = width;
4205
4206                         switch (test_pattern_color_space) {
4207                         case DP_TEST_PATTERN_COLOR_SPACE_RGB:
4208                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
4209                                 break;
4210                         case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
4211                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR601;
4212                                 break;
4213                         case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
4214                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR709;
4215                                 break;
4216                         case DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED:
4217                         default:
4218                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
4219                                 DC_LOG_ERROR("%s: Color space must be defined for test pattern", __func__);
4220                                 ASSERT(0);
4221                                 break;
4222                         }
4223
4224                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
4225                                 opp_cnt++;
4226                         dpg_width = width / opp_cnt;
4227                         offset = dpg_width;
4228
4229                         link->dc->hwss.set_disp_pattern_generator(link->dc,
4230                                         pipe_ctx,
4231                                         controller_test_pattern,
4232                                         controller_color_space,
4233                                         color_depth,
4234                                         NULL,
4235                                         dpg_width,
4236                                         height,
4237                                         0);
4238
4239                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
4240                                 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
4241
4242                                 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
4243                                 link->dc->hwss.set_disp_pattern_generator(link->dc,
4244                                                 odm_pipe,
4245                                                 controller_test_pattern,
4246                                                 controller_color_space,
4247                                                 color_depth,
4248                                                 NULL,
4249                                                 dpg_width,
4250                                                 height,
4251                                                 offset);
4252                                 offset += offset;
4253                         }
4254                 }
4255         }
4256         break;
4257         case DP_TEST_PATTERN_VIDEO_MODE:
4258         {
4259                 /* restore bitdepth reduction */
4260                 resource_build_bit_depth_reduction_params(pipe_ctx->stream, &params);
4261                 pipe_ctx->stream->bit_depth_params = params;
4262                 opp->funcs->opp_program_bit_depth_reduction(opp, &params);
4263                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
4264                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4265                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4266                                 color_depth);
4267                 else if (link->dc->hwss.set_disp_pattern_generator) {
4268                         struct pipe_ctx *odm_pipe;
4269                         int opp_cnt = 1;
4270                         int dpg_width = width;
4271
4272                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
4273                                 opp_cnt++;
4274
4275                         dpg_width = width / opp_cnt;
4276                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
4277                                 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
4278
4279                                 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
4280                                 link->dc->hwss.set_disp_pattern_generator(link->dc,
4281                                                 odm_pipe,
4282                                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4283                                                 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
4284                                                 color_depth,
4285                                                 NULL,
4286                                                 dpg_width,
4287                                                 height,
4288                                                 0);
4289                         }
4290                         link->dc->hwss.set_disp_pattern_generator(link->dc,
4291                                         pipe_ctx,
4292                                         CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4293                                         CONTROLLER_DP_COLOR_SPACE_UDEFINED,
4294                                         color_depth,
4295                                         NULL,
4296                                         dpg_width,
4297                                         height,
4298                                         0);
4299                 }
4300         }
4301         break;
4302
4303         default:
4304         break;
4305         }
4306 }
4307
4308 bool dc_link_dp_set_test_pattern(
4309         struct dc_link *link,
4310         enum dp_test_pattern test_pattern,
4311         enum dp_test_pattern_color_space test_pattern_color_space,
4312         const struct link_training_settings *p_link_settings,
4313         const unsigned char *p_custom_pattern,
4314         unsigned int cust_pattern_size)
4315 {
4316         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
4317         struct pipe_ctx *pipe_ctx = NULL;
4318         unsigned int lane;
4319         unsigned int i;
4320         unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0};
4321         union dpcd_training_pattern training_pattern;
4322         enum dpcd_phy_test_patterns pattern;
4323
4324         memset(&training_pattern, 0, sizeof(training_pattern));
4325
4326         for (i = 0; i < MAX_PIPES; i++) {
4327                 if (pipes[i].stream == NULL)
4328                         continue;
4329
4330                 if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
4331                         pipe_ctx = &pipes[i];
4332                         break;
4333                 }
4334         }
4335
4336         if (pipe_ctx == NULL)
4337                 return false;
4338
4339         /* Reset CRTC Test Pattern if it is currently running and request is VideoMode */
4340         if (link->test_pattern_enabled && test_pattern ==
4341                         DP_TEST_PATTERN_VIDEO_MODE) {
4342                 /* Set CRTC Test Pattern */
4343                 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
4344                 dp_set_hw_test_pattern(link, test_pattern,
4345                                 (uint8_t *)p_custom_pattern,
4346                                 (uint32_t)cust_pattern_size);
4347
4348                 /* Unblank Stream */
4349                 link->dc->hwss.unblank_stream(
4350                         pipe_ctx,
4351                         &link->verified_link_cap);
4352                 /* TODO:m_pHwss->MuteAudioEndpoint
4353                  * (pPathMode->pDisplayPath, false);
4354                  */
4355
4356                 /* Reset Test Pattern state */
4357                 link->test_pattern_enabled = false;
4358
4359                 return true;
4360         }
4361
4362         /* Check for PHY Test Patterns */
4363         if (is_dp_phy_pattern(test_pattern)) {
4364                 /* Set DPCD Lane Settings before running test pattern */
4365                 if (p_link_settings != NULL) {
4366                         dp_set_hw_lane_settings(link, p_link_settings, DPRX);
4367                         dpcd_set_lane_settings(link, p_link_settings, DPRX);
4368                 }
4369
4370                 /* Blank stream if running test pattern */
4371                 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
4372                         /*TODO:
4373                          * m_pHwss->
4374                          * MuteAudioEndpoint(pPathMode->pDisplayPath, true);
4375                          */
4376                         /* Blank stream */
4377                         pipes->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
4378                 }
4379
4380                 dp_set_hw_test_pattern(link, test_pattern,
4381                                 (uint8_t *)p_custom_pattern,
4382                                 (uint32_t)cust_pattern_size);
4383
4384                 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
4385                         /* Set Test Pattern state */
4386                         link->test_pattern_enabled = true;
4387                         if (p_link_settings != NULL)
4388                                 dpcd_set_link_settings(link,
4389                                                 p_link_settings);
4390                 }
4391
4392                 switch (test_pattern) {
4393                 case DP_TEST_PATTERN_VIDEO_MODE:
4394                         pattern = PHY_TEST_PATTERN_NONE;
4395                         break;
4396                 case DP_TEST_PATTERN_D102:
4397                         pattern = PHY_TEST_PATTERN_D10_2;
4398                         break;
4399                 case DP_TEST_PATTERN_SYMBOL_ERROR:
4400                         pattern = PHY_TEST_PATTERN_SYMBOL_ERROR;
4401                         break;
4402                 case DP_TEST_PATTERN_PRBS7:
4403                         pattern = PHY_TEST_PATTERN_PRBS7;
4404                         break;
4405                 case DP_TEST_PATTERN_80BIT_CUSTOM:
4406                         pattern = PHY_TEST_PATTERN_80BIT_CUSTOM;
4407                         break;
4408                 case DP_TEST_PATTERN_CP2520_1:
4409                         pattern = PHY_TEST_PATTERN_CP2520_1;
4410                         break;
4411                 case DP_TEST_PATTERN_CP2520_2:
4412                         pattern = PHY_TEST_PATTERN_CP2520_2;
4413                         break;
4414                 case DP_TEST_PATTERN_CP2520_3:
4415                         pattern = PHY_TEST_PATTERN_CP2520_3;
4416                         break;
4417                 default:
4418                         return false;
4419                 }
4420
4421                 if (test_pattern == DP_TEST_PATTERN_VIDEO_MODE
4422                 /*TODO:&& !pPathMode->pDisplayPath->IsTargetPoweredOn()*/)
4423                         return false;
4424
4425                 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
4426                         /* tell receiver that we are sending qualification
4427                          * pattern DP 1.2 or later - DP receiver's link quality
4428                          * pattern is set using DPCD LINK_QUAL_LANEx_SET
4429                          * register (0x10B~0x10E)\
4430                          */
4431                         for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++)
4432                                 link_qual_pattern[lane] =
4433                                                 (unsigned char)(pattern);
4434
4435                         core_link_write_dpcd(link,
4436                                         DP_LINK_QUAL_LANE0_SET,
4437                                         link_qual_pattern,
4438                                         sizeof(link_qual_pattern));
4439                 } else if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_10 ||
4440                            link->dpcd_caps.dpcd_rev.raw == 0) {
4441                         /* tell receiver that we are sending qualification
4442                          * pattern DP 1.1a or earlier - DP receiver's link
4443                          * quality pattern is set using
4444                          * DPCD TRAINING_PATTERN_SET -> LINK_QUAL_PATTERN_SET
4445                          * register (0x102). We will use v_1.3 when we are
4446                          * setting test pattern for DP 1.1.
4447                          */
4448                         core_link_read_dpcd(link, DP_TRAINING_PATTERN_SET,
4449                                             &training_pattern.raw,
4450                                             sizeof(training_pattern));
4451                         training_pattern.v1_3.LINK_QUAL_PATTERN_SET = pattern;
4452                         core_link_write_dpcd(link, DP_TRAINING_PATTERN_SET,
4453                                              &training_pattern.raw,
4454                                              sizeof(training_pattern));
4455                 }
4456         } else {
4457                 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
4458
4459                 switch (test_pattern_color_space) {
4460                 case DP_TEST_PATTERN_COLOR_SPACE_RGB:
4461                         color_space = COLOR_SPACE_SRGB;
4462                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4463                                 color_space = COLOR_SPACE_SRGB_LIMITED;
4464                         break;
4465
4466                 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
4467                         color_space = COLOR_SPACE_YCBCR601;
4468                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4469                                 color_space = COLOR_SPACE_YCBCR601_LIMITED;
4470                         break;
4471                 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
4472                         color_space = COLOR_SPACE_YCBCR709;
4473                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4474                                 color_space = COLOR_SPACE_YCBCR709_LIMITED;
4475                         break;
4476                 default:
4477                         break;
4478                 }
4479
4480                 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable) {
4481                         if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) {
4482                                 union dmub_hw_lock_flags hw_locks = { 0 };
4483                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
4484
4485                                 hw_locks.bits.lock_dig = 1;
4486                                 inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;
4487
4488                                 dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,
4489                                                         true,
4490                                                         &hw_locks,
4491                                                         &inst_flags);
4492                         } else
4493                                 pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable(
4494                                                 pipe_ctx->stream_res.tg);
4495                 }
4496
4497                 pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
4498                 /* update MSA to requested color space */
4499                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(pipe_ctx->stream_res.stream_enc,
4500                                 &pipe_ctx->stream->timing,
4501                                 color_space,
4502                                 pipe_ctx->stream->use_vsc_sdp_for_colorimetry,
4503                                 link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
4504
4505                 if (pipe_ctx->stream->use_vsc_sdp_for_colorimetry) {
4506                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4507                                 pipe_ctx->stream->vsc_infopacket.sb[17] |= (1 << 7); // sb17 bit 7 Dynamic Range: 0 = VESA range, 1 = CTA range
4508                         else
4509                                 pipe_ctx->stream->vsc_infopacket.sb[17] &= ~(1 << 7);
4510                         resource_build_info_frame(pipe_ctx);
4511                         link->dc->hwss.update_info_frame(pipe_ctx);
4512                 }
4513
4514                 /* CRTC Patterns */
4515                 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
4516                 pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg);
4517                 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4518                                 CRTC_STATE_VACTIVE);
4519                 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4520                                 CRTC_STATE_VBLANK);
4521                 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4522                                 CRTC_STATE_VACTIVE);
4523
4524                 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable) {
4525                         if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) {
4526                                 union dmub_hw_lock_flags hw_locks = { 0 };
4527                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
4528
4529                                 hw_locks.bits.lock_dig = 1;
4530                                 inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;
4531
4532                                 dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,
4533                                                         false,
4534                                                         &hw_locks,
4535                                                         &inst_flags);
4536                         } else
4537                                 pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable(
4538                                                 pipe_ctx->stream_res.tg);
4539                 }
4540
4541                 /* Set Test Pattern state */
4542                 link->test_pattern_enabled = true;
4543         }
4544
4545         return true;
4546 }
4547
4548 void dp_enable_mst_on_sink(struct dc_link *link, bool enable)
4549 {
4550         unsigned char mstmCntl;
4551
4552         core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
4553         if (enable)
4554                 mstmCntl |= DP_MST_EN;
4555         else
4556                 mstmCntl &= (~DP_MST_EN);
4557
4558         core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
4559 }
4560
4561 void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode)
4562 {
4563         union dpcd_edp_config edp_config_set;
4564         bool panel_mode_edp = false;
4565
4566         memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
4567
4568         if (panel_mode != DP_PANEL_MODE_DEFAULT) {
4569
4570                 switch (panel_mode) {
4571                 case DP_PANEL_MODE_EDP:
4572                 case DP_PANEL_MODE_SPECIAL:
4573                         panel_mode_edp = true;
4574                         break;
4575
4576                 default:
4577                                 break;
4578                 }
4579
4580                 /*set edp panel mode in receiver*/
4581                 core_link_read_dpcd(
4582                         link,
4583                         DP_EDP_CONFIGURATION_SET,
4584                         &edp_config_set.raw,
4585                         sizeof(edp_config_set.raw));
4586
4587                 if (edp_config_set.bits.PANEL_MODE_EDP
4588                         != panel_mode_edp) {
4589                         enum dc_status result;
4590
4591                         edp_config_set.bits.PANEL_MODE_EDP =
4592                         panel_mode_edp;
4593                         result = core_link_write_dpcd(
4594                                 link,
4595                                 DP_EDP_CONFIGURATION_SET,
4596                                 &edp_config_set.raw,
4597                                 sizeof(edp_config_set.raw));
4598
4599                         ASSERT(result == DC_OK);
4600                 }
4601         }
4602         DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d "
4603                  "eDP panel mode enabled: %d \n",
4604                  link->link_index,
4605                  link->dpcd_caps.panel_mode_edp,
4606                  panel_mode_edp);
4607 }
4608
4609 enum dp_panel_mode dp_get_panel_mode(struct dc_link *link)
4610 {
4611         /* We need to explicitly check that connector
4612          * is not DP. Some Travis_VGA get reported
4613          * by video bios as DP.
4614          */
4615         if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) {
4616
4617                 switch (link->dpcd_caps.branch_dev_id) {
4618                 case DP_BRANCH_DEVICE_ID_0022B9:
4619                         /* alternate scrambler reset is required for Travis
4620                          * for the case when external chip does not
4621                          * provide sink device id, alternate scrambler
4622                          * scheme will  be overriden later by querying
4623                          * Encoder features
4624                          */
4625                         if (strncmp(
4626                                 link->dpcd_caps.branch_dev_name,
4627                                 DP_VGA_LVDS_CONVERTER_ID_2,
4628                                 sizeof(
4629                                 link->dpcd_caps.
4630                                 branch_dev_name)) == 0) {
4631                                         return DP_PANEL_MODE_SPECIAL;
4632                         }
4633                         break;
4634                 case DP_BRANCH_DEVICE_ID_00001A:
4635                         /* alternate scrambler reset is required for Travis
4636                          * for the case when external chip does not provide
4637                          * sink device id, alternate scrambler scheme will
4638                          * be overriden later by querying Encoder feature
4639                          */
4640                         if (strncmp(link->dpcd_caps.branch_dev_name,
4641                                 DP_VGA_LVDS_CONVERTER_ID_3,
4642                                 sizeof(
4643                                 link->dpcd_caps.
4644                                 branch_dev_name)) == 0) {
4645                                         return DP_PANEL_MODE_SPECIAL;
4646                         }
4647                         break;
4648                 default:
4649                         break;
4650                 }
4651         }
4652
4653         if (link->dpcd_caps.panel_mode_edp &&
4654                 (link->connector_signal == SIGNAL_TYPE_EDP ||
4655                  (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
4656                   link->is_internal_display))) {
4657                 return DP_PANEL_MODE_EDP;
4658         }
4659
4660         return DP_PANEL_MODE_DEFAULT;
4661 }
4662
4663 enum dc_status dp_set_fec_ready(struct dc_link *link, bool ready)
4664 {
4665         /* FEC has to be "set ready" before the link training.
4666          * The policy is to always train with FEC
4667          * if the sink supports it and leave it enabled on link.
4668          * If FEC is not supported, disable it.
4669          */
4670         struct link_encoder *link_enc = NULL;
4671         enum dc_status status = DC_OK;
4672         uint8_t fec_config = 0;
4673
4674         /* Access link encoder based on whether it is statically
4675          * or dynamically assigned to a link.
4676          */
4677         if (link->is_dig_mapping_flexible &&
4678                         link->dc->res_pool->funcs->link_encs_assign)
4679                 link_enc = link_enc_cfg_get_link_enc_used_by_link(link->dc->current_state, link);
4680         else
4681                 link_enc = link->link_enc;
4682         ASSERT(link_enc);
4683
4684         if (!dc_link_should_enable_fec(link))
4685                 return status;
4686
4687         if (link_enc->funcs->fec_set_ready &&
4688                         link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
4689                 if (ready) {
4690                         fec_config = 1;
4691                         status = core_link_write_dpcd(link,
4692                                         DP_FEC_CONFIGURATION,
4693                                         &fec_config,
4694                                         sizeof(fec_config));
4695                         if (status == DC_OK) {
4696                                 link_enc->funcs->fec_set_ready(link_enc, true);
4697                                 link->fec_state = dc_link_fec_ready;
4698                         } else {
4699                                 link_enc->funcs->fec_set_ready(link->link_enc, false);
4700                                 link->fec_state = dc_link_fec_not_ready;
4701                                 dm_error("dpcd write failed to set fec_ready");
4702                         }
4703                 } else if (link->fec_state == dc_link_fec_ready) {
4704                         fec_config = 0;
4705                         status = core_link_write_dpcd(link,
4706                                         DP_FEC_CONFIGURATION,
4707                                         &fec_config,
4708                                         sizeof(fec_config));
4709                         link_enc->funcs->fec_set_ready(link_enc, false);
4710                         link->fec_state = dc_link_fec_not_ready;
4711                 }
4712         }
4713
4714         return status;
4715 }
4716
4717 void dp_set_fec_enable(struct dc_link *link, bool enable)
4718 {
4719         struct link_encoder *link_enc = NULL;
4720
4721         /* Access link encoder based on whether it is statically
4722          * or dynamically assigned to a link.
4723          */
4724         if (link->is_dig_mapping_flexible &&
4725                         link->dc->res_pool->funcs->link_encs_assign)
4726                 link_enc = link_enc_cfg_get_link_enc_used_by_link(
4727                                 link->dc->current_state, link);
4728         else
4729                 link_enc = link->link_enc;
4730         ASSERT(link_enc);
4731
4732         if (!dc_link_should_enable_fec(link))
4733                 return;
4734
4735         if (link_enc->funcs->fec_set_enable &&
4736                         link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
4737                 if (link->fec_state == dc_link_fec_ready && enable) {
4738                         /* Accord to DP spec, FEC enable sequence can first
4739                          * be transmitted anytime after 1000 LL codes have
4740                          * been transmitted on the link after link training
4741                          * completion. Using 1 lane RBR should have the maximum
4742                          * time for transmitting 1000 LL codes which is 6.173 us.
4743                          * So use 7 microseconds delay instead.
4744                          */
4745                         udelay(7);
4746                         link_enc->funcs->fec_set_enable(link_enc, true);
4747                         link->fec_state = dc_link_fec_enabled;
4748                 } else if (link->fec_state == dc_link_fec_enabled && !enable) {
4749                         link_enc->funcs->fec_set_enable(link_enc, false);
4750                         link->fec_state = dc_link_fec_ready;
4751                 }
4752         }
4753 }
4754
4755 void dpcd_set_source_specific_data(struct dc_link *link)
4756 {
4757         if (!link->dc->vendor_signature.is_valid) {
4758                 enum dc_status __maybe_unused result_write_min_hblank = DC_NOT_SUPPORTED;
4759                 struct dpcd_amd_signature amd_signature = {0};
4760                 struct dpcd_amd_device_id amd_device_id = {0};
4761
4762                 amd_device_id.device_id_byte1 =
4763                                 (uint8_t)(link->ctx->asic_id.chip_id);
4764                 amd_device_id.device_id_byte2 =
4765                                 (uint8_t)(link->ctx->asic_id.chip_id >> 8);
4766                 amd_device_id.dce_version =
4767                                 (uint8_t)(link->ctx->dce_version);
4768                 amd_device_id.dal_version_byte1 = 0x0; // needed? where to get?
4769                 amd_device_id.dal_version_byte2 = 0x0; // needed? where to get?
4770
4771                 core_link_read_dpcd(link, DP_SOURCE_OUI,
4772                                 (uint8_t *)(&amd_signature),
4773                                 sizeof(amd_signature));
4774
4775                 if (!((amd_signature.AMD_IEEE_TxSignature_byte1 == 0x0) &&
4776                         (amd_signature.AMD_IEEE_TxSignature_byte2 == 0x0) &&
4777                         (amd_signature.AMD_IEEE_TxSignature_byte3 == 0x1A))) {
4778
4779                         amd_signature.AMD_IEEE_TxSignature_byte1 = 0x0;
4780                         amd_signature.AMD_IEEE_TxSignature_byte2 = 0x0;
4781                         amd_signature.AMD_IEEE_TxSignature_byte3 = 0x1A;
4782
4783                         core_link_write_dpcd(link, DP_SOURCE_OUI,
4784                                 (uint8_t *)(&amd_signature),
4785                                 sizeof(amd_signature));
4786                 }
4787
4788                 core_link_write_dpcd(link, DP_SOURCE_OUI+0x03,
4789                                 (uint8_t *)(&amd_device_id),
4790                                 sizeof(amd_device_id));
4791
4792                 if (link->ctx->dce_version >= DCN_VERSION_2_0 &&
4793                         link->dc->caps.min_horizontal_blanking_period != 0) {
4794
4795                         uint8_t hblank_size = (uint8_t)link->dc->caps.min_horizontal_blanking_period;
4796
4797                         if (link->preferred_link_setting.dpcd_source_device_specific_field_support) {
4798                                 result_write_min_hblank = core_link_write_dpcd(link,
4799                                         DP_SOURCE_MINIMUM_HBLANK_SUPPORTED, (uint8_t *)(&hblank_size),
4800                                         sizeof(hblank_size));
4801
4802                                 if (result_write_min_hblank == DC_ERROR_UNEXPECTED)
4803                                         link->preferred_link_setting.dpcd_source_device_specific_field_support = false;
4804                         } else {
4805                                 DC_LOG_DC("Sink device does not support 00340h DPCD write. Skipping on purpose.\n");
4806                         }
4807                 }
4808
4809                 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
4810                                                         WPP_BIT_FLAG_DC_DETECTION_DP_CAPS,
4811                                                         "result=%u link_index=%u enum dce_version=%d DPCD=0x%04X min_hblank=%u branch_dev_id=0x%x branch_dev_name='%c%c%c%c%c%c'",
4812                                                         result_write_min_hblank,
4813                                                         link->link_index,
4814                                                         link->ctx->dce_version,
4815                                                         DP_SOURCE_MINIMUM_HBLANK_SUPPORTED,
4816                                                         link->dc->caps.min_horizontal_blanking_period,
4817                                                         link->dpcd_caps.branch_dev_id,
4818                                                         link->dpcd_caps.branch_dev_name[0],
4819                                                         link->dpcd_caps.branch_dev_name[1],
4820                                                         link->dpcd_caps.branch_dev_name[2],
4821                                                         link->dpcd_caps.branch_dev_name[3],
4822                                                         link->dpcd_caps.branch_dev_name[4],
4823                                                         link->dpcd_caps.branch_dev_name[5]);
4824         } else {
4825                 core_link_write_dpcd(link, DP_SOURCE_OUI,
4826                                 link->dc->vendor_signature.data.raw,
4827                                 sizeof(link->dc->vendor_signature.data.raw));
4828         }
4829 }
4830
4831 bool dc_link_set_backlight_level_nits(struct dc_link *link,
4832                 bool isHDR,
4833                 uint32_t backlight_millinits,
4834                 uint32_t transition_time_in_ms)
4835 {
4836         struct dpcd_source_backlight_set dpcd_backlight_set;
4837         uint8_t backlight_control = isHDR ? 1 : 0;
4838
4839         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4840                         link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4841                 return false;
4842
4843         // OLEDs have no PWM, they can only use AUX
4844         if (link->dpcd_sink_ext_caps.bits.oled == 1)
4845                 backlight_control = 1;
4846
4847         *(uint32_t *)&dpcd_backlight_set.backlight_level_millinits = backlight_millinits;
4848         *(uint16_t *)&dpcd_backlight_set.backlight_transition_time_ms = (uint16_t)transition_time_in_ms;
4849
4850
4851         if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
4852                         (uint8_t *)(&dpcd_backlight_set),
4853                         sizeof(dpcd_backlight_set)) != DC_OK)
4854                 return false;
4855
4856         if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_CONTROL,
4857                         &backlight_control, 1) != DC_OK)
4858                 return false;
4859
4860         return true;
4861 }
4862
4863 bool dc_link_get_backlight_level_nits(struct dc_link *link,
4864                 uint32_t *backlight_millinits_avg,
4865                 uint32_t *backlight_millinits_peak)
4866 {
4867         union dpcd_source_backlight_get dpcd_backlight_get;
4868
4869         memset(&dpcd_backlight_get, 0, sizeof(union dpcd_source_backlight_get));
4870
4871         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4872                         link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4873                 return false;
4874
4875         if (core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_CURRENT_PEAK,
4876                         dpcd_backlight_get.raw,
4877                         sizeof(union dpcd_source_backlight_get)) != DC_OK)
4878                 return false;
4879
4880         *backlight_millinits_avg =
4881                 dpcd_backlight_get.bytes.backlight_millinits_avg;
4882         *backlight_millinits_peak =
4883                 dpcd_backlight_get.bytes.backlight_millinits_peak;
4884
4885         /* On non-supported panels dpcd_read usually succeeds with 0 returned */
4886         if (*backlight_millinits_avg == 0 ||
4887                         *backlight_millinits_avg > *backlight_millinits_peak)
4888                 return false;
4889
4890         return true;
4891 }
4892
4893 bool dc_link_backlight_enable_aux(struct dc_link *link, bool enable)
4894 {
4895         uint8_t backlight_enable = enable ? 1 : 0;
4896
4897         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4898                 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4899                 return false;
4900
4901         if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_ENABLE,
4902                 &backlight_enable, 1) != DC_OK)
4903                 return false;
4904
4905         return true;
4906 }
4907
4908 // we read default from 0x320 because we expect BIOS wrote it there
4909 // regular get_backlight_nit reads from panel set at 0x326
4910 bool dc_link_read_default_bl_aux(struct dc_link *link, uint32_t *backlight_millinits)
4911 {
4912         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4913                 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4914                 return false;
4915
4916         if (core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
4917                 (uint8_t *) backlight_millinits,
4918                 sizeof(uint32_t)) != DC_OK)
4919                 return false;
4920
4921         return true;
4922 }
4923
4924 bool dc_link_set_default_brightness_aux(struct dc_link *link)
4925 {
4926         uint32_t default_backlight;
4927
4928         if (link && link->dpcd_sink_ext_caps.bits.oled == 1) {
4929                 if (!dc_link_read_default_bl_aux(link, &default_backlight))
4930                         default_backlight = 150000;
4931                 // if < 5 nits or > 5000, it might be wrong readback
4932                 if (default_backlight < 5000 || default_backlight > 5000000)
4933                         default_backlight = 150000; //
4934
4935                 return dc_link_set_backlight_level_nits(link, true,
4936                                 default_backlight, 0);
4937         }
4938         return false;
4939 }
4940
4941 bool is_edp_ilr_optimization_required(struct dc_link *link, struct dc_crtc_timing *crtc_timing)
4942 {
4943         struct dc_link_settings link_setting;
4944         uint8_t link_bw_set;
4945         uint8_t link_rate_set;
4946         uint32_t req_bw;
4947         union lane_count_set lane_count_set = { {0} };
4948
4949         ASSERT(link || crtc_timing); // invalid input
4950
4951         if (link->dpcd_caps.edp_supported_link_rates_count == 0 ||
4952                         !link->dc->debug.optimize_edp_link_rate)
4953                 return false;
4954
4955
4956         // Read DPCD 00100h to find if standard link rates are set
4957         core_link_read_dpcd(link, DP_LINK_BW_SET,
4958                                 &link_bw_set, sizeof(link_bw_set));
4959
4960         if (link_bw_set) {
4961                 DC_LOG_EVENT_LINK_TRAINING("eDP ILR: Optimization required, VBIOS used link_bw_set\n");
4962                 return true;
4963         }
4964
4965         // Read DPCD 00115h to find the edp link rate set used
4966         core_link_read_dpcd(link, DP_LINK_RATE_SET,
4967                             &link_rate_set, sizeof(link_rate_set));
4968
4969         // Read DPCD 00101h to find out the number of lanes currently set
4970         core_link_read_dpcd(link, DP_LANE_COUNT_SET,
4971                                 &lane_count_set.raw, sizeof(lane_count_set));
4972
4973         req_bw = dc_bandwidth_in_kbps_from_timing(crtc_timing);
4974
4975         decide_edp_link_settings(link, &link_setting, req_bw);
4976
4977         if (link->dpcd_caps.edp_supported_link_rates[link_rate_set] != link_setting.link_rate ||
4978                         lane_count_set.bits.LANE_COUNT_SET != link_setting.lane_count) {
4979                 DC_LOG_EVENT_LINK_TRAINING("eDP ILR: Optimization required, VBIOS link_rate_set not optimal\n");
4980                 return true;
4981         }
4982
4983         DC_LOG_EVENT_LINK_TRAINING("eDP ILR: No optimization required, VBIOS set optimal link_rate_set\n");
4984         return false;
4985 }
4986
4987 enum dp_link_encoding dp_get_link_encoding_format(const struct dc_link_settings *link_settings)
4988 {
4989         if ((link_settings->link_rate >= LINK_RATE_LOW) &&
4990                         (link_settings->link_rate <= LINK_RATE_HIGH3))
4991                 return DP_8b_10b_ENCODING;
4992         return DP_UNKNOWN_ENCODING;
4993 }
4994