2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <linux/slab.h>
28 #include "dm_services.h"
29 #include "atomfirmware.h"
30 #include "dm_helpers.h"
32 #include "grph_object_id.h"
33 #include "gpio_service_interface.h"
34 #include "core_status.h"
35 #include "dc_link_dp.h"
36 #include "dc_link_ddc.h"
37 #include "link_hwss.h"
40 #include "link_encoder.h"
41 #include "hw_sequencer.h"
44 #include "fixed31_32.h"
45 #include "dpcd_defs.h"
47 #include "hw/clk_mgr.h"
48 #include "dce/dmub_psr.h"
49 #include "dmub/dmub_srv.h"
50 #include "inc/hw/panel_cntl.h"
52 #define DC_LOGGER_INIT(logger)
54 #define LINK_INFO(...) \
58 #define RETIMER_REDRIVER_INFO(...) \
59 DC_LOG_RETIMER_REDRIVER( \
61 /*******************************************************************************
63 ******************************************************************************/
66 PEAK_FACTOR_X1000 = 1006,
68 * Some receivers fail to train on first try and are good
69 * on subsequent tries. 2 retries should be plenty. If we
70 * don't have a successful training then we don't expect to
73 LINK_TRAINING_MAX_VERIFY_RETRY = 2
76 /*******************************************************************************
78 ******************************************************************************/
79 static void dc_link_destruct(struct dc_link *link)
84 dal_gpio_destroy_irq(&link->hpd_gpio);
85 link->hpd_gpio = NULL;
89 dal_ddc_service_destroy(&link->ddc);
92 link->panel_cntl->funcs->destroy(&link->panel_cntl);
95 /* Update link encoder resource tracking variables. These are used for
96 * the dynamic assignment of link encoders to streams. Virtual links
97 * are not assigned encoder resources on creation.
99 if (link->link_id.id != CONNECTOR_ID_VIRTUAL) {
100 link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = NULL;
101 link->dc->res_pool->dig_link_enc_count--;
103 link->link_enc->funcs->destroy(&link->link_enc);
106 if (link->local_sink)
107 dc_sink_release(link->local_sink);
109 for (i = 0; i < link->sink_count; ++i)
110 dc_sink_release(link->remote_sinks[i]);
113 struct gpio *get_hpd_gpio(struct dc_bios *dcb,
114 struct graphics_object_id link_id,
115 struct gpio_service *gpio_service)
117 enum bp_result bp_result;
118 struct graphics_object_hpd_info hpd_info;
119 struct gpio_pin_info pin_info;
121 if (dcb->funcs->get_hpd_info(dcb, link_id, &hpd_info) != BP_RESULT_OK)
124 bp_result = dcb->funcs->get_gpio_pin_info(dcb,
125 hpd_info.hpd_int_gpio_uid, &pin_info);
127 if (bp_result != BP_RESULT_OK) {
128 ASSERT(bp_result == BP_RESULT_NORECORD);
132 return dal_gpio_service_create_irq(gpio_service,
138 * Function: program_hpd_filter
141 * Programs HPD filter on associated HPD line
143 * @param [in] delay_on_connect_in_ms: Connect filter timeout
144 * @param [in] delay_on_disconnect_in_ms: Disconnect filter timeout
147 * true on success, false otherwise
149 static bool program_hpd_filter(const struct dc_link *link)
153 int delay_on_connect_in_ms = 0;
154 int delay_on_disconnect_in_ms = 0;
156 if (link->is_hpd_filter_disabled)
158 /* Verify feature is supported */
159 switch (link->connector_signal) {
160 case SIGNAL_TYPE_DVI_SINGLE_LINK:
161 case SIGNAL_TYPE_DVI_DUAL_LINK:
162 case SIGNAL_TYPE_HDMI_TYPE_A:
163 /* Program hpd filter */
164 delay_on_connect_in_ms = 500;
165 delay_on_disconnect_in_ms = 100;
167 case SIGNAL_TYPE_DISPLAY_PORT:
168 case SIGNAL_TYPE_DISPLAY_PORT_MST:
169 /* Program hpd filter to allow DP signal to settle */
170 /* 500: not able to detect MST <-> SST switch as HPD is low for
171 * only 100ms on DELL U2413
172 * 0: some passive dongle still show aux mode instead of i2c
173 * 20-50: not enough to hide bouncing HPD with passive dongle.
174 * also see intermittent i2c read issues.
176 delay_on_connect_in_ms = 80;
177 delay_on_disconnect_in_ms = 0;
179 case SIGNAL_TYPE_LVDS:
180 case SIGNAL_TYPE_EDP:
182 /* Don't program hpd filter */
186 /* Obtain HPD handle */
187 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
188 link->ctx->gpio_service);
193 /* Setup HPD filtering */
194 if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
195 struct gpio_hpd_config config;
197 config.delay_on_connect = delay_on_connect_in_ms;
198 config.delay_on_disconnect = delay_on_disconnect_in_ms;
200 dal_irq_setup_hpd_filter(hpd, &config);
206 ASSERT_CRITICAL(false);
209 /* Release HPD handle */
210 dal_gpio_destroy_irq(&hpd);
215 bool dc_link_wait_for_t12(struct dc_link *link)
217 if (link->connector_signal == SIGNAL_TYPE_EDP && link->dc->hwss.edp_wait_for_T12) {
218 link->dc->hwss.edp_wait_for_T12(link);
227 * dc_link_detect_sink() - Determine if there is a sink connected
229 * @link: pointer to the dc link
230 * @type: Returned connection type
231 * Does not detect downstream devices, such as MST sinks
232 * or display connected through active dongles
234 bool dc_link_detect_sink(struct dc_link *link, enum dc_connection_type *type)
236 uint32_t is_hpd_high = 0;
237 struct gpio *hpd_pin;
239 if (link->connector_signal == SIGNAL_TYPE_LVDS) {
240 *type = dc_connection_single;
244 if (link->connector_signal == SIGNAL_TYPE_EDP) {
245 /*in case it is not on*/
246 link->dc->hwss.edp_power_control(link, true);
247 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
250 /* todo: may need to lock gpio access */
251 hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
252 link->ctx->gpio_service);
254 goto hpd_gpio_failure;
256 dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
257 dal_gpio_get_value(hpd_pin, &is_hpd_high);
258 dal_gpio_close(hpd_pin);
259 dal_gpio_destroy_irq(&hpd_pin);
262 *type = dc_connection_single;
263 /* TODO: need to do the actual detection */
265 *type = dc_connection_none;
274 static enum ddc_transaction_type get_ddc_transaction_type(enum signal_type sink_signal)
276 enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
278 switch (sink_signal) {
279 case SIGNAL_TYPE_DVI_SINGLE_LINK:
280 case SIGNAL_TYPE_DVI_DUAL_LINK:
281 case SIGNAL_TYPE_HDMI_TYPE_A:
282 case SIGNAL_TYPE_LVDS:
283 case SIGNAL_TYPE_RGB:
284 transaction_type = DDC_TRANSACTION_TYPE_I2C;
287 case SIGNAL_TYPE_DISPLAY_PORT:
288 case SIGNAL_TYPE_EDP:
289 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
292 case SIGNAL_TYPE_DISPLAY_PORT_MST:
293 /* MST does not use I2COverAux, but there is the
294 * SPECIAL use case for "immediate dwnstrm device
295 * access" (EPR#370830).
297 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
304 return transaction_type;
307 static enum signal_type get_basic_signal_type(struct graphics_object_id encoder,
308 struct graphics_object_id downstream)
310 if (downstream.type == OBJECT_TYPE_CONNECTOR) {
311 switch (downstream.id) {
312 case CONNECTOR_ID_SINGLE_LINK_DVII:
313 switch (encoder.id) {
314 case ENCODER_ID_INTERNAL_DAC1:
315 case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
316 case ENCODER_ID_INTERNAL_DAC2:
317 case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
318 return SIGNAL_TYPE_RGB;
320 return SIGNAL_TYPE_DVI_SINGLE_LINK;
323 case CONNECTOR_ID_DUAL_LINK_DVII:
325 switch (encoder.id) {
326 case ENCODER_ID_INTERNAL_DAC1:
327 case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
328 case ENCODER_ID_INTERNAL_DAC2:
329 case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
330 return SIGNAL_TYPE_RGB;
332 return SIGNAL_TYPE_DVI_DUAL_LINK;
336 case CONNECTOR_ID_SINGLE_LINK_DVID:
337 return SIGNAL_TYPE_DVI_SINGLE_LINK;
338 case CONNECTOR_ID_DUAL_LINK_DVID:
339 return SIGNAL_TYPE_DVI_DUAL_LINK;
340 case CONNECTOR_ID_VGA:
341 return SIGNAL_TYPE_RGB;
342 case CONNECTOR_ID_HDMI_TYPE_A:
343 return SIGNAL_TYPE_HDMI_TYPE_A;
344 case CONNECTOR_ID_LVDS:
345 return SIGNAL_TYPE_LVDS;
346 case CONNECTOR_ID_DISPLAY_PORT:
347 return SIGNAL_TYPE_DISPLAY_PORT;
348 case CONNECTOR_ID_EDP:
349 return SIGNAL_TYPE_EDP;
351 return SIGNAL_TYPE_NONE;
353 } else if (downstream.type == OBJECT_TYPE_ENCODER) {
354 switch (downstream.id) {
355 case ENCODER_ID_EXTERNAL_NUTMEG:
356 case ENCODER_ID_EXTERNAL_TRAVIS:
357 return SIGNAL_TYPE_DISPLAY_PORT;
359 return SIGNAL_TYPE_NONE;
363 return SIGNAL_TYPE_NONE;
367 * dc_link_is_dp_sink_present() - Check if there is a native DP
368 * or passive DP-HDMI dongle connected
370 bool dc_link_is_dp_sink_present(struct dc_link *link)
372 enum gpio_result gpio_result;
373 uint32_t clock_pin = 0;
377 enum connector_id connector_id =
378 dal_graphics_object_id_get_connector_id(link->link_id);
381 ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
382 (connector_id == CONNECTOR_ID_EDP));
384 ddc = dal_ddc_service_get_ddc_pin(link->ddc);
391 /* Open GPIO and set it to I2C mode */
392 /* Note: this GpioMode_Input will be converted
393 * to GpioConfigType_I2cAuxDualMode in GPIO component,
394 * which indicates we need additional delay
397 if (dal_ddc_open(ddc, GPIO_MODE_INPUT,
398 GPIO_DDC_CONFIG_TYPE_MODE_I2C) != GPIO_RESULT_OK) {
405 * Read GPIO: DP sink is present if both clock and data pins are zero
407 * [W/A] plug-unplug DP cable, sometimes customer board has
408 * one short pulse on clk_pin(1V, < 1ms). DP will be config to HDMI/DVI
409 * then monitor can't br light up. Add retry 3 times
410 * But in real passive dongle, it need additional 3ms to detect
413 gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
414 ASSERT(gpio_result == GPIO_RESULT_OK);
419 } while (retry++ < 3);
421 present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
430 * Detect output sink type
432 static enum signal_type link_detect_sink(struct dc_link *link,
433 enum dc_detect_reason reason)
435 enum signal_type result = get_basic_signal_type(link->link_enc->id,
438 /* Internal digital encoder will detect only dongles
439 * that require digital signal
442 /* Detection mechanism is different
443 * for different native connectors.
444 * LVDS connector supports only LVDS signal;
445 * PCIE is a bus slot, the actual connector needs to be detected first;
446 * eDP connector supports only eDP signal;
447 * HDMI should check straps for audio
450 /* PCIE detects the actual connector on add-on board */
451 if (link->link_id.id == CONNECTOR_ID_PCIE) {
452 /* ZAZTODO implement PCIE add-on card detection */
455 switch (link->link_id.id) {
456 case CONNECTOR_ID_HDMI_TYPE_A: {
457 /* check audio support:
458 * if native HDMI is not supported, switch to DVI
460 struct audio_support *aud_support =
461 &link->dc->res_pool->audio_support;
463 if (!aud_support->hdmi_audio_native)
464 if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
465 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
468 case CONNECTOR_ID_DISPLAY_PORT: {
469 /* DP HPD short pulse. Passive DP dongle will not
472 if (reason != DETECT_REASON_HPDRX) {
473 /* Check whether DP signal detected: if not -
474 * we assume signal is DVI; it could be corrected
475 * to HDMI after dongle detection
477 if (!dm_helpers_is_dp_sink_present(link))
478 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
489 static enum signal_type decide_signal_from_strap_and_dongle_type(enum display_dongle_type dongle_type,
490 struct audio_support *audio_support)
492 enum signal_type signal = SIGNAL_TYPE_NONE;
494 switch (dongle_type) {
495 case DISPLAY_DONGLE_DP_HDMI_DONGLE:
496 if (audio_support->hdmi_audio_on_dongle)
497 signal = SIGNAL_TYPE_HDMI_TYPE_A;
499 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
501 case DISPLAY_DONGLE_DP_DVI_DONGLE:
502 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
504 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
505 if (audio_support->hdmi_audio_native)
506 signal = SIGNAL_TYPE_HDMI_TYPE_A;
508 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
511 signal = SIGNAL_TYPE_NONE;
518 static enum signal_type dp_passive_dongle_detection(struct ddc_service *ddc,
519 struct display_sink_capability *sink_cap,
520 struct audio_support *audio_support)
522 dal_ddc_service_i2c_query_dp_dual_mode_adaptor(ddc, sink_cap);
524 return decide_signal_from_strap_and_dongle_type(sink_cap->dongle_type,
528 static void link_disconnect_sink(struct dc_link *link)
530 if (link->local_sink) {
531 dc_sink_release(link->local_sink);
532 link->local_sink = NULL;
535 link->dpcd_sink_count = 0;
538 static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link)
540 dc_sink_release(link->local_sink);
541 link->local_sink = prev_sink;
544 #if defined(CONFIG_DRM_AMD_DC_HDCP)
545 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal)
550 case SIGNAL_TYPE_DISPLAY_PORT:
551 case SIGNAL_TYPE_DISPLAY_PORT_MST:
552 ret = link->hdcp_caps.bcaps.bits.HDCP_CAPABLE;
554 case SIGNAL_TYPE_DVI_SINGLE_LINK:
555 case SIGNAL_TYPE_DVI_DUAL_LINK:
556 case SIGNAL_TYPE_HDMI_TYPE_A:
557 /* HDMI doesn't tell us its HDCP(1.4) capability, so assume to always be capable,
558 * we can poll for bksv but some displays have an issue with this. Since its so rare
559 * for a display to not be 1.4 capable, this assumtion is ok
569 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal)
574 case SIGNAL_TYPE_DISPLAY_PORT:
575 case SIGNAL_TYPE_DISPLAY_PORT_MST:
576 ret = (link->hdcp_caps.bcaps.bits.HDCP_CAPABLE &&
577 link->hdcp_caps.rx_caps.fields.byte0.hdcp_capable &&
578 (link->hdcp_caps.rx_caps.fields.version == 0x2)) ? 1 : 0;
580 case SIGNAL_TYPE_DVI_SINGLE_LINK:
581 case SIGNAL_TYPE_DVI_DUAL_LINK:
582 case SIGNAL_TYPE_HDMI_TYPE_A:
583 ret = (link->hdcp_caps.rx_caps.fields.version == 0x4) ? 1:0;
592 static void query_hdcp_capability(enum signal_type signal, struct dc_link *link)
594 struct hdcp_protection_message msg22;
595 struct hdcp_protection_message msg14;
597 memset(&msg22, 0, sizeof(struct hdcp_protection_message));
598 memset(&msg14, 0, sizeof(struct hdcp_protection_message));
599 memset(link->hdcp_caps.rx_caps.raw, 0,
600 sizeof(link->hdcp_caps.rx_caps.raw));
602 if ((link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
603 link->ddc->transaction_type ==
604 DDC_TRANSACTION_TYPE_I2C_OVER_AUX) ||
605 link->connector_signal == SIGNAL_TYPE_EDP) {
606 msg22.data = link->hdcp_caps.rx_caps.raw;
607 msg22.length = sizeof(link->hdcp_caps.rx_caps.raw);
608 msg22.msg_id = HDCP_MESSAGE_ID_RX_CAPS;
610 msg22.data = &link->hdcp_caps.rx_caps.fields.version;
611 msg22.length = sizeof(link->hdcp_caps.rx_caps.fields.version);
612 msg22.msg_id = HDCP_MESSAGE_ID_HDCP2VERSION;
614 msg22.version = HDCP_VERSION_22;
615 msg22.link = HDCP_LINK_PRIMARY;
616 msg22.max_retries = 5;
617 dc_process_hdcp_msg(signal, link, &msg22);
619 if (signal == SIGNAL_TYPE_DISPLAY_PORT || signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
620 msg14.data = &link->hdcp_caps.bcaps.raw;
621 msg14.length = sizeof(link->hdcp_caps.bcaps.raw);
622 msg14.msg_id = HDCP_MESSAGE_ID_READ_BCAPS;
623 msg14.version = HDCP_VERSION_14;
624 msg14.link = HDCP_LINK_PRIMARY;
625 msg14.max_retries = 5;
627 dc_process_hdcp_msg(signal, link, &msg14);
633 static void read_current_link_settings_on_detect(struct dc_link *link)
635 union lane_count_set lane_count_set = { {0} };
637 uint8_t link_rate_set;
638 uint32_t read_dpcd_retry_cnt = 10;
639 enum dc_status status = DC_ERROR_UNEXPECTED;
641 union max_down_spread max_down_spread = { {0} };
643 // Read DPCD 00101h to find out the number of lanes currently set
644 for (i = 0; i < read_dpcd_retry_cnt; i++) {
645 status = core_link_read_dpcd(link,
648 sizeof(lane_count_set));
649 /* First DPCD read after VDD ON can fail if the particular board
650 * does not have HPD pin wired correctly. So if DPCD read fails,
651 * which it should never happen, retry a few times. Target worst
652 * case scenario of 80 ms.
654 if (status == DC_OK) {
655 link->cur_link_settings.lane_count =
656 lane_count_set.bits.LANE_COUNT_SET;
663 // Read DPCD 00100h to find if standard link rates are set
664 core_link_read_dpcd(link, DP_LINK_BW_SET,
665 &link_bw_set, sizeof(link_bw_set));
667 if (link_bw_set == 0) {
668 if (link->connector_signal == SIGNAL_TYPE_EDP) {
669 /* If standard link rates are not being used,
670 * Read DPCD 00115h to find the edp link rate set used
672 core_link_read_dpcd(link, DP_LINK_RATE_SET,
673 &link_rate_set, sizeof(link_rate_set));
675 // edp_supported_link_rates_count = 0 for DP
676 if (link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
677 link->cur_link_settings.link_rate =
678 link->dpcd_caps.edp_supported_link_rates[link_rate_set];
679 link->cur_link_settings.link_rate_set = link_rate_set;
680 link->cur_link_settings.use_link_rate_set = true;
683 // Link Rate not found. Seamless boot may not work.
687 link->cur_link_settings.link_rate = link_bw_set;
688 link->cur_link_settings.use_link_rate_set = false;
690 // Read DPCD 00003h to find the max down spread.
691 core_link_read_dpcd(link, DP_MAX_DOWNSPREAD,
692 &max_down_spread.raw, sizeof(max_down_spread));
693 link->cur_link_settings.link_spread =
694 max_down_spread.bits.MAX_DOWN_SPREAD ?
695 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
698 static bool detect_dp(struct dc_link *link,
699 struct display_sink_capability *sink_caps,
700 bool *converter_disable_audio,
701 struct audio_support *audio_support,
702 enum dc_detect_reason reason)
706 sink_caps->signal = link_detect_sink(link, reason);
707 sink_caps->transaction_type =
708 get_ddc_transaction_type(sink_caps->signal);
710 if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
711 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
712 if (!detect_dp_sink_caps(link))
714 if (is_mst_supported(link)) {
715 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
716 link->type = dc_connection_mst_branch;
718 dal_ddc_service_set_transaction_type(link->ddc,
719 sink_caps->transaction_type);
721 #if defined(CONFIG_DRM_AMD_DC_HDCP)
722 /* In case of fallback to SST when topology discovery below fails
723 * HDCP caps will be querried again later by the upper layer (caller
724 * of this function). */
725 query_hdcp_capability(SIGNAL_TYPE_DISPLAY_PORT_MST, link);
728 * This call will initiate MST topology discovery. Which
729 * will detect MST ports and add new DRM connector DRM
730 * framework. Then read EDID via remote i2c over aux. In
731 * the end, will notify DRM detect result and save EDID
732 * into DRM framework.
734 * .detect is called by .fill_modes.
735 * .fill_modes is called by user mode ioctl
736 * DRM_IOCTL_MODE_GETCONNECTOR.
738 * .get_modes is called by .fill_modes.
740 * call .get_modes, AMDGPU DM implementation will create
741 * new dc_sink and add to dc_link. For long HPD plug
742 * in/out, MST has its own handle.
744 * Therefore, just after dc_create, link->sink is not
745 * created for MST until user mode app calls
746 * DRM_IOCTL_MODE_GETCONNECTOR.
748 * Need check ->sink usages in case ->sink = NULL
749 * TODO: s3 resume check
751 if (reason == DETECT_REASON_BOOT)
754 dm_helpers_dp_update_branch_info(link->ctx, link);
756 if (!dm_helpers_dp_mst_start_top_mgr(link->ctx,
758 /* MST not supported */
759 link->type = dc_connection_single;
760 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
764 if (link->type != dc_connection_mst_branch &&
765 is_dp_active_dongle(link)) {
766 /* DP active dongles */
767 link->type = dc_connection_active_dongle;
768 if (!link->dpcd_caps.sink_count.bits.SINK_COUNT) {
770 * active dongle unplug processing for short irq
772 link_disconnect_sink(link);
776 if (link->dpcd_caps.dongle_type !=
777 DISPLAY_DONGLE_DP_HDMI_CONVERTER)
778 *converter_disable_audio = true;
781 /* DP passive dongles */
782 sink_caps->signal = dp_passive_dongle_detection(link->ddc,
785 link->dpcd_caps.dongle_type = sink_caps->dongle_type;
791 static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
793 if (old_edid->length != new_edid->length)
796 if (new_edid->length == 0)
799 return (memcmp(old_edid->raw_edid,
800 new_edid->raw_edid, new_edid->length) == 0);
803 static bool wait_for_entering_dp_alt_mode(struct dc_link *link)
806 * something is terribly wrong if time out is > 200ms. (5Hz)
807 * 500 microseconds * 400 tries us 200 ms
809 unsigned int sleep_time_in_microseconds = 500;
810 unsigned int tries_allowed = 400;
812 unsigned long long enter_timestamp;
813 unsigned long long finish_timestamp;
814 unsigned long long time_taken_in_ns;
817 DC_LOGGER_INIT(link->ctx->logger);
819 if (!link->link_enc->funcs->is_in_alt_mode)
822 is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc);
823 DC_LOG_WARNING("DP Alt mode state on HPD: %d\n", is_in_alt_mode);
828 enter_timestamp = dm_get_timestamp(link->ctx);
830 for (tries_taken = 0; tries_taken < tries_allowed; tries_taken++) {
831 udelay(sleep_time_in_microseconds);
832 /* ask the link if alt mode is enabled, if so return ok */
833 if (link->link_enc->funcs->is_in_alt_mode(link->link_enc)) {
834 finish_timestamp = dm_get_timestamp(link->ctx);
836 dm_get_elapse_time_in_ns(link->ctx,
839 DC_LOG_WARNING("Alt mode entered finished after %llu ms\n",
840 div_u64(time_taken_in_ns, 1000000));
844 finish_timestamp = dm_get_timestamp(link->ctx);
845 time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp,
847 DC_LOG_WARNING("Alt mode has timed out after %llu ms\n",
848 div_u64(time_taken_in_ns, 1000000));
853 * dc_link_detect() - Detect if a sink is attached to a given link
855 * link->local_sink is created or destroyed as needed.
857 * This does not create remote sinks but will trigger DM
858 * to start MST detection if a branch is detected.
860 static bool dc_link_detect_helper(struct dc_link *link,
861 enum dc_detect_reason reason)
863 struct dc_sink_init_data sink_init_data = { 0 };
864 struct display_sink_capability sink_caps = { 0 };
866 bool converter_disable_audio = false;
867 struct audio_support *aud_support = &link->dc->res_pool->audio_support;
868 bool same_edid = false;
869 enum dc_edid_status edid_status;
870 struct dc_context *dc_ctx = link->ctx;
871 struct dc_sink *sink = NULL;
872 struct dc_sink *prev_sink = NULL;
873 struct dpcd_caps prev_dpcd_caps;
874 bool same_dpcd = true;
875 enum dc_connection_type new_connection_type = dc_connection_none;
876 enum dc_connection_type pre_connection_type = dc_connection_none;
877 bool perform_dp_seamless_boot = false;
878 const uint32_t post_oui_delay = 30; // 30ms
880 DC_LOGGER_INIT(link->ctx->logger);
882 if (dc_is_virtual_signal(link->connector_signal))
885 if ((link->connector_signal == SIGNAL_TYPE_LVDS ||
886 link->connector_signal == SIGNAL_TYPE_EDP) &&
888 // need to re-write OUI and brightness in resume case
889 if (link->connector_signal == SIGNAL_TYPE_EDP) {
890 dpcd_set_source_specific_data(link);
891 msleep(post_oui_delay);
892 dc_link_set_default_brightness_aux(link);
899 if (!dc_link_detect_sink(link, &new_connection_type)) {
904 prev_sink = link->local_sink;
906 dc_sink_retain(prev_sink);
907 memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps));
910 link_disconnect_sink(link);
911 if (new_connection_type != dc_connection_none) {
912 pre_connection_type = link->type;
913 link->type = new_connection_type;
914 link->link_state_valid = false;
916 /* From Disconnected-to-Connected. */
917 switch (link->connector_signal) {
918 case SIGNAL_TYPE_HDMI_TYPE_A: {
919 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
920 if (aud_support->hdmi_audio_native)
921 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
923 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
927 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
928 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
929 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
933 case SIGNAL_TYPE_DVI_DUAL_LINK: {
934 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
935 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
939 case SIGNAL_TYPE_LVDS: {
940 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
941 sink_caps.signal = SIGNAL_TYPE_LVDS;
945 case SIGNAL_TYPE_EDP: {
946 read_current_link_settings_on_detect(link);
948 detect_edp_sink_caps(link);
949 read_current_link_settings_on_detect(link);
950 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
951 sink_caps.signal = SIGNAL_TYPE_EDP;
955 case SIGNAL_TYPE_DISPLAY_PORT: {
956 /* wa HPD high coming too early*/
957 if (link->link_enc->features.flags.bits.DP_IS_USB_C == 1) {
958 /* if alt mode times out, return false */
959 if (!wait_for_entering_dp_alt_mode(link))
963 if (!detect_dp(link, &sink_caps,
964 &converter_disable_audio,
965 aud_support, reason)) {
967 dc_sink_release(prev_sink);
971 // Check if dpcp block is the same
973 if (memcmp(&link->dpcd_caps, &prev_dpcd_caps,
974 sizeof(struct dpcd_caps)))
977 /* Active dongle downstream unplug*/
978 if (link->type == dc_connection_active_dongle &&
979 link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) {
981 /* Downstream unplug */
982 dc_sink_release(prev_sink);
986 // link switch from MST to non-MST stop topology manager
987 if (pre_connection_type == dc_connection_mst_branch &&
988 link->type != dc_connection_mst_branch) {
989 dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
992 if (link->type == dc_connection_mst_branch) {
993 LINK_INFO("link=%d, mst branch is now Connected\n",
995 /* Need to setup mst link_cap struct here
996 * otherwise dc_link_detect() will leave mst link_cap
997 * empty which leads to allocate_mst_payload() has "0"
998 * pbn_per_slot value leading to exception on dc_fixpt_div()
1000 dp_verify_mst_link_cap(link);
1003 dc_sink_release(prev_sink);
1007 // For seamless boot, to skip verify link cap, we read UEFI settings and set them as verified.
1008 if (reason == DETECT_REASON_BOOT &&
1009 !dc_ctx->dc->config.power_down_display_on_boot &&
1010 link->link_status.link_active)
1011 perform_dp_seamless_boot = true;
1013 if (perform_dp_seamless_boot) {
1014 read_current_link_settings_on_detect(link);
1015 link->verified_link_cap = link->reported_link_cap;
1022 DC_ERROR("Invalid connector type! signal:%d\n",
1023 link->connector_signal);
1025 dc_sink_release(prev_sink);
1029 if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
1030 link->dpcd_sink_count =
1031 link->dpcd_caps.sink_count.bits.SINK_COUNT;
1033 link->dpcd_sink_count = 1;
1035 dal_ddc_service_set_transaction_type(link->ddc,
1036 sink_caps.transaction_type);
1039 dal_ddc_service_is_in_aux_transaction_mode(link->ddc);
1041 sink_init_data.link = link;
1042 sink_init_data.sink_signal = sink_caps.signal;
1044 sink = dc_sink_create(&sink_init_data);
1046 DC_ERROR("Failed to create sink!\n");
1048 dc_sink_release(prev_sink);
1052 sink->link->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
1053 sink->converter_disable_audio = converter_disable_audio;
1055 /* dc_sink_create returns a new reference */
1056 link->local_sink = sink;
1058 edid_status = dm_helpers_read_local_edid(link->ctx,
1061 switch (edid_status) {
1062 case EDID_BAD_CHECKSUM:
1063 DC_LOG_ERROR("EDID checksum invalid.\n");
1065 case EDID_NO_RESPONSE:
1066 DC_LOG_ERROR("No EDID read.\n");
1068 * Abort detection for non-DP connectors if we have
1071 * DP needs to report as connected if HDP is high
1072 * even if we have no EDID in order to go to
1075 if (dc_is_hdmi_signal(link->connector_signal) ||
1076 dc_is_dvi_signal(link->connector_signal)) {
1078 dc_sink_release(prev_sink);
1079 link_disconnect_sink(link);
1084 * Abort detection for DP connectors if we have
1085 * no EDID and connector is active converter
1086 * as there are no display downstream
1089 if (dc_is_dp_sst_signal(link->connector_signal) &&
1090 (link->dpcd_caps.dongle_type ==
1091 DISPLAY_DONGLE_DP_VGA_CONVERTER ||
1092 link->dpcd_caps.dongle_type ==
1093 DISPLAY_DONGLE_DP_DVI_CONVERTER)) {
1095 dc_sink_release(prev_sink);
1096 link_disconnect_sink(link);
1105 // Check if edid is the same
1107 (edid_status == EDID_THE_SAME || edid_status == EDID_OK))
1108 same_edid = is_same_edid(&prev_sink->dc_edid,
1111 if (sink->edid_caps.panel_patch.skip_scdc_overwrite)
1112 link->ctx->dc->debug.hdmi20_disable = true;
1114 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
1115 sink_caps.transaction_type ==
1116 DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
1118 * TODO debug why Dell 2413 doesn't like
1119 * two link trainings
1121 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1122 query_hdcp_capability(sink->sink_signal, link);
1125 // verify link cap for SST non-seamless boot
1126 if (!perform_dp_seamless_boot)
1127 dp_verify_link_cap_with_retries(link,
1128 &link->reported_link_cap,
1129 LINK_TRAINING_MAX_VERIFY_RETRY);
1131 // If edid is the same, then discard new sink and revert back to original sink
1133 link_disconnect_remap(prev_sink, link);
1137 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1138 query_hdcp_capability(sink->sink_signal, link);
1142 /* HDMI-DVI Dongle */
1143 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
1144 !sink->edid_caps.edid_hdmi)
1145 sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1147 /* Connectivity log: detection */
1148 for (i = 0; i < sink->dc_edid.length / DC_EDID_BLOCK_SIZE; i++) {
1149 CONN_DATA_DETECT(link,
1150 &sink->dc_edid.raw_edid[i * DC_EDID_BLOCK_SIZE],
1152 "%s: [Block %d] ", sink->edid_caps.display_name, i);
1155 DC_LOG_DETECTION_EDID_PARSER("%s: "
1156 "manufacturer_id = %X, "
1158 "serial_number = %X, "
1159 "manufacture_week = %d, "
1160 "manufacture_year = %d, "
1161 "display_name = %s, "
1162 "speaker_flag = %d, "
1163 "audio_mode_count = %d\n",
1165 sink->edid_caps.manufacturer_id,
1166 sink->edid_caps.product_id,
1167 sink->edid_caps.serial_number,
1168 sink->edid_caps.manufacture_week,
1169 sink->edid_caps.manufacture_year,
1170 sink->edid_caps.display_name,
1171 sink->edid_caps.speaker_flags,
1172 sink->edid_caps.audio_mode_count);
1174 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
1175 DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, "
1176 "format_code = %d, "
1177 "channel_count = %d, "
1178 "sample_rate = %d, "
1179 "sample_size = %d\n",
1182 sink->edid_caps.audio_modes[i].format_code,
1183 sink->edid_caps.audio_modes[i].channel_count,
1184 sink->edid_caps.audio_modes[i].sample_rate,
1185 sink->edid_caps.audio_modes[i].sample_size);
1188 /* From Connected-to-Disconnected. */
1189 if (link->type == dc_connection_mst_branch) {
1190 LINK_INFO("link=%d, mst branch is now Disconnected\n",
1193 dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
1195 link->mst_stream_alloc_table.stream_count = 0;
1196 memset(link->mst_stream_alloc_table.stream_allocations,
1198 sizeof(link->mst_stream_alloc_table.stream_allocations));
1201 link->type = dc_connection_none;
1202 sink_caps.signal = SIGNAL_TYPE_NONE;
1203 /* When we unplug a passive DP-HDMI dongle connection, dongle_max_pix_clk
1204 * is not cleared. If we emulate a DP signal on this connection, it thinks
1205 * the dongle is still there and limits the number of modes we can emulate.
1206 * Clear dongle_max_pix_clk on disconnect to fix this
1208 link->dongle_max_pix_clk = 0;
1211 LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p dpcd same=%d edid same=%d\n",
1212 link->link_index, sink,
1213 (sink_caps.signal ==
1214 SIGNAL_TYPE_NONE ? "Disconnected" : "Connected"),
1215 prev_sink, same_dpcd, same_edid);
1218 dc_sink_release(prev_sink);
1223 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
1225 const struct dc *dc = link->dc;
1228 /* get out of low power state */
1229 clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
1231 ret = dc_link_detect_helper(link, reason);
1233 /* Go back to power optimized state */
1234 clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
1239 bool dc_link_get_hpd_state(struct dc_link *dc_link)
1243 dal_gpio_lock_pin(dc_link->hpd_gpio);
1244 dal_gpio_get_value(dc_link->hpd_gpio, &state);
1245 dal_gpio_unlock_pin(dc_link->hpd_gpio);
1250 static enum hpd_source_id get_hpd_line(struct dc_link *link)
1253 enum hpd_source_id hpd_id = HPD_SOURCEID_UNKNOWN;
1255 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
1256 link->ctx->gpio_service);
1259 switch (dal_irq_get_source(hpd)) {
1260 case DC_IRQ_SOURCE_HPD1:
1261 hpd_id = HPD_SOURCEID1;
1263 case DC_IRQ_SOURCE_HPD2:
1264 hpd_id = HPD_SOURCEID2;
1266 case DC_IRQ_SOURCE_HPD3:
1267 hpd_id = HPD_SOURCEID3;
1269 case DC_IRQ_SOURCE_HPD4:
1270 hpd_id = HPD_SOURCEID4;
1272 case DC_IRQ_SOURCE_HPD5:
1273 hpd_id = HPD_SOURCEID5;
1275 case DC_IRQ_SOURCE_HPD6:
1276 hpd_id = HPD_SOURCEID6;
1279 BREAK_TO_DEBUGGER();
1283 dal_gpio_destroy_irq(&hpd);
1289 static enum channel_id get_ddc_line(struct dc_link *link)
1292 enum channel_id channel = CHANNEL_ID_UNKNOWN;
1294 ddc = dal_ddc_service_get_ddc_pin(link->ddc);
1297 switch (dal_ddc_get_line(ddc)) {
1298 case GPIO_DDC_LINE_DDC1:
1299 channel = CHANNEL_ID_DDC1;
1301 case GPIO_DDC_LINE_DDC2:
1302 channel = CHANNEL_ID_DDC2;
1304 case GPIO_DDC_LINE_DDC3:
1305 channel = CHANNEL_ID_DDC3;
1307 case GPIO_DDC_LINE_DDC4:
1308 channel = CHANNEL_ID_DDC4;
1310 case GPIO_DDC_LINE_DDC5:
1311 channel = CHANNEL_ID_DDC5;
1313 case GPIO_DDC_LINE_DDC6:
1314 channel = CHANNEL_ID_DDC6;
1316 case GPIO_DDC_LINE_DDC_VGA:
1317 channel = CHANNEL_ID_DDC_VGA;
1319 case GPIO_DDC_LINE_I2C_PAD:
1320 channel = CHANNEL_ID_I2C_PAD;
1323 BREAK_TO_DEBUGGER();
1331 static enum transmitter translate_encoder_to_transmitter(struct graphics_object_id encoder)
1333 switch (encoder.id) {
1334 case ENCODER_ID_INTERNAL_UNIPHY:
1335 switch (encoder.enum_id) {
1337 return TRANSMITTER_UNIPHY_A;
1339 return TRANSMITTER_UNIPHY_B;
1341 return TRANSMITTER_UNKNOWN;
1344 case ENCODER_ID_INTERNAL_UNIPHY1:
1345 switch (encoder.enum_id) {
1347 return TRANSMITTER_UNIPHY_C;
1349 return TRANSMITTER_UNIPHY_D;
1351 return TRANSMITTER_UNKNOWN;
1354 case ENCODER_ID_INTERNAL_UNIPHY2:
1355 switch (encoder.enum_id) {
1357 return TRANSMITTER_UNIPHY_E;
1359 return TRANSMITTER_UNIPHY_F;
1361 return TRANSMITTER_UNKNOWN;
1364 case ENCODER_ID_INTERNAL_UNIPHY3:
1365 switch (encoder.enum_id) {
1367 return TRANSMITTER_UNIPHY_G;
1369 return TRANSMITTER_UNKNOWN;
1372 case ENCODER_ID_EXTERNAL_NUTMEG:
1373 switch (encoder.enum_id) {
1375 return TRANSMITTER_NUTMEG_CRT;
1377 return TRANSMITTER_UNKNOWN;
1380 case ENCODER_ID_EXTERNAL_TRAVIS:
1381 switch (encoder.enum_id) {
1383 return TRANSMITTER_TRAVIS_CRT;
1385 return TRANSMITTER_TRAVIS_LCD;
1387 return TRANSMITTER_UNKNOWN;
1391 return TRANSMITTER_UNKNOWN;
1395 static bool dc_link_construct(struct dc_link *link,
1396 const struct link_init_data *init_params)
1399 struct ddc_service_init_data ddc_service_init_data = { { 0 } };
1400 struct dc_context *dc_ctx = init_params->ctx;
1401 struct encoder_init_data enc_init_data = { 0 };
1402 struct panel_cntl_init_data panel_cntl_init_data = { 0 };
1403 struct integrated_info *info;
1404 struct dc_bios *bios = init_params->dc->ctx->dc_bios;
1405 const struct dc_vbios_funcs *bp_funcs = bios->funcs;
1406 struct bp_disp_connector_caps_info disp_connect_caps_info = { 0 };
1408 DC_LOGGER_INIT(dc_ctx->logger);
1410 info = kzalloc(sizeof(*info), GFP_KERNEL);
1414 link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1415 link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
1417 link->link_status.dpcd_caps = &link->dpcd_caps;
1419 link->dc = init_params->dc;
1421 link->link_index = init_params->link_index;
1423 memset(&link->preferred_training_settings, 0,
1424 sizeof(struct dc_link_training_overrides));
1425 memset(&link->preferred_link_setting, 0,
1426 sizeof(struct dc_link_settings));
1429 bios->funcs->get_connector_id(bios, init_params->connector_index);
1431 link->ep_type = DISPLAY_ENDPOINT_PHY;
1433 DC_LOG_DC("BIOS object table - link_id: %d", link->link_id.id);
1435 if (bios->funcs->get_disp_connector_caps_info) {
1436 bios->funcs->get_disp_connector_caps_info(bios, link->link_id, &disp_connect_caps_info);
1437 link->is_internal_display = disp_connect_caps_info.INTERNAL_DISPLAY;
1438 DC_LOG_DC("BIOS object table - is_internal_display: %d", link->is_internal_display);
1441 if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
1442 dm_output_to_console("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",
1443 __func__, init_params->connector_index,
1444 link->link_id.type, OBJECT_TYPE_CONNECTOR);
1448 if (link->dc->res_pool->funcs->link_init)
1449 link->dc->res_pool->funcs->link_init(link);
1451 link->hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
1452 link->ctx->gpio_service);
1454 if (link->hpd_gpio) {
1455 dal_gpio_open(link->hpd_gpio, GPIO_MODE_INTERRUPT);
1456 dal_gpio_unlock_pin(link->hpd_gpio);
1457 link->irq_source_hpd = dal_irq_get_source(link->hpd_gpio);
1459 DC_LOG_DC("BIOS object table - hpd_gpio id: %d", link->hpd_gpio->id);
1460 DC_LOG_DC("BIOS object table - hpd_gpio en: %d", link->hpd_gpio->en);
1463 switch (link->link_id.id) {
1464 case CONNECTOR_ID_HDMI_TYPE_A:
1465 link->connector_signal = SIGNAL_TYPE_HDMI_TYPE_A;
1468 case CONNECTOR_ID_SINGLE_LINK_DVID:
1469 case CONNECTOR_ID_SINGLE_LINK_DVII:
1470 link->connector_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1472 case CONNECTOR_ID_DUAL_LINK_DVID:
1473 case CONNECTOR_ID_DUAL_LINK_DVII:
1474 link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1476 case CONNECTOR_ID_DISPLAY_PORT:
1477 link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;
1480 link->irq_source_hpd_rx =
1481 dal_irq_get_rx_source(link->hpd_gpio);
1484 case CONNECTOR_ID_EDP:
1485 link->connector_signal = SIGNAL_TYPE_EDP;
1487 if (link->hpd_gpio) {
1488 link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1489 link->irq_source_hpd_rx =
1490 dal_irq_get_rx_source(link->hpd_gpio);
1494 case CONNECTOR_ID_LVDS:
1495 link->connector_signal = SIGNAL_TYPE_LVDS;
1498 DC_LOG_WARNING("Unsupported Connector type:%d!\n",
1503 /* TODO: #DAL3 Implement id to str function.*/
1504 LINK_INFO("Connector[%d] description:"
1506 init_params->connector_index,
1507 link->connector_signal);
1509 ddc_service_init_data.ctx = link->ctx;
1510 ddc_service_init_data.id = link->link_id;
1511 ddc_service_init_data.link = link;
1512 link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1515 DC_ERROR("Failed to create ddc_service!\n");
1516 goto ddc_create_fail;
1519 if (!link->ddc->ddc_pin) {
1520 DC_ERROR("Failed to get I2C info for connector!\n");
1521 goto ddc_create_fail;
1525 dal_ddc_get_line(dal_ddc_service_get_ddc_pin(link->ddc));
1528 if (link->dc->res_pool->funcs->panel_cntl_create &&
1529 (link->link_id.id == CONNECTOR_ID_EDP ||
1530 link->link_id.id == CONNECTOR_ID_LVDS)) {
1531 panel_cntl_init_data.ctx = dc_ctx;
1532 panel_cntl_init_data.inst =
1533 panel_cntl_init_data.ctx->dc_edp_id_count;
1535 link->dc->res_pool->funcs->panel_cntl_create(
1536 &panel_cntl_init_data);
1537 panel_cntl_init_data.ctx->dc_edp_id_count++;
1539 if (link->panel_cntl == NULL) {
1540 DC_ERROR("Failed to create link panel_cntl!\n");
1541 goto panel_cntl_create_fail;
1545 enc_init_data.ctx = dc_ctx;
1546 bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0,
1547 &enc_init_data.encoder);
1548 enc_init_data.connector = link->link_id;
1549 enc_init_data.channel = get_ddc_line(link);
1550 enc_init_data.hpd_source = get_hpd_line(link);
1552 link->hpd_src = enc_init_data.hpd_source;
1554 enc_init_data.transmitter =
1555 translate_encoder_to_transmitter(enc_init_data.encoder);
1557 link->dc->res_pool->funcs->link_enc_create(&enc_init_data);
1559 if (!link->link_enc) {
1560 DC_ERROR("Failed to create link encoder!\n");
1561 goto link_enc_create_fail;
1564 DC_LOG_DC("BIOS object table - DP_IS_USB_C: %d", link->link_enc->features.flags.bits.DP_IS_USB_C);
1566 /* Update link encoder tracking variables. These are used for the dynamic
1567 * assignment of link encoders to streams.
1569 link->eng_id = link->link_enc->preferred_engine;
1570 link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = link->link_enc;
1571 link->dc->res_pool->dig_link_enc_count++;
1573 link->link_enc_hw_inst = link->link_enc->transmitter;
1575 for (i = 0; i < 4; i++) {
1576 if (bp_funcs->get_device_tag(dc_ctx->dc_bios,
1578 &link->device_tag) != BP_RESULT_OK) {
1579 DC_ERROR("Failed to find device tag!\n");
1580 goto device_tag_fail;
1583 /* Look for device tag that matches connector signal,
1584 * CRT for rgb, LCD for other supported signal tyes
1586 if (!bp_funcs->is_device_id_supported(dc_ctx->dc_bios,
1587 link->device_tag.dev_id))
1589 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT &&
1590 link->connector_signal != SIGNAL_TYPE_RGB)
1592 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD &&
1593 link->connector_signal == SIGNAL_TYPE_RGB)
1596 DC_LOG_DC("BIOS object table - device_tag.acpi_device: %d", link->device_tag.acpi_device);
1597 DC_LOG_DC("BIOS object table - device_tag.dev_id.device_type: %d", link->device_tag.dev_id.device_type);
1598 DC_LOG_DC("BIOS object table - device_tag.dev_id.enum_id: %d", link->device_tag.dev_id.enum_id);
1602 if (bios->integrated_info)
1603 memcpy(info, bios->integrated_info, sizeof(*info));
1605 /* Look for channel mapping corresponding to connector and device tag */
1606 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
1607 struct external_display_path *path =
1608 &info->ext_disp_conn_info.path[i];
1610 if (path->device_connector_id.enum_id == link->link_id.enum_id &&
1611 path->device_connector_id.id == link->link_id.id &&
1612 path->device_connector_id.type == link->link_id.type) {
1613 if (link->device_tag.acpi_device != 0 &&
1614 path->device_acpi_enum == link->device_tag.acpi_device) {
1615 link->ddi_channel_mapping = path->channel_mapping;
1616 link->chip_caps = path->caps;
1617 DC_LOG_DC("BIOS object table - ddi_channel_mapping: 0x%04X", link->ddi_channel_mapping.raw);
1618 DC_LOG_DC("BIOS object table - chip_caps: %d", link->chip_caps);
1619 } else if (path->device_tag ==
1620 link->device_tag.dev_id.raw_device_tag) {
1621 link->ddi_channel_mapping = path->channel_mapping;
1622 link->chip_caps = path->caps;
1623 DC_LOG_DC("BIOS object table - ddi_channel_mapping: 0x%04X", link->ddi_channel_mapping.raw);
1624 DC_LOG_DC("BIOS object table - chip_caps: %d", link->chip_caps);
1630 if (bios->funcs->get_atom_dc_golden_table)
1631 bios->funcs->get_atom_dc_golden_table(bios);
1634 * TODO check if GPIO programmed correctly
1636 * If GPIO isn't programmed correctly HPD might not rise or drain
1637 * fast enough, leading to bounces.
1639 program_hpd_filter(link);
1641 link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
1643 DC_LOG_DC("BIOS object table - %s finished successfully.\n", __func__);
1647 link->link_enc->funcs->destroy(&link->link_enc);
1648 link_enc_create_fail:
1649 if (link->panel_cntl != NULL)
1650 link->panel_cntl->funcs->destroy(&link->panel_cntl);
1651 panel_cntl_create_fail:
1652 dal_ddc_service_destroy(&link->ddc);
1656 if (link->hpd_gpio) {
1657 dal_gpio_destroy_irq(&link->hpd_gpio);
1658 link->hpd_gpio = NULL;
1661 DC_LOG_DC("BIOS object table - %s failed.\n", __func__);
1667 /*******************************************************************************
1669 ******************************************************************************/
1670 struct dc_link *link_create(const struct link_init_data *init_params)
1672 struct dc_link *link =
1673 kzalloc(sizeof(*link), GFP_KERNEL);
1678 if (false == dc_link_construct(link, init_params))
1679 goto construct_fail;
1690 void link_destroy(struct dc_link **link)
1692 dc_link_destruct(*link);
1697 static void enable_stream_features(struct pipe_ctx *pipe_ctx)
1699 struct dc_stream_state *stream = pipe_ctx->stream;
1701 if (pipe_ctx->stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) {
1702 struct dc_link *link = stream->link;
1703 union down_spread_ctrl old_downspread;
1704 union down_spread_ctrl new_downspread;
1706 core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,
1707 &old_downspread.raw, sizeof(old_downspread));
1709 new_downspread.raw = old_downspread.raw;
1711 new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
1712 (stream->ignore_msa_timing_param) ? 1 : 0;
1714 if (new_downspread.raw != old_downspread.raw) {
1715 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
1716 &new_downspread.raw, sizeof(new_downspread));
1720 dm_helpers_mst_enable_stream_features(stream);
1724 static enum dc_status enable_link_dp(struct dc_state *state,
1725 struct pipe_ctx *pipe_ctx)
1727 struct dc_stream_state *stream = pipe_ctx->stream;
1728 enum dc_status status;
1729 bool skip_video_pattern;
1730 struct dc_link *link = stream->link;
1731 struct dc_link_settings link_settings = {0};
1734 bool apply_seamless_boot_optimization = false;
1735 uint32_t bl_oled_enable_delay = 50; // in ms
1736 const uint32_t post_oui_delay = 30; // 30ms
1738 // check for seamless boot
1739 for (i = 0; i < state->stream_count; i++) {
1740 if (state->streams[i]->apply_seamless_boot_optimization) {
1741 apply_seamless_boot_optimization = true;
1746 /* get link settings for video mode timing */
1747 decide_link_settings(stream, &link_settings);
1749 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {
1750 /*in case it is not on*/
1751 link->dc->hwss.edp_power_control(link, true);
1752 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
1755 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
1756 link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
1757 if (state->clk_mgr && !apply_seamless_boot_optimization)
1758 state->clk_mgr->funcs->update_clocks(state->clk_mgr,
1761 // during mode switch we do DP_SET_POWER off then on, and OUI is lost
1762 dpcd_set_source_specific_data(link);
1763 if (link->dpcd_sink_ext_caps.raw != 0)
1764 msleep(post_oui_delay);
1766 skip_video_pattern = true;
1768 if (link_settings.link_rate == LINK_RATE_LOW)
1769 skip_video_pattern = false;
1771 if (perform_link_training_with_retries(&link_settings,
1773 LINK_TRAINING_ATTEMPTS,
1775 pipe_ctx->stream->signal)) {
1776 link->cur_link_settings = link_settings;
1779 status = DC_FAIL_DP_LINK_TRAINING;
1782 if (link->preferred_training_settings.fec_enable)
1783 fec_enable = *link->preferred_training_settings.fec_enable;
1787 dp_set_fec_enable(link, fec_enable);
1789 // during mode set we do DP_SET_POWER off then on, aux writes are lost
1790 if (link->dpcd_sink_ext_caps.bits.oled == 1 ||
1791 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 ||
1792 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) {
1793 dc_link_set_default_brightness_aux(link); // TODO: use cached if known
1794 if (link->dpcd_sink_ext_caps.bits.oled == 1)
1795 msleep(bl_oled_enable_delay);
1796 dc_link_backlight_enable_aux(link, true);
1802 static enum dc_status enable_link_edp(
1803 struct dc_state *state,
1804 struct pipe_ctx *pipe_ctx)
1806 enum dc_status status;
1808 status = enable_link_dp(state, pipe_ctx);
1813 static enum dc_status enable_link_dp_mst(
1814 struct dc_state *state,
1815 struct pipe_ctx *pipe_ctx)
1817 struct dc_link *link = pipe_ctx->stream->link;
1819 /* sink signal type after MST branch is MST. Multiple MST sinks
1820 * share one link. Link DP PHY is enable or training only once.
1822 if (link->link_status.link_active)
1825 /* clear payload table */
1826 dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link);
1828 /* to make sure the pending down rep can be processed
1829 * before enabling the link
1831 dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link);
1833 /* set the sink to MST mode before enabling the link */
1834 dp_enable_mst_on_sink(link, true);
1836 return enable_link_dp(state, pipe_ctx);
1839 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
1840 enum engine_id eng_id,
1841 struct ext_hdmi_settings *settings)
1843 bool result = false;
1845 struct integrated_info *integrated_info =
1846 pipe_ctx->stream->ctx->dc_bios->integrated_info;
1848 if (integrated_info == NULL)
1852 * Get retimer settings from sbios for passing SI eye test for DCE11
1853 * The setting values are varied based on board revision and port id
1854 * Therefore the setting values of each ports is passed by sbios.
1857 // Check if current bios contains ext Hdmi settings
1858 if (integrated_info->gpu_cap_info & 0x20) {
1860 case ENGINE_ID_DIGA:
1861 settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr;
1862 settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;
1863 settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num;
1864 memmove(settings->reg_settings,
1865 integrated_info->dp0_ext_hdmi_reg_settings,
1866 sizeof(integrated_info->dp0_ext_hdmi_reg_settings));
1867 memmove(settings->reg_settings_6g,
1868 integrated_info->dp0_ext_hdmi_6g_reg_settings,
1869 sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings));
1872 case ENGINE_ID_DIGB:
1873 settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr;
1874 settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;
1875 settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num;
1876 memmove(settings->reg_settings,
1877 integrated_info->dp1_ext_hdmi_reg_settings,
1878 sizeof(integrated_info->dp1_ext_hdmi_reg_settings));
1879 memmove(settings->reg_settings_6g,
1880 integrated_info->dp1_ext_hdmi_6g_reg_settings,
1881 sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings));
1884 case ENGINE_ID_DIGC:
1885 settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr;
1886 settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;
1887 settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num;
1888 memmove(settings->reg_settings,
1889 integrated_info->dp2_ext_hdmi_reg_settings,
1890 sizeof(integrated_info->dp2_ext_hdmi_reg_settings));
1891 memmove(settings->reg_settings_6g,
1892 integrated_info->dp2_ext_hdmi_6g_reg_settings,
1893 sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings));
1896 case ENGINE_ID_DIGD:
1897 settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr;
1898 settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;
1899 settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num;
1900 memmove(settings->reg_settings,
1901 integrated_info->dp3_ext_hdmi_reg_settings,
1902 sizeof(integrated_info->dp3_ext_hdmi_reg_settings));
1903 memmove(settings->reg_settings_6g,
1904 integrated_info->dp3_ext_hdmi_6g_reg_settings,
1905 sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings));
1912 if (result == true) {
1913 // Validate settings from bios integrated info table
1914 if (settings->slv_addr == 0)
1916 if (settings->reg_num > 9)
1918 if (settings->reg_num_6g > 3)
1921 for (i = 0; i < settings->reg_num; i++) {
1922 if (settings->reg_settings[i].i2c_reg_index > 0x20)
1926 for (i = 0; i < settings->reg_num_6g; i++) {
1927 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20)
1936 static bool i2c_write(struct pipe_ctx *pipe_ctx,
1937 uint8_t address, uint8_t *buffer, uint32_t length)
1939 struct i2c_command cmd = {0};
1940 struct i2c_payload payload = {0};
1942 memset(&payload, 0, sizeof(payload));
1943 memset(&cmd, 0, sizeof(cmd));
1945 cmd.number_of_payloads = 1;
1946 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
1947 cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;
1949 payload.address = address;
1950 payload.data = buffer;
1951 payload.length = length;
1952 payload.write = true;
1953 cmd.payloads = &payload;
1955 if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx,
1956 pipe_ctx->stream->link, &cmd))
1962 static void write_i2c_retimer_setting(
1963 struct pipe_ctx *pipe_ctx,
1965 bool is_over_340mhz,
1966 struct ext_hdmi_settings *settings)
1968 uint8_t slave_address = (settings->slv_addr >> 1);
1970 const uint8_t apply_rx_tx_change = 0x4;
1971 uint8_t offset = 0xA;
1974 bool i2c_success = false;
1975 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1977 memset(&buffer, 0, sizeof(buffer));
1979 /* Start Ext-Hdmi programming*/
1981 for (i = 0; i < settings->reg_num; i++) {
1982 /* Apply 3G settings */
1983 if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
1985 buffer[0] = settings->reg_settings[i].i2c_reg_index;
1986 buffer[1] = settings->reg_settings[i].i2c_reg_val;
1987 i2c_success = i2c_write(pipe_ctx, slave_address,
1988 buffer, sizeof(buffer));
1989 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1990 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
1991 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1994 goto i2c_write_fail;
1996 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
1997 * needs to be set to 1 on every 0xA-0xC write.
1999 if (settings->reg_settings[i].i2c_reg_index == 0xA ||
2000 settings->reg_settings[i].i2c_reg_index == 0xB ||
2001 settings->reg_settings[i].i2c_reg_index == 0xC) {
2003 /* Query current value from offset 0xA */
2004 if (settings->reg_settings[i].i2c_reg_index == 0xA)
2005 value = settings->reg_settings[i].i2c_reg_val;
2008 dal_ddc_service_query_ddc_data(
2009 pipe_ctx->stream->link->ddc,
2010 slave_address, &offset, 1, &value, 1);
2012 goto i2c_write_fail;
2016 /* Set APPLY_RX_TX_CHANGE bit to 1 */
2017 buffer[1] = value | apply_rx_tx_change;
2018 i2c_success = i2c_write(pipe_ctx, slave_address,
2019 buffer, sizeof(buffer));
2020 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2021 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2022 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2024 goto i2c_write_fail;
2029 /* Apply 3G settings */
2030 if (is_over_340mhz) {
2031 for (i = 0; i < settings->reg_num_6g; i++) {
2032 /* Apply 3G settings */
2033 if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
2035 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index;
2036 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val;
2037 i2c_success = i2c_write(pipe_ctx, slave_address,
2038 buffer, sizeof(buffer));
2039 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\
2040 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2041 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2044 goto i2c_write_fail;
2046 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
2047 * needs to be set to 1 on every 0xA-0xC write.
2049 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA ||
2050 settings->reg_settings_6g[i].i2c_reg_index == 0xB ||
2051 settings->reg_settings_6g[i].i2c_reg_index == 0xC) {
2053 /* Query current value from offset 0xA */
2054 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA)
2055 value = settings->reg_settings_6g[i].i2c_reg_val;
2058 dal_ddc_service_query_ddc_data(
2059 pipe_ctx->stream->link->ddc,
2060 slave_address, &offset, 1, &value, 1);
2062 goto i2c_write_fail;
2066 /* Set APPLY_RX_TX_CHANGE bit to 1 */
2067 buffer[1] = value | apply_rx_tx_change;
2068 i2c_success = i2c_write(pipe_ctx, slave_address,
2069 buffer, sizeof(buffer));
2070 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2071 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2072 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2074 goto i2c_write_fail;
2081 /* Program additional settings if using 640x480 resolution */
2083 /* Write offset 0xFF to 0x01 */
2086 i2c_success = i2c_write(pipe_ctx, slave_address,
2087 buffer, sizeof(buffer));
2088 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2089 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2090 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2092 goto i2c_write_fail;
2094 /* Write offset 0x00 to 0x23 */
2097 i2c_success = i2c_write(pipe_ctx, slave_address,
2098 buffer, sizeof(buffer));
2099 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2100 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2101 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2103 goto i2c_write_fail;
2105 /* Write offset 0xff to 0x00 */
2108 i2c_success = i2c_write(pipe_ctx, slave_address,
2109 buffer, sizeof(buffer));
2110 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2111 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2112 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2114 goto i2c_write_fail;
2121 DC_LOG_DEBUG("Set retimer failed");
2124 static void write_i2c_default_retimer_setting(
2125 struct pipe_ctx *pipe_ctx,
2127 bool is_over_340mhz)
2129 uint8_t slave_address = (0xBA >> 1);
2131 bool i2c_success = false;
2132 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2134 memset(&buffer, 0, sizeof(buffer));
2136 /* Program Slave Address for tuning single integrity */
2137 /* Write offset 0x0A to 0x13 */
2140 i2c_success = i2c_write(pipe_ctx, slave_address,
2141 buffer, sizeof(buffer));
2142 RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\
2143 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2144 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2146 goto i2c_write_fail;
2148 /* Write offset 0x0A to 0x17 */
2151 i2c_success = i2c_write(pipe_ctx, slave_address,
2152 buffer, sizeof(buffer));
2153 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2154 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2155 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2157 goto i2c_write_fail;
2159 /* Write offset 0x0B to 0xDA or 0xD8 */
2161 buffer[1] = is_over_340mhz ? 0xDA : 0xD8;
2162 i2c_success = i2c_write(pipe_ctx, slave_address,
2163 buffer, sizeof(buffer));
2164 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2165 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2166 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2168 goto i2c_write_fail;
2170 /* Write offset 0x0A to 0x17 */
2173 i2c_success = i2c_write(pipe_ctx, slave_address,
2174 buffer, sizeof(buffer));
2175 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2176 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2177 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2179 goto i2c_write_fail;
2181 /* Write offset 0x0C to 0x1D or 0x91 */
2183 buffer[1] = is_over_340mhz ? 0x1D : 0x91;
2184 i2c_success = i2c_write(pipe_ctx, slave_address,
2185 buffer, sizeof(buffer));
2186 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2187 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2188 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2190 goto i2c_write_fail;
2192 /* Write offset 0x0A to 0x17 */
2195 i2c_success = i2c_write(pipe_ctx, slave_address,
2196 buffer, sizeof(buffer));
2197 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2198 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2199 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2201 goto i2c_write_fail;
2205 /* Program additional settings if using 640x480 resolution */
2207 /* Write offset 0xFF to 0x01 */
2210 i2c_success = i2c_write(pipe_ctx, slave_address,
2211 buffer, sizeof(buffer));
2212 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2213 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2214 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2216 goto i2c_write_fail;
2218 /* Write offset 0x00 to 0x23 */
2221 i2c_success = i2c_write(pipe_ctx, slave_address,
2222 buffer, sizeof(buffer));
2223 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2224 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2225 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2227 goto i2c_write_fail;
2229 /* Write offset 0xff to 0x00 */
2232 i2c_success = i2c_write(pipe_ctx, slave_address,
2233 buffer, sizeof(buffer));
2234 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\
2235 offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n",
2236 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2238 goto i2c_write_fail;
2244 DC_LOG_DEBUG("Set default retimer failed");
2247 static void write_i2c_redriver_setting(
2248 struct pipe_ctx *pipe_ctx,
2249 bool is_over_340mhz)
2251 uint8_t slave_address = (0xF0 >> 1);
2253 bool i2c_success = false;
2254 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2256 memset(&buffer, 0, sizeof(buffer));
2258 // Program Slave Address for tuning single integrity
2262 buffer[6] = is_over_340mhz ? 0x4E : 0x4A;
2264 i2c_success = i2c_write(pipe_ctx, slave_address,
2265 buffer, sizeof(buffer));
2266 RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\
2267 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\
2268 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\
2269 i2c_success = %d\n",
2270 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0);
2273 DC_LOG_DEBUG("Set redriver failed");
2276 static void disable_link(struct dc_link *link, enum signal_type signal)
2279 * TODO: implement call for dp_set_hw_test_pattern
2280 * it is needed for compliance testing
2283 /* Here we need to specify that encoder output settings
2284 * need to be calculated as for the set mode,
2285 * it will lead to querying dynamic link capabilities
2286 * which should be done before enable output
2289 if (dc_is_dp_signal(signal)) {
2291 if (dc_is_dp_sst_signal(signal))
2292 dp_disable_link_phy(link, signal);
2294 dp_disable_link_phy_mst(link, signal);
2296 if (dc_is_dp_sst_signal(signal) ||
2297 link->mst_stream_alloc_table.stream_count == 0) {
2298 dp_set_fec_enable(link, false);
2299 dp_set_fec_ready(link, false);
2302 if (signal != SIGNAL_TYPE_VIRTUAL)
2303 link->link_enc->funcs->disable_output(link->link_enc, signal);
2306 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2307 /* MST disable link only when no stream use the link */
2308 if (link->mst_stream_alloc_table.stream_count <= 0)
2309 link->link_status.link_active = false;
2311 link->link_status.link_active = false;
2315 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
2317 struct dc_stream_state *stream = pipe_ctx->stream;
2318 struct dc_link *link = stream->link;
2319 enum dc_color_depth display_color_depth;
2320 enum engine_id eng_id;
2321 struct ext_hdmi_settings settings = {0};
2322 bool is_over_340mhz = false;
2323 bool is_vga_mode = (stream->timing.h_addressable == 640)
2324 && (stream->timing.v_addressable == 480);
2326 if (stream->phy_pix_clk == 0)
2327 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2328 if (stream->phy_pix_clk > 340000)
2329 is_over_340mhz = true;
2331 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
2332 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps &
2333 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
2334 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
2335 /* DP159, Retimer settings */
2336 eng_id = pipe_ctx->stream_res.stream_enc->id;
2338 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) {
2339 write_i2c_retimer_setting(pipe_ctx,
2340 is_vga_mode, is_over_340mhz, &settings);
2342 write_i2c_default_retimer_setting(pipe_ctx,
2343 is_vga_mode, is_over_340mhz);
2345 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
2346 /* PI3EQX1204, Redriver settings */
2347 write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);
2351 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2352 dal_ddc_service_write_scdc_data(
2354 stream->phy_pix_clk,
2355 stream->timing.flags.LTE_340MCSC_SCRAMBLE);
2357 memset(&stream->link->cur_link_settings, 0,
2358 sizeof(struct dc_link_settings));
2360 display_color_depth = stream->timing.display_color_depth;
2361 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
2362 display_color_depth = COLOR_DEPTH_888;
2364 link->link_enc->funcs->enable_tmds_output(
2366 pipe_ctx->clock_source->id,
2367 display_color_depth,
2368 pipe_ctx->stream->signal,
2369 stream->phy_pix_clk);
2371 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2372 dal_ddc_service_read_scdc_data(link->ddc);
2375 static void enable_link_lvds(struct pipe_ctx *pipe_ctx)
2377 struct dc_stream_state *stream = pipe_ctx->stream;
2378 struct dc_link *link = stream->link;
2380 if (stream->phy_pix_clk == 0)
2381 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2383 memset(&stream->link->cur_link_settings, 0,
2384 sizeof(struct dc_link_settings));
2386 link->link_enc->funcs->enable_lvds_output(
2388 pipe_ctx->clock_source->id,
2389 stream->phy_pix_clk);
2393 /****************************enable_link***********************************/
2394 static enum dc_status enable_link(
2395 struct dc_state *state,
2396 struct pipe_ctx *pipe_ctx)
2398 enum dc_status status = DC_ERROR_UNEXPECTED;
2399 struct dc_stream_state *stream = pipe_ctx->stream;
2400 struct dc_link *link = stream->link;
2402 /* There's some scenarios where driver is unloaded with display
2403 * still enabled. When driver is reloaded, it may cause a display
2404 * to not light up if there is a mismatch between old and new
2405 * link settings. Need to call disable first before enabling at
2406 * new link settings.
2408 if (link->link_status.link_active) {
2409 disable_link(link, pipe_ctx->stream->signal);
2412 switch (pipe_ctx->stream->signal) {
2413 case SIGNAL_TYPE_DISPLAY_PORT:
2414 status = enable_link_dp(state, pipe_ctx);
2416 case SIGNAL_TYPE_EDP:
2417 status = enable_link_edp(state, pipe_ctx);
2419 case SIGNAL_TYPE_DISPLAY_PORT_MST:
2420 status = enable_link_dp_mst(state, pipe_ctx);
2423 case SIGNAL_TYPE_DVI_SINGLE_LINK:
2424 case SIGNAL_TYPE_DVI_DUAL_LINK:
2425 case SIGNAL_TYPE_HDMI_TYPE_A:
2426 enable_link_hdmi(pipe_ctx);
2429 case SIGNAL_TYPE_LVDS:
2430 enable_link_lvds(pipe_ctx);
2433 case SIGNAL_TYPE_VIRTUAL:
2440 if (status == DC_OK)
2441 pipe_ctx->stream->link->link_status.link_active = true;
2446 static uint32_t get_timing_pixel_clock_100hz(const struct dc_crtc_timing *timing)
2449 uint32_t pxl_clk = timing->pix_clk_100hz;
2451 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2453 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
2454 pxl_clk = pxl_clk * 2 / 3;
2456 if (timing->display_color_depth == COLOR_DEPTH_101010)
2457 pxl_clk = pxl_clk * 10 / 8;
2458 else if (timing->display_color_depth == COLOR_DEPTH_121212)
2459 pxl_clk = pxl_clk * 12 / 8;
2464 static bool dp_active_dongle_validate_timing(
2465 const struct dc_crtc_timing *timing,
2466 const struct dpcd_caps *dpcd_caps)
2468 const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps;
2470 switch (dpcd_caps->dongle_type) {
2471 case DISPLAY_DONGLE_DP_VGA_CONVERTER:
2472 case DISPLAY_DONGLE_DP_DVI_CONVERTER:
2473 case DISPLAY_DONGLE_DP_DVI_DONGLE:
2474 if (timing->pixel_encoding == PIXEL_ENCODING_RGB)
2482 if (dpcd_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER ||
2483 dongle_caps->extendedCapValid == false)
2486 /* Check Pixel Encoding */
2487 switch (timing->pixel_encoding) {
2488 case PIXEL_ENCODING_RGB:
2489 case PIXEL_ENCODING_YCBCR444:
2491 case PIXEL_ENCODING_YCBCR422:
2492 if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through)
2495 case PIXEL_ENCODING_YCBCR420:
2496 if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through)
2500 /* Invalid Pixel Encoding*/
2504 switch (timing->display_color_depth) {
2505 case COLOR_DEPTH_666:
2506 case COLOR_DEPTH_888:
2507 /*888 and 666 should always be supported*/
2509 case COLOR_DEPTH_101010:
2510 if (dongle_caps->dp_hdmi_max_bpc < 10)
2513 case COLOR_DEPTH_121212:
2514 if (dongle_caps->dp_hdmi_max_bpc < 12)
2517 case COLOR_DEPTH_141414:
2518 case COLOR_DEPTH_161616:
2520 /* These color depths are currently not supported */
2524 if (get_timing_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk_in_khz * 10))
2530 enum dc_status dc_link_validate_mode_timing(
2531 const struct dc_stream_state *stream,
2532 struct dc_link *link,
2533 const struct dc_crtc_timing *timing)
2535 uint32_t max_pix_clk = stream->link->dongle_max_pix_clk * 10;
2536 struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
2538 /* A hack to avoid failing any modes for EDID override feature on
2539 * topology change such as lower quality cable for DP or different dongle
2541 if (link->remote_sinks[0] && link->remote_sinks[0]->sink_signal == SIGNAL_TYPE_VIRTUAL)
2544 /* Passive Dongle */
2545 if (max_pix_clk != 0 && get_timing_pixel_clock_100hz(timing) > max_pix_clk)
2546 return DC_EXCEED_DONGLE_CAP;
2549 if (!dp_active_dongle_validate_timing(timing, dpcd_caps))
2550 return DC_EXCEED_DONGLE_CAP;
2552 switch (stream->signal) {
2553 case SIGNAL_TYPE_EDP:
2554 case SIGNAL_TYPE_DISPLAY_PORT:
2555 if (!dp_validate_mode_timing(
2558 return DC_NO_DP_LINK_BANDWIDTH;
2568 static struct abm *get_abm_from_stream_res(const struct dc_link *link)
2571 struct dc *dc = NULL;
2572 struct abm *abm = NULL;
2574 if (!link || !link->ctx)
2579 for (i = 0; i < MAX_PIPES; i++) {
2580 struct pipe_ctx pipe_ctx = dc->current_state->res_ctx.pipe_ctx[i];
2581 struct dc_stream_state *stream = pipe_ctx.stream;
2583 if (stream && stream->link == link) {
2584 abm = pipe_ctx.stream_res.abm;
2591 int dc_link_get_backlight_level(const struct dc_link *link)
2594 struct abm *abm = get_abm_from_stream_res(link);
2596 if (abm == NULL || abm->funcs->get_current_backlight == NULL)
2597 return DC_ERROR_UNEXPECTED;
2599 return (int) abm->funcs->get_current_backlight(abm);
2602 int dc_link_get_target_backlight_pwm(const struct dc_link *link)
2604 struct abm *abm = get_abm_from_stream_res(link);
2606 if (abm == NULL || abm->funcs->get_target_backlight == NULL)
2607 return DC_ERROR_UNEXPECTED;
2609 return (int) abm->funcs->get_target_backlight(abm);
2612 static struct pipe_ctx *get_pipe_from_link(const struct dc_link *link)
2615 struct dc *dc = link->ctx->dc;
2616 struct pipe_ctx *pipe_ctx = NULL;
2618 for (i = 0; i < MAX_PIPES; i++) {
2619 if (dc->current_state->res_ctx.pipe_ctx[i].stream) {
2620 if (dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) {
2621 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
2630 bool dc_link_set_backlight_level(const struct dc_link *link,
2631 uint32_t backlight_pwm_u16_16,
2632 uint32_t frame_ramp)
2634 struct dc *dc = link->ctx->dc;
2636 DC_LOGGER_INIT(link->ctx->logger);
2637 DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",
2638 backlight_pwm_u16_16, backlight_pwm_u16_16);
2640 if (dc_is_embedded_signal(link->connector_signal)) {
2641 struct pipe_ctx *pipe_ctx = get_pipe_from_link(link);
2644 /* Disable brightness ramping when the display is blanked
2645 * as it can hang the DMCU
2647 if (pipe_ctx->plane_state == NULL)
2653 dc->hwss.set_backlight_level(
2655 backlight_pwm_u16_16,
2661 bool dc_link_set_psr_allow_active(struct dc_link *link, bool allow_active,
2662 bool wait, bool force_static)
2664 struct dc *dc = link->ctx->dc;
2665 struct dmcu *dmcu = dc->res_pool->dmcu;
2666 struct dmub_psr *psr = dc->res_pool->psr;
2668 if (psr == NULL && force_static)
2671 link->psr_settings.psr_allow_active = allow_active;
2673 if (psr != NULL && link->psr_settings.psr_feature_enabled) {
2674 if (force_static && psr->funcs->psr_force_static)
2675 psr->funcs->psr_force_static(psr);
2676 psr->funcs->psr_enable(psr, allow_active, wait);
2677 } else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) && link->psr_settings.psr_feature_enabled)
2678 dmcu->funcs->set_psr_enable(dmcu, allow_active, wait);
2685 bool dc_link_get_psr_state(const struct dc_link *link, enum dc_psr_state *state)
2687 struct dc *dc = link->ctx->dc;
2688 struct dmcu *dmcu = dc->res_pool->dmcu;
2689 struct dmub_psr *psr = dc->res_pool->psr;
2691 if (psr != NULL && link->psr_settings.psr_feature_enabled)
2692 psr->funcs->psr_get_state(psr, state);
2693 else if (dmcu != NULL && link->psr_settings.psr_feature_enabled)
2694 dmcu->funcs->get_psr_state(dmcu, state);
2699 static inline enum physical_phy_id
2700 transmitter_to_phy_id(enum transmitter transmitter_value)
2702 switch (transmitter_value) {
2703 case TRANSMITTER_UNIPHY_A:
2705 case TRANSMITTER_UNIPHY_B:
2707 case TRANSMITTER_UNIPHY_C:
2709 case TRANSMITTER_UNIPHY_D:
2711 case TRANSMITTER_UNIPHY_E:
2713 case TRANSMITTER_UNIPHY_F:
2715 case TRANSMITTER_NUTMEG_CRT:
2717 case TRANSMITTER_TRAVIS_CRT:
2719 case TRANSMITTER_TRAVIS_LCD:
2721 case TRANSMITTER_UNIPHY_G:
2723 case TRANSMITTER_COUNT:
2725 case TRANSMITTER_UNKNOWN:
2726 return PHYLD_UNKNOWN;
2728 WARN_ONCE(1, "Unknown transmitter value %d\n",
2730 return PHYLD_UNKNOWN;
2734 bool dc_link_setup_psr(struct dc_link *link,
2735 const struct dc_stream_state *stream, struct psr_config *psr_config,
2736 struct psr_context *psr_context)
2740 struct dmub_psr *psr;
2742 /* updateSinkPsrDpcdConfig*/
2743 union dpcd_psr_configuration psr_configuration;
2745 psr_context->controllerId = CONTROLLER_ID_UNDEFINED;
2751 dmcu = dc->res_pool->dmcu;
2752 psr = dc->res_pool->psr;
2758 memset(&psr_configuration, 0, sizeof(psr_configuration));
2760 psr_configuration.bits.ENABLE = 1;
2761 psr_configuration.bits.CRC_VERIFICATION = 1;
2762 psr_configuration.bits.FRAME_CAPTURE_INDICATION =
2763 psr_config->psr_frame_capture_indication_req;
2765 /* Check for PSR v2*/
2766 if (psr_config->psr_version == 0x2) {
2767 /* For PSR v2 selective update.
2768 * Indicates whether sink should start capturing
2769 * immediately following active scan line,
2770 * or starting with the 2nd active scan line.
2772 psr_configuration.bits.LINE_CAPTURE_INDICATION = 0;
2773 /*For PSR v2, determines whether Sink should generate
2774 * IRQ_HPD when CRC mismatch is detected.
2776 psr_configuration.bits.IRQ_HPD_WITH_CRC_ERROR = 1;
2779 dm_helpers_dp_write_dpcd(
2783 &psr_configuration.raw,
2784 sizeof(psr_configuration.raw));
2786 psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
2787 psr_context->transmitterId = link->link_enc->transmitter;
2788 psr_context->engineId = link->link_enc->preferred_engine;
2790 for (i = 0; i < MAX_PIPES; i++) {
2791 if (dc->current_state->res_ctx.pipe_ctx[i].stream
2793 /* dmcu -1 for all controller id values,
2796 psr_context->controllerId =
2797 dc->current_state->res_ctx.
2798 pipe_ctx[i].stream_res.tg->inst + 1;
2803 /* Hardcoded for now. Can be Pcie or Uniphy (or Unknown)*/
2804 psr_context->phyType = PHY_TYPE_UNIPHY;
2805 /*PhyId is associated with the transmitter id*/
2806 psr_context->smuPhyId =
2807 transmitter_to_phy_id(link->link_enc->transmitter);
2809 psr_context->crtcTimingVerticalTotal = stream->timing.v_total;
2810 psr_context->vsync_rate_hz = div64_u64(div64_u64((stream->
2811 timing.pix_clk_100hz * 100),
2812 stream->timing.v_total),
2813 stream->timing.h_total);
2815 psr_context->psrSupportedDisplayConfig = true;
2816 psr_context->psrExitLinkTrainingRequired =
2817 psr_config->psr_exit_link_training_required;
2818 psr_context->sdpTransmitLineNumDeadline =
2819 psr_config->psr_sdp_transmit_line_num_deadline;
2820 psr_context->psrFrameCaptureIndicationReq =
2821 psr_config->psr_frame_capture_indication_req;
2823 psr_context->skipPsrWaitForPllLock = 0; /* only = 1 in KV */
2825 psr_context->numberOfControllers =
2826 link->dc->res_pool->timing_generator_count;
2828 psr_context->rfb_update_auto_en = true;
2830 /* 2 frames before enter PSR. */
2831 psr_context->timehyst_frames = 2;
2833 * (units in 100 lines, i.e. a value of 1 represents 100 lines)
2835 psr_context->hyst_lines = stream->timing.v_total / 2 / 100;
2836 psr_context->aux_repeats = 10;
2838 psr_context->psr_level.u32all = 0;
2840 /*skip power down the single pipe since it blocks the cstate*/
2841 if (link->ctx->asic_id.chip_family >= FAMILY_RV)
2842 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
2844 /* SMU will perform additional powerdown sequence.
2845 * For unsupported ASICs, set psr_level flag to skip PSR
2846 * static screen notification to SMU.
2847 * (Always set for DAL2, did not check ASIC)
2849 psr_context->allow_smu_optimizations = psr_config->allow_smu_optimizations;
2850 psr_context->allow_multi_disp_optimizations = psr_config->allow_multi_disp_optimizations;
2852 /* Complete PSR entry before aborting to prevent intermittent
2853 * freezes on certain eDPs
2855 psr_context->psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1;
2857 /* Controls additional delay after remote frame capture before
2858 * continuing power down, default = 0
2860 psr_context->frame_delay = 0;
2863 link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr, link, psr_context);
2865 link->psr_settings.psr_feature_enabled = dmcu->funcs->setup_psr(dmcu, link, psr_context);
2867 /* psr_enabled == 0 indicates setup_psr did not succeed, but this
2868 * should not happen since firmware should be running at this point
2870 if (link->psr_settings.psr_feature_enabled == 0)
2877 void dc_link_get_psr_residency(const struct dc_link *link, uint32_t *residency)
2879 struct dc *dc = link->ctx->dc;
2880 struct dmub_psr *psr = dc->res_pool->psr;
2882 // PSR residency measurements only supported on DMCUB
2883 if (psr != NULL && link->psr_settings.psr_feature_enabled)
2884 psr->funcs->psr_get_residency(psr, residency);
2889 const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
2891 return &link->link_status;
2894 void core_link_resume(struct dc_link *link)
2896 if (link->connector_signal != SIGNAL_TYPE_VIRTUAL)
2897 program_hpd_filter(link);
2900 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
2902 struct fixed31_32 mbytes_per_sec;
2903 uint32_t link_rate_in_mbytes_per_sec = dc_link_bandwidth_kbps(stream->link,
2904 &stream->link->cur_link_settings);
2905 link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */
2907 mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec);
2909 return dc_fixpt_div_int(mbytes_per_sec, 54);
2912 static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps)
2914 struct fixed31_32 peak_kbps;
2915 uint32_t numerator = 0;
2916 uint32_t denominator = 1;
2919 * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
2920 * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
2921 * common multiplier to render an integer PBN for all link rate/lane
2922 * counts combinations
2924 * peak_kbps *= (1006/1000)
2925 * peak_kbps *= (64/54)
2926 * peak_kbps *= 8 convert to bytes
2929 numerator = 64 * PEAK_FACTOR_X1000;
2930 denominator = 54 * 8 * 1000 * 1000;
2932 peak_kbps = dc_fixpt_from_fraction(kbps, denominator);
2937 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
2941 kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing);
2942 return get_pbn_from_bw_in_kbps(kbps);
2945 static void update_mst_stream_alloc_table(
2946 struct dc_link *link,
2947 struct stream_encoder *stream_enc,
2948 const struct dp_mst_stream_allocation_table *proposed_table)
2950 struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = {
2952 struct link_mst_stream_allocation *dc_alloc;
2957 /* if DRM proposed_table has more than one new payload */
2958 ASSERT(proposed_table->stream_count -
2959 link->mst_stream_alloc_table.stream_count < 2);
2961 /* copy proposed_table to link, add stream encoder */
2962 for (i = 0; i < proposed_table->stream_count; i++) {
2964 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) {
2966 &link->mst_stream_alloc_table.stream_allocations[j];
2968 if (dc_alloc->vcp_id ==
2969 proposed_table->stream_allocations[i].vcp_id) {
2971 work_table[i] = *dc_alloc;
2972 work_table[i].slot_count = proposed_table->stream_allocations[i].slot_count;
2973 break; /* exit j loop */
2978 if (j == link->mst_stream_alloc_table.stream_count) {
2979 work_table[i].vcp_id =
2980 proposed_table->stream_allocations[i].vcp_id;
2981 work_table[i].slot_count =
2982 proposed_table->stream_allocations[i].slot_count;
2983 work_table[i].stream_enc = stream_enc;
2987 /* update link->mst_stream_alloc_table with work_table */
2988 link->mst_stream_alloc_table.stream_count =
2989 proposed_table->stream_count;
2990 for (i = 0; i < MAX_CONTROLLER_NUM; i++)
2991 link->mst_stream_alloc_table.stream_allocations[i] =
2995 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table
2996 * because stream_encoder is not exposed to dm
2998 enum dc_status dc_link_allocate_mst_payload(struct pipe_ctx *pipe_ctx)
3000 struct dc_stream_state *stream = pipe_ctx->stream;
3001 struct dc_link *link = stream->link;
3002 struct link_encoder *link_encoder = link->link_enc;
3003 struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
3004 struct dp_mst_stream_allocation_table proposed_table = {0};
3005 struct fixed31_32 avg_time_slots_per_mtp;
3006 struct fixed31_32 pbn;
3007 struct fixed31_32 pbn_per_slot;
3009 enum act_return_status ret;
3010 DC_LOGGER_INIT(link->ctx->logger);
3012 /* enable_link_dp_mst already check link->enabled_stream_count
3013 * and stream is in link->stream[]. This is called during set mode,
3014 * stream_enc is available.
3017 /* get calculate VC payload for stream: stream_alloc */
3018 if (dm_helpers_dp_mst_write_payload_allocation_table(
3023 update_mst_stream_alloc_table(
3024 link, pipe_ctx->stream_res.stream_enc, &proposed_table);
3027 DC_LOG_WARNING("Failed to update"
3028 "MST allocation table for"
3030 pipe_ctx->pipe_idx);
3033 "stream_count: %d: \n ",
3035 link->mst_stream_alloc_table.stream_count);
3037 for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3038 DC_LOG_MST("stream_enc[%d]: %p "
3039 "stream[%d].vcp_id: %d "
3040 "stream[%d].slot_count: %d\n",
3042 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3044 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3046 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3049 ASSERT(proposed_table.stream_count > 0);
3051 /* program DP source TX for payload */
3052 link_encoder->funcs->update_mst_stream_allocation_table(
3054 &link->mst_stream_alloc_table);
3056 /* send down message */
3057 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3061 if (ret != ACT_LINK_LOST) {
3062 dm_helpers_dp_mst_send_payload_allocation(
3068 /* slot X.Y for only current stream */
3069 pbn_per_slot = get_pbn_per_slot(stream);
3070 if (pbn_per_slot.value == 0) {
3071 DC_LOG_ERROR("Failure: pbn_per_slot==0 not allowed. Cannot continue, returning DC_UNSUPPORTED_VALUE.\n");
3072 return DC_UNSUPPORTED_VALUE;
3074 pbn = get_pbn_from_timing(pipe_ctx);
3075 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
3077 stream_encoder->funcs->set_throttled_vcp_size(
3079 avg_time_slots_per_mtp);
3085 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
3087 struct dc_stream_state *stream = pipe_ctx->stream;
3088 struct dc_link *link = stream->link;
3089 struct link_encoder *link_encoder = link->link_enc;
3090 struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
3091 struct dp_mst_stream_allocation_table proposed_table = {0};
3092 struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
3094 bool mst_mode = (link->type == dc_connection_mst_branch);
3095 DC_LOGGER_INIT(link->ctx->logger);
3097 /* deallocate_mst_payload is called before disable link. When mode or
3098 * disable/enable monitor, new stream is created which is not in link
3099 * stream[] yet. For this, payload is not allocated yet, so de-alloc
3100 * should not done. For new mode set, map_resources will get engine
3101 * for new stream, so stream_enc->id should be validated until here.
3105 stream_encoder->funcs->set_throttled_vcp_size(
3107 avg_time_slots_per_mtp);
3109 /* TODO: which component is responsible for remove payload table? */
3111 if (dm_helpers_dp_mst_write_payload_allocation_table(
3117 update_mst_stream_alloc_table(
3118 link, pipe_ctx->stream_res.stream_enc, &proposed_table);
3121 DC_LOG_WARNING("Failed to update"
3122 "MST allocation table for"
3124 pipe_ctx->pipe_idx);
3129 "stream_count: %d: ",
3131 link->mst_stream_alloc_table.stream_count);
3133 for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3134 DC_LOG_MST("stream_enc[%d]: %p "
3135 "stream[%d].vcp_id: %d "
3136 "stream[%d].slot_count: %d\n",
3138 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3140 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3142 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3145 link_encoder->funcs->update_mst_stream_allocation_table(
3147 &link->mst_stream_alloc_table);
3150 dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3154 dm_helpers_dp_mst_send_payload_allocation(
3164 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3165 static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off)
3167 struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp;
3168 if (cp_psp && cp_psp->funcs.update_stream_config) {
3169 struct cp_psp_stream_config config = {0};
3170 enum dp_panel_mode panel_mode =
3171 dp_get_panel_mode(pipe_ctx->stream->link);
3173 config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst;
3174 config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst;
3175 config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst;
3176 config.dpms_off = dpms_off;
3177 config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context;
3178 config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP);
3179 config.mst_enabled = (pipe_ctx->stream->signal ==
3180 SIGNAL_TYPE_DISPLAY_PORT_MST);
3181 cp_psp->funcs.update_stream_config(cp_psp->handle, &config);
3186 void core_link_enable_stream(
3187 struct dc_state *state,
3188 struct pipe_ctx *pipe_ctx)
3190 struct dc *dc = pipe_ctx->stream->ctx->dc;
3191 struct dc_stream_state *stream = pipe_ctx->stream;
3192 enum dc_status status;
3193 #if defined(CONFIG_DRM_AMD_DC_DCN)
3194 enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO;
3196 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
3198 if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
3199 dc_is_virtual_signal(pipe_ctx->stream->signal))
3202 if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) {
3203 stream->link->link_enc->funcs->setup(
3204 stream->link->link_enc,
3205 pipe_ctx->stream->signal);
3206 pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync(
3207 pipe_ctx->stream_res.stream_enc,
3208 pipe_ctx->stream_res.tg->inst,
3209 stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE);
3212 if (dc_is_dp_signal(pipe_ctx->stream->signal))
3213 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(
3214 pipe_ctx->stream_res.stream_enc,
3216 stream->output_color_space,
3217 stream->use_vsc_sdp_for_colorimetry,
3218 stream->link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
3220 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
3221 pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute(
3222 pipe_ctx->stream_res.stream_enc,
3224 stream->phy_pix_clk,
3225 pipe_ctx->stream_res.audio != NULL);
3227 pipe_ctx->stream->link->link_state_valid = true;
3229 #if defined(CONFIG_DRM_AMD_DC_DCN)
3230 if (pipe_ctx->stream_res.tg->funcs->set_out_mux)
3231 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest);
3234 if (dc_is_dvi_signal(pipe_ctx->stream->signal))
3235 pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute(
3236 pipe_ctx->stream_res.stream_enc,
3238 (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
3241 if (dc_is_lvds_signal(pipe_ctx->stream->signal))
3242 pipe_ctx->stream_res.stream_enc->funcs->lvds_set_stream_attribute(
3243 pipe_ctx->stream_res.stream_enc,
3246 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
3247 bool apply_edp_fast_boot_optimization =
3248 pipe_ctx->stream->apply_edp_fast_boot_optimization;
3250 pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
3252 resource_build_info_frame(pipe_ctx);
3253 dc->hwss.update_info_frame(pipe_ctx);
3255 /* Do not touch link on seamless boot optimization. */
3256 if (pipe_ctx->stream->apply_seamless_boot_optimization) {
3257 pipe_ctx->stream->dpms_off = false;
3259 /* Still enable stream features & audio on seamless boot for DP external displays */
3260 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) {
3261 enable_stream_features(pipe_ctx);
3262 if (pipe_ctx->stream_res.audio != NULL) {
3263 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
3264 dc->hwss.enable_audio_stream(pipe_ctx);
3268 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3269 update_psp_stream_config(pipe_ctx, false);
3274 /* eDP lit up by bios already, no need to enable again. */
3275 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
3276 apply_edp_fast_boot_optimization &&
3277 !pipe_ctx->stream->timing.flags.DSC) {
3278 pipe_ctx->stream->dpms_off = false;
3279 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3280 update_psp_stream_config(pipe_ctx, false);
3285 if (pipe_ctx->stream->dpms_off)
3288 /* Have to setup DSC before DIG FE and BE are connected (which happens before the
3289 * link training). This is to make sure the bandwidth sent to DIG BE won't be
3290 * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag
3291 * will be automatically set at a later time when the video is enabled
3292 * (DP_VID_STREAM_EN = 1).
3294 if (pipe_ctx->stream->timing.flags.DSC) {
3295 if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
3296 dc_is_virtual_signal(pipe_ctx->stream->signal))
3297 dp_set_dsc_enable(pipe_ctx, true);
3300 status = enable_link(state, pipe_ctx);
3302 if (status != DC_OK) {
3303 DC_LOG_WARNING("enabling link %u failed: %d\n",
3304 pipe_ctx->stream->link->link_index,
3307 /* Abort stream enable *unless* the failure was due to
3308 * DP link training - some DP monitors will recover and
3309 * show the stream anyway. But MST displays can't proceed
3310 * without link training.
3312 if (status != DC_FAIL_DP_LINK_TRAINING ||
3313 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3314 BREAK_TO_DEBUGGER();
3319 /* turn off otg test pattern if enable */
3320 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
3321 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
3322 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
3323 COLOR_DEPTH_UNDEFINED);
3325 /* This second call is needed to reconfigure the DIG
3326 * as a workaround for the incorrect value being applied
3327 * from transmitter control.
3329 if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
3330 stream->link->link_enc->funcs->setup(
3331 stream->link->link_enc,
3332 pipe_ctx->stream->signal);
3334 dc->hwss.enable_stream(pipe_ctx);
3336 /* Set DPS PPS SDP (AKA "info frames") */
3337 if (pipe_ctx->stream->timing.flags.DSC) {
3338 if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
3339 dc_is_virtual_signal(pipe_ctx->stream->signal)) {
3340 dp_set_dsc_on_rx(pipe_ctx, true);
3341 dp_set_dsc_pps_sdp(pipe_ctx, true);
3345 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
3346 dc_link_allocate_mst_payload(pipe_ctx);
3348 dc->hwss.unblank_stream(pipe_ctx,
3349 &pipe_ctx->stream->link->cur_link_settings);
3351 if (stream->sink_patches.delay_ignore_msa > 0)
3352 msleep(stream->sink_patches.delay_ignore_msa);
3354 if (dc_is_dp_signal(pipe_ctx->stream->signal))
3355 enable_stream_features(pipe_ctx);
3356 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3357 update_psp_stream_config(pipe_ctx, false);
3360 dc->hwss.enable_audio_stream(pipe_ctx);
3362 } else { // if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
3363 if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
3364 dc_is_virtual_signal(pipe_ctx->stream->signal))
3365 dp_set_dsc_enable(pipe_ctx, true);
3369 if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
3370 core_link_set_avmute(pipe_ctx, false);
3374 void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
3376 struct dc *dc = pipe_ctx->stream->ctx->dc;
3377 struct dc_stream_state *stream = pipe_ctx->stream;
3378 struct dc_link *link = stream->sink->link;
3380 if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
3381 dc_is_virtual_signal(pipe_ctx->stream->signal))
3384 if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) {
3385 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
3386 core_link_set_avmute(pipe_ctx, true);
3389 dc->hwss.disable_audio_stream(pipe_ctx);
3391 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3392 update_psp_stream_config(pipe_ctx, true);
3394 dc->hwss.blank_stream(pipe_ctx);
3396 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
3397 deallocate_mst_payload(pipe_ctx);
3399 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
3400 struct ext_hdmi_settings settings = {0};
3401 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id;
3403 unsigned short masked_chip_caps = link->chip_caps &
3404 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
3405 //Need to inform that sink is going to use legacy HDMI mode.
3406 dal_ddc_service_write_scdc_data(
3408 165000,//vbios only handles 165Mhz.
3410 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
3411 /* DP159, Retimer settings */
3412 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings))
3413 write_i2c_retimer_setting(pipe_ctx,
3414 false, false, &settings);
3416 write_i2c_default_retimer_setting(pipe_ctx,
3418 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
3419 /* PI3EQX1204, Redriver settings */
3420 write_i2c_redriver_setting(pipe_ctx, false);
3424 disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
3426 dc->hwss.disable_stream(pipe_ctx);
3428 if (pipe_ctx->stream->timing.flags.DSC) {
3429 if (dc_is_dp_signal(pipe_ctx->stream->signal))
3430 dp_set_dsc_enable(pipe_ctx, false);
3434 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
3436 struct dc *dc = pipe_ctx->stream->ctx->dc;
3438 if (!dc_is_hdmi_signal(pipe_ctx->stream->signal))
3441 dc->hwss.set_avmute(pipe_ctx, enable);
3445 * dc_link_enable_hpd_filter:
3446 * If enable is true, programs HPD filter on associated HPD line using
3447 * delay_on_disconnect/delay_on_connect values dependent on
3448 * link->connector_signal
3450 * If enable is false, programs HPD filter on associated HPD line with no
3451 * delays on connect or disconnect
3453 * @link: pointer to the dc link
3454 * @enable: boolean specifying whether to enable hbd
3456 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)
3461 link->is_hpd_filter_disabled = false;
3462 program_hpd_filter(link);
3464 link->is_hpd_filter_disabled = true;
3465 /* Obtain HPD handle */
3466 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
3471 /* Setup HPD filtering */
3472 if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
3473 struct gpio_hpd_config config;
3475 config.delay_on_connect = 0;
3476 config.delay_on_disconnect = 0;
3478 dal_irq_setup_hpd_filter(hpd, &config);
3480 dal_gpio_close(hpd);
3482 ASSERT_CRITICAL(false);
3484 /* Release HPD handle */
3485 dal_gpio_destroy_irq(&hpd);
3489 uint32_t dc_bandwidth_in_kbps_from_timing(
3490 const struct dc_crtc_timing *timing)
3492 uint32_t bits_per_channel = 0;
3495 #if defined(CONFIG_DRM_AMD_DC_DCN)
3496 if (timing->flags.DSC) {
3497 return dc_dsc_stream_bandwidth_in_kbps(timing->pix_clk_100hz, timing->dsc_cfg.bits_per_pixel);
3501 switch (timing->display_color_depth) {
3502 case COLOR_DEPTH_666:
3503 bits_per_channel = 6;
3505 case COLOR_DEPTH_888:
3506 bits_per_channel = 8;
3508 case COLOR_DEPTH_101010:
3509 bits_per_channel = 10;
3511 case COLOR_DEPTH_121212:
3512 bits_per_channel = 12;
3514 case COLOR_DEPTH_141414:
3515 bits_per_channel = 14;
3517 case COLOR_DEPTH_161616:
3518 bits_per_channel = 16;
3521 ASSERT(bits_per_channel != 0);
3522 bits_per_channel = 8;
3526 kbps = timing->pix_clk_100hz / 10;
3527 kbps *= bits_per_channel;
3529 if (timing->flags.Y_ONLY != 1) {
3530 /*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
3532 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
3534 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
3535 kbps = kbps * 2 / 3;
3542 void dc_link_set_drive_settings(struct dc *dc,
3543 struct link_training_settings *lt_settings,
3544 const struct dc_link *link)
3549 for (i = 0; i < dc->link_count; i++) {
3550 if (dc->links[i] == link)
3554 if (i >= dc->link_count)
3555 ASSERT_CRITICAL(false);
3557 dc_link_dp_set_drive_settings(dc->links[i], lt_settings);
3560 void dc_link_perform_link_training(struct dc *dc,
3561 struct dc_link_settings *link_setting,
3562 bool skip_video_pattern)
3566 for (i = 0; i < dc->link_count; i++)
3567 dc_link_dp_perform_link_training(
3570 skip_video_pattern);
3573 void dc_link_set_preferred_link_settings(struct dc *dc,
3574 struct dc_link_settings *link_setting,
3575 struct dc_link *link)
3578 struct pipe_ctx *pipe;
3579 struct dc_stream_state *link_stream;
3580 struct dc_link_settings store_settings = *link_setting;
3582 link->preferred_link_setting = store_settings;
3584 /* Retrain with preferred link settings only relevant for
3586 * Check for non-DP signal or if passive dongle present
3588 if (!dc_is_dp_signal(link->connector_signal) ||
3589 link->dongle_max_pix_clk > 0)
3592 for (i = 0; i < MAX_PIPES; i++) {
3593 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
3594 if (pipe->stream && pipe->stream->link) {
3595 if (pipe->stream->link == link) {
3596 link_stream = pipe->stream;
3602 /* Stream not found */
3606 /* Cannot retrain link if backend is off */
3607 if (link_stream->dpms_off)
3610 decide_link_settings(link_stream, &store_settings);
3612 if ((store_settings.lane_count != LANE_COUNT_UNKNOWN) &&
3613 (store_settings.link_rate != LINK_RATE_UNKNOWN))
3614 dp_retrain_link_dp_test(link, &store_settings, false);
3617 void dc_link_set_preferred_training_settings(struct dc *dc,
3618 struct dc_link_settings *link_setting,
3619 struct dc_link_training_overrides *lt_overrides,
3620 struct dc_link *link,
3621 bool skip_immediate_retrain)
3623 if (lt_overrides != NULL)
3624 link->preferred_training_settings = *lt_overrides;
3626 memset(&link->preferred_training_settings, 0, sizeof(link->preferred_training_settings));
3628 if (link_setting != NULL) {
3629 link->preferred_link_setting = *link_setting;
3631 link->preferred_link_setting.lane_count = LANE_COUNT_UNKNOWN;
3632 link->preferred_link_setting.link_rate = LINK_RATE_UNKNOWN;
3635 /* Retrain now, or wait until next stream update to apply */
3636 if (skip_immediate_retrain == false)
3637 dc_link_set_preferred_link_settings(dc, &link->preferred_link_setting, link);
3640 void dc_link_enable_hpd(const struct dc_link *link)
3642 dc_link_dp_enable_hpd(link);
3645 void dc_link_disable_hpd(const struct dc_link *link)
3647 dc_link_dp_disable_hpd(link);
3650 void dc_link_set_test_pattern(struct dc_link *link,
3651 enum dp_test_pattern test_pattern,
3652 enum dp_test_pattern_color_space test_pattern_color_space,
3653 const struct link_training_settings *p_link_settings,
3654 const unsigned char *p_custom_pattern,
3655 unsigned int cust_pattern_size)
3658 dc_link_dp_set_test_pattern(
3661 test_pattern_color_space,
3667 uint32_t dc_link_bandwidth_kbps(
3668 const struct dc_link *link,
3669 const struct dc_link_settings *link_setting)
3671 uint32_t link_bw_kbps =
3672 link_setting->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; /* bytes per sec */
3674 link_bw_kbps *= 8; /* 8 bits per byte*/
3675 link_bw_kbps *= link_setting->lane_count;
3677 if (dc_link_should_enable_fec(link)) {
3678 /* Account for FEC overhead.
3679 * We have to do it based on caps,
3680 * and not based on FEC being set ready,
3681 * because FEC is set ready too late in
3682 * the process to correctly be picked up
3683 * by mode enumeration.
3685 * There's enough zeros at the end of 'kbps'
3686 * that make the below operation 100% precise
3688 * 'long long' makes it work even for HDMI 2.1
3689 * max bandwidth (and much, much bigger bandwidths
3690 * than that, actually).
3692 * NOTE: Reducing link BW by 3% may not be precise
3693 * because it may be a stream BT that increases by 3%, and so
3694 * 1/1.03 = 0.970873 factor should have been used instead,
3695 * but the difference is minimal and is in a safe direction,
3696 * which all works well around potential ambiguity of DP 1.4a spec.
3698 long long fec_link_bw_kbps = link_bw_kbps * 970LL;
3699 link_bw_kbps = (uint32_t)(div64_s64(fec_link_bw_kbps, 1000LL));
3702 return link_bw_kbps;
3706 const struct dc_link_settings *dc_link_get_link_cap(
3707 const struct dc_link *link)
3709 if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
3710 link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
3711 return &link->preferred_link_setting;
3712 return &link->verified_link_cap;
3715 void dc_link_overwrite_extended_receiver_cap(
3716 struct dc_link *link)
3718 dp_overwrite_extended_receiver_cap(link);
3721 bool dc_link_is_fec_supported(const struct dc_link *link)
3723 return (dc_is_dp_signal(link->connector_signal) &&
3724 link->link_enc->features.fec_supported &&
3725 link->dpcd_caps.fec_cap.bits.FEC_CAPABLE &&
3726 !IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment));
3729 bool dc_link_should_enable_fec(const struct dc_link *link)
3731 bool is_fec_disable = false;
3734 if ((link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT_MST &&
3736 link->local_sink->edid_caps.panel_patch.disable_fec) ||
3737 (link->connector_signal == SIGNAL_TYPE_EDP &&
3738 link->dc->debug.force_enable_edp_fec == false)) // Disable FEC for eDP
3739 is_fec_disable = true;
3741 if (dc_link_is_fec_supported(link) && !link->dc->debug.disable_fec && !is_fec_disable)