drivers/gpu/drm/amd/display/dc/core/dc_link.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/slab.h>
  27
  28 #include "dm_services.h"
  29 #include "atomfirmware.h"
  30 #include "dm_helpers.h"
  31 #include "dc.h"
  32 #include "grph_object_id.h"
  33 #include "gpio_service_interface.h"
  34 #include "core_status.h"
  35 #include "dc_link_dp.h"
  36 #include "dc_link_dpia.h"
  37 #include "dc_link_ddc.h"
  38 #include "link_hwss.h"
  39 #include "opp.h"
  40
  41 #include "link_encoder.h"
  42 #include "hw_sequencer.h"
  43 #include "resource.h"
  44 #include "abm.h"
  45 #include "fixed31_32.h"
  46 #include "dpcd_defs.h"
  47 #include "dmcu.h"
  48 #include "hw/clk_mgr.h"
  49 #include "dce/dmub_psr.h"
  50 #include "dmub/dmub_srv.h"
  51 #include "inc/hw/panel_cntl.h"
  52 #include "inc/link_enc_cfg.h"
  53 #include "inc/link_dpcd.h"
  54 #include "link/link_dp_trace.h"
  55
  56 #include "dc/dcn30/dcn30_vpg.h"
  57
  58 #define DC_LOGGER_INIT(logger)
  59
  60 #define LINK_INFO(...) \
  61         DC_LOG_HW_HOTPLUG(  \
  62                 __VA_ARGS__)
  63
  64 #define RETIMER_REDRIVER_INFO(...) \
  65         DC_LOG_RETIMER_REDRIVER(  \
  66                 __VA_ARGS__)
  67
  68 /*******************************************************************************
  69  * Private functions
  70  ******************************************************************************/
  71 static void dc_link_destruct(struct dc_link *link)
  72 {
  73         int i;
  74
  75         if (link->hpd_gpio) {
  76                 dal_gpio_destroy_irq(&link->hpd_gpio);
  77                 link->hpd_gpio = NULL;
  78         }
  79
  80         if (link->ddc)
  81                 dal_ddc_service_destroy(&link->ddc);
  82
  83         if (link->panel_cntl)
  84                 link->panel_cntl->funcs->destroy(&link->panel_cntl);
  85
  86         if (link->link_enc) {
  87                 /* Update link encoder resource tracking variables. These are used for
  88                  * the dynamic assignment of link encoders to streams. Virtual links
  89                  * are not assigned encoder resources on creation.
  90                  */
  91                 if (link->link_id.id != CONNECTOR_ID_VIRTUAL) {
  92                         link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = NULL;
  93                         link->dc->res_pool->dig_link_enc_count--;
  94                 }
  95                 link->link_enc->funcs->destroy(&link->link_enc);
  96         }
  97
  98         if (link->local_sink)
  99                 dc_sink_release(link->local_sink);
 100
 101         for (i = 0; i < link->sink_count; ++i)
 102                 dc_sink_release(link->remote_sinks[i]);
 103 }
 104
 105 struct gpio *get_hpd_gpio(struct dc_bios *dcb,
 106                           struct graphics_object_id link_id,
 107                           struct gpio_service *gpio_service)
 108 {
 109         enum bp_result bp_result;
 110         struct graphics_object_hpd_info hpd_info;
 111         struct gpio_pin_info pin_info;
 112
 113         if (dcb->funcs->get_hpd_info(dcb, link_id, &hpd_info) != BP_RESULT_OK)
 114                 return NULL;
 115
 116         bp_result = dcb->funcs->get_gpio_pin_info(dcb,
 117                 hpd_info.hpd_int_gpio_uid, &pin_info);
 118
 119         if (bp_result != BP_RESULT_OK) {
 120                 ASSERT(bp_result == BP_RESULT_NORECORD);
 121                 return NULL;
 122         }
 123
 124         return dal_gpio_service_create_irq(gpio_service,
 125                                            pin_info.offset,
 126                                            pin_info.mask);
 127 }
 128
 129 /*
 130  *  Function: program_hpd_filter
 131  *
 132  *  @brief
 133  *     Programs HPD filter on associated HPD line
 134  *
 135  *  @param [in] delay_on_connect_in_ms: Connect filter timeout
 136  *  @param [in] delay_on_disconnect_in_ms: Disconnect filter timeout
 137  *
 138  *  @return
 139  *     true on success, false otherwise
 140  */
 141 static bool program_hpd_filter(const struct dc_link *link)
 142 {
 143         bool result = false;
 144         struct gpio *hpd;
 145         int delay_on_connect_in_ms = 0;
 146         int delay_on_disconnect_in_ms = 0;
 147
 148         if (link->is_hpd_filter_disabled)
 149                 return false;
 150         /* Verify feature is supported */
 151         switch (link->connector_signal) {
 152         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 153         case SIGNAL_TYPE_DVI_DUAL_LINK:
 154         case SIGNAL_TYPE_HDMI_TYPE_A:
 155                 /* Program hpd filter */
 156                 delay_on_connect_in_ms = 500;
 157                 delay_on_disconnect_in_ms = 100;
 158                 break;
 159         case SIGNAL_TYPE_DISPLAY_PORT:
 160         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 161                 /* Program hpd filter to allow DP signal to settle */
 162                 /* 500: not able to detect MST <-> SST switch as HPD is low for
 163                  * only 100ms on DELL U2413
 164                  * 0: some passive dongle still show aux mode instead of i2c
 165                  * 20-50: not enough to hide bouncing HPD with passive dongle.
 166                  * also see intermittent i2c read issues.
 167                  */
 168                 delay_on_connect_in_ms = 80;
 169                 delay_on_disconnect_in_ms = 0;
 170                 break;
 171         case SIGNAL_TYPE_LVDS:
 172         case SIGNAL_TYPE_EDP:
 173         default:
 174                 /* Don't program hpd filter */
 175                 return false;
 176         }
 177
 178         /* Obtain HPD handle */
 179         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
 180                            link->ctx->gpio_service);
 181
 182         if (!hpd)
 183                 return result;
 184
 185         /* Setup HPD filtering */
 186         if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
 187                 struct gpio_hpd_config config;
 188
 189                 config.delay_on_connect = delay_on_connect_in_ms;
 190                 config.delay_on_disconnect = delay_on_disconnect_in_ms;
 191
 192                 dal_irq_setup_hpd_filter(hpd, &config);
 193
 194                 dal_gpio_close(hpd);
 195
 196                 result = true;
 197         } else {
 198                 ASSERT_CRITICAL(false);
 199         }
 200
 201         /* Release HPD handle */
 202         dal_gpio_destroy_irq(&hpd);
 203
 204         return result;
 205 }
 206
 207 bool dc_link_wait_for_t12(struct dc_link *link)
 208 {
 209         if (link->connector_signal == SIGNAL_TYPE_EDP && link->dc->hwss.edp_wait_for_T12) {
 210                 link->dc->hwss.edp_wait_for_T12(link);
 211
 212                 return true;
 213         }
 214
 215         return false;
 216 }
 217
 218 /**
 219  * dc_link_detect_sink() - Determine if there is a sink connected
 220  *
 221  * @link: pointer to the dc link
 222  * @type: Returned connection type
 223  * Does not detect downstream devices, such as MST sinks
 224  * or display connected through active dongles
 225  */
 226 bool dc_link_detect_sink(struct dc_link *link, enum dc_connection_type *type)
 227 {
 228         uint32_t is_hpd_high = 0;
 229         struct gpio *hpd_pin;
 230
 231         if (link->connector_signal == SIGNAL_TYPE_LVDS) {
 232                 *type = dc_connection_single;
 233                 return true;
 234         }
 235
 236         if (link->connector_signal == SIGNAL_TYPE_EDP) {
 237                 /*in case it is not on*/
 238                 if (!link->dc->config.edp_no_power_sequencing)
 239                         link->dc->hwss.edp_power_control(link, true);
 240                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
 241         }
 242
 243         /* Link may not have physical HPD pin. */
 244         if (link->ep_type != DISPLAY_ENDPOINT_PHY) {
 245                 if (link->is_hpd_pending || !dc_link_dpia_query_hpd_status(link))
 246                         *type = dc_connection_none;
 247                 else
 248                         *type = dc_connection_single;
 249
 250                 return true;
 251         }
 252
 253         /* todo: may need to lock gpio access */
 254         hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
 255                                link->ctx->gpio_service);
 256         if (!hpd_pin)
 257                 goto hpd_gpio_failure;
 258
 259         dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
 260         dal_gpio_get_value(hpd_pin, &is_hpd_high);
 261         dal_gpio_close(hpd_pin);
 262         dal_gpio_destroy_irq(&hpd_pin);
 263
 264         if (is_hpd_high) {
 265                 *type = dc_connection_single;
 266                 /* TODO: need to do the actual detection */
 267         } else {
 268                 *type = dc_connection_none;
 269         }
 270
 271         return true;
 272
 273 hpd_gpio_failure:
 274         return false;
 275 }
 276
 277 static enum ddc_transaction_type get_ddc_transaction_type(enum signal_type sink_signal)
 278 {
 279         enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
 280
 281         switch (sink_signal) {
 282         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 283         case SIGNAL_TYPE_DVI_DUAL_LINK:
 284         case SIGNAL_TYPE_HDMI_TYPE_A:
 285         case SIGNAL_TYPE_LVDS:
 286         case SIGNAL_TYPE_RGB:
 287                 transaction_type = DDC_TRANSACTION_TYPE_I2C;
 288                 break;
 289
 290         case SIGNAL_TYPE_DISPLAY_PORT:
 291         case SIGNAL_TYPE_EDP:
 292                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 293                 break;
 294
 295         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 296                 /* MST does not use I2COverAux, but there is the
 297                  * SPECIAL use case for "immediate dwnstrm device
 298                  * access" (EPR#370830).
 299                  */
 300                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 301                 break;
 302
 303         default:
 304                 break;
 305         }
 306
 307         return transaction_type;
 308 }
 309
 310 static enum signal_type get_basic_signal_type(struct graphics_object_id encoder,
 311                                               struct graphics_object_id downstream)
 312 {
 313         if (downstream.type == OBJECT_TYPE_CONNECTOR) {
 314                 switch (downstream.id) {
 315                 case CONNECTOR_ID_SINGLE_LINK_DVII:
 316                         switch (encoder.id) {
 317                         case ENCODER_ID_INTERNAL_DAC1:
 318                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 319                         case ENCODER_ID_INTERNAL_DAC2:
 320                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 321                                 return SIGNAL_TYPE_RGB;
 322                         default:
 323                                 return SIGNAL_TYPE_DVI_SINGLE_LINK;
 324                         }
 325                 break;
 326                 case CONNECTOR_ID_DUAL_LINK_DVII:
 327                 {
 328                         switch (encoder.id) {
 329                         case ENCODER_ID_INTERNAL_DAC1:
 330                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 331                         case ENCODER_ID_INTERNAL_DAC2:
 332                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 333                                 return SIGNAL_TYPE_RGB;
 334                         default:
 335                                 return SIGNAL_TYPE_DVI_DUAL_LINK;
 336                         }
 337                 }
 338                 break;
 339                 case CONNECTOR_ID_SINGLE_LINK_DVID:
 340                         return SIGNAL_TYPE_DVI_SINGLE_LINK;
 341                 case CONNECTOR_ID_DUAL_LINK_DVID:
 342                         return SIGNAL_TYPE_DVI_DUAL_LINK;
 343                 case CONNECTOR_ID_VGA:
 344                         return SIGNAL_TYPE_RGB;
 345                 case CONNECTOR_ID_HDMI_TYPE_A:
 346                         return SIGNAL_TYPE_HDMI_TYPE_A;
 347                 case CONNECTOR_ID_LVDS:
 348                         return SIGNAL_TYPE_LVDS;
 349                 case CONNECTOR_ID_DISPLAY_PORT:
 350                 case CONNECTOR_ID_USBC:
 351                         return SIGNAL_TYPE_DISPLAY_PORT;
 352                 case CONNECTOR_ID_EDP:
 353                         return SIGNAL_TYPE_EDP;
 354                 default:
 355                         return SIGNAL_TYPE_NONE;
 356                 }
 357         } else if (downstream.type == OBJECT_TYPE_ENCODER) {
 358                 switch (downstream.id) {
 359                 case ENCODER_ID_EXTERNAL_NUTMEG:
 360                 case ENCODER_ID_EXTERNAL_TRAVIS:
 361                         return SIGNAL_TYPE_DISPLAY_PORT;
 362                 default:
 363                         return SIGNAL_TYPE_NONE;
 364                 }
 365         }
 366
 367         return SIGNAL_TYPE_NONE;
 368 }
 369
 370 /*
 371  * dc_link_is_dp_sink_present() - Check if there is a native DP
 372  * or passive DP-HDMI dongle connected
 373  */
 374 bool dc_link_is_dp_sink_present(struct dc_link *link)
 375 {
 376         enum gpio_result gpio_result;
 377         uint32_t clock_pin = 0;
 378         uint8_t retry = 0;
 379         struct ddc *ddc;
 380
 381         enum connector_id connector_id =
 382                 dal_graphics_object_id_get_connector_id(link->link_id);
 383
 384         bool present =
 385                 ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
 386                 (connector_id == CONNECTOR_ID_EDP) ||
 387                 (connector_id == CONNECTOR_ID_USBC));
 388
 389         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
 390
 391         if (!ddc) {
 392                 BREAK_TO_DEBUGGER();
 393                 return present;
 394         }
 395
 396         /* Open GPIO and set it to I2C mode */
 397         /* Note: this GpioMode_Input will be converted
 398          * to GpioConfigType_I2cAuxDualMode in GPIO component,
 399          * which indicates we need additional delay
 400          */
 401
 402         if (dal_ddc_open(ddc, GPIO_MODE_INPUT,
 403                          GPIO_DDC_CONFIG_TYPE_MODE_I2C) != GPIO_RESULT_OK) {
 404                 dal_ddc_close(ddc);
 405
 406                 return present;
 407         }
 408
 409         /*
 410          * Read GPIO: DP sink is present if both clock and data pins are zero
 411          *
 412          * [W/A] plug-unplug DP cable, sometimes customer board has
 413          * one short pulse on clk_pin(1V, < 1ms). DP will be config to HDMI/DVI
 414          * then monitor can't br light up. Add retry 3 times
 415          * But in real passive dongle, it need additional 3ms to detect
 416          */
 417         do {
 418                 gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
 419                 ASSERT(gpio_result == GPIO_RESULT_OK);
 420                 if (clock_pin)
 421                         udelay(1000);
 422                 else
 423                         break;
 424         } while (retry++ < 3);
 425
 426         present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
 427
 428         dal_ddc_close(ddc);
 429
 430         return present;
 431 }
 432
 433 /*
 434  * @brief
 435  * Detect output sink type
 436  */
 437 static enum signal_type link_detect_sink(struct dc_link *link,
 438                                          enum dc_detect_reason reason)
 439 {
 440         enum signal_type result;
 441         struct graphics_object_id enc_id;
 442
 443         if (link->is_dig_mapping_flexible)
 444                 enc_id = (struct graphics_object_id){.id = ENCODER_ID_UNKNOWN};
 445         else
 446                 enc_id = link->link_enc->id;
 447         result = get_basic_signal_type(enc_id, link->link_id);
 448
 449         /* Use basic signal type for link without physical connector. */
 450         if (link->ep_type != DISPLAY_ENDPOINT_PHY)
 451                 return result;
 452
 453         /* Internal digital encoder will detect only dongles
 454          * that require digital signal
 455          */
 456
 457         /* Detection mechanism is different
 458          * for different native connectors.
 459          * LVDS connector supports only LVDS signal;
 460          * PCIE is a bus slot, the actual connector needs to be detected first;
 461          * eDP connector supports only eDP signal;
 462          * HDMI should check straps for audio
 463          */
 464
 465         /* PCIE detects the actual connector on add-on board */
 466         if (link->link_id.id == CONNECTOR_ID_PCIE) {
 467                 /* ZAZTODO implement PCIE add-on card detection */
 468         }
 469
 470         switch (link->link_id.id) {
 471         case CONNECTOR_ID_HDMI_TYPE_A: {
 472                 /* check audio support:
 473                  * if native HDMI is not supported, switch to DVI
 474                  */
 475                 struct audio_support *aud_support =
 476                                         &link->dc->res_pool->audio_support;
 477
 478                 if (!aud_support->hdmi_audio_native)
 479                         if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
 480                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 481         }
 482         break;
 483         case CONNECTOR_ID_DISPLAY_PORT:
 484         case CONNECTOR_ID_USBC: {
 485                 /* DP HPD short pulse. Passive DP dongle will not
 486                  * have short pulse
 487                  */
 488                 if (reason != DETECT_REASON_HPDRX) {
 489                         /* Check whether DP signal detected: if not -
 490                          * we assume signal is DVI; it could be corrected
 491                          * to HDMI after dongle detection
 492                          */
 493                         if (!dm_helpers_is_dp_sink_present(link))
 494                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 495                 }
 496         }
 497         break;
 498         default:
 499         break;
 500         }
 501
 502         return result;
 503 }
 504
 505 static enum signal_type decide_signal_from_strap_and_dongle_type(enum display_dongle_type dongle_type,
 506                                                                  struct audio_support *audio_support)
 507 {
 508         enum signal_type signal = SIGNAL_TYPE_NONE;
 509
 510         switch (dongle_type) {
 511         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 512                 if (audio_support->hdmi_audio_on_dongle)
 513                         signal = SIGNAL_TYPE_HDMI_TYPE_A;
 514                 else
 515                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 516                 break;
 517         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 518                 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 519                 break;
 520         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 521                 if (audio_support->hdmi_audio_native)
 522                         signal =  SIGNAL_TYPE_HDMI_TYPE_A;
 523                 else
 524                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 525                 break;
 526         default:
 527                 signal = SIGNAL_TYPE_NONE;
 528                 break;
 529         }
 530
 531         return signal;
 532 }
 533
 534 static enum signal_type dp_passive_dongle_detection(struct ddc_service *ddc,
 535                                                     struct display_sink_capability *sink_cap,
 536                                                     struct audio_support *audio_support)
 537 {
 538         dal_ddc_service_i2c_query_dp_dual_mode_adaptor(ddc, sink_cap);
 539
 540         return decide_signal_from_strap_and_dongle_type(sink_cap->dongle_type,
 541                                                         audio_support);
 542 }
 543
 544 static void link_disconnect_sink(struct dc_link *link)
 545 {
 546         if (link->local_sink) {
 547                 dc_sink_release(link->local_sink);
 548                 link->local_sink = NULL;
 549         }
 550
 551         link->dpcd_sink_count = 0;
 552         //link->dpcd_caps.dpcd_rev.raw = 0;
 553 }
 554
 555 static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link)
 556 {
 557         dc_sink_release(link->local_sink);
 558         link->local_sink = prev_sink;
 559 }
 560
 561 #if defined(CONFIG_DRM_AMD_DC_HDCP)
 562 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal)
 563 {
 564         bool ret = false;
 565
 566         switch (signal) {
 567         case SIGNAL_TYPE_DISPLAY_PORT:
 568         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 569                 ret = link->hdcp_caps.bcaps.bits.HDCP_CAPABLE;
 570                 break;
 571         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 572         case SIGNAL_TYPE_DVI_DUAL_LINK:
 573         case SIGNAL_TYPE_HDMI_TYPE_A:
 574         /* HDMI doesn't tell us its HDCP(1.4) capability, so assume to always be capable,
 575          * we can poll for bksv but some displays have an issue with this. Since its so rare
 576          * for a display to not be 1.4 capable, this assumtion is ok
 577          */
 578                 ret = true;
 579                 break;
 580         default:
 581                 break;
 582         }
 583         return ret;
 584 }
 585
 586 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal)
 587 {
 588         bool ret = false;
 589
 590         switch (signal) {
 591         case SIGNAL_TYPE_DISPLAY_PORT:
 592         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 593                 ret = (link->hdcp_caps.bcaps.bits.HDCP_CAPABLE &&
 594                                 link->hdcp_caps.rx_caps.fields.byte0.hdcp_capable &&
 595                                 (link->hdcp_caps.rx_caps.fields.version == 0x2)) ? 1 : 0;
 596                 break;
 597         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 598         case SIGNAL_TYPE_DVI_DUAL_LINK:
 599         case SIGNAL_TYPE_HDMI_TYPE_A:
 600                 ret = (link->hdcp_caps.rx_caps.fields.version == 0x4) ? 1:0;
 601                 break;
 602         default:
 603                 break;
 604         }
 605
 606         return ret;
 607 }
 608
 609 static void query_hdcp_capability(enum signal_type signal, struct dc_link *link)
 610 {
 611         struct hdcp_protection_message msg22;
 612         struct hdcp_protection_message msg14;
 613
 614         memset(&msg22, 0, sizeof(struct hdcp_protection_message));
 615         memset(&msg14, 0, sizeof(struct hdcp_protection_message));
 616         memset(link->hdcp_caps.rx_caps.raw, 0,
 617                 sizeof(link->hdcp_caps.rx_caps.raw));
 618
 619         if ((link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
 620                         link->ddc->transaction_type ==
 621                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX) ||
 622                         link->connector_signal == SIGNAL_TYPE_EDP) {
 623                 msg22.data = link->hdcp_caps.rx_caps.raw;
 624                 msg22.length = sizeof(link->hdcp_caps.rx_caps.raw);
 625                 msg22.msg_id = HDCP_MESSAGE_ID_RX_CAPS;
 626         } else {
 627                 msg22.data = &link->hdcp_caps.rx_caps.fields.version;
 628                 msg22.length = sizeof(link->hdcp_caps.rx_caps.fields.version);
 629                 msg22.msg_id = HDCP_MESSAGE_ID_HDCP2VERSION;
 630         }
 631         msg22.version = HDCP_VERSION_22;
 632         msg22.link = HDCP_LINK_PRIMARY;
 633         msg22.max_retries = 5;
 634         dc_process_hdcp_msg(signal, link, &msg22);
 635
 636         if (signal == SIGNAL_TYPE_DISPLAY_PORT || signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
 637                 msg14.data = &link->hdcp_caps.bcaps.raw;
 638                 msg14.length = sizeof(link->hdcp_caps.bcaps.raw);
 639                 msg14.msg_id = HDCP_MESSAGE_ID_READ_BCAPS;
 640                 msg14.version = HDCP_VERSION_14;
 641                 msg14.link = HDCP_LINK_PRIMARY;
 642                 msg14.max_retries = 5;
 643
 644                 dc_process_hdcp_msg(signal, link, &msg14);
 645         }
 646
 647 }
 648 #endif
 649
 650 static void read_current_link_settings_on_detect(struct dc_link *link)
 651 {
 652         union lane_count_set lane_count_set = {0};
 653         uint8_t link_bw_set;
 654         uint8_t link_rate_set;
 655         uint32_t read_dpcd_retry_cnt = 10;
 656         enum dc_status status = DC_ERROR_UNEXPECTED;
 657         int i;
 658         union max_down_spread max_down_spread = {0};
 659
 660         // Read DPCD 00101h to find out the number of lanes currently set
 661         for (i = 0; i < read_dpcd_retry_cnt; i++) {
 662                 status = core_link_read_dpcd(link,
 663                                              DP_LANE_COUNT_SET,
 664                                              &lane_count_set.raw,
 665                                              sizeof(lane_count_set));
 666                 /* First DPCD read after VDD ON can fail if the particular board
 667                  * does not have HPD pin wired correctly. So if DPCD read fails,
 668                  * which it should never happen, retry a few times. Target worst
 669                  * case scenario of 80 ms.
 670                  */
 671                 if (status == DC_OK) {
 672                         link->cur_link_settings.lane_count =
 673                                         lane_count_set.bits.LANE_COUNT_SET;
 674                         break;
 675                 }
 676
 677                 msleep(8);
 678         }
 679
 680         // Read DPCD 00100h to find if standard link rates are set
 681         core_link_read_dpcd(link, DP_LINK_BW_SET,
 682                             &link_bw_set, sizeof(link_bw_set));
 683
 684         if (link_bw_set == 0) {
 685                 if (link->connector_signal == SIGNAL_TYPE_EDP) {
 686                         /* If standard link rates are not being used,
 687                          * Read DPCD 00115h to find the edp link rate set used
 688                          */
 689                         core_link_read_dpcd(link, DP_LINK_RATE_SET,
 690                                             &link_rate_set, sizeof(link_rate_set));
 691
 692                         // edp_supported_link_rates_count = 0 for DP
 693                         if (link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
 694                                 link->cur_link_settings.link_rate =
 695                                         link->dpcd_caps.edp_supported_link_rates[link_rate_set];
 696                                 link->cur_link_settings.link_rate_set = link_rate_set;
 697                                 link->cur_link_settings.use_link_rate_set = true;
 698                         }
 699                 } else {
 700                         // Link Rate not found. Seamless boot may not work.
 701                         ASSERT(false);
 702                 }
 703         } else {
 704                 link->cur_link_settings.link_rate = link_bw_set;
 705                 link->cur_link_settings.use_link_rate_set = false;
 706         }
 707         // Read DPCD 00003h to find the max down spread.
 708         core_link_read_dpcd(link, DP_MAX_DOWNSPREAD,
 709                             &max_down_spread.raw, sizeof(max_down_spread));
 710         link->cur_link_settings.link_spread =
 711                 max_down_spread.bits.MAX_DOWN_SPREAD ?
 712                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
 713 }
 714
 715 static bool detect_dp(struct dc_link *link,
 716                       struct display_sink_capability *sink_caps,
 717                       enum dc_detect_reason reason)
 718 {
 719         struct audio_support *audio_support = &link->dc->res_pool->audio_support;
 720
 721         sink_caps->signal = link_detect_sink(link, reason);
 722         sink_caps->transaction_type =
 723                 get_ddc_transaction_type(sink_caps->signal);
 724
 725         if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
 726                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 727                 if (!detect_dp_sink_caps(link))
 728                         return false;
 729
 730                 if (is_dp_branch_device(link))
 731                         /* DP SST branch */
 732                         link->type = dc_connection_sst_branch;
 733         } else {
 734                 /* DP passive dongles */
 735                 sink_caps->signal = dp_passive_dongle_detection(link->ddc,
 736                                                                 sink_caps,
 737                                                                 audio_support);
 738                 link->dpcd_caps.dongle_type = sink_caps->dongle_type;
 739                 link->dpcd_caps.is_dongle_type_one = sink_caps->is_dongle_type_one;
 740                 link->dpcd_caps.dpcd_rev.raw = 0;
 741         }
 742
 743         return true;
 744 }
 745
 746 static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
 747 {
 748         if (old_edid->length != new_edid->length)
 749                 return false;
 750
 751         if (new_edid->length == 0)
 752                 return false;
 753
 754         return (memcmp(old_edid->raw_edid,
 755                        new_edid->raw_edid, new_edid->length) == 0);
 756 }
 757
 758 static bool wait_for_entering_dp_alt_mode(struct dc_link *link)
 759 {
 760         /**
 761          * something is terribly wrong if time out is > 200ms. (5Hz)
 762          * 500 microseconds * 400 tries us 200 ms
 763          **/
 764         unsigned int sleep_time_in_microseconds = 500;
 765         unsigned int tries_allowed = 400;
 766         bool is_in_alt_mode;
 767         unsigned long long enter_timestamp;
 768         unsigned long long finish_timestamp;
 769         unsigned long long time_taken_in_ns;
 770         int tries_taken;
 771
 772         DC_LOGGER_INIT(link->ctx->logger);
 773
 774         if (!link->link_enc->funcs->is_in_alt_mode)
 775                 return true;
 776
 777         is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc);
 778         DC_LOG_WARNING("DP Alt mode state on HPD: %d\n", is_in_alt_mode);
 779
 780         if (is_in_alt_mode)
 781                 return true;
 782
 783         enter_timestamp = dm_get_timestamp(link->ctx);
 784
 785         for (tries_taken = 0; tries_taken < tries_allowed; tries_taken++) {
 786                 udelay(sleep_time_in_microseconds);
 787                 /* ask the link if alt mode is enabled, if so return ok */
 788                 if (link->link_enc->funcs->is_in_alt_mode(link->link_enc)) {
 789                         finish_timestamp = dm_get_timestamp(link->ctx);
 790                         time_taken_in_ns =
 791                                 dm_get_elapse_time_in_ns(link->ctx,
 792                                                          finish_timestamp,
 793                                                          enter_timestamp);
 794                         DC_LOG_WARNING("Alt mode entered finished after %llu ms\n",
 795                                        div_u64(time_taken_in_ns, 1000000));
 796                         return true;
 797                 }
 798         }
 799         finish_timestamp = dm_get_timestamp(link->ctx);
 800         time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp,
 801                                                     enter_timestamp);
 802         DC_LOG_WARNING("Alt mode has timed out after %llu ms\n",
 803                        div_u64(time_taken_in_ns, 1000000));
 804         return false;
 805 }
 806
 807 static void apply_dpia_mst_dsc_always_on_wa(struct dc_link *link)
 808 {
 809         /* Apply work around for tunneled MST on certain USB4 docks. Always use DSC if dock
 810          * reports DSC support.
 811          */
 812         if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
 813                         link->type == dc_connection_mst_branch &&
 814                         link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
 815                         link->dpcd_caps.branch_hw_revision == DP_BRANCH_HW_REV_20 &&
 816                         link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT &&
 817                         !link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around)
 818                 link->wa_flags.dpia_mst_dsc_always_on = true;
 819 }
 820
 821 static void revert_dpia_mst_dsc_always_on_wa(struct dc_link *link)
 822 {
 823         /* Disable work around which keeps DSC on for tunneled MST on certain USB4 docks. */
 824         if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
 825                 link->wa_flags.dpia_mst_dsc_always_on = false;
 826 }
 827
 828 static bool discover_dp_mst_topology(struct dc_link *link, enum dc_detect_reason reason)
 829 {
 830         DC_LOGGER_INIT(link->ctx->logger);
 831
 832         LINK_INFO("link=%d, mst branch is now Connected\n",
 833                   link->link_index);
 834
 835         link->type = dc_connection_mst_branch;
 836         apply_dpia_mst_dsc_always_on_wa(link);
 837
 838         dm_helpers_dp_update_branch_info(link->ctx, link);
 839         if (dm_helpers_dp_mst_start_top_mgr(link->ctx,
 840                         link, (reason == DETECT_REASON_BOOT || reason == DETECT_REASON_RESUMEFROMS3S4))) {
 841                 link_disconnect_sink(link);
 842         } else {
 843                 link->type = dc_connection_sst_branch;
 844         }
 845
 846         return link->type == dc_connection_mst_branch;
 847 }
 848
 849 bool reset_cur_dp_mst_topology(struct dc_link *link)
 850 {
 851         DC_LOGGER_INIT(link->ctx->logger);
 852
 853         LINK_INFO("link=%d, mst branch is now Disconnected\n",
 854                   link->link_index);
 855
 856         revert_dpia_mst_dsc_always_on_wa(link);
 857         return dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
 858 }
 859
 860 static bool should_prepare_phy_clocks_for_link_verification(const struct dc *dc,
 861                 enum dc_detect_reason reason)
 862 {
 863         int i;
 864         bool can_apply_seamless_boot = false;
 865
 866         for (i = 0; i < dc->current_state->stream_count; i++) {
 867                 if (dc->current_state->streams[i]->apply_seamless_boot_optimization) {
 868                         can_apply_seamless_boot = true;
 869                         break;
 870                 }
 871         }
 872
 873         return !can_apply_seamless_boot && reason != DETECT_REASON_BOOT;
 874 }
 875
 876 static void prepare_phy_clocks_for_destructive_link_verification(const struct dc *dc)
 877 {
 878         dc_z10_restore(dc);
 879         clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
 880 }
 881
 882 static void restore_phy_clocks_for_destructive_link_verification(const struct dc *dc)
 883 {
 884         clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
 885 }
 886
 887 static void set_all_streams_dpms_off_for_link(struct dc_link *link)
 888 {
 889         int i;
 890         struct pipe_ctx *pipe_ctx;
 891         struct dc_stream_update stream_update;
 892         bool dpms_off = true;
 893         struct link_resource link_res = {0};
 894
 895         memset(&stream_update, 0, sizeof(stream_update));
 896         stream_update.dpms_off = &dpms_off;
 897
 898         for (i = 0; i < MAX_PIPES; i++) {
 899                 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
 900                 if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
 901                                 pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe) {
 902                         stream_update.stream = pipe_ctx->stream;
 903                         dc_commit_updates_for_stream(link->ctx->dc, NULL, 0,
 904                                         pipe_ctx->stream, &stream_update,
 905                                         link->ctx->dc->current_state);
 906                 }
 907         }
 908
 909         /* link can be also enabled by vbios. In this case it is not recorded
 910          * in pipe_ctx. Disable link phy here to make sure it is completely off
 911          */
 912         dp_disable_link_phy(link, &link_res, link->connector_signal);
 913 }
 914
 915 static void verify_link_capability_destructive(struct dc_link *link,
 916                 struct dc_sink *sink,
 917                 enum dc_detect_reason reason)
 918 {
 919         bool should_prepare_phy_clocks =
 920                         should_prepare_phy_clocks_for_link_verification(link->dc, reason);
 921
 922         if (should_prepare_phy_clocks)
 923                 prepare_phy_clocks_for_destructive_link_verification(link->dc);
 924
 925         if (dc_is_dp_signal(link->local_sink->sink_signal)) {
 926                 struct dc_link_settings known_limit_link_setting =
 927                                 dp_get_max_link_cap(link);
 928                 set_all_streams_dpms_off_for_link(link);
 929                 dp_verify_link_cap_with_retries(
 930                                 link, &known_limit_link_setting,
 931                                 LINK_TRAINING_MAX_VERIFY_RETRY);
 932         } else {
 933                 ASSERT(0);
 934         }
 935
 936         if (should_prepare_phy_clocks)
 937                 restore_phy_clocks_for_destructive_link_verification(link->dc);
 938 }
 939
 940 static void verify_link_capability_non_destructive(struct dc_link *link)
 941 {
 942         if (dc_is_dp_signal(link->local_sink->sink_signal)) {
 943                 if (dc_is_embedded_signal(link->local_sink->sink_signal) ||
 944                                 link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
 945                         /* TODO - should we check link encoder's max link caps here?
 946                          * How do we know which link encoder to check from?
 947                          */
 948                         link->verified_link_cap = link->reported_link_cap;
 949                 else
 950                         link->verified_link_cap = dp_get_max_link_cap(link);
 951         }
 952 }
 953
 954 static bool should_verify_link_capability_destructively(struct dc_link *link,
 955                 enum dc_detect_reason reason)
 956 {
 957         bool destrictive = false;
 958         struct dc_link_settings max_link_cap;
 959         bool is_link_enc_unavailable = link->link_enc &&
 960                         link->dc->res_pool->funcs->link_encs_assign &&
 961                         !link_enc_cfg_is_link_enc_avail(
 962                                         link->ctx->dc,
 963                                         link->link_enc->preferred_engine,
 964                                         link);
 965
 966         if (dc_is_dp_signal(link->local_sink->sink_signal)) {
 967                 max_link_cap = dp_get_max_link_cap(link);
 968                 destrictive = true;
 969
 970                 if (link->dc->debug.skip_detection_link_training ||
 971                                 dc_is_embedded_signal(link->local_sink->sink_signal) ||
 972                                 link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
 973                         destrictive = false;
 974                 } else if (dp_get_link_encoding_format(&max_link_cap) ==
 975                                 DP_8b_10b_ENCODING) {
 976                         if (link->dpcd_caps.is_mst_capable ||
 977                                         is_link_enc_unavailable) {
 978                                 destrictive = false;
 979                         }
 980                 }
 981         }
 982
 983         return destrictive;
 984 }
 985
 986 static void verify_link_capability(struct dc_link *link, struct dc_sink *sink,
 987                 enum dc_detect_reason reason)
 988 {
 989         if (should_verify_link_capability_destructively(link, reason))
 990                 verify_link_capability_destructive(link, sink, reason);
 991         else
 992                 verify_link_capability_non_destructive(link);
 993 }
 994
 995
 996 /**
 997  * detect_link_and_local_sink() - Detect if a sink is attached to a given link
 998  *
 999  * link->local_sink is created or destroyed as needed.
1000  *
1001  * This does not create remote sinks.
1002  */
1003 static bool detect_link_and_local_sink(struct dc_link *link,
1004                                   enum dc_detect_reason reason)
1005 {
1006         struct dc_sink_init_data sink_init_data = { 0 };
1007         struct display_sink_capability sink_caps = { 0 };
1008         uint32_t i;
1009         bool converter_disable_audio = false;
1010         struct audio_support *aud_support = &link->dc->res_pool->audio_support;
1011         bool same_edid = false;
1012         enum dc_edid_status edid_status;
1013         struct dc_context *dc_ctx = link->ctx;
1014         struct dc *dc = dc_ctx->dc;
1015         struct dc_sink *sink = NULL;
1016         struct dc_sink *prev_sink = NULL;
1017         struct dpcd_caps prev_dpcd_caps;
1018         enum dc_connection_type new_connection_type = dc_connection_none;
1019         const uint32_t post_oui_delay = 30; // 30ms
1020
1021         DC_LOGGER_INIT(link->ctx->logger);
1022
1023         if (dc_is_virtual_signal(link->connector_signal))
1024                 return false;
1025
1026         if (((link->connector_signal == SIGNAL_TYPE_LVDS ||
1027                 link->connector_signal == SIGNAL_TYPE_EDP) &&
1028                 (!link->dc->config.allow_edp_hotplug_detection)) &&
1029                 link->local_sink) {
1030                 // need to re-write OUI and brightness in resume case
1031                 if (link->connector_signal == SIGNAL_TYPE_EDP &&
1032                         (link->dpcd_sink_ext_caps.bits.oled == 1)) {
1033                         dpcd_set_source_specific_data(link);
1034                         msleep(post_oui_delay);
1035                         dc_link_set_default_brightness_aux(link);
1036                         //TODO: use cached
1037                 }
1038
1039                 return true;
1040         }
1041
1042         if (!dc_link_detect_sink(link, &new_connection_type)) {
1043                 BREAK_TO_DEBUGGER();
1044                 return false;
1045         }
1046
1047         prev_sink = link->local_sink;
1048         if (prev_sink) {
1049                 dc_sink_retain(prev_sink);
1050                 memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps));
1051         }
1052
1053         link_disconnect_sink(link);
1054         if (new_connection_type != dc_connection_none) {
1055                 link->type = new_connection_type;
1056                 link->link_state_valid = false;
1057
1058                 /* From Disconnected-to-Connected. */
1059                 switch (link->connector_signal) {
1060                 case SIGNAL_TYPE_HDMI_TYPE_A: {
1061                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1062                         if (aud_support->hdmi_audio_native)
1063                                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
1064                         else
1065                                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1066                         break;
1067                 }
1068
1069                 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
1070                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1071                         sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1072                         break;
1073                 }
1074
1075                 case SIGNAL_TYPE_DVI_DUAL_LINK: {
1076                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1077                         sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1078                         break;
1079                 }
1080
1081                 case SIGNAL_TYPE_LVDS: {
1082                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1083                         sink_caps.signal = SIGNAL_TYPE_LVDS;
1084                         break;
1085                 }
1086
1087                 case SIGNAL_TYPE_EDP: {
1088                         read_current_link_settings_on_detect(link);
1089
1090                         detect_edp_sink_caps(link);
1091                         read_current_link_settings_on_detect(link);
1092
1093                         /* Disable power sequence on MIPI panel + converter
1094                          */
1095                         if (dc->config.enable_mipi_converter_optimization &&
1096                                 dc_ctx->dce_version == DCN_VERSION_3_01 &&
1097                                 link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_0022B9 &&
1098                                 memcmp(&link->dpcd_caps.branch_dev_name, DP_SINK_BRANCH_DEV_NAME_7580,
1099                                         sizeof(link->dpcd_caps.branch_dev_name)) == 0) {
1100                                 dc->config.edp_no_power_sequencing = true;
1101
1102                                 if (!link->dpcd_caps.set_power_state_capable_edp)
1103                                         link->wa_flags.dp_keep_receiver_powered = true;
1104                         }
1105
1106                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
1107                         sink_caps.signal = SIGNAL_TYPE_EDP;
1108                         break;
1109                 }
1110
1111                 case SIGNAL_TYPE_DISPLAY_PORT: {
1112                         /* wa HPD high coming too early*/
1113                         if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
1114                             link->link_enc->features.flags.bits.DP_IS_USB_C == 1) {
1115                                 /* if alt mode times out, return false */
1116                                 if (!wait_for_entering_dp_alt_mode(link))
1117                                         return false;
1118                         }
1119
1120                         if (!detect_dp(link, &sink_caps, reason)) {
1121                                 if (prev_sink)
1122                                         dc_sink_release(prev_sink);
1123                                 return false;
1124                         }
1125
1126                         /* Active SST downstream branch device unplug*/
1127                         if (link->type == dc_connection_sst_branch &&
1128                             link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) {
1129                                 if (prev_sink)
1130                                         /* Downstream unplug */
1131                                         dc_sink_release(prev_sink);
1132                                 return true;
1133                         }
1134
1135                         /* disable audio for non DP to HDMI active sst converter */
1136                         if (link->type == dc_connection_sst_branch &&
1137                                         is_dp_active_dongle(link) &&
1138                                         (link->dpcd_caps.dongle_type !=
1139                                                         DISPLAY_DONGLE_DP_HDMI_CONVERTER))
1140                                 converter_disable_audio = true;
1141                         break;
1142                 }
1143
1144                 default:
1145                         DC_ERROR("Invalid connector type! signal:%d\n",
1146                                  link->connector_signal);
1147                         if (prev_sink)
1148                                 dc_sink_release(prev_sink);
1149                         return false;
1150                 } /* switch() */
1151
1152                 if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
1153                         link->dpcd_sink_count =
1154                                 link->dpcd_caps.sink_count.bits.SINK_COUNT;
1155                 else
1156                         link->dpcd_sink_count = 1;
1157
1158                 dal_ddc_service_set_transaction_type(link->ddc,
1159                                                      sink_caps.transaction_type);
1160
1161                 link->aux_mode =
1162                         dal_ddc_service_is_in_aux_transaction_mode(link->ddc);
1163
1164                 sink_init_data.link = link;
1165                 sink_init_data.sink_signal = sink_caps.signal;
1166
1167                 sink = dc_sink_create(&sink_init_data);
1168                 if (!sink) {
1169                         DC_ERROR("Failed to create sink!\n");
1170                         if (prev_sink)
1171                                 dc_sink_release(prev_sink);
1172                         return false;
1173                 }
1174
1175                 sink->link->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
1176                 sink->converter_disable_audio = converter_disable_audio;
1177
1178                 /* dc_sink_create returns a new reference */
1179                 link->local_sink = sink;
1180
1181                 edid_status = dm_helpers_read_local_edid(link->ctx,
1182                                                          link, sink);
1183
1184                 switch (edid_status) {
1185                 case EDID_BAD_CHECKSUM:
1186                         DC_LOG_ERROR("EDID checksum invalid.\n");
1187                         break;
1188                 case EDID_PARTIAL_VALID:
1189                         DC_LOG_ERROR("Partial EDID valid, abandon invalid blocks.\n");
1190                         break;
1191                 case EDID_NO_RESPONSE:
1192                         DC_LOG_ERROR("No EDID read.\n");
1193                         /*
1194                          * Abort detection for non-DP connectors if we have
1195                          * no EDID
1196                          *
1197                          * DP needs to report as connected if HDP is high
1198                          * even if we have no EDID in order to go to
1199                          * fail-safe mode
1200                          */
1201                         if (dc_is_hdmi_signal(link->connector_signal) ||
1202                             dc_is_dvi_signal(link->connector_signal)) {
1203                                 if (prev_sink)
1204                                         dc_sink_release(prev_sink);
1205
1206                                 return false;
1207                         }
1208
1209                         if (link->type == dc_connection_sst_branch &&
1210                                         link->dpcd_caps.dongle_type ==
1211                                                 DISPLAY_DONGLE_DP_VGA_CONVERTER &&
1212                                         reason == DETECT_REASON_HPDRX) {
1213                                 /* Abort detection for DP-VGA adapters when EDID
1214                                  * can't be read and detection reason is VGA-side
1215                                  * hotplug
1216                                  */
1217                                 if (prev_sink)
1218                                         dc_sink_release(prev_sink);
1219                                 link_disconnect_sink(link);
1220
1221                                 return true;
1222                         }
1223
1224                         break;
1225                 default:
1226                         break;
1227                 }
1228
1229                 // Check if edid is the same
1230                 if ((prev_sink) &&
1231                     (edid_status == EDID_THE_SAME || edid_status == EDID_OK))
1232                         same_edid = is_same_edid(&prev_sink->dc_edid,
1233                                                  &sink->dc_edid);
1234
1235                 if (sink->edid_caps.panel_patch.skip_scdc_overwrite)
1236                         link->ctx->dc->debug.hdmi20_disable = true;
1237
1238                 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
1239                     sink_caps.transaction_type ==
1240                     DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
1241                         /*
1242                          * TODO debug why Dell 2413 doesn't like
1243                          *  two link trainings
1244                          */
1245 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1246                         query_hdcp_capability(sink->sink_signal, link);
1247 #endif
1248                 } else {
1249                         // If edid is the same, then discard new sink and revert back to original sink
1250                         if (same_edid) {
1251                                 link_disconnect_remap(prev_sink, link);
1252                                 sink = prev_sink;
1253                                 prev_sink = NULL;
1254                         }
1255 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1256                         query_hdcp_capability(sink->sink_signal, link);
1257 #endif
1258                 }
1259
1260                 /* HDMI-DVI Dongle */
1261                 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
1262                     !sink->edid_caps.edid_hdmi)
1263                         sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1264
1265                 if (link->local_sink && dc_is_dp_signal(sink_caps.signal))
1266                         dp_trace_init(link);
1267
1268                 /* Connectivity log: detection */
1269                 for (i = 0; i < sink->dc_edid.length / DC_EDID_BLOCK_SIZE; i++) {
1270                         CONN_DATA_DETECT(link,
1271                                          &sink->dc_edid.raw_edid[i * DC_EDID_BLOCK_SIZE],
1272                                          DC_EDID_BLOCK_SIZE,
1273                                          "%s: [Block %d] ", sink->edid_caps.display_name, i);
1274                 }
1275
1276                 DC_LOG_DETECTION_EDID_PARSER("%s: "
1277                         "manufacturer_id = %X, "
1278                         "product_id = %X, "
1279                         "serial_number = %X, "
1280                         "manufacture_week = %d, "
1281                         "manufacture_year = %d, "
1282                         "display_name = %s, "
1283                         "speaker_flag = %d, "
1284                         "audio_mode_count = %d\n",
1285                         __func__,
1286                         sink->edid_caps.manufacturer_id,
1287                         sink->edid_caps.product_id,
1288                         sink->edid_caps.serial_number,
1289                         sink->edid_caps.manufacture_week,
1290                         sink->edid_caps.manufacture_year,
1291                         sink->edid_caps.display_name,
1292                         sink->edid_caps.speaker_flags,
1293                         sink->edid_caps.audio_mode_count);
1294
1295                 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
1296                         DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, "
1297                                 "format_code = %d, "
1298                                 "channel_count = %d, "
1299                                 "sample_rate = %d, "
1300                                 "sample_size = %d\n",
1301                                 __func__,
1302                                 i,
1303                                 sink->edid_caps.audio_modes[i].format_code,
1304                                 sink->edid_caps.audio_modes[i].channel_count,
1305                                 sink->edid_caps.audio_modes[i].sample_rate,
1306                                 sink->edid_caps.audio_modes[i].sample_size);
1307                 }
1308
1309                 if (link->connector_signal == SIGNAL_TYPE_EDP) {
1310                         // Init dc_panel_config
1311                         dm_helpers_init_panel_settings(dc_ctx, &link->panel_config, sink);
1312                         // Override dc_panel_config if system has specific settings
1313                         dm_helpers_override_panel_settings(dc_ctx, &link->panel_config);
1314                 }
1315
1316         } else {
1317                 /* From Connected-to-Disconnected. */
1318                 link->type = dc_connection_none;
1319                 sink_caps.signal = SIGNAL_TYPE_NONE;
1320                 /* When we unplug a passive DP-HDMI dongle connection, dongle_max_pix_clk
1321                  *  is not cleared. If we emulate a DP signal on this connection, it thinks
1322                  *  the dongle is still there and limits the number of modes we can emulate.
1323                  *  Clear dongle_max_pix_clk on disconnect to fix this
1324                  */
1325                 link->dongle_max_pix_clk = 0;
1326
1327                 dc_link_clear_dprx_states(link);
1328                 dp_trace_reset(link);
1329         }
1330
1331         LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p edid same=%d\n",
1332                   link->link_index, sink,
1333                   (sink_caps.signal ==
1334                    SIGNAL_TYPE_NONE ? "Disconnected" : "Connected"),
1335                   prev_sink, same_edid);
1336
1337         if (prev_sink)
1338                 dc_sink_release(prev_sink);
1339
1340         return true;
1341 }
1342
1343 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
1344 {
1345         bool is_local_sink_detect_success;
1346         bool is_delegated_to_mst_top_mgr = false;
1347         enum dc_connection_type pre_link_type = link->type;
1348
1349         is_local_sink_detect_success = detect_link_and_local_sink(link, reason);
1350
1351         if (is_local_sink_detect_success && link->local_sink)
1352                 verify_link_capability(link, link->local_sink, reason);
1353
1354         if (is_local_sink_detect_success && link->local_sink &&
1355                         dc_is_dp_signal(link->local_sink->sink_signal) &&
1356                         link->dpcd_caps.is_mst_capable)
1357                 is_delegated_to_mst_top_mgr = discover_dp_mst_topology(link, reason);
1358
1359         if (is_local_sink_detect_success &&
1360                         pre_link_type == dc_connection_mst_branch &&
1361                         link->type != dc_connection_mst_branch)
1362                 is_delegated_to_mst_top_mgr = reset_cur_dp_mst_topology(link);
1363
1364         return is_local_sink_detect_success && !is_delegated_to_mst_top_mgr;
1365 }
1366
1367 bool dc_link_get_hpd_state(struct dc_link *dc_link)
1368 {
1369         uint32_t state;
1370
1371         dal_gpio_lock_pin(dc_link->hpd_gpio);
1372         dal_gpio_get_value(dc_link->hpd_gpio, &state);
1373         dal_gpio_unlock_pin(dc_link->hpd_gpio);
1374
1375         return state;
1376 }
1377
1378 static enum hpd_source_id get_hpd_line(struct dc_link *link)
1379 {
1380         struct gpio *hpd;
1381         enum hpd_source_id hpd_id;
1382
1383         hpd_id = HPD_SOURCEID_UNKNOWN;
1384
1385         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
1386                            link->ctx->gpio_service);
1387
1388         if (hpd) {
1389                 switch (dal_irq_get_source(hpd)) {
1390                 case DC_IRQ_SOURCE_HPD1:
1391                         hpd_id = HPD_SOURCEID1;
1392                 break;
1393                 case DC_IRQ_SOURCE_HPD2:
1394                         hpd_id = HPD_SOURCEID2;
1395                 break;
1396                 case DC_IRQ_SOURCE_HPD3:
1397                         hpd_id = HPD_SOURCEID3;
1398                 break;
1399                 case DC_IRQ_SOURCE_HPD4:
1400                         hpd_id = HPD_SOURCEID4;
1401                 break;
1402                 case DC_IRQ_SOURCE_HPD5:
1403                         hpd_id = HPD_SOURCEID5;
1404                 break;
1405                 case DC_IRQ_SOURCE_HPD6:
1406                         hpd_id = HPD_SOURCEID6;
1407                 break;
1408                 default:
1409                         BREAK_TO_DEBUGGER();
1410                 break;
1411                 }
1412
1413                 dal_gpio_destroy_irq(&hpd);
1414         }
1415
1416         return hpd_id;
1417 }
1418
1419 static enum channel_id get_ddc_line(struct dc_link *link)
1420 {
1421         struct ddc *ddc;
1422         enum channel_id channel;
1423
1424         channel = CHANNEL_ID_UNKNOWN;
1425
1426         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
1427
1428         if (ddc) {
1429                 switch (dal_ddc_get_line(ddc)) {
1430                 case GPIO_DDC_LINE_DDC1:
1431                         channel = CHANNEL_ID_DDC1;
1432                         break;
1433                 case GPIO_DDC_LINE_DDC2:
1434                         channel = CHANNEL_ID_DDC2;
1435                         break;
1436                 case GPIO_DDC_LINE_DDC3:
1437                         channel = CHANNEL_ID_DDC3;
1438                         break;
1439                 case GPIO_DDC_LINE_DDC4:
1440                         channel = CHANNEL_ID_DDC4;
1441                         break;
1442                 case GPIO_DDC_LINE_DDC5:
1443                         channel = CHANNEL_ID_DDC5;
1444                         break;
1445                 case GPIO_DDC_LINE_DDC6:
1446                         channel = CHANNEL_ID_DDC6;
1447                         break;
1448                 case GPIO_DDC_LINE_DDC_VGA:
1449                         channel = CHANNEL_ID_DDC_VGA;
1450                         break;
1451                 case GPIO_DDC_LINE_I2C_PAD:
1452                         channel = CHANNEL_ID_I2C_PAD;
1453                         break;
1454                 default:
1455                         BREAK_TO_DEBUGGER();
1456                         break;
1457                 }
1458         }
1459
1460         return channel;
1461 }
1462
1463 static enum transmitter translate_encoder_to_transmitter(struct graphics_object_id encoder)
1464 {
1465         switch (encoder.id) {
1466         case ENCODER_ID_INTERNAL_UNIPHY:
1467                 switch (encoder.enum_id) {
1468                 case ENUM_ID_1:
1469                         return TRANSMITTER_UNIPHY_A;
1470                 case ENUM_ID_2:
1471                         return TRANSMITTER_UNIPHY_B;
1472                 default:
1473                         return TRANSMITTER_UNKNOWN;
1474                 }
1475         break;
1476         case ENCODER_ID_INTERNAL_UNIPHY1:
1477                 switch (encoder.enum_id) {
1478                 case ENUM_ID_1:
1479                         return TRANSMITTER_UNIPHY_C;
1480                 case ENUM_ID_2:
1481                         return TRANSMITTER_UNIPHY_D;
1482                 default:
1483                         return TRANSMITTER_UNKNOWN;
1484                 }
1485         break;
1486         case ENCODER_ID_INTERNAL_UNIPHY2:
1487                 switch (encoder.enum_id) {
1488                 case ENUM_ID_1:
1489                         return TRANSMITTER_UNIPHY_E;
1490                 case ENUM_ID_2:
1491                         return TRANSMITTER_UNIPHY_F;
1492                 default:
1493                         return TRANSMITTER_UNKNOWN;
1494                 }
1495         break;
1496         case ENCODER_ID_INTERNAL_UNIPHY3:
1497                 switch (encoder.enum_id) {
1498                 case ENUM_ID_1:
1499                         return TRANSMITTER_UNIPHY_G;
1500                 default:
1501                         return TRANSMITTER_UNKNOWN;
1502                 }
1503         break;
1504         case ENCODER_ID_EXTERNAL_NUTMEG:
1505                 switch (encoder.enum_id) {
1506                 case ENUM_ID_1:
1507                         return TRANSMITTER_NUTMEG_CRT;
1508                 default:
1509                         return TRANSMITTER_UNKNOWN;
1510                 }
1511         break;
1512         case ENCODER_ID_EXTERNAL_TRAVIS:
1513                 switch (encoder.enum_id) {
1514                 case ENUM_ID_1:
1515                         return TRANSMITTER_TRAVIS_CRT;
1516                 case ENUM_ID_2:
1517                         return TRANSMITTER_TRAVIS_LCD;
1518                 default:
1519                         return TRANSMITTER_UNKNOWN;
1520                 }
1521         break;
1522         default:
1523                 return TRANSMITTER_UNKNOWN;
1524         }
1525 }
1526
1527 static bool dc_link_construct_legacy(struct dc_link *link,
1528                                      const struct link_init_data *init_params)
1529 {
1530         uint8_t i;
1531         struct ddc_service_init_data ddc_service_init_data = { 0 };
1532         struct dc_context *dc_ctx = init_params->ctx;
1533         struct encoder_init_data enc_init_data = { 0 };
1534         struct panel_cntl_init_data panel_cntl_init_data = { 0 };
1535         struct integrated_info *info;
1536         struct dc_bios *bios = init_params->dc->ctx->dc_bios;
1537         const struct dc_vbios_funcs *bp_funcs = bios->funcs;
1538         struct bp_disp_connector_caps_info disp_connect_caps_info = { 0 };
1539
1540         DC_LOGGER_INIT(dc_ctx->logger);
1541
1542         info = kzalloc(sizeof(*info), GFP_KERNEL);
1543         if (!info)
1544                 goto create_fail;
1545
1546         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1547         link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
1548
1549         link->link_status.dpcd_caps = &link->dpcd_caps;
1550
1551         link->dc = init_params->dc;
1552         link->ctx = dc_ctx;
1553         link->link_index = init_params->link_index;
1554
1555         memset(&link->preferred_training_settings, 0,
1556                sizeof(struct dc_link_training_overrides));
1557         memset(&link->preferred_link_setting, 0,
1558                sizeof(struct dc_link_settings));
1559
1560         link->link_id =
1561                 bios->funcs->get_connector_id(bios, init_params->connector_index);
1562
1563         link->ep_type = DISPLAY_ENDPOINT_PHY;
1564
1565         DC_LOG_DC("BIOS object table - link_id: %d", link->link_id.id);
1566
1567         if (bios->funcs->get_disp_connector_caps_info) {
1568                 bios->funcs->get_disp_connector_caps_info(bios, link->link_id, &disp_connect_caps_info);
1569                 link->is_internal_display = disp_connect_caps_info.INTERNAL_DISPLAY;
1570                 DC_LOG_DC("BIOS object table - is_internal_display: %d", link->is_internal_display);
1571         }
1572
1573         if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
1574                 dm_output_to_console("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",
1575                                      __func__, init_params->connector_index,
1576                                      link->link_id.type, OBJECT_TYPE_CONNECTOR);
1577                 goto create_fail;
1578         }
1579
1580         if (link->dc->res_pool->funcs->link_init)
1581                 link->dc->res_pool->funcs->link_init(link);
1582
1583         link->hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
1584                                       link->ctx->gpio_service);
1585
1586         if (link->hpd_gpio) {
1587                 dal_gpio_open(link->hpd_gpio, GPIO_MODE_INTERRUPT);
1588                 dal_gpio_unlock_pin(link->hpd_gpio);
1589                 link->irq_source_hpd = dal_irq_get_source(link->hpd_gpio);
1590
1591                 DC_LOG_DC("BIOS object table - hpd_gpio id: %d", link->hpd_gpio->id);
1592                 DC_LOG_DC("BIOS object table - hpd_gpio en: %d", link->hpd_gpio->en);
1593         }
1594
1595         switch (link->link_id.id) {
1596         case CONNECTOR_ID_HDMI_TYPE_A:
1597                 link->connector_signal = SIGNAL_TYPE_HDMI_TYPE_A;
1598
1599                 break;
1600         case CONNECTOR_ID_SINGLE_LINK_DVID:
1601         case CONNECTOR_ID_SINGLE_LINK_DVII:
1602                 link->connector_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1603                 break;
1604         case CONNECTOR_ID_DUAL_LINK_DVID:
1605         case CONNECTOR_ID_DUAL_LINK_DVII:
1606                 link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1607                 break;
1608         case CONNECTOR_ID_DISPLAY_PORT:
1609         case CONNECTOR_ID_USBC:
1610                 link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;
1611
1612                 if (link->hpd_gpio)
1613                         link->irq_source_hpd_rx =
1614                                         dal_irq_get_rx_source(link->hpd_gpio);
1615
1616                 break;
1617         case CONNECTOR_ID_EDP:
1618                 link->connector_signal = SIGNAL_TYPE_EDP;
1619
1620                 if (link->hpd_gpio) {
1621                         if (!link->dc->config.allow_edp_hotplug_detection)
1622                                 link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1623
1624                         switch (link->dc->config.allow_edp_hotplug_detection) {
1625                         case 1: // only the 1st eDP handles hotplug
1626                                 if (link->link_index == 0)
1627                                         link->irq_source_hpd_rx =
1628                                                 dal_irq_get_rx_source(link->hpd_gpio);
1629                                 else
1630                                         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1631                                 break;
1632                         case 2: // only the 2nd eDP handles hotplug
1633                                 if (link->link_index == 1)
1634                                         link->irq_source_hpd_rx =
1635                                                 dal_irq_get_rx_source(link->hpd_gpio);
1636                                 else
1637                                         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1638                                 break;
1639                         default:
1640                                 break;
1641                         }
1642                 }
1643
1644                 break;
1645         case CONNECTOR_ID_LVDS:
1646                 link->connector_signal = SIGNAL_TYPE_LVDS;
1647                 break;
1648         default:
1649                 DC_LOG_WARNING("Unsupported Connector type:%d!\n",
1650                                link->link_id.id);
1651                 goto create_fail;
1652         }
1653
1654         /* TODO: #DAL3 Implement id to str function.*/
1655         LINK_INFO("Connector[%d] description:"
1656                   "signal %d\n",
1657                   init_params->connector_index,
1658                   link->connector_signal);
1659
1660         ddc_service_init_data.ctx = link->ctx;
1661         ddc_service_init_data.id = link->link_id;
1662         ddc_service_init_data.link = link;
1663         link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1664
1665         if (!link->ddc) {
1666                 DC_ERROR("Failed to create ddc_service!\n");
1667                 goto ddc_create_fail;
1668         }
1669
1670         if (!link->ddc->ddc_pin) {
1671                 DC_ERROR("Failed to get I2C info for connector!\n");
1672                 goto ddc_create_fail;
1673         }
1674
1675         link->ddc_hw_inst =
1676                 dal_ddc_get_line(dal_ddc_service_get_ddc_pin(link->ddc));
1677
1678
1679         if (link->dc->res_pool->funcs->panel_cntl_create &&
1680                 (link->link_id.id == CONNECTOR_ID_EDP ||
1681                         link->link_id.id == CONNECTOR_ID_LVDS)) {
1682                 panel_cntl_init_data.ctx = dc_ctx;
1683                 panel_cntl_init_data.inst =
1684                         panel_cntl_init_data.ctx->dc_edp_id_count;
1685                 link->panel_cntl =
1686                         link->dc->res_pool->funcs->panel_cntl_create(
1687                                                                 &panel_cntl_init_data);
1688                 panel_cntl_init_data.ctx->dc_edp_id_count++;
1689
1690                 if (link->panel_cntl == NULL) {
1691                         DC_ERROR("Failed to create link panel_cntl!\n");
1692                         goto panel_cntl_create_fail;
1693                 }
1694         }
1695
1696         enc_init_data.ctx = dc_ctx;
1697         bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0,
1698                               &enc_init_data.encoder);
1699         enc_init_data.connector = link->link_id;
1700         enc_init_data.channel = get_ddc_line(link);
1701         enc_init_data.hpd_source = get_hpd_line(link);
1702
1703         link->hpd_src = enc_init_data.hpd_source;
1704
1705         enc_init_data.transmitter =
1706                 translate_encoder_to_transmitter(enc_init_data.encoder);
1707         link->link_enc =
1708                 link->dc->res_pool->funcs->link_enc_create(dc_ctx, &enc_init_data);
1709
1710         if (!link->link_enc) {
1711                 DC_ERROR("Failed to create link encoder!\n");
1712                 goto link_enc_create_fail;
1713         }
1714
1715         DC_LOG_DC("BIOS object table - DP_IS_USB_C: %d", link->link_enc->features.flags.bits.DP_IS_USB_C);
1716         DC_LOG_DC("BIOS object table - IS_DP2_CAPABLE: %d", link->link_enc->features.flags.bits.IS_DP2_CAPABLE);
1717
1718         /* Update link encoder tracking variables. These are used for the dynamic
1719          * assignment of link encoders to streams.
1720          */
1721         link->eng_id = link->link_enc->preferred_engine;
1722         link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = link->link_enc;
1723         link->dc->res_pool->dig_link_enc_count++;
1724
1725         link->link_enc_hw_inst = link->link_enc->transmitter;
1726
1727         for (i = 0; i < 4; i++) {
1728                 if (bp_funcs->get_device_tag(dc_ctx->dc_bios,
1729                                              link->link_id, i,
1730                                              &link->device_tag) != BP_RESULT_OK) {
1731                         DC_ERROR("Failed to find device tag!\n");
1732                         goto device_tag_fail;
1733                 }
1734
1735                 /* Look for device tag that matches connector signal,
1736                  * CRT for rgb, LCD for other supported signal tyes
1737                  */
1738                 if (!bp_funcs->is_device_id_supported(dc_ctx->dc_bios,
1739                                                       link->device_tag.dev_id))
1740                         continue;
1741                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT &&
1742                     link->connector_signal != SIGNAL_TYPE_RGB)
1743                         continue;
1744                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD &&
1745                     link->connector_signal == SIGNAL_TYPE_RGB)
1746                         continue;
1747
1748                 DC_LOG_DC("BIOS object table - device_tag.acpi_device: %d", link->device_tag.acpi_device);
1749                 DC_LOG_DC("BIOS object table - device_tag.dev_id.device_type: %d", link->device_tag.dev_id.device_type);
1750                 DC_LOG_DC("BIOS object table - device_tag.dev_id.enum_id: %d", link->device_tag.dev_id.enum_id);
1751                 break;
1752         }
1753
1754         if (bios->integrated_info)
1755                 memcpy(info, bios->integrated_info, sizeof(*info));
1756
1757         /* Look for channel mapping corresponding to connector and device tag */
1758         for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
1759                 struct external_display_path *path =
1760                         &info->ext_disp_conn_info.path[i];
1761
1762                 if (path->device_connector_id.enum_id == link->link_id.enum_id &&
1763                     path->device_connector_id.id == link->link_id.id &&
1764                     path->device_connector_id.type == link->link_id.type) {
1765                         if (link->device_tag.acpi_device != 0 &&
1766                             path->device_acpi_enum == link->device_tag.acpi_device) {
1767                                 link->ddi_channel_mapping = path->channel_mapping;
1768                                 link->chip_caps = path->caps;
1769                                 DC_LOG_DC("BIOS object table - ddi_channel_mapping: 0x%04X", link->ddi_channel_mapping.raw);
1770                                 DC_LOG_DC("BIOS object table - chip_caps: %d", link->chip_caps);
1771                         } else if (path->device_tag ==
1772                                    link->device_tag.dev_id.raw_device_tag) {
1773                                 link->ddi_channel_mapping = path->channel_mapping;
1774                                 link->chip_caps = path->caps;
1775                                 DC_LOG_DC("BIOS object table - ddi_channel_mapping: 0x%04X", link->ddi_channel_mapping.raw);
1776                                 DC_LOG_DC("BIOS object table - chip_caps: %d", link->chip_caps);
1777                         }
1778
1779                         if (link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) {
1780                                 link->bios_forced_drive_settings.VOLTAGE_SWING =
1781                                                 (info->ext_disp_conn_info.fixdpvoltageswing & 0x3);
1782                                 link->bios_forced_drive_settings.PRE_EMPHASIS =
1783                                                 ((info->ext_disp_conn_info.fixdpvoltageswing >> 2) & 0x3);
1784                         }
1785
1786                         break;
1787                 }
1788         }
1789
1790         if (bios->funcs->get_atom_dc_golden_table)
1791                 bios->funcs->get_atom_dc_golden_table(bios);
1792
1793         /*
1794          * TODO check if GPIO programmed correctly
1795          *
1796          * If GPIO isn't programmed correctly HPD might not rise or drain
1797          * fast enough, leading to bounces.
1798          */
1799         program_hpd_filter(link);
1800
1801         link->psr_settings.psr_vtotal_control_support = false;
1802         link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
1803
1804         DC_LOG_DC("BIOS object table - %s finished successfully.\n", __func__);
1805         kfree(info);
1806         return true;
1807 device_tag_fail:
1808         link->link_enc->funcs->destroy(&link->link_enc);
1809 link_enc_create_fail:
1810         if (link->panel_cntl != NULL)
1811                 link->panel_cntl->funcs->destroy(&link->panel_cntl);
1812 panel_cntl_create_fail:
1813         dal_ddc_service_destroy(&link->ddc);
1814 ddc_create_fail:
1815 create_fail:
1816
1817         if (link->hpd_gpio) {
1818                 dal_gpio_destroy_irq(&link->hpd_gpio);
1819                 link->hpd_gpio = NULL;
1820         }
1821
1822         DC_LOG_DC("BIOS object table - %s failed.\n", __func__);
1823         kfree(info);
1824
1825         return false;
1826 }
1827
1828 static bool dc_link_construct_dpia(struct dc_link *link,
1829                                    const struct link_init_data *init_params)
1830 {
1831         struct ddc_service_init_data ddc_service_init_data = { 0 };
1832         struct dc_context *dc_ctx = init_params->ctx;
1833
1834         DC_LOGGER_INIT(dc_ctx->logger);
1835
1836         /* Initialized irq source for hpd and hpd rx */
1837         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1838         link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
1839         link->link_status.dpcd_caps = &link->dpcd_caps;
1840
1841         link->dc = init_params->dc;
1842         link->ctx = dc_ctx;
1843         link->link_index = init_params->link_index;
1844
1845         memset(&link->preferred_training_settings, 0,
1846                sizeof(struct dc_link_training_overrides));
1847         memset(&link->preferred_link_setting, 0,
1848                sizeof(struct dc_link_settings));
1849
1850         /* Dummy Init for linkid */
1851         link->link_id.type = OBJECT_TYPE_CONNECTOR;
1852         link->link_id.id = CONNECTOR_ID_DISPLAY_PORT;
1853         link->link_id.enum_id = ENUM_ID_1 + init_params->connector_index;
1854         link->is_internal_display = false;
1855         link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;
1856         LINK_INFO("Connector[%d] description:signal %d\n",
1857                   init_params->connector_index,
1858                   link->connector_signal);
1859
1860         link->ep_type = DISPLAY_ENDPOINT_USB4_DPIA;
1861         link->is_dig_mapping_flexible = true;
1862
1863         /* TODO: Initialize link : funcs->link_init */
1864
1865         ddc_service_init_data.ctx = link->ctx;
1866         ddc_service_init_data.id = link->link_id;
1867         ddc_service_init_data.link = link;
1868         /* Set indicator for dpia link so that ddc won't be created */
1869         ddc_service_init_data.is_dpia_link = true;
1870
1871         link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1872         if (!link->ddc) {
1873                 DC_ERROR("Failed to create ddc_service!\n");
1874                 goto ddc_create_fail;
1875         }
1876
1877         /* Set dpia port index : 0 to number of dpia ports */
1878         link->ddc_hw_inst = init_params->connector_index;
1879
1880         /* TODO: Create link encoder */
1881
1882         link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
1883
1884         /* Some docks seem to NAK I2C writes to segment pointer with mot=0. */
1885         link->wa_flags.dp_mot_reset_segment = true;
1886
1887         return true;
1888
1889 ddc_create_fail:
1890         return false;
1891 }
1892
1893 static bool dc_link_construct(struct dc_link *link,
1894                               const struct link_init_data *init_params)
1895 {
1896         /* Handle dpia case */
1897         if (init_params->is_dpia_link)
1898                 return dc_link_construct_dpia(link, init_params);
1899         else
1900                 return dc_link_construct_legacy(link, init_params);
1901 }
1902 /*******************************************************************************
1903  * Public functions
1904  ******************************************************************************/
1905 struct dc_link *link_create(const struct link_init_data *init_params)
1906 {
1907         struct dc_link *link =
1908                         kzalloc(sizeof(*link), GFP_KERNEL);
1909
1910         if (NULL == link)
1911                 goto alloc_fail;
1912
1913         if (false == dc_link_construct(link, init_params))
1914                 goto construct_fail;
1915
1916         /*
1917          * Must use preferred_link_setting, not reported_link_cap or verified_link_cap,
1918          * since struct preferred_link_setting won't be reset after S3.
1919          */
1920         link->preferred_link_setting.dpcd_source_device_specific_field_support = true;
1921
1922         return link;
1923
1924 construct_fail:
1925         kfree(link);
1926
1927 alloc_fail:
1928         return NULL;
1929 }
1930
1931 void link_destroy(struct dc_link **link)
1932 {
1933         dc_link_destruct(*link);
1934         kfree(*link);
1935         *link = NULL;
1936 }
1937
1938 static void enable_stream_features(struct pipe_ctx *pipe_ctx)
1939 {
1940         struct dc_stream_state *stream = pipe_ctx->stream;
1941
1942         if (pipe_ctx->stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) {
1943                 struct dc_link *link = stream->link;
1944                 union down_spread_ctrl old_downspread;
1945                 union down_spread_ctrl new_downspread;
1946
1947                 memset(&old_downspread, 0, sizeof(old_downspread));
1948
1949                 core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,
1950                                 &old_downspread.raw, sizeof(old_downspread));
1951
1952                 new_downspread.raw = old_downspread.raw;
1953
1954                 new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
1955                                 (stream->ignore_msa_timing_param) ? 1 : 0;
1956
1957                 if (new_downspread.raw != old_downspread.raw) {
1958                         core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
1959                                 &new_downspread.raw, sizeof(new_downspread));
1960                 }
1961
1962         } else {
1963                 dm_helpers_mst_enable_stream_features(stream);
1964         }
1965 }
1966
1967 static enum dc_status enable_link_dp(struct dc_state *state,
1968                                      struct pipe_ctx *pipe_ctx)
1969 {
1970         struct dc_stream_state *stream = pipe_ctx->stream;
1971         enum dc_status status;
1972         bool skip_video_pattern;
1973         struct dc_link *link = stream->link;
1974         const struct dc_link_settings *link_settings =
1975                         &pipe_ctx->link_config.dp_link_settings;
1976         bool fec_enable;
1977         int i;
1978         bool apply_seamless_boot_optimization = false;
1979         uint32_t bl_oled_enable_delay = 50; // in ms
1980         uint32_t post_oui_delay = 30; // 30ms
1981         /* Reduce link bandwidth between failed link training attempts. */
1982         bool do_fallback = false;
1983
1984         // check for seamless boot
1985         for (i = 0; i < state->stream_count; i++) {
1986                 if (state->streams[i]->apply_seamless_boot_optimization) {
1987                         apply_seamless_boot_optimization = true;
1988                         break;
1989                 }
1990         }
1991
1992         /* Train with fallback when enabling DPIA link. Conventional links are
1993          * trained with fallback during sink detection.
1994          */
1995         if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
1996                 do_fallback = true;
1997
1998         /*
1999          * Temporary w/a to get DP2.0 link rates to work with SST.
2000          * TODO DP2.0 - Workaround: Remove w/a if and when the issue is resolved.
2001          */
2002         if (dp_get_link_encoding_format(link_settings) == DP_128b_132b_ENCODING &&
2003                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
2004                         link->dc->debug.set_mst_en_for_sst) {
2005                 dp_enable_mst_on_sink(link, true);
2006         }
2007
2008         if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {
2009                 /*in case it is not on*/
2010                 if (!link->dc->config.edp_no_power_sequencing)
2011                         link->dc->hwss.edp_power_control(link, true);
2012                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
2013         }
2014
2015         if (dp_get_link_encoding_format(link_settings) == DP_128b_132b_ENCODING) {
2016                 /* TODO - DP2.0 HW: calculate 32 symbol clock for HPO encoder */
2017         } else {
2018                 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
2019                                 link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
2020                 if (state->clk_mgr && !apply_seamless_boot_optimization)
2021                         state->clk_mgr->funcs->update_clocks(state->clk_mgr,
2022                                         state, false);
2023         }
2024
2025         // during mode switch we do DP_SET_POWER off then on, and OUI is lost
2026         dpcd_set_source_specific_data(link);
2027         if (link->dpcd_sink_ext_caps.raw != 0) {
2028                 post_oui_delay += link->panel_config.pps.extra_post_OUI_ms;
2029                 msleep(post_oui_delay);
2030         }
2031
2032         // similarly, mode switch can cause loss of cable ID
2033         dpcd_write_cable_id_to_dprx(link);
2034
2035         skip_video_pattern = true;
2036
2037         if (link_settings->link_rate == LINK_RATE_LOW)
2038                 skip_video_pattern = false;
2039
2040         if (perform_link_training_with_retries(link_settings,
2041                                                skip_video_pattern,
2042                                                LINK_TRAINING_ATTEMPTS,
2043                                                pipe_ctx,
2044                                                pipe_ctx->stream->signal,
2045                                                do_fallback)) {
2046                 status = DC_OK;
2047         } else {
2048                 status = DC_FAIL_DP_LINK_TRAINING;
2049         }
2050
2051         if (link->preferred_training_settings.fec_enable)
2052                 fec_enable = *link->preferred_training_settings.fec_enable;
2053         else
2054                 fec_enable = true;
2055
2056         if (dp_get_link_encoding_format(link_settings) == DP_8b_10b_ENCODING)
2057                 dp_set_fec_enable(link, fec_enable);
2058
2059         // during mode set we do DP_SET_POWER off then on, aux writes are lost
2060         if (link->dpcd_sink_ext_caps.bits.oled == 1 ||
2061                 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 ||
2062                 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) {
2063                 dc_link_set_default_brightness_aux(link); // TODO: use cached if known
2064                 if (link->dpcd_sink_ext_caps.bits.oled == 1)
2065                         msleep(bl_oled_enable_delay);
2066                 dc_link_backlight_enable_aux(link, true);
2067         }
2068
2069         return status;
2070 }
2071
2072 static enum dc_status enable_link_edp(
2073                 struct dc_state *state,
2074                 struct pipe_ctx *pipe_ctx)
2075 {
2076         return enable_link_dp(state, pipe_ctx);
2077 }
2078
2079 static enum dc_status enable_link_dp_mst(
2080                 struct dc_state *state,
2081                 struct pipe_ctx *pipe_ctx)
2082 {
2083         struct dc_link *link = pipe_ctx->stream->link;
2084
2085         /* sink signal type after MST branch is MST. Multiple MST sinks
2086          * share one link. Link DP PHY is enable or training only once.
2087          */
2088         if (link->link_status.link_active)
2089                 return DC_OK;
2090
2091         /* clear payload table */
2092         dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link);
2093
2094         /* to make sure the pending down rep can be processed
2095          * before enabling the link
2096          */
2097         dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link);
2098
2099         /* set the sink to MST mode before enabling the link */
2100         dp_enable_mst_on_sink(link, true);
2101
2102         return enable_link_dp(state, pipe_ctx);
2103 }
2104
2105 void dc_link_blank_all_dp_displays(struct dc *dc)
2106 {
2107         unsigned int i;
2108         uint8_t dpcd_power_state = '\0';
2109         enum dc_status status = DC_ERROR_UNEXPECTED;
2110
2111         for (i = 0; i < dc->link_count; i++) {
2112                 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) ||
2113                         (dc->links[i]->priv == NULL) || (dc->links[i]->local_sink == NULL))
2114                         continue;
2115
2116                 /* DP 2.0 spec requires that we read LTTPR caps first */
2117                 dp_retrieve_lttpr_cap(dc->links[i]);
2118                 /* if any of the displays are lit up turn them off */
2119                 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,
2120                                                         &dpcd_power_state, sizeof(dpcd_power_state));
2121
2122                 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0)
2123                         dc_link_blank_dp_stream(dc->links[i], true);
2124         }
2125
2126 }
2127
2128 void dc_link_blank_all_edp_displays(struct dc *dc)
2129 {
2130         unsigned int i;
2131         uint8_t dpcd_power_state = '\0';
2132         enum dc_status status = DC_ERROR_UNEXPECTED;
2133
2134         for (i = 0; i < dc->link_count; i++) {
2135                 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_EDP) ||
2136                         (!dc->links[i]->edp_sink_present))
2137                         continue;
2138
2139                 /* if any of the displays are lit up turn them off */
2140                 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,
2141                                                         &dpcd_power_state, sizeof(dpcd_power_state));
2142
2143                 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0)
2144                         dc_link_blank_dp_stream(dc->links[i], true);
2145         }
2146 }
2147
2148 void dc_link_blank_dp_stream(struct dc_link *link, bool hw_init)
2149 {
2150         unsigned int j;
2151         struct dc  *dc = link->ctx->dc;
2152         enum signal_type signal = link->connector_signal;
2153
2154         if ((signal == SIGNAL_TYPE_EDP) ||
2155                 (signal == SIGNAL_TYPE_DISPLAY_PORT)) {
2156                 if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
2157                         link->link_enc->funcs->get_dig_frontend &&
2158                         link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
2159                         unsigned int fe = link->link_enc->funcs->get_dig_frontend(link->link_enc);
2160
2161                         if (fe != ENGINE_ID_UNKNOWN)
2162                                 for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
2163                                         if (fe == dc->res_pool->stream_enc[j]->id) {
2164                                                 dc->res_pool->stream_enc[j]->funcs->dp_blank(link,
2165                                                                         dc->res_pool->stream_enc[j]);
2166                                                 break;
2167                                         }
2168                                 }
2169                 }
2170
2171                 if ((!link->wa_flags.dp_keep_receiver_powered) || hw_init)
2172                         dp_receiver_power_ctrl(link, false);
2173         }
2174 }
2175
2176 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
2177                 enum engine_id eng_id,
2178                 struct ext_hdmi_settings *settings)
2179 {
2180         bool result = false;
2181         int i = 0;
2182         struct integrated_info *integrated_info =
2183                         pipe_ctx->stream->ctx->dc_bios->integrated_info;
2184
2185         if (integrated_info == NULL)
2186                 return false;
2187
2188         /*
2189          * Get retimer settings from sbios for passing SI eye test for DCE11
2190          * The setting values are varied based on board revision and port id
2191          * Therefore the setting values of each ports is passed by sbios.
2192          */
2193
2194         // Check if current bios contains ext Hdmi settings
2195         if (integrated_info->gpu_cap_info & 0x20) {
2196                 switch (eng_id) {
2197                 case ENGINE_ID_DIGA:
2198                         settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr;
2199                         settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;
2200                         settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num;
2201                         memmove(settings->reg_settings,
2202                                         integrated_info->dp0_ext_hdmi_reg_settings,
2203                                         sizeof(integrated_info->dp0_ext_hdmi_reg_settings));
2204                         memmove(settings->reg_settings_6g,
2205                                         integrated_info->dp0_ext_hdmi_6g_reg_settings,
2206                                         sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings));
2207                         result = true;
2208                         break;
2209                 case ENGINE_ID_DIGB:
2210                         settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr;
2211                         settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;
2212                         settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num;
2213                         memmove(settings->reg_settings,
2214                                         integrated_info->dp1_ext_hdmi_reg_settings,
2215                                         sizeof(integrated_info->dp1_ext_hdmi_reg_settings));
2216                         memmove(settings->reg_settings_6g,
2217                                         integrated_info->dp1_ext_hdmi_6g_reg_settings,
2218                                         sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings));
2219                         result = true;
2220                         break;
2221                 case ENGINE_ID_DIGC:
2222                         settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr;
2223                         settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;
2224                         settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num;
2225                         memmove(settings->reg_settings,
2226                                         integrated_info->dp2_ext_hdmi_reg_settings,
2227                                         sizeof(integrated_info->dp2_ext_hdmi_reg_settings));
2228                         memmove(settings->reg_settings_6g,
2229                                         integrated_info->dp2_ext_hdmi_6g_reg_settings,
2230                                         sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings));
2231                         result = true;
2232                         break;
2233                 case ENGINE_ID_DIGD:
2234                         settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr;
2235                         settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;
2236                         settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num;
2237                         memmove(settings->reg_settings,
2238                                         integrated_info->dp3_ext_hdmi_reg_settings,
2239                                         sizeof(integrated_info->dp3_ext_hdmi_reg_settings));
2240                         memmove(settings->reg_settings_6g,
2241                                         integrated_info->dp3_ext_hdmi_6g_reg_settings,
2242                                         sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings));
2243                         result = true;
2244                         break;
2245                 default:
2246                         break;
2247                 }
2248
2249                 if (result == true) {
2250                         // Validate settings from bios integrated info table
2251                         if (settings->slv_addr == 0)
2252                                 return false;
2253                         if (settings->reg_num > 9)
2254                                 return false;
2255                         if (settings->reg_num_6g > 3)
2256                                 return false;
2257
2258                         for (i = 0; i < settings->reg_num; i++) {
2259                                 if (settings->reg_settings[i].i2c_reg_index > 0x20)
2260                                         return false;
2261                         }
2262
2263                         for (i = 0; i < settings->reg_num_6g; i++) {
2264                                 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20)
2265                                         return false;
2266                         }
2267                 }
2268         }
2269
2270         return result;
2271 }
2272
2273 static bool i2c_write(struct pipe_ctx *pipe_ctx,
2274                 uint8_t address, uint8_t *buffer, uint32_t length)
2275 {
2276         struct i2c_command cmd = {0};
2277         struct i2c_payload payload = {0};
2278
2279         memset(&payload, 0, sizeof(payload));
2280         memset(&cmd, 0, sizeof(cmd));
2281
2282         cmd.number_of_payloads = 1;
2283         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
2284         cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;
2285
2286         payload.address = address;
2287         payload.data = buffer;
2288         payload.length = length;
2289         payload.write = true;
2290         cmd.payloads = &payload;
2291
2292         if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx,
2293                         pipe_ctx->stream->link, &cmd))
2294                 return true;
2295
2296         return false;
2297 }
2298
2299 static void write_i2c_retimer_setting(
2300                 struct pipe_ctx *pipe_ctx,
2301                 bool is_vga_mode,
2302                 bool is_over_340mhz,
2303                 struct ext_hdmi_settings *settings)
2304 {
2305         uint8_t slave_address = (settings->slv_addr >> 1);
2306         uint8_t buffer[2];
2307         const uint8_t apply_rx_tx_change = 0x4;
2308         uint8_t offset = 0xA;
2309         uint8_t value = 0;
2310         int i = 0;
2311         bool i2c_success = false;
2312         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2313
2314         memset(&buffer, 0, sizeof(buffer));
2315
2316         /* Start Ext-Hdmi programming*/
2317
2318         for (i = 0; i < settings->reg_num; i++) {
2319                 /* Apply 3G settings */
2320                 if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
2321
2322                         buffer[0] = settings->reg_settings[i].i2c_reg_index;
2323                         buffer[1] = settings->reg_settings[i].i2c_reg_val;
2324                         i2c_success = i2c_write(pipe_ctx, slave_address,
2325                                                 buffer, sizeof(buffer));
2326                         RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2327                                 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2328                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2329
2330                         if (!i2c_success)
2331                                 goto i2c_write_fail;
2332
2333                         /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
2334                          * needs to be set to 1 on every 0xA-0xC write.
2335                          */
2336                         if (settings->reg_settings[i].i2c_reg_index == 0xA ||
2337                                 settings->reg_settings[i].i2c_reg_index == 0xB ||
2338                                 settings->reg_settings[i].i2c_reg_index == 0xC) {
2339
2340                                 /* Query current value from offset 0xA */
2341                                 if (settings->reg_settings[i].i2c_reg_index == 0xA)
2342                                         value = settings->reg_settings[i].i2c_reg_val;
2343                                 else {
2344                                         i2c_success =
2345                                                 dal_ddc_service_query_ddc_data(
2346                                                 pipe_ctx->stream->link->ddc,
2347                                                 slave_address, &offset, 1, &value, 1);
2348                                         if (!i2c_success)
2349                                                 goto i2c_write_fail;
2350                                 }
2351
2352                                 buffer[0] = offset;
2353                                 /* Set APPLY_RX_TX_CHANGE bit to 1 */
2354                                 buffer[1] = value | apply_rx_tx_change;
2355                                 i2c_success = i2c_write(pipe_ctx, slave_address,
2356                                                 buffer, sizeof(buffer));
2357                                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2358                                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2359                                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2360                                 if (!i2c_success)
2361                                         goto i2c_write_fail;
2362                         }
2363                 }
2364         }
2365
2366         /* Apply 3G settings */
2367         if (is_over_340mhz) {
2368                 for (i = 0; i < settings->reg_num_6g; i++) {
2369                         /* Apply 3G settings */
2370                         if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
2371
2372                                 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index;
2373                                 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val;
2374                                 i2c_success = i2c_write(pipe_ctx, slave_address,
2375                                                         buffer, sizeof(buffer));
2376                                 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\
2377                                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2378                                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2379
2380                                 if (!i2c_success)
2381                                         goto i2c_write_fail;
2382
2383                                 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
2384                                  * needs to be set to 1 on every 0xA-0xC write.
2385                                  */
2386                                 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA ||
2387                                         settings->reg_settings_6g[i].i2c_reg_index == 0xB ||
2388                                         settings->reg_settings_6g[i].i2c_reg_index == 0xC) {
2389
2390                                         /* Query current value from offset 0xA */
2391                                         if (settings->reg_settings_6g[i].i2c_reg_index == 0xA)
2392                                                 value = settings->reg_settings_6g[i].i2c_reg_val;
2393                                         else {
2394                                                 i2c_success =
2395                                                                 dal_ddc_service_query_ddc_data(
2396                                                                 pipe_ctx->stream->link->ddc,
2397                                                                 slave_address, &offset, 1, &value, 1);
2398                                                 if (!i2c_success)
2399                                                         goto i2c_write_fail;
2400                                         }
2401
2402                                         buffer[0] = offset;
2403                                         /* Set APPLY_RX_TX_CHANGE bit to 1 */
2404                                         buffer[1] = value | apply_rx_tx_change;
2405                                         i2c_success = i2c_write(pipe_ctx, slave_address,
2406                                                         buffer, sizeof(buffer));
2407                                         RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2408                                                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2409                                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2410                                         if (!i2c_success)
2411                                                 goto i2c_write_fail;
2412                                 }
2413                         }
2414                 }
2415         }
2416
2417         if (is_vga_mode) {
2418                 /* Program additional settings if using 640x480 resolution */
2419
2420                 /* Write offset 0xFF to 0x01 */
2421                 buffer[0] = 0xff;
2422                 buffer[1] = 0x01;
2423                 i2c_success = i2c_write(pipe_ctx, slave_address,
2424                                 buffer, sizeof(buffer));
2425                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2426                                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2427                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2428                 if (!i2c_success)
2429                         goto i2c_write_fail;
2430
2431                 /* Write offset 0x00 to 0x23 */
2432                 buffer[0] = 0x00;
2433                 buffer[1] = 0x23;
2434                 i2c_success = i2c_write(pipe_ctx, slave_address,
2435                                 buffer, sizeof(buffer));
2436                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2437                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2438                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2439                 if (!i2c_success)
2440                         goto i2c_write_fail;
2441
2442                 /* Write offset 0xff to 0x00 */
2443                 buffer[0] = 0xff;
2444                 buffer[1] = 0x00;
2445                 i2c_success = i2c_write(pipe_ctx, slave_address,
2446                                 buffer, sizeof(buffer));
2447                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2448                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2449                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2450                 if (!i2c_success)
2451                         goto i2c_write_fail;
2452
2453         }
2454
2455         return;
2456
2457 i2c_write_fail:
2458         DC_LOG_DEBUG("Set retimer failed");
2459 }
2460
2461 static void write_i2c_default_retimer_setting(
2462                 struct pipe_ctx *pipe_ctx,
2463                 bool is_vga_mode,
2464                 bool is_over_340mhz)
2465 {
2466         uint8_t slave_address = (0xBA >> 1);
2467         uint8_t buffer[2];
2468         bool i2c_success = false;
2469         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2470
2471         memset(&buffer, 0, sizeof(buffer));
2472
2473         /* Program Slave Address for tuning single integrity */
2474         /* Write offset 0x0A to 0x13 */
2475         buffer[0] = 0x0A;
2476         buffer[1] = 0x13;
2477         i2c_success = i2c_write(pipe_ctx, slave_address,
2478                         buffer, sizeof(buffer));
2479         RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\
2480                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2481                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2482         if (!i2c_success)
2483                 goto i2c_write_fail;
2484
2485         /* Write offset 0x0A to 0x17 */
2486         buffer[0] = 0x0A;
2487         buffer[1] = 0x17;
2488         i2c_success = i2c_write(pipe_ctx, slave_address,
2489                         buffer, sizeof(buffer));
2490         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2491                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2492                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2493         if (!i2c_success)
2494                 goto i2c_write_fail;
2495
2496         /* Write offset 0x0B to 0xDA or 0xD8 */
2497         buffer[0] = 0x0B;
2498         buffer[1] = is_over_340mhz ? 0xDA : 0xD8;
2499         i2c_success = i2c_write(pipe_ctx, slave_address,
2500                         buffer, sizeof(buffer));
2501         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2502                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2503                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2504         if (!i2c_success)
2505                 goto i2c_write_fail;
2506
2507         /* Write offset 0x0A to 0x17 */
2508         buffer[0] = 0x0A;
2509         buffer[1] = 0x17;
2510         i2c_success = i2c_write(pipe_ctx, slave_address,
2511                         buffer, sizeof(buffer));
2512         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2513                 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2514                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2515         if (!i2c_success)
2516                 goto i2c_write_fail;
2517
2518         /* Write offset 0x0C to 0x1D or 0x91 */
2519         buffer[0] = 0x0C;
2520         buffer[1] = is_over_340mhz ? 0x1D : 0x91;
2521         i2c_success = i2c_write(pipe_ctx, slave_address,
2522                         buffer, sizeof(buffer));
2523         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2524                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2525                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2526         if (!i2c_success)
2527                 goto i2c_write_fail;
2528
2529         /* Write offset 0x0A to 0x17 */
2530         buffer[0] = 0x0A;
2531         buffer[1] = 0x17;
2532         i2c_success = i2c_write(pipe_ctx, slave_address,
2533                         buffer, sizeof(buffer));
2534         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2535                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2536                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2537         if (!i2c_success)
2538                 goto i2c_write_fail;
2539
2540
2541         if (is_vga_mode) {
2542                 /* Program additional settings if using 640x480 resolution */
2543
2544                 /* Write offset 0xFF to 0x01 */
2545                 buffer[0] = 0xff;
2546                 buffer[1] = 0x01;
2547                 i2c_success = i2c_write(pipe_ctx, slave_address,
2548                                 buffer, sizeof(buffer));
2549                 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2550                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2551                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2552                 if (!i2c_success)
2553                         goto i2c_write_fail;
2554
2555                 /* Write offset 0x00 to 0x23 */
2556                 buffer[0] = 0x00;
2557                 buffer[1] = 0x23;
2558                 i2c_success = i2c_write(pipe_ctx, slave_address,
2559                                 buffer, sizeof(buffer));
2560                 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2561                         offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2562                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2563                 if (!i2c_success)
2564                         goto i2c_write_fail;
2565
2566                 /* Write offset 0xff to 0x00 */
2567                 buffer[0] = 0xff;
2568                 buffer[1] = 0x00;
2569                 i2c_success = i2c_write(pipe_ctx, slave_address,
2570                                 buffer, sizeof(buffer));
2571                 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\
2572                         offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n",
2573                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2574                 if (!i2c_success)
2575                         goto i2c_write_fail;
2576         }
2577
2578         return;
2579
2580 i2c_write_fail:
2581         DC_LOG_DEBUG("Set default retimer failed");
2582 }
2583
2584 static void write_i2c_redriver_setting(
2585                 struct pipe_ctx *pipe_ctx,
2586                 bool is_over_340mhz)
2587 {
2588         uint8_t slave_address = (0xF0 >> 1);
2589         uint8_t buffer[16];
2590         bool i2c_success = false;
2591         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2592
2593         memset(&buffer, 0, sizeof(buffer));
2594
2595         // Program Slave Address for tuning single integrity
2596         buffer[3] = 0x4E;
2597         buffer[4] = 0x4E;
2598         buffer[5] = 0x4E;
2599         buffer[6] = is_over_340mhz ? 0x4E : 0x4A;
2600
2601         i2c_success = i2c_write(pipe_ctx, slave_address,
2602                                         buffer, sizeof(buffer));
2603         RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\
2604                 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\
2605                 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\
2606                 i2c_success = %d\n",
2607                 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0);
2608
2609         if (!i2c_success)
2610                 DC_LOG_DEBUG("Set redriver failed");
2611 }
2612
2613 static void disable_link(struct dc_link *link, const struct link_resource *link_res,
2614                 enum signal_type signal)
2615 {
2616         /*
2617          * TODO: implement call for dp_set_hw_test_pattern
2618          * it is needed for compliance testing
2619          */
2620
2621         /* Here we need to specify that encoder output settings
2622          * need to be calculated as for the set mode,
2623          * it will lead to querying dynamic link capabilities
2624          * which should be done before enable output
2625          */
2626
2627         if (dc_is_dp_signal(signal)) {
2628                 /* SST DP, eDP */
2629                 struct dc_link_settings link_settings = link->cur_link_settings;
2630                 if (dc_is_dp_sst_signal(signal))
2631                         dp_disable_link_phy(link, link_res, signal);
2632                 else
2633                         dp_disable_link_phy_mst(link, link_res, signal);
2634
2635                 if (dc_is_dp_sst_signal(signal) ||
2636                                 link->mst_stream_alloc_table.stream_count == 0) {
2637                         if (dp_get_link_encoding_format(&link_settings) == DP_8b_10b_ENCODING) {
2638                                 dp_set_fec_enable(link, false);
2639                                 dp_set_fec_ready(link, link_res, false);
2640                         }
2641                 }
2642         } else if (signal != SIGNAL_TYPE_VIRTUAL) {
2643                 link->dc->hwss.disable_link_output(link, link_res, signal);
2644         }
2645
2646         if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2647                 /* MST disable link only when no stream use the link */
2648                 if (link->mst_stream_alloc_table.stream_count <= 0)
2649                         link->link_status.link_active = false;
2650         } else {
2651                 link->link_status.link_active = false;
2652         }
2653 }
2654
2655 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
2656 {
2657         struct dc_stream_state *stream = pipe_ctx->stream;
2658         struct dc_link *link = stream->link;
2659         enum dc_color_depth display_color_depth;
2660         enum engine_id eng_id;
2661         struct ext_hdmi_settings settings = {0};
2662         bool is_over_340mhz = false;
2663         bool is_vga_mode = (stream->timing.h_addressable == 640)
2664                         && (stream->timing.v_addressable == 480);
2665         struct dc *dc = pipe_ctx->stream->ctx->dc;
2666
2667         if (stream->phy_pix_clk == 0)
2668                 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2669         if (stream->phy_pix_clk > 340000)
2670                 is_over_340mhz = true;
2671
2672         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
2673                 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps &
2674                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
2675                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
2676                         /* DP159, Retimer settings */
2677                         eng_id = pipe_ctx->stream_res.stream_enc->id;
2678
2679                         if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) {
2680                                 write_i2c_retimer_setting(pipe_ctx,
2681                                                 is_vga_mode, is_over_340mhz, &settings);
2682                         } else {
2683                                 write_i2c_default_retimer_setting(pipe_ctx,
2684                                                 is_vga_mode, is_over_340mhz);
2685                         }
2686                 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
2687                         /* PI3EQX1204, Redriver settings */
2688                         write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);
2689                 }
2690         }
2691
2692         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2693                 dal_ddc_service_write_scdc_data(
2694                         stream->link->ddc,
2695                         stream->phy_pix_clk,
2696                         stream->timing.flags.LTE_340MCSC_SCRAMBLE);
2697
2698         memset(&stream->link->cur_link_settings, 0,
2699                         sizeof(struct dc_link_settings));
2700
2701         display_color_depth = stream->timing.display_color_depth;
2702         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
2703                 display_color_depth = COLOR_DEPTH_888;
2704
2705         dc->hwss.enable_tmds_link_output(
2706                         link,
2707                         &pipe_ctx->link_res,
2708                         pipe_ctx->stream->signal,
2709                         pipe_ctx->clock_source->id,
2710                         display_color_depth,
2711                         stream->phy_pix_clk);
2712
2713         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2714                 dal_ddc_service_read_scdc_data(link->ddc);
2715 }
2716
2717 static void enable_link_lvds(struct pipe_ctx *pipe_ctx)
2718 {
2719         struct dc_stream_state *stream = pipe_ctx->stream;
2720         struct dc_link *link = stream->link;
2721         struct dc *dc = stream->ctx->dc;
2722
2723         if (stream->phy_pix_clk == 0)
2724                 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2725
2726         memset(&stream->link->cur_link_settings, 0,
2727                         sizeof(struct dc_link_settings));
2728         dc->hwss.enable_lvds_link_output(
2729                         link,
2730                         &pipe_ctx->link_res,
2731                         pipe_ctx->clock_source->id,
2732                         stream->phy_pix_clk);
2733
2734 }
2735
2736 bool dc_power_alpm_dpcd_enable(struct dc_link *link, bool enable)
2737 {
2738         bool ret = false;
2739         union dpcd_alpm_configuration alpm_config;
2740
2741         if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) {
2742                 memset(&alpm_config, 0, sizeof(alpm_config));
2743
2744                 alpm_config.bits.ENABLE = (enable ? true : false);
2745                 ret = dm_helpers_dp_write_dpcd(link->ctx, link,
2746                                 DP_RECEIVER_ALPM_CONFIG, &alpm_config.raw,
2747                                 sizeof(alpm_config.raw));
2748         }
2749         return ret;
2750 }
2751
2752 /****************************enable_link***********************************/
2753 static enum dc_status enable_link(
2754                 struct dc_state *state,
2755                 struct pipe_ctx *pipe_ctx)
2756 {
2757         enum dc_status status = DC_ERROR_UNEXPECTED;
2758         struct dc_stream_state *stream = pipe_ctx->stream;
2759         struct dc_link *link = stream->link;
2760
2761         /* There's some scenarios where driver is unloaded with display
2762          * still enabled. When driver is reloaded, it may cause a display
2763          * to not light up if there is a mismatch between old and new
2764          * link settings. Need to call disable first before enabling at
2765          * new link settings.
2766          */
2767         if (link->link_status.link_active) {
2768                 disable_link(link, &pipe_ctx->link_res, pipe_ctx->stream->signal);
2769         }
2770
2771         switch (pipe_ctx->stream->signal) {
2772         case SIGNAL_TYPE_DISPLAY_PORT:
2773                 status = enable_link_dp(state, pipe_ctx);
2774                 break;
2775         case SIGNAL_TYPE_EDP:
2776                 status = enable_link_edp(state, pipe_ctx);
2777                 break;
2778         case SIGNAL_TYPE_DISPLAY_PORT_MST:
2779                 status = enable_link_dp_mst(state, pipe_ctx);
2780                 msleep(200);
2781                 break;
2782         case SIGNAL_TYPE_DVI_SINGLE_LINK:
2783         case SIGNAL_TYPE_DVI_DUAL_LINK:
2784         case SIGNAL_TYPE_HDMI_TYPE_A:
2785                 enable_link_hdmi(pipe_ctx);
2786                 status = DC_OK;
2787                 break;
2788         case SIGNAL_TYPE_LVDS:
2789                 enable_link_lvds(pipe_ctx);
2790                 status = DC_OK;
2791                 break;
2792         case SIGNAL_TYPE_VIRTUAL:
2793                 status = DC_OK;
2794                 break;
2795         default:
2796                 break;
2797         }
2798
2799         if (status == DC_OK)
2800                 pipe_ctx->stream->link->link_status.link_active = true;
2801
2802         return status;
2803 }
2804
2805 static uint32_t get_timing_pixel_clock_100hz(const struct dc_crtc_timing *timing)
2806 {
2807
2808         uint32_t pxl_clk = timing->pix_clk_100hz;
2809
2810         if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2811                 pxl_clk /= 2;
2812         else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
2813                 pxl_clk = pxl_clk * 2 / 3;
2814
2815         if (timing->display_color_depth == COLOR_DEPTH_101010)
2816                 pxl_clk = pxl_clk * 10 / 8;
2817         else if (timing->display_color_depth == COLOR_DEPTH_121212)
2818                 pxl_clk = pxl_clk * 12 / 8;
2819
2820         return pxl_clk;
2821 }
2822
2823 static bool dp_active_dongle_validate_timing(
2824                 const struct dc_crtc_timing *timing,
2825                 const struct dpcd_caps *dpcd_caps)
2826 {
2827         const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps;
2828
2829         switch (dpcd_caps->dongle_type) {
2830         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
2831         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
2832         case DISPLAY_DONGLE_DP_DVI_DONGLE:
2833                 if (timing->pixel_encoding == PIXEL_ENCODING_RGB)
2834                         return true;
2835                 else
2836                         return false;
2837         default:
2838                 break;
2839         }
2840
2841         if (dpcd_caps->dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER &&
2842                         dongle_caps->extendedCapValid == true) {
2843                 /* Check Pixel Encoding */
2844                 switch (timing->pixel_encoding) {
2845                 case PIXEL_ENCODING_RGB:
2846                 case PIXEL_ENCODING_YCBCR444:
2847                         break;
2848                 case PIXEL_ENCODING_YCBCR422:
2849                         if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through)
2850                                 return false;
2851                         break;
2852                 case PIXEL_ENCODING_YCBCR420:
2853                         if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through)
2854                                 return false;
2855                         break;
2856                 default:
2857                         /* Invalid Pixel Encoding*/
2858                         return false;
2859                 }
2860
2861                 switch (timing->display_color_depth) {
2862                 case COLOR_DEPTH_666:
2863                 case COLOR_DEPTH_888:
2864                         /*888 and 666 should always be supported*/
2865                         break;
2866                 case COLOR_DEPTH_101010:
2867                         if (dongle_caps->dp_hdmi_max_bpc < 10)
2868                                 return false;
2869                         break;
2870                 case COLOR_DEPTH_121212:
2871                         if (dongle_caps->dp_hdmi_max_bpc < 12)
2872                                 return false;
2873                         break;
2874                 case COLOR_DEPTH_141414:
2875                 case COLOR_DEPTH_161616:
2876                 default:
2877                         /* These color depths are currently not supported */
2878                         return false;
2879                 }
2880
2881                 /* Check 3D format */
2882                 switch (timing->timing_3d_format) {
2883                 case TIMING_3D_FORMAT_NONE:
2884                 case TIMING_3D_FORMAT_FRAME_ALTERNATE:
2885                         /*Only frame alternate 3D is supported on active dongle*/
2886                         break;
2887                 default:
2888                         /*other 3D formats are not supported due to bad infoframe translation */
2889                         return false;
2890                 }
2891
2892 #if defined(CONFIG_DRM_AMD_DC_DCN)
2893                 if (dongle_caps->dp_hdmi_frl_max_link_bw_in_kbps > 0) { // DP to HDMI FRL converter
2894                         struct dc_crtc_timing outputTiming = *timing;
2895
2896                         if (timing->flags.DSC && !timing->dsc_cfg.is_frl)
2897                                 /* DP input has DSC, HDMI FRL output doesn't have DSC, remove DSC from output timing */
2898                                 outputTiming.flags.DSC = 0;
2899                         if (dc_bandwidth_in_kbps_from_timing(&outputTiming) > dongle_caps->dp_hdmi_frl_max_link_bw_in_kbps)
2900                                 return false;
2901                 } else { // DP to HDMI TMDS converter
2902                         if (get_timing_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk_in_khz * 10))
2903                                 return false;
2904                 }
2905 #else
2906                 if (get_timing_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk_in_khz * 10))
2907                         return false;
2908 #endif
2909         }
2910
2911         if (dpcd_caps->channel_coding_cap.bits.DP_128b_132b_SUPPORTED == 0 &&
2912                         dpcd_caps->dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT == 0 &&
2913                         dongle_caps->dfp_cap_ext.supported) {
2914
2915                 if (dongle_caps->dfp_cap_ext.max_pixel_rate_in_mps < (timing->pix_clk_100hz / 10000))
2916                         return false;
2917
2918                 if (dongle_caps->dfp_cap_ext.max_video_h_active_width < timing->h_addressable)
2919                         return false;
2920
2921                 if (dongle_caps->dfp_cap_ext.max_video_v_active_height < timing->v_addressable)
2922                         return false;
2923
2924                 if (timing->pixel_encoding == PIXEL_ENCODING_RGB) {
2925                         if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
2926                                 return false;
2927                         if (timing->display_color_depth == COLOR_DEPTH_666 &&
2928                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_6bpc)
2929                                 return false;
2930                         else if (timing->display_color_depth == COLOR_DEPTH_888 &&
2931                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_8bpc)
2932                                 return false;
2933                         else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
2934                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_10bpc)
2935                                 return false;
2936                         else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
2937                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_12bpc)
2938                                 return false;
2939                         else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
2940                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_16bpc)
2941                                 return false;
2942                 } else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) {
2943                         if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
2944                                 return false;
2945                         if (timing->display_color_depth == COLOR_DEPTH_888 &&
2946                                         !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_8bpc)
2947                                 return false;
2948                         else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
2949                                         !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_10bpc)
2950                                 return false;
2951                         else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
2952                                         !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_12bpc)
2953                                 return false;
2954                         else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
2955                                         !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_16bpc)
2956                                 return false;
2957                 } else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
2958                         if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
2959                                 return false;
2960                         if (timing->display_color_depth == COLOR_DEPTH_888 &&
2961                                         !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_8bpc)
2962                                 return false;
2963                         else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
2964                                         !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_10bpc)
2965                                 return false;
2966                         else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
2967                                         !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_12bpc)
2968                                 return false;
2969                         else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
2970                                         !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_16bpc)
2971                                 return false;
2972                 } else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) {
2973                         if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
2974                                 return false;
2975                         if (timing->display_color_depth == COLOR_DEPTH_888 &&
2976                                         !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_8bpc)
2977                                 return false;
2978                         else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
2979                                         !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_10bpc)
2980                                 return false;
2981                         else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
2982                                         !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_12bpc)
2983                                 return false;
2984                         else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
2985                                         !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_16bpc)
2986                                 return false;
2987                 }
2988         }
2989
2990         return true;
2991 }
2992
2993 enum dc_status dc_link_validate_mode_timing(
2994                 const struct dc_stream_state *stream,
2995                 struct dc_link *link,
2996                 const struct dc_crtc_timing *timing)
2997 {
2998         uint32_t max_pix_clk = stream->link->dongle_max_pix_clk * 10;
2999         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
3000
3001         /* A hack to avoid failing any modes for EDID override feature on
3002          * topology change such as lower quality cable for DP or different dongle
3003          */
3004         if (link->remote_sinks[0] && link->remote_sinks[0]->sink_signal == SIGNAL_TYPE_VIRTUAL)
3005                 return DC_OK;
3006
3007         /* Passive Dongle */
3008         if (max_pix_clk != 0 && get_timing_pixel_clock_100hz(timing) > max_pix_clk)
3009                 return DC_EXCEED_DONGLE_CAP;
3010
3011         /* Active Dongle*/
3012         if (!dp_active_dongle_validate_timing(timing, dpcd_caps))
3013                 return DC_EXCEED_DONGLE_CAP;
3014
3015         switch (stream->signal) {
3016         case SIGNAL_TYPE_EDP:
3017         case SIGNAL_TYPE_DISPLAY_PORT:
3018                 if (!dp_validate_mode_timing(
3019                                 link,
3020                                 timing))
3021                         return DC_NO_DP_LINK_BANDWIDTH;
3022                 break;
3023
3024         default:
3025                 break;
3026         }
3027
3028         return DC_OK;
3029 }
3030
3031 static struct abm *get_abm_from_stream_res(const struct dc_link *link)
3032 {
3033         int i;
3034         struct dc *dc = NULL;
3035         struct abm *abm = NULL;
3036
3037         if (!link || !link->ctx)
3038                 return NULL;
3039
3040         dc = link->ctx->dc;
3041
3042         for (i = 0; i < MAX_PIPES; i++) {
3043                 struct pipe_ctx pipe_ctx = dc->current_state->res_ctx.pipe_ctx[i];
3044                 struct dc_stream_state *stream = pipe_ctx.stream;
3045
3046                 if (stream && stream->link == link) {
3047                         abm = pipe_ctx.stream_res.abm;
3048                         break;
3049                 }
3050         }
3051         return abm;
3052 }
3053
3054 int dc_link_get_backlight_level(const struct dc_link *link)
3055 {
3056         struct abm *abm = get_abm_from_stream_res(link);
3057         struct panel_cntl *panel_cntl = link->panel_cntl;
3058         struct dc  *dc = link->ctx->dc;
3059         struct dmcu *dmcu = dc->res_pool->dmcu;
3060         bool fw_set_brightness = true;
3061
3062         if (dmcu)
3063                 fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
3064
3065         if (!fw_set_brightness && panel_cntl->funcs->get_current_backlight)
3066                 return panel_cntl->funcs->get_current_backlight(panel_cntl);
3067         else if (abm != NULL && abm->funcs->get_current_backlight != NULL)
3068                 return (int) abm->funcs->get_current_backlight(abm);
3069         else
3070                 return DC_ERROR_UNEXPECTED;
3071 }
3072
3073 int dc_link_get_target_backlight_pwm(const struct dc_link *link)
3074 {
3075         struct abm *abm = get_abm_from_stream_res(link);
3076
3077         if (abm == NULL || abm->funcs->get_target_backlight == NULL)
3078                 return DC_ERROR_UNEXPECTED;
3079
3080         return (int) abm->funcs->get_target_backlight(abm);
3081 }
3082
3083 static struct pipe_ctx *get_pipe_from_link(const struct dc_link *link)
3084 {
3085         int i;
3086         struct dc *dc = link->ctx->dc;
3087         struct pipe_ctx *pipe_ctx = NULL;
3088
3089         for (i = 0; i < MAX_PIPES; i++) {
3090                 if (dc->current_state->res_ctx.pipe_ctx[i].stream) {
3091                         if (dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) {
3092                                 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
3093                                 break;
3094                         }
3095                 }
3096         }
3097
3098         return pipe_ctx;
3099 }
3100
3101 bool dc_link_set_backlight_level(const struct dc_link *link,
3102                 uint32_t backlight_pwm_u16_16,
3103                 uint32_t frame_ramp)
3104 {
3105         struct dc  *dc = link->ctx->dc;
3106
3107         DC_LOGGER_INIT(link->ctx->logger);
3108         DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",
3109                         backlight_pwm_u16_16, backlight_pwm_u16_16);
3110
3111         if (dc_is_embedded_signal(link->connector_signal)) {
3112                 struct pipe_ctx *pipe_ctx = get_pipe_from_link(link);
3113
3114                 if (pipe_ctx) {
3115                         /* Disable brightness ramping when the display is blanked
3116                          * as it can hang the DMCU
3117                          */
3118                         if (pipe_ctx->plane_state == NULL)
3119                                 frame_ramp = 0;
3120                 } else {
3121                         return false;
3122                 }
3123
3124                 dc->hwss.set_backlight_level(
3125                                 pipe_ctx,
3126                                 backlight_pwm_u16_16,
3127                                 frame_ramp);
3128         }
3129         return true;
3130 }
3131
3132 bool dc_link_set_psr_allow_active(struct dc_link *link, const bool *allow_active,
3133                 bool wait, bool force_static, const unsigned int *power_opts)
3134 {
3135         struct dc  *dc = link->ctx->dc;
3136         struct dmcu *dmcu = dc->res_pool->dmcu;
3137         struct dmub_psr *psr = dc->res_pool->psr;
3138         unsigned int panel_inst;
3139
3140         if (psr == NULL && force_static)
3141                 return false;
3142
3143         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
3144                 return false;
3145
3146         if (allow_active && link->type == dc_connection_none) {
3147                 // Don't enter PSR if panel is not connected
3148                 return false;
3149         }
3150
3151         /* Set power optimization flag */
3152         if (power_opts && link->psr_settings.psr_power_opt != *power_opts) {
3153                 link->psr_settings.psr_power_opt = *power_opts;
3154
3155                 if (psr != NULL && link->psr_settings.psr_feature_enabled && psr->funcs->psr_set_power_opt)
3156                         psr->funcs->psr_set_power_opt(psr, link->psr_settings.psr_power_opt, panel_inst);
3157         }
3158
3159         if (psr != NULL && link->psr_settings.psr_feature_enabled &&
3160                         force_static && psr->funcs->psr_force_static)
3161                 psr->funcs->psr_force_static(psr, panel_inst);
3162
3163         /* Enable or Disable PSR */
3164         if (allow_active && link->psr_settings.psr_allow_active != *allow_active) {
3165                 link->psr_settings.psr_allow_active = *allow_active;
3166
3167                 if (!link->psr_settings.psr_allow_active)
3168                         dc_z10_restore(dc);
3169
3170                 if (psr != NULL && link->psr_settings.psr_feature_enabled) {
3171                         psr->funcs->psr_enable(psr, link->psr_settings.psr_allow_active, wait, panel_inst);
3172                 } else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) &&
3173                         link->psr_settings.psr_feature_enabled)
3174                         dmcu->funcs->set_psr_enable(dmcu, link->psr_settings.psr_allow_active, wait);
3175                 else
3176                         return false;
3177         }
3178
3179         return true;
3180 }
3181
3182 bool dc_link_get_psr_state(const struct dc_link *link, enum dc_psr_state *state)
3183 {
3184         struct dc  *dc = link->ctx->dc;
3185         struct dmcu *dmcu = dc->res_pool->dmcu;
3186         struct dmub_psr *psr = dc->res_pool->psr;
3187         unsigned int panel_inst;
3188
3189         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
3190                 return false;
3191
3192         if (psr != NULL && link->psr_settings.psr_feature_enabled)
3193                 psr->funcs->psr_get_state(psr, state, panel_inst);
3194         else if (dmcu != NULL && link->psr_settings.psr_feature_enabled)
3195                 dmcu->funcs->get_psr_state(dmcu, state);
3196
3197         return true;
3198 }
3199
3200 static inline enum physical_phy_id
3201 transmitter_to_phy_id(enum transmitter transmitter_value)
3202 {
3203         switch (transmitter_value) {
3204         case TRANSMITTER_UNIPHY_A:
3205                 return PHYLD_0;
3206         case TRANSMITTER_UNIPHY_B:
3207                 return PHYLD_1;
3208         case TRANSMITTER_UNIPHY_C:
3209                 return PHYLD_2;
3210         case TRANSMITTER_UNIPHY_D:
3211                 return PHYLD_3;
3212         case TRANSMITTER_UNIPHY_E:
3213                 return PHYLD_4;
3214         case TRANSMITTER_UNIPHY_F:
3215                 return PHYLD_5;
3216         case TRANSMITTER_NUTMEG_CRT:
3217                 return PHYLD_6;
3218         case TRANSMITTER_TRAVIS_CRT:
3219                 return PHYLD_7;
3220         case TRANSMITTER_TRAVIS_LCD:
3221                 return PHYLD_8;
3222         case TRANSMITTER_UNIPHY_G:
3223                 return PHYLD_9;
3224         case TRANSMITTER_COUNT:
3225                 return PHYLD_COUNT;
3226         case TRANSMITTER_UNKNOWN:
3227                 return PHYLD_UNKNOWN;
3228         default:
3229                 WARN_ONCE(1, "Unknown transmitter value %d\n",
3230                           transmitter_value);
3231                 return PHYLD_UNKNOWN;
3232         }
3233 }
3234
3235 bool dc_link_setup_psr(struct dc_link *link,
3236                 const struct dc_stream_state *stream, struct psr_config *psr_config,
3237                 struct psr_context *psr_context)
3238 {
3239         struct dc *dc;
3240         struct dmcu *dmcu;
3241         struct dmub_psr *psr;
3242         int i;
3243         unsigned int panel_inst;
3244         /* updateSinkPsrDpcdConfig*/
3245         union dpcd_psr_configuration psr_configuration;
3246         union dpcd_sink_active_vtotal_control_mode vtotal_control = {0};
3247
3248         psr_context->controllerId = CONTROLLER_ID_UNDEFINED;
3249
3250         if (!link)
3251                 return false;
3252
3253         dc = link->ctx->dc;
3254         dmcu = dc->res_pool->dmcu;
3255         psr = dc->res_pool->psr;
3256
3257         if (!dmcu && !psr)
3258                 return false;
3259
3260         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
3261                 return false;
3262
3263
3264         memset(&psr_configuration, 0, sizeof(psr_configuration));
3265
3266         psr_configuration.bits.ENABLE                    = 1;
3267         psr_configuration.bits.CRC_VERIFICATION          = 1;
3268         psr_configuration.bits.FRAME_CAPTURE_INDICATION  =
3269                         psr_config->psr_frame_capture_indication_req;
3270
3271         /* Check for PSR v2*/
3272         if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) {
3273                 /* For PSR v2 selective update.
3274                  * Indicates whether sink should start capturing
3275                  * immediately following active scan line,
3276                  * or starting with the 2nd active scan line.
3277                  */
3278                 psr_configuration.bits.LINE_CAPTURE_INDICATION = 0;
3279                 /*For PSR v2, determines whether Sink should generate
3280                  * IRQ_HPD when CRC mismatch is detected.
3281                  */
3282                 psr_configuration.bits.IRQ_HPD_WITH_CRC_ERROR    = 1;
3283                 /* For PSR v2, set the bit when the Source device will
3284                  * be enabling PSR2 operation.
3285                  */
3286                 psr_configuration.bits.ENABLE_PSR2    = 1;
3287                 /* For PSR v2, the Sink device must be able to receive
3288                  * SU region updates early in the frame time.
3289                  */
3290                 psr_configuration.bits.EARLY_TRANSPORT_ENABLE    = 1;
3291         }
3292
3293         dm_helpers_dp_write_dpcd(
3294                 link->ctx,
3295                 link,
3296                 368,
3297                 &psr_configuration.raw,
3298                 sizeof(psr_configuration.raw));
3299
3300         if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) {
3301                 dc_power_alpm_dpcd_enable(link, true);
3302                 psr_context->su_granularity_required =
3303                         psr_config->su_granularity_required;
3304                 psr_context->su_y_granularity =
3305                         psr_config->su_y_granularity;
3306                 psr_context->line_time_in_us =
3307                         psr_config->line_time_in_us;
3308
3309                 if (link->psr_settings.psr_vtotal_control_support) {
3310                         psr_context->rate_control_caps = psr_config->rate_control_caps;
3311                         vtotal_control.bits.ENABLE = true;
3312                         core_link_write_dpcd(link, DP_SINK_PSR_ACTIVE_VTOTAL_CONTROL_MODE,
3313                                                         &vtotal_control.raw, sizeof(vtotal_control.raw));
3314                 }
3315         }
3316
3317         psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
3318         psr_context->transmitterId = link->link_enc->transmitter;
3319         psr_context->engineId = link->link_enc->preferred_engine;
3320
3321         for (i = 0; i < MAX_PIPES; i++) {
3322                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
3323                                 == stream) {
3324                         /* dmcu -1 for all controller id values,
3325                          * therefore +1 here
3326                          */
3327                         psr_context->controllerId =
3328                                 dc->current_state->res_ctx.
3329                                 pipe_ctx[i].stream_res.tg->inst + 1;
3330                         break;
3331                 }
3332         }
3333
3334         /* Hardcoded for now.  Can be Pcie or Uniphy (or Unknown)*/
3335         psr_context->phyType = PHY_TYPE_UNIPHY;
3336         /*PhyId is associated with the transmitter id*/
3337         psr_context->smuPhyId =
3338                 transmitter_to_phy_id(link->link_enc->transmitter);
3339
3340         psr_context->crtcTimingVerticalTotal = stream->timing.v_total;
3341         psr_context->vsync_rate_hz = div64_u64(div64_u64((stream->
3342                                         timing.pix_clk_100hz * 100),
3343                                         stream->timing.v_total),
3344                                         stream->timing.h_total);
3345
3346         psr_context->psrSupportedDisplayConfig = true;
3347         psr_context->psrExitLinkTrainingRequired =
3348                 psr_config->psr_exit_link_training_required;
3349         psr_context->sdpTransmitLineNumDeadline =
3350                 psr_config->psr_sdp_transmit_line_num_deadline;
3351         psr_context->psrFrameCaptureIndicationReq =
3352                 psr_config->psr_frame_capture_indication_req;
3353
3354         psr_context->skipPsrWaitForPllLock = 0; /* only = 1 in KV */
3355
3356         psr_context->numberOfControllers =
3357                         link->dc->res_pool->timing_generator_count;
3358
3359         psr_context->rfb_update_auto_en = true;
3360
3361         /* 2 frames before enter PSR. */
3362         psr_context->timehyst_frames = 2;
3363         /* half a frame
3364          * (units in 100 lines, i.e. a value of 1 represents 100 lines)
3365          */
3366         psr_context->hyst_lines = stream->timing.v_total / 2 / 100;
3367         psr_context->aux_repeats = 10;
3368
3369         psr_context->psr_level.u32all = 0;
3370
3371         /*skip power down the single pipe since it blocks the cstate*/
3372 #if defined(CONFIG_DRM_AMD_DC_DCN)
3373         if (link->ctx->asic_id.chip_family >= FAMILY_RV) {
3374                 switch(link->ctx->asic_id.chip_family) {
3375                 case FAMILY_YELLOW_CARP:
3376                 case AMDGPU_FAMILY_GC_10_3_6:
3377                 case AMDGPU_FAMILY_GC_11_0_1:
3378                         if(!dc->debug.disable_z10)
3379                                 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = false;
3380                         break;
3381                 default:
3382                         psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
3383                         break;
3384                 }
3385         }
3386 #else
3387         if (link->ctx->asic_id.chip_family >= FAMILY_RV)
3388                 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
3389 #endif
3390
3391         /* SMU will perform additional powerdown sequence.
3392          * For unsupported ASICs, set psr_level flag to skip PSR
3393          *  static screen notification to SMU.
3394          *  (Always set for DAL2, did not check ASIC)
3395          */
3396         psr_context->allow_smu_optimizations = psr_config->allow_smu_optimizations;
3397         psr_context->allow_multi_disp_optimizations = psr_config->allow_multi_disp_optimizations;
3398
3399         /* Complete PSR entry before aborting to prevent intermittent
3400          * freezes on certain eDPs
3401          */
3402         psr_context->psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1;
3403
3404         /* enable ALPM */
3405         psr_context->psr_level.bits.DISABLE_ALPM = 0;
3406         psr_context->psr_level.bits.ALPM_DEFAULT_PD_MODE = 1;
3407
3408         /* Controls additional delay after remote frame capture before
3409          * continuing power down, default = 0
3410          */
3411         psr_context->frame_delay = 0;
3412
3413         if (psr) {
3414                 link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr,
3415                         link, psr_context, panel_inst);
3416                 link->psr_settings.psr_power_opt = 0;
3417                 link->psr_settings.psr_allow_active = 0;
3418         }
3419         else
3420                 link->psr_settings.psr_feature_enabled = dmcu->funcs->setup_psr(dmcu, link, psr_context);
3421
3422         /* psr_enabled == 0 indicates setup_psr did not succeed, but this
3423          * should not happen since firmware should be running at this point
3424          */
3425         if (link->psr_settings.psr_feature_enabled == 0)
3426                 ASSERT(0);
3427
3428         return true;
3429
3430 }
3431
3432 void dc_link_get_psr_residency(const struct dc_link *link, uint32_t *residency)
3433 {
3434         struct dc  *dc = link->ctx->dc;
3435         struct dmub_psr *psr = dc->res_pool->psr;
3436         unsigned int panel_inst;
3437
3438         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
3439                 return;
3440
3441         /* PSR residency measurements only supported on DMCUB */
3442         if (psr != NULL && link->psr_settings.psr_feature_enabled)
3443                 psr->funcs->psr_get_residency(psr, residency, panel_inst);
3444         else
3445                 *residency = 0;
3446 }
3447
3448 bool dc_link_set_sink_vtotal_in_psr_active(const struct dc_link *link, uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su)
3449 {
3450         struct dc *dc = link->ctx->dc;
3451         struct dmub_psr *psr = dc->res_pool->psr;
3452
3453         if (psr == NULL || !link->psr_settings.psr_feature_enabled || !link->psr_settings.psr_vtotal_control_support)
3454                 return false;
3455
3456         psr->funcs->psr_set_sink_vtotal_in_psr_active(psr, psr_vtotal_idle, psr_vtotal_su);
3457
3458         return true;
3459 }
3460
3461 const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
3462 {
3463         return &link->link_status;
3464 }
3465
3466 void core_link_resume(struct dc_link *link)
3467 {
3468         if (link->connector_signal != SIGNAL_TYPE_VIRTUAL)
3469                 program_hpd_filter(link);
3470 }
3471
3472 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
3473 {
3474         struct fixed31_32 mbytes_per_sec;
3475         uint32_t link_rate_in_mbytes_per_sec = dc_link_bandwidth_kbps(stream->link,
3476                         &stream->link->cur_link_settings);
3477         link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */
3478
3479         mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec);
3480
3481         return dc_fixpt_div_int(mbytes_per_sec, 54);
3482 }
3483
3484 static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps)
3485 {
3486         struct fixed31_32 peak_kbps;
3487         uint32_t numerator = 0;
3488         uint32_t denominator = 1;
3489
3490         /*
3491          * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
3492          * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
3493          * common multiplier to render an integer PBN for all link rate/lane
3494          * counts combinations
3495          * calculate
3496          * peak_kbps *= (1006/1000)
3497          * peak_kbps *= (64/54)
3498          * peak_kbps *= 8    convert to bytes
3499          */
3500
3501         numerator = 64 * PEAK_FACTOR_X1000;
3502         denominator = 54 * 8 * 1000 * 1000;
3503         kbps *= numerator;
3504         peak_kbps = dc_fixpt_from_fraction(kbps, denominator);
3505
3506         return peak_kbps;
3507 }
3508
3509 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
3510 {
3511         uint64_t kbps;
3512
3513         kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing);
3514         return get_pbn_from_bw_in_kbps(kbps);
3515 }
3516
3517 static void update_mst_stream_alloc_table(
3518         struct dc_link *link,
3519         struct stream_encoder *stream_enc,
3520         struct hpo_dp_stream_encoder *hpo_dp_stream_enc, // TODO: Rename stream_enc to dio_stream_enc?
3521         const struct dc_dp_mst_stream_allocation_table *proposed_table)
3522 {
3523         struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = { 0 };
3524         struct link_mst_stream_allocation *dc_alloc;
3525
3526         int i;
3527         int j;
3528
3529         /* if DRM proposed_table has more than one new payload */
3530         ASSERT(proposed_table->stream_count -
3531                         link->mst_stream_alloc_table.stream_count < 2);
3532
3533         /* copy proposed_table to link, add stream encoder */
3534         for (i = 0; i < proposed_table->stream_count; i++) {
3535
3536                 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) {
3537                         dc_alloc =
3538                         &link->mst_stream_alloc_table.stream_allocations[j];
3539
3540                         if (dc_alloc->vcp_id ==
3541                                 proposed_table->stream_allocations[i].vcp_id) {
3542
3543                                 work_table[i] = *dc_alloc;
3544                                 work_table[i].slot_count = proposed_table->stream_allocations[i].slot_count;
3545                                 break; /* exit j loop */
3546                         }
3547                 }
3548
3549                 /* new vcp_id */
3550                 if (j == link->mst_stream_alloc_table.stream_count) {
3551                         work_table[i].vcp_id =
3552                                 proposed_table->stream_allocations[i].vcp_id;
3553                         work_table[i].slot_count =
3554                                 proposed_table->stream_allocations[i].slot_count;
3555                         work_table[i].stream_enc = stream_enc;
3556                         work_table[i].hpo_dp_stream_enc = hpo_dp_stream_enc;
3557                 }
3558         }
3559
3560         /* update link->mst_stream_alloc_table with work_table */
3561         link->mst_stream_alloc_table.stream_count =
3562                         proposed_table->stream_count;
3563         for (i = 0; i < MAX_CONTROLLER_NUM; i++)
3564                 link->mst_stream_alloc_table.stream_allocations[i] =
3565                                 work_table[i];
3566 }
3567
3568 static void remove_stream_from_alloc_table(
3569                 struct dc_link *link,
3570                 struct stream_encoder *dio_stream_enc,
3571                 struct hpo_dp_stream_encoder *hpo_dp_stream_enc)
3572 {
3573         int i = 0;
3574         struct link_mst_stream_allocation_table *table =
3575                         &link->mst_stream_alloc_table;
3576
3577         if (hpo_dp_stream_enc) {
3578                 for (; i < table->stream_count; i++)
3579                         if (hpo_dp_stream_enc == table->stream_allocations[i].hpo_dp_stream_enc)
3580                                 break;
3581         } else {
3582                 for (; i < table->stream_count; i++)
3583                         if (dio_stream_enc == table->stream_allocations[i].stream_enc)
3584                                 break;
3585         }
3586
3587         if (i < table->stream_count) {
3588                 i++;
3589                 for (; i < table->stream_count; i++)
3590                         table->stream_allocations[i-1] = table->stream_allocations[i];
3591                 memset(&table->stream_allocations[table->stream_count-1], 0,
3592                                 sizeof(struct link_mst_stream_allocation));
3593                 table->stream_count--;
3594         }
3595 }
3596
3597 static void dc_log_vcp_x_y(const struct dc_link *link, struct fixed31_32 avg_time_slots_per_mtp)
3598 {
3599         const uint32_t VCP_Y_PRECISION = 1000;
3600         uint64_t vcp_x, vcp_y;
3601
3602         // Add 0.5*(1/VCP_Y_PRECISION) to round up to decimal precision
3603         avg_time_slots_per_mtp = dc_fixpt_add(
3604                         avg_time_slots_per_mtp, dc_fixpt_from_fraction(1, 2 * VCP_Y_PRECISION));
3605
3606         vcp_x = dc_fixpt_floor(avg_time_slots_per_mtp);
3607         vcp_y = dc_fixpt_floor(
3608                         dc_fixpt_mul_int(
3609                                 dc_fixpt_sub_int(avg_time_slots_per_mtp, dc_fixpt_floor(avg_time_slots_per_mtp)),
3610                                 VCP_Y_PRECISION));
3611
3612         if (link->type == dc_connection_mst_branch)
3613                 DC_LOG_DP2("MST Update Payload: set_throttled_vcp_size slot X.Y for MST stream "
3614                                 "X: %lld Y: %lld/%d", vcp_x, vcp_y, VCP_Y_PRECISION);
3615         else
3616                 DC_LOG_DP2("SST Update Payload: set_throttled_vcp_size slot X.Y for SST stream "
3617                                 "X: %lld Y: %lld/%d", vcp_x, vcp_y, VCP_Y_PRECISION);
3618 }
3619
3620 /*
3621  * Payload allocation/deallocation for SST introduced in DP2.0
3622  */
3623 static enum dc_status dc_link_update_sst_payload(struct pipe_ctx *pipe_ctx,
3624                                                  bool allocate)
3625 {
3626         struct dc_stream_state *stream = pipe_ctx->stream;
3627         struct dc_link *link = stream->link;
3628         struct link_mst_stream_allocation_table proposed_table = {0};
3629         struct fixed31_32 avg_time_slots_per_mtp;
3630         const struct dc_link_settings empty_link_settings = {0};
3631         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
3632         DC_LOGGER_INIT(link->ctx->logger);
3633
3634         /* slot X.Y for SST payload deallocate */
3635         if (!allocate) {
3636                 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
3637
3638                 dc_log_vcp_x_y(link, avg_time_slots_per_mtp);
3639
3640                 if (link_hwss->ext.set_throttled_vcp_size)
3641                         link_hwss->ext.set_throttled_vcp_size(pipe_ctx,
3642                                         avg_time_slots_per_mtp);
3643                 if (link_hwss->ext.set_hblank_min_symbol_width)
3644                         link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
3645                                         &empty_link_settings,
3646                                         avg_time_slots_per_mtp);
3647         }
3648
3649         /* calculate VC payload and update branch with new payload allocation table*/
3650         if (!dpcd_write_128b_132b_sst_payload_allocation_table(
3651                         stream,
3652                         link,
3653                         &proposed_table,
3654                         allocate)) {
3655                 DC_LOG_ERROR("SST Update Payload: Failed to update "
3656                                                 "allocation table for "
3657                                                 "pipe idx: %d\n",
3658                                                 pipe_ctx->pipe_idx);
3659                 return DC_FAIL_DP_PAYLOAD_ALLOCATION;
3660         }
3661
3662         proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc;
3663
3664         ASSERT(proposed_table.stream_count == 1);
3665
3666         //TODO - DP2.0 Logging: Instead of hpo_dp_stream_enc pointer, log instance id
3667         DC_LOG_DP2("SST Update Payload: hpo_dp_stream_enc: %p      "
3668                 "vcp_id: %d      "
3669                 "slot_count: %d\n",
3670                 (void *) proposed_table.stream_allocations[0].hpo_dp_stream_enc,
3671                 proposed_table.stream_allocations[0].vcp_id,
3672                 proposed_table.stream_allocations[0].slot_count);
3673
3674         /* program DP source TX for payload */
3675         link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res,
3676                         &proposed_table);
3677
3678         /* poll for ACT handled */
3679         if (!dpcd_poll_for_allocation_change_trigger(link)) {
3680                 // Failures will result in blackscreen and errors logged
3681                 BREAK_TO_DEBUGGER();
3682         }
3683
3684         /* slot X.Y for SST payload allocate */
3685         if (allocate && dp_get_link_encoding_format(&link->cur_link_settings) ==
3686                         DP_128b_132b_ENCODING) {
3687                 avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(stream, link);
3688
3689                 dc_log_vcp_x_y(link, avg_time_slots_per_mtp);
3690
3691                 if (link_hwss->ext.set_throttled_vcp_size)
3692                         link_hwss->ext.set_throttled_vcp_size(pipe_ctx,
3693                                         avg_time_slots_per_mtp);
3694                 if (link_hwss->ext.set_hblank_min_symbol_width)
3695                         link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
3696                                         &link->cur_link_settings,
3697                                         avg_time_slots_per_mtp);
3698         }
3699
3700         /* Always return DC_OK.
3701          * If part of sequence fails, log failure(s) and show blackscreen
3702          */
3703         return DC_OK;
3704 }
3705
3706 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table
3707  * because stream_encoder is not exposed to dm
3708  */
3709 enum dc_status dc_link_allocate_mst_payload(struct pipe_ctx *pipe_ctx)
3710 {
3711         struct dc_stream_state *stream = pipe_ctx->stream;
3712         struct dc_link *link = stream->link;
3713         struct dc_dp_mst_stream_allocation_table proposed_table = {0};
3714         struct fixed31_32 avg_time_slots_per_mtp;
3715         struct fixed31_32 pbn;
3716         struct fixed31_32 pbn_per_slot;
3717         int i;
3718         enum act_return_status ret;
3719         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
3720         DC_LOGGER_INIT(link->ctx->logger);
3721
3722         /* enable_link_dp_mst already check link->enabled_stream_count
3723          * and stream is in link->stream[]. This is called during set mode,
3724          * stream_enc is available.
3725          */
3726
3727         /* get calculate VC payload for stream: stream_alloc */
3728         if (dm_helpers_dp_mst_write_payload_allocation_table(
3729                 stream->ctx,
3730                 stream,
3731                 &proposed_table,
3732                 true))
3733                 update_mst_stream_alloc_table(
3734                                         link,
3735                                         pipe_ctx->stream_res.stream_enc,
3736                                         pipe_ctx->stream_res.hpo_dp_stream_enc,
3737                                         &proposed_table);
3738         else
3739                 DC_LOG_WARNING("Failed to update"
3740                                 "MST allocation table for"
3741                                 "pipe idx:%d\n",
3742                                 pipe_ctx->pipe_idx);
3743
3744         DC_LOG_MST("%s  "
3745                         "stream_count: %d: \n ",
3746                         __func__,
3747                         link->mst_stream_alloc_table.stream_count);
3748
3749         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3750                 DC_LOG_MST("stream_enc[%d]: %p      "
3751                 "stream[%d].hpo_dp_stream_enc: %p      "
3752                 "stream[%d].vcp_id: %d      "
3753                 "stream[%d].slot_count: %d\n",
3754                 i,
3755                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3756                 i,
3757                 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc,
3758                 i,
3759                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3760                 i,
3761                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3762         }
3763
3764         ASSERT(proposed_table.stream_count > 0);
3765
3766         /* program DP source TX for payload */
3767         if (link_hwss->ext.update_stream_allocation_table == NULL ||
3768                         dp_get_link_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) {
3769                 DC_LOG_ERROR("Failure: unknown encoding format\n");
3770                 return DC_ERROR_UNEXPECTED;
3771         }
3772
3773         link_hwss->ext.update_stream_allocation_table(link,
3774                         &pipe_ctx->link_res,
3775                         &link->mst_stream_alloc_table);
3776
3777         /* send down message */
3778         ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3779                         stream->ctx,
3780                         stream);
3781
3782         if (ret != ACT_LINK_LOST) {
3783                 dm_helpers_dp_mst_send_payload_allocation(
3784                                 stream->ctx,
3785                                 stream,
3786                                 true);
3787         }
3788
3789         /* slot X.Y for only current stream */
3790         pbn_per_slot = get_pbn_per_slot(stream);
3791         if (pbn_per_slot.value == 0) {
3792                 DC_LOG_ERROR("Failure: pbn_per_slot==0 not allowed. Cannot continue, returning DC_UNSUPPORTED_VALUE.\n");
3793                 return DC_UNSUPPORTED_VALUE;
3794         }
3795         pbn = get_pbn_from_timing(pipe_ctx);
3796         avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
3797
3798         dc_log_vcp_x_y(link, avg_time_slots_per_mtp);
3799
3800         if (link_hwss->ext.set_throttled_vcp_size)
3801                 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);
3802         if (link_hwss->ext.set_hblank_min_symbol_width)
3803                 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
3804                                 &link->cur_link_settings,
3805                                 avg_time_slots_per_mtp);
3806
3807         return DC_OK;
3808
3809 }
3810
3811 enum dc_status dc_link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps)
3812 {
3813         struct dc_stream_state *stream = pipe_ctx->stream;
3814         struct dc_link *link = stream->link;
3815         struct fixed31_32 avg_time_slots_per_mtp;
3816         struct fixed31_32 pbn;
3817         struct fixed31_32 pbn_per_slot;
3818         struct dc_dp_mst_stream_allocation_table proposed_table = {0};
3819         uint8_t i;
3820         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
3821         DC_LOGGER_INIT(link->ctx->logger);
3822
3823         /* decrease throttled vcp size */
3824         pbn_per_slot = get_pbn_per_slot(stream);
3825         pbn = get_pbn_from_bw_in_kbps(bw_in_kbps);
3826         avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
3827
3828         if (link_hwss->ext.set_throttled_vcp_size)
3829                 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);
3830         if (link_hwss->ext.set_hblank_min_symbol_width)
3831                 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
3832                                 &link->cur_link_settings,
3833                                 avg_time_slots_per_mtp);
3834
3835         /* send ALLOCATE_PAYLOAD sideband message with updated pbn */
3836         dm_helpers_dp_mst_send_payload_allocation(
3837                         stream->ctx,
3838                         stream,
3839                         true);
3840
3841         /* notify immediate branch device table update */
3842         if (dm_helpers_dp_mst_write_payload_allocation_table(
3843                         stream->ctx,
3844                         stream,
3845                         &proposed_table,
3846                         true)) {
3847                 /* update mst stream allocation table software state */
3848                 update_mst_stream_alloc_table(
3849                                 link,
3850                                 pipe_ctx->stream_res.stream_enc,
3851                                 pipe_ctx->stream_res.hpo_dp_stream_enc,
3852                                 &proposed_table);
3853         } else {
3854                 DC_LOG_WARNING("Failed to update"
3855                                 "MST allocation table for"
3856                                 "pipe idx:%d\n",
3857                                 pipe_ctx->pipe_idx);
3858         }
3859
3860         DC_LOG_MST("%s  "
3861                         "stream_count: %d: \n ",
3862                         __func__,
3863                         link->mst_stream_alloc_table.stream_count);
3864
3865         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3866                 DC_LOG_MST("stream_enc[%d]: %p      "
3867                                 "stream[%d].hpo_dp_stream_enc: %p      "
3868                                 "stream[%d].vcp_id: %d      "
3869                                 "stream[%d].slot_count: %d\n",
3870                                 i,
3871                                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3872                                 i,
3873                                 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc,
3874                                 i,
3875                                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3876                                 i,
3877                                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3878         }
3879
3880         ASSERT(proposed_table.stream_count > 0);
3881
3882         /* update mst stream allocation table hardware state */
3883         if (link_hwss->ext.update_stream_allocation_table == NULL ||
3884                         dp_get_link_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) {
3885                 DC_LOG_ERROR("Failure: unknown encoding format\n");
3886                 return DC_ERROR_UNEXPECTED;
3887         }
3888
3889         link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res,
3890                         &link->mst_stream_alloc_table);
3891
3892         /* poll for immediate branch device ACT handled */
3893         dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3894                         stream->ctx,
3895                         stream);
3896
3897         return DC_OK;
3898 }
3899
3900 enum dc_status dc_link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps)
3901 {
3902         struct dc_stream_state *stream = pipe_ctx->stream;
3903         struct dc_link *link = stream->link;
3904         struct fixed31_32 avg_time_slots_per_mtp;
3905         struct fixed31_32 pbn;
3906         struct fixed31_32 pbn_per_slot;
3907         struct dc_dp_mst_stream_allocation_table proposed_table = {0};
3908         uint8_t i;
3909         enum act_return_status ret;
3910         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
3911         DC_LOGGER_INIT(link->ctx->logger);
3912
3913         /* notify immediate branch device table update */
3914         if (dm_helpers_dp_mst_write_payload_allocation_table(
3915                                 stream->ctx,
3916                                 stream,
3917                                 &proposed_table,
3918                                 true)) {
3919                 /* update mst stream allocation table software state */
3920                 update_mst_stream_alloc_table(
3921                                 link,
3922                                 pipe_ctx->stream_res.stream_enc,
3923                                 pipe_ctx->stream_res.hpo_dp_stream_enc,
3924                                 &proposed_table);
3925         }
3926
3927         DC_LOG_MST("%s  "
3928                         "stream_count: %d: \n ",
3929                         __func__,
3930                         link->mst_stream_alloc_table.stream_count);
3931
3932         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3933                 DC_LOG_MST("stream_enc[%d]: %p      "
3934                                 "stream[%d].hpo_dp_stream_enc: %p      "
3935                                 "stream[%d].vcp_id: %d      "
3936                                 "stream[%d].slot_count: %d\n",
3937                                 i,
3938                                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3939                                 i,
3940                                 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc,
3941                                 i,
3942                                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3943                                 i,
3944                                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3945         }
3946
3947         ASSERT(proposed_table.stream_count > 0);
3948
3949         /* update mst stream allocation table hardware state */
3950         if (link_hwss->ext.update_stream_allocation_table == NULL ||
3951                         dp_get_link_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) {
3952                 DC_LOG_ERROR("Failure: unknown encoding format\n");
3953                 return DC_ERROR_UNEXPECTED;
3954         }
3955
3956         link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res,
3957                         &link->mst_stream_alloc_table);
3958
3959         /* poll for immediate branch device ACT handled */
3960         ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3961                         stream->ctx,
3962                         stream);
3963
3964         if (ret != ACT_LINK_LOST) {
3965                 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */
3966                 dm_helpers_dp_mst_send_payload_allocation(
3967                                 stream->ctx,
3968                                 stream,
3969                                 true);
3970         }
3971
3972         /* increase throttled vcp size */
3973         pbn = get_pbn_from_bw_in_kbps(bw_in_kbps);
3974         pbn_per_slot = get_pbn_per_slot(stream);
3975         avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
3976
3977         if (link_hwss->ext.set_throttled_vcp_size)
3978                 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);
3979         if (link_hwss->ext.set_hblank_min_symbol_width)
3980                 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
3981                                 &link->cur_link_settings,
3982                                 avg_time_slots_per_mtp);
3983
3984         return DC_OK;
3985 }
3986
3987 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
3988 {
3989         struct dc_stream_state *stream = pipe_ctx->stream;
3990         struct dc_link *link = stream->link;
3991         struct dc_dp_mst_stream_allocation_table proposed_table = {0};
3992         struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
3993         int i;
3994         bool mst_mode = (link->type == dc_connection_mst_branch);
3995         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
3996         const struct dc_link_settings empty_link_settings = {0};
3997         DC_LOGGER_INIT(link->ctx->logger);
3998
3999         /* deallocate_mst_payload is called before disable link. When mode or
4000          * disable/enable monitor, new stream is created which is not in link
4001          * stream[] yet. For this, payload is not allocated yet, so de-alloc
4002          * should not done. For new mode set, map_resources will get engine
4003          * for new stream, so stream_enc->id should be validated until here.
4004          */
4005
4006         /* slot X.Y */
4007         if (link_hwss->ext.set_throttled_vcp_size)
4008                 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);
4009         if (link_hwss->ext.set_hblank_min_symbol_width)
4010                 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
4011                                 &empty_link_settings,
4012                                 avg_time_slots_per_mtp);
4013
4014         if (mst_mode) {
4015                 /* when link is in mst mode, reply on mst manager to remove
4016                  * payload
4017                  */
4018                 if (dm_helpers_dp_mst_write_payload_allocation_table(
4019                                 stream->ctx,
4020                                 stream,
4021                                 &proposed_table,
4022                                 false))
4023
4024                         update_mst_stream_alloc_table(
4025                                         link,
4026                                         pipe_ctx->stream_res.stream_enc,
4027                                         pipe_ctx->stream_res.hpo_dp_stream_enc,
4028                                         &proposed_table);
4029                 else
4030                         DC_LOG_WARNING("Failed to update"
4031                                         "MST allocation table for"
4032                                         "pipe idx:%d\n",
4033                                         pipe_ctx->pipe_idx);
4034         } else {
4035                 /* when link is no longer in mst mode (mst hub unplugged),
4036                  * remove payload with default dc logic
4037                  */
4038                 remove_stream_from_alloc_table(link, pipe_ctx->stream_res.stream_enc,
4039                                 pipe_ctx->stream_res.hpo_dp_stream_enc);
4040         }
4041
4042         DC_LOG_MST("%s"
4043                         "stream_count: %d: ",
4044                         __func__,
4045                         link->mst_stream_alloc_table.stream_count);
4046
4047         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
4048                 DC_LOG_MST("stream_enc[%d]: %p      "
4049                 "stream[%d].hpo_dp_stream_enc: %p      "
4050                 "stream[%d].vcp_id: %d      "
4051                 "stream[%d].slot_count: %d\n",
4052                 i,
4053                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
4054                 i,
4055                 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc,
4056                 i,
4057                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
4058                 i,
4059                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
4060         }
4061
4062         /* update mst stream allocation table hardware state */
4063         if (link_hwss->ext.update_stream_allocation_table == NULL ||
4064                         dp_get_link_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) {
4065                 DC_LOG_DEBUG("Unknown encoding format\n");
4066                 return DC_ERROR_UNEXPECTED;
4067         }
4068
4069         link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res,
4070                         &link->mst_stream_alloc_table);
4071
4072         if (mst_mode) {
4073                 dm_helpers_dp_mst_poll_for_allocation_change_trigger(
4074                         stream->ctx,
4075                         stream);
4076
4077                 dm_helpers_dp_mst_send_payload_allocation(
4078                         stream->ctx,
4079                         stream,
4080                         false);
4081         }
4082
4083         return DC_OK;
4084 }
4085
4086
4087 #if defined(CONFIG_DRM_AMD_DC_HDCP)
4088 static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off)
4089 {
4090         struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp;
4091         struct link_encoder *link_enc = NULL;
4092         struct cp_psp_stream_config config = {0};
4093         enum dp_panel_mode panel_mode =
4094                         dp_get_panel_mode(pipe_ctx->stream->link);
4095
4096         if (cp_psp == NULL || cp_psp->funcs.update_stream_config == NULL)
4097                 return;
4098
4099         link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link);
4100         ASSERT(link_enc);
4101         if (link_enc == NULL)
4102                 return;
4103
4104         /* otg instance */
4105         config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst;
4106
4107         /* dig front end */
4108         config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst;
4109
4110         /* stream encoder index */
4111         config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA;
4112         if (is_dp_128b_132b_signal(pipe_ctx))
4113                 config.stream_enc_idx =
4114                                 pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0;
4115
4116         /* dig back end */
4117         config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst;
4118
4119         /* link encoder index */
4120         config.link_enc_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A;
4121         if (is_dp_128b_132b_signal(pipe_ctx))
4122                 config.link_enc_idx = pipe_ctx->link_res.hpo_dp_link_enc->inst;
4123
4124         /* dio output index is dpia index for DPIA endpoint & dcio index by default */
4125         if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
4126                 config.dio_output_idx = pipe_ctx->stream->link->link_id.enum_id - ENUM_ID_1;
4127         else
4128                 config.dio_output_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A;
4129
4130
4131         /* phy index */
4132         config.phy_idx = resource_transmitter_to_phy_idx(
4133                         pipe_ctx->stream->link->dc, link_enc->transmitter);
4134         if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
4135                 /* USB4 DPIA doesn't use PHY in our soc, initialize it to 0 */
4136                 config.phy_idx = 0;
4137
4138         /* stream properties */
4139         config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP) ? 1 : 0;
4140         config.mst_enabled = (pipe_ctx->stream->signal ==
4141                         SIGNAL_TYPE_DISPLAY_PORT_MST) ? 1 : 0;
4142         config.dp2_enabled = is_dp_128b_132b_signal(pipe_ctx) ? 1 : 0;
4143         config.usb4_enabled = (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ?
4144                         1 : 0;
4145         config.dpms_off = dpms_off;
4146
4147         /* dm stream context */
4148         config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context;
4149
4150         cp_psp->funcs.update_stream_config(cp_psp->handle, &config);
4151 }
4152 #endif
4153
4154 static void fpga_dp_hpo_enable_link_and_stream(struct dc_state *state, struct pipe_ctx *pipe_ctx)
4155 {
4156         struct dc *dc = pipe_ctx->stream->ctx->dc;
4157         struct dc_stream_state *stream = pipe_ctx->stream;
4158         struct link_mst_stream_allocation_table proposed_table = {0};
4159         struct fixed31_32 avg_time_slots_per_mtp;
4160         uint8_t req_slot_count = 0;
4161         uint8_t vc_id = 1; /// VC ID always 1 for SST
4162         struct dc_link_settings link_settings = pipe_ctx->link_config.dp_link_settings;
4163         const struct link_hwss *link_hwss = get_link_hwss(stream->link, &pipe_ctx->link_res);
4164         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
4165
4166         stream->link->cur_link_settings = link_settings;
4167
4168         if (link_hwss->ext.enable_dp_link_output)
4169                 link_hwss->ext.enable_dp_link_output(stream->link, &pipe_ctx->link_res,
4170                                 stream->signal, pipe_ctx->clock_source->id,
4171                                 &link_settings);
4172
4173 #ifdef DIAGS_BUILD
4174         /* Workaround for FPGA HPO capture DP link data:
4175          * HPO capture will set link to active mode
4176          * This workaround is required to get a capture from start of frame
4177          */
4178         if (!dc->debug.fpga_hpo_capture_en) {
4179                 struct encoder_set_dp_phy_pattern_param params = {0};
4180                 params.dp_phy_pattern = DP_TEST_PATTERN_VIDEO_MODE;
4181
4182                 /* Set link active */
4183                 stream->link->hpo_dp_link_enc->funcs->set_link_test_pattern(
4184                                 stream->link->hpo_dp_link_enc,
4185                                 &params);
4186         }
4187 #endif
4188
4189         /* Enable DP_STREAM_ENC */
4190         dc->hwss.enable_stream(pipe_ctx);
4191
4192         /* Set DPS PPS SDP (AKA "info frames") */
4193         if (pipe_ctx->stream->timing.flags.DSC) {
4194                 dp_set_dsc_pps_sdp(pipe_ctx, true, true);
4195         }
4196
4197         /* Allocate Payload */
4198         if ((stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) && (state->stream_count > 1)) {
4199                 // MST case
4200                 uint8_t i;
4201
4202                 proposed_table.stream_count = state->stream_count;
4203                 for (i = 0; i < state->stream_count; i++) {
4204                         avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(state->streams[i], state->streams[i]->link);
4205                         req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp);
4206                         proposed_table.stream_allocations[i].slot_count = req_slot_count;
4207                         proposed_table.stream_allocations[i].vcp_id = i+1;
4208                         /* NOTE: This makes assumption that pipe_ctx index is same as stream index */
4209                         proposed_table.stream_allocations[i].hpo_dp_stream_enc = state->res_ctx.pipe_ctx[i].stream_res.hpo_dp_stream_enc;
4210                 }
4211         } else {
4212                 // SST case
4213                 avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(stream, stream->link);
4214                 req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp);
4215                 proposed_table.stream_count = 1; /// Always 1 stream for SST
4216                 proposed_table.stream_allocations[0].slot_count = req_slot_count;
4217                 proposed_table.stream_allocations[0].vcp_id = vc_id;
4218                 proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc;
4219         }
4220
4221         link_hwss->ext.update_stream_allocation_table(stream->link,
4222                         &pipe_ctx->link_res,
4223                         &proposed_table);
4224
4225         if (link_hwss->ext.set_throttled_vcp_size)
4226                 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);
4227
4228         dc->hwss.unblank_stream(pipe_ctx, &stream->link->cur_link_settings);
4229 }
4230
4231 void core_link_enable_stream(
4232                 struct dc_state *state,
4233                 struct pipe_ctx *pipe_ctx)
4234 {
4235         struct dc *dc = pipe_ctx->stream->ctx->dc;
4236         struct dc_stream_state *stream = pipe_ctx->stream;
4237         struct dc_link *link = stream->sink->link;
4238         enum dc_status status;
4239         struct link_encoder *link_enc;
4240         enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO;
4241         struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg;
4242         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
4243
4244         if (is_dp_128b_132b_signal(pipe_ctx))
4245                 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg;
4246
4247         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
4248
4249         if (pipe_ctx->stream->sink) {
4250                 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
4251                         pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) {
4252                         DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__,
4253                         pipe_ctx->stream->sink->edid_caps.display_name,
4254                         pipe_ctx->stream->signal);
4255                 }
4256         }
4257
4258         if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
4259                         dc_is_virtual_signal(pipe_ctx->stream->signal))
4260                 return;
4261
4262         link_enc = link_enc_cfg_get_link_enc(link);
4263         ASSERT(link_enc);
4264
4265         if (!dc_is_virtual_signal(pipe_ctx->stream->signal)
4266                         && !is_dp_128b_132b_signal(pipe_ctx)) {
4267                 if (link_enc)
4268                         link_enc->funcs->setup(
4269                                 link_enc,
4270                                 pipe_ctx->stream->signal);
4271         }
4272
4273         pipe_ctx->stream->link->link_state_valid = true;
4274
4275         if (pipe_ctx->stream_res.tg->funcs->set_out_mux) {
4276                 if (is_dp_128b_132b_signal(pipe_ctx))
4277                         otg_out_dest = OUT_MUX_HPO_DP;
4278                 else
4279                         otg_out_dest = OUT_MUX_DIO;
4280                 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest);
4281         }
4282
4283         link_hwss->setup_stream_attribute(pipe_ctx);
4284
4285         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
4286                 bool apply_edp_fast_boot_optimization =
4287                         pipe_ctx->stream->apply_edp_fast_boot_optimization;
4288
4289                 pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
4290
4291                 // Enable VPG before building infoframe
4292                 if (vpg && vpg->funcs->vpg_poweron)
4293                         vpg->funcs->vpg_poweron(vpg);
4294
4295                 resource_build_info_frame(pipe_ctx);
4296                 dc->hwss.update_info_frame(pipe_ctx);
4297
4298                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
4299                         dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME);
4300
4301                 /* Do not touch link on seamless boot optimization. */
4302                 if (pipe_ctx->stream->apply_seamless_boot_optimization) {
4303                         pipe_ctx->stream->dpms_off = false;
4304
4305                         /* Still enable stream features & audio on seamless boot for DP external displays */
4306                         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) {
4307                                 enable_stream_features(pipe_ctx);
4308                                 if (pipe_ctx->stream_res.audio != NULL) {
4309                                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
4310                                         dc->hwss.enable_audio_stream(pipe_ctx);
4311                                 }
4312                         }
4313
4314 #if defined(CONFIG_DRM_AMD_DC_HDCP)
4315                         update_psp_stream_config(pipe_ctx, false);
4316 #endif
4317                         return;
4318                 }
4319
4320                 /* eDP lit up by bios already, no need to enable again. */
4321                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
4322                                         apply_edp_fast_boot_optimization &&
4323                                         !pipe_ctx->stream->timing.flags.DSC &&
4324                                         !pipe_ctx->next_odm_pipe) {
4325                         pipe_ctx->stream->dpms_off = false;
4326 #if defined(CONFIG_DRM_AMD_DC_HDCP)
4327                         update_psp_stream_config(pipe_ctx, false);
4328 #endif
4329                         return;
4330                 }
4331
4332                 if (pipe_ctx->stream->dpms_off)
4333                         return;
4334
4335                 /* Have to setup DSC before DIG FE and BE are connected (which happens before the
4336                  * link training). This is to make sure the bandwidth sent to DIG BE won't be
4337                  * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag
4338                  * will be automatically set at a later time when the video is enabled
4339                  * (DP_VID_STREAM_EN = 1).
4340                  */
4341                 if (pipe_ctx->stream->timing.flags.DSC) {
4342                         if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
4343                                 dc_is_virtual_signal(pipe_ctx->stream->signal))
4344                         dp_set_dsc_enable(pipe_ctx, true);
4345
4346                 }
4347
4348                 status = enable_link(state, pipe_ctx);
4349
4350                 if (status != DC_OK) {
4351                         DC_LOG_WARNING("enabling link %u failed: %d\n",
4352                         pipe_ctx->stream->link->link_index,
4353                         status);
4354
4355                         /* Abort stream enable *unless* the failure was due to
4356                          * DP link training - some DP monitors will recover and
4357                          * show the stream anyway. But MST displays can't proceed
4358                          * without link training.
4359                          */
4360                         if (status != DC_FAIL_DP_LINK_TRAINING ||
4361                                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
4362                                 if (false == stream->link->link_status.link_active)
4363                                         disable_link(stream->link, &pipe_ctx->link_res,
4364                                                         pipe_ctx->stream->signal);
4365                                 BREAK_TO_DEBUGGER();
4366                                 return;
4367                         }
4368                 }
4369
4370                 /* turn off otg test pattern if enable */
4371                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
4372                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4373                                         CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4374                                         COLOR_DEPTH_UNDEFINED);
4375
4376                 /* This second call is needed to reconfigure the DIG
4377                  * as a workaround for the incorrect value being applied
4378                  * from transmitter control.
4379                  */
4380                 if (!(dc_is_virtual_signal(pipe_ctx->stream->signal) ||
4381                                 is_dp_128b_132b_signal(pipe_ctx)))
4382                         if (link_enc)
4383                                 link_enc->funcs->setup(
4384                                         link_enc,
4385                                         pipe_ctx->stream->signal);
4386
4387                 dc->hwss.enable_stream(pipe_ctx);
4388
4389                 /* Set DPS PPS SDP (AKA "info frames") */
4390                 if (pipe_ctx->stream->timing.flags.DSC) {
4391                         if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
4392                                         dc_is_virtual_signal(pipe_ctx->stream->signal)) {
4393                                 dp_set_dsc_on_rx(pipe_ctx, true);
4394                                 dp_set_dsc_pps_sdp(pipe_ctx, true, true);
4395                         }
4396                 }
4397
4398                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
4399                         dc_link_allocate_mst_payload(pipe_ctx);
4400                 else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
4401                                 is_dp_128b_132b_signal(pipe_ctx))
4402                         dc_link_update_sst_payload(pipe_ctx, true);
4403
4404                 dc->hwss.unblank_stream(pipe_ctx,
4405                         &pipe_ctx->stream->link->cur_link_settings);
4406
4407                 if (stream->sink_patches.delay_ignore_msa > 0)
4408                         msleep(stream->sink_patches.delay_ignore_msa);
4409
4410                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
4411                         enable_stream_features(pipe_ctx);
4412 #if defined(CONFIG_DRM_AMD_DC_HDCP)
4413                 update_psp_stream_config(pipe_ctx, false);
4414 #endif
4415
4416                 dc->hwss.enable_audio_stream(pipe_ctx);
4417
4418         } else { // if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
4419                 if (is_dp_128b_132b_signal(pipe_ctx))
4420                         fpga_dp_hpo_enable_link_and_stream(state, pipe_ctx);
4421                 if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
4422                                 dc_is_virtual_signal(pipe_ctx->stream->signal))
4423                         dp_set_dsc_enable(pipe_ctx, true);
4424         }
4425
4426         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
4427                 core_link_set_avmute(pipe_ctx, false);
4428         }
4429 }
4430
4431 void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
4432 {
4433         struct dc  *dc = pipe_ctx->stream->ctx->dc;
4434         struct dc_stream_state *stream = pipe_ctx->stream;
4435         struct dc_link *link = stream->sink->link;
4436         struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg;
4437
4438         if (is_dp_128b_132b_signal(pipe_ctx))
4439                 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg;
4440
4441         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
4442
4443         if (pipe_ctx->stream->sink) {
4444                 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
4445                         pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) {
4446                         DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__,
4447                         pipe_ctx->stream->sink->edid_caps.display_name,
4448                         pipe_ctx->stream->signal);
4449                 }
4450         }
4451
4452         if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
4453                         dc_is_virtual_signal(pipe_ctx->stream->signal))
4454                 return;
4455
4456         if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) {
4457                 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
4458                         core_link_set_avmute(pipe_ctx, true);
4459         }
4460
4461         dc->hwss.disable_audio_stream(pipe_ctx);
4462
4463 #if defined(CONFIG_DRM_AMD_DC_HDCP)
4464         update_psp_stream_config(pipe_ctx, true);
4465 #endif
4466         dc->hwss.blank_stream(pipe_ctx);
4467
4468         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
4469                 deallocate_mst_payload(pipe_ctx);
4470         else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
4471                         is_dp_128b_132b_signal(pipe_ctx))
4472                 dc_link_update_sst_payload(pipe_ctx, false);
4473
4474         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
4475                 struct ext_hdmi_settings settings = {0};
4476                 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id;
4477
4478                 unsigned short masked_chip_caps = link->chip_caps &
4479                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
4480                 //Need to inform that sink is going to use legacy HDMI mode.
4481                 dal_ddc_service_write_scdc_data(
4482                         link->ddc,
4483                         165000,//vbios only handles 165Mhz.
4484                         false);
4485                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
4486                         /* DP159, Retimer settings */
4487                         if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings))
4488                                 write_i2c_retimer_setting(pipe_ctx,
4489                                                 false, false, &settings);
4490                         else
4491                                 write_i2c_default_retimer_setting(pipe_ctx,
4492                                                 false, false);
4493                 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
4494                         /* PI3EQX1204, Redriver settings */
4495                         write_i2c_redriver_setting(pipe_ctx, false);
4496                 }
4497         }
4498
4499         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
4500                         !is_dp_128b_132b_signal(pipe_ctx)) {
4501
4502                 /* In DP1.x SST mode, our encoder will go to TPS1
4503                  * when link is on but stream is off.
4504                  * Disabling link before stream will avoid exposing TPS1 pattern
4505                  * during the disable sequence as it will confuse some receivers
4506                  * state machine.
4507                  * In DP2 or MST mode, our encoder will stay video active
4508                  */
4509                 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal);
4510                 dc->hwss.disable_stream(pipe_ctx);
4511         } else {
4512                 dc->hwss.disable_stream(pipe_ctx);
4513                 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal);
4514         }
4515
4516         if (pipe_ctx->stream->timing.flags.DSC) {
4517                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
4518                         dp_set_dsc_enable(pipe_ctx, false);
4519         }
4520         if (is_dp_128b_132b_signal(pipe_ctx)) {
4521                 if (pipe_ctx->stream_res.tg->funcs->set_out_mux)
4522                         pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, OUT_MUX_DIO);
4523         }
4524
4525         if (vpg && vpg->funcs->vpg_powerdown)
4526                 vpg->funcs->vpg_powerdown(vpg);
4527 }
4528
4529 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
4530 {
4531         struct dc  *dc = pipe_ctx->stream->ctx->dc;
4532
4533         if (!dc_is_hdmi_signal(pipe_ctx->stream->signal))
4534                 return;
4535
4536         dc->hwss.set_avmute(pipe_ctx, enable);
4537 }
4538
4539 /**
4540  *  dc_link_enable_hpd_filter:
4541  *     If enable is true, programs HPD filter on associated HPD line using
4542  *     delay_on_disconnect/delay_on_connect values dependent on
4543  *     link->connector_signal
4544  *
4545  *     If enable is false, programs HPD filter on associated HPD line with no
4546  *     delays on connect or disconnect
4547  *
4548  *  @link:   pointer to the dc link
4549  *  @enable: boolean specifying whether to enable hbd
4550  */
4551 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)
4552 {
4553         struct gpio *hpd;
4554
4555         if (enable) {
4556                 link->is_hpd_filter_disabled = false;
4557                 program_hpd_filter(link);
4558         } else {
4559                 link->is_hpd_filter_disabled = true;
4560                 /* Obtain HPD handle */
4561                 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
4562
4563                 if (!hpd)
4564                         return;
4565
4566                 /* Setup HPD filtering */
4567                 if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
4568                         struct gpio_hpd_config config;
4569
4570                         config.delay_on_connect = 0;
4571                         config.delay_on_disconnect = 0;
4572
4573                         dal_irq_setup_hpd_filter(hpd, &config);
4574
4575                         dal_gpio_close(hpd);
4576                 } else {
4577                         ASSERT_CRITICAL(false);
4578                 }
4579                 /* Release HPD handle */
4580                 dal_gpio_destroy_irq(&hpd);
4581         }
4582 }
4583
4584 void dc_link_set_drive_settings(struct dc *dc,
4585                                 struct link_training_settings *lt_settings,
4586                                 const struct dc_link *link)
4587 {
4588
4589         int i;
4590         struct link_resource link_res;
4591
4592         for (i = 0; i < dc->link_count; i++)
4593                 if (dc->links[i] == link)
4594                         break;
4595
4596         if (i >= dc->link_count)
4597                 ASSERT_CRITICAL(false);
4598
4599         dc_link_get_cur_link_res(link, &link_res);
4600         dc_link_dp_set_drive_settings(dc->links[i], &link_res, lt_settings);
4601 }
4602
4603 void dc_link_set_preferred_link_settings(struct dc *dc,
4604                                          struct dc_link_settings *link_setting,
4605                                          struct dc_link *link)
4606 {
4607         int i;
4608         struct pipe_ctx *pipe;
4609         struct dc_stream_state *link_stream;
4610         struct dc_link_settings store_settings = *link_setting;
4611
4612         link->preferred_link_setting = store_settings;
4613
4614         /* Retrain with preferred link settings only relevant for
4615          * DP signal type
4616          * Check for non-DP signal or if passive dongle present
4617          */
4618         if (!dc_is_dp_signal(link->connector_signal) ||
4619                 link->dongle_max_pix_clk > 0)
4620                 return;
4621
4622         for (i = 0; i < MAX_PIPES; i++) {
4623                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
4624                 if (pipe->stream && pipe->stream->link) {
4625                         if (pipe->stream->link == link) {
4626                                 link_stream = pipe->stream;
4627                                 break;
4628                         }
4629                 }
4630         }
4631
4632         /* Stream not found */
4633         if (i == MAX_PIPES)
4634                 return;
4635
4636         /* Cannot retrain link if backend is off */
4637         if (link_stream->dpms_off)
4638                 return;
4639
4640         if (decide_link_settings(link_stream, &store_settings))
4641                 dp_retrain_link_dp_test(link, &store_settings, false);
4642 }
4643
4644 void dc_link_set_preferred_training_settings(struct dc *dc,
4645                                                  struct dc_link_settings *link_setting,
4646                                                  struct dc_link_training_overrides *lt_overrides,
4647                                                  struct dc_link *link,
4648                                                  bool skip_immediate_retrain)
4649 {
4650         if (lt_overrides != NULL)
4651                 link->preferred_training_settings = *lt_overrides;
4652         else
4653                 memset(&link->preferred_training_settings, 0, sizeof(link->preferred_training_settings));
4654
4655         if (link_setting != NULL) {
4656                 link->preferred_link_setting = *link_setting;
4657                 if (dp_get_link_encoding_format(link_setting) == DP_128b_132b_ENCODING)
4658                         /* TODO: add dc update for acquiring link res  */
4659                         skip_immediate_retrain = true;
4660         } else {
4661                 link->preferred_link_setting.lane_count = LANE_COUNT_UNKNOWN;
4662                 link->preferred_link_setting.link_rate = LINK_RATE_UNKNOWN;
4663         }
4664
4665         /* Retrain now, or wait until next stream update to apply */
4666         if (skip_immediate_retrain == false)
4667                 dc_link_set_preferred_link_settings(dc, &link->preferred_link_setting, link);
4668 }
4669
4670 void dc_link_enable_hpd(const struct dc_link *link)
4671 {
4672         dc_link_dp_enable_hpd(link);
4673 }
4674
4675 void dc_link_disable_hpd(const struct dc_link *link)
4676 {
4677         dc_link_dp_disable_hpd(link);
4678 }
4679
4680 void dc_link_set_test_pattern(struct dc_link *link,
4681                               enum dp_test_pattern test_pattern,
4682                               enum dp_test_pattern_color_space test_pattern_color_space,
4683                               const struct link_training_settings *p_link_settings,
4684                               const unsigned char *p_custom_pattern,
4685                               unsigned int cust_pattern_size)
4686 {
4687         if (link != NULL)
4688                 dc_link_dp_set_test_pattern(
4689                         link,
4690                         test_pattern,
4691                         test_pattern_color_space,
4692                         p_link_settings,
4693                         p_custom_pattern,
4694                         cust_pattern_size);
4695 }
4696
4697 uint32_t dc_link_bandwidth_kbps(
4698         const struct dc_link *link,
4699         const struct dc_link_settings *link_setting)
4700 {
4701         uint32_t total_data_bw_efficiency_x10000 = 0;
4702         uint32_t link_rate_per_lane_kbps = 0;
4703
4704         switch (dp_get_link_encoding_format(link_setting)) {
4705         case DP_8b_10b_ENCODING:
4706                 /* For 8b/10b encoding:
4707                  * link rate is defined in the unit of LINK_RATE_REF_FREQ_IN_KHZ per DP byte per lane.
4708                  * data bandwidth efficiency is 80% with additional 3% overhead if FEC is supported.
4709                  */
4710                 link_rate_per_lane_kbps = link_setting->link_rate * LINK_RATE_REF_FREQ_IN_KHZ * BITS_PER_DP_BYTE;
4711                 total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_8b_10b_x10000;
4712                 if (dc_link_should_enable_fec(link)) {
4713                         total_data_bw_efficiency_x10000 /= 100;
4714                         total_data_bw_efficiency_x10000 *= DATA_EFFICIENCY_8b_10b_FEC_EFFICIENCY_x100;
4715                 }
4716                 break;
4717         case DP_128b_132b_ENCODING:
4718                 /* For 128b/132b encoding:
4719                  * link rate is defined in the unit of 10mbps per lane.
4720                  * total data bandwidth efficiency is always 96.71%.
4721                  */
4722                 link_rate_per_lane_kbps = link_setting->link_rate * 10000;
4723                 total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_128b_132b_x10000;
4724                 break;
4725         default:
4726                 break;
4727         }
4728
4729         /* overall effective link bandwidth = link rate per lane * lane count * total data bandwidth efficiency */
4730         return link_rate_per_lane_kbps * link_setting->lane_count / 10000 * total_data_bw_efficiency_x10000;
4731 }
4732
4733 const struct dc_link_settings *dc_link_get_link_cap(
4734                 const struct dc_link *link)
4735 {
4736         if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
4737                         link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
4738                 return &link->preferred_link_setting;
4739         return &link->verified_link_cap;
4740 }
4741
4742 void dc_link_overwrite_extended_receiver_cap(
4743                 struct dc_link *link)
4744 {
4745         dp_overwrite_extended_receiver_cap(link);
4746 }
4747
4748 bool dc_link_is_fec_supported(const struct dc_link *link)
4749 {
4750         /* TODO - use asic cap instead of link_enc->features
4751          * we no longer know which link enc to use for this link before commit
4752          */
4753         struct link_encoder *link_enc = NULL;
4754
4755         link_enc = link_enc_cfg_get_link_enc(link);
4756         ASSERT(link_enc);
4757
4758         return (dc_is_dp_signal(link->connector_signal) && link_enc &&
4759                         link_enc->features.fec_supported &&
4760                         link->dpcd_caps.fec_cap.bits.FEC_CAPABLE &&
4761                         !IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment));
4762 }
4763
4764 bool dc_link_should_enable_fec(const struct dc_link *link)
4765 {
4766         bool force_disable = false;
4767
4768         if (link->fec_state == dc_link_fec_enabled)
4769                 force_disable = false;
4770         else if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT_MST &&
4771                         link->local_sink &&
4772                         link->local_sink->edid_caps.panel_patch.disable_fec)
4773                 force_disable = true;
4774         else if (link->connector_signal == SIGNAL_TYPE_EDP
4775                         && (link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.
4776                          dsc_support.DSC_SUPPORT == false
4777                                 || link->panel_config.dsc.disable_dsc_edp
4778                                 || !link->dc->caps.edp_dsc_support))
4779                 force_disable = true;
4780
4781         return !force_disable && dc_link_is_fec_supported(link);
4782 }
4783
4784 uint32_t dc_bandwidth_in_kbps_from_timing(
4785                 const struct dc_crtc_timing *timing)
4786 {
4787         uint32_t bits_per_channel = 0;
4788         uint32_t kbps;
4789
4790 #if defined(CONFIG_DRM_AMD_DC_DCN)
4791         if (timing->flags.DSC)
4792                 return dc_dsc_stream_bandwidth_in_kbps(timing,
4793                                 timing->dsc_cfg.bits_per_pixel,
4794                                 timing->dsc_cfg.num_slices_h,
4795                                 timing->dsc_cfg.is_dp);
4796 #endif /* CONFIG_DRM_AMD_DC_DCN */
4797
4798         switch (timing->display_color_depth) {
4799         case COLOR_DEPTH_666:
4800                 bits_per_channel = 6;
4801                 break;
4802         case COLOR_DEPTH_888:
4803                 bits_per_channel = 8;
4804                 break;
4805         case COLOR_DEPTH_101010:
4806                 bits_per_channel = 10;
4807                 break;
4808         case COLOR_DEPTH_121212:
4809                 bits_per_channel = 12;
4810                 break;
4811         case COLOR_DEPTH_141414:
4812                 bits_per_channel = 14;
4813                 break;
4814         case COLOR_DEPTH_161616:
4815                 bits_per_channel = 16;
4816                 break;
4817         default:
4818                 ASSERT(bits_per_channel != 0);
4819                 bits_per_channel = 8;
4820                 break;
4821         }
4822
4823         kbps = timing->pix_clk_100hz / 10;
4824         kbps *= bits_per_channel;
4825
4826         if (timing->flags.Y_ONLY != 1) {
4827                 /*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
4828                 kbps *= 3;
4829                 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
4830                         kbps /= 2;
4831                 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
4832                         kbps = kbps * 2 / 3;
4833         }
4834
4835         return kbps;
4836
4837 }
4838
4839 void dc_link_get_cur_link_res(const struct dc_link *link,
4840                 struct link_resource *link_res)
4841 {
4842         int i;
4843         struct pipe_ctx *pipe = NULL;
4844
4845         memset(link_res, 0, sizeof(*link_res));
4846
4847         for (i = 0; i < MAX_PIPES; i++) {
4848                 pipe = &link->dc->current_state->res_ctx.pipe_ctx[i];
4849                 if (pipe->stream && pipe->stream->link && pipe->top_pipe == NULL) {
4850                         if (pipe->stream->link == link) {
4851                                 *link_res = pipe->link_res;
4852                                 break;
4853                         }
4854                 }
4855         }
4856
4857 }
4858
4859 /**
4860  * dc_get_cur_link_res_map() - take a snapshot of current link resource allocation state
4861  * @dc: pointer to dc of the dm calling this
4862  * @map: a dc link resource snapshot defined internally to dc.
4863  *
4864  * DM needs to capture a snapshot of current link resource allocation mapping
4865  * and store it in its persistent storage.
4866  *
4867  * Some of the link resource is using first come first serve policy.
4868  * The allocation mapping depends on original hotplug order. This information
4869  * is lost after driver is loaded next time. The snapshot is used in order to
4870  * restore link resource to its previous state so user will get consistent
4871  * link capability allocation across reboot.
4872  *
4873  * Return: none (void function)
4874  *
4875  */
4876 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map)
4877 {
4878         struct dc_link *link;
4879         uint32_t i;
4880         uint32_t hpo_dp_recycle_map = 0;
4881
4882         *map = 0;
4883
4884         if (dc->caps.dp_hpo) {
4885                 for (i = 0; i < dc->caps.max_links; i++) {
4886                         link = dc->links[i];
4887                         if (link->link_status.link_active &&
4888                                         dp_get_link_encoding_format(&link->reported_link_cap) == DP_128b_132b_ENCODING &&
4889                                         dp_get_link_encoding_format(&link->cur_link_settings) != DP_128b_132b_ENCODING)
4890                                 /* hpo dp link encoder is considered as recycled, when RX reports 128b/132b encoding capability
4891                                  * but current link doesn't use it.
4892                                  */
4893                                 hpo_dp_recycle_map |= (1 << i);
4894                 }
4895                 *map |= (hpo_dp_recycle_map << LINK_RES_HPO_DP_REC_MAP__SHIFT);
4896         }
4897 }
4898
4899 /**
4900  * dc_restore_link_res_map() - restore link resource allocation state from a snapshot
4901  * @dc: pointer to dc of the dm calling this
4902  * @map: a dc link resource snapshot defined internally to dc.
4903  *
4904  * DM needs to call this function after initial link detection on boot and
4905  * before first commit streams to restore link resource allocation state
4906  * from previous boot session.
4907  *
4908  * Some of the link resource is using first come first serve policy.
4909  * The allocation mapping depends on original hotplug order. This information
4910  * is lost after driver is loaded next time. The snapshot is used in order to
4911  * restore link resource to its previous state so user will get consistent
4912  * link capability allocation across reboot.
4913  *
4914  * Return: none (void function)
4915  *
4916  */
4917 void dc_restore_link_res_map(const struct dc *dc, uint32_t *map)
4918 {
4919         struct dc_link *link;
4920         uint32_t i;
4921         unsigned int available_hpo_dp_count;
4922         uint32_t hpo_dp_recycle_map = (*map & LINK_RES_HPO_DP_REC_MAP__MASK)
4923                         >> LINK_RES_HPO_DP_REC_MAP__SHIFT;
4924
4925         if (dc->caps.dp_hpo) {
4926                 available_hpo_dp_count = dc->res_pool->hpo_dp_link_enc_count;
4927                 /* remove excess 128b/132b encoding support for not recycled links */
4928                 for (i = 0; i < dc->caps.max_links; i++) {
4929                         if ((hpo_dp_recycle_map & (1 << i)) == 0) {
4930                                 link = dc->links[i];
4931                                 if (link->type != dc_connection_none &&
4932                                                 dp_get_link_encoding_format(&link->verified_link_cap) == DP_128b_132b_ENCODING) {
4933                                         if (available_hpo_dp_count > 0)
4934                                                 available_hpo_dp_count--;
4935                                         else
4936                                                 /* remove 128b/132b encoding capability by limiting verified link rate to HBR3 */
4937                                                 link->verified_link_cap.link_rate = LINK_RATE_HIGH3;
4938                                 }
4939                         }
4940                 }
4941                 /* remove excess 128b/132b encoding support for recycled links */
4942                 for (i = 0; i < dc->caps.max_links; i++) {
4943                         if ((hpo_dp_recycle_map & (1 << i)) != 0) {
4944                                 link = dc->links[i];
4945                                 if (link->type != dc_connection_none &&
4946                                                 dp_get_link_encoding_format(&link->verified_link_cap) == DP_128b_132b_ENCODING) {
4947                                         if (available_hpo_dp_count > 0)
4948                                                 available_hpo_dp_count--;
4949                                         else
4950                                                 /* remove 128b/132b encoding capability by limiting verified link rate to HBR3 */
4951                                                 link->verified_link_cap.link_rate = LINK_RATE_HIGH3;
4952                                 }
4953                         }
4954                 }
4955         }
4956 }