drivers/gpu/drm/amd/display/dc/core/dc.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  */
  24
  25 #include "dm_services.h"
  26
  27 #include "dc.h"
  28
  29 #include "core_status.h"
  30 #include "core_types.h"
  31 #include "hw_sequencer.h"
  32 #include "dce/dce_hwseq.h"
  33
  34 #include "resource.h"
  35
  36 #include "gpio_service_interface.h"
  37 #include "clk_mgr.h"
  38 #include "clock_source.h"
  39 #include "dc_bios_types.h"
  40
  41 #include "bios_parser_interface.h"
  42 #include "bios/bios_parser_helper.h"
  43 #include "include/irq_service_interface.h"
  44 #include "transform.h"
  45 #include "dmcu.h"
  46 #include "dpp.h"
  47 #include "timing_generator.h"
  48 #include "abm.h"
  49 #include "virtual/virtual_link_encoder.h"
  50 #include "hubp.h"
  51
  52 #include "link_hwss.h"
  53 #include "link_encoder.h"
  54 #include "link_enc_cfg.h"
  55
  56 #include "link.h"
  57 #include "dm_helpers.h"
  58 #include "mem_input.h"
  59
  60 #include "dc_dmub_srv.h"
  61
  62 #include "dsc.h"
  63
  64 #include "vm_helper.h"
  65
  66 #include "dce/dce_i2c.h"
  67
  68 #include "dmub/dmub_srv.h"
  69
  70 #include "dce/dmub_psr.h"
  71
  72 #include "dce/dmub_hw_lock_mgr.h"
  73
  74 #include "dc_trace.h"
  75
  76 #include "hw_sequencer_private.h"
  77
  78 #include "dce/dmub_outbox.h"
  79
  80 #define CTX \
  81         dc->ctx
  82
  83 #define DC_LOGGER \
  84         dc->ctx->logger
  85
  86 static const char DC_BUILD_ID[] = "production-build";
  87
  88 /**
  89  * DOC: Overview
  90  *
  91  * DC is the OS-agnostic component of the amdgpu DC driver.
  92  *
  93  * DC maintains and validates a set of structs representing the state of the
  94  * driver and writes that state to AMD hardware
  95  *
  96  * Main DC HW structs:
  97  *
  98  * struct dc - The central struct.  One per driver.  Created on driver load,
  99  * destroyed on driver unload.
 100  *
 101  * struct dc_context - One per driver.
 102  * Used as a backpointer by most other structs in dc.
 103  *
 104  * struct dc_link - One per connector (the physical DP, HDMI, miniDP, or eDP
 105  * plugpoints).  Created on driver load, destroyed on driver unload.
 106  *
 107  * struct dc_sink - One per display.  Created on boot or hotplug.
 108  * Destroyed on shutdown or hotunplug.  A dc_link can have a local sink
 109  * (the display directly attached).  It may also have one or more remote
 110  * sinks (in the Multi-Stream Transport case)
 111  *
 112  * struct resource_pool - One per driver.  Represents the hw blocks not in the
 113  * main pipeline.  Not directly accessible by dm.
 114  *
 115  * Main dc state structs:
 116  *
 117  * These structs can be created and destroyed as needed.  There is a full set of
 118  * these structs in dc->current_state representing the currently programmed state.
 119  *
 120  * struct dc_state - The global DC state to track global state information,
 121  * such as bandwidth values.
 122  *
 123  * struct dc_stream_state - Represents the hw configuration for the pipeline from
 124  * a framebuffer to a display.  Maps one-to-one with dc_sink.
 125  *
 126  * struct dc_plane_state - Represents a framebuffer.  Each stream has at least one,
 127  * and may have more in the Multi-Plane Overlay case.
 128  *
 129  * struct resource_context - Represents the programmable state of everything in
 130  * the resource_pool.  Not directly accessible by dm.
 131  *
 132  * struct pipe_ctx - A member of struct resource_context.  Represents the
 133  * internal hardware pipeline components.  Each dc_plane_state has either
 134  * one or two (in the pipe-split case).
 135  */
 136
 137 /* Private functions */
 138
 139 static inline void elevate_update_type(enum surface_update_type *original, enum surface_update_type new)
 140 {
 141         if (new > *original)
 142                 *original = new;
 143 }
 144
 145 static void destroy_links(struct dc *dc)
 146 {
 147         uint32_t i;
 148
 149         for (i = 0; i < dc->link_count; i++) {
 150                 if (NULL != dc->links[i])
 151                         dc->link_srv->destroy_link(&dc->links[i]);
 152         }
 153 }
 154
 155 static uint32_t get_num_of_internal_disp(struct dc_link **links, uint32_t num_links)
 156 {
 157         int i;
 158         uint32_t count = 0;
 159
 160         for (i = 0; i < num_links; i++) {
 161                 if (links[i]->connector_signal == SIGNAL_TYPE_EDP ||
 162                                 links[i]->is_internal_display)
 163                         count++;
 164         }
 165
 166         return count;
 167 }
 168
 169 static int get_seamless_boot_stream_count(struct dc_state *ctx)
 170 {
 171         uint8_t i;
 172         uint8_t seamless_boot_stream_count = 0;
 173
 174         for (i = 0; i < ctx->stream_count; i++)
 175                 if (ctx->streams[i]->apply_seamless_boot_optimization)
 176                         seamless_boot_stream_count++;
 177
 178         return seamless_boot_stream_count;
 179 }
 180
 181 static bool create_links(
 182                 struct dc *dc,
 183                 uint32_t num_virtual_links)
 184 {
 185         int i;
 186         int connectors_num;
 187         struct dc_bios *bios = dc->ctx->dc_bios;
 188
 189         dc->link_count = 0;
 190
 191         connectors_num = bios->funcs->get_connectors_number(bios);
 192
 193         DC_LOG_DC("BIOS object table - number of connectors: %d", connectors_num);
 194
 195         if (connectors_num > ENUM_ID_COUNT) {
 196                 dm_error(
 197                         "DC: Number of connectors %d exceeds maximum of %d!\n",
 198                         connectors_num,
 199                         ENUM_ID_COUNT);
 200                 return false;
 201         }
 202
 203         dm_output_to_console(
 204                 "DC: %s: connectors_num: physical:%d, virtual:%d\n",
 205                 __func__,
 206                 connectors_num,
 207                 num_virtual_links);
 208
 209         for (i = 0; i < connectors_num; i++) {
 210                 struct link_init_data link_init_params = {0};
 211                 struct dc_link *link;
 212
 213                 DC_LOG_DC("BIOS object table - printing link object info for connector number: %d, link_index: %d", i, dc->link_count);
 214
 215                 link_init_params.ctx = dc->ctx;
 216                 /* next BIOS object table connector */
 217                 link_init_params.connector_index = i;
 218                 link_init_params.link_index = dc->link_count;
 219                 link_init_params.dc = dc;
 220                 link = dc->link_srv->create_link(&link_init_params);
 221
 222                 if (link) {
 223                         dc->links[dc->link_count] = link;
 224                         link->dc = dc;
 225                         ++dc->link_count;
 226                 }
 227         }
 228
 229         DC_LOG_DC("BIOS object table - end");
 230
 231         /* Create a link for each usb4 dpia port */
 232         for (i = 0; i < dc->res_pool->usb4_dpia_count; i++) {
 233                 struct link_init_data link_init_params = {0};
 234                 struct dc_link *link;
 235
 236                 link_init_params.ctx = dc->ctx;
 237                 link_init_params.connector_index = i;
 238                 link_init_params.link_index = dc->link_count;
 239                 link_init_params.dc = dc;
 240                 link_init_params.is_dpia_link = true;
 241
 242                 link = dc->link_srv->create_link(&link_init_params);
 243                 if (link) {
 244                         dc->links[dc->link_count] = link;
 245                         link->dc = dc;
 246                         ++dc->link_count;
 247                 }
 248         }
 249
 250         for (i = 0; i < num_virtual_links; i++) {
 251                 struct dc_link *link = kzalloc(sizeof(*link), GFP_KERNEL);
 252                 struct encoder_init_data enc_init = {0};
 253
 254                 if (link == NULL) {
 255                         BREAK_TO_DEBUGGER();
 256                         goto failed_alloc;
 257                 }
 258
 259                 link->link_index = dc->link_count;
 260                 dc->links[dc->link_count] = link;
 261                 dc->link_count++;
 262
 263                 link->ctx = dc->ctx;
 264                 link->dc = dc;
 265                 link->connector_signal = SIGNAL_TYPE_VIRTUAL;
 266                 link->link_id.type = OBJECT_TYPE_CONNECTOR;
 267                 link->link_id.id = CONNECTOR_ID_VIRTUAL;
 268                 link->link_id.enum_id = ENUM_ID_1;
 269                 link->link_enc = kzalloc(sizeof(*link->link_enc), GFP_KERNEL);
 270
 271                 if (!link->link_enc) {
 272                         BREAK_TO_DEBUGGER();
 273                         goto failed_alloc;
 274                 }
 275
 276                 link->link_status.dpcd_caps = &link->dpcd_caps;
 277
 278                 enc_init.ctx = dc->ctx;
 279                 enc_init.channel = CHANNEL_ID_UNKNOWN;
 280                 enc_init.hpd_source = HPD_SOURCEID_UNKNOWN;
 281                 enc_init.transmitter = TRANSMITTER_UNKNOWN;
 282                 enc_init.connector = link->link_id;
 283                 enc_init.encoder.type = OBJECT_TYPE_ENCODER;
 284                 enc_init.encoder.id = ENCODER_ID_INTERNAL_VIRTUAL;
 285                 enc_init.encoder.enum_id = ENUM_ID_1;
 286                 virtual_link_encoder_construct(link->link_enc, &enc_init);
 287         }
 288
 289         dc->caps.num_of_internal_disp = get_num_of_internal_disp(dc->links, dc->link_count);
 290
 291         return true;
 292
 293 failed_alloc:
 294         return false;
 295 }
 296
 297 /* Create additional DIG link encoder objects if fewer than the platform
 298  * supports were created during link construction. This can happen if the
 299  * number of physical connectors is less than the number of DIGs.
 300  */
 301 static bool create_link_encoders(struct dc *dc)
 302 {
 303         bool res = true;
 304         unsigned int num_usb4_dpia = dc->res_pool->res_cap->num_usb4_dpia;
 305         unsigned int num_dig_link_enc = dc->res_pool->res_cap->num_dig_link_enc;
 306         int i;
 307
 308         /* A platform without USB4 DPIA endpoints has a fixed mapping between DIG
 309          * link encoders and physical display endpoints and does not require
 310          * additional link encoder objects.
 311          */
 312         if (num_usb4_dpia == 0)
 313                 return res;
 314
 315         /* Create as many link encoder objects as the platform supports. DPIA
 316          * endpoints can be programmably mapped to any DIG.
 317          */
 318         if (num_dig_link_enc > dc->res_pool->dig_link_enc_count) {
 319                 for (i = 0; i < num_dig_link_enc; i++) {
 320                         struct link_encoder *link_enc = dc->res_pool->link_encoders[i];
 321
 322                         if (!link_enc && dc->res_pool->funcs->link_enc_create_minimal) {
 323                                 link_enc = dc->res_pool->funcs->link_enc_create_minimal(dc->ctx,
 324                                                 (enum engine_id)(ENGINE_ID_DIGA + i));
 325                                 if (link_enc) {
 326                                         dc->res_pool->link_encoders[i] = link_enc;
 327                                         dc->res_pool->dig_link_enc_count++;
 328                                 } else {
 329                                         res = false;
 330                                 }
 331                         }
 332                 }
 333         }
 334
 335         return res;
 336 }
 337
 338 /* Destroy any additional DIG link encoder objects created by
 339  * create_link_encoders().
 340  * NB: Must only be called after destroy_links().
 341  */
 342 static void destroy_link_encoders(struct dc *dc)
 343 {
 344         unsigned int num_usb4_dpia;
 345         unsigned int num_dig_link_enc;
 346         int i;
 347
 348         if (!dc->res_pool)
 349                 return;
 350
 351         num_usb4_dpia = dc->res_pool->res_cap->num_usb4_dpia;
 352         num_dig_link_enc = dc->res_pool->res_cap->num_dig_link_enc;
 353
 354         /* A platform without USB4 DPIA endpoints has a fixed mapping between DIG
 355          * link encoders and physical display endpoints and does not require
 356          * additional link encoder objects.
 357          */
 358         if (num_usb4_dpia == 0)
 359                 return;
 360
 361         for (i = 0; i < num_dig_link_enc; i++) {
 362                 struct link_encoder *link_enc = dc->res_pool->link_encoders[i];
 363
 364                 if (link_enc) {
 365                         link_enc->funcs->destroy(&link_enc);
 366                         dc->res_pool->link_encoders[i] = NULL;
 367                         dc->res_pool->dig_link_enc_count--;
 368                 }
 369         }
 370 }
 371
 372 static struct dc_perf_trace *dc_perf_trace_create(void)
 373 {
 374         return kzalloc(sizeof(struct dc_perf_trace), GFP_KERNEL);
 375 }
 376
 377 static void dc_perf_trace_destroy(struct dc_perf_trace **perf_trace)
 378 {
 379         kfree(*perf_trace);
 380         *perf_trace = NULL;
 381 }
 382
 383 /**
 384  *  dc_stream_adjust_vmin_vmax - look up pipe context & update parts of DRR
 385  *  @dc:     dc reference
 386  *  @stream: Initial dc stream state
 387  *  @adjust: Updated parameters for vertical_total_min and vertical_total_max
 388  *
 389  *  Looks up the pipe context of dc_stream_state and updates the
 390  *  vertical_total_min and vertical_total_max of the DRR, Dynamic Refresh
 391  *  Rate, which is a power-saving feature that targets reducing panel
 392  *  refresh rate while the screen is static
 393  *
 394  *  Return: %true if the pipe context is found and adjusted;
 395  *          %false if the pipe context is not found.
 396  */
 397 bool dc_stream_adjust_vmin_vmax(struct dc *dc,
 398                 struct dc_stream_state *stream,
 399                 struct dc_crtc_timing_adjust *adjust)
 400 {
 401         int i;
 402
 403         /*
 404          * Don't adjust DRR while there's bandwidth optimizations pending to
 405          * avoid conflicting with firmware updates.
 406          */
 407         if (dc->ctx->dce_version > DCE_VERSION_MAX)
 408                 if (dc->optimized_required || dc->wm_optimized_required)
 409                         return false;
 410
 411         stream->adjust.v_total_max = adjust->v_total_max;
 412         stream->adjust.v_total_mid = adjust->v_total_mid;
 413         stream->adjust.v_total_mid_frame_num = adjust->v_total_mid_frame_num;
 414         stream->adjust.v_total_min = adjust->v_total_min;
 415
 416         for (i = 0; i < MAX_PIPES; i++) {
 417                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 418
 419                 if (pipe->stream == stream && pipe->stream_res.tg) {
 420                         dc->hwss.set_drr(&pipe,
 421                                         1,
 422                                         *adjust);
 423
 424                         return true;
 425                 }
 426         }
 427         return false;
 428 }
 429
 430 /**
 431  * dc_stream_get_last_used_drr_vtotal - Looks up the pipe context of
 432  * dc_stream_state and gets the last VTOTAL used by DRR (Dynamic Refresh Rate)
 433  *
 434  * @dc: [in] dc reference
 435  * @stream: [in] Initial dc stream state
 436  * @refresh_rate: [in] new refresh_rate
 437  *
 438  * Return: %true if the pipe context is found and there is an associated
 439  *         timing_generator for the DC;
 440  *         %false if the pipe context is not found or there is no
 441  *         timing_generator for the DC.
 442  */
 443 bool dc_stream_get_last_used_drr_vtotal(struct dc *dc,
 444                 struct dc_stream_state *stream,
 445                 uint32_t *refresh_rate)
 446 {
 447         bool status = false;
 448
 449         int i = 0;
 450
 451         for (i = 0; i < MAX_PIPES; i++) {
 452                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 453
 454                 if (pipe->stream == stream && pipe->stream_res.tg) {
 455                         /* Only execute if a function pointer has been defined for
 456                          * the DC version in question
 457                          */
 458                         if (pipe->stream_res.tg->funcs->get_last_used_drr_vtotal) {
 459                                 pipe->stream_res.tg->funcs->get_last_used_drr_vtotal(pipe->stream_res.tg, refresh_rate);
 460
 461                                 status = true;
 462
 463                                 break;
 464                         }
 465                 }
 466         }
 467
 468         return status;
 469 }
 470
 471 bool dc_stream_get_crtc_position(struct dc *dc,
 472                 struct dc_stream_state **streams, int num_streams,
 473                 unsigned int *v_pos, unsigned int *nom_v_pos)
 474 {
 475         /* TODO: Support multiple streams */
 476         const struct dc_stream_state *stream = streams[0];
 477         int i;
 478         bool ret = false;
 479         struct crtc_position position;
 480
 481         for (i = 0; i < MAX_PIPES; i++) {
 482                 struct pipe_ctx *pipe =
 483                                 &dc->current_state->res_ctx.pipe_ctx[i];
 484
 485                 if (pipe->stream == stream && pipe->stream_res.stream_enc) {
 486                         dc->hwss.get_position(&pipe, 1, &position);
 487
 488                         *v_pos = position.vertical_count;
 489                         *nom_v_pos = position.nominal_vcount;
 490                         ret = true;
 491                 }
 492         }
 493         return ret;
 494 }
 495
 496 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
 497 static inline void
 498 dc_stream_forward_dmub_crc_window(struct dc_dmub_srv *dmub_srv,
 499                 struct rect *rect, struct otg_phy_mux *mux_mapping, bool is_stop)
 500 {
 501         union dmub_rb_cmd cmd = {0};
 502
 503         cmd.secure_display.roi_info.phy_id = mux_mapping->phy_output_num;
 504         cmd.secure_display.roi_info.otg_id = mux_mapping->otg_output_num;
 505
 506         if (is_stop) {
 507                 cmd.secure_display.header.type = DMUB_CMD__SECURE_DISPLAY;
 508                 cmd.secure_display.header.sub_type = DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE;
 509         } else {
 510                 cmd.secure_display.header.type = DMUB_CMD__SECURE_DISPLAY;
 511                 cmd.secure_display.header.sub_type = DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY;
 512                 cmd.secure_display.roi_info.x_start = rect->x;
 513                 cmd.secure_display.roi_info.y_start = rect->y;
 514                 cmd.secure_display.roi_info.x_end = rect->x + rect->width;
 515                 cmd.secure_display.roi_info.y_end = rect->y + rect->height;
 516         }
 517
 518         dm_execute_dmub_cmd(dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
 519 }
 520
 521 static inline void
 522 dc_stream_forward_dmcu_crc_window(struct dmcu *dmcu,
 523                 struct rect *rect, struct otg_phy_mux *mux_mapping, bool is_stop)
 524 {
 525         if (is_stop)
 526                 dmcu->funcs->stop_crc_win_update(dmcu, mux_mapping);
 527         else
 528                 dmcu->funcs->forward_crc_window(dmcu, rect, mux_mapping);
 529 }
 530
 531 bool
 532 dc_stream_forward_crc_window(struct dc_stream_state *stream,
 533                 struct rect *rect, bool is_stop)
 534 {
 535         struct dmcu *dmcu;
 536         struct dc_dmub_srv *dmub_srv;
 537         struct otg_phy_mux mux_mapping;
 538         struct pipe_ctx *pipe;
 539         int i;
 540         struct dc *dc = stream->ctx->dc;
 541
 542         for (i = 0; i < MAX_PIPES; i++) {
 543                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 544                 if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe)
 545                         break;
 546         }
 547
 548         /* Stream not found */
 549         if (i == MAX_PIPES)
 550                 return false;
 551
 552         mux_mapping.phy_output_num = stream->link->link_enc_hw_inst;
 553         mux_mapping.otg_output_num = pipe->stream_res.tg->inst;
 554
 555         dmcu = dc->res_pool->dmcu;
 556         dmub_srv = dc->ctx->dmub_srv;
 557
 558         /* forward to dmub */
 559         if (dmub_srv)
 560                 dc_stream_forward_dmub_crc_window(dmub_srv, rect, &mux_mapping, is_stop);
 561         /* forward to dmcu */
 562         else if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))
 563                 dc_stream_forward_dmcu_crc_window(dmcu, rect, &mux_mapping, is_stop);
 564         else
 565                 return false;
 566
 567         return true;
 568 }
 569 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */
 570
 571 /**
 572  * dc_stream_configure_crc() - Configure CRC capture for the given stream.
 573  * @dc: DC Object
 574  * @stream: The stream to configure CRC on.
 575  * @enable: Enable CRC if true, disable otherwise.
 576  * @crc_window: CRC window (x/y start/end) information
 577  * @continuous: Capture CRC on every frame if true. Otherwise, only capture
 578  *              once.
 579  *
 580  * By default, only CRC0 is configured, and the entire frame is used to
 581  * calculate the CRC.
 582  *
 583  * Return: %false if the stream is not found or CRC capture is not supported;
 584  *         %true if the stream has been configured.
 585  */
 586 bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,
 587                              struct crc_params *crc_window, bool enable, bool continuous)
 588 {
 589         int i;
 590         struct pipe_ctx *pipe;
 591         struct crc_params param;
 592         struct timing_generator *tg;
 593
 594         for (i = 0; i < MAX_PIPES; i++) {
 595                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 596                 if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe)
 597                         break;
 598         }
 599         /* Stream not found */
 600         if (i == MAX_PIPES)
 601                 return false;
 602
 603         /* By default, capture the full frame */
 604         param.windowa_x_start = 0;
 605         param.windowa_y_start = 0;
 606         param.windowa_x_end = pipe->stream->timing.h_addressable;
 607         param.windowa_y_end = pipe->stream->timing.v_addressable;
 608         param.windowb_x_start = 0;
 609         param.windowb_y_start = 0;
 610         param.windowb_x_end = pipe->stream->timing.h_addressable;
 611         param.windowb_y_end = pipe->stream->timing.v_addressable;
 612
 613         if (crc_window) {
 614                 param.windowa_x_start = crc_window->windowa_x_start;
 615                 param.windowa_y_start = crc_window->windowa_y_start;
 616                 param.windowa_x_end = crc_window->windowa_x_end;
 617                 param.windowa_y_end = crc_window->windowa_y_end;
 618                 param.windowb_x_start = crc_window->windowb_x_start;
 619                 param.windowb_y_start = crc_window->windowb_y_start;
 620                 param.windowb_x_end = crc_window->windowb_x_end;
 621                 param.windowb_y_end = crc_window->windowb_y_end;
 622         }
 623
 624         param.dsc_mode = pipe->stream->timing.flags.DSC ? 1:0;
 625         param.odm_mode = pipe->next_odm_pipe ? 1:0;
 626
 627         /* Default to the union of both windows */
 628         param.selection = UNION_WINDOW_A_B;
 629         param.continuous_mode = continuous;
 630         param.enable = enable;
 631
 632         tg = pipe->stream_res.tg;
 633
 634         /* Only call if supported */
 635         if (tg->funcs->configure_crc)
 636                 return tg->funcs->configure_crc(tg, &param);
 637         DC_LOG_WARNING("CRC capture not supported.");
 638         return false;
 639 }
 640
 641 /**
 642  * dc_stream_get_crc() - Get CRC values for the given stream.
 643  *
 644  * @dc: DC object.
 645  * @stream: The DC stream state of the stream to get CRCs from.
 646  * @r_cr: CRC value for the red component.
 647  * @g_y:  CRC value for the green component.
 648  * @b_cb: CRC value for the blue component.
 649  *
 650  * dc_stream_configure_crc needs to be called beforehand to enable CRCs.
 651  *
 652  * Return:
 653  * %false if stream is not found, or if CRCs are not enabled.
 654  */
 655 bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream,
 656                        uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)
 657 {
 658         int i;
 659         struct pipe_ctx *pipe;
 660         struct timing_generator *tg;
 661
 662         for (i = 0; i < MAX_PIPES; i++) {
 663                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 664                 if (pipe->stream == stream)
 665                         break;
 666         }
 667         /* Stream not found */
 668         if (i == MAX_PIPES)
 669                 return false;
 670
 671         tg = pipe->stream_res.tg;
 672
 673         if (tg->funcs->get_crc)
 674                 return tg->funcs->get_crc(tg, r_cr, g_y, b_cb);
 675         DC_LOG_WARNING("CRC capture not supported.");
 676         return false;
 677 }
 678
 679 void dc_stream_set_dyn_expansion(struct dc *dc, struct dc_stream_state *stream,
 680                 enum dc_dynamic_expansion option)
 681 {
 682         /* OPP FMT dyn expansion updates*/
 683         int i;
 684         struct pipe_ctx *pipe_ctx;
 685
 686         for (i = 0; i < MAX_PIPES; i++) {
 687                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
 688                                 == stream) {
 689                         pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 690                         pipe_ctx->stream_res.opp->dyn_expansion = option;
 691                         pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
 692                                         pipe_ctx->stream_res.opp,
 693                                         COLOR_SPACE_YCBCR601,
 694                                         stream->timing.display_color_depth,
 695                                         stream->signal);
 696                 }
 697         }
 698 }
 699
 700 void dc_stream_set_dither_option(struct dc_stream_state *stream,
 701                 enum dc_dither_option option)
 702 {
 703         struct bit_depth_reduction_params params;
 704         struct dc_link *link = stream->link;
 705         struct pipe_ctx *pipes = NULL;
 706         int i;
 707
 708         for (i = 0; i < MAX_PIPES; i++) {
 709                 if (link->dc->current_state->res_ctx.pipe_ctx[i].stream ==
 710                                 stream) {
 711                         pipes = &link->dc->current_state->res_ctx.pipe_ctx[i];
 712                         break;
 713                 }
 714         }
 715
 716         if (!pipes)
 717                 return;
 718         if (option > DITHER_OPTION_MAX)
 719                 return;
 720
 721         stream->dither_option = option;
 722
 723         memset(&params, 0, sizeof(params));
 724         resource_build_bit_depth_reduction_params(stream, &params);
 725         stream->bit_depth_params = params;
 726
 727         if (pipes->plane_res.xfm &&
 728             pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth) {
 729                 pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
 730                         pipes->plane_res.xfm,
 731                         pipes->plane_res.scl_data.lb_params.depth,
 732                         &stream->bit_depth_params);
 733         }
 734
 735         pipes->stream_res.opp->funcs->
 736                 opp_program_bit_depth_reduction(pipes->stream_res.opp, &params);
 737 }
 738
 739 bool dc_stream_set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream)
 740 {
 741         int i;
 742         bool ret = false;
 743         struct pipe_ctx *pipes;
 744
 745         for (i = 0; i < MAX_PIPES; i++) {
 746                 if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) {
 747                         pipes = &dc->current_state->res_ctx.pipe_ctx[i];
 748                         dc->hwss.program_gamut_remap(pipes);
 749                         ret = true;
 750                 }
 751         }
 752
 753         return ret;
 754 }
 755
 756 bool dc_stream_program_csc_matrix(struct dc *dc, struct dc_stream_state *stream)
 757 {
 758         int i;
 759         bool ret = false;
 760         struct pipe_ctx *pipes;
 761
 762         for (i = 0; i < MAX_PIPES; i++) {
 763                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
 764                                 == stream) {
 765
 766                         pipes = &dc->current_state->res_ctx.pipe_ctx[i];
 767                         dc->hwss.program_output_csc(dc,
 768                                         pipes,
 769                                         stream->output_color_space,
 770                                         stream->csc_color_matrix.matrix,
 771                                         pipes->stream_res.opp->inst);
 772                         ret = true;
 773                 }
 774         }
 775
 776         return ret;
 777 }
 778
 779 void dc_stream_set_static_screen_params(struct dc *dc,
 780                 struct dc_stream_state **streams,
 781                 int num_streams,
 782                 const struct dc_static_screen_params *params)
 783 {
 784         int i, j;
 785         struct pipe_ctx *pipes_affected[MAX_PIPES];
 786         int num_pipes_affected = 0;
 787
 788         for (i = 0; i < num_streams; i++) {
 789                 struct dc_stream_state *stream = streams[i];
 790
 791                 for (j = 0; j < MAX_PIPES; j++) {
 792                         if (dc->current_state->res_ctx.pipe_ctx[j].stream
 793                                         == stream) {
 794                                 pipes_affected[num_pipes_affected++] =
 795                                                 &dc->current_state->res_ctx.pipe_ctx[j];
 796                         }
 797                 }
 798         }
 799
 800         dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, params);
 801 }
 802
 803 static void dc_destruct(struct dc *dc)
 804 {
 805         // reset link encoder assignment table on destruct
 806         if (dc->res_pool && dc->res_pool->funcs->link_encs_assign)
 807                 link_enc_cfg_init(dc, dc->current_state);
 808
 809         if (dc->current_state) {
 810                 dc_release_state(dc->current_state);
 811                 dc->current_state = NULL;
 812         }
 813
 814         destroy_links(dc);
 815
 816         destroy_link_encoders(dc);
 817
 818         if (dc->clk_mgr) {
 819                 dc_destroy_clk_mgr(dc->clk_mgr);
 820                 dc->clk_mgr = NULL;
 821         }
 822
 823         dc_destroy_resource_pool(dc);
 824
 825         if (dc->link_srv)
 826                 link_destroy_link_service(&dc->link_srv);
 827
 828         if (dc->ctx->gpio_service)
 829                 dal_gpio_service_destroy(&dc->ctx->gpio_service);
 830
 831         if (dc->ctx->created_bios)
 832                 dal_bios_parser_destroy(&dc->ctx->dc_bios);
 833
 834         dc_perf_trace_destroy(&dc->ctx->perf_trace);
 835
 836         kfree(dc->ctx);
 837         dc->ctx = NULL;
 838
 839         kfree(dc->bw_vbios);
 840         dc->bw_vbios = NULL;
 841
 842         kfree(dc->bw_dceip);
 843         dc->bw_dceip = NULL;
 844
 845         kfree(dc->dcn_soc);
 846         dc->dcn_soc = NULL;
 847
 848         kfree(dc->dcn_ip);
 849         dc->dcn_ip = NULL;
 850
 851         kfree(dc->vm_helper);
 852         dc->vm_helper = NULL;
 853
 854 }
 855
 856 static bool dc_construct_ctx(struct dc *dc,
 857                 const struct dc_init_data *init_params)
 858 {
 859         struct dc_context *dc_ctx;
 860
 861         dc_ctx = kzalloc(sizeof(*dc_ctx), GFP_KERNEL);
 862         if (!dc_ctx)
 863                 return false;
 864
 865         dc_ctx->cgs_device = init_params->cgs_device;
 866         dc_ctx->driver_context = init_params->driver;
 867         dc_ctx->dc = dc;
 868         dc_ctx->asic_id = init_params->asic_id;
 869         dc_ctx->dc_sink_id_count = 0;
 870         dc_ctx->dc_stream_id_count = 0;
 871         dc_ctx->dce_environment = init_params->dce_environment;
 872         dc_ctx->dcn_reg_offsets = init_params->dcn_reg_offsets;
 873         dc_ctx->nbio_reg_offsets = init_params->nbio_reg_offsets;
 874
 875         /* Create logger */
 876
 877         dc_ctx->dce_version = resource_parse_asic_id(init_params->asic_id);
 878
 879         dc_ctx->perf_trace = dc_perf_trace_create();
 880         if (!dc_ctx->perf_trace) {
 881                 kfree(dc_ctx);
 882                 ASSERT_CRITICAL(false);
 883                 return false;
 884         }
 885
 886         dc->ctx = dc_ctx;
 887
 888         dc->link_srv = link_create_link_service();
 889         if (!dc->link_srv)
 890                 return false;
 891
 892         return true;
 893 }
 894
 895 static bool dc_construct(struct dc *dc,
 896                 const struct dc_init_data *init_params)
 897 {
 898         struct dc_context *dc_ctx;
 899         struct bw_calcs_dceip *dc_dceip;
 900         struct bw_calcs_vbios *dc_vbios;
 901         struct dcn_soc_bounding_box *dcn_soc;
 902         struct dcn_ip_params *dcn_ip;
 903
 904         dc->config = init_params->flags;
 905
 906         // Allocate memory for the vm_helper
 907         dc->vm_helper = kzalloc(sizeof(struct vm_helper), GFP_KERNEL);
 908         if (!dc->vm_helper) {
 909                 dm_error("%s: failed to create dc->vm_helper\n", __func__);
 910                 goto fail;
 911         }
 912
 913         memcpy(&dc->bb_overrides, &init_params->bb_overrides, sizeof(dc->bb_overrides));
 914
 915         dc_dceip = kzalloc(sizeof(*dc_dceip), GFP_KERNEL);
 916         if (!dc_dceip) {
 917                 dm_error("%s: failed to create dceip\n", __func__);
 918                 goto fail;
 919         }
 920
 921         dc->bw_dceip = dc_dceip;
 922
 923         dc_vbios = kzalloc(sizeof(*dc_vbios), GFP_KERNEL);
 924         if (!dc_vbios) {
 925                 dm_error("%s: failed to create vbios\n", __func__);
 926                 goto fail;
 927         }
 928
 929         dc->bw_vbios = dc_vbios;
 930         dcn_soc = kzalloc(sizeof(*dcn_soc), GFP_KERNEL);
 931         if (!dcn_soc) {
 932                 dm_error("%s: failed to create dcn_soc\n", __func__);
 933                 goto fail;
 934         }
 935
 936         dc->dcn_soc = dcn_soc;
 937
 938         dcn_ip = kzalloc(sizeof(*dcn_ip), GFP_KERNEL);
 939         if (!dcn_ip) {
 940                 dm_error("%s: failed to create dcn_ip\n", __func__);
 941                 goto fail;
 942         }
 943
 944         dc->dcn_ip = dcn_ip;
 945
 946         if (!dc_construct_ctx(dc, init_params)) {
 947                 dm_error("%s: failed to create ctx\n", __func__);
 948                 goto fail;
 949         }
 950
 951         dc_ctx = dc->ctx;
 952
 953         /* Resource should construct all asic specific resources.
 954          * This should be the only place where we need to parse the asic id
 955          */
 956         if (init_params->vbios_override)
 957                 dc_ctx->dc_bios = init_params->vbios_override;
 958         else {
 959                 /* Create BIOS parser */
 960                 struct bp_init_data bp_init_data;
 961
 962                 bp_init_data.ctx = dc_ctx;
 963                 bp_init_data.bios = init_params->asic_id.atombios_base_address;
 964
 965                 dc_ctx->dc_bios = dal_bios_parser_create(
 966                                 &bp_init_data, dc_ctx->dce_version);
 967
 968                 if (!dc_ctx->dc_bios) {
 969                         ASSERT_CRITICAL(false);
 970                         goto fail;
 971                 }
 972
 973                 dc_ctx->created_bios = true;
 974         }
 975
 976         dc->vendor_signature = init_params->vendor_signature;
 977
 978         /* Create GPIO service */
 979         dc_ctx->gpio_service = dal_gpio_service_create(
 980                         dc_ctx->dce_version,
 981                         dc_ctx->dce_environment,
 982                         dc_ctx);
 983
 984         if (!dc_ctx->gpio_service) {
 985                 ASSERT_CRITICAL(false);
 986                 goto fail;
 987         }
 988
 989         dc->res_pool = dc_create_resource_pool(dc, init_params, dc_ctx->dce_version);
 990         if (!dc->res_pool)
 991                 goto fail;
 992
 993         /* set i2c speed if not done by the respective dcnxxx__resource.c */
 994         if (dc->caps.i2c_speed_in_khz_hdcp == 0)
 995                 dc->caps.i2c_speed_in_khz_hdcp = dc->caps.i2c_speed_in_khz;
 996
 997         dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg);
 998         if (!dc->clk_mgr)
 999                 goto fail;
1000 #ifdef CONFIG_DRM_AMD_DC_FP
1001         dc->clk_mgr->force_smu_not_present = init_params->force_smu_not_present;
1002
1003         if (dc->res_pool->funcs->update_bw_bounding_box) {
1004                 DC_FP_START();
1005                 dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params);
1006                 DC_FP_END();
1007         }
1008 #endif
1009
1010         /* Creation of current_state must occur after dc->dml
1011          * is initialized in dc_create_resource_pool because
1012          * on creation it copies the contents of dc->dml
1013          */
1014
1015         dc->current_state = dc_create_state(dc);
1016
1017         if (!dc->current_state) {
1018                 dm_error("%s: failed to create validate ctx\n", __func__);
1019                 goto fail;
1020         }
1021
1022         if (!create_links(dc, init_params->num_virtual_links))
1023                 goto fail;
1024
1025         /* Create additional DIG link encoder objects if fewer than the platform
1026          * supports were created during link construction.
1027          */
1028         if (!create_link_encoders(dc))
1029                 goto fail;
1030
1031         dc_resource_state_construct(dc, dc->current_state);
1032
1033         return true;
1034
1035 fail:
1036         return false;
1037 }
1038
1039 static void disable_all_writeback_pipes_for_stream(
1040                 const struct dc *dc,
1041                 struct dc_stream_state *stream,
1042                 struct dc_state *context)
1043 {
1044         int i;
1045
1046         for (i = 0; i < stream->num_wb_info; i++)
1047                 stream->writeback_info[i].wb_enabled = false;
1048 }
1049
1050 static void apply_ctx_interdependent_lock(struct dc *dc, struct dc_state *context,
1051                                           struct dc_stream_state *stream, bool lock)
1052 {
1053         int i;
1054
1055         /* Checks if interdependent update function pointer is NULL or not, takes care of DCE110 case */
1056         if (dc->hwss.interdependent_update_lock)
1057                 dc->hwss.interdependent_update_lock(dc, context, lock);
1058         else {
1059                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1060                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1061                         struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
1062
1063                         // Copied conditions that were previously in dce110_apply_ctx_for_surface
1064                         if (stream == pipe_ctx->stream) {
1065                                 if (!pipe_ctx->top_pipe &&
1066                                         (pipe_ctx->plane_state || old_pipe_ctx->plane_state))
1067                                         dc->hwss.pipe_control_lock(dc, pipe_ctx, lock);
1068                         }
1069                 }
1070         }
1071 }
1072
1073 static void phantom_pipe_blank(
1074                 struct dc *dc,
1075                 struct timing_generator *tg,
1076                 int width,
1077                 int height)
1078 {
1079         struct dce_hwseq *hws = dc->hwseq;
1080         enum dc_color_space color_space;
1081         struct tg_color black_color = {0};
1082         struct output_pixel_processor *opp = NULL;
1083         uint32_t num_opps, opp_id_src0, opp_id_src1;
1084         uint32_t otg_active_width, otg_active_height;
1085         uint32_t i;
1086
1087         /* program opp dpg blank color */
1088         color_space = COLOR_SPACE_SRGB;
1089         color_space_to_black_color(dc, color_space, &black_color);
1090
1091         otg_active_width = width;
1092         otg_active_height = height;
1093
1094         /* get the OPTC source */
1095         tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1);
1096         ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp);
1097
1098         for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
1099                 if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src0) {
1100                         opp = dc->res_pool->opps[i];
1101                         break;
1102                 }
1103         }
1104
1105         if (opp && opp->funcs->opp_set_disp_pattern_generator)
1106                 opp->funcs->opp_set_disp_pattern_generator(
1107                                 opp,
1108                                 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
1109                                 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
1110                                 COLOR_DEPTH_UNDEFINED,
1111                                 &black_color,
1112                                 otg_active_width,
1113                                 otg_active_height,
1114                                 0);
1115
1116         if (tg->funcs->is_tg_enabled(tg))
1117                 hws->funcs.wait_for_blank_complete(opp);
1118 }
1119
1120 static void dc_update_viusal_confirm_color(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
1121 {
1122         if (dc->ctx->dce_version >= DCN_VERSION_1_0) {
1123                 memset(&pipe_ctx->visual_confirm_color, 0, sizeof(struct tg_color));
1124
1125                 if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR)
1126                         get_hdr_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));
1127                 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
1128                         get_surface_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));
1129                 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SWIZZLE)
1130                         get_surface_tile_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));
1131                 else {
1132                         if (dc->ctx->dce_version < DCN_VERSION_2_0)
1133                                 color_space_to_black_color(
1134                                         dc, pipe_ctx->stream->output_color_space, &(pipe_ctx->visual_confirm_color));
1135                 }
1136                 if (dc->ctx->dce_version >= DCN_VERSION_2_0) {
1137                         if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE)
1138                                 get_mpctree_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));
1139                         else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SUBVP)
1140                                 get_subvp_visual_confirm_color(dc, context, pipe_ctx, &(pipe_ctx->visual_confirm_color));
1141                         else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MCLK_SWITCH)
1142                                 get_mclk_switch_visual_confirm_color(dc, context, pipe_ctx, &(pipe_ctx->visual_confirm_color));
1143                 }
1144         }
1145 }
1146
1147 static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
1148 {
1149         int i, j;
1150         struct dc_state *dangling_context = dc_create_state(dc);
1151         struct dc_state *current_ctx;
1152         struct pipe_ctx *pipe;
1153         struct timing_generator *tg;
1154
1155         if (dangling_context == NULL)
1156                 return;
1157
1158         dc_resource_state_copy_construct(dc->current_state, dangling_context);
1159
1160         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1161                 struct dc_stream_state *old_stream =
1162                                 dc->current_state->res_ctx.pipe_ctx[i].stream;
1163                 bool should_disable = true;
1164                 bool pipe_split_change = false;
1165
1166                 if ((context->res_ctx.pipe_ctx[i].top_pipe) &&
1167                         (dc->current_state->res_ctx.pipe_ctx[i].top_pipe))
1168                         pipe_split_change = context->res_ctx.pipe_ctx[i].top_pipe->pipe_idx !=
1169                                 dc->current_state->res_ctx.pipe_ctx[i].top_pipe->pipe_idx;
1170                 else
1171                         pipe_split_change = context->res_ctx.pipe_ctx[i].top_pipe !=
1172                                 dc->current_state->res_ctx.pipe_ctx[i].top_pipe;
1173
1174                 for (j = 0; j < context->stream_count; j++) {
1175                         if (old_stream == context->streams[j]) {
1176                                 should_disable = false;
1177                                 break;
1178                         }
1179                 }
1180                 if (!should_disable && pipe_split_change &&
1181                                 dc->current_state->stream_count != context->stream_count)
1182                         should_disable = true;
1183
1184                 if (old_stream && !dc->current_state->res_ctx.pipe_ctx[i].top_pipe &&
1185                                 !dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe) {
1186                         struct pipe_ctx *old_pipe, *new_pipe;
1187
1188                         old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1189                         new_pipe = &context->res_ctx.pipe_ctx[i];
1190
1191                         if (old_pipe->plane_state && !new_pipe->plane_state)
1192                                 should_disable = true;
1193                 }
1194
1195                 if (should_disable && old_stream) {
1196                         pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1197                         tg = pipe->stream_res.tg;
1198                         /* When disabling plane for a phantom pipe, we must turn on the
1199                          * phantom OTG so the disable programming gets the double buffer
1200                          * update. Otherwise the pipe will be left in a partially disabled
1201                          * state that can result in underflow or hang when enabling it
1202                          * again for different use.
1203                          */
1204                         if (old_stream->mall_stream_config.type == SUBVP_PHANTOM) {
1205                                 if (tg->funcs->enable_crtc) {
1206                                         int main_pipe_width, main_pipe_height;
1207
1208                                         main_pipe_width = old_stream->mall_stream_config.paired_stream->dst.width;
1209                                         main_pipe_height = old_stream->mall_stream_config.paired_stream->dst.height;
1210                                         phantom_pipe_blank(dc, tg, main_pipe_width, main_pipe_height);
1211                                         tg->funcs->enable_crtc(tg);
1212                                 }
1213                         }
1214                         dc_rem_all_planes_for_stream(dc, old_stream, dangling_context);
1215                         disable_all_writeback_pipes_for_stream(dc, old_stream, dangling_context);
1216
1217                         if (pipe->stream && pipe->plane_state)
1218                                 dc_update_viusal_confirm_color(dc, context, pipe);
1219
1220                         if (dc->hwss.apply_ctx_for_surface) {
1221                                 apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, true);
1222                                 dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context);
1223                                 apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, false);
1224                                 dc->hwss.post_unlock_program_front_end(dc, dangling_context);
1225                         }
1226                         if (dc->hwss.program_front_end_for_ctx) {
1227                                 dc->hwss.interdependent_update_lock(dc, dc->current_state, true);
1228                                 dc->hwss.program_front_end_for_ctx(dc, dangling_context);
1229                                 dc->hwss.interdependent_update_lock(dc, dc->current_state, false);
1230                                 dc->hwss.post_unlock_program_front_end(dc, dangling_context);
1231                         }
1232                         /* We need to put the phantom OTG back into it's default (disabled) state or we
1233                          * can get corruption when transition from one SubVP config to a different one.
1234                          * The OTG is set to disable on falling edge of VUPDATE so the plane disable
1235                          * will still get it's double buffer update.
1236                          */
1237                         if (old_stream->mall_stream_config.type == SUBVP_PHANTOM) {
1238                                 if (tg->funcs->disable_phantom_crtc)
1239                                         tg->funcs->disable_phantom_crtc(tg);
1240                         }
1241                 }
1242         }
1243
1244         current_ctx = dc->current_state;
1245         dc->current_state = dangling_context;
1246         dc_release_state(current_ctx);
1247 }
1248
1249 static void disable_vbios_mode_if_required(
1250                 struct dc *dc,
1251                 struct dc_state *context)
1252 {
1253         unsigned int i, j;
1254
1255         /* check if timing_changed, disable stream*/
1256         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1257                 struct dc_stream_state *stream = NULL;
1258                 struct dc_link *link = NULL;
1259                 struct pipe_ctx *pipe = NULL;
1260
1261                 pipe = &context->res_ctx.pipe_ctx[i];
1262                 stream = pipe->stream;
1263                 if (stream == NULL)
1264                         continue;
1265
1266                 // only looking for first odm pipe
1267                 if (pipe->prev_odm_pipe)
1268                         continue;
1269
1270                 if (stream->link->local_sink &&
1271                         stream->link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1272                         link = stream->link;
1273                 }
1274
1275                 if (link != NULL && link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
1276                         unsigned int enc_inst, tg_inst = 0;
1277                         unsigned int pix_clk_100hz;
1278
1279                         enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
1280                         if (enc_inst != ENGINE_ID_UNKNOWN) {
1281                                 for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
1282                                         if (dc->res_pool->stream_enc[j]->id == enc_inst) {
1283                                                 tg_inst = dc->res_pool->stream_enc[j]->funcs->dig_source_otg(
1284                                                         dc->res_pool->stream_enc[j]);
1285                                                 break;
1286                                         }
1287                                 }
1288
1289                                 dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
1290                                         dc->res_pool->dp_clock_source,
1291                                         tg_inst, &pix_clk_100hz);
1292
1293                                 if (link->link_status.link_active) {
1294                                         uint32_t requested_pix_clk_100hz =
1295                                                 pipe->stream_res.pix_clk_params.requested_pix_clk_100hz;
1296
1297                                         if (pix_clk_100hz != requested_pix_clk_100hz) {
1298                                                 dc->link_srv->set_dpms_off(pipe);
1299                                                 pipe->stream->dpms_off = true;
1300                                         }
1301                                 }
1302                         }
1303                 }
1304         }
1305 }
1306
1307 static void wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context)
1308 {
1309         int i;
1310         PERF_TRACE();
1311         for (i = 0; i < MAX_PIPES; i++) {
1312                 int count = 0;
1313                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1314
1315                 if (!pipe->plane_state || pipe->stream->mall_stream_config.type == SUBVP_PHANTOM)
1316                         continue;
1317
1318                 /* Timeout 100 ms */
1319                 while (count < 100000) {
1320                         /* Must set to false to start with, due to OR in update function */
1321                         pipe->plane_state->status.is_flip_pending = false;
1322                         dc->hwss.update_pending_status(pipe);
1323                         if (!pipe->plane_state->status.is_flip_pending)
1324                                 break;
1325                         udelay(1);
1326                         count++;
1327                 }
1328                 ASSERT(!pipe->plane_state->status.is_flip_pending);
1329         }
1330         PERF_TRACE();
1331 }
1332
1333 /* Public functions */
1334
1335 struct dc *dc_create(const struct dc_init_data *init_params)
1336 {
1337         struct dc *dc = kzalloc(sizeof(*dc), GFP_KERNEL);
1338         unsigned int full_pipe_count;
1339
1340         if (!dc)
1341                 return NULL;
1342
1343         if (init_params->dce_environment == DCE_ENV_VIRTUAL_HW) {
1344                 if (!dc_construct_ctx(dc, init_params))
1345                         goto destruct_dc;
1346         } else {
1347                 if (!dc_construct(dc, init_params))
1348                         goto destruct_dc;
1349
1350                 full_pipe_count = dc->res_pool->pipe_count;
1351                 if (dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
1352                         full_pipe_count--;
1353                 dc->caps.max_streams = min(
1354                                 full_pipe_count,
1355                                 dc->res_pool->stream_enc_count);
1356
1357                 dc->caps.max_links = dc->link_count;
1358                 dc->caps.max_audios = dc->res_pool->audio_count;
1359                 dc->caps.linear_pitch_alignment = 64;
1360
1361                 dc->caps.max_dp_protocol_version = DP_VERSION_1_4;
1362
1363                 dc->caps.max_otg_num = dc->res_pool->res_cap->num_timing_generator;
1364
1365                 if (dc->res_pool->dmcu != NULL)
1366                         dc->versions.dmcu_version = dc->res_pool->dmcu->dmcu_version;
1367         }
1368
1369         dc->dcn_reg_offsets = init_params->dcn_reg_offsets;
1370         dc->nbio_reg_offsets = init_params->nbio_reg_offsets;
1371
1372         /* Populate versioning information */
1373         dc->versions.dc_ver = DC_VER;
1374
1375         dc->build_id = DC_BUILD_ID;
1376
1377         DC_LOG_DC("Display Core initialized\n");
1378
1379
1380
1381         return dc;
1382
1383 destruct_dc:
1384         dc_destruct(dc);
1385         kfree(dc);
1386         return NULL;
1387 }
1388
1389 static void detect_edp_presence(struct dc *dc)
1390 {
1391         struct dc_link *edp_links[MAX_NUM_EDP];
1392         struct dc_link *edp_link = NULL;
1393         enum dc_connection_type type;
1394         int i;
1395         int edp_num;
1396
1397         dc_get_edp_links(dc, edp_links, &edp_num);
1398         if (!edp_num)
1399                 return;
1400
1401         for (i = 0; i < edp_num; i++) {
1402                 edp_link = edp_links[i];
1403                 if (dc->config.edp_not_connected) {
1404                         edp_link->edp_sink_present = false;
1405                 } else {
1406                         dc_link_detect_connection_type(edp_link, &type);
1407                         edp_link->edp_sink_present = (type != dc_connection_none);
1408                 }
1409         }
1410 }
1411
1412 void dc_hardware_init(struct dc *dc)
1413 {
1414
1415         detect_edp_presence(dc);
1416         if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW)
1417                 dc->hwss.init_hw(dc);
1418 }
1419
1420 void dc_init_callbacks(struct dc *dc,
1421                 const struct dc_callback_init *init_params)
1422 {
1423         dc->ctx->cp_psp = init_params->cp_psp;
1424 }
1425
1426 void dc_deinit_callbacks(struct dc *dc)
1427 {
1428         memset(&dc->ctx->cp_psp, 0, sizeof(dc->ctx->cp_psp));
1429 }
1430
1431 void dc_destroy(struct dc **dc)
1432 {
1433         dc_destruct(*dc);
1434         kfree(*dc);
1435         *dc = NULL;
1436 }
1437
1438 static void enable_timing_multisync(
1439                 struct dc *dc,
1440                 struct dc_state *ctx)
1441 {
1442         int i, multisync_count = 0;
1443         int pipe_count = dc->res_pool->pipe_count;
1444         struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL };
1445
1446         for (i = 0; i < pipe_count; i++) {
1447                 if (!ctx->res_ctx.pipe_ctx[i].stream ||
1448                                 !ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.enabled)
1449                         continue;
1450                 if (ctx->res_ctx.pipe_ctx[i].stream == ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.event_source)
1451                         continue;
1452                 multisync_pipes[multisync_count] = &ctx->res_ctx.pipe_ctx[i];
1453                 multisync_count++;
1454         }
1455
1456         if (multisync_count > 0) {
1457                 dc->hwss.enable_per_frame_crtc_position_reset(
1458                         dc, multisync_count, multisync_pipes);
1459         }
1460 }
1461
1462 static void program_timing_sync(
1463                 struct dc *dc,
1464                 struct dc_state *ctx)
1465 {
1466         int i, j, k;
1467         int group_index = 0;
1468         int num_group = 0;
1469         int pipe_count = dc->res_pool->pipe_count;
1470         struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };
1471
1472         for (i = 0; i < pipe_count; i++) {
1473                 if (!ctx->res_ctx.pipe_ctx[i].stream
1474                                 || ctx->res_ctx.pipe_ctx[i].top_pipe
1475                                 || ctx->res_ctx.pipe_ctx[i].prev_odm_pipe)
1476                         continue;
1477
1478                 unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i];
1479         }
1480
1481         for (i = 0; i < pipe_count; i++) {
1482                 int group_size = 1;
1483                 enum timing_synchronization_type sync_type = NOT_SYNCHRONIZABLE;
1484                 struct pipe_ctx *pipe_set[MAX_PIPES];
1485
1486                 if (!unsynced_pipes[i])
1487                         continue;
1488
1489                 pipe_set[0] = unsynced_pipes[i];
1490                 unsynced_pipes[i] = NULL;
1491
1492                 /* Add tg to the set, search rest of the tg's for ones with
1493                  * same timing, add all tgs with same timing to the group
1494                  */
1495                 for (j = i + 1; j < pipe_count; j++) {
1496                         if (!unsynced_pipes[j])
1497                                 continue;
1498                         if (sync_type != TIMING_SYNCHRONIZABLE &&
1499                                 dc->hwss.enable_vblanks_synchronization &&
1500                                 unsynced_pipes[j]->stream_res.tg->funcs->align_vblanks &&
1501                                 resource_are_vblanks_synchronizable(
1502                                         unsynced_pipes[j]->stream,
1503                                         pipe_set[0]->stream)) {
1504                                 sync_type = VBLANK_SYNCHRONIZABLE;
1505                                 pipe_set[group_size] = unsynced_pipes[j];
1506                                 unsynced_pipes[j] = NULL;
1507                                 group_size++;
1508                         } else
1509                         if (sync_type != VBLANK_SYNCHRONIZABLE &&
1510                                 resource_are_streams_timing_synchronizable(
1511                                         unsynced_pipes[j]->stream,
1512                                         pipe_set[0]->stream)) {
1513                                 sync_type = TIMING_SYNCHRONIZABLE;
1514                                 pipe_set[group_size] = unsynced_pipes[j];
1515                                 unsynced_pipes[j] = NULL;
1516                                 group_size++;
1517                         }
1518                 }
1519
1520                 /* set first unblanked pipe as master */
1521                 for (j = 0; j < group_size; j++) {
1522                         bool is_blanked;
1523
1524                         if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)
1525                                 is_blanked =
1526                                         pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);
1527                         else
1528                                 is_blanked =
1529                                         pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);
1530                         if (!is_blanked) {
1531                                 if (j == 0)
1532                                         break;
1533
1534                                 swap(pipe_set[0], pipe_set[j]);
1535                                 break;
1536                         }
1537                 }
1538
1539                 for (k = 0; k < group_size; k++) {
1540                         struct dc_stream_status *status = dc_stream_get_status_from_state(ctx, pipe_set[k]->stream);
1541
1542                         status->timing_sync_info.group_id = num_group;
1543                         status->timing_sync_info.group_size = group_size;
1544                         if (k == 0)
1545                                 status->timing_sync_info.master = true;
1546                         else
1547                                 status->timing_sync_info.master = false;
1548
1549                 }
1550
1551                 /* remove any other pipes that are already been synced */
1552                 if (dc->config.use_pipe_ctx_sync_logic) {
1553                         /* check pipe's syncd to decide which pipe to be removed */
1554                         for (j = 1; j < group_size; j++) {
1555                                 if (pipe_set[j]->pipe_idx_syncd == pipe_set[0]->pipe_idx_syncd) {
1556                                         group_size--;
1557                                         pipe_set[j] = pipe_set[group_size];
1558                                         j--;
1559                                 } else
1560                                         /* link slave pipe's syncd with master pipe */
1561                                         pipe_set[j]->pipe_idx_syncd = pipe_set[0]->pipe_idx_syncd;
1562                         }
1563                 } else {
1564                         for (j = j + 1; j < group_size; j++) {
1565                                 bool is_blanked;
1566
1567                                 if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)
1568                                         is_blanked =
1569                                                 pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);
1570                                 else
1571                                         is_blanked =
1572                                                 pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);
1573                                 if (!is_blanked) {
1574                                         group_size--;
1575                                         pipe_set[j] = pipe_set[group_size];
1576                                         j--;
1577                                 }
1578                         }
1579                 }
1580
1581                 if (group_size > 1) {
1582                         if (sync_type == TIMING_SYNCHRONIZABLE) {
1583                                 dc->hwss.enable_timing_synchronization(
1584                                         dc, group_index, group_size, pipe_set);
1585                         } else
1586                                 if (sync_type == VBLANK_SYNCHRONIZABLE) {
1587                                 dc->hwss.enable_vblanks_synchronization(
1588                                         dc, group_index, group_size, pipe_set);
1589                                 }
1590                         group_index++;
1591                 }
1592                 num_group++;
1593         }
1594 }
1595
1596 static bool streams_changed(struct dc *dc,
1597                             struct dc_stream_state *streams[],
1598                             uint8_t stream_count)
1599 {
1600         uint8_t i;
1601
1602         if (stream_count != dc->current_state->stream_count)
1603                 return true;
1604
1605         for (i = 0; i < dc->current_state->stream_count; i++) {
1606                 if (dc->current_state->streams[i] != streams[i])
1607                         return true;
1608                 if (!streams[i]->link->link_state_valid)
1609                         return true;
1610         }
1611
1612         return false;
1613 }
1614
1615 bool dc_validate_boot_timing(const struct dc *dc,
1616                                 const struct dc_sink *sink,
1617                                 struct dc_crtc_timing *crtc_timing)
1618 {
1619         struct timing_generator *tg;
1620         struct stream_encoder *se = NULL;
1621
1622         struct dc_crtc_timing hw_crtc_timing = {0};
1623
1624         struct dc_link *link = sink->link;
1625         unsigned int i, enc_inst, tg_inst = 0;
1626
1627         /* Support seamless boot on EDP displays only */
1628         if (sink->sink_signal != SIGNAL_TYPE_EDP) {
1629                 return false;
1630         }
1631
1632         /* Check for enabled DIG to identify enabled display */
1633         if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
1634                 return false;
1635
1636         enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
1637
1638         if (enc_inst == ENGINE_ID_UNKNOWN)
1639                 return false;
1640
1641         for (i = 0; i < dc->res_pool->stream_enc_count; i++) {
1642                 if (dc->res_pool->stream_enc[i]->id == enc_inst) {
1643
1644                         se = dc->res_pool->stream_enc[i];
1645
1646                         tg_inst = dc->res_pool->stream_enc[i]->funcs->dig_source_otg(
1647                                 dc->res_pool->stream_enc[i]);
1648                         break;
1649                 }
1650         }
1651
1652         // tg_inst not found
1653         if (i == dc->res_pool->stream_enc_count)
1654                 return false;
1655
1656         if (tg_inst >= dc->res_pool->timing_generator_count)
1657                 return false;
1658
1659         if (tg_inst != link->link_enc->preferred_engine)
1660                 return false;
1661
1662         tg = dc->res_pool->timing_generators[tg_inst];
1663
1664         if (!tg->funcs->get_hw_timing)
1665                 return false;
1666
1667         if (!tg->funcs->get_hw_timing(tg, &hw_crtc_timing))
1668                 return false;
1669
1670         if (crtc_timing->h_total != hw_crtc_timing.h_total)
1671                 return false;
1672
1673         if (crtc_timing->h_border_left != hw_crtc_timing.h_border_left)
1674                 return false;
1675
1676         if (crtc_timing->h_addressable != hw_crtc_timing.h_addressable)
1677                 return false;
1678
1679         if (crtc_timing->h_border_right != hw_crtc_timing.h_border_right)
1680                 return false;
1681
1682         if (crtc_timing->h_front_porch != hw_crtc_timing.h_front_porch)
1683                 return false;
1684
1685         if (crtc_timing->h_sync_width != hw_crtc_timing.h_sync_width)
1686                 return false;
1687
1688         if (crtc_timing->v_total != hw_crtc_timing.v_total)
1689                 return false;
1690
1691         if (crtc_timing->v_border_top != hw_crtc_timing.v_border_top)
1692                 return false;
1693
1694         if (crtc_timing->v_addressable != hw_crtc_timing.v_addressable)
1695                 return false;
1696
1697         if (crtc_timing->v_border_bottom != hw_crtc_timing.v_border_bottom)
1698                 return false;
1699
1700         if (crtc_timing->v_front_porch != hw_crtc_timing.v_front_porch)
1701                 return false;
1702
1703         if (crtc_timing->v_sync_width != hw_crtc_timing.v_sync_width)
1704                 return false;
1705
1706         /* block DSC for now, as VBIOS does not currently support DSC timings */
1707         if (crtc_timing->flags.DSC)
1708                 return false;
1709
1710         if (dc_is_dp_signal(link->connector_signal)) {
1711                 unsigned int pix_clk_100hz;
1712                 uint32_t numOdmPipes = 1;
1713                 uint32_t id_src[4] = {0};
1714
1715                 dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
1716                         dc->res_pool->dp_clock_source,
1717                         tg_inst, &pix_clk_100hz);
1718
1719                 if (tg->funcs->get_optc_source)
1720                         tg->funcs->get_optc_source(tg,
1721                                                 &numOdmPipes, &id_src[0], &id_src[1]);
1722
1723                 if (numOdmPipes == 2)
1724                         pix_clk_100hz *= 2;
1725                 if (numOdmPipes == 4)
1726                         pix_clk_100hz *= 4;
1727
1728                 // Note: In rare cases, HW pixclk may differ from crtc's pixclk
1729                 // slightly due to rounding issues in 10 kHz units.
1730                 if (crtc_timing->pix_clk_100hz != pix_clk_100hz)
1731                         return false;
1732
1733                 if (!se->funcs->dp_get_pixel_format)
1734                         return false;
1735
1736                 if (!se->funcs->dp_get_pixel_format(
1737                         se,
1738                         &hw_crtc_timing.pixel_encoding,
1739                         &hw_crtc_timing.display_color_depth))
1740                         return false;
1741
1742                 if (hw_crtc_timing.display_color_depth != crtc_timing->display_color_depth)
1743                         return false;
1744
1745                 if (hw_crtc_timing.pixel_encoding != crtc_timing->pixel_encoding)
1746                         return false;
1747         }
1748
1749         if (link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED) {
1750                 return false;
1751         }
1752
1753         if (dc->link_srv->edp_is_ilr_optimization_required(link, crtc_timing)) {
1754                 DC_LOG_EVENT_LINK_TRAINING("Seamless boot disabled to optimize eDP link rate\n");
1755                 return false;
1756         }
1757
1758         return true;
1759 }
1760
1761 static inline bool should_update_pipe_for_stream(
1762                 struct dc_state *context,
1763                 struct pipe_ctx *pipe_ctx,
1764                 struct dc_stream_state *stream)
1765 {
1766         return (pipe_ctx->stream && pipe_ctx->stream == stream);
1767 }
1768
1769 static inline bool should_update_pipe_for_plane(
1770                 struct dc_state *context,
1771                 struct pipe_ctx *pipe_ctx,
1772                 struct dc_plane_state *plane_state)
1773 {
1774         return (pipe_ctx->plane_state == plane_state);
1775 }
1776
1777 void dc_enable_stereo(
1778         struct dc *dc,
1779         struct dc_state *context,
1780         struct dc_stream_state *streams[],
1781         uint8_t stream_count)
1782 {
1783         int i, j;
1784         struct pipe_ctx *pipe;
1785
1786         for (i = 0; i < MAX_PIPES; i++) {
1787                 if (context != NULL) {
1788                         pipe = &context->res_ctx.pipe_ctx[i];
1789                 } else {
1790                         context = dc->current_state;
1791                         pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1792                 }
1793
1794                 for (j = 0; pipe && j < stream_count; j++)  {
1795                         if (should_update_pipe_for_stream(context, pipe, streams[j]) &&
1796                                 dc->hwss.setup_stereo)
1797                                 dc->hwss.setup_stereo(pipe, dc);
1798                 }
1799         }
1800 }
1801
1802 void dc_trigger_sync(struct dc *dc, struct dc_state *context)
1803 {
1804         if (context->stream_count > 1 && !dc->debug.disable_timing_sync) {
1805                 enable_timing_multisync(dc, context);
1806                 program_timing_sync(dc, context);
1807         }
1808 }
1809
1810 static uint8_t get_stream_mask(struct dc *dc, struct dc_state *context)
1811 {
1812         int i;
1813         unsigned int stream_mask = 0;
1814
1815         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1816                 if (context->res_ctx.pipe_ctx[i].stream)
1817                         stream_mask |= 1 << i;
1818         }
1819
1820         return stream_mask;
1821 }
1822
1823 void dc_z10_restore(const struct dc *dc)
1824 {
1825         if (dc->hwss.z10_restore)
1826                 dc->hwss.z10_restore(dc);
1827 }
1828
1829 void dc_z10_save_init(struct dc *dc)
1830 {
1831         if (dc->hwss.z10_save_init)
1832                 dc->hwss.z10_save_init(dc);
1833 }
1834
1835 /**
1836  * dc_commit_state_no_check - Apply context to the hardware
1837  *
1838  * @dc: DC object with the current status to be updated
1839  * @context: New state that will become the current status at the end of this function
1840  *
1841  * Applies given context to the hardware and copy it into current context.
1842  * It's up to the user to release the src context afterwards.
1843  *
1844  * Return: an enum dc_status result code for the operation
1845  */
1846 static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *context)
1847 {
1848         struct dc_bios *dcb = dc->ctx->dc_bios;
1849         enum dc_status result = DC_ERROR_UNEXPECTED;
1850         struct pipe_ctx *pipe;
1851         int i, k, l;
1852         struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
1853         struct dc_state *old_state;
1854         bool subvp_prev_use = false;
1855
1856         dc_z10_restore(dc);
1857         dc_allow_idle_optimizations(dc, false);
1858
1859         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1860                 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1861
1862                 /* Check old context for SubVP */
1863                 subvp_prev_use |= (old_pipe->stream && old_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM);
1864                 if (subvp_prev_use)
1865                         break;
1866         }
1867
1868         for (i = 0; i < context->stream_count; i++)
1869                 dc_streams[i] =  context->streams[i];
1870
1871         if (!dcb->funcs->is_accelerated_mode(dcb)) {
1872                 disable_vbios_mode_if_required(dc, context);
1873                 dc->hwss.enable_accelerated_mode(dc, context);
1874         }
1875
1876         if (context->stream_count > get_seamless_boot_stream_count(context) ||
1877                 context->stream_count == 0)
1878                 dc->hwss.prepare_bandwidth(dc, context);
1879
1880         /* When SubVP is active, all HW programming must be done while
1881          * SubVP lock is acquired
1882          */
1883         if (dc->hwss.subvp_pipe_control_lock)
1884                 dc->hwss.subvp_pipe_control_lock(dc, context, true, true, NULL, subvp_prev_use);
1885
1886         if (dc->debug.enable_double_buffered_dsc_pg_support)
1887                 dc->hwss.update_dsc_pg(dc, context, false);
1888
1889         disable_dangling_plane(dc, context);
1890         /* re-program planes for existing stream, in case we need to
1891          * free up plane resource for later use
1892          */
1893         if (dc->hwss.apply_ctx_for_surface) {
1894                 for (i = 0; i < context->stream_count; i++) {
1895                         if (context->streams[i]->mode_changed)
1896                                 continue;
1897                         apply_ctx_interdependent_lock(dc, context, context->streams[i], true);
1898                         dc->hwss.apply_ctx_for_surface(
1899                                 dc, context->streams[i],
1900                                 context->stream_status[i].plane_count,
1901                                 context); /* use new pipe config in new context */
1902                         apply_ctx_interdependent_lock(dc, context, context->streams[i], false);
1903                         dc->hwss.post_unlock_program_front_end(dc, context);
1904                 }
1905         }
1906
1907         /* Program hardware */
1908         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1909                 pipe = &context->res_ctx.pipe_ctx[i];
1910                 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe);
1911         }
1912
1913         result = dc->hwss.apply_ctx_to_hw(dc, context);
1914
1915         if (result != DC_OK) {
1916                 /* Application of dc_state to hardware stopped. */
1917                 dc->current_state->res_ctx.link_enc_cfg_ctx.mode = LINK_ENC_CFG_STEADY;
1918                 return result;
1919         }
1920
1921         dc_trigger_sync(dc, context);
1922
1923         /* Program all planes within new context*/
1924         if (dc->hwss.program_front_end_for_ctx) {
1925                 dc->hwss.interdependent_update_lock(dc, context, true);
1926                 dc->hwss.program_front_end_for_ctx(dc, context);
1927                 dc->hwss.interdependent_update_lock(dc, context, false);
1928                 dc->hwss.post_unlock_program_front_end(dc, context);
1929         }
1930
1931         if (dc->hwss.commit_subvp_config)
1932                 dc->hwss.commit_subvp_config(dc, context);
1933         if (dc->hwss.subvp_pipe_control_lock)
1934                 dc->hwss.subvp_pipe_control_lock(dc, context, false, true, NULL, subvp_prev_use);
1935
1936         for (i = 0; i < context->stream_count; i++) {
1937                 const struct dc_link *link = context->streams[i]->link;
1938
1939                 if (!context->streams[i]->mode_changed)
1940                         continue;
1941
1942                 if (dc->hwss.apply_ctx_for_surface) {
1943                         apply_ctx_interdependent_lock(dc, context, context->streams[i], true);
1944                         dc->hwss.apply_ctx_for_surface(
1945                                         dc, context->streams[i],
1946                                         context->stream_status[i].plane_count,
1947                                         context);
1948                         apply_ctx_interdependent_lock(dc, context, context->streams[i], false);
1949                         dc->hwss.post_unlock_program_front_end(dc, context);
1950                 }
1951
1952                 /*
1953                  * enable stereo
1954                  * TODO rework dc_enable_stereo call to work with validation sets?
1955                  */
1956                 for (k = 0; k < MAX_PIPES; k++) {
1957                         pipe = &context->res_ctx.pipe_ctx[k];
1958
1959                         for (l = 0 ; pipe && l < context->stream_count; l++)  {
1960                                 if (context->streams[l] &&
1961                                         context->streams[l] == pipe->stream &&
1962                                         dc->hwss.setup_stereo)
1963                                         dc->hwss.setup_stereo(pipe, dc);
1964                         }
1965                 }
1966
1967                 CONN_MSG_MODE(link, "{%dx%d, %dx%d@%dKhz}",
1968                                 context->streams[i]->timing.h_addressable,
1969                                 context->streams[i]->timing.v_addressable,
1970                                 context->streams[i]->timing.h_total,
1971                                 context->streams[i]->timing.v_total,
1972                                 context->streams[i]->timing.pix_clk_100hz / 10);
1973         }
1974
1975         dc_enable_stereo(dc, context, dc_streams, context->stream_count);
1976
1977         if (context->stream_count > get_seamless_boot_stream_count(context) ||
1978                 context->stream_count == 0) {
1979                 /* Must wait for no flips to be pending before doing optimize bw */
1980                 wait_for_no_pipes_pending(dc, context);
1981                 /* pplib is notified if disp_num changed */
1982                 dc->hwss.optimize_bandwidth(dc, context);
1983         }
1984
1985         if (dc->debug.enable_double_buffered_dsc_pg_support)
1986                 dc->hwss.update_dsc_pg(dc, context, true);
1987
1988         if (dc->ctx->dce_version >= DCE_VERSION_MAX)
1989                 TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk);
1990         else
1991                 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);
1992
1993         context->stream_mask = get_stream_mask(dc, context);
1994
1995         if (context->stream_mask != dc->current_state->stream_mask)
1996                 dc_dmub_srv_notify_stream_mask(dc->ctx->dmub_srv, context->stream_mask);
1997
1998         for (i = 0; i < context->stream_count; i++)
1999                 context->streams[i]->mode_changed = false;
2000
2001         old_state = dc->current_state;
2002         dc->current_state = context;
2003
2004         dc_release_state(old_state);
2005
2006         dc_retain_state(dc->current_state);
2007
2008         return result;
2009 }
2010
2011 static bool commit_minimal_transition_state(struct dc *dc,
2012                 struct dc_state *transition_base_context);
2013
2014 /**
2015  * dc_commit_streams - Commit current stream state
2016  *
2017  * @dc: DC object with the commit state to be configured in the hardware
2018  * @streams: Array with a list of stream state
2019  * @stream_count: Total of streams
2020  *
2021  * Function responsible for commit streams change to the hardware.
2022  *
2023  * Return:
2024  * Return DC_OK if everything work as expected, otherwise, return a dc_status
2025  * code.
2026  */
2027 enum dc_status dc_commit_streams(struct dc *dc,
2028                                  struct dc_stream_state *streams[],
2029                                  uint8_t stream_count)
2030 {
2031         int i, j;
2032         struct dc_state *context;
2033         enum dc_status res = DC_OK;
2034         struct dc_validation_set set[MAX_STREAMS] = {0};
2035         struct pipe_ctx *pipe;
2036         bool handle_exit_odm2to1 = false;
2037
2038         if (dc->ctx->dce_environment == DCE_ENV_VIRTUAL_HW)
2039                 return res;
2040
2041         if (!streams_changed(dc, streams, stream_count))
2042                 return res;
2043
2044         DC_LOG_DC("%s: %d streams\n", __func__, stream_count);
2045
2046         for (i = 0; i < stream_count; i++) {
2047                 struct dc_stream_state *stream = streams[i];
2048                 struct dc_stream_status *status = dc_stream_get_status(stream);
2049
2050                 dc_stream_log(dc, stream);
2051
2052                 set[i].stream = stream;
2053
2054                 if (status) {
2055                         set[i].plane_count = status->plane_count;
2056                         for (j = 0; j < status->plane_count; j++)
2057                                 set[i].plane_states[j] = status->plane_states[j];
2058                 }
2059         }
2060
2061         /* Check for case where we are going from odm 2:1 to max
2062          *  pipe scenario.  For these cases, we will call
2063          *  commit_minimal_transition_state() to exit out of odm 2:1
2064          *  first before processing new streams
2065          */
2066         if (stream_count == dc->res_pool->pipe_count) {
2067                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2068                         pipe = &dc->current_state->res_ctx.pipe_ctx[i];
2069                         if (pipe->next_odm_pipe)
2070                                 handle_exit_odm2to1 = true;
2071                 }
2072         }
2073
2074         if (handle_exit_odm2to1)
2075                 res = commit_minimal_transition_state(dc, dc->current_state);
2076
2077         context = dc_create_state(dc);
2078         if (!context)
2079                 goto context_alloc_fail;
2080
2081         dc_resource_state_copy_construct_current(dc, context);
2082
2083         res = dc_validate_with_context(dc, set, stream_count, context, false);
2084         if (res != DC_OK) {
2085                 BREAK_TO_DEBUGGER();
2086                 goto fail;
2087         }
2088
2089         res = dc_commit_state_no_check(dc, context);
2090
2091         for (i = 0; i < stream_count; i++) {
2092                 for (j = 0; j < context->stream_count; j++) {
2093                         if (streams[i]->stream_id == context->streams[j]->stream_id)
2094                                 streams[i]->out.otg_offset = context->stream_status[j].primary_otg_inst;
2095
2096                         if (dc_is_embedded_signal(streams[i]->signal)) {
2097                                 struct dc_stream_status *status = dc_stream_get_status_from_state(context, streams[i]);
2098
2099                                 if (dc->hwss.is_abm_supported)
2100                                         status->is_abm_supported = dc->hwss.is_abm_supported(dc, context, streams[i]);
2101                                 else
2102                                         status->is_abm_supported = true;
2103                         }
2104                 }
2105         }
2106
2107 fail:
2108         dc_release_state(context);
2109
2110 context_alloc_fail:
2111
2112         DC_LOG_DC("%s Finished.\n", __func__);
2113
2114         return res;
2115 }
2116
2117 bool dc_acquire_release_mpc_3dlut(
2118                 struct dc *dc, bool acquire,
2119                 struct dc_stream_state *stream,
2120                 struct dc_3dlut **lut,
2121                 struct dc_transfer_func **shaper)
2122 {
2123         int pipe_idx;
2124         bool ret = false;
2125         bool found_pipe_idx = false;
2126         const struct resource_pool *pool = dc->res_pool;
2127         struct resource_context *res_ctx = &dc->current_state->res_ctx;
2128         int mpcc_id = 0;
2129
2130         if (pool && res_ctx) {
2131                 if (acquire) {
2132                         /*find pipe idx for the given stream*/
2133                         for (pipe_idx = 0; pipe_idx < pool->pipe_count; pipe_idx++) {
2134                                 if (res_ctx->pipe_ctx[pipe_idx].stream == stream) {
2135                                         found_pipe_idx = true;
2136                                         mpcc_id = res_ctx->pipe_ctx[pipe_idx].plane_res.hubp->inst;
2137                                         break;
2138                                 }
2139                         }
2140                 } else
2141                         found_pipe_idx = true;/*for release pipe_idx is not required*/
2142
2143                 if (found_pipe_idx) {
2144                         if (acquire && pool->funcs->acquire_post_bldn_3dlut)
2145                                 ret = pool->funcs->acquire_post_bldn_3dlut(res_ctx, pool, mpcc_id, lut, shaper);
2146                         else if (!acquire && pool->funcs->release_post_bldn_3dlut)
2147                                 ret = pool->funcs->release_post_bldn_3dlut(res_ctx, pool, lut, shaper);
2148                 }
2149         }
2150         return ret;
2151 }
2152
2153 static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)
2154 {
2155         int i;
2156         struct pipe_ctx *pipe;
2157
2158         for (i = 0; i < MAX_PIPES; i++) {
2159                 pipe = &context->res_ctx.pipe_ctx[i];
2160
2161                 // Don't check flip pending on phantom pipes
2162                 if (!pipe->plane_state || (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM))
2163                         continue;
2164
2165                 /* Must set to false to start with, due to OR in update function */
2166                 pipe->plane_state->status.is_flip_pending = false;
2167                 dc->hwss.update_pending_status(pipe);
2168                 if (pipe->plane_state->status.is_flip_pending)
2169                         return true;
2170         }
2171         return false;
2172 }
2173
2174 /* Perform updates here which need to be deferred until next vupdate
2175  *
2176  * i.e. blnd lut, 3dlut, and shaper lut bypass regs are double buffered
2177  * but forcing lut memory to shutdown state is immediate. This causes
2178  * single frame corruption as lut gets disabled mid-frame unless shutdown
2179  * is deferred until after entering bypass.
2180  */
2181 static void process_deferred_updates(struct dc *dc)
2182 {
2183         int i = 0;
2184
2185         if (dc->debug.enable_mem_low_power.bits.cm) {
2186                 ASSERT(dc->dcn_ip->max_num_dpp);
2187                 for (i = 0; i < dc->dcn_ip->max_num_dpp; i++)
2188                         if (dc->res_pool->dpps[i]->funcs->dpp_deferred_update)
2189                                 dc->res_pool->dpps[i]->funcs->dpp_deferred_update(dc->res_pool->dpps[i]);
2190         }
2191 }
2192
2193 void dc_post_update_surfaces_to_stream(struct dc *dc)
2194 {
2195         int i;
2196         struct dc_state *context = dc->current_state;
2197
2198         if ((!dc->optimized_required) || get_seamless_boot_stream_count(context) > 0)
2199                 return;
2200
2201         post_surface_trace(dc);
2202
2203         /*
2204          * Only relevant for DCN behavior where we can guarantee the optimization
2205          * is safe to apply - retain the legacy behavior for DCE.
2206          */
2207
2208         if (dc->ctx->dce_version < DCE_VERSION_MAX)
2209                 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);
2210         else {
2211                 TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk);
2212
2213                 if (is_flip_pending_in_pipes(dc, context))
2214                         return;
2215
2216                 for (i = 0; i < dc->res_pool->pipe_count; i++)
2217                         if (context->res_ctx.pipe_ctx[i].stream == NULL ||
2218                                         context->res_ctx.pipe_ctx[i].plane_state == NULL) {
2219                                 context->res_ctx.pipe_ctx[i].pipe_idx = i;
2220                                 dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]);
2221                         }
2222
2223                 process_deferred_updates(dc);
2224
2225                 dc->hwss.optimize_bandwidth(dc, context);
2226
2227                 if (dc->debug.enable_double_buffered_dsc_pg_support)
2228                         dc->hwss.update_dsc_pg(dc, context, true);
2229         }
2230
2231         dc->optimized_required = false;
2232         dc->wm_optimized_required = false;
2233 }
2234
2235 static void init_state(struct dc *dc, struct dc_state *context)
2236 {
2237         /* Each context must have their own instance of VBA and in order to
2238          * initialize and obtain IP and SOC the base DML instance from DC is
2239          * initially copied into every context
2240          */
2241         memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib));
2242 }
2243
2244 struct dc_state *dc_create_state(struct dc *dc)
2245 {
2246         struct dc_state *context = kvzalloc(sizeof(struct dc_state),
2247                                             GFP_KERNEL);
2248
2249         if (!context)
2250                 return NULL;
2251
2252         init_state(dc, context);
2253
2254         kref_init(&context->refcount);
2255
2256         return context;
2257 }
2258
2259 struct dc_state *dc_copy_state(struct dc_state *src_ctx)
2260 {
2261         int i, j;
2262         struct dc_state *new_ctx = kvmalloc(sizeof(struct dc_state), GFP_KERNEL);
2263
2264         if (!new_ctx)
2265                 return NULL;
2266         memcpy(new_ctx, src_ctx, sizeof(struct dc_state));
2267
2268         for (i = 0; i < MAX_PIPES; i++) {
2269                         struct pipe_ctx *cur_pipe = &new_ctx->res_ctx.pipe_ctx[i];
2270
2271                         if (cur_pipe->top_pipe)
2272                                 cur_pipe->top_pipe =  &new_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
2273
2274                         if (cur_pipe->bottom_pipe)
2275                                 cur_pipe->bottom_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
2276
2277                         if (cur_pipe->prev_odm_pipe)
2278                                 cur_pipe->prev_odm_pipe =  &new_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];
2279
2280                         if (cur_pipe->next_odm_pipe)
2281                                 cur_pipe->next_odm_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];
2282
2283         }
2284
2285         for (i = 0; i < new_ctx->stream_count; i++) {
2286                         dc_stream_retain(new_ctx->streams[i]);
2287                         for (j = 0; j < new_ctx->stream_status[i].plane_count; j++)
2288                                 dc_plane_state_retain(
2289                                         new_ctx->stream_status[i].plane_states[j]);
2290         }
2291
2292         kref_init(&new_ctx->refcount);
2293
2294         return new_ctx;
2295 }
2296
2297 void dc_retain_state(struct dc_state *context)
2298 {
2299         kref_get(&context->refcount);
2300 }
2301
2302 static void dc_state_free(struct kref *kref)
2303 {
2304         struct dc_state *context = container_of(kref, struct dc_state, refcount);
2305         dc_resource_state_destruct(context);
2306         kvfree(context);
2307 }
2308
2309 void dc_release_state(struct dc_state *context)
2310 {
2311         kref_put(&context->refcount, dc_state_free);
2312 }
2313
2314 bool dc_set_generic_gpio_for_stereo(bool enable,
2315                 struct gpio_service *gpio_service)
2316 {
2317         enum gpio_result gpio_result = GPIO_RESULT_NON_SPECIFIC_ERROR;
2318         struct gpio_pin_info pin_info;
2319         struct gpio *generic;
2320         struct gpio_generic_mux_config *config = kzalloc(sizeof(struct gpio_generic_mux_config),
2321                            GFP_KERNEL);
2322
2323         if (!config)
2324                 return false;
2325         pin_info = dal_gpio_get_generic_pin_info(gpio_service, GPIO_ID_GENERIC, 0);
2326
2327         if (pin_info.mask == 0xFFFFFFFF || pin_info.offset == 0xFFFFFFFF) {
2328                 kfree(config);
2329                 return false;
2330         } else {
2331                 generic = dal_gpio_service_create_generic_mux(
2332                         gpio_service,
2333                         pin_info.offset,
2334                         pin_info.mask);
2335         }
2336
2337         if (!generic) {
2338                 kfree(config);
2339                 return false;
2340         }
2341
2342         gpio_result = dal_gpio_open(generic, GPIO_MODE_OUTPUT);
2343
2344         config->enable_output_from_mux = enable;
2345         config->mux_select = GPIO_SIGNAL_SOURCE_PASS_THROUGH_STEREO_SYNC;
2346
2347         if (gpio_result == GPIO_RESULT_OK)
2348                 gpio_result = dal_mux_setup_config(generic, config);
2349
2350         if (gpio_result == GPIO_RESULT_OK) {
2351                 dal_gpio_close(generic);
2352                 dal_gpio_destroy_generic_mux(&generic);
2353                 kfree(config);
2354                 return true;
2355         } else {
2356                 dal_gpio_close(generic);
2357                 dal_gpio_destroy_generic_mux(&generic);
2358                 kfree(config);
2359                 return false;
2360         }
2361 }
2362
2363 static bool is_surface_in_context(
2364                 const struct dc_state *context,
2365                 const struct dc_plane_state *plane_state)
2366 {
2367         int j;
2368
2369         for (j = 0; j < MAX_PIPES; j++) {
2370                 const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2371
2372                 if (plane_state == pipe_ctx->plane_state) {
2373                         return true;
2374                 }
2375         }
2376
2377         return false;
2378 }
2379
2380 static enum surface_update_type get_plane_info_update_type(const struct dc_surface_update *u)
2381 {
2382         union surface_update_flags *update_flags = &u->surface->update_flags;
2383         enum surface_update_type update_type = UPDATE_TYPE_FAST;
2384
2385         if (!u->plane_info)
2386                 return UPDATE_TYPE_FAST;
2387
2388         if (u->plane_info->color_space != u->surface->color_space) {
2389                 update_flags->bits.color_space_change = 1;
2390                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
2391         }
2392
2393         if (u->plane_info->horizontal_mirror != u->surface->horizontal_mirror) {
2394                 update_flags->bits.horizontal_mirror_change = 1;
2395                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
2396         }
2397
2398         if (u->plane_info->rotation != u->surface->rotation) {
2399                 update_flags->bits.rotation_change = 1;
2400                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
2401         }
2402
2403         if (u->plane_info->format != u->surface->format) {
2404                 update_flags->bits.pixel_format_change = 1;
2405                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
2406         }
2407
2408         if (u->plane_info->stereo_format != u->surface->stereo_format) {
2409                 update_flags->bits.stereo_format_change = 1;
2410                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
2411         }
2412
2413         if (u->plane_info->per_pixel_alpha != u->surface->per_pixel_alpha) {
2414                 update_flags->bits.per_pixel_alpha_change = 1;
2415                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
2416         }
2417
2418         if (u->plane_info->global_alpha_value != u->surface->global_alpha_value) {
2419                 update_flags->bits.global_alpha_change = 1;
2420                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
2421         }
2422
2423         if (u->plane_info->dcc.enable != u->surface->dcc.enable
2424                         || u->plane_info->dcc.dcc_ind_blk != u->surface->dcc.dcc_ind_blk
2425                         || u->plane_info->dcc.meta_pitch != u->surface->dcc.meta_pitch) {
2426                 /* During DCC on/off, stutter period is calculated before
2427                  * DCC has fully transitioned. This results in incorrect
2428                  * stutter period calculation. Triggering a full update will
2429                  * recalculate stutter period.
2430                  */
2431                 update_flags->bits.dcc_change = 1;
2432                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
2433         }
2434
2435         if (resource_pixel_format_to_bpp(u->plane_info->format) !=
2436                         resource_pixel_format_to_bpp(u->surface->format)) {
2437                 /* different bytes per element will require full bandwidth
2438                  * and DML calculation
2439                  */
2440                 update_flags->bits.bpp_change = 1;
2441                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
2442         }
2443
2444         if (u->plane_info->plane_size.surface_pitch != u->surface->plane_size.surface_pitch
2445                         || u->plane_info->plane_size.chroma_pitch != u->surface->plane_size.chroma_pitch) {
2446                 update_flags->bits.plane_size_change = 1;
2447                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
2448         }
2449
2450
2451         if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info,
2452                         sizeof(union dc_tiling_info)) != 0) {
2453                 update_flags->bits.swizzle_change = 1;
2454                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
2455
2456                 /* todo: below are HW dependent, we should add a hook to
2457                  * DCE/N resource and validated there.
2458                  */
2459                 if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR) {
2460                         /* swizzled mode requires RQ to be setup properly,
2461                          * thus need to run DML to calculate RQ settings
2462                          */
2463                         update_flags->bits.bandwidth_change = 1;
2464                         elevate_update_type(&update_type, UPDATE_TYPE_FULL);
2465                 }
2466         }
2467
2468         /* This should be UPDATE_TYPE_FAST if nothing has changed. */
2469         return update_type;
2470 }
2471
2472 static enum surface_update_type get_scaling_info_update_type(
2473                 const struct dc_surface_update *u)
2474 {
2475         union surface_update_flags *update_flags = &u->surface->update_flags;
2476
2477         if (!u->scaling_info)
2478                 return UPDATE_TYPE_FAST;
2479
2480         if (u->scaling_info->clip_rect.width != u->surface->clip_rect.width
2481                         || u->scaling_info->clip_rect.height != u->surface->clip_rect.height
2482                         || u->scaling_info->dst_rect.width != u->surface->dst_rect.width
2483                         || u->scaling_info->dst_rect.height != u->surface->dst_rect.height
2484                         || u->scaling_info->scaling_quality.integer_scaling !=
2485                                 u->surface->scaling_quality.integer_scaling
2486                         ) {
2487                 update_flags->bits.scaling_change = 1;
2488
2489                 if ((u->scaling_info->dst_rect.width < u->surface->dst_rect.width
2490                         || u->scaling_info->dst_rect.height < u->surface->dst_rect.height)
2491                                 && (u->scaling_info->dst_rect.width < u->surface->src_rect.width
2492                                         || u->scaling_info->dst_rect.height < u->surface->src_rect.height))
2493                         /* Making dst rect smaller requires a bandwidth change */
2494                         update_flags->bits.bandwidth_change = 1;
2495         }
2496
2497         if (u->scaling_info->src_rect.width != u->surface->src_rect.width
2498                 || u->scaling_info->src_rect.height != u->surface->src_rect.height) {
2499
2500                 update_flags->bits.scaling_change = 1;
2501                 if (u->scaling_info->src_rect.width > u->surface->src_rect.width
2502                                 || u->scaling_info->src_rect.height > u->surface->src_rect.height)
2503                         /* Making src rect bigger requires a bandwidth change */
2504                         update_flags->bits.clock_change = 1;
2505         }
2506
2507         if (u->scaling_info->src_rect.x != u->surface->src_rect.x
2508                         || u->scaling_info->src_rect.y != u->surface->src_rect.y
2509                         || u->scaling_info->clip_rect.x != u->surface->clip_rect.x
2510                         || u->scaling_info->clip_rect.y != u->surface->clip_rect.y
2511                         || u->scaling_info->dst_rect.x != u->surface->dst_rect.x
2512                         || u->scaling_info->dst_rect.y != u->surface->dst_rect.y)
2513                 update_flags->bits.position_change = 1;
2514
2515         if (update_flags->bits.clock_change
2516                         || update_flags->bits.bandwidth_change
2517                         || update_flags->bits.scaling_change)
2518                 return UPDATE_TYPE_FULL;
2519
2520         if (update_flags->bits.position_change)
2521                 return UPDATE_TYPE_MED;
2522
2523         return UPDATE_TYPE_FAST;
2524 }
2525
2526 static enum surface_update_type det_surface_update(const struct dc *dc,
2527                 const struct dc_surface_update *u)
2528 {
2529         const struct dc_state *context = dc->current_state;
2530         enum surface_update_type type;
2531         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
2532         union surface_update_flags *update_flags = &u->surface->update_flags;
2533
2534         if (!is_surface_in_context(context, u->surface) || u->surface->force_full_update) {
2535                 update_flags->raw = 0xFFFFFFFF;
2536                 return UPDATE_TYPE_FULL;
2537         }
2538
2539         update_flags->raw = 0; // Reset all flags
2540
2541         type = get_plane_info_update_type(u);
2542         elevate_update_type(&overall_type, type);
2543
2544         type = get_scaling_info_update_type(u);
2545         elevate_update_type(&overall_type, type);
2546
2547         if (u->flip_addr) {
2548                 update_flags->bits.addr_update = 1;
2549                 if (u->flip_addr->address.tmz_surface != u->surface->address.tmz_surface) {
2550                         update_flags->bits.tmz_changed = 1;
2551                         elevate_update_type(&overall_type, UPDATE_TYPE_FULL);
2552                 }
2553         }
2554         if (u->in_transfer_func)
2555                 update_flags->bits.in_transfer_func_change = 1;
2556
2557         if (u->input_csc_color_matrix)
2558                 update_flags->bits.input_csc_change = 1;
2559
2560         if (u->coeff_reduction_factor)
2561                 update_flags->bits.coeff_reduction_change = 1;
2562
2563         if (u->gamut_remap_matrix)
2564                 update_flags->bits.gamut_remap_change = 1;
2565
2566         if (u->gamma) {
2567                 enum surface_pixel_format format = SURFACE_PIXEL_FORMAT_GRPH_BEGIN;
2568
2569                 if (u->plane_info)
2570                         format = u->plane_info->format;
2571                 else if (u->surface)
2572                         format = u->surface->format;
2573
2574                 if (dce_use_lut(format))
2575                         update_flags->bits.gamma_change = 1;
2576         }
2577
2578         if (u->lut3d_func || u->func_shaper)
2579                 update_flags->bits.lut_3d = 1;
2580
2581         if (u->hdr_mult.value)
2582                 if (u->hdr_mult.value != u->surface->hdr_mult.value) {
2583                         update_flags->bits.hdr_mult = 1;
2584                         elevate_update_type(&overall_type, UPDATE_TYPE_MED);
2585                 }
2586
2587         if (update_flags->bits.in_transfer_func_change) {
2588                 type = UPDATE_TYPE_MED;
2589                 elevate_update_type(&overall_type, type);
2590         }
2591
2592         if (update_flags->bits.lut_3d) {
2593                 type = UPDATE_TYPE_FULL;
2594                 elevate_update_type(&overall_type, type);
2595         }
2596
2597         if (dc->debug.enable_legacy_fast_update &&
2598                         (update_flags->bits.gamma_change ||
2599                         update_flags->bits.gamut_remap_change ||
2600                         update_flags->bits.input_csc_change ||
2601                         update_flags->bits.coeff_reduction_change)) {
2602                 type = UPDATE_TYPE_FULL;
2603                 elevate_update_type(&overall_type, type);
2604         }
2605         return overall_type;
2606 }
2607
2608 static enum surface_update_type check_update_surfaces_for_stream(
2609                 struct dc *dc,
2610                 struct dc_surface_update *updates,
2611                 int surface_count,
2612                 struct dc_stream_update *stream_update,
2613                 const struct dc_stream_status *stream_status)
2614 {
2615         int i;
2616         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
2617
2618         if (dc->idle_optimizations_allowed)
2619                 overall_type = UPDATE_TYPE_FULL;
2620
2621         if (stream_status == NULL || stream_status->plane_count != surface_count)
2622                 overall_type = UPDATE_TYPE_FULL;
2623
2624         if (stream_update && stream_update->pending_test_pattern) {
2625                 overall_type = UPDATE_TYPE_FULL;
2626         }
2627
2628         /* some stream updates require passive update */
2629         if (stream_update) {
2630                 union stream_update_flags *su_flags = &stream_update->stream->update_flags;
2631
2632                 if ((stream_update->src.height != 0 && stream_update->src.width != 0) ||
2633                         (stream_update->dst.height != 0 && stream_update->dst.width != 0) ||
2634                         stream_update->integer_scaling_update)
2635                         su_flags->bits.scaling = 1;
2636
2637                 if (dc->debug.enable_legacy_fast_update && stream_update->out_transfer_func)
2638                         su_flags->bits.out_tf = 1;
2639
2640                 if (stream_update->abm_level)
2641                         su_flags->bits.abm_level = 1;
2642
2643                 if (stream_update->dpms_off)
2644                         su_flags->bits.dpms_off = 1;
2645
2646                 if (stream_update->gamut_remap)
2647                         su_flags->bits.gamut_remap = 1;
2648
2649                 if (stream_update->wb_update)
2650                         su_flags->bits.wb_update = 1;
2651
2652                 if (stream_update->dsc_config)
2653                         su_flags->bits.dsc_changed = 1;
2654
2655                 if (stream_update->mst_bw_update)
2656                         su_flags->bits.mst_bw = 1;
2657
2658                 if (stream_update->stream && stream_update->stream->freesync_on_desktop &&
2659                         (stream_update->vrr_infopacket || stream_update->allow_freesync ||
2660                                 stream_update->vrr_active_variable || stream_update->vrr_active_fixed))
2661                         su_flags->bits.fams_changed = 1;
2662
2663                 if (su_flags->raw != 0)
2664                         overall_type = UPDATE_TYPE_FULL;
2665
2666                 if (stream_update->output_csc_transform || stream_update->output_color_space)
2667                         su_flags->bits.out_csc = 1;
2668
2669                 /* Output transfer function changes do not require bandwidth recalculation,
2670                  * so don't trigger a full update
2671                  */
2672                 if (!dc->debug.enable_legacy_fast_update && stream_update->out_transfer_func)
2673                         su_flags->bits.out_tf = 1;
2674         }
2675
2676         for (i = 0 ; i < surface_count; i++) {
2677                 enum surface_update_type type =
2678                                 det_surface_update(dc, &updates[i]);
2679
2680                 elevate_update_type(&overall_type, type);
2681         }
2682
2683         return overall_type;
2684 }
2685
2686 static bool dc_check_is_fullscreen_video(struct rect src, struct rect clip_rect)
2687 {
2688         int view_height, view_width, clip_x, clip_y, clip_width, clip_height;
2689
2690         view_height = src.height;
2691         view_width = src.width;
2692
2693         clip_x = clip_rect.x;
2694         clip_y = clip_rect.y;
2695
2696         clip_width = clip_rect.width;
2697         clip_height = clip_rect.height;
2698
2699         /* check for centered video accounting for off by 1 scaling truncation */
2700         if ((view_height - clip_y - clip_height <= clip_y + 1) &&
2701                         (view_width - clip_x - clip_width <= clip_x + 1) &&
2702                         (view_height - clip_y - clip_height >= clip_y - 1) &&
2703                         (view_width - clip_x - clip_width >= clip_x - 1)) {
2704
2705                 /* when OS scales up/down to letter box, it may end up
2706                  * with few blank pixels on the border due to truncating.
2707                  * Add offset margin to account for this
2708                  */
2709                 if (clip_x <= 4 || clip_y <= 4)
2710                         return true;
2711         }
2712
2713         return false;
2714 }
2715
2716 static enum surface_update_type check_boundary_crossing_for_windowed_mpo_with_odm(struct dc *dc,
2717                 struct dc_surface_update *srf_updates, int surface_count,
2718                 enum surface_update_type update_type)
2719 {
2720         enum surface_update_type new_update_type = update_type;
2721         int i, j;
2722         struct pipe_ctx *pipe = NULL;
2723         struct dc_stream_state *stream;
2724
2725         /* Check that we are in windowed MPO with ODM
2726          * - look for MPO pipe by scanning pipes for first pipe matching
2727          *   surface that has moved ( position change )
2728          * - MPO pipe will have top pipe
2729          * - check that top pipe has ODM pointer
2730          */
2731         if ((surface_count > 1) && dc->config.enable_windowed_mpo_odm) {
2732                 for (i = 0; i < surface_count; i++) {
2733                         if (srf_updates[i].surface && srf_updates[i].scaling_info
2734                                         && srf_updates[i].surface->update_flags.bits.position_change) {
2735
2736                                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2737                                         if (srf_updates[i].surface == dc->current_state->res_ctx.pipe_ctx[j].plane_state) {
2738                                                 pipe = &dc->current_state->res_ctx.pipe_ctx[j];
2739                                                 stream = pipe->stream;
2740                                                 break;
2741                                         }
2742                                 }
2743
2744                                 if (pipe && pipe->top_pipe && (get_num_odm_splits(pipe->top_pipe) > 0) && stream
2745                                                 && !dc_check_is_fullscreen_video(stream->src, srf_updates[i].scaling_info->clip_rect)) {
2746                                         struct rect old_clip_rect, new_clip_rect;
2747                                         bool old_clip_rect_left, old_clip_rect_right, old_clip_rect_middle;
2748                                         bool new_clip_rect_left, new_clip_rect_right, new_clip_rect_middle;
2749
2750                                         old_clip_rect = srf_updates[i].surface->clip_rect;
2751                                         new_clip_rect = srf_updates[i].scaling_info->clip_rect;
2752
2753                                         old_clip_rect_left = ((old_clip_rect.x + old_clip_rect.width) <= (stream->src.x + (stream->src.width/2)));
2754                                         old_clip_rect_right = (old_clip_rect.x >= (stream->src.x + (stream->src.width/2)));
2755                                         old_clip_rect_middle = !old_clip_rect_left && !old_clip_rect_right;
2756
2757                                         new_clip_rect_left = ((new_clip_rect.x + new_clip_rect.width) <= (stream->src.x + (stream->src.width/2)));
2758                                         new_clip_rect_right = (new_clip_rect.x >= (stream->src.x + (stream->src.width/2)));
2759                                         new_clip_rect_middle = !new_clip_rect_left && !new_clip_rect_right;
2760
2761                                         if (old_clip_rect_left && new_clip_rect_middle)
2762                                                 new_update_type = UPDATE_TYPE_FULL;
2763                                         else if (old_clip_rect_middle && new_clip_rect_right)
2764                                                 new_update_type = UPDATE_TYPE_FULL;
2765                                         else if (old_clip_rect_right && new_clip_rect_middle)
2766                                                 new_update_type = UPDATE_TYPE_FULL;
2767                                         else if (old_clip_rect_middle && new_clip_rect_left)
2768                                                 new_update_type = UPDATE_TYPE_FULL;
2769                                 }
2770                         }
2771                 }
2772         }
2773         return new_update_type;
2774 }
2775
2776 /*
2777  * dc_check_update_surfaces_for_stream() - Determine update type (fast, med, or full)
2778  *
2779  * See :c:type:`enum surface_update_type <surface_update_type>` for explanation of update types
2780  */
2781 enum surface_update_type dc_check_update_surfaces_for_stream(
2782                 struct dc *dc,
2783                 struct dc_surface_update *updates,
2784                 int surface_count,
2785                 struct dc_stream_update *stream_update,
2786                 const struct dc_stream_status *stream_status)
2787 {
2788         int i;
2789         enum surface_update_type type;
2790
2791         if (stream_update)
2792                 stream_update->stream->update_flags.raw = 0;
2793         for (i = 0; i < surface_count; i++)
2794                 updates[i].surface->update_flags.raw = 0;
2795
2796         type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status);
2797         if (type == UPDATE_TYPE_FULL) {
2798                 if (stream_update) {
2799                         uint32_t dsc_changed = stream_update->stream->update_flags.bits.dsc_changed;
2800                         stream_update->stream->update_flags.raw = 0xFFFFFFFF;
2801                         stream_update->stream->update_flags.bits.dsc_changed = dsc_changed;
2802                 }
2803                 for (i = 0; i < surface_count; i++)
2804                         updates[i].surface->update_flags.raw = 0xFFFFFFFF;
2805         }
2806
2807         if (type == UPDATE_TYPE_MED)
2808                 type = check_boundary_crossing_for_windowed_mpo_with_odm(dc,
2809                                 updates, surface_count, type);
2810
2811         if (type == UPDATE_TYPE_FAST) {
2812                 // If there's an available clock comparator, we use that.
2813                 if (dc->clk_mgr->funcs->are_clock_states_equal) {
2814                         if (!dc->clk_mgr->funcs->are_clock_states_equal(&dc->clk_mgr->clks, &dc->current_state->bw_ctx.bw.dcn.clk))
2815                                 dc->optimized_required = true;
2816                 // Else we fallback to mem compare.
2817                 } else if (memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_clocks, prev_p_state_change_support)) != 0) {
2818                         dc->optimized_required = true;
2819                 }
2820
2821                 dc->optimized_required |= dc->wm_optimized_required;
2822         }
2823
2824         return type;
2825 }
2826
2827 static struct dc_stream_status *stream_get_status(
2828         struct dc_state *ctx,
2829         struct dc_stream_state *stream)
2830 {
2831         uint8_t i;
2832
2833         for (i = 0; i < ctx->stream_count; i++) {
2834                 if (stream == ctx->streams[i]) {
2835                         return &ctx->stream_status[i];
2836                 }
2837         }
2838
2839         return NULL;
2840 }
2841
2842 static const enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL;
2843
2844 static void copy_surface_update_to_plane(
2845                 struct dc_plane_state *surface,
2846                 struct dc_surface_update *srf_update)
2847 {
2848         if (srf_update->flip_addr) {
2849                 surface->address = srf_update->flip_addr->address;
2850                 surface->flip_immediate =
2851                         srf_update->flip_addr->flip_immediate;
2852                 surface->time.time_elapsed_in_us[surface->time.index] =
2853                         srf_update->flip_addr->flip_timestamp_in_us -
2854                                 surface->time.prev_update_time_in_us;
2855                 surface->time.prev_update_time_in_us =
2856                         srf_update->flip_addr->flip_timestamp_in_us;
2857                 surface->time.index++;
2858                 if (surface->time.index >= DC_PLANE_UPDATE_TIMES_MAX)
2859                         surface->time.index = 0;
2860
2861                 surface->triplebuffer_flips = srf_update->flip_addr->triplebuffer_flips;
2862         }
2863
2864         if (srf_update->scaling_info) {
2865                 surface->scaling_quality =
2866                                 srf_update->scaling_info->scaling_quality;
2867                 surface->dst_rect =
2868                                 srf_update->scaling_info->dst_rect;
2869                 surface->src_rect =
2870                                 srf_update->scaling_info->src_rect;
2871                 surface->clip_rect =
2872                                 srf_update->scaling_info->clip_rect;
2873         }
2874
2875         if (srf_update->plane_info) {
2876                 surface->color_space =
2877                                 srf_update->plane_info->color_space;
2878                 surface->format =
2879                                 srf_update->plane_info->format;
2880                 surface->plane_size =
2881                                 srf_update->plane_info->plane_size;
2882                 surface->rotation =
2883                                 srf_update->plane_info->rotation;
2884                 surface->horizontal_mirror =
2885                                 srf_update->plane_info->horizontal_mirror;
2886                 surface->stereo_format =
2887                                 srf_update->plane_info->stereo_format;
2888                 surface->tiling_info =
2889                                 srf_update->plane_info->tiling_info;
2890                 surface->visible =
2891                                 srf_update->plane_info->visible;
2892                 surface->per_pixel_alpha =
2893                                 srf_update->plane_info->per_pixel_alpha;
2894                 surface->global_alpha =
2895                                 srf_update->plane_info->global_alpha;
2896                 surface->global_alpha_value =
2897                                 srf_update->plane_info->global_alpha_value;
2898                 surface->dcc =
2899                                 srf_update->plane_info->dcc;
2900                 surface->layer_index =
2901                                 srf_update->plane_info->layer_index;
2902         }
2903
2904         if (srf_update->gamma &&
2905                         (surface->gamma_correction !=
2906                                         srf_update->gamma)) {
2907                 memcpy(&surface->gamma_correction->entries,
2908                         &srf_update->gamma->entries,
2909                         sizeof(struct dc_gamma_entries));
2910                 surface->gamma_correction->is_identity =
2911                         srf_update->gamma->is_identity;
2912                 surface->gamma_correction->num_entries =
2913                         srf_update->gamma->num_entries;
2914                 surface->gamma_correction->type =
2915                         srf_update->gamma->type;
2916         }
2917
2918         if (srf_update->in_transfer_func &&
2919                         (surface->in_transfer_func !=
2920                                 srf_update->in_transfer_func)) {
2921                 surface->in_transfer_func->sdr_ref_white_level =
2922                         srf_update->in_transfer_func->sdr_ref_white_level;
2923                 surface->in_transfer_func->tf =
2924                         srf_update->in_transfer_func->tf;
2925                 surface->in_transfer_func->type =
2926                         srf_update->in_transfer_func->type;
2927                 memcpy(&surface->in_transfer_func->tf_pts,
2928                         &srf_update->in_transfer_func->tf_pts,
2929                         sizeof(struct dc_transfer_func_distributed_points));
2930         }
2931
2932         if (srf_update->func_shaper &&
2933                         (surface->in_shaper_func !=
2934                         srf_update->func_shaper))
2935                 memcpy(surface->in_shaper_func, srf_update->func_shaper,
2936                 sizeof(*surface->in_shaper_func));
2937
2938         if (srf_update->lut3d_func &&
2939                         (surface->lut3d_func !=
2940                         srf_update->lut3d_func))
2941                 memcpy(surface->lut3d_func, srf_update->lut3d_func,
2942                 sizeof(*surface->lut3d_func));
2943
2944         if (srf_update->hdr_mult.value)
2945                 surface->hdr_mult =
2946                                 srf_update->hdr_mult;
2947
2948         if (srf_update->blend_tf &&
2949                         (surface->blend_tf !=
2950                         srf_update->blend_tf))
2951                 memcpy(surface->blend_tf, srf_update->blend_tf,
2952                 sizeof(*surface->blend_tf));
2953
2954         if (srf_update->input_csc_color_matrix)
2955                 surface->input_csc_color_matrix =
2956                         *srf_update->input_csc_color_matrix;
2957
2958         if (srf_update->coeff_reduction_factor)
2959                 surface->coeff_reduction_factor =
2960                         *srf_update->coeff_reduction_factor;
2961
2962         if (srf_update->gamut_remap_matrix)
2963                 surface->gamut_remap_matrix =
2964                         *srf_update->gamut_remap_matrix;
2965 }
2966
2967 static void copy_stream_update_to_stream(struct dc *dc,
2968                                          struct dc_state *context,
2969                                          struct dc_stream_state *stream,
2970                                          struct dc_stream_update *update)
2971 {
2972         struct dc_context *dc_ctx = dc->ctx;
2973
2974         if (update == NULL || stream == NULL)
2975                 return;
2976
2977         if (update->src.height && update->src.width)
2978                 stream->src = update->src;
2979
2980         if (update->dst.height && update->dst.width)
2981                 stream->dst = update->dst;
2982
2983         if (update->out_transfer_func &&
2984             stream->out_transfer_func != update->out_transfer_func) {
2985                 stream->out_transfer_func->sdr_ref_white_level =
2986                         update->out_transfer_func->sdr_ref_white_level;
2987                 stream->out_transfer_func->tf = update->out_transfer_func->tf;
2988                 stream->out_transfer_func->type =
2989                         update->out_transfer_func->type;
2990                 memcpy(&stream->out_transfer_func->tf_pts,
2991                        &update->out_transfer_func->tf_pts,
2992                        sizeof(struct dc_transfer_func_distributed_points));
2993         }
2994
2995         if (update->hdr_static_metadata)
2996                 stream->hdr_static_metadata = *update->hdr_static_metadata;
2997
2998         if (update->abm_level)
2999                 stream->abm_level = *update->abm_level;
3000
3001         if (update->periodic_interrupt)
3002                 stream->periodic_interrupt = *update->periodic_interrupt;
3003
3004         if (update->gamut_remap)
3005                 stream->gamut_remap_matrix = *update->gamut_remap;
3006
3007         /* Note: this being updated after mode set is currently not a use case
3008          * however if it arises OCSC would need to be reprogrammed at the
3009          * minimum
3010          */
3011         if (update->output_color_space)
3012                 stream->output_color_space = *update->output_color_space;
3013
3014         if (update->output_csc_transform)
3015                 stream->csc_color_matrix = *update->output_csc_transform;
3016
3017         if (update->vrr_infopacket)
3018                 stream->vrr_infopacket = *update->vrr_infopacket;
3019
3020         if (update->allow_freesync)
3021                 stream->allow_freesync = *update->allow_freesync;
3022
3023         if (update->vrr_active_variable)
3024                 stream->vrr_active_variable = *update->vrr_active_variable;
3025
3026         if (update->vrr_active_fixed)
3027                 stream->vrr_active_fixed = *update->vrr_active_fixed;
3028
3029         if (update->crtc_timing_adjust)
3030                 stream->adjust = *update->crtc_timing_adjust;
3031
3032         if (update->dpms_off)
3033                 stream->dpms_off = *update->dpms_off;
3034
3035         if (update->hfvsif_infopacket)
3036                 stream->hfvsif_infopacket = *update->hfvsif_infopacket;
3037
3038         if (update->vtem_infopacket)
3039                 stream->vtem_infopacket = *update->vtem_infopacket;
3040
3041         if (update->vsc_infopacket)
3042                 stream->vsc_infopacket = *update->vsc_infopacket;
3043
3044         if (update->vsp_infopacket)
3045                 stream->vsp_infopacket = *update->vsp_infopacket;
3046
3047         if (update->adaptive_sync_infopacket)
3048                 stream->adaptive_sync_infopacket = *update->adaptive_sync_infopacket;
3049
3050         if (update->dither_option)
3051                 stream->dither_option = *update->dither_option;
3052
3053         if (update->pending_test_pattern)
3054                 stream->test_pattern = *update->pending_test_pattern;
3055         /* update current stream with writeback info */
3056         if (update->wb_update) {
3057                 int i;
3058
3059                 stream->num_wb_info = update->wb_update->num_wb_info;
3060                 ASSERT(stream->num_wb_info <= MAX_DWB_PIPES);
3061                 for (i = 0; i < stream->num_wb_info; i++)
3062                         stream->writeback_info[i] =
3063                                 update->wb_update->writeback_info[i];
3064         }
3065         if (update->dsc_config) {
3066                 struct dc_dsc_config old_dsc_cfg = stream->timing.dsc_cfg;
3067                 uint32_t old_dsc_enabled = stream->timing.flags.DSC;
3068                 uint32_t enable_dsc = (update->dsc_config->num_slices_h != 0 &&
3069                                        update->dsc_config->num_slices_v != 0);
3070
3071                 /* Use temporarry context for validating new DSC config */
3072                 struct dc_state *dsc_validate_context = dc_create_state(dc);
3073
3074                 if (dsc_validate_context) {
3075                         dc_resource_state_copy_construct(dc->current_state, dsc_validate_context);
3076
3077                         stream->timing.dsc_cfg = *update->dsc_config;
3078                         stream->timing.flags.DSC = enable_dsc;
3079                         if (!dc->res_pool->funcs->validate_bandwidth(dc, dsc_validate_context, true)) {
3080                                 stream->timing.dsc_cfg = old_dsc_cfg;
3081                                 stream->timing.flags.DSC = old_dsc_enabled;
3082                                 update->dsc_config = NULL;
3083                         }
3084
3085                         dc_release_state(dsc_validate_context);
3086                 } else {
3087                         DC_ERROR("Failed to allocate new validate context for DSC change\n");
3088                         update->dsc_config = NULL;
3089                 }
3090         }
3091 }
3092
3093 static bool update_planes_and_stream_state(struct dc *dc,
3094                 struct dc_surface_update *srf_updates, int surface_count,
3095                 struct dc_stream_state *stream,
3096                 struct dc_stream_update *stream_update,
3097                 enum surface_update_type *new_update_type,
3098                 struct dc_state **new_context)
3099 {
3100         struct dc_state *context;
3101         int i, j;
3102         enum surface_update_type update_type;
3103         const struct dc_stream_status *stream_status;
3104         struct dc_context *dc_ctx = dc->ctx;
3105
3106         stream_status = dc_stream_get_status(stream);
3107
3108         if (!stream_status) {
3109                 if (surface_count) /* Only an error condition if surf_count non-zero*/
3110                         ASSERT(false);
3111
3112                 return false; /* Cannot commit surface to stream that is not committed */
3113         }
3114
3115         context = dc->current_state;
3116
3117         update_type = dc_check_update_surfaces_for_stream(
3118                         dc, srf_updates, surface_count, stream_update, stream_status);
3119
3120         /* update current stream with the new updates */
3121         copy_stream_update_to_stream(dc, context, stream, stream_update);
3122
3123         /* do not perform surface update if surface has invalid dimensions
3124          * (all zero) and no scaling_info is provided
3125          */
3126         if (surface_count > 0) {
3127                 for (i = 0; i < surface_count; i++) {
3128                         if ((srf_updates[i].surface->src_rect.width == 0 ||
3129                                  srf_updates[i].surface->src_rect.height == 0 ||
3130                                  srf_updates[i].surface->dst_rect.width == 0 ||
3131                                  srf_updates[i].surface->dst_rect.height == 0) &&
3132                                 (!srf_updates[i].scaling_info ||
3133                                   srf_updates[i].scaling_info->src_rect.width == 0 ||
3134                                   srf_updates[i].scaling_info->src_rect.height == 0 ||
3135                                   srf_updates[i].scaling_info->dst_rect.width == 0 ||
3136                                   srf_updates[i].scaling_info->dst_rect.height == 0)) {
3137                                 DC_ERROR("Invalid src/dst rects in surface update!\n");
3138                                 return false;
3139                         }
3140                 }
3141         }
3142
3143         if (update_type >= update_surface_trace_level)
3144                 update_surface_trace(dc, srf_updates, surface_count);
3145
3146         if (update_type >= UPDATE_TYPE_FULL) {
3147                 struct dc_plane_state *new_planes[MAX_SURFACES] = {0};
3148
3149                 for (i = 0; i < surface_count; i++)
3150                         new_planes[i] = srf_updates[i].surface;
3151
3152                 /* initialize scratch memory for building context */
3153                 context = dc_create_state(dc);
3154                 if (context == NULL) {
3155                         DC_ERROR("Failed to allocate new validate context!\n");
3156                         return false;
3157                 }
3158
3159                 dc_resource_state_copy_construct(
3160                                 dc->current_state, context);
3161
3162                 /* For each full update, remove all existing phantom pipes first.
3163                  * Ensures that we have enough pipes for newly added MPO planes
3164                  */
3165                 if (dc->res_pool->funcs->remove_phantom_pipes)
3166                         dc->res_pool->funcs->remove_phantom_pipes(dc, context, false);
3167
3168                 /*remove old surfaces from context */
3169                 if (!dc_rem_all_planes_for_stream(dc, stream, context)) {
3170
3171                         BREAK_TO_DEBUGGER();
3172                         goto fail;
3173                 }
3174
3175                 /* add surface to context */
3176                 if (!dc_add_all_planes_for_stream(dc, stream, new_planes, surface_count, context)) {
3177
3178                         BREAK_TO_DEBUGGER();
3179                         goto fail;
3180                 }
3181         }
3182
3183         /* save update parameters into surface */
3184         for (i = 0; i < surface_count; i++) {
3185                 struct dc_plane_state *surface = srf_updates[i].surface;
3186
3187                 copy_surface_update_to_plane(surface, &srf_updates[i]);
3188
3189                 if (update_type >= UPDATE_TYPE_MED) {
3190                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
3191                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3192
3193                                 if (pipe_ctx->plane_state != surface)
3194                                         continue;
3195
3196                                 resource_build_scaling_params(pipe_ctx);
3197                         }
3198                 }
3199         }
3200
3201         if (update_type == UPDATE_TYPE_FULL) {
3202                 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) {
3203                         /* For phantom pipes we remove and create a new set of phantom pipes
3204                          * for each full update (because we don't know if we'll need phantom
3205                          * pipes until after the first round of validation). However, if validation
3206                          * fails we need to keep the existing phantom pipes (because we don't update
3207                          * the dc->current_state).
3208                          *
3209                          * The phantom stream/plane refcount is decremented for validation because
3210                          * we assume it'll be removed (the free comes when the dc_state is freed),
3211                          * but if validation fails we have to increment back the refcount so it's
3212                          * consistent.
3213                          */
3214                         if (dc->res_pool->funcs->retain_phantom_pipes)
3215                                 dc->res_pool->funcs->retain_phantom_pipes(dc, dc->current_state);
3216                         BREAK_TO_DEBUGGER();
3217                         goto fail;
3218                 }
3219         }
3220
3221         *new_context = context;
3222         *new_update_type = update_type;
3223
3224         return true;
3225
3226 fail:
3227         dc_release_state(context);
3228
3229         return false;
3230
3231 }
3232
3233 static void commit_planes_do_stream_update(struct dc *dc,
3234                 struct dc_stream_state *stream,
3235                 struct dc_stream_update *stream_update,
3236                 enum surface_update_type update_type,
3237                 struct dc_state *context)
3238 {
3239         int j;
3240
3241         // Stream updates
3242         for (j = 0; j < dc->res_pool->pipe_count; j++) {
3243                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3244
3245                 if (!pipe_ctx->top_pipe &&  !pipe_ctx->prev_odm_pipe && pipe_ctx->stream == stream) {
3246
3247                         if (stream_update->periodic_interrupt && dc->hwss.setup_periodic_interrupt)
3248                                 dc->hwss.setup_periodic_interrupt(dc, pipe_ctx);
3249
3250                         if ((stream_update->hdr_static_metadata && !stream->use_dynamic_meta) ||
3251                                         stream_update->vrr_infopacket ||
3252                                         stream_update->vsc_infopacket ||
3253                                         stream_update->vsp_infopacket ||
3254                                         stream_update->hfvsif_infopacket ||
3255                                         stream_update->adaptive_sync_infopacket ||
3256                                         stream_update->vtem_infopacket) {
3257                                 resource_build_info_frame(pipe_ctx);
3258                                 dc->hwss.update_info_frame(pipe_ctx);
3259
3260                                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
3261                                         dc->link_srv->dp_trace_source_sequence(
3262                                                         pipe_ctx->stream->link,
3263                                                         DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME);
3264                         }
3265
3266                         if (stream_update->hdr_static_metadata &&
3267                                         stream->use_dynamic_meta &&
3268                                         dc->hwss.set_dmdata_attributes &&
3269                                         pipe_ctx->stream->dmdata_address.quad_part != 0)
3270                                 dc->hwss.set_dmdata_attributes(pipe_ctx);
3271
3272                         if (stream_update->gamut_remap)
3273                                 dc_stream_set_gamut_remap(dc, stream);
3274
3275                         if (stream_update->output_csc_transform)
3276                                 dc_stream_program_csc_matrix(dc, stream);
3277
3278                         if (stream_update->dither_option) {
3279                                 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
3280                                 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
3281                                                                         &pipe_ctx->stream->bit_depth_params);
3282                                 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(pipe_ctx->stream_res.opp,
3283                                                 &stream->bit_depth_params,
3284                                                 &stream->clamping);
3285                                 while (odm_pipe) {
3286                                         odm_pipe->stream_res.opp->funcs->opp_program_fmt(odm_pipe->stream_res.opp,
3287                                                         &stream->bit_depth_params,
3288                                                         &stream->clamping);
3289                                         odm_pipe = odm_pipe->next_odm_pipe;
3290                                 }
3291                         }
3292
3293
3294                         /* Full fe update*/
3295                         if (update_type == UPDATE_TYPE_FAST)
3296                                 continue;
3297
3298                         if (stream_update->dsc_config)
3299                                 dc->link_srv->update_dsc_config(pipe_ctx);
3300
3301                         if (stream_update->mst_bw_update) {
3302                                 if (stream_update->mst_bw_update->is_increase)
3303                                         dc->link_srv->increase_mst_payload(pipe_ctx,
3304                                                         stream_update->mst_bw_update->mst_stream_bw);
3305                                 else
3306                                         dc->link_srv->reduce_mst_payload(pipe_ctx,
3307                                                         stream_update->mst_bw_update->mst_stream_bw);
3308                         }
3309
3310                         if (stream_update->pending_test_pattern) {
3311                                 dc_link_dp_set_test_pattern(stream->link,
3312                                         stream->test_pattern.type,
3313                                         stream->test_pattern.color_space,
3314                                         stream->test_pattern.p_link_settings,
3315                                         stream->test_pattern.p_custom_pattern,
3316                                         stream->test_pattern.cust_pattern_size);
3317                         }
3318
3319                         if (stream_update->dpms_off) {
3320                                 if (*stream_update->dpms_off) {
3321                                         dc->link_srv->set_dpms_off(pipe_ctx);
3322                                         /* for dpms, keep acquired resources*/
3323                                         if (pipe_ctx->stream_res.audio && !dc->debug.az_endpoint_mute_only)
3324                                                 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
3325
3326                                         dc->optimized_required = true;
3327
3328                                 } else {
3329                                         if (get_seamless_boot_stream_count(context) == 0)
3330                                                 dc->hwss.prepare_bandwidth(dc, dc->current_state);
3331                                         dc->link_srv->set_dpms_on(dc->current_state, pipe_ctx);
3332                                 }
3333                         } else if (pipe_ctx->stream->link->wa_flags.blank_stream_on_ocs_change && stream_update->output_color_space
3334                                         && !stream->dpms_off && dc_is_dp_signal(pipe_ctx->stream->signal)) {
3335                                 /*
3336                                  * Workaround for firmware issue in some receivers where they don't pick up
3337                                  * correct output color space unless DP link is disabled/re-enabled
3338                                  */
3339                                 dc->link_srv->set_dpms_on(dc->current_state, pipe_ctx);
3340                         }
3341
3342                         if (stream_update->abm_level && pipe_ctx->stream_res.abm) {
3343                                 bool should_program_abm = true;
3344
3345                                 // if otg funcs defined check if blanked before programming
3346                                 if (pipe_ctx->stream_res.tg->funcs->is_blanked)
3347                                         if (pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg))
3348                                                 should_program_abm = false;
3349
3350                                 if (should_program_abm) {
3351                                         if (*stream_update->abm_level == ABM_LEVEL_IMMEDIATE_DISABLE) {
3352                                                 dc->hwss.set_abm_immediate_disable(pipe_ctx);
3353                                         } else {
3354                                                 pipe_ctx->stream_res.abm->funcs->set_abm_level(
3355                                                         pipe_ctx->stream_res.abm, stream->abm_level);
3356                                         }
3357                                 }
3358                         }
3359                 }
3360         }
3361 }
3362
3363 static bool dc_dmub_should_send_dirty_rect_cmd(struct dc *dc, struct dc_stream_state *stream)
3364 {
3365         if ((stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1
3366                         || stream->link->psr_settings.psr_version == DC_PSR_VERSION_1)
3367                         && stream->ctx->dce_version >= DCN_VERSION_3_1)
3368                 return true;
3369
3370         return false;
3371 }
3372
3373 void dc_dmub_update_dirty_rect(struct dc *dc,
3374                                int surface_count,
3375                                struct dc_stream_state *stream,
3376                                struct dc_surface_update *srf_updates,
3377                                struct dc_state *context)
3378 {
3379         union dmub_rb_cmd cmd;
3380         struct dmub_cmd_update_dirty_rect_data *update_dirty_rect;
3381         unsigned int i, j;
3382         unsigned int panel_inst = 0;
3383
3384         if (!dc_dmub_should_send_dirty_rect_cmd(dc, stream))
3385                 return;
3386
3387         if (!dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst))
3388                 return;
3389
3390         memset(&cmd, 0x0, sizeof(cmd));
3391         cmd.update_dirty_rect.header.type = DMUB_CMD__UPDATE_DIRTY_RECT;
3392         cmd.update_dirty_rect.header.sub_type = 0;
3393         cmd.update_dirty_rect.header.payload_bytes =
3394                 sizeof(cmd.update_dirty_rect) -
3395                 sizeof(cmd.update_dirty_rect.header);
3396         update_dirty_rect = &cmd.update_dirty_rect.update_dirty_rect_data;
3397         for (i = 0; i < surface_count; i++) {
3398                 struct dc_plane_state *plane_state = srf_updates[i].surface;
3399                 const struct dc_flip_addrs *flip_addr = srf_updates[i].flip_addr;
3400
3401                 if (!srf_updates[i].surface || !flip_addr)
3402                         continue;
3403                 /* Do not send in immediate flip mode */
3404                 if (srf_updates[i].surface->flip_immediate)
3405                         continue;
3406
3407                 update_dirty_rect->dirty_rect_count = flip_addr->dirty_rect_count;
3408                 memcpy(update_dirty_rect->src_dirty_rects, flip_addr->dirty_rects,
3409                                 sizeof(flip_addr->dirty_rects));
3410                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
3411                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3412
3413                         if (pipe_ctx->stream != stream)
3414                                 continue;
3415                         if (pipe_ctx->plane_state != plane_state)
3416                                 continue;
3417
3418                         update_dirty_rect->panel_inst = panel_inst;
3419                         update_dirty_rect->pipe_idx = j;
3420                         dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
3421                 }
3422         }
3423 }
3424
3425 static void build_dmub_update_dirty_rect(
3426                 struct dc *dc,
3427                 int surface_count,
3428                 struct dc_stream_state *stream,
3429                 struct dc_surface_update *srf_updates,
3430                 struct dc_state *context,
3431                 struct dc_dmub_cmd dc_dmub_cmd[],
3432                 unsigned int *dmub_cmd_count)
3433 {
3434         union dmub_rb_cmd cmd;
3435         struct dmub_cmd_update_dirty_rect_data *update_dirty_rect;
3436         unsigned int i, j;
3437         unsigned int panel_inst = 0;
3438
3439         if (!dc_dmub_should_send_dirty_rect_cmd(dc, stream))
3440                 return;
3441
3442         if (!dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst))
3443                 return;
3444
3445         memset(&cmd, 0x0, sizeof(cmd));
3446         cmd.update_dirty_rect.header.type = DMUB_CMD__UPDATE_DIRTY_RECT;
3447         cmd.update_dirty_rect.header.sub_type = 0;
3448         cmd.update_dirty_rect.header.payload_bytes =
3449                 sizeof(cmd.update_dirty_rect) -
3450                 sizeof(cmd.update_dirty_rect.header);
3451         update_dirty_rect = &cmd.update_dirty_rect.update_dirty_rect_data;
3452         for (i = 0; i < surface_count; i++) {
3453                 struct dc_plane_state *plane_state = srf_updates[i].surface;
3454                 const struct dc_flip_addrs *flip_addr = srf_updates[i].flip_addr;
3455
3456                 if (!srf_updates[i].surface || !flip_addr)
3457                         continue;
3458                 /* Do not send in immediate flip mode */
3459                 if (srf_updates[i].surface->flip_immediate)
3460                         continue;
3461                 update_dirty_rect->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
3462                 update_dirty_rect->dirty_rect_count = flip_addr->dirty_rect_count;
3463                 memcpy(update_dirty_rect->src_dirty_rects, flip_addr->dirty_rects,
3464                                 sizeof(flip_addr->dirty_rects));
3465                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
3466                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3467
3468                         if (pipe_ctx->stream != stream)
3469                                 continue;
3470                         if (pipe_ctx->plane_state != plane_state)
3471                                 continue;
3472                         update_dirty_rect->panel_inst = panel_inst;
3473                         update_dirty_rect->pipe_idx = j;
3474                         dc_dmub_cmd[*dmub_cmd_count].dmub_cmd = cmd;
3475                         dc_dmub_cmd[*dmub_cmd_count].wait_type = DM_DMUB_WAIT_TYPE_NO_WAIT;
3476                         (*dmub_cmd_count)++;
3477                 }
3478         }
3479 }
3480
3481
3482 /**
3483  * ************************************************************************************************
3484  * build_dmub_cmd_list: Build an array of DMCUB commands to be sent to DMCUB
3485  *
3486  * @param [in]: dc: Current DC state
3487  * @param [in]: srf_updates: Array of surface updates
3488  * @param [in]: surface_count: Number of surfaces that have an updated
3489  * @param [in]: stream: Correponding stream to be updated in the current flip
3490  * @param [in]: context: New DC state to be programmed
3491  *
3492  * @param [out]: dc_dmub_cmd: Array of DMCUB commands to be sent to DMCUB
3493  * @param [out]: dmub_cmd_count: Count indicating the number of DMCUB commands in dc_dmub_cmd array
3494  *
3495  * This function builds an array of DMCUB commands to be sent to DMCUB. This function is required
3496  * to build an array of commands and have them sent while the OTG lock is acquired.
3497  *
3498  * @return: void
3499  * ************************************************************************************************
3500  */
3501 static void build_dmub_cmd_list(struct dc *dc,
3502                 struct dc_surface_update *srf_updates,
3503                 int surface_count,
3504                 struct dc_stream_state *stream,
3505                 struct dc_state *context,
3506                 struct dc_dmub_cmd dc_dmub_cmd[],
3507                 unsigned int *dmub_cmd_count)
3508 {
3509         // Initialize cmd count to 0
3510         *dmub_cmd_count = 0;
3511         build_dmub_update_dirty_rect(dc, surface_count, stream, srf_updates, context, dc_dmub_cmd, dmub_cmd_count);
3512 }
3513
3514 static void commit_planes_for_stream_fast(struct dc *dc,
3515                 struct dc_surface_update *srf_updates,
3516                 int surface_count,
3517                 struct dc_stream_state *stream,
3518                 struct dc_stream_update *stream_update,
3519                 enum surface_update_type update_type,
3520                 struct dc_state *context)
3521 {
3522         int i, j;
3523         struct pipe_ctx *top_pipe_to_program = NULL;
3524         dc_z10_restore(dc);
3525
3526         for (j = 0; j < dc->res_pool->pipe_count; j++) {
3527                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3528
3529                 if (!pipe_ctx->top_pipe &&
3530                         !pipe_ctx->prev_odm_pipe &&
3531                         pipe_ctx->stream &&
3532                         pipe_ctx->stream == stream) {
3533                         top_pipe_to_program = pipe_ctx;
3534                 }
3535         }
3536
3537         if (dc->debug.visual_confirm) {
3538                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
3539                         struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
3540
3541                         if (pipe->stream && pipe->plane_state)
3542                                 dc_update_viusal_confirm_color(dc, context, pipe);
3543                 }
3544         }
3545
3546         for (i = 0; i < surface_count; i++) {
3547                 struct dc_plane_state *plane_state = srf_updates[i].surface;
3548                 /*set logical flag for lock/unlock use*/
3549                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
3550                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3551
3552                         if (!pipe_ctx->plane_state)
3553                                 continue;
3554                         if (should_update_pipe_for_plane(context, pipe_ctx, plane_state))
3555                                 continue;
3556                         pipe_ctx->plane_state->triplebuffer_flips = false;
3557                         if (update_type == UPDATE_TYPE_FAST &&
3558                             dc->hwss.program_triplebuffer &&
3559                             !pipe_ctx->plane_state->flip_immediate && dc->debug.enable_tri_buf) {
3560                                 /*triple buffer for VUpdate  only*/
3561                                 pipe_ctx->plane_state->triplebuffer_flips = true;
3562                         }
3563                 }
3564         }
3565
3566         build_dmub_cmd_list(dc,
3567                         srf_updates,
3568                         surface_count,
3569                         stream,
3570                         context,
3571                         context->dc_dmub_cmd,
3572                         &(context->dmub_cmd_count));
3573         hwss_build_fast_sequence(dc,
3574                         context->dc_dmub_cmd,
3575                         context->dmub_cmd_count,
3576                         context->block_sequence,
3577                         &(context->block_sequence_steps),
3578                         top_pipe_to_program);
3579         hwss_execute_sequence(dc,
3580                         context->block_sequence,
3581                         context->block_sequence_steps);
3582 }
3583
3584 static void commit_planes_for_stream(struct dc *dc,
3585                 struct dc_surface_update *srf_updates,
3586                 int surface_count,
3587                 struct dc_stream_state *stream,
3588                 struct dc_stream_update *stream_update,
3589                 enum surface_update_type update_type,
3590                 struct dc_state *context)
3591 {
3592         int i, j;
3593         struct pipe_ctx *top_pipe_to_program = NULL;
3594         bool should_lock_all_pipes = (update_type != UPDATE_TYPE_FAST);
3595         bool subvp_prev_use = false;
3596         bool subvp_curr_use = false;
3597
3598         // Once we apply the new subvp context to hardware it won't be in the
3599         // dc->current_state anymore, so we have to cache it before we apply
3600         // the new SubVP context
3601         subvp_prev_use = false;
3602
3603
3604         dc_z10_restore(dc);
3605
3606         if (update_type == UPDATE_TYPE_FULL) {
3607                 /* wait for all double-buffer activity to clear on all pipes */
3608                 int pipe_idx;
3609
3610                 for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) {
3611                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
3612
3613                         if (!pipe_ctx->stream)
3614                                 continue;
3615
3616                         if (pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear)
3617                                 pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear(pipe_ctx->stream_res.tg);
3618                 }
3619         }
3620
3621         if (update_type == UPDATE_TYPE_FULL) {
3622                 dc_allow_idle_optimizations(dc, false);
3623
3624                 if (get_seamless_boot_stream_count(context) == 0)
3625                         dc->hwss.prepare_bandwidth(dc, context);
3626
3627                 if (dc->debug.enable_double_buffered_dsc_pg_support)
3628                         dc->hwss.update_dsc_pg(dc, context, false);
3629
3630                 context_clock_trace(dc, context);
3631         }
3632
3633         for (j = 0; j < dc->res_pool->pipe_count; j++) {
3634                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3635
3636                 if (!pipe_ctx->top_pipe &&
3637                         !pipe_ctx->prev_odm_pipe &&
3638                         pipe_ctx->stream &&
3639                         pipe_ctx->stream == stream) {
3640                         top_pipe_to_program = pipe_ctx;
3641                 }
3642         }
3643
3644         for (i = 0; i < dc->res_pool->pipe_count; i++) {
3645                 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
3646
3647                 // Check old context for SubVP
3648                 subvp_prev_use |= (old_pipe->stream && old_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM);
3649                 if (subvp_prev_use)
3650                         break;
3651         }
3652
3653         for (i = 0; i < dc->res_pool->pipe_count; i++) {
3654                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
3655
3656                 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
3657                         subvp_curr_use = true;
3658                         break;
3659                 }
3660         }
3661
3662         if (dc->debug.visual_confirm)
3663                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
3664                         struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
3665
3666                         if (pipe->stream && pipe->plane_state)
3667                                 dc_update_viusal_confirm_color(dc, context, pipe);
3668                 }
3669
3670         if (stream->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE) {
3671                 struct pipe_ctx *mpcc_pipe;
3672                 struct pipe_ctx *odm_pipe;
3673
3674                 for (mpcc_pipe = top_pipe_to_program; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe)
3675                         for (odm_pipe = mpcc_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
3676                                 odm_pipe->ttu_regs.min_ttu_vblank = MAX_TTU;
3677         }
3678
3679         if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
3680                 if (top_pipe_to_program &&
3681                         top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
3682                         if (should_use_dmub_lock(stream->link)) {
3683                                 union dmub_hw_lock_flags hw_locks = { 0 };
3684                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
3685
3686                                 hw_locks.bits.lock_dig = 1;
3687                                 inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst;
3688
3689                                 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
3690                                                         true,
3691                                                         &hw_locks,
3692                                                         &inst_flags);
3693                         } else
3694                                 top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable(
3695                                                 top_pipe_to_program->stream_res.tg);
3696                 }
3697
3698         if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {
3699                 if (dc->hwss.subvp_pipe_control_lock)
3700                                 dc->hwss.subvp_pipe_control_lock(dc, context, true, should_lock_all_pipes, NULL, subvp_prev_use);
3701                 dc->hwss.interdependent_update_lock(dc, context, true);
3702
3703         } else {
3704                 if (dc->hwss.subvp_pipe_control_lock)
3705                         dc->hwss.subvp_pipe_control_lock(dc, context, true, should_lock_all_pipes, top_pipe_to_program, subvp_prev_use);
3706                 /* Lock the top pipe while updating plane addrs, since freesync requires
3707                  *  plane addr update event triggers to be synchronized.
3708                  *  top_pipe_to_program is expected to never be NULL
3709                  */
3710                 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);
3711         }
3712
3713         dc_dmub_update_dirty_rect(dc, surface_count, stream, srf_updates, context);
3714
3715         // Stream updates
3716         if (stream_update)
3717                 commit_planes_do_stream_update(dc, stream, stream_update, update_type, context);
3718
3719         if (surface_count == 0) {
3720                 /*
3721                  * In case of turning off screen, no need to program front end a second time.
3722                  * just return after program blank.
3723                  */
3724                 if (dc->hwss.apply_ctx_for_surface)
3725                         dc->hwss.apply_ctx_for_surface(dc, stream, 0, context);
3726                 if (dc->hwss.program_front_end_for_ctx)
3727                         dc->hwss.program_front_end_for_ctx(dc, context);
3728
3729                 if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {
3730                         dc->hwss.interdependent_update_lock(dc, context, false);
3731                 } else {
3732                         dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
3733                 }
3734                 dc->hwss.post_unlock_program_front_end(dc, context);
3735
3736                 if (update_type != UPDATE_TYPE_FAST)
3737                         if (dc->hwss.commit_subvp_config)
3738                                 dc->hwss.commit_subvp_config(dc, context);
3739
3740                 /* Since phantom pipe programming is moved to post_unlock_program_front_end,
3741                  * move the SubVP lock to after the phantom pipes have been setup
3742                  */
3743                 if (dc->hwss.subvp_pipe_control_lock)
3744                         dc->hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes,
3745                                                          NULL, subvp_prev_use);
3746                 return;
3747         }
3748
3749         if (update_type != UPDATE_TYPE_FAST) {
3750                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
3751                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3752
3753                         if ((dc->debug.visual_confirm == VISUAL_CONFIRM_SUBVP ||
3754                                 dc->debug.visual_confirm == VISUAL_CONFIRM_MCLK_SWITCH) &&
3755                                 pipe_ctx->stream && pipe_ctx->plane_state) {
3756                                 /* Only update visual confirm for SUBVP and Mclk switching here.
3757                                  * The bar appears on all pipes, so we need to update the bar on all displays,
3758                                  * so the information doesn't get stale.
3759                                  */
3760                                 dc->hwss.update_visual_confirm_color(dc, pipe_ctx,
3761                                                 pipe_ctx->plane_res.hubp->inst);
3762                         }
3763                 }
3764         }
3765
3766         for (i = 0; i < surface_count; i++) {
3767                 struct dc_plane_state *plane_state = srf_updates[i].surface;
3768                 /*set logical flag for lock/unlock use*/
3769                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
3770                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3771                         if (!pipe_ctx->plane_state)
3772                                 continue;
3773                         if (should_update_pipe_for_plane(context, pipe_ctx, plane_state))
3774                                 continue;
3775                         pipe_ctx->plane_state->triplebuffer_flips = false;
3776                         if (update_type == UPDATE_TYPE_FAST &&
3777                                 dc->hwss.program_triplebuffer != NULL &&
3778                                 !pipe_ctx->plane_state->flip_immediate && dc->debug.enable_tri_buf) {
3779                                         /*triple buffer for VUpdate  only*/
3780                                         pipe_ctx->plane_state->triplebuffer_flips = true;
3781                         }
3782                 }
3783                 if (update_type == UPDATE_TYPE_FULL) {
3784                         /* force vsync flip when reconfiguring pipes to prevent underflow */
3785                         plane_state->flip_immediate = false;
3786                 }
3787         }
3788
3789         // Update Type FULL, Surface updates
3790         for (j = 0; j < dc->res_pool->pipe_count; j++) {
3791                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3792
3793                 if (!pipe_ctx->top_pipe &&
3794                         !pipe_ctx->prev_odm_pipe &&
3795                         should_update_pipe_for_stream(context, pipe_ctx, stream)) {
3796                         struct dc_stream_status *stream_status = NULL;
3797
3798                         if (!pipe_ctx->plane_state)
3799                                 continue;
3800
3801                         /* Full fe update*/
3802                         if (update_type == UPDATE_TYPE_FAST)
3803                                 continue;
3804
3805                         ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);
3806
3807                         if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
3808                                 /*turn off triple buffer for full update*/
3809                                 dc->hwss.program_triplebuffer(
3810                                         dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
3811                         }
3812                         stream_status =
3813                                 stream_get_status(context, pipe_ctx->stream);
3814
3815                         if (dc->hwss.apply_ctx_for_surface)
3816                                 dc->hwss.apply_ctx_for_surface(
3817                                         dc, pipe_ctx->stream, stream_status->plane_count, context);
3818                 }
3819         }
3820         if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) {
3821                 dc->hwss.program_front_end_for_ctx(dc, context);
3822                 if (dc->debug.validate_dml_output) {
3823                         for (i = 0; i < dc->res_pool->pipe_count; i++) {
3824                                 struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[i];
3825                                 if (cur_pipe->stream == NULL)
3826                                         continue;
3827
3828                                 cur_pipe->plane_res.hubp->funcs->validate_dml_output(
3829                                                 cur_pipe->plane_res.hubp, dc->ctx,
3830                                                 &context->res_ctx.pipe_ctx[i].rq_regs,
3831                                                 &context->res_ctx.pipe_ctx[i].dlg_regs,
3832                                                 &context->res_ctx.pipe_ctx[i].ttu_regs);
3833                         }
3834                 }
3835         }
3836
3837         // Update Type FAST, Surface updates
3838         if (update_type == UPDATE_TYPE_FAST) {
3839                 if (dc->hwss.set_flip_control_gsl)
3840                         for (i = 0; i < surface_count; i++) {
3841                                 struct dc_plane_state *plane_state = srf_updates[i].surface;
3842
3843                                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
3844                                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3845
3846                                         if (!should_update_pipe_for_stream(context, pipe_ctx, stream))
3847                                                 continue;
3848
3849                                         if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))
3850                                                 continue;
3851
3852                                         // GSL has to be used for flip immediate
3853                                         dc->hwss.set_flip_control_gsl(pipe_ctx,
3854                                                         pipe_ctx->plane_state->flip_immediate);
3855                                 }
3856                         }
3857
3858                 /* Perform requested Updates */
3859                 for (i = 0; i < surface_count; i++) {
3860                         struct dc_plane_state *plane_state = srf_updates[i].surface;
3861
3862                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
3863                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3864
3865                                 if (!should_update_pipe_for_stream(context, pipe_ctx, stream))
3866                                         continue;
3867
3868                                 if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))
3869                                         continue;
3870
3871                                 /*program triple buffer after lock based on flip type*/
3872                                 if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
3873                                         /*only enable triplebuffer for  fast_update*/
3874                                         dc->hwss.program_triplebuffer(
3875                                                 dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
3876                                 }
3877                                 if (pipe_ctx->plane_state->update_flags.bits.addr_update)
3878                                         dc->hwss.update_plane_addr(dc, pipe_ctx);
3879                         }
3880                 }
3881         }
3882
3883         if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {
3884                 dc->hwss.interdependent_update_lock(dc, context, false);
3885         } else {
3886                 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
3887         }
3888
3889         if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
3890                 if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
3891                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
3892                                 top_pipe_to_program->stream_res.tg,
3893                                 CRTC_STATE_VACTIVE);
3894                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
3895                                 top_pipe_to_program->stream_res.tg,
3896                                 CRTC_STATE_VBLANK);
3897                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
3898                                 top_pipe_to_program->stream_res.tg,
3899                                 CRTC_STATE_VACTIVE);
3900
3901                         if (should_use_dmub_lock(stream->link)) {
3902                                 union dmub_hw_lock_flags hw_locks = { 0 };
3903                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
3904
3905                                 hw_locks.bits.lock_dig = 1;
3906                                 inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst;
3907
3908                                 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
3909                                                         false,
3910                                                         &hw_locks,
3911                                                         &inst_flags);
3912                         } else
3913                                 top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_disable(
3914                                         top_pipe_to_program->stream_res.tg);
3915                 }
3916
3917         if (subvp_curr_use) {
3918                 /* If enabling subvp or transitioning from subvp->subvp, enable the
3919                  * phantom streams before we program front end for the phantom pipes.
3920                  */
3921                 if (update_type != UPDATE_TYPE_FAST) {
3922                         if (dc->hwss.enable_phantom_streams)
3923                                 dc->hwss.enable_phantom_streams(dc, context);
3924                 }
3925         }
3926
3927         if (update_type != UPDATE_TYPE_FAST)
3928                 dc->hwss.post_unlock_program_front_end(dc, context);
3929
3930         if (subvp_prev_use && !subvp_curr_use) {
3931                 /* If disabling subvp, disable phantom streams after front end
3932                  * programming has completed (we turn on phantom OTG in order
3933                  * to complete the plane disable for phantom pipes).
3934                  */
3935                 dc->hwss.apply_ctx_to_hw(dc, context);
3936         }
3937
3938         if (update_type != UPDATE_TYPE_FAST)
3939                 if (dc->hwss.commit_subvp_config)
3940                         dc->hwss.commit_subvp_config(dc, context);
3941         /* Since phantom pipe programming is moved to post_unlock_program_front_end,
3942          * move the SubVP lock to after the phantom pipes have been setup
3943          */
3944         if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {
3945                 if (dc->hwss.subvp_pipe_control_lock)
3946                         dc->hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes, NULL, subvp_prev_use);
3947         } else {
3948                 if (dc->hwss.subvp_pipe_control_lock)
3949                         dc->hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes, top_pipe_to_program, subvp_prev_use);
3950         }
3951
3952         // Fire manual trigger only when bottom plane is flipped
3953         for (j = 0; j < dc->res_pool->pipe_count; j++) {
3954                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3955
3956                 if (!pipe_ctx->plane_state)
3957                         continue;
3958
3959                 if (pipe_ctx->bottom_pipe || pipe_ctx->next_odm_pipe ||
3960                                 !pipe_ctx->stream || !should_update_pipe_for_stream(context, pipe_ctx, stream) ||
3961                                 !pipe_ctx->plane_state->update_flags.bits.addr_update ||
3962                                 pipe_ctx->plane_state->skip_manual_trigger)
3963                         continue;
3964
3965                 if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger)
3966                         pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);
3967         }
3968 }
3969
3970 /**
3971  * could_mpcc_tree_change_for_active_pipes - Check if an OPP associated with MPCC might change
3972  *
3973  * @dc: Used to get the current state status
3974  * @stream: Target stream, which we want to remove the attached planes
3975  * @surface_count: Number of surface update
3976  * @is_plane_addition: [in] Fill out with true if it is a plane addition case
3977  *
3978  * DCN32x and newer support a feature named Dynamic ODM which can conflict with
3979  * the MPO if used simultaneously in some specific configurations (e.g.,
3980  * 4k@144). This function checks if the incoming context requires applying a
3981  * transition state with unnecessary pipe splitting and ODM disabled to
3982  * circumvent our hardware limitations to prevent this edge case. If the OPP
3983  * associated with an MPCC might change due to plane additions, this function
3984  * returns true.
3985  *
3986  * Return:
3987  * Return true if OPP and MPCC might change, otherwise, return false.
3988  */
3989 static bool could_mpcc_tree_change_for_active_pipes(struct dc *dc,
3990                 struct dc_stream_state *stream,
3991                 int surface_count,
3992                 bool *is_plane_addition)
3993 {
3994
3995         struct dc_stream_status *cur_stream_status = stream_get_status(dc->current_state, stream);
3996         bool force_minimal_pipe_splitting = false;
3997         bool subvp_active = false;
3998         uint32_t i;
3999
4000         *is_plane_addition = false;
4001
4002         if (cur_stream_status &&
4003                         dc->current_state->stream_count > 0 &&
4004                         dc->debug.pipe_split_policy != MPC_SPLIT_AVOID) {
4005                 /* determine if minimal transition is required due to MPC*/
4006                 if (surface_count > 0) {
4007                         if (cur_stream_status->plane_count > surface_count) {
4008                                 force_minimal_pipe_splitting = true;
4009                         } else if (cur_stream_status->plane_count < surface_count) {
4010                                 force_minimal_pipe_splitting = true;
4011                                 *is_plane_addition = true;
4012                         }
4013                 }
4014         }
4015
4016         if (cur_stream_status &&
4017                         dc->current_state->stream_count == 1 &&
4018                         dc->debug.enable_single_display_2to1_odm_policy) {
4019                 /* determine if minimal transition is required due to dynamic ODM*/
4020                 if (surface_count > 0) {
4021                         if (cur_stream_status->plane_count > 2 && cur_stream_status->plane_count > surface_count) {
4022                                 force_minimal_pipe_splitting = true;
4023                         } else if (surface_count > 2 && cur_stream_status->plane_count < surface_count) {
4024                                 force_minimal_pipe_splitting = true;
4025                                 *is_plane_addition = true;
4026                         }
4027                 }
4028         }
4029
4030         for (i = 0; i < dc->res_pool->pipe_count; i++) {
4031                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
4032
4033                 if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_NONE) {
4034                         subvp_active = true;
4035                         break;
4036                 }
4037         }
4038
4039         /* For SubVP when adding or removing planes we need to add a minimal transition
4040          * (even when disabling all planes). Whenever disabling a phantom pipe, we
4041          * must use the minimal transition path to disable the pipe correctly.
4042          *
4043          * We want to use the minimal transition whenever subvp is active, not only if
4044          * a plane is being added / removed from a subvp stream (MPO plane can be added
4045          * to a DRR pipe of SubVP + DRR config, in which case we still want to run through
4046          * a min transition to disable subvp.
4047          */
4048         if (cur_stream_status && subvp_active) {
4049                 /* determine if minimal transition is required due to SubVP*/
4050                 if (cur_stream_status->plane_count > surface_count) {
4051                         force_minimal_pipe_splitting = true;
4052                 } else if (cur_stream_status->plane_count < surface_count) {
4053                         force_minimal_pipe_splitting = true;
4054                         *is_plane_addition = true;
4055                 }
4056         }
4057
4058         return force_minimal_pipe_splitting;
4059 }
4060
4061 /**
4062  * commit_minimal_transition_state - Create a transition pipe split state
4063  *
4064  * @dc: Used to get the current state status
4065  * @transition_base_context: New transition state
4066  *
4067  * In some specific configurations, such as pipe split on multi-display with
4068  * MPO and/or Dynamic ODM, removing a plane may cause unsupported pipe
4069  * programming when moving to new planes. To mitigate those types of problems,
4070  * this function adds a transition state that minimizes pipe usage before
4071  * programming the new configuration. When adding a new plane, the current
4072  * state requires the least pipes, so it is applied without splitting. When
4073  * removing a plane, the new state requires the least pipes, so it is applied
4074  * without splitting.
4075  *
4076  * Return:
4077  * Return false if something is wrong in the transition state.
4078  */
4079 static bool commit_minimal_transition_state(struct dc *dc,
4080                 struct dc_state *transition_base_context)
4081 {
4082         struct dc_state *transition_context = dc_create_state(dc);
4083         enum pipe_split_policy tmp_mpc_policy;
4084         bool temp_dynamic_odm_policy;
4085         bool temp_subvp_policy;
4086         enum dc_status ret = DC_ERROR_UNEXPECTED;
4087         unsigned int i, j;
4088         unsigned int pipe_in_use = 0;
4089         bool subvp_in_use = false;
4090         bool odm_in_use = false;
4091
4092         if (!transition_context)
4093                 return false;
4094         /* Setup:
4095          * Store the current ODM and MPC config in some temp variables to be
4096          * restored after we commit the transition state.
4097          */
4098
4099         /* check current pipes in use*/
4100         for (i = 0; i < dc->res_pool->pipe_count; i++) {
4101                 struct pipe_ctx *pipe = &transition_base_context->res_ctx.pipe_ctx[i];
4102
4103                 if (pipe->plane_state)
4104                         pipe_in_use++;
4105         }
4106
4107         /* If SubVP is enabled and we are adding or removing planes from any main subvp
4108          * pipe, we must use the minimal transition.
4109          */
4110         for (i = 0; i < dc->res_pool->pipe_count; i++) {
4111                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
4112
4113                 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
4114                         subvp_in_use = true;
4115                         break;
4116                 }
4117         }
4118
4119         /* If ODM is enabled and we are adding or removing planes from any ODM
4120          * pipe, we must use the minimal transition.
4121          */
4122         for (i = 0; i < dc->res_pool->pipe_count; i++) {
4123                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
4124
4125                 if (pipe->stream && pipe->next_odm_pipe) {
4126                         odm_in_use = true;
4127                         break;
4128                 }
4129         }
4130
4131         /* When the OS add a new surface if we have been used all of pipes with odm combine
4132          * and mpc split feature, it need use commit_minimal_transition_state to transition safely.
4133          * After OS exit MPO, it will back to use odm and mpc split with all of pipes, we need
4134          * call it again. Otherwise return true to skip.
4135          *
4136          * Reduce the scenarios to use dc_commit_state_no_check in the stage of flip. Especially
4137          * enter/exit MPO when DCN still have enough resources.
4138          */
4139         if (pipe_in_use != dc->res_pool->pipe_count && !subvp_in_use && !odm_in_use) {
4140                 dc_release_state(transition_context);
4141                 return true;
4142         }
4143
4144         if (!dc->config.is_vmin_only_asic) {
4145                 tmp_mpc_policy = dc->debug.pipe_split_policy;
4146                 dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
4147         }
4148
4149         temp_dynamic_odm_policy = dc->debug.enable_single_display_2to1_odm_policy;
4150         dc->debug.enable_single_display_2to1_odm_policy = false;
4151
4152         temp_subvp_policy = dc->debug.force_disable_subvp;
4153         dc->debug.force_disable_subvp = true;
4154
4155         dc_resource_state_copy_construct(transition_base_context, transition_context);
4156
4157         /* commit minimal state */
4158         if (dc->res_pool->funcs->validate_bandwidth(dc, transition_context, false)) {
4159                 for (i = 0; i < transition_context->stream_count; i++) {
4160                         struct dc_stream_status *stream_status = &transition_context->stream_status[i];
4161
4162                         for (j = 0; j < stream_status->plane_count; j++) {
4163                                 struct dc_plane_state *plane_state = stream_status->plane_states[j];
4164
4165                                 /* force vsync flip when reconfiguring pipes to prevent underflow
4166                                  * and corruption
4167                                  */
4168                                 plane_state->flip_immediate = false;
4169                         }
4170                 }
4171
4172                 ret = dc_commit_state_no_check(dc, transition_context);
4173         }
4174
4175         /* always release as dc_commit_state_no_check retains in good case */
4176         dc_release_state(transition_context);
4177
4178         /* TearDown:
4179          * Restore original configuration for ODM and MPO.
4180          */
4181         if (!dc->config.is_vmin_only_asic)
4182                 dc->debug.pipe_split_policy = tmp_mpc_policy;
4183
4184         dc->debug.enable_single_display_2to1_odm_policy = temp_dynamic_odm_policy;
4185         dc->debug.force_disable_subvp = temp_subvp_policy;
4186
4187         if (ret != DC_OK) {
4188                 /* this should never happen */
4189                 BREAK_TO_DEBUGGER();
4190                 return false;
4191         }
4192
4193         /* force full surface update */
4194         for (i = 0; i < dc->current_state->stream_count; i++) {
4195                 for (j = 0; j < dc->current_state->stream_status[i].plane_count; j++) {
4196                         dc->current_state->stream_status[i].plane_states[j]->update_flags.raw = 0xFFFFFFFF;
4197                 }
4198         }
4199
4200         return true;
4201 }
4202
4203 /**
4204  * *******************************************************************************
4205  * update_seamless_boot_flags: Helper function for updating seamless boot flags
4206  *
4207  * @param [in]: dc: Current DC state
4208  * @param [in]: context: New DC state to be programmed
4209  * @param [in]: surface_count: Number of surfaces that have an updated
4210  * @param [in]: stream: Correponding stream to be updated in the current flip
4211  *
4212  * Updating seamless boot flags do not need to be part of the commit sequence. This
4213  * helper function will update the seamless boot flags on each flip (if required)
4214  * outside of the HW commit sequence (fast or slow).
4215  *
4216  * @return: void
4217  * *******************************************************************************
4218  */
4219 static void update_seamless_boot_flags(struct dc *dc,
4220                 struct dc_state *context,
4221                 int surface_count,
4222                 struct dc_stream_state *stream)
4223 {
4224         if (get_seamless_boot_stream_count(context) > 0 && surface_count > 0) {
4225                 /* Optimize seamless boot flag keeps clocks and watermarks high until
4226                  * first flip. After first flip, optimization is required to lower
4227                  * bandwidth. Important to note that it is expected UEFI will
4228                  * only light up a single display on POST, therefore we only expect
4229                  * one stream with seamless boot flag set.
4230                  */
4231                 if (stream->apply_seamless_boot_optimization) {
4232                         stream->apply_seamless_boot_optimization = false;
4233
4234                         if (get_seamless_boot_stream_count(context) == 0)
4235                                 dc->optimized_required = true;
4236                 }
4237         }
4238 }
4239
4240 bool dc_update_planes_and_stream(struct dc *dc,
4241                 struct dc_surface_update *srf_updates, int surface_count,
4242                 struct dc_stream_state *stream,
4243                 struct dc_stream_update *stream_update)
4244 {
4245         struct dc_state *context;
4246         enum surface_update_type update_type;
4247         int i;
4248         struct mall_temp_config mall_temp_config;
4249
4250         /* In cases where MPO and split or ODM are used transitions can
4251          * cause underflow. Apply stream configuration with minimal pipe
4252          * split first to avoid unsupported transitions for active pipes.
4253          */
4254         bool force_minimal_pipe_splitting;
4255         bool is_plane_addition;
4256
4257         force_minimal_pipe_splitting = could_mpcc_tree_change_for_active_pipes(
4258                         dc,
4259                         stream,
4260                         surface_count,
4261                         &is_plane_addition);
4262
4263         /* on plane addition, minimal state is the current one */
4264         if (force_minimal_pipe_splitting && is_plane_addition &&
4265                 !commit_minimal_transition_state(dc, dc->current_state))
4266                                 return false;
4267
4268         if (!update_planes_and_stream_state(
4269                         dc,
4270                         srf_updates,
4271                         surface_count,
4272                         stream,
4273                         stream_update,
4274                         &update_type,
4275                         &context))
4276                 return false;
4277
4278         /* on plane removal, minimal state is the new one */
4279         if (force_minimal_pipe_splitting && !is_plane_addition) {
4280                 /* Since all phantom pipes are removed in full validation,
4281                  * we have to save and restore the subvp/mall config when
4282                  * we do a minimal transition since the flags marking the
4283                  * pipe as subvp/phantom will be cleared (dc copy constructor
4284                  * creates a shallow copy).
4285                  */
4286                 if (dc->res_pool->funcs->save_mall_state)
4287                         dc->res_pool->funcs->save_mall_state(dc, context, &mall_temp_config);
4288                 if (!commit_minimal_transition_state(dc, context)) {
4289                         dc_release_state(context);
4290                         return false;
4291                 }
4292                 if (dc->res_pool->funcs->restore_mall_state)
4293                         dc->res_pool->funcs->restore_mall_state(dc, context, &mall_temp_config);
4294
4295                 /* If we do a minimal transition with plane removal and the context
4296                  * has subvp we also have to retain back the phantom stream / planes
4297                  * since the refcount is decremented as part of the min transition
4298                  * (we commit a state with no subvp, so the phantom streams / planes
4299                  * had to be removed).
4300                  */
4301                 if (dc->res_pool->funcs->retain_phantom_pipes)
4302                         dc->res_pool->funcs->retain_phantom_pipes(dc, context);
4303                 update_type = UPDATE_TYPE_FULL;
4304         }
4305
4306         update_seamless_boot_flags(dc, context, surface_count, stream);
4307         if (!dc->debug.enable_legacy_fast_update && update_type == UPDATE_TYPE_FAST) {
4308                 commit_planes_for_stream_fast(dc,
4309                                 srf_updates,
4310                                 surface_count,
4311                                 stream,
4312                                 stream_update,
4313                                 update_type,
4314                                 context);
4315         } else {
4316                 commit_planes_for_stream(
4317                                 dc,
4318                                 srf_updates,
4319                                 surface_count,
4320                                 stream,
4321                                 stream_update,
4322                                 update_type,
4323                                 context);
4324         }
4325
4326         if (dc->current_state != context) {
4327
4328                 /* Since memory free requires elevated IRQL, an interrupt
4329                  * request is generated by mem free. If this happens
4330                  * between freeing and reassigning the context, our vsync
4331                  * interrupt will call into dc and cause a memory
4332                  * corruption BSOD. Hence, we first reassign the context,
4333                  * then free the old context.
4334                  */
4335
4336                 struct dc_state *old = dc->current_state;
4337
4338                 dc->current_state = context;
4339                 dc_release_state(old);
4340
4341                 // clear any forced full updates
4342                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
4343                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
4344
4345                         if (pipe_ctx->plane_state && pipe_ctx->stream == stream)
4346                                 pipe_ctx->plane_state->force_full_update = false;
4347                 }
4348         }
4349         return true;
4350 }
4351
4352 void dc_commit_updates_for_stream(struct dc *dc,
4353                 struct dc_surface_update *srf_updates,
4354                 int surface_count,
4355                 struct dc_stream_state *stream,
4356                 struct dc_stream_update *stream_update,
4357                 struct dc_state *state)
4358 {
4359         const struct dc_stream_status *stream_status;
4360         enum surface_update_type update_type;
4361         struct dc_state *context;
4362         struct dc_context *dc_ctx = dc->ctx;
4363         int i, j;
4364
4365         stream_status = dc_stream_get_status(stream);
4366         context = dc->current_state;
4367
4368         update_type = dc_check_update_surfaces_for_stream(
4369                                 dc, srf_updates, surface_count, stream_update, stream_status);
4370
4371         /* TODO: Since change commit sequence can have a huge impact,
4372          * we decided to only enable it for DCN3x. However, as soon as
4373          * we get more confident about this change we'll need to enable
4374          * the new sequence for all ASICs.
4375          */
4376         if (dc->ctx->dce_version >= DCN_VERSION_3_2) {
4377                 /*
4378                  * Previous frame finished and HW is ready for optimization.
4379                  */
4380                 if (update_type == UPDATE_TYPE_FAST)
4381                         dc_post_update_surfaces_to_stream(dc);
4382
4383                 dc_update_planes_and_stream(dc, srf_updates,
4384                                             surface_count, stream,
4385                                             stream_update);
4386                 return;
4387         }
4388
4389         if (update_type >= update_surface_trace_level)
4390                 update_surface_trace(dc, srf_updates, surface_count);
4391
4392
4393         if (update_type >= UPDATE_TYPE_FULL) {
4394
4395                 /* initialize scratch memory for building context */
4396                 context = dc_create_state(dc);
4397                 if (context == NULL) {
4398                         DC_ERROR("Failed to allocate new validate context!\n");
4399                         return;
4400                 }
4401
4402                 dc_resource_state_copy_construct(state, context);
4403
4404                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
4405                         struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];
4406                         struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
4407
4408                         if (new_pipe->plane_state && new_pipe->plane_state != old_pipe->plane_state)
4409                                 new_pipe->plane_state->force_full_update = true;
4410                 }
4411         } else if (update_type == UPDATE_TYPE_FAST) {
4412                 /*
4413                  * Previous frame finished and HW is ready for optimization.
4414                  */
4415                 dc_post_update_surfaces_to_stream(dc);
4416         }
4417
4418
4419         for (i = 0; i < surface_count; i++) {
4420                 struct dc_plane_state *surface = srf_updates[i].surface;
4421
4422                 copy_surface_update_to_plane(surface, &srf_updates[i]);
4423
4424                 if (update_type >= UPDATE_TYPE_MED) {
4425                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
4426                                 struct pipe_ctx *pipe_ctx =
4427                                         &context->res_ctx.pipe_ctx[j];
4428
4429                                 if (pipe_ctx->plane_state != surface)
4430                                         continue;
4431
4432                                 resource_build_scaling_params(pipe_ctx);
4433                         }
4434                 }
4435         }
4436
4437         copy_stream_update_to_stream(dc, context, stream, stream_update);
4438
4439         if (update_type >= UPDATE_TYPE_FULL) {
4440                 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) {
4441                         DC_ERROR("Mode validation failed for stream update!\n");
4442                         dc_release_state(context);
4443                         return;
4444                 }
4445         }
4446
4447         TRACE_DC_PIPE_STATE(pipe_ctx, i, MAX_PIPES);
4448
4449         update_seamless_boot_flags(dc, context, surface_count, stream);
4450         if (!dc->debug.enable_legacy_fast_update && update_type == UPDATE_TYPE_FAST) {
4451                 commit_planes_for_stream_fast(dc,
4452                                 srf_updates,
4453                                 surface_count,
4454                                 stream,
4455                                 stream_update,
4456                                 update_type,
4457                                 context);
4458         } else {
4459                 commit_planes_for_stream(
4460                                 dc,
4461                                 srf_updates,
4462                                 surface_count,
4463                                 stream,
4464                                 stream_update,
4465                                 update_type,
4466                                 context);
4467         }
4468         /*update current_State*/
4469         if (dc->current_state != context) {
4470
4471                 struct dc_state *old = dc->current_state;
4472
4473                 dc->current_state = context;
4474                 dc_release_state(old);
4475
4476                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
4477                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
4478
4479                         if (pipe_ctx->plane_state && pipe_ctx->stream == stream)
4480                                 pipe_ctx->plane_state->force_full_update = false;
4481                 }
4482         }
4483
4484         /* Legacy optimization path for DCE. */
4485         if (update_type >= UPDATE_TYPE_FULL && dc_ctx->dce_version < DCE_VERSION_MAX) {
4486                 dc_post_update_surfaces_to_stream(dc);
4487                 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);
4488         }
4489
4490         return;
4491
4492 }
4493
4494 uint8_t dc_get_current_stream_count(struct dc *dc)
4495 {
4496         return dc->current_state->stream_count;
4497 }
4498
4499 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i)
4500 {
4501         if (i < dc->current_state->stream_count)
4502                 return dc->current_state->streams[i];
4503         return NULL;
4504 }
4505
4506 enum dc_irq_source dc_interrupt_to_irq_source(
4507                 struct dc *dc,
4508                 uint32_t src_id,
4509                 uint32_t ext_id)
4510 {
4511         return dal_irq_service_to_irq_source(dc->res_pool->irqs, src_id, ext_id);
4512 }
4513
4514 /*
4515  * dc_interrupt_set() - Enable/disable an AMD hw interrupt source
4516  */
4517 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable)
4518 {
4519
4520         if (dc == NULL)
4521                 return false;
4522
4523         return dal_irq_service_set(dc->res_pool->irqs, src, enable);
4524 }
4525
4526 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
4527 {
4528         dal_irq_service_ack(dc->res_pool->irqs, src);
4529 }
4530
4531 void dc_power_down_on_boot(struct dc *dc)
4532 {
4533         if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW &&
4534                         dc->hwss.power_down_on_boot)
4535                 dc->hwss.power_down_on_boot(dc);
4536 }
4537
4538 void dc_set_power_state(
4539         struct dc *dc,
4540         enum dc_acpi_cm_power_state power_state)
4541 {
4542         struct kref refcount;
4543         struct display_mode_lib *dml;
4544
4545         if (!dc->current_state)
4546                 return;
4547
4548         switch (power_state) {
4549         case DC_ACPI_CM_POWER_STATE_D0:
4550                 dc_resource_state_construct(dc, dc->current_state);
4551
4552                 dc_z10_restore(dc);
4553
4554                 dc->hwss.init_hw(dc);
4555
4556                 if (dc->hwss.init_sys_ctx != NULL &&
4557                         dc->vm_pa_config.valid) {
4558                         dc->hwss.init_sys_ctx(dc->hwseq, dc, &dc->vm_pa_config);
4559                 }
4560
4561                 break;
4562         default:
4563                 ASSERT(dc->current_state->stream_count == 0);
4564                 /* Zero out the current context so that on resume we start with
4565                  * clean state, and dc hw programming optimizations will not
4566                  * cause any trouble.
4567                  */
4568                 dml = kzalloc(sizeof(struct display_mode_lib),
4569                                 GFP_KERNEL);
4570
4571                 ASSERT(dml);
4572                 if (!dml)
4573                         return;
4574
4575                 /* Preserve refcount */
4576                 refcount = dc->current_state->refcount;
4577                 /* Preserve display mode lib */
4578                 memcpy(dml, &dc->current_state->bw_ctx.dml, sizeof(struct display_mode_lib));
4579
4580                 dc_resource_state_destruct(dc->current_state);
4581                 memset(dc->current_state, 0,
4582                                 sizeof(*dc->current_state));
4583
4584                 dc->current_state->refcount = refcount;
4585                 dc->current_state->bw_ctx.dml = *dml;
4586
4587                 kfree(dml);
4588
4589                 break;
4590         }
4591 }
4592
4593 void dc_resume(struct dc *dc)
4594 {
4595         uint32_t i;
4596
4597         for (i = 0; i < dc->link_count; i++)
4598                 dc->link_srv->resume(dc->links[i]);
4599 }
4600
4601 bool dc_is_dmcu_initialized(struct dc *dc)
4602 {
4603         struct dmcu *dmcu = dc->res_pool->dmcu;
4604
4605         if (dmcu)
4606                 return dmcu->funcs->is_dmcu_initialized(dmcu);
4607         return false;
4608 }
4609
4610 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info)
4611 {
4612         info->displayClock                              = (unsigned int)state->bw_ctx.bw.dcn.clk.dispclk_khz;
4613         info->engineClock                               = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_khz;
4614         info->memoryClock                               = (unsigned int)state->bw_ctx.bw.dcn.clk.dramclk_khz;
4615         info->maxSupportedDppClock              = (unsigned int)state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz;
4616         info->dppClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.dppclk_khz;
4617         info->socClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.socclk_khz;
4618         info->dcfClockDeepSleep                 = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz;
4619         info->fClock                                    = (unsigned int)state->bw_ctx.bw.dcn.clk.fclk_khz;
4620         info->phyClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.phyclk_khz;
4621 }
4622 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping)
4623 {
4624         if (dc->hwss.set_clock)
4625                 return dc->hwss.set_clock(dc, clock_type, clk_khz, stepping);
4626         return DC_ERROR_UNEXPECTED;
4627 }
4628 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg)
4629 {
4630         if (dc->hwss.get_clock)
4631                 dc->hwss.get_clock(dc, clock_type, clock_cfg);
4632 }
4633
4634 /* enable/disable eDP PSR without specify stream for eDP */
4635 bool dc_set_psr_allow_active(struct dc *dc, bool enable)
4636 {
4637         int i;
4638         bool allow_active;
4639
4640         for (i = 0; i < dc->current_state->stream_count ; i++) {
4641                 struct dc_link *link;
4642                 struct dc_stream_state *stream = dc->current_state->streams[i];
4643
4644                 link = stream->link;
4645                 if (!link)
4646                         continue;
4647
4648                 if (link->psr_settings.psr_feature_enabled) {
4649                         if (enable && !link->psr_settings.psr_allow_active) {
4650                                 allow_active = true;
4651                                 if (!dc_link_set_psr_allow_active(link, &allow_active, false, false, NULL))
4652                                         return false;
4653                         } else if (!enable && link->psr_settings.psr_allow_active) {
4654                                 allow_active = false;
4655                                 if (!dc_link_set_psr_allow_active(link, &allow_active, true, false, NULL))
4656                                         return false;
4657                         }
4658                 }
4659         }
4660
4661         return true;
4662 }
4663
4664 void dc_allow_idle_optimizations(struct dc *dc, bool allow)
4665 {
4666         if (dc->debug.disable_idle_power_optimizations)
4667                 return;
4668
4669         if (dc->clk_mgr != NULL && dc->clk_mgr->funcs->is_smu_present)
4670                 if (!dc->clk_mgr->funcs->is_smu_present(dc->clk_mgr))
4671                         return;
4672
4673         if (allow == dc->idle_optimizations_allowed)
4674                 return;
4675
4676         if (dc->hwss.apply_idle_power_optimizations && dc->hwss.apply_idle_power_optimizations(dc, allow))
4677                 dc->idle_optimizations_allowed = allow;
4678 }
4679
4680 /* set min and max memory clock to lowest and highest DPM level, respectively */
4681 void dc_unlock_memory_clock_frequency(struct dc *dc)
4682 {
4683         if (dc->clk_mgr->funcs->set_hard_min_memclk)
4684                 dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, false);
4685
4686         if (dc->clk_mgr->funcs->set_hard_max_memclk)
4687                 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
4688 }
4689
4690 /* set min memory clock to the min required for current mode, max to maxDPM */
4691 void dc_lock_memory_clock_frequency(struct dc *dc)
4692 {
4693         if (dc->clk_mgr->funcs->get_memclk_states_from_smu)
4694                 dc->clk_mgr->funcs->get_memclk_states_from_smu(dc->clk_mgr);
4695
4696         if (dc->clk_mgr->funcs->set_hard_min_memclk)
4697                 dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, true);
4698
4699         if (dc->clk_mgr->funcs->set_hard_max_memclk)
4700                 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
4701 }
4702
4703 static void blank_and_force_memclk(struct dc *dc, bool apply, unsigned int memclk_mhz)
4704 {
4705         struct dc_state *context = dc->current_state;
4706         struct hubp *hubp;
4707         struct pipe_ctx *pipe;
4708         int i;
4709
4710         for (i = 0; i < dc->res_pool->pipe_count; i++) {
4711                 pipe = &context->res_ctx.pipe_ctx[i];
4712
4713                 if (pipe->stream != NULL) {
4714                         dc->hwss.disable_pixel_data(dc, pipe, true);
4715
4716                         // wait for double buffer
4717                         pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VACTIVE);
4718                         pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VBLANK);
4719                         pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VACTIVE);
4720
4721                         hubp = pipe->plane_res.hubp;
4722                         hubp->funcs->set_blank_regs(hubp, true);
4723                 }
4724         }
4725
4726         dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, memclk_mhz);
4727         dc->clk_mgr->funcs->set_min_memclk(dc->clk_mgr, memclk_mhz);
4728
4729         for (i = 0; i < dc->res_pool->pipe_count; i++) {
4730                 pipe = &context->res_ctx.pipe_ctx[i];
4731
4732                 if (pipe->stream != NULL) {
4733                         dc->hwss.disable_pixel_data(dc, pipe, false);
4734
4735                         hubp = pipe->plane_res.hubp;
4736                         hubp->funcs->set_blank_regs(hubp, false);
4737                 }
4738         }
4739 }
4740
4741
4742 /**
4743  * dc_enable_dcmode_clk_limit() - lower clocks in dc (battery) mode
4744  * @dc: pointer to dc of the dm calling this
4745  * @enable: True = transition to DC mode, false = transition back to AC mode
4746  *
4747  * Some SoCs define additional clock limits when in DC mode, DM should
4748  * invoke this function when the platform undergoes a power source transition
4749  * so DC can apply/unapply the limit. This interface may be disruptive to
4750  * the onscreen content.
4751  *
4752  * Context: Triggered by OS through DM interface, or manually by escape calls.
4753  * Need to hold a dclock when doing so.
4754  *
4755  * Return: none (void function)
4756  *
4757  */
4758 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable)
4759 {
4760         uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
4761         unsigned int softMax, maxDPM, funcMin;
4762         bool p_state_change_support;
4763
4764         if (!ASICREV_IS_BEIGE_GOBY_P(hw_internal_rev))
4765                 return;
4766
4767         softMax = dc->clk_mgr->bw_params->dc_mode_softmax_memclk;
4768         maxDPM = dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz;
4769         funcMin = (dc->clk_mgr->clks.dramclk_khz + 999) / 1000;
4770         p_state_change_support = dc->clk_mgr->clks.p_state_change_support;
4771
4772         if (enable && !dc->clk_mgr->dc_mode_softmax_enabled) {
4773                 if (p_state_change_support) {
4774                         if (funcMin <= softMax)
4775                                 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, softMax);
4776                         // else: No-Op
4777                 } else {
4778                         if (funcMin <= softMax)
4779                                 blank_and_force_memclk(dc, true, softMax);
4780                         // else: No-Op
4781                 }
4782         } else if (!enable && dc->clk_mgr->dc_mode_softmax_enabled) {
4783                 if (p_state_change_support) {
4784                         if (funcMin <= softMax)
4785                                 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, maxDPM);
4786                         // else: No-Op
4787                 } else {
4788                         if (funcMin <= softMax)
4789                                 blank_and_force_memclk(dc, true, maxDPM);
4790                         // else: No-Op
4791                 }
4792         }
4793         dc->clk_mgr->dc_mode_softmax_enabled = enable;
4794 }
4795 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane,
4796                 struct dc_cursor_attributes *cursor_attr)
4797 {
4798         if (dc->hwss.does_plane_fit_in_mall && dc->hwss.does_plane_fit_in_mall(dc, plane, cursor_attr))
4799                 return true;
4800         return false;
4801 }
4802
4803 /* cleanup on driver unload */
4804 void dc_hardware_release(struct dc *dc)
4805 {
4806         dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(dc);
4807
4808         if (dc->hwss.hardware_release)
4809                 dc->hwss.hardware_release(dc);
4810 }
4811
4812 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc)
4813 {
4814         if (dc->current_state)
4815                 dc->current_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching_shut_down = true;
4816 }
4817
4818 /**
4819  * dc_is_dmub_outbox_supported - Check if DMUB firmware support outbox notification
4820  *
4821  * @dc: [in] dc structure
4822  *
4823  * Checks whether DMUB FW supports outbox notifications, if supported DM
4824  * should register outbox interrupt prior to actually enabling interrupts
4825  * via dc_enable_dmub_outbox
4826  *
4827  * Return:
4828  * True if DMUB FW supports outbox notifications, False otherwise
4829  */
4830 bool dc_is_dmub_outbox_supported(struct dc *dc)
4831 {
4832         /* DCN31 B0 USB4 DPIA needs dmub notifications for interrupts */
4833         if (dc->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP &&
4834             dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 &&
4835             !dc->debug.dpia_debug.bits.disable_dpia)
4836                 return true;
4837
4838         if (dc->ctx->asic_id.chip_family == AMDGPU_FAMILY_GC_11_0_1 &&
4839             !dc->debug.dpia_debug.bits.disable_dpia)
4840                 return true;
4841
4842         /* dmub aux needs dmub notifications to be enabled */
4843         return dc->debug.enable_dmub_aux_for_legacy_ddc;
4844 }
4845
4846 /**
4847  * dc_enable_dmub_notifications - Check if dmub fw supports outbox
4848  *
4849  * @dc: [in] dc structure
4850  *
4851  * Calls dc_is_dmub_outbox_supported to check if dmub fw supports outbox
4852  * notifications. All DMs shall switch to dc_is_dmub_outbox_supported.  This
4853  * API shall be removed after switching.
4854  *
4855  * Return:
4856  * True if DMUB FW supports outbox notifications, False otherwise
4857  */
4858 bool dc_enable_dmub_notifications(struct dc *dc)
4859 {
4860         return dc_is_dmub_outbox_supported(dc);
4861 }
4862
4863 /**
4864  * dc_enable_dmub_outbox - Enables DMUB unsolicited notification
4865  *
4866  * @dc: [in] dc structure
4867  *
4868  * Enables DMUB unsolicited notifications to x86 via outbox.
4869  */
4870 void dc_enable_dmub_outbox(struct dc *dc)
4871 {
4872         struct dc_context *dc_ctx = dc->ctx;
4873
4874         dmub_enable_outbox_notification(dc_ctx->dmub_srv);
4875         DC_LOG_DC("%s: dmub outbox notifications enabled\n", __func__);
4876 }
4877
4878 /**
4879  * dc_process_dmub_aux_transfer_async - Submits aux command to dmub via inbox message
4880  *                                      Sets port index appropriately for legacy DDC
4881  * @dc: dc structure
4882  * @link_index: link index
4883  * @payload: aux payload
4884  *
4885  * Returns: True if successful, False if failure
4886  */
4887 bool dc_process_dmub_aux_transfer_async(struct dc *dc,
4888                                 uint32_t link_index,
4889                                 struct aux_payload *payload)
4890 {
4891         uint8_t action;
4892         union dmub_rb_cmd cmd = {0};
4893
4894         ASSERT(payload->length <= 16);
4895
4896         cmd.dp_aux_access.header.type = DMUB_CMD__DP_AUX_ACCESS;
4897         cmd.dp_aux_access.header.payload_bytes = 0;
4898         /* For dpia, ddc_pin is set to NULL */
4899         if (!dc->links[link_index]->ddc->ddc_pin)
4900                 cmd.dp_aux_access.aux_control.type = AUX_CHANNEL_DPIA;
4901         else
4902                 cmd.dp_aux_access.aux_control.type = AUX_CHANNEL_LEGACY_DDC;
4903
4904         cmd.dp_aux_access.aux_control.instance = dc->links[link_index]->ddc_hw_inst;
4905         cmd.dp_aux_access.aux_control.sw_crc_enabled = 0;
4906         cmd.dp_aux_access.aux_control.timeout = 0;
4907         cmd.dp_aux_access.aux_control.dpaux.address = payload->address;
4908         cmd.dp_aux_access.aux_control.dpaux.is_i2c_over_aux = payload->i2c_over_aux;
4909         cmd.dp_aux_access.aux_control.dpaux.length = payload->length;
4910
4911         /* set aux action */
4912         if (payload->i2c_over_aux) {
4913                 if (payload->write) {
4914                         if (payload->mot)
4915                                 action = DP_AUX_REQ_ACTION_I2C_WRITE_MOT;
4916                         else
4917                                 action = DP_AUX_REQ_ACTION_I2C_WRITE;
4918                 } else {
4919                         if (payload->mot)
4920                                 action = DP_AUX_REQ_ACTION_I2C_READ_MOT;
4921                         else
4922                                 action = DP_AUX_REQ_ACTION_I2C_READ;
4923                         }
4924         } else {
4925                 if (payload->write)
4926                         action = DP_AUX_REQ_ACTION_DPCD_WRITE;
4927                 else
4928                         action = DP_AUX_REQ_ACTION_DPCD_READ;
4929         }
4930
4931         cmd.dp_aux_access.aux_control.dpaux.action = action;
4932
4933         if (payload->length && payload->write) {
4934                 memcpy(cmd.dp_aux_access.aux_control.dpaux.data,
4935                         payload->data,
4936                         payload->length
4937                         );
4938         }
4939
4940         dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
4941
4942         return true;
4943 }
4944
4945 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc,
4946                                             uint8_t dpia_port_index)
4947 {
4948         uint8_t index, link_index = 0xFF;
4949
4950         for (index = 0; index < dc->link_count; index++) {
4951                 /* ddc_hw_inst has dpia port index for dpia links
4952                  * and ddc instance for legacy links
4953                  */
4954                 if (!dc->links[index]->ddc->ddc_pin) {
4955                         if (dc->links[index]->ddc_hw_inst == dpia_port_index) {
4956                                 link_index = index;
4957                                 break;
4958                         }
4959                 }
4960         }
4961         ASSERT(link_index != 0xFF);
4962         return link_index;
4963 }
4964
4965 /**
4966  * dc_process_dmub_set_config_async - Submits set_config command
4967  *
4968  * @dc: [in] dc structure
4969  * @link_index: [in] link_index: link index
4970  * @payload: [in] aux payload
4971  * @notify: [out] set_config immediate reply
4972  *
4973  * Submits set_config command to dmub via inbox message.
4974  *
4975  * Return:
4976  * True if successful, False if failure
4977  */
4978 bool dc_process_dmub_set_config_async(struct dc *dc,
4979                                 uint32_t link_index,
4980                                 struct set_config_cmd_payload *payload,
4981                                 struct dmub_notification *notify)
4982 {
4983         union dmub_rb_cmd cmd = {0};
4984         bool is_cmd_complete = true;
4985
4986         /* prepare SET_CONFIG command */
4987         cmd.set_config_access.header.type = DMUB_CMD__DPIA;
4988         cmd.set_config_access.header.sub_type = DMUB_CMD__DPIA_SET_CONFIG_ACCESS;
4989
4990         cmd.set_config_access.set_config_control.instance = dc->links[link_index]->ddc_hw_inst;
4991         cmd.set_config_access.set_config_control.cmd_pkt.msg_type = payload->msg_type;
4992         cmd.set_config_access.set_config_control.cmd_pkt.msg_data = payload->msg_data;
4993
4994         if (!dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) {
4995                 /* command is not processed by dmub */
4996                 notify->sc_status = SET_CONFIG_UNKNOWN_ERROR;
4997                 return is_cmd_complete;
4998         }
4999
5000         /* command processed by dmub, if ret_status is 1, it is completed instantly */
5001         if (cmd.set_config_access.header.ret_status == 1)
5002                 notify->sc_status = cmd.set_config_access.set_config_control.immed_status;
5003         else
5004                 /* cmd pending, will receive notification via outbox */
5005                 is_cmd_complete = false;
5006
5007         return is_cmd_complete;
5008 }
5009
5010 /**
5011  * dc_process_dmub_set_mst_slots - Submits MST solt allocation
5012  *
5013  * @dc: [in] dc structure
5014  * @link_index: [in] link index
5015  * @mst_alloc_slots: [in] mst slots to be allotted
5016  * @mst_slots_in_use: [out] mst slots in use returned in failure case
5017  *
5018  * Submits mst slot allocation command to dmub via inbox message
5019  *
5020  * Return:
5021  * DC_OK if successful, DC_ERROR if failure
5022  */
5023 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc,
5024                                 uint32_t link_index,
5025                                 uint8_t mst_alloc_slots,
5026                                 uint8_t *mst_slots_in_use)
5027 {
5028         union dmub_rb_cmd cmd = {0};
5029
5030         /* prepare MST_ALLOC_SLOTS command */
5031         cmd.set_mst_alloc_slots.header.type = DMUB_CMD__DPIA;
5032         cmd.set_mst_alloc_slots.header.sub_type = DMUB_CMD__DPIA_MST_ALLOC_SLOTS;
5033
5034         cmd.set_mst_alloc_slots.mst_slots_control.instance = dc->links[link_index]->ddc_hw_inst;
5035         cmd.set_mst_alloc_slots.mst_slots_control.mst_alloc_slots = mst_alloc_slots;
5036
5037         if (!dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))
5038                 /* command is not processed by dmub */
5039                 return DC_ERROR_UNEXPECTED;
5040
5041         /* command processed by dmub, if ret_status is 1 */
5042         if (cmd.set_config_access.header.ret_status != 1)
5043                 /* command processing error */
5044                 return DC_ERROR_UNEXPECTED;
5045
5046         /* command processed and we have a status of 2, mst not enabled in dpia */
5047         if (cmd.set_mst_alloc_slots.mst_slots_control.immed_status == 2)
5048                 return DC_FAIL_UNSUPPORTED_1;
5049
5050         /* previously configured mst alloc and used slots did not match */
5051         if (cmd.set_mst_alloc_slots.mst_slots_control.immed_status == 3) {
5052                 *mst_slots_in_use = cmd.set_mst_alloc_slots.mst_slots_control.mst_slots_in_use;
5053                 return DC_NOT_SUPPORTED;
5054         }
5055
5056         return DC_OK;
5057 }
5058
5059 /**
5060  * dc_process_dmub_dpia_hpd_int_enable - Submits DPIA DPD interruption
5061  *
5062  * @dc: [in] dc structure
5063  * @hpd_int_enable: [in] 1 for hpd int enable, 0 to disable
5064  *
5065  * Submits dpia hpd int enable command to dmub via inbox message
5066  */
5067 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc,
5068                                 uint32_t hpd_int_enable)
5069 {
5070         union dmub_rb_cmd cmd = {0};
5071
5072         cmd.dpia_hpd_int_enable.header.type = DMUB_CMD__DPIA_HPD_INT_ENABLE;
5073         cmd.dpia_hpd_int_enable.enable = hpd_int_enable;
5074
5075         dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
5076
5077         DC_LOG_DEBUG("%s: hpd_int_enable(%d)\n", __func__, hpd_int_enable);
5078 }
5079
5080 /**
5081  * dc_print_dmub_diagnostic_data - Print DMUB diagnostic data for debugging
5082  *
5083  * @dc: [in] dc structure
5084  *
5085  *
5086  */
5087 void dc_print_dmub_diagnostic_data(const struct dc *dc)
5088 {
5089         dc_dmub_srv_log_diagnostic_data(dc->ctx->dmub_srv);
5090 }
5091
5092 /**
5093  * dc_disable_accelerated_mode - disable accelerated mode
5094  * @dc: dc structure
5095  */
5096 void dc_disable_accelerated_mode(struct dc *dc)
5097 {
5098         bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 0);
5099 }
5100
5101
5102 /**
5103  *  dc_notify_vsync_int_state - notifies vsync enable/disable state
5104  *  @dc: dc structure
5105  *  @stream: stream where vsync int state changed
5106  *  @enable: whether vsync is enabled or disabled
5107  *
5108  *  Called when vsync is enabled/disabled Will notify DMUB to start/stop ABM
5109  *  interrupts after steady state is reached.
5110  */
5111 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable)
5112 {
5113         int i;
5114         int edp_num;
5115         struct pipe_ctx *pipe = NULL;
5116         struct dc_link *link = stream->sink->link;
5117         struct dc_link *edp_links[MAX_NUM_EDP];
5118
5119
5120         if (link->psr_settings.psr_feature_enabled)
5121                 return;
5122
5123         /*find primary pipe associated with stream*/
5124         for (i = 0; i < MAX_PIPES; i++) {
5125                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
5126
5127                 if (pipe->stream == stream && pipe->stream_res.tg)
5128                         break;
5129         }
5130
5131         if (i == MAX_PIPES) {
5132                 ASSERT(0);
5133                 return;
5134         }
5135
5136         dc_get_edp_links(dc, edp_links, &edp_num);
5137
5138         /* Determine panel inst */
5139         for (i = 0; i < edp_num; i++) {
5140                 if (edp_links[i] == link)
5141                         break;
5142         }
5143
5144         if (i == edp_num) {
5145                 return;
5146         }
5147
5148         if (pipe->stream_res.abm && pipe->stream_res.abm->funcs->set_abm_pause)
5149                 pipe->stream_res.abm->funcs->set_abm_pause(pipe->stream_res.abm, !enable, i, pipe->stream_res.tg->inst);
5150 }