drivers/gpu/drm/amd/display/dc/core/dc.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  */
  24
  25 #include <linux/slab.h>
  26 #include <linux/mm.h>
  27
  28 #include "dm_services.h"
  29
  30 #include "dc.h"
  31
  32 #include "core_status.h"
  33 #include "core_types.h"
  34 #include "hw_sequencer.h"
  35 #include "dce/dce_hwseq.h"
  36
  37 #include "resource.h"
  38
  39 #include "clk_mgr.h"
  40 #include "clock_source.h"
  41 #include "dc_bios_types.h"
  42
  43 #include "bios_parser_interface.h"
  44 #include "bios/bios_parser_helper.h"
  45 #include "include/irq_service_interface.h"
  46 #include "transform.h"
  47 #include "dmcu.h"
  48 #include "dpp.h"
  49 #include "timing_generator.h"
  50 #include "abm.h"
  51 #include "virtual/virtual_link_encoder.h"
  52 #include "hubp.h"
  53
  54 #include "link_hwss.h"
  55 #include "link_encoder.h"
  56 #include "link_enc_cfg.h"
  57
  58 #include "dc_link.h"
  59 #include "dc_link_ddc.h"
  60 #include "dm_helpers.h"
  61 #include "mem_input.h"
  62
  63 #include "dc_link_dp.h"
  64 #include "dc_dmub_srv.h"
  65
  66 #include "dsc.h"
  67
  68 #include "vm_helper.h"
  69
  70 #include "dce/dce_i2c.h"
  71
  72 #include "dmub/dmub_srv.h"
  73
  74 #include "i2caux_interface.h"
  75 #include "dce/dmub_hw_lock_mgr.h"
  76
  77 #include "dc_trace.h"
  78
  79 #define CTX \
  80         dc->ctx
  81
  82 #define DC_LOGGER \
  83         dc->ctx->logger
  84
  85 static const char DC_BUILD_ID[] = "production-build";
  86
  87 /**
  88  * DOC: Overview
  89  *
  90  * DC is the OS-agnostic component of the amdgpu DC driver.
  91  *
  92  * DC maintains and validates a set of structs representing the state of the
  93  * driver and writes that state to AMD hardware
  94  *
  95  * Main DC HW structs:
  96  *
  97  * struct dc - The central struct.  One per driver.  Created on driver load,
  98  * destroyed on driver unload.
  99  *
 100  * struct dc_context - One per driver.
 101  * Used as a backpointer by most other structs in dc.
 102  *
 103  * struct dc_link - One per connector (the physical DP, HDMI, miniDP, or eDP
 104  * plugpoints).  Created on driver load, destroyed on driver unload.
 105  *
 106  * struct dc_sink - One per display.  Created on boot or hotplug.
 107  * Destroyed on shutdown or hotunplug.  A dc_link can have a local sink
 108  * (the display directly attached).  It may also have one or more remote
 109  * sinks (in the Multi-Stream Transport case)
 110  *
 111  * struct resource_pool - One per driver.  Represents the hw blocks not in the
 112  * main pipeline.  Not directly accessible by dm.
 113  *
 114  * Main dc state structs:
 115  *
 116  * These structs can be created and destroyed as needed.  There is a full set of
 117  * these structs in dc->current_state representing the currently programmed state.
 118  *
 119  * struct dc_state - The global DC state to track global state information,
 120  * such as bandwidth values.
 121  *
 122  * struct dc_stream_state - Represents the hw configuration for the pipeline from
 123  * a framebuffer to a display.  Maps one-to-one with dc_sink.
 124  *
 125  * struct dc_plane_state - Represents a framebuffer.  Each stream has at least one,
 126  * and may have more in the Multi-Plane Overlay case.
 127  *
 128  * struct resource_context - Represents the programmable state of everything in
 129  * the resource_pool.  Not directly accessible by dm.
 130  *
 131  * struct pipe_ctx - A member of struct resource_context.  Represents the
 132  * internal hardware pipeline components.  Each dc_plane_state has either
 133  * one or two (in the pipe-split case).
 134  */
 135
 136 /*******************************************************************************
 137  * Private functions
 138  ******************************************************************************/
 139
 140 static inline void elevate_update_type(enum surface_update_type *original, enum surface_update_type new)
 141 {
 142         if (new > *original)
 143                 *original = new;
 144 }
 145
 146 static void destroy_links(struct dc *dc)
 147 {
 148         uint32_t i;
 149
 150         for (i = 0; i < dc->link_count; i++) {
 151                 if (NULL != dc->links[i])
 152                         link_destroy(&dc->links[i]);
 153         }
 154 }
 155
 156 static uint32_t get_num_of_internal_disp(struct dc_link **links, uint32_t num_links)
 157 {
 158         int i;
 159         uint32_t count = 0;
 160
 161         for (i = 0; i < num_links; i++) {
 162                 if (links[i]->connector_signal == SIGNAL_TYPE_EDP ||
 163                                 links[i]->is_internal_display)
 164                         count++;
 165         }
 166
 167         return count;
 168 }
 169
 170 static int get_seamless_boot_stream_count(struct dc_state *ctx)
 171 {
 172         uint8_t i;
 173         uint8_t seamless_boot_stream_count = 0;
 174
 175         for (i = 0; i < ctx->stream_count; i++)
 176                 if (ctx->streams[i]->apply_seamless_boot_optimization)
 177                         seamless_boot_stream_count++;
 178
 179         return seamless_boot_stream_count;
 180 }
 181
 182 static bool create_links(
 183                 struct dc *dc,
 184                 uint32_t num_virtual_links)
 185 {
 186         int i;
 187         int connectors_num;
 188         struct dc_bios *bios = dc->ctx->dc_bios;
 189
 190         dc->link_count = 0;
 191
 192         connectors_num = bios->funcs->get_connectors_number(bios);
 193
 194         DC_LOG_DC("BIOS object table - number of connectors: %d", connectors_num);
 195
 196         if (connectors_num > ENUM_ID_COUNT) {
 197                 dm_error(
 198                         "DC: Number of connectors %d exceeds maximum of %d!\n",
 199                         connectors_num,
 200                         ENUM_ID_COUNT);
 201                 return false;
 202         }
 203
 204         dm_output_to_console(
 205                 "DC: %s: connectors_num: physical:%d, virtual:%d\n",
 206                 __func__,
 207                 connectors_num,
 208                 num_virtual_links);
 209
 210         for (i = 0; i < connectors_num; i++) {
 211                 struct link_init_data link_init_params = {0};
 212                 struct dc_link *link;
 213
 214                 DC_LOG_DC("BIOS object table - printing link object info for connector number: %d, link_index: %d", i, dc->link_count);
 215
 216                 link_init_params.ctx = dc->ctx;
 217                 /* next BIOS object table connector */
 218                 link_init_params.connector_index = i;
 219                 link_init_params.link_index = dc->link_count;
 220                 link_init_params.dc = dc;
 221                 link = link_create(&link_init_params);
 222
 223                 if (link) {
 224                                 dc->links[dc->link_count] = link;
 225                                 link->dc = dc;
 226                                 ++dc->link_count;
 227                 }
 228         }
 229
 230         DC_LOG_DC("BIOS object table - end");
 231
 232         for (i = 0; i < num_virtual_links; i++) {
 233                 struct dc_link *link = kzalloc(sizeof(*link), GFP_KERNEL);
 234                 struct encoder_init_data enc_init = {0};
 235
 236                 if (link == NULL) {
 237                         BREAK_TO_DEBUGGER();
 238                         goto failed_alloc;
 239                 }
 240
 241                 link->link_index = dc->link_count;
 242                 dc->links[dc->link_count] = link;
 243                 dc->link_count++;
 244
 245                 link->ctx = dc->ctx;
 246                 link->dc = dc;
 247                 link->connector_signal = SIGNAL_TYPE_VIRTUAL;
 248                 link->link_id.type = OBJECT_TYPE_CONNECTOR;
 249                 link->link_id.id = CONNECTOR_ID_VIRTUAL;
 250                 link->link_id.enum_id = ENUM_ID_1;
 251                 link->link_enc = kzalloc(sizeof(*link->link_enc), GFP_KERNEL);
 252
 253                 if (!link->link_enc) {
 254                         BREAK_TO_DEBUGGER();
 255                         goto failed_alloc;
 256                 }
 257
 258                 link->link_status.dpcd_caps = &link->dpcd_caps;
 259
 260                 enc_init.ctx = dc->ctx;
 261                 enc_init.channel = CHANNEL_ID_UNKNOWN;
 262                 enc_init.hpd_source = HPD_SOURCEID_UNKNOWN;
 263                 enc_init.transmitter = TRANSMITTER_UNKNOWN;
 264                 enc_init.connector = link->link_id;
 265                 enc_init.encoder.type = OBJECT_TYPE_ENCODER;
 266                 enc_init.encoder.id = ENCODER_ID_INTERNAL_VIRTUAL;
 267                 enc_init.encoder.enum_id = ENUM_ID_1;
 268                 virtual_link_encoder_construct(link->link_enc, &enc_init);
 269         }
 270
 271         dc->caps.num_of_internal_disp = get_num_of_internal_disp(dc->links, dc->link_count);
 272
 273         return true;
 274
 275 failed_alloc:
 276         return false;
 277 }
 278
 279 static struct dc_perf_trace *dc_perf_trace_create(void)
 280 {
 281         return kzalloc(sizeof(struct dc_perf_trace), GFP_KERNEL);
 282 }
 283
 284 static void dc_perf_trace_destroy(struct dc_perf_trace **perf_trace)
 285 {
 286         kfree(*perf_trace);
 287         *perf_trace = NULL;
 288 }
 289
 290 /**
 291  *  dc_stream_adjust_vmin_vmax:
 292  *
 293  *  Looks up the pipe context of dc_stream_state and updates the
 294  *  vertical_total_min and vertical_total_max of the DRR, Dynamic Refresh
 295  *  Rate, which is a power-saving feature that targets reducing panel
 296  *  refresh rate while the screen is static
 297  *
 298  *  @dc:     dc reference
 299  *  @stream: Initial dc stream state
 300  *  @adjust: Updated parameters for vertical_total_min and vertical_total_max
 301  */
 302 bool dc_stream_adjust_vmin_vmax(struct dc *dc,
 303                 struct dc_stream_state *stream,
 304                 struct dc_crtc_timing_adjust *adjust)
 305 {
 306         int i;
 307         bool ret = false;
 308
 309         stream->adjust.v_total_max = adjust->v_total_max;
 310         stream->adjust.v_total_mid = adjust->v_total_mid;
 311         stream->adjust.v_total_mid_frame_num = adjust->v_total_mid_frame_num;
 312         stream->adjust.v_total_min = adjust->v_total_min;
 313
 314         for (i = 0; i < MAX_PIPES; i++) {
 315                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 316
 317                 if (pipe->stream == stream && pipe->stream_res.tg) {
 318                         dc->hwss.set_drr(&pipe,
 319                                         1,
 320                                         *adjust);
 321
 322                         ret = true;
 323                 }
 324         }
 325         return ret;
 326 }
 327
 328 /**
 329  *****************************************************************************
 330  *  Function: dc_stream_get_last_vrr_vtotal
 331  *
 332  *  @brief
 333  *     Looks up the pipe context of dc_stream_state and gets the
 334  *     last VTOTAL used by DRR (Dynamic Refresh Rate)
 335  *
 336  *  @param [in] dc: dc reference
 337  *  @param [in] stream: Initial dc stream state
 338  *  @param [in] adjust: Updated parameters for vertical_total_min and
 339  *  vertical_total_max
 340  *****************************************************************************
 341  */
 342 bool dc_stream_get_last_used_drr_vtotal(struct dc *dc,
 343                 struct dc_stream_state *stream,
 344                 uint32_t *refresh_rate)
 345 {
 346         bool status = false;
 347
 348         int i = 0;
 349
 350         for (i = 0; i < MAX_PIPES; i++) {
 351                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 352
 353                 if (pipe->stream == stream && pipe->stream_res.tg) {
 354                         /* Only execute if a function pointer has been defined for
 355                          * the DC version in question
 356                          */
 357                         if (pipe->stream_res.tg->funcs->get_last_used_drr_vtotal) {
 358                                 pipe->stream_res.tg->funcs->get_last_used_drr_vtotal(pipe->stream_res.tg, refresh_rate);
 359
 360                                 status = true;
 361
 362                                 break;
 363                         }
 364                 }
 365         }
 366
 367         return status;
 368 }
 369
 370 bool dc_stream_get_crtc_position(struct dc *dc,
 371                 struct dc_stream_state **streams, int num_streams,
 372                 unsigned int *v_pos, unsigned int *nom_v_pos)
 373 {
 374         /* TODO: Support multiple streams */
 375         const struct dc_stream_state *stream = streams[0];
 376         int i;
 377         bool ret = false;
 378         struct crtc_position position;
 379
 380         for (i = 0; i < MAX_PIPES; i++) {
 381                 struct pipe_ctx *pipe =
 382                                 &dc->current_state->res_ctx.pipe_ctx[i];
 383
 384                 if (pipe->stream == stream && pipe->stream_res.stream_enc) {
 385                         dc->hwss.get_position(&pipe, 1, &position);
 386
 387                         *v_pos = position.vertical_count;
 388                         *nom_v_pos = position.nominal_vcount;
 389                         ret = true;
 390                 }
 391         }
 392         return ret;
 393 }
 394
 395 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
 396 bool dc_stream_forward_dmcu_crc_window(struct dc *dc, struct dc_stream_state *stream,
 397                              struct crc_params *crc_window)
 398 {
 399         int i;
 400         struct dmcu *dmcu = dc->res_pool->dmcu;
 401         struct pipe_ctx *pipe;
 402         struct crc_region tmp_win, *crc_win;
 403         struct otg_phy_mux mapping_tmp, *mux_mapping;
 404
 405         /*crc window can't be null*/
 406         if (!crc_window)
 407                 return false;
 408
 409         if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu))) {
 410                 crc_win = &tmp_win;
 411                 mux_mapping = &mapping_tmp;
 412                 /*set crc window*/
 413                 tmp_win.x_start = crc_window->windowa_x_start;
 414                 tmp_win.y_start = crc_window->windowa_y_start;
 415                 tmp_win.x_end = crc_window->windowa_x_end;
 416                 tmp_win.y_end = crc_window->windowa_y_end;
 417
 418                 for (i = 0; i < MAX_PIPES; i++) {
 419                         pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 420                         if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe)
 421                                 break;
 422                 }
 423
 424                 /* Stream not found */
 425                 if (i == MAX_PIPES)
 426                         return false;
 427
 428
 429                 /*set mux routing info*/
 430                 mapping_tmp.phy_output_num = stream->link->link_enc_hw_inst;
 431                 mapping_tmp.otg_output_num = pipe->stream_res.tg->inst;
 432
 433                 dmcu->funcs->forward_crc_window(dmcu, crc_win, mux_mapping);
 434         } else {
 435                 DC_LOG_DC("dmcu is not initialized");
 436                 return false;
 437         }
 438
 439         return true;
 440 }
 441
 442 bool dc_stream_stop_dmcu_crc_win_update(struct dc *dc, struct dc_stream_state *stream)
 443 {
 444         int i;
 445         struct dmcu *dmcu = dc->res_pool->dmcu;
 446         struct pipe_ctx *pipe;
 447         struct otg_phy_mux mapping_tmp, *mux_mapping;
 448
 449         if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu))) {
 450                 mux_mapping = &mapping_tmp;
 451
 452                 for (i = 0; i < MAX_PIPES; i++) {
 453                         pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 454                         if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe)
 455                                 break;
 456                 }
 457
 458                 /* Stream not found */
 459                 if (i == MAX_PIPES)
 460                         return false;
 461
 462
 463                 /*set mux routing info*/
 464                 mapping_tmp.phy_output_num = stream->link->link_enc_hw_inst;
 465                 mapping_tmp.otg_output_num = pipe->stream_res.tg->inst;
 466
 467                 dmcu->funcs->stop_crc_win_update(dmcu, mux_mapping);
 468         } else {
 469                 DC_LOG_DC("dmcu is not initialized");
 470                 return false;
 471         }
 472
 473         return true;
 474 }
 475 #endif
 476
 477 /**
 478  * dc_stream_configure_crc() - Configure CRC capture for the given stream.
 479  * @dc: DC Object
 480  * @stream: The stream to configure CRC on.
 481  * @enable: Enable CRC if true, disable otherwise.
 482  * @crc_window: CRC window (x/y start/end) information
 483  * @continuous: Capture CRC on every frame if true. Otherwise, only capture
 484  *              once.
 485  *
 486  * By default, only CRC0 is configured, and the entire frame is used to
 487  * calculate the crc.
 488  */
 489 bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,
 490                              struct crc_params *crc_window, bool enable, bool continuous)
 491 {
 492         int i;
 493         struct pipe_ctx *pipe;
 494         struct crc_params param;
 495         struct timing_generator *tg;
 496
 497         for (i = 0; i < MAX_PIPES; i++) {
 498                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 499                 if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe)
 500                         break;
 501         }
 502         /* Stream not found */
 503         if (i == MAX_PIPES)
 504                 return false;
 505
 506         /* By default, capture the full frame */
 507         param.windowa_x_start = 0;
 508         param.windowa_y_start = 0;
 509         param.windowa_x_end = pipe->stream->timing.h_addressable;
 510         param.windowa_y_end = pipe->stream->timing.v_addressable;
 511         param.windowb_x_start = 0;
 512         param.windowb_y_start = 0;
 513         param.windowb_x_end = pipe->stream->timing.h_addressable;
 514         param.windowb_y_end = pipe->stream->timing.v_addressable;
 515
 516         if (crc_window) {
 517                 param.windowa_x_start = crc_window->windowa_x_start;
 518                 param.windowa_y_start = crc_window->windowa_y_start;
 519                 param.windowa_x_end = crc_window->windowa_x_end;
 520                 param.windowa_y_end = crc_window->windowa_y_end;
 521                 param.windowb_x_start = crc_window->windowb_x_start;
 522                 param.windowb_y_start = crc_window->windowb_y_start;
 523                 param.windowb_x_end = crc_window->windowb_x_end;
 524                 param.windowb_y_end = crc_window->windowb_y_end;
 525         }
 526
 527         param.dsc_mode = pipe->stream->timing.flags.DSC ? 1:0;
 528         param.odm_mode = pipe->next_odm_pipe ? 1:0;
 529
 530         /* Default to the union of both windows */
 531         param.selection = UNION_WINDOW_A_B;
 532         param.continuous_mode = continuous;
 533         param.enable = enable;
 534
 535         tg = pipe->stream_res.tg;
 536
 537         /* Only call if supported */
 538         if (tg->funcs->configure_crc)
 539                 return tg->funcs->configure_crc(tg, &param);
 540         DC_LOG_WARNING("CRC capture not supported.");
 541         return false;
 542 }
 543
 544 /**
 545  * dc_stream_get_crc() - Get CRC values for the given stream.
 546  * @dc: DC object
 547  * @stream: The DC stream state of the stream to get CRCs from.
 548  * @r_cr: CRC value for the first of the 3 channels stored here.
 549  * @g_y:  CRC value for the second of the 3 channels stored here.
 550  * @b_cb: CRC value for the third of the 3 channels stored here.
 551  *
 552  * dc_stream_configure_crc needs to be called beforehand to enable CRCs.
 553  * Return false if stream is not found, or if CRCs are not enabled.
 554  */
 555 bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream,
 556                        uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)
 557 {
 558         int i;
 559         struct pipe_ctx *pipe;
 560         struct timing_generator *tg;
 561
 562         for (i = 0; i < MAX_PIPES; i++) {
 563                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 564                 if (pipe->stream == stream)
 565                         break;
 566         }
 567         /* Stream not found */
 568         if (i == MAX_PIPES)
 569                 return false;
 570
 571         tg = pipe->stream_res.tg;
 572
 573         if (tg->funcs->get_crc)
 574                 return tg->funcs->get_crc(tg, r_cr, g_y, b_cb);
 575         DC_LOG_WARNING("CRC capture not supported.");
 576         return false;
 577 }
 578
 579 void dc_stream_set_dyn_expansion(struct dc *dc, struct dc_stream_state *stream,
 580                 enum dc_dynamic_expansion option)
 581 {
 582         /* OPP FMT dyn expansion updates*/
 583         int i;
 584         struct pipe_ctx *pipe_ctx;
 585
 586         for (i = 0; i < MAX_PIPES; i++) {
 587                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
 588                                 == stream) {
 589                         pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 590                         pipe_ctx->stream_res.opp->dyn_expansion = option;
 591                         pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
 592                                         pipe_ctx->stream_res.opp,
 593                                         COLOR_SPACE_YCBCR601,
 594                                         stream->timing.display_color_depth,
 595                                         stream->signal);
 596                 }
 597         }
 598 }
 599
 600 void dc_stream_set_dither_option(struct dc_stream_state *stream,
 601                 enum dc_dither_option option)
 602 {
 603         struct bit_depth_reduction_params params;
 604         struct dc_link *link = stream->link;
 605         struct pipe_ctx *pipes = NULL;
 606         int i;
 607
 608         for (i = 0; i < MAX_PIPES; i++) {
 609                 if (link->dc->current_state->res_ctx.pipe_ctx[i].stream ==
 610                                 stream) {
 611                         pipes = &link->dc->current_state->res_ctx.pipe_ctx[i];
 612                         break;
 613                 }
 614         }
 615
 616         if (!pipes)
 617                 return;
 618         if (option > DITHER_OPTION_MAX)
 619                 return;
 620
 621         stream->dither_option = option;
 622
 623         memset(&params, 0, sizeof(params));
 624         resource_build_bit_depth_reduction_params(stream, &params);
 625         stream->bit_depth_params = params;
 626
 627         if (pipes->plane_res.xfm &&
 628             pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth) {
 629                 pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
 630                         pipes->plane_res.xfm,
 631                         pipes->plane_res.scl_data.lb_params.depth,
 632                         &stream->bit_depth_params);
 633         }
 634
 635         pipes->stream_res.opp->funcs->
 636                 opp_program_bit_depth_reduction(pipes->stream_res.opp, &params);
 637 }
 638
 639 bool dc_stream_set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream)
 640 {
 641         int i;
 642         bool ret = false;
 643         struct pipe_ctx *pipes;
 644
 645         for (i = 0; i < MAX_PIPES; i++) {
 646                 if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) {
 647                         pipes = &dc->current_state->res_ctx.pipe_ctx[i];
 648                         dc->hwss.program_gamut_remap(pipes);
 649                         ret = true;
 650                 }
 651         }
 652
 653         return ret;
 654 }
 655
 656 bool dc_stream_program_csc_matrix(struct dc *dc, struct dc_stream_state *stream)
 657 {
 658         int i;
 659         bool ret = false;
 660         struct pipe_ctx *pipes;
 661
 662         for (i = 0; i < MAX_PIPES; i++) {
 663                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
 664                                 == stream) {
 665
 666                         pipes = &dc->current_state->res_ctx.pipe_ctx[i];
 667                         dc->hwss.program_output_csc(dc,
 668                                         pipes,
 669                                         stream->output_color_space,
 670                                         stream->csc_color_matrix.matrix,
 671                                         pipes->stream_res.opp->inst);
 672                         ret = true;
 673                 }
 674         }
 675
 676         return ret;
 677 }
 678
 679 void dc_stream_set_static_screen_params(struct dc *dc,
 680                 struct dc_stream_state **streams,
 681                 int num_streams,
 682                 const struct dc_static_screen_params *params)
 683 {
 684         int i, j;
 685         struct pipe_ctx *pipes_affected[MAX_PIPES];
 686         int num_pipes_affected = 0;
 687
 688         for (i = 0; i < num_streams; i++) {
 689                 struct dc_stream_state *stream = streams[i];
 690
 691                 for (j = 0; j < MAX_PIPES; j++) {
 692                         if (dc->current_state->res_ctx.pipe_ctx[j].stream
 693                                         == stream) {
 694                                 pipes_affected[num_pipes_affected++] =
 695                                                 &dc->current_state->res_ctx.pipe_ctx[j];
 696                         }
 697                 }
 698         }
 699
 700         dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, params);
 701 }
 702
 703 static void dc_destruct(struct dc *dc)
 704 {
 705         if (dc->current_state) {
 706                 dc_release_state(dc->current_state);
 707                 dc->current_state = NULL;
 708         }
 709
 710         destroy_links(dc);
 711
 712         if (dc->clk_mgr) {
 713                 dc_destroy_clk_mgr(dc->clk_mgr);
 714                 dc->clk_mgr = NULL;
 715         }
 716
 717         dc_destroy_resource_pool(dc);
 718
 719         if (dc->ctx->gpio_service)
 720                 dal_gpio_service_destroy(&dc->ctx->gpio_service);
 721
 722         if (dc->ctx->created_bios)
 723                 dal_bios_parser_destroy(&dc->ctx->dc_bios);
 724
 725         dc_perf_trace_destroy(&dc->ctx->perf_trace);
 726
 727         kfree(dc->ctx);
 728         dc->ctx = NULL;
 729
 730         kfree(dc->bw_vbios);
 731         dc->bw_vbios = NULL;
 732
 733         kfree(dc->bw_dceip);
 734         dc->bw_dceip = NULL;
 735
 736 #ifdef CONFIG_DRM_AMD_DC_DCN
 737         kfree(dc->dcn_soc);
 738         dc->dcn_soc = NULL;
 739
 740         kfree(dc->dcn_ip);
 741         dc->dcn_ip = NULL;
 742
 743 #endif
 744         kfree(dc->vm_helper);
 745         dc->vm_helper = NULL;
 746
 747 }
 748
 749 static bool dc_construct_ctx(struct dc *dc,
 750                 const struct dc_init_data *init_params)
 751 {
 752         struct dc_context *dc_ctx;
 753         enum dce_version dc_version = DCE_VERSION_UNKNOWN;
 754
 755         dc_ctx = kzalloc(sizeof(*dc_ctx), GFP_KERNEL);
 756         if (!dc_ctx)
 757                 return false;
 758
 759         dc_ctx->cgs_device = init_params->cgs_device;
 760         dc_ctx->driver_context = init_params->driver;
 761         dc_ctx->dc = dc;
 762         dc_ctx->asic_id = init_params->asic_id;
 763         dc_ctx->dc_sink_id_count = 0;
 764         dc_ctx->dc_stream_id_count = 0;
 765         dc_ctx->dce_environment = init_params->dce_environment;
 766
 767         /* Create logger */
 768
 769         dc_version = resource_parse_asic_id(init_params->asic_id);
 770         dc_ctx->dce_version = dc_version;
 771
 772         dc_ctx->perf_trace = dc_perf_trace_create();
 773         if (!dc_ctx->perf_trace) {
 774                 ASSERT_CRITICAL(false);
 775                 return false;
 776         }
 777
 778         dc->ctx = dc_ctx;
 779
 780         return true;
 781 }
 782
 783 static bool dc_construct(struct dc *dc,
 784                 const struct dc_init_data *init_params)
 785 {
 786         struct dc_context *dc_ctx;
 787         struct bw_calcs_dceip *dc_dceip;
 788         struct bw_calcs_vbios *dc_vbios;
 789 #ifdef CONFIG_DRM_AMD_DC_DCN
 790         struct dcn_soc_bounding_box *dcn_soc;
 791         struct dcn_ip_params *dcn_ip;
 792 #endif
 793
 794         dc->config = init_params->flags;
 795
 796         // Allocate memory for the vm_helper
 797         dc->vm_helper = kzalloc(sizeof(struct vm_helper), GFP_KERNEL);
 798         if (!dc->vm_helper) {
 799                 dm_error("%s: failed to create dc->vm_helper\n", __func__);
 800                 goto fail;
 801         }
 802
 803         memcpy(&dc->bb_overrides, &init_params->bb_overrides, sizeof(dc->bb_overrides));
 804
 805         dc_dceip = kzalloc(sizeof(*dc_dceip), GFP_KERNEL);
 806         if (!dc_dceip) {
 807                 dm_error("%s: failed to create dceip\n", __func__);
 808                 goto fail;
 809         }
 810
 811         dc->bw_dceip = dc_dceip;
 812
 813         dc_vbios = kzalloc(sizeof(*dc_vbios), GFP_KERNEL);
 814         if (!dc_vbios) {
 815                 dm_error("%s: failed to create vbios\n", __func__);
 816                 goto fail;
 817         }
 818
 819         dc->bw_vbios = dc_vbios;
 820 #ifdef CONFIG_DRM_AMD_DC_DCN
 821         dcn_soc = kzalloc(sizeof(*dcn_soc), GFP_KERNEL);
 822         if (!dcn_soc) {
 823                 dm_error("%s: failed to create dcn_soc\n", __func__);
 824                 goto fail;
 825         }
 826
 827         dc->dcn_soc = dcn_soc;
 828
 829         dcn_ip = kzalloc(sizeof(*dcn_ip), GFP_KERNEL);
 830         if (!dcn_ip) {
 831                 dm_error("%s: failed to create dcn_ip\n", __func__);
 832                 goto fail;
 833         }
 834
 835         dc->dcn_ip = dcn_ip;
 836 #endif
 837
 838         if (!dc_construct_ctx(dc, init_params)) {
 839                 dm_error("%s: failed to create ctx\n", __func__);
 840                 goto fail;
 841         }
 842
 843         dc_ctx = dc->ctx;
 844
 845         /* Resource should construct all asic specific resources.
 846          * This should be the only place where we need to parse the asic id
 847          */
 848         if (init_params->vbios_override)
 849                 dc_ctx->dc_bios = init_params->vbios_override;
 850         else {
 851                 /* Create BIOS parser */
 852                 struct bp_init_data bp_init_data;
 853
 854                 bp_init_data.ctx = dc_ctx;
 855                 bp_init_data.bios = init_params->asic_id.atombios_base_address;
 856
 857                 dc_ctx->dc_bios = dal_bios_parser_create(
 858                                 &bp_init_data, dc_ctx->dce_version);
 859
 860                 if (!dc_ctx->dc_bios) {
 861                         ASSERT_CRITICAL(false);
 862                         goto fail;
 863                 }
 864
 865                 dc_ctx->created_bios = true;
 866         }
 867
 868         dc->vendor_signature = init_params->vendor_signature;
 869
 870         /* Create GPIO service */
 871         dc_ctx->gpio_service = dal_gpio_service_create(
 872                         dc_ctx->dce_version,
 873                         dc_ctx->dce_environment,
 874                         dc_ctx);
 875
 876         if (!dc_ctx->gpio_service) {
 877                 ASSERT_CRITICAL(false);
 878                 goto fail;
 879         }
 880
 881         dc->res_pool = dc_create_resource_pool(dc, init_params, dc_ctx->dce_version);
 882         if (!dc->res_pool)
 883                 goto fail;
 884
 885         /* set i2c speed if not done by the respective dcnxxx__resource.c */
 886         if (dc->caps.i2c_speed_in_khz_hdcp == 0)
 887                 dc->caps.i2c_speed_in_khz_hdcp = dc->caps.i2c_speed_in_khz;
 888
 889         dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg);
 890         if (!dc->clk_mgr)
 891                 goto fail;
 892 #ifdef CONFIG_DRM_AMD_DC_DCN
 893         dc->clk_mgr->force_smu_not_present = init_params->force_smu_not_present;
 894 #endif
 895
 896         if (dc->res_pool->funcs->update_bw_bounding_box)
 897                 dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params);
 898
 899         /* Creation of current_state must occur after dc->dml
 900          * is initialized in dc_create_resource_pool because
 901          * on creation it copies the contents of dc->dml
 902          */
 903
 904         dc->current_state = dc_create_state(dc);
 905
 906         if (!dc->current_state) {
 907                 dm_error("%s: failed to create validate ctx\n", __func__);
 908                 goto fail;
 909         }
 910
 911         dc_resource_state_construct(dc, dc->current_state);
 912
 913         if (!create_links(dc, init_params->num_virtual_links))
 914                 goto fail;
 915
 916         /* Initialise DIG link encoder resource tracking variables. */
 917         link_enc_cfg_init(dc, dc->current_state);
 918
 919         return true;
 920
 921 fail:
 922         return false;
 923 }
 924
 925 static void disable_all_writeback_pipes_for_stream(
 926                 const struct dc *dc,
 927                 struct dc_stream_state *stream,
 928                 struct dc_state *context)
 929 {
 930         int i;
 931
 932         for (i = 0; i < stream->num_wb_info; i++)
 933                 stream->writeback_info[i].wb_enabled = false;
 934 }
 935
 936 static void apply_ctx_interdependent_lock(struct dc *dc, struct dc_state *context,
 937                                           struct dc_stream_state *stream, bool lock)
 938 {
 939         int i;
 940
 941         /* Checks if interdependent update function pointer is NULL or not, takes care of DCE110 case */
 942         if (dc->hwss.interdependent_update_lock)
 943                 dc->hwss.interdependent_update_lock(dc, context, lock);
 944         else {
 945                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
 946                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 947                         struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 948
 949                         // Copied conditions that were previously in dce110_apply_ctx_for_surface
 950                         if (stream == pipe_ctx->stream) {
 951                                 if (!pipe_ctx->top_pipe &&
 952                                         (pipe_ctx->plane_state || old_pipe_ctx->plane_state))
 953                                         dc->hwss.pipe_control_lock(dc, pipe_ctx, lock);
 954                         }
 955                 }
 956         }
 957 }
 958
 959 static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
 960 {
 961         int i, j;
 962         struct dc_state *dangling_context = dc_create_state(dc);
 963         struct dc_state *current_ctx;
 964
 965         if (dangling_context == NULL)
 966                 return;
 967
 968         dc_resource_state_copy_construct(dc->current_state, dangling_context);
 969
 970         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 971                 struct dc_stream_state *old_stream =
 972                                 dc->current_state->res_ctx.pipe_ctx[i].stream;
 973                 bool should_disable = true;
 974
 975                 for (j = 0; j < context->stream_count; j++) {
 976                         if (old_stream == context->streams[j]) {
 977                                 should_disable = false;
 978                                 break;
 979                         }
 980                 }
 981                 if (should_disable && old_stream) {
 982                         dc_rem_all_planes_for_stream(dc, old_stream, dangling_context);
 983                         disable_all_writeback_pipes_for_stream(dc, old_stream, dangling_context);
 984
 985                         if (dc->hwss.apply_ctx_for_surface) {
 986                                 apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, true);
 987                                 dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context);
 988                                 apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, false);
 989                                 dc->hwss.post_unlock_program_front_end(dc, dangling_context);
 990                         }
 991                         if (dc->hwss.program_front_end_for_ctx) {
 992                                 dc->hwss.interdependent_update_lock(dc, dc->current_state, true);
 993                                 dc->hwss.program_front_end_for_ctx(dc, dangling_context);
 994                                 dc->hwss.interdependent_update_lock(dc, dc->current_state, false);
 995                                 dc->hwss.post_unlock_program_front_end(dc, dangling_context);
 996                         }
 997                 }
 998         }
 999
1000         current_ctx = dc->current_state;
1001         dc->current_state = dangling_context;
1002         dc_release_state(current_ctx);
1003 }
1004
1005 static void disable_vbios_mode_if_required(
1006                 struct dc *dc,
1007                 struct dc_state *context)
1008 {
1009         unsigned int i, j;
1010
1011         /* check if timing_changed, disable stream*/
1012         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1013                 struct dc_stream_state *stream = NULL;
1014                 struct dc_link *link = NULL;
1015                 struct pipe_ctx *pipe = NULL;
1016
1017                 pipe = &context->res_ctx.pipe_ctx[i];
1018                 stream = pipe->stream;
1019                 if (stream == NULL)
1020                         continue;
1021
1022                 // only looking for first odm pipe
1023                 if (pipe->prev_odm_pipe)
1024                         continue;
1025
1026                 if (stream->link->local_sink &&
1027                         stream->link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1028                         link = stream->link;
1029                 }
1030
1031                 if (link != NULL && link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
1032                         unsigned int enc_inst, tg_inst = 0;
1033                         unsigned int pix_clk_100hz;
1034
1035                         enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
1036                         if (enc_inst != ENGINE_ID_UNKNOWN) {
1037                                 for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
1038                                         if (dc->res_pool->stream_enc[j]->id == enc_inst) {
1039                                                 tg_inst = dc->res_pool->stream_enc[j]->funcs->dig_source_otg(
1040                                                         dc->res_pool->stream_enc[j]);
1041                                                 break;
1042                                         }
1043                                 }
1044
1045                                 dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
1046                                         dc->res_pool->dp_clock_source,
1047                                         tg_inst, &pix_clk_100hz);
1048
1049                                 if (link->link_status.link_active) {
1050                                         uint32_t requested_pix_clk_100hz =
1051                                                 pipe->stream_res.pix_clk_params.requested_pix_clk_100hz;
1052
1053                                         if (pix_clk_100hz != requested_pix_clk_100hz) {
1054                                                 core_link_disable_stream(pipe);
1055                                                 pipe->stream->dpms_off = false;
1056                                         }
1057                                 }
1058                         }
1059                 }
1060         }
1061 }
1062
1063 static void wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context)
1064 {
1065         int i;
1066         PERF_TRACE();
1067         for (i = 0; i < MAX_PIPES; i++) {
1068                 int count = 0;
1069                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1070
1071                 if (!pipe->plane_state)
1072                         continue;
1073
1074                 /* Timeout 100 ms */
1075                 while (count < 100000) {
1076                         /* Must set to false to start with, due to OR in update function */
1077                         pipe->plane_state->status.is_flip_pending = false;
1078                         dc->hwss.update_pending_status(pipe);
1079                         if (!pipe->plane_state->status.is_flip_pending)
1080                                 break;
1081                         udelay(1);
1082                         count++;
1083                 }
1084                 ASSERT(!pipe->plane_state->status.is_flip_pending);
1085         }
1086         PERF_TRACE();
1087 }
1088
1089 /*******************************************************************************
1090  * Public functions
1091  ******************************************************************************/
1092
1093 struct dc *dc_create(const struct dc_init_data *init_params)
1094 {
1095         struct dc *dc = kzalloc(sizeof(*dc), GFP_KERNEL);
1096         unsigned int full_pipe_count;
1097
1098         if (!dc)
1099                 return NULL;
1100
1101         if (init_params->dce_environment == DCE_ENV_VIRTUAL_HW) {
1102                 if (!dc_construct_ctx(dc, init_params))
1103                         goto destruct_dc;
1104         } else {
1105                 if (!dc_construct(dc, init_params))
1106                         goto destruct_dc;
1107
1108                 full_pipe_count = dc->res_pool->pipe_count;
1109                 if (dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
1110                         full_pipe_count--;
1111                 dc->caps.max_streams = min(
1112                                 full_pipe_count,
1113                                 dc->res_pool->stream_enc_count);
1114
1115                 dc->caps.max_links = dc->link_count;
1116                 dc->caps.max_audios = dc->res_pool->audio_count;
1117                 dc->caps.linear_pitch_alignment = 64;
1118
1119                 dc->caps.max_dp_protocol_version = DP_VERSION_1_4;
1120
1121                 if (dc->res_pool->dmcu != NULL)
1122                         dc->versions.dmcu_version = dc->res_pool->dmcu->dmcu_version;
1123         }
1124
1125         /* Populate versioning information */
1126         dc->versions.dc_ver = DC_VER;
1127
1128         dc->build_id = DC_BUILD_ID;
1129
1130         DC_LOG_DC("Display Core initialized\n");
1131
1132
1133
1134         return dc;
1135
1136 destruct_dc:
1137         dc_destruct(dc);
1138         kfree(dc);
1139         return NULL;
1140 }
1141
1142 static void detect_edp_presence(struct dc *dc)
1143 {
1144         struct dc_link *edp_links[MAX_NUM_EDP];
1145         struct dc_link *edp_link = NULL;
1146         enum dc_connection_type type;
1147         int i;
1148         int edp_num;
1149
1150         get_edp_links(dc, edp_links, &edp_num);
1151         if (!edp_num)
1152                 return;
1153
1154         for (i = 0; i < edp_num; i++) {
1155                 edp_link = edp_links[i];
1156                 if (dc->config.edp_not_connected) {
1157                         edp_link->edp_sink_present = false;
1158                 } else {
1159                         dc_link_detect_sink(edp_link, &type);
1160                         edp_link->edp_sink_present = (type != dc_connection_none);
1161                 }
1162         }
1163 }
1164
1165 void dc_hardware_init(struct dc *dc)
1166 {
1167
1168         detect_edp_presence(dc);
1169         if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW)
1170                 dc->hwss.init_hw(dc);
1171 }
1172
1173 void dc_init_callbacks(struct dc *dc,
1174                 const struct dc_callback_init *init_params)
1175 {
1176 #ifdef CONFIG_DRM_AMD_DC_HDCP
1177         dc->ctx->cp_psp = init_params->cp_psp;
1178 #endif
1179 }
1180
1181 void dc_deinit_callbacks(struct dc *dc)
1182 {
1183 #ifdef CONFIG_DRM_AMD_DC_HDCP
1184         memset(&dc->ctx->cp_psp, 0, sizeof(dc->ctx->cp_psp));
1185 #endif
1186 }
1187
1188 void dc_destroy(struct dc **dc)
1189 {
1190         dc_destruct(*dc);
1191         kfree(*dc);
1192         *dc = NULL;
1193 }
1194
1195 static void enable_timing_multisync(
1196                 struct dc *dc,
1197                 struct dc_state *ctx)
1198 {
1199         int i, multisync_count = 0;
1200         int pipe_count = dc->res_pool->pipe_count;
1201         struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL };
1202
1203         for (i = 0; i < pipe_count; i++) {
1204                 if (!ctx->res_ctx.pipe_ctx[i].stream ||
1205                                 !ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.enabled)
1206                         continue;
1207                 if (ctx->res_ctx.pipe_ctx[i].stream == ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.event_source)
1208                         continue;
1209                 multisync_pipes[multisync_count] = &ctx->res_ctx.pipe_ctx[i];
1210                 multisync_count++;
1211         }
1212
1213         if (multisync_count > 0) {
1214                 dc->hwss.enable_per_frame_crtc_position_reset(
1215                         dc, multisync_count, multisync_pipes);
1216         }
1217 }
1218
1219 static void program_timing_sync(
1220                 struct dc *dc,
1221                 struct dc_state *ctx)
1222 {
1223         int i, j, k;
1224         int group_index = 0;
1225         int num_group = 0;
1226         int pipe_count = dc->res_pool->pipe_count;
1227         struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };
1228
1229         for (i = 0; i < pipe_count; i++) {
1230                 if (!ctx->res_ctx.pipe_ctx[i].stream || ctx->res_ctx.pipe_ctx[i].top_pipe)
1231                         continue;
1232
1233                 unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i];
1234         }
1235
1236         for (i = 0; i < pipe_count; i++) {
1237                 int group_size = 1;
1238                 enum timing_synchronization_type sync_type = NOT_SYNCHRONIZABLE;
1239                 struct pipe_ctx *pipe_set[MAX_PIPES];
1240
1241                 if (!unsynced_pipes[i])
1242                         continue;
1243
1244                 pipe_set[0] = unsynced_pipes[i];
1245                 unsynced_pipes[i] = NULL;
1246
1247                 /* Add tg to the set, search rest of the tg's for ones with
1248                  * same timing, add all tgs with same timing to the group
1249                  */
1250                 for (j = i + 1; j < pipe_count; j++) {
1251                         if (!unsynced_pipes[j])
1252                                 continue;
1253                         if (sync_type != TIMING_SYNCHRONIZABLE &&
1254                                 dc->hwss.enable_vblanks_synchronization &&
1255                                 unsynced_pipes[j]->stream_res.tg->funcs->align_vblanks &&
1256                                 resource_are_vblanks_synchronizable(
1257                                         unsynced_pipes[j]->stream,
1258                                         pipe_set[0]->stream)) {
1259                                 sync_type = VBLANK_SYNCHRONIZABLE;
1260                                 pipe_set[group_size] = unsynced_pipes[j];
1261                                 unsynced_pipes[j] = NULL;
1262                                 group_size++;
1263                         } else
1264                         if (sync_type != VBLANK_SYNCHRONIZABLE &&
1265                                 resource_are_streams_timing_synchronizable(
1266                                         unsynced_pipes[j]->stream,
1267                                         pipe_set[0]->stream)) {
1268                                 sync_type = TIMING_SYNCHRONIZABLE;
1269                                 pipe_set[group_size] = unsynced_pipes[j];
1270                                 unsynced_pipes[j] = NULL;
1271                                 group_size++;
1272                         }
1273                 }
1274
1275                 /* set first unblanked pipe as master */
1276                 for (j = 0; j < group_size; j++) {
1277                         bool is_blanked;
1278
1279                         if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)
1280                                 is_blanked =
1281                                         pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);
1282                         else
1283                                 is_blanked =
1284                                         pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);
1285                         if (!is_blanked) {
1286                                 if (j == 0)
1287                                         break;
1288
1289                                 swap(pipe_set[0], pipe_set[j]);
1290                                 break;
1291                         }
1292                 }
1293
1294                 for (k = 0; k < group_size; k++) {
1295                         struct dc_stream_status *status = dc_stream_get_status_from_state(ctx, pipe_set[k]->stream);
1296
1297                         status->timing_sync_info.group_id = num_group;
1298                         status->timing_sync_info.group_size = group_size;
1299                         if (k == 0)
1300                                 status->timing_sync_info.master = true;
1301                         else
1302                                 status->timing_sync_info.master = false;
1303
1304                 }
1305                 /* remove any other unblanked pipes as they have already been synced */
1306                 for (j = j + 1; j < group_size; j++) {
1307                         bool is_blanked;
1308
1309                         if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)
1310                                 is_blanked =
1311                                         pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);
1312                         else
1313                                 is_blanked =
1314                                         pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);
1315                         if (!is_blanked) {
1316                                 group_size--;
1317                                 pipe_set[j] = pipe_set[group_size];
1318                                 j--;
1319                         }
1320                 }
1321
1322                 if (group_size > 1) {
1323                         if (sync_type == TIMING_SYNCHRONIZABLE) {
1324                                 dc->hwss.enable_timing_synchronization(
1325                                         dc, group_index, group_size, pipe_set);
1326                         } else
1327                                 if (sync_type == VBLANK_SYNCHRONIZABLE) {
1328                                 dc->hwss.enable_vblanks_synchronization(
1329                                         dc, group_index, group_size, pipe_set);
1330                                 }
1331                         group_index++;
1332                 }
1333                 num_group++;
1334         }
1335 }
1336
1337 static bool context_changed(
1338                 struct dc *dc,
1339                 struct dc_state *context)
1340 {
1341         uint8_t i;
1342
1343         if (context->stream_count != dc->current_state->stream_count)
1344                 return true;
1345
1346         for (i = 0; i < dc->current_state->stream_count; i++) {
1347                 if (dc->current_state->streams[i] != context->streams[i])
1348                         return true;
1349         }
1350
1351         return false;
1352 }
1353
1354 bool dc_validate_seamless_boot_timing(const struct dc *dc,
1355                                 const struct dc_sink *sink,
1356                                 struct dc_crtc_timing *crtc_timing)
1357 {
1358         struct timing_generator *tg;
1359         struct stream_encoder *se = NULL;
1360
1361         struct dc_crtc_timing hw_crtc_timing = {0};
1362
1363         struct dc_link *link = sink->link;
1364         unsigned int i, enc_inst, tg_inst = 0;
1365
1366         /* Support seamless boot on EDP displays only */
1367         if (sink->sink_signal != SIGNAL_TYPE_EDP) {
1368                 return false;
1369         }
1370
1371         /* Check for enabled DIG to identify enabled display */
1372         if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
1373                 return false;
1374
1375         enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
1376
1377         if (enc_inst == ENGINE_ID_UNKNOWN)
1378                 return false;
1379
1380         for (i = 0; i < dc->res_pool->stream_enc_count; i++) {
1381                 if (dc->res_pool->stream_enc[i]->id == enc_inst) {
1382
1383                         se = dc->res_pool->stream_enc[i];
1384
1385                         tg_inst = dc->res_pool->stream_enc[i]->funcs->dig_source_otg(
1386                                 dc->res_pool->stream_enc[i]);
1387                         break;
1388                 }
1389         }
1390
1391         // tg_inst not found
1392         if (i == dc->res_pool->stream_enc_count)
1393                 return false;
1394
1395         if (tg_inst >= dc->res_pool->timing_generator_count)
1396                 return false;
1397
1398         tg = dc->res_pool->timing_generators[tg_inst];
1399
1400         if (!tg->funcs->get_hw_timing)
1401                 return false;
1402
1403         if (!tg->funcs->get_hw_timing(tg, &hw_crtc_timing))
1404                 return false;
1405
1406         if (crtc_timing->h_total != hw_crtc_timing.h_total)
1407                 return false;
1408
1409         if (crtc_timing->h_border_left != hw_crtc_timing.h_border_left)
1410                 return false;
1411
1412         if (crtc_timing->h_addressable != hw_crtc_timing.h_addressable)
1413                 return false;
1414
1415         if (crtc_timing->h_border_right != hw_crtc_timing.h_border_right)
1416                 return false;
1417
1418         if (crtc_timing->h_front_porch != hw_crtc_timing.h_front_porch)
1419                 return false;
1420
1421         if (crtc_timing->h_sync_width != hw_crtc_timing.h_sync_width)
1422                 return false;
1423
1424         if (crtc_timing->v_total != hw_crtc_timing.v_total)
1425                 return false;
1426
1427         if (crtc_timing->v_border_top != hw_crtc_timing.v_border_top)
1428                 return false;
1429
1430         if (crtc_timing->v_addressable != hw_crtc_timing.v_addressable)
1431                 return false;
1432
1433         if (crtc_timing->v_border_bottom != hw_crtc_timing.v_border_bottom)
1434                 return false;
1435
1436         if (crtc_timing->v_front_porch != hw_crtc_timing.v_front_porch)
1437                 return false;
1438
1439         if (crtc_timing->v_sync_width != hw_crtc_timing.v_sync_width)
1440                 return false;
1441
1442         /* block DSC for now, as VBIOS does not currently support DSC timings */
1443         if (crtc_timing->flags.DSC)
1444                 return false;
1445
1446         if (dc_is_dp_signal(link->connector_signal)) {
1447                 unsigned int pix_clk_100hz;
1448
1449                 dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
1450                         dc->res_pool->dp_clock_source,
1451                         tg_inst, &pix_clk_100hz);
1452
1453                 if (crtc_timing->pix_clk_100hz != pix_clk_100hz)
1454                         return false;
1455
1456                 if (!se->funcs->dp_get_pixel_format)
1457                         return false;
1458
1459                 if (!se->funcs->dp_get_pixel_format(
1460                         se,
1461                         &hw_crtc_timing.pixel_encoding,
1462                         &hw_crtc_timing.display_color_depth))
1463                         return false;
1464
1465                 if (hw_crtc_timing.display_color_depth != crtc_timing->display_color_depth)
1466                         return false;
1467
1468                 if (hw_crtc_timing.pixel_encoding != crtc_timing->pixel_encoding)
1469                         return false;
1470         }
1471
1472         if (link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED) {
1473                 return false;
1474         }
1475
1476         if (is_edp_ilr_optimization_required(link, crtc_timing)) {
1477                 DC_LOG_EVENT_LINK_TRAINING("Seamless boot disabled to optimize eDP link rate\n");
1478                 return false;
1479         }
1480
1481         return true;
1482 }
1483
1484 void dc_enable_stereo(
1485         struct dc *dc,
1486         struct dc_state *context,
1487         struct dc_stream_state *streams[],
1488         uint8_t stream_count)
1489 {
1490         int i, j;
1491         struct pipe_ctx *pipe;
1492
1493         for (i = 0; i < MAX_PIPES; i++) {
1494                 if (context != NULL)
1495                         pipe = &context->res_ctx.pipe_ctx[i];
1496                 else
1497                         pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1498                 for (j = 0 ; pipe && j < stream_count; j++)  {
1499                         if (streams[j] && streams[j] == pipe->stream &&
1500                                 dc->hwss.setup_stereo)
1501                                 dc->hwss.setup_stereo(pipe, dc);
1502                 }
1503         }
1504 }
1505
1506 void dc_trigger_sync(struct dc *dc, struct dc_state *context)
1507 {
1508         if (context->stream_count > 1 && !dc->debug.disable_timing_sync) {
1509                 enable_timing_multisync(dc, context);
1510                 program_timing_sync(dc, context);
1511         }
1512 }
1513
1514 static uint8_t get_stream_mask(struct dc *dc, struct dc_state *context)
1515 {
1516         int i;
1517         unsigned int stream_mask = 0;
1518
1519         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1520                 if (context->res_ctx.pipe_ctx[i].stream)
1521                         stream_mask |= 1 << i;
1522         }
1523
1524         return stream_mask;
1525 }
1526
1527 #if defined(CONFIG_DRM_AMD_DC_DCN3_1)
1528 void dc_z10_restore(struct dc *dc)
1529 {
1530         if (dc->hwss.z10_restore)
1531                 dc->hwss.z10_restore(dc);
1532 }
1533 #endif
1534 /*
1535  * Applies given context to HW and copy it into current context.
1536  * It's up to the user to release the src context afterwards.
1537  */
1538 static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *context)
1539 {
1540         struct dc_bios *dcb = dc->ctx->dc_bios;
1541         enum dc_status result = DC_ERROR_UNEXPECTED;
1542         struct pipe_ctx *pipe;
1543         int i, k, l;
1544         struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
1545
1546 #if defined(CONFIG_DRM_AMD_DC_DCN)
1547 #if defined(CONFIG_DRM_AMD_DC_DCN3_1)
1548         dc_z10_restore(dc);
1549 #endif
1550         dc_allow_idle_optimizations(dc, false);
1551 #endif
1552
1553         for (i = 0; i < context->stream_count; i++)
1554                 dc_streams[i] =  context->streams[i];
1555
1556         if (!dcb->funcs->is_accelerated_mode(dcb)) {
1557                 disable_vbios_mode_if_required(dc, context);
1558                 dc->hwss.enable_accelerated_mode(dc, context);
1559         }
1560
1561         if (context->stream_count > get_seamless_boot_stream_count(context) ||
1562                 context->stream_count == 0)
1563                 dc->hwss.prepare_bandwidth(dc, context);
1564
1565         disable_dangling_plane(dc, context);
1566         /* re-program planes for existing stream, in case we need to
1567          * free up plane resource for later use
1568          */
1569         if (dc->hwss.apply_ctx_for_surface) {
1570                 for (i = 0; i < context->stream_count; i++) {
1571                         if (context->streams[i]->mode_changed)
1572                                 continue;
1573                         apply_ctx_interdependent_lock(dc, context, context->streams[i], true);
1574                         dc->hwss.apply_ctx_for_surface(
1575                                 dc, context->streams[i],
1576                                 context->stream_status[i].plane_count,
1577                                 context); /* use new pipe config in new context */
1578                         apply_ctx_interdependent_lock(dc, context, context->streams[i], false);
1579                         dc->hwss.post_unlock_program_front_end(dc, context);
1580                 }
1581         }
1582
1583         /* Program hardware */
1584         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1585                 pipe = &context->res_ctx.pipe_ctx[i];
1586                 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe);
1587         }
1588
1589         result = dc->hwss.apply_ctx_to_hw(dc, context);
1590
1591         if (result != DC_OK)
1592                 return result;
1593
1594         dc_trigger_sync(dc, context);
1595
1596         /* Program all planes within new context*/
1597         if (dc->hwss.program_front_end_for_ctx) {
1598                 dc->hwss.interdependent_update_lock(dc, context, true);
1599                 dc->hwss.program_front_end_for_ctx(dc, context);
1600                 dc->hwss.interdependent_update_lock(dc, context, false);
1601                 dc->hwss.post_unlock_program_front_end(dc, context);
1602         }
1603         for (i = 0; i < context->stream_count; i++) {
1604                 const struct dc_link *link = context->streams[i]->link;
1605
1606                 if (!context->streams[i]->mode_changed)
1607                         continue;
1608
1609                 if (dc->hwss.apply_ctx_for_surface) {
1610                         apply_ctx_interdependent_lock(dc, context, context->streams[i], true);
1611                         dc->hwss.apply_ctx_for_surface(
1612                                         dc, context->streams[i],
1613                                         context->stream_status[i].plane_count,
1614                                         context);
1615                         apply_ctx_interdependent_lock(dc, context, context->streams[i], false);
1616                         dc->hwss.post_unlock_program_front_end(dc, context);
1617                 }
1618
1619                 /*
1620                  * enable stereo
1621                  * TODO rework dc_enable_stereo call to work with validation sets?
1622                  */
1623                 for (k = 0; k < MAX_PIPES; k++) {
1624                         pipe = &context->res_ctx.pipe_ctx[k];
1625
1626                         for (l = 0 ; pipe && l < context->stream_count; l++)  {
1627                                 if (context->streams[l] &&
1628                                         context->streams[l] == pipe->stream &&
1629                                         dc->hwss.setup_stereo)
1630                                         dc->hwss.setup_stereo(pipe, dc);
1631                         }
1632                 }
1633
1634                 CONN_MSG_MODE(link, "{%dx%d, %dx%d@%dKhz}",
1635                                 context->streams[i]->timing.h_addressable,
1636                                 context->streams[i]->timing.v_addressable,
1637                                 context->streams[i]->timing.h_total,
1638                                 context->streams[i]->timing.v_total,
1639                                 context->streams[i]->timing.pix_clk_100hz / 10);
1640         }
1641
1642         dc_enable_stereo(dc, context, dc_streams, context->stream_count);
1643
1644         if (context->stream_count > get_seamless_boot_stream_count(context) ||
1645                 context->stream_count == 0) {
1646                 /* Must wait for no flips to be pending before doing optimize bw */
1647                 wait_for_no_pipes_pending(dc, context);
1648                 /* pplib is notified if disp_num changed */
1649                 dc->hwss.optimize_bandwidth(dc, context);
1650         }
1651
1652         if (dc->ctx->dce_version >= DCE_VERSION_MAX)
1653                 TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk);
1654         else
1655                 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);
1656
1657         context->stream_mask = get_stream_mask(dc, context);
1658
1659         if (context->stream_mask != dc->current_state->stream_mask)
1660                 dc_dmub_srv_notify_stream_mask(dc->ctx->dmub_srv, context->stream_mask);
1661
1662         for (i = 0; i < context->stream_count; i++)
1663                 context->streams[i]->mode_changed = false;
1664
1665         dc_release_state(dc->current_state);
1666
1667         dc->current_state = context;
1668
1669         dc_retain_state(dc->current_state);
1670
1671         return result;
1672 }
1673
1674 bool dc_commit_state(struct dc *dc, struct dc_state *context)
1675 {
1676         enum dc_status result = DC_ERROR_UNEXPECTED;
1677         int i;
1678
1679         if (!context_changed(dc, context))
1680                 return DC_OK;
1681
1682         DC_LOG_DC("%s: %d streams\n",
1683                                 __func__, context->stream_count);
1684
1685         for (i = 0; i < context->stream_count; i++) {
1686                 struct dc_stream_state *stream = context->streams[i];
1687
1688                 dc_stream_log(dc, stream);
1689         }
1690
1691         result = dc_commit_state_no_check(dc, context);
1692
1693         return (result == DC_OK);
1694 }
1695
1696 #if defined(CONFIG_DRM_AMD_DC_DCN)
1697 bool dc_acquire_release_mpc_3dlut(
1698                 struct dc *dc, bool acquire,
1699                 struct dc_stream_state *stream,
1700                 struct dc_3dlut **lut,
1701                 struct dc_transfer_func **shaper)
1702 {
1703         int pipe_idx;
1704         bool ret = false;
1705         bool found_pipe_idx = false;
1706         const struct resource_pool *pool = dc->res_pool;
1707         struct resource_context *res_ctx = &dc->current_state->res_ctx;
1708         int mpcc_id = 0;
1709
1710         if (pool && res_ctx) {
1711                 if (acquire) {
1712                         /*find pipe idx for the given stream*/
1713                         for (pipe_idx = 0; pipe_idx < pool->pipe_count; pipe_idx++) {
1714                                 if (res_ctx->pipe_ctx[pipe_idx].stream == stream) {
1715                                         found_pipe_idx = true;
1716                                         mpcc_id = res_ctx->pipe_ctx[pipe_idx].plane_res.hubp->inst;
1717                                         break;
1718                                 }
1719                         }
1720                 } else
1721                         found_pipe_idx = true;/*for release pipe_idx is not required*/
1722
1723                 if (found_pipe_idx) {
1724                         if (acquire && pool->funcs->acquire_post_bldn_3dlut)
1725                                 ret = pool->funcs->acquire_post_bldn_3dlut(res_ctx, pool, mpcc_id, lut, shaper);
1726                         else if (!acquire && pool->funcs->release_post_bldn_3dlut)
1727                                 ret = pool->funcs->release_post_bldn_3dlut(res_ctx, pool, lut, shaper);
1728                 }
1729         }
1730         return ret;
1731 }
1732 #endif
1733 static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)
1734 {
1735         int i;
1736         struct pipe_ctx *pipe;
1737
1738         for (i = 0; i < MAX_PIPES; i++) {
1739                 pipe = &context->res_ctx.pipe_ctx[i];
1740
1741                 if (!pipe->plane_state)
1742                         continue;
1743
1744                 /* Must set to false to start with, due to OR in update function */
1745                 pipe->plane_state->status.is_flip_pending = false;
1746                 dc->hwss.update_pending_status(pipe);
1747                 if (pipe->plane_state->status.is_flip_pending)
1748                         return true;
1749         }
1750         return false;
1751 }
1752
1753 void dc_post_update_surfaces_to_stream(struct dc *dc)
1754 {
1755         int i;
1756         struct dc_state *context = dc->current_state;
1757
1758         if ((!dc->optimized_required) || get_seamless_boot_stream_count(context) > 0)
1759                 return;
1760
1761         post_surface_trace(dc);
1762
1763         if (is_flip_pending_in_pipes(dc, context))
1764                 return;
1765
1766         for (i = 0; i < dc->res_pool->pipe_count; i++)
1767                 if (context->res_ctx.pipe_ctx[i].stream == NULL ||
1768                     context->res_ctx.pipe_ctx[i].plane_state == NULL) {
1769                         context->res_ctx.pipe_ctx[i].pipe_idx = i;
1770                         dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]);
1771                 }
1772
1773         dc->hwss.optimize_bandwidth(dc, context);
1774
1775         dc->optimized_required = false;
1776         dc->wm_optimized_required = false;
1777 }
1778
1779 static void init_state(struct dc *dc, struct dc_state *context)
1780 {
1781         /* Each context must have their own instance of VBA and in order to
1782          * initialize and obtain IP and SOC the base DML instance from DC is
1783          * initially copied into every context
1784          */
1785 #ifdef CONFIG_DRM_AMD_DC_DCN
1786         memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib));
1787 #endif
1788 }
1789
1790 struct dc_state *dc_create_state(struct dc *dc)
1791 {
1792         struct dc_state *context = kvzalloc(sizeof(struct dc_state),
1793                                             GFP_KERNEL);
1794
1795         if (!context)
1796                 return NULL;
1797
1798         init_state(dc, context);
1799
1800         kref_init(&context->refcount);
1801
1802         return context;
1803 }
1804
1805 struct dc_state *dc_copy_state(struct dc_state *src_ctx)
1806 {
1807         int i, j;
1808         struct dc_state *new_ctx = kvmalloc(sizeof(struct dc_state), GFP_KERNEL);
1809
1810         if (!new_ctx)
1811                 return NULL;
1812         memcpy(new_ctx, src_ctx, sizeof(struct dc_state));
1813
1814         for (i = 0; i < MAX_PIPES; i++) {
1815                         struct pipe_ctx *cur_pipe = &new_ctx->res_ctx.pipe_ctx[i];
1816
1817                         if (cur_pipe->top_pipe)
1818                                 cur_pipe->top_pipe =  &new_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
1819
1820                         if (cur_pipe->bottom_pipe)
1821                                 cur_pipe->bottom_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
1822
1823                         if (cur_pipe->prev_odm_pipe)
1824                                 cur_pipe->prev_odm_pipe =  &new_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];
1825
1826                         if (cur_pipe->next_odm_pipe)
1827                                 cur_pipe->next_odm_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];
1828
1829         }
1830
1831         for (i = 0; i < new_ctx->stream_count; i++) {
1832                         dc_stream_retain(new_ctx->streams[i]);
1833                         for (j = 0; j < new_ctx->stream_status[i].plane_count; j++)
1834                                 dc_plane_state_retain(
1835                                         new_ctx->stream_status[i].plane_states[j]);
1836         }
1837
1838         kref_init(&new_ctx->refcount);
1839
1840         return new_ctx;
1841 }
1842
1843 void dc_retain_state(struct dc_state *context)
1844 {
1845         kref_get(&context->refcount);
1846 }
1847
1848 static void dc_state_free(struct kref *kref)
1849 {
1850         struct dc_state *context = container_of(kref, struct dc_state, refcount);
1851         dc_resource_state_destruct(context);
1852         kvfree(context);
1853 }
1854
1855 void dc_release_state(struct dc_state *context)
1856 {
1857         kref_put(&context->refcount, dc_state_free);
1858 }
1859
1860 bool dc_set_generic_gpio_for_stereo(bool enable,
1861                 struct gpio_service *gpio_service)
1862 {
1863         enum gpio_result gpio_result = GPIO_RESULT_NON_SPECIFIC_ERROR;
1864         struct gpio_pin_info pin_info;
1865         struct gpio *generic;
1866         struct gpio_generic_mux_config *config = kzalloc(sizeof(struct gpio_generic_mux_config),
1867                            GFP_KERNEL);
1868
1869         if (!config)
1870                 return false;
1871         pin_info = dal_gpio_get_generic_pin_info(gpio_service, GPIO_ID_GENERIC, 0);
1872
1873         if (pin_info.mask == 0xFFFFFFFF || pin_info.offset == 0xFFFFFFFF) {
1874                 kfree(config);
1875                 return false;
1876         } else {
1877                 generic = dal_gpio_service_create_generic_mux(
1878                         gpio_service,
1879                         pin_info.offset,
1880                         pin_info.mask);
1881         }
1882
1883         if (!generic) {
1884                 kfree(config);
1885                 return false;
1886         }
1887
1888         gpio_result = dal_gpio_open(generic, GPIO_MODE_OUTPUT);
1889
1890         config->enable_output_from_mux = enable;
1891         config->mux_select = GPIO_SIGNAL_SOURCE_PASS_THROUGH_STEREO_SYNC;
1892
1893         if (gpio_result == GPIO_RESULT_OK)
1894                 gpio_result = dal_mux_setup_config(generic, config);
1895
1896         if (gpio_result == GPIO_RESULT_OK) {
1897                 dal_gpio_close(generic);
1898                 dal_gpio_destroy_generic_mux(&generic);
1899                 kfree(config);
1900                 return true;
1901         } else {
1902                 dal_gpio_close(generic);
1903                 dal_gpio_destroy_generic_mux(&generic);
1904                 kfree(config);
1905                 return false;
1906         }
1907 }
1908
1909 static bool is_surface_in_context(
1910                 const struct dc_state *context,
1911                 const struct dc_plane_state *plane_state)
1912 {
1913         int j;
1914
1915         for (j = 0; j < MAX_PIPES; j++) {
1916                 const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1917
1918                 if (plane_state == pipe_ctx->plane_state) {
1919                         return true;
1920                 }
1921         }
1922
1923         return false;
1924 }
1925
1926 static enum surface_update_type get_plane_info_update_type(const struct dc_surface_update *u)
1927 {
1928         union surface_update_flags *update_flags = &u->surface->update_flags;
1929         enum surface_update_type update_type = UPDATE_TYPE_FAST;
1930
1931         if (!u->plane_info)
1932                 return UPDATE_TYPE_FAST;
1933
1934         if (u->plane_info->color_space != u->surface->color_space) {
1935                 update_flags->bits.color_space_change = 1;
1936                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1937         }
1938
1939         if (u->plane_info->horizontal_mirror != u->surface->horizontal_mirror) {
1940                 update_flags->bits.horizontal_mirror_change = 1;
1941                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1942         }
1943
1944         if (u->plane_info->rotation != u->surface->rotation) {
1945                 update_flags->bits.rotation_change = 1;
1946                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1947         }
1948
1949         if (u->plane_info->format != u->surface->format) {
1950                 update_flags->bits.pixel_format_change = 1;
1951                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1952         }
1953
1954         if (u->plane_info->stereo_format != u->surface->stereo_format) {
1955                 update_flags->bits.stereo_format_change = 1;
1956                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1957         }
1958
1959         if (u->plane_info->per_pixel_alpha != u->surface->per_pixel_alpha) {
1960                 update_flags->bits.per_pixel_alpha_change = 1;
1961                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1962         }
1963
1964         if (u->plane_info->global_alpha_value != u->surface->global_alpha_value) {
1965                 update_flags->bits.global_alpha_change = 1;
1966                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1967         }
1968
1969         if (u->plane_info->dcc.enable != u->surface->dcc.enable
1970                         || u->plane_info->dcc.independent_64b_blks != u->surface->dcc.independent_64b_blks
1971                         || u->plane_info->dcc.meta_pitch != u->surface->dcc.meta_pitch) {
1972                 /* During DCC on/off, stutter period is calculated before
1973                  * DCC has fully transitioned. This results in incorrect
1974                  * stutter period calculation. Triggering a full update will
1975                  * recalculate stutter period.
1976                  */
1977                 update_flags->bits.dcc_change = 1;
1978                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1979         }
1980
1981         if (resource_pixel_format_to_bpp(u->plane_info->format) !=
1982                         resource_pixel_format_to_bpp(u->surface->format)) {
1983                 /* different bytes per element will require full bandwidth
1984                  * and DML calculation
1985                  */
1986                 update_flags->bits.bpp_change = 1;
1987                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1988         }
1989
1990         if (u->plane_info->plane_size.surface_pitch != u->surface->plane_size.surface_pitch
1991                         || u->plane_info->plane_size.chroma_pitch != u->surface->plane_size.chroma_pitch) {
1992                 update_flags->bits.plane_size_change = 1;
1993                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1994         }
1995
1996
1997         if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info,
1998                         sizeof(union dc_tiling_info)) != 0) {
1999                 update_flags->bits.swizzle_change = 1;
2000                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
2001
2002                 /* todo: below are HW dependent, we should add a hook to
2003                  * DCE/N resource and validated there.
2004                  */
2005                 if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR) {
2006                         /* swizzled mode requires RQ to be setup properly,
2007                          * thus need to run DML to calculate RQ settings
2008                          */
2009                         update_flags->bits.bandwidth_change = 1;
2010                         elevate_update_type(&update_type, UPDATE_TYPE_FULL);
2011                 }
2012         }
2013
2014         /* This should be UPDATE_TYPE_FAST if nothing has changed. */
2015         return update_type;
2016 }
2017
2018 static enum surface_update_type get_scaling_info_update_type(
2019                 const struct dc_surface_update *u)
2020 {
2021         union surface_update_flags *update_flags = &u->surface->update_flags;
2022
2023         if (!u->scaling_info)
2024                 return UPDATE_TYPE_FAST;
2025
2026         if (u->scaling_info->clip_rect.width != u->surface->clip_rect.width
2027                         || u->scaling_info->clip_rect.height != u->surface->clip_rect.height
2028                         || u->scaling_info->dst_rect.width != u->surface->dst_rect.width
2029                         || u->scaling_info->dst_rect.height != u->surface->dst_rect.height
2030                         || u->scaling_info->scaling_quality.integer_scaling !=
2031                                 u->surface->scaling_quality.integer_scaling
2032                         ) {
2033                 update_flags->bits.scaling_change = 1;
2034
2035                 if ((u->scaling_info->dst_rect.width < u->surface->dst_rect.width
2036                         || u->scaling_info->dst_rect.height < u->surface->dst_rect.height)
2037                                 && (u->scaling_info->dst_rect.width < u->surface->src_rect.width
2038                                         || u->scaling_info->dst_rect.height < u->surface->src_rect.height))
2039                         /* Making dst rect smaller requires a bandwidth change */
2040                         update_flags->bits.bandwidth_change = 1;
2041         }
2042
2043         if (u->scaling_info->src_rect.width != u->surface->src_rect.width
2044                 || u->scaling_info->src_rect.height != u->surface->src_rect.height) {
2045
2046                 update_flags->bits.scaling_change = 1;
2047                 if (u->scaling_info->src_rect.width > u->surface->src_rect.width
2048                                 || u->scaling_info->src_rect.height > u->surface->src_rect.height)
2049                         /* Making src rect bigger requires a bandwidth change */
2050                         update_flags->bits.clock_change = 1;
2051         }
2052
2053         if (u->scaling_info->src_rect.x != u->surface->src_rect.x
2054                         || u->scaling_info->src_rect.y != u->surface->src_rect.y
2055                         || u->scaling_info->clip_rect.x != u->surface->clip_rect.x
2056                         || u->scaling_info->clip_rect.y != u->surface->clip_rect.y
2057                         || u->scaling_info->dst_rect.x != u->surface->dst_rect.x
2058                         || u->scaling_info->dst_rect.y != u->surface->dst_rect.y)
2059                 update_flags->bits.position_change = 1;
2060
2061         if (update_flags->bits.clock_change
2062                         || update_flags->bits.bandwidth_change
2063                         || update_flags->bits.scaling_change)
2064                 return UPDATE_TYPE_FULL;
2065
2066         if (update_flags->bits.position_change)
2067                 return UPDATE_TYPE_MED;
2068
2069         return UPDATE_TYPE_FAST;
2070 }
2071
2072 static enum surface_update_type det_surface_update(const struct dc *dc,
2073                 const struct dc_surface_update *u)
2074 {
2075         const struct dc_state *context = dc->current_state;
2076         enum surface_update_type type;
2077         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
2078         union surface_update_flags *update_flags = &u->surface->update_flags;
2079
2080         if (u->flip_addr)
2081                 update_flags->bits.addr_update = 1;
2082
2083         if (!is_surface_in_context(context, u->surface) || u->surface->force_full_update) {
2084                 update_flags->raw = 0xFFFFFFFF;
2085                 return UPDATE_TYPE_FULL;
2086         }
2087
2088         update_flags->raw = 0; // Reset all flags
2089
2090         type = get_plane_info_update_type(u);
2091         elevate_update_type(&overall_type, type);
2092
2093         type = get_scaling_info_update_type(u);
2094         elevate_update_type(&overall_type, type);
2095
2096         if (u->flip_addr)
2097                 update_flags->bits.addr_update = 1;
2098
2099         if (u->in_transfer_func)
2100                 update_flags->bits.in_transfer_func_change = 1;
2101
2102         if (u->input_csc_color_matrix)
2103                 update_flags->bits.input_csc_change = 1;
2104
2105         if (u->coeff_reduction_factor)
2106                 update_flags->bits.coeff_reduction_change = 1;
2107
2108         if (u->gamut_remap_matrix)
2109                 update_flags->bits.gamut_remap_change = 1;
2110
2111         if (u->gamma) {
2112                 enum surface_pixel_format format = SURFACE_PIXEL_FORMAT_GRPH_BEGIN;
2113
2114                 if (u->plane_info)
2115                         format = u->plane_info->format;
2116                 else if (u->surface)
2117                         format = u->surface->format;
2118
2119                 if (dce_use_lut(format))
2120                         update_flags->bits.gamma_change = 1;
2121         }
2122
2123         if (u->hdr_mult.value)
2124                 if (u->hdr_mult.value != u->surface->hdr_mult.value) {
2125                         update_flags->bits.hdr_mult = 1;
2126                         elevate_update_type(&overall_type, UPDATE_TYPE_MED);
2127                 }
2128
2129         if (update_flags->bits.in_transfer_func_change) {
2130                 type = UPDATE_TYPE_MED;
2131                 elevate_update_type(&overall_type, type);
2132         }
2133
2134         if (update_flags->bits.input_csc_change
2135                         || update_flags->bits.coeff_reduction_change
2136                         || update_flags->bits.gamma_change
2137                         || update_flags->bits.gamut_remap_change) {
2138                 type = UPDATE_TYPE_FULL;
2139                 elevate_update_type(&overall_type, type);
2140         }
2141
2142         return overall_type;
2143 }
2144
2145 static enum surface_update_type check_update_surfaces_for_stream(
2146                 struct dc *dc,
2147                 struct dc_surface_update *updates,
2148                 int surface_count,
2149                 struct dc_stream_update *stream_update,
2150                 const struct dc_stream_status *stream_status)
2151 {
2152         int i;
2153         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
2154
2155 #if defined(CONFIG_DRM_AMD_DC_DCN)
2156         if (dc->idle_optimizations_allowed)
2157                 overall_type = UPDATE_TYPE_FULL;
2158
2159 #endif
2160         if (stream_status == NULL || stream_status->plane_count != surface_count)
2161                 overall_type = UPDATE_TYPE_FULL;
2162
2163         if (stream_update && stream_update->pending_test_pattern) {
2164                 overall_type = UPDATE_TYPE_FULL;
2165         }
2166
2167         /* some stream updates require passive update */
2168         if (stream_update) {
2169                 union stream_update_flags *su_flags = &stream_update->stream->update_flags;
2170
2171                 if ((stream_update->src.height != 0 && stream_update->src.width != 0) ||
2172                         (stream_update->dst.height != 0 && stream_update->dst.width != 0) ||
2173                         stream_update->integer_scaling_update)
2174                         su_flags->bits.scaling = 1;
2175
2176                 if (stream_update->out_transfer_func)
2177                         su_flags->bits.out_tf = 1;
2178
2179                 if (stream_update->abm_level)
2180                         su_flags->bits.abm_level = 1;
2181
2182                 if (stream_update->dpms_off)
2183                         su_flags->bits.dpms_off = 1;
2184
2185                 if (stream_update->gamut_remap)
2186                         su_flags->bits.gamut_remap = 1;
2187
2188                 if (stream_update->wb_update)
2189                         su_flags->bits.wb_update = 1;
2190
2191                 if (stream_update->dsc_config)
2192                         su_flags->bits.dsc_changed = 1;
2193
2194                 if (su_flags->raw != 0)
2195                         overall_type = UPDATE_TYPE_FULL;
2196
2197                 if (stream_update->output_csc_transform || stream_update->output_color_space)
2198                         su_flags->bits.out_csc = 1;
2199         }
2200
2201         for (i = 0 ; i < surface_count; i++) {
2202                 enum surface_update_type type =
2203                                 det_surface_update(dc, &updates[i]);
2204
2205                 elevate_update_type(&overall_type, type);
2206         }
2207
2208         return overall_type;
2209 }
2210
2211 /*
2212  * dc_check_update_surfaces_for_stream() - Determine update type (fast, med, or full)
2213  *
2214  * See :c:type:`enum surface_update_type <surface_update_type>` for explanation of update types
2215  */
2216 enum surface_update_type dc_check_update_surfaces_for_stream(
2217                 struct dc *dc,
2218                 struct dc_surface_update *updates,
2219                 int surface_count,
2220                 struct dc_stream_update *stream_update,
2221                 const struct dc_stream_status *stream_status)
2222 {
2223         int i;
2224         enum surface_update_type type;
2225
2226         if (stream_update)
2227                 stream_update->stream->update_flags.raw = 0;
2228         for (i = 0; i < surface_count; i++)
2229                 updates[i].surface->update_flags.raw = 0;
2230
2231         type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status);
2232         if (type == UPDATE_TYPE_FULL) {
2233                 if (stream_update) {
2234                         uint32_t dsc_changed = stream_update->stream->update_flags.bits.dsc_changed;
2235                         stream_update->stream->update_flags.raw = 0xFFFFFFFF;
2236                         stream_update->stream->update_flags.bits.dsc_changed = dsc_changed;
2237                 }
2238                 for (i = 0; i < surface_count; i++)
2239                         updates[i].surface->update_flags.raw = 0xFFFFFFFF;
2240         }
2241
2242         if (type == UPDATE_TYPE_FAST) {
2243                 // If there's an available clock comparator, we use that.
2244                 if (dc->clk_mgr->funcs->are_clock_states_equal) {
2245                         if (!dc->clk_mgr->funcs->are_clock_states_equal(&dc->clk_mgr->clks, &dc->current_state->bw_ctx.bw.dcn.clk))
2246                                 dc->optimized_required = true;
2247                 // Else we fallback to mem compare.
2248                 } else if (memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_clocks, prev_p_state_change_support)) != 0) {
2249                         dc->optimized_required = true;
2250                 }
2251
2252                 dc->optimized_required |= dc->wm_optimized_required;
2253         }
2254
2255         return type;
2256 }
2257
2258 static struct dc_stream_status *stream_get_status(
2259         struct dc_state *ctx,
2260         struct dc_stream_state *stream)
2261 {
2262         uint8_t i;
2263
2264         for (i = 0; i < ctx->stream_count; i++) {
2265                 if (stream == ctx->streams[i]) {
2266                         return &ctx->stream_status[i];
2267                 }
2268         }
2269
2270         return NULL;
2271 }
2272
2273 static const enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL;
2274
2275 static void copy_surface_update_to_plane(
2276                 struct dc_plane_state *surface,
2277                 struct dc_surface_update *srf_update)
2278 {
2279         if (srf_update->flip_addr) {
2280                 surface->address = srf_update->flip_addr->address;
2281                 surface->flip_immediate =
2282                         srf_update->flip_addr->flip_immediate;
2283                 surface->time.time_elapsed_in_us[surface->time.index] =
2284                         srf_update->flip_addr->flip_timestamp_in_us -
2285                                 surface->time.prev_update_time_in_us;
2286                 surface->time.prev_update_time_in_us =
2287                         srf_update->flip_addr->flip_timestamp_in_us;
2288                 surface->time.index++;
2289                 if (surface->time.index >= DC_PLANE_UPDATE_TIMES_MAX)
2290                         surface->time.index = 0;
2291
2292                 surface->triplebuffer_flips = srf_update->flip_addr->triplebuffer_flips;
2293         }
2294
2295         if (srf_update->scaling_info) {
2296                 surface->scaling_quality =
2297                                 srf_update->scaling_info->scaling_quality;
2298                 surface->dst_rect =
2299                                 srf_update->scaling_info->dst_rect;
2300                 surface->src_rect =
2301                                 srf_update->scaling_info->src_rect;
2302                 surface->clip_rect =
2303                                 srf_update->scaling_info->clip_rect;
2304         }
2305
2306         if (srf_update->plane_info) {
2307                 surface->color_space =
2308                                 srf_update->plane_info->color_space;
2309                 surface->format =
2310                                 srf_update->plane_info->format;
2311                 surface->plane_size =
2312                                 srf_update->plane_info->plane_size;
2313                 surface->rotation =
2314                                 srf_update->plane_info->rotation;
2315                 surface->horizontal_mirror =
2316                                 srf_update->plane_info->horizontal_mirror;
2317                 surface->stereo_format =
2318                                 srf_update->plane_info->stereo_format;
2319                 surface->tiling_info =
2320                                 srf_update->plane_info->tiling_info;
2321                 surface->visible =
2322                                 srf_update->plane_info->visible;
2323                 surface->per_pixel_alpha =
2324                                 srf_update->plane_info->per_pixel_alpha;
2325                 surface->global_alpha =
2326                                 srf_update->plane_info->global_alpha;
2327                 surface->global_alpha_value =
2328                                 srf_update->plane_info->global_alpha_value;
2329                 surface->dcc =
2330                                 srf_update->plane_info->dcc;
2331                 surface->layer_index =
2332                                 srf_update->plane_info->layer_index;
2333         }
2334
2335         if (srf_update->gamma &&
2336                         (surface->gamma_correction !=
2337                                         srf_update->gamma)) {
2338                 memcpy(&surface->gamma_correction->entries,
2339                         &srf_update->gamma->entries,
2340                         sizeof(struct dc_gamma_entries));
2341                 surface->gamma_correction->is_identity =
2342                         srf_update->gamma->is_identity;
2343                 surface->gamma_correction->num_entries =
2344                         srf_update->gamma->num_entries;
2345                 surface->gamma_correction->type =
2346                         srf_update->gamma->type;
2347         }
2348
2349         if (srf_update->in_transfer_func &&
2350                         (surface->in_transfer_func !=
2351                                 srf_update->in_transfer_func)) {
2352                 surface->in_transfer_func->sdr_ref_white_level =
2353                         srf_update->in_transfer_func->sdr_ref_white_level;
2354                 surface->in_transfer_func->tf =
2355                         srf_update->in_transfer_func->tf;
2356                 surface->in_transfer_func->type =
2357                         srf_update->in_transfer_func->type;
2358                 memcpy(&surface->in_transfer_func->tf_pts,
2359                         &srf_update->in_transfer_func->tf_pts,
2360                         sizeof(struct dc_transfer_func_distributed_points));
2361         }
2362
2363         if (srf_update->func_shaper &&
2364                         (surface->in_shaper_func !=
2365                         srf_update->func_shaper))
2366                 memcpy(surface->in_shaper_func, srf_update->func_shaper,
2367                 sizeof(*surface->in_shaper_func));
2368
2369         if (srf_update->lut3d_func &&
2370                         (surface->lut3d_func !=
2371                         srf_update->lut3d_func))
2372                 memcpy(surface->lut3d_func, srf_update->lut3d_func,
2373                 sizeof(*surface->lut3d_func));
2374
2375         if (srf_update->hdr_mult.value)
2376                 surface->hdr_mult =
2377                                 srf_update->hdr_mult;
2378
2379         if (srf_update->blend_tf &&
2380                         (surface->blend_tf !=
2381                         srf_update->blend_tf))
2382                 memcpy(surface->blend_tf, srf_update->blend_tf,
2383                 sizeof(*surface->blend_tf));
2384
2385         if (srf_update->input_csc_color_matrix)
2386                 surface->input_csc_color_matrix =
2387                         *srf_update->input_csc_color_matrix;
2388
2389         if (srf_update->coeff_reduction_factor)
2390                 surface->coeff_reduction_factor =
2391                         *srf_update->coeff_reduction_factor;
2392
2393         if (srf_update->gamut_remap_matrix)
2394                 surface->gamut_remap_matrix =
2395                         *srf_update->gamut_remap_matrix;
2396 }
2397
2398 static void copy_stream_update_to_stream(struct dc *dc,
2399                                          struct dc_state *context,
2400                                          struct dc_stream_state *stream,
2401                                          struct dc_stream_update *update)
2402 {
2403         struct dc_context *dc_ctx = dc->ctx;
2404
2405         if (update == NULL || stream == NULL)
2406                 return;
2407
2408         if (update->src.height && update->src.width)
2409                 stream->src = update->src;
2410
2411         if (update->dst.height && update->dst.width)
2412                 stream->dst = update->dst;
2413
2414         if (update->out_transfer_func &&
2415             stream->out_transfer_func != update->out_transfer_func) {
2416                 stream->out_transfer_func->sdr_ref_white_level =
2417                         update->out_transfer_func->sdr_ref_white_level;
2418                 stream->out_transfer_func->tf = update->out_transfer_func->tf;
2419                 stream->out_transfer_func->type =
2420                         update->out_transfer_func->type;
2421                 memcpy(&stream->out_transfer_func->tf_pts,
2422                        &update->out_transfer_func->tf_pts,
2423                        sizeof(struct dc_transfer_func_distributed_points));
2424         }
2425
2426         if (update->hdr_static_metadata)
2427                 stream->hdr_static_metadata = *update->hdr_static_metadata;
2428
2429         if (update->abm_level)
2430                 stream->abm_level = *update->abm_level;
2431
2432         if (update->periodic_interrupt0)
2433                 stream->periodic_interrupt0 = *update->periodic_interrupt0;
2434
2435         if (update->periodic_interrupt1)
2436                 stream->periodic_interrupt1 = *update->periodic_interrupt1;
2437
2438         if (update->gamut_remap)
2439                 stream->gamut_remap_matrix = *update->gamut_remap;
2440
2441         /* Note: this being updated after mode set is currently not a use case
2442          * however if it arises OCSC would need to be reprogrammed at the
2443          * minimum
2444          */
2445         if (update->output_color_space)
2446                 stream->output_color_space = *update->output_color_space;
2447
2448         if (update->output_csc_transform)
2449                 stream->csc_color_matrix = *update->output_csc_transform;
2450
2451         if (update->vrr_infopacket)
2452                 stream->vrr_infopacket = *update->vrr_infopacket;
2453
2454         if (update->dpms_off)
2455                 stream->dpms_off = *update->dpms_off;
2456
2457         if (update->vsc_infopacket)
2458                 stream->vsc_infopacket = *update->vsc_infopacket;
2459
2460         if (update->vsp_infopacket)
2461                 stream->vsp_infopacket = *update->vsp_infopacket;
2462
2463         if (update->dither_option)
2464                 stream->dither_option = *update->dither_option;
2465
2466         if (update->pending_test_pattern)
2467                 stream->test_pattern = *update->pending_test_pattern;
2468         /* update current stream with writeback info */
2469         if (update->wb_update) {
2470                 int i;
2471
2472                 stream->num_wb_info = update->wb_update->num_wb_info;
2473                 ASSERT(stream->num_wb_info <= MAX_DWB_PIPES);
2474                 for (i = 0; i < stream->num_wb_info; i++)
2475                         stream->writeback_info[i] =
2476                                 update->wb_update->writeback_info[i];
2477         }
2478         if (update->dsc_config) {
2479                 struct dc_dsc_config old_dsc_cfg = stream->timing.dsc_cfg;
2480                 uint32_t old_dsc_enabled = stream->timing.flags.DSC;
2481                 uint32_t enable_dsc = (update->dsc_config->num_slices_h != 0 &&
2482                                        update->dsc_config->num_slices_v != 0);
2483
2484                 /* Use temporarry context for validating new DSC config */
2485                 struct dc_state *dsc_validate_context = dc_create_state(dc);
2486
2487                 if (dsc_validate_context) {
2488                         dc_resource_state_copy_construct(dc->current_state, dsc_validate_context);
2489
2490                         stream->timing.dsc_cfg = *update->dsc_config;
2491                         stream->timing.flags.DSC = enable_dsc;
2492                         if (!dc->res_pool->funcs->validate_bandwidth(dc, dsc_validate_context, true)) {
2493                                 stream->timing.dsc_cfg = old_dsc_cfg;
2494                                 stream->timing.flags.DSC = old_dsc_enabled;
2495                                 update->dsc_config = NULL;
2496                         }
2497
2498                         dc_release_state(dsc_validate_context);
2499                 } else {
2500                         DC_ERROR("Failed to allocate new validate context for DSC change\n");
2501                         update->dsc_config = NULL;
2502                 }
2503         }
2504 }
2505
2506 static void commit_planes_do_stream_update(struct dc *dc,
2507                 struct dc_stream_state *stream,
2508                 struct dc_stream_update *stream_update,
2509                 enum surface_update_type update_type,
2510                 struct dc_state *context)
2511 {
2512         int j;
2513
2514         // Stream updates
2515         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2516                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2517
2518                 if (!pipe_ctx->top_pipe &&  !pipe_ctx->prev_odm_pipe && pipe_ctx->stream == stream) {
2519
2520                         if (stream_update->periodic_interrupt0 &&
2521                                         dc->hwss.setup_periodic_interrupt)
2522                                 dc->hwss.setup_periodic_interrupt(dc, pipe_ctx, VLINE0);
2523
2524                         if (stream_update->periodic_interrupt1 &&
2525                                         dc->hwss.setup_periodic_interrupt)
2526                                 dc->hwss.setup_periodic_interrupt(dc, pipe_ctx, VLINE1);
2527
2528                         if ((stream_update->hdr_static_metadata && !stream->use_dynamic_meta) ||
2529                                         stream_update->vrr_infopacket ||
2530                                         stream_update->vsc_infopacket ||
2531                                         stream_update->vsp_infopacket) {
2532                                 resource_build_info_frame(pipe_ctx);
2533                                 dc->hwss.update_info_frame(pipe_ctx);
2534                         }
2535
2536                         if (stream_update->hdr_static_metadata &&
2537                                         stream->use_dynamic_meta &&
2538                                         dc->hwss.set_dmdata_attributes &&
2539                                         pipe_ctx->stream->dmdata_address.quad_part != 0)
2540                                 dc->hwss.set_dmdata_attributes(pipe_ctx);
2541
2542                         if (stream_update->gamut_remap)
2543                                 dc_stream_set_gamut_remap(dc, stream);
2544
2545                         if (stream_update->output_csc_transform)
2546                                 dc_stream_program_csc_matrix(dc, stream);
2547
2548                         if (stream_update->dither_option) {
2549                                 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
2550                                 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
2551                                                                         &pipe_ctx->stream->bit_depth_params);
2552                                 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(pipe_ctx->stream_res.opp,
2553                                                 &stream->bit_depth_params,
2554                                                 &stream->clamping);
2555                                 while (odm_pipe) {
2556                                         odm_pipe->stream_res.opp->funcs->opp_program_fmt(odm_pipe->stream_res.opp,
2557                                                         &stream->bit_depth_params,
2558                                                         &stream->clamping);
2559                                         odm_pipe = odm_pipe->next_odm_pipe;
2560                                 }
2561                         }
2562
2563
2564                         /* Full fe update*/
2565                         if (update_type == UPDATE_TYPE_FAST)
2566                                 continue;
2567
2568                         if (stream_update->dsc_config)
2569                                 dp_update_dsc_config(pipe_ctx);
2570
2571                         if (stream_update->pending_test_pattern) {
2572                                 dc_link_dp_set_test_pattern(stream->link,
2573                                         stream->test_pattern.type,
2574                                         stream->test_pattern.color_space,
2575                                         stream->test_pattern.p_link_settings,
2576                                         stream->test_pattern.p_custom_pattern,
2577                                         stream->test_pattern.cust_pattern_size);
2578                         }
2579
2580                         if (stream_update->dpms_off) {
2581                                 if (*stream_update->dpms_off) {
2582                                         core_link_disable_stream(pipe_ctx);
2583                                         /* for dpms, keep acquired resources*/
2584                                         if (pipe_ctx->stream_res.audio && !dc->debug.az_endpoint_mute_only)
2585                                                 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
2586
2587                                         dc->optimized_required = true;
2588
2589                                 } else {
2590                                         if (get_seamless_boot_stream_count(context) == 0)
2591                                                 dc->hwss.prepare_bandwidth(dc, dc->current_state);
2592
2593                                         core_link_enable_stream(dc->current_state, pipe_ctx);
2594                                 }
2595                         }
2596
2597                         if (stream_update->abm_level && pipe_ctx->stream_res.abm) {
2598                                 bool should_program_abm = true;
2599
2600                                 // if otg funcs defined check if blanked before programming
2601                                 if (pipe_ctx->stream_res.tg->funcs->is_blanked)
2602                                         if (pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg))
2603                                                 should_program_abm = false;
2604
2605                                 if (should_program_abm) {
2606                                         if (*stream_update->abm_level == ABM_LEVEL_IMMEDIATE_DISABLE) {
2607                                                 dc->hwss.set_abm_immediate_disable(pipe_ctx);
2608                                         } else {
2609                                                 pipe_ctx->stream_res.abm->funcs->set_abm_level(
2610                                                         pipe_ctx->stream_res.abm, stream->abm_level);
2611                                         }
2612                                 }
2613                         }
2614                 }
2615         }
2616 }
2617
2618 static void commit_planes_for_stream(struct dc *dc,
2619                 struct dc_surface_update *srf_updates,
2620                 int surface_count,
2621                 struct dc_stream_state *stream,
2622                 struct dc_stream_update *stream_update,
2623                 enum surface_update_type update_type,
2624                 struct dc_state *context)
2625 {
2626         int i, j;
2627         struct pipe_ctx *top_pipe_to_program = NULL;
2628
2629 #if defined(CONFIG_DRM_AMD_DC_DCN3_1)
2630         dc_z10_restore(dc);
2631 #endif
2632
2633         if (get_seamless_boot_stream_count(context) > 0 && surface_count > 0) {
2634                 /* Optimize seamless boot flag keeps clocks and watermarks high until
2635                  * first flip. After first flip, optimization is required to lower
2636                  * bandwidth. Important to note that it is expected UEFI will
2637                  * only light up a single display on POST, therefore we only expect
2638                  * one stream with seamless boot flag set.
2639                  */
2640                 if (stream->apply_seamless_boot_optimization) {
2641                         stream->apply_seamless_boot_optimization = false;
2642
2643                         if (get_seamless_boot_stream_count(context) == 0)
2644                                 dc->optimized_required = true;
2645                 }
2646         }
2647
2648         if (update_type == UPDATE_TYPE_FULL) {
2649 #if defined(CONFIG_DRM_AMD_DC_DCN)
2650                 dc_allow_idle_optimizations(dc, false);
2651
2652 #endif
2653                 if (get_seamless_boot_stream_count(context) == 0)
2654                         dc->hwss.prepare_bandwidth(dc, context);
2655
2656                 context_clock_trace(dc, context);
2657         }
2658
2659         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2660                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2661
2662                 if (!pipe_ctx->top_pipe &&
2663                         !pipe_ctx->prev_odm_pipe &&
2664                         pipe_ctx->stream &&
2665                         pipe_ctx->stream == stream) {
2666                         top_pipe_to_program = pipe_ctx;
2667                 }
2668         }
2669
2670 #ifdef CONFIG_DRM_AMD_DC_DCN
2671         if (stream->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE) {
2672                 struct pipe_ctx *mpcc_pipe;
2673                 struct pipe_ctx *odm_pipe;
2674
2675                 for (mpcc_pipe = top_pipe_to_program; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe)
2676                         for (odm_pipe = mpcc_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
2677                                 odm_pipe->ttu_regs.min_ttu_vblank = MAX_TTU;
2678         }
2679 #endif
2680
2681         if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
2682                 if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
2683                         if (should_use_dmub_lock(stream->link)) {
2684                                 union dmub_hw_lock_flags hw_locks = { 0 };
2685                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
2686
2687                                 hw_locks.bits.lock_dig = 1;
2688                                 inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst;
2689
2690                                 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
2691                                                         true,
2692                                                         &hw_locks,
2693                                                         &inst_flags);
2694                         } else
2695                                 top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable(
2696                                                 top_pipe_to_program->stream_res.tg);
2697                 }
2698
2699         if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)
2700                 dc->hwss.interdependent_update_lock(dc, context, true);
2701         else
2702                 /* Lock the top pipe while updating plane addrs, since freesync requires
2703                  *  plane addr update event triggers to be synchronized.
2704                  *  top_pipe_to_program is expected to never be NULL
2705                  */
2706                 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);
2707
2708         // Stream updates
2709         if (stream_update)
2710                 commit_planes_do_stream_update(dc, stream, stream_update, update_type, context);
2711
2712         if (surface_count == 0) {
2713                 /*
2714                  * In case of turning off screen, no need to program front end a second time.
2715                  * just return after program blank.
2716                  */
2717                 if (dc->hwss.apply_ctx_for_surface)
2718                         dc->hwss.apply_ctx_for_surface(dc, stream, 0, context);
2719                 if (dc->hwss.program_front_end_for_ctx)
2720                         dc->hwss.program_front_end_for_ctx(dc, context);
2721
2722                 if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)
2723                         dc->hwss.interdependent_update_lock(dc, context, false);
2724                 else
2725                         dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
2726                 dc->hwss.post_unlock_program_front_end(dc, context);
2727                 return;
2728         }
2729
2730         if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
2731                 for (i = 0; i < surface_count; i++) {
2732                         struct dc_plane_state *plane_state = srf_updates[i].surface;
2733                         /*set logical flag for lock/unlock use*/
2734                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2735                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2736                                 if (!pipe_ctx->plane_state)
2737                                         continue;
2738                                 if (pipe_ctx->plane_state != plane_state)
2739                                         continue;
2740                                 plane_state->triplebuffer_flips = false;
2741                                 if (update_type == UPDATE_TYPE_FAST &&
2742                                         dc->hwss.program_triplebuffer != NULL &&
2743                                         !plane_state->flip_immediate && dc->debug.enable_tri_buf) {
2744                                                 /*triple buffer for VUpdate  only*/
2745                                                 plane_state->triplebuffer_flips = true;
2746                                 }
2747                         }
2748                         if (update_type == UPDATE_TYPE_FULL) {
2749                                 /* force vsync flip when reconfiguring pipes to prevent underflow */
2750                                 plane_state->flip_immediate = false;
2751                         }
2752                 }
2753         }
2754
2755         // Update Type FULL, Surface updates
2756         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2757                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2758
2759                 if (!pipe_ctx->top_pipe &&
2760                         !pipe_ctx->prev_odm_pipe &&
2761                         pipe_ctx->stream &&
2762                         pipe_ctx->stream == stream) {
2763                         struct dc_stream_status *stream_status = NULL;
2764
2765                         if (!pipe_ctx->plane_state)
2766                                 continue;
2767
2768                         /* Full fe update*/
2769                         if (update_type == UPDATE_TYPE_FAST)
2770                                 continue;
2771
2772                         ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);
2773
2774                         if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
2775                                 /*turn off triple buffer for full update*/
2776                                 dc->hwss.program_triplebuffer(
2777                                         dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
2778                         }
2779                         stream_status =
2780                                 stream_get_status(context, pipe_ctx->stream);
2781
2782                         if (dc->hwss.apply_ctx_for_surface)
2783                                 dc->hwss.apply_ctx_for_surface(
2784                                         dc, pipe_ctx->stream, stream_status->plane_count, context);
2785                 }
2786         }
2787         if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) {
2788                 dc->hwss.program_front_end_for_ctx(dc, context);
2789 #ifdef CONFIG_DRM_AMD_DC_DCN
2790                 if (dc->debug.validate_dml_output) {
2791                         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2792                                 struct pipe_ctx cur_pipe = context->res_ctx.pipe_ctx[i];
2793                                 if (cur_pipe.stream == NULL)
2794                                         continue;
2795
2796                                 cur_pipe.plane_res.hubp->funcs->validate_dml_output(
2797                                                 cur_pipe.plane_res.hubp, dc->ctx,
2798                                                 &context->res_ctx.pipe_ctx[i].rq_regs,
2799                                                 &context->res_ctx.pipe_ctx[i].dlg_regs,
2800                                                 &context->res_ctx.pipe_ctx[i].ttu_regs);
2801                         }
2802                 }
2803 #endif
2804         }
2805
2806         // Update Type FAST, Surface updates
2807         if (update_type == UPDATE_TYPE_FAST) {
2808                 if (dc->hwss.set_flip_control_gsl)
2809                         for (i = 0; i < surface_count; i++) {
2810                                 struct dc_plane_state *plane_state = srf_updates[i].surface;
2811
2812                                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2813                                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2814
2815                                         if (pipe_ctx->stream != stream)
2816                                                 continue;
2817
2818                                         if (pipe_ctx->plane_state != plane_state)
2819                                                 continue;
2820
2821                                         // GSL has to be used for flip immediate
2822                                         dc->hwss.set_flip_control_gsl(pipe_ctx,
2823                                                         plane_state->flip_immediate);
2824                                 }
2825                         }
2826
2827                 /* Perform requested Updates */
2828                 for (i = 0; i < surface_count; i++) {
2829                         struct dc_plane_state *plane_state = srf_updates[i].surface;
2830
2831                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2832                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2833
2834                                 if (pipe_ctx->stream != stream)
2835                                         continue;
2836
2837                                 if (pipe_ctx->plane_state != plane_state)
2838                                         continue;
2839                                 /*program triple buffer after lock based on flip type*/
2840                                 if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
2841                                         /*only enable triplebuffer for  fast_update*/
2842                                         dc->hwss.program_triplebuffer(
2843                                                 dc, pipe_ctx, plane_state->triplebuffer_flips);
2844                                 }
2845                                 if (srf_updates[i].flip_addr)
2846                                         dc->hwss.update_plane_addr(dc, pipe_ctx);
2847                         }
2848                 }
2849
2850         }
2851
2852         if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)
2853                 dc->hwss.interdependent_update_lock(dc, context, false);
2854         else
2855                 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
2856
2857         if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
2858                 if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
2859                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
2860                                         top_pipe_to_program->stream_res.tg,
2861                                         CRTC_STATE_VACTIVE);
2862                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
2863                                         top_pipe_to_program->stream_res.tg,
2864                                         CRTC_STATE_VBLANK);
2865                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
2866                                         top_pipe_to_program->stream_res.tg,
2867                                         CRTC_STATE_VACTIVE);
2868
2869                         if (stream && should_use_dmub_lock(stream->link)) {
2870                                 union dmub_hw_lock_flags hw_locks = { 0 };
2871                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
2872
2873                                 hw_locks.bits.lock_dig = 1;
2874                                 inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst;
2875
2876                                 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
2877                                                         false,
2878                                                         &hw_locks,
2879                                                         &inst_flags);
2880                         } else
2881                                 top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_disable(
2882                                         top_pipe_to_program->stream_res.tg);
2883                 }
2884
2885         if (update_type != UPDATE_TYPE_FAST)
2886                 dc->hwss.post_unlock_program_front_end(dc, context);
2887
2888         // Fire manual trigger only when bottom plane is flipped
2889         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2890                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2891
2892                 if (!pipe_ctx->plane_state)
2893                         continue;
2894
2895                 if (pipe_ctx->bottom_pipe || pipe_ctx->next_odm_pipe ||
2896                                 !pipe_ctx->stream || pipe_ctx->stream != stream ||
2897                                 !pipe_ctx->plane_state->update_flags.bits.addr_update ||
2898                                 pipe_ctx->plane_state->skip_manual_trigger)
2899                         continue;
2900
2901                 if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger)
2902                         pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);
2903         }
2904 }
2905
2906 void dc_commit_updates_for_stream(struct dc *dc,
2907                 struct dc_surface_update *srf_updates,
2908                 int surface_count,
2909                 struct dc_stream_state *stream,
2910                 struct dc_stream_update *stream_update,
2911                 struct dc_state *state)
2912 {
2913         const struct dc_stream_status *stream_status;
2914         enum surface_update_type update_type;
2915         struct dc_state *context;
2916         struct dc_context *dc_ctx = dc->ctx;
2917         int i, j;
2918
2919         stream_status = dc_stream_get_status(stream);
2920         context = dc->current_state;
2921
2922         update_type = dc_check_update_surfaces_for_stream(
2923                                 dc, srf_updates, surface_count, stream_update, stream_status);
2924
2925         if (update_type >= update_surface_trace_level)
2926                 update_surface_trace(dc, srf_updates, surface_count);
2927
2928
2929         if (update_type >= UPDATE_TYPE_FULL) {
2930
2931                 /* initialize scratch memory for building context */
2932                 context = dc_create_state(dc);
2933                 if (context == NULL) {
2934                         DC_ERROR("Failed to allocate new validate context!\n");
2935                         return;
2936                 }
2937
2938                 dc_resource_state_copy_construct(state, context);
2939
2940                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2941                         struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];
2942                         struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
2943
2944                         if (new_pipe->plane_state && new_pipe->plane_state != old_pipe->plane_state)
2945                                 new_pipe->plane_state->force_full_update = true;
2946                 }
2947         }
2948
2949
2950         for (i = 0; i < surface_count; i++) {
2951                 struct dc_plane_state *surface = srf_updates[i].surface;
2952
2953                 copy_surface_update_to_plane(surface, &srf_updates[i]);
2954
2955                 if (update_type >= UPDATE_TYPE_MED) {
2956                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2957                                 struct pipe_ctx *pipe_ctx =
2958                                         &context->res_ctx.pipe_ctx[j];
2959
2960                                 if (pipe_ctx->plane_state != surface)
2961                                         continue;
2962
2963                                 resource_build_scaling_params(pipe_ctx);
2964                         }
2965                 }
2966         }
2967
2968         copy_stream_update_to_stream(dc, context, stream, stream_update);
2969
2970         if (update_type >= UPDATE_TYPE_FULL) {
2971                 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) {
2972                         DC_ERROR("Mode validation failed for stream update!\n");
2973                         dc_release_state(context);
2974                         return;
2975                 }
2976         }
2977
2978         TRACE_DC_PIPE_STATE(pipe_ctx, i, MAX_PIPES);
2979
2980         commit_planes_for_stream(
2981                                 dc,
2982                                 srf_updates,
2983                                 surface_count,
2984                                 stream,
2985                                 stream_update,
2986                                 update_type,
2987                                 context);
2988         /*update current_State*/
2989         if (dc->current_state != context) {
2990
2991                 struct dc_state *old = dc->current_state;
2992
2993                 dc->current_state = context;
2994                 dc_release_state(old);
2995
2996                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2997                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2998
2999                         if (pipe_ctx->plane_state && pipe_ctx->stream == stream)
3000                                 pipe_ctx->plane_state->force_full_update = false;
3001                 }
3002         }
3003         /*let's use current_state to update watermark etc*/
3004         if (update_type >= UPDATE_TYPE_FULL) {
3005                 dc_post_update_surfaces_to_stream(dc);
3006
3007                 if (dc_ctx->dce_version >= DCE_VERSION_MAX)
3008                         TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk);
3009                 else
3010                         TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);
3011         }
3012
3013         return;
3014
3015 }
3016
3017 uint8_t dc_get_current_stream_count(struct dc *dc)
3018 {
3019         return dc->current_state->stream_count;
3020 }
3021
3022 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i)
3023 {
3024         if (i < dc->current_state->stream_count)
3025                 return dc->current_state->streams[i];
3026         return NULL;
3027 }
3028
3029 struct dc_stream_state *dc_stream_find_from_link(const struct dc_link *link)
3030 {
3031         uint8_t i;
3032         struct dc_context *ctx = link->ctx;
3033
3034         for (i = 0; i < ctx->dc->current_state->stream_count; i++) {
3035                 if (ctx->dc->current_state->streams[i]->link == link)
3036                         return ctx->dc->current_state->streams[i];
3037         }
3038
3039         return NULL;
3040 }
3041
3042 enum dc_irq_source dc_interrupt_to_irq_source(
3043                 struct dc *dc,
3044                 uint32_t src_id,
3045                 uint32_t ext_id)
3046 {
3047         return dal_irq_service_to_irq_source(dc->res_pool->irqs, src_id, ext_id);
3048 }
3049
3050 /*
3051  * dc_interrupt_set() - Enable/disable an AMD hw interrupt source
3052  */
3053 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable)
3054 {
3055
3056         if (dc == NULL)
3057                 return false;
3058
3059         return dal_irq_service_set(dc->res_pool->irqs, src, enable);
3060 }
3061
3062 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
3063 {
3064         dal_irq_service_ack(dc->res_pool->irqs, src);
3065 }
3066
3067 void dc_power_down_on_boot(struct dc *dc)
3068 {
3069         if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW &&
3070                         dc->hwss.power_down_on_boot)
3071                 dc->hwss.power_down_on_boot(dc);
3072 }
3073
3074 void dc_set_power_state(
3075         struct dc *dc,
3076         enum dc_acpi_cm_power_state power_state)
3077 {
3078         struct kref refcount;
3079         struct display_mode_lib *dml;
3080
3081         if (!dc->current_state)
3082                 return;
3083
3084         switch (power_state) {
3085         case DC_ACPI_CM_POWER_STATE_D0:
3086                 dc_resource_state_construct(dc, dc->current_state);
3087
3088 #if defined(CONFIG_DRM_AMD_DC_DCN3_1)
3089                 dc_z10_restore(dc);
3090 #endif
3091                 if (dc->ctx->dmub_srv)
3092                         dc_dmub_srv_wait_phy_init(dc->ctx->dmub_srv);
3093
3094                 dc->hwss.init_hw(dc);
3095
3096                 if (dc->hwss.init_sys_ctx != NULL &&
3097                         dc->vm_pa_config.valid) {
3098                         dc->hwss.init_sys_ctx(dc->hwseq, dc, &dc->vm_pa_config);
3099                 }
3100
3101                 break;
3102         default:
3103                 ASSERT(dc->current_state->stream_count == 0);
3104                 /* Zero out the current context so that on resume we start with
3105                  * clean state, and dc hw programming optimizations will not
3106                  * cause any trouble.
3107                  */
3108                 dml = kzalloc(sizeof(struct display_mode_lib),
3109                                 GFP_KERNEL);
3110
3111                 ASSERT(dml);
3112                 if (!dml)
3113                         return;
3114
3115                 /* Preserve refcount */
3116                 refcount = dc->current_state->refcount;
3117                 /* Preserve display mode lib */
3118                 memcpy(dml, &dc->current_state->bw_ctx.dml, sizeof(struct display_mode_lib));
3119
3120                 dc_resource_state_destruct(dc->current_state);
3121                 memset(dc->current_state, 0,
3122                                 sizeof(*dc->current_state));
3123
3124                 dc->current_state->refcount = refcount;
3125                 dc->current_state->bw_ctx.dml = *dml;
3126
3127                 kfree(dml);
3128
3129                 break;
3130         }
3131 }
3132
3133 void dc_resume(struct dc *dc)
3134 {
3135         uint32_t i;
3136
3137         for (i = 0; i < dc->link_count; i++)
3138                 core_link_resume(dc->links[i]);
3139 }
3140
3141 bool dc_is_dmcu_initialized(struct dc *dc)
3142 {
3143         struct dmcu *dmcu = dc->res_pool->dmcu;
3144
3145         if (dmcu)
3146                 return dmcu->funcs->is_dmcu_initialized(dmcu);
3147         return false;
3148 }
3149
3150 bool dc_submit_i2c(
3151                 struct dc *dc,
3152                 uint32_t link_index,
3153                 struct i2c_command *cmd)
3154 {
3155
3156         struct dc_link *link = dc->links[link_index];
3157         struct ddc_service *ddc = link->ddc;
3158         return dce_i2c_submit_command(
3159                 dc->res_pool,
3160                 ddc->ddc_pin,
3161                 cmd);
3162 }
3163
3164 bool dc_submit_i2c_oem(
3165                 struct dc *dc,
3166                 struct i2c_command *cmd)
3167 {
3168         struct ddc_service *ddc = dc->res_pool->oem_device;
3169         return dce_i2c_submit_command(
3170                 dc->res_pool,
3171                 ddc->ddc_pin,
3172                 cmd);
3173 }
3174
3175 static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink)
3176 {
3177         if (dc_link->sink_count >= MAX_SINKS_PER_LINK) {
3178                 BREAK_TO_DEBUGGER();
3179                 return false;
3180         }
3181
3182         dc_sink_retain(sink);
3183
3184         dc_link->remote_sinks[dc_link->sink_count] = sink;
3185         dc_link->sink_count++;
3186
3187         return true;
3188 }
3189
3190 /*
3191  * dc_link_add_remote_sink() - Create a sink and attach it to an existing link
3192  *
3193  * EDID length is in bytes
3194  */
3195 struct dc_sink *dc_link_add_remote_sink(
3196                 struct dc_link *link,
3197                 const uint8_t *edid,
3198                 int len,
3199                 struct dc_sink_init_data *init_data)
3200 {
3201         struct dc_sink *dc_sink;
3202         enum dc_edid_status edid_status;
3203
3204         if (len > DC_MAX_EDID_BUFFER_SIZE) {
3205                 dm_error("Max EDID buffer size breached!\n");
3206                 return NULL;
3207         }
3208
3209         if (!init_data) {
3210                 BREAK_TO_DEBUGGER();
3211                 return NULL;
3212         }
3213
3214         if (!init_data->link) {
3215                 BREAK_TO_DEBUGGER();
3216                 return NULL;
3217         }
3218
3219         dc_sink = dc_sink_create(init_data);
3220
3221         if (!dc_sink)
3222                 return NULL;
3223
3224         memmove(dc_sink->dc_edid.raw_edid, edid, len);
3225         dc_sink->dc_edid.length = len;
3226
3227         if (!link_add_remote_sink_helper(
3228                         link,
3229                         dc_sink))
3230                 goto fail_add_sink;
3231
3232         edid_status = dm_helpers_parse_edid_caps(
3233                         link->ctx,
3234                         &dc_sink->dc_edid,
3235                         &dc_sink->edid_caps);
3236
3237         /*
3238          * Treat device as no EDID device if EDID
3239          * parsing fails
3240          */
3241         if (edid_status != EDID_OK) {
3242                 dc_sink->dc_edid.length = 0;
3243                 dm_error("Bad EDID, status%d!\n", edid_status);
3244         }
3245
3246         return dc_sink;
3247
3248 fail_add_sink:
3249         dc_sink_release(dc_sink);
3250         return NULL;
3251 }
3252
3253 /*
3254  * dc_link_remove_remote_sink() - Remove a remote sink from a dc_link
3255  *
3256  * Note that this just removes the struct dc_sink - it doesn't
3257  * program hardware or alter other members of dc_link
3258  */
3259 void dc_link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink)
3260 {
3261         int i;
3262
3263         if (!link->sink_count) {
3264                 BREAK_TO_DEBUGGER();
3265                 return;
3266         }
3267
3268         for (i = 0; i < link->sink_count; i++) {
3269                 if (link->remote_sinks[i] == sink) {
3270                         dc_sink_release(sink);
3271                         link->remote_sinks[i] = NULL;
3272
3273                         /* shrink array to remove empty place */
3274                         while (i < link->sink_count - 1) {
3275                                 link->remote_sinks[i] = link->remote_sinks[i+1];
3276                                 i++;
3277                         }
3278                         link->remote_sinks[i] = NULL;
3279                         link->sink_count--;
3280                         return;
3281                 }
3282         }
3283 }
3284
3285 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info)
3286 {
3287         info->displayClock                              = (unsigned int)state->bw_ctx.bw.dcn.clk.dispclk_khz;
3288         info->engineClock                               = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_khz;
3289         info->memoryClock                               = (unsigned int)state->bw_ctx.bw.dcn.clk.dramclk_khz;
3290         info->maxSupportedDppClock              = (unsigned int)state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz;
3291         info->dppClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.dppclk_khz;
3292         info->socClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.socclk_khz;
3293         info->dcfClockDeepSleep                 = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz;
3294         info->fClock                                    = (unsigned int)state->bw_ctx.bw.dcn.clk.fclk_khz;
3295         info->phyClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.phyclk_khz;
3296 }
3297 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping)
3298 {
3299         if (dc->hwss.set_clock)
3300                 return dc->hwss.set_clock(dc, clock_type, clk_khz, stepping);
3301         return DC_ERROR_UNEXPECTED;
3302 }
3303 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg)
3304 {
3305         if (dc->hwss.get_clock)
3306                 dc->hwss.get_clock(dc, clock_type, clock_cfg);
3307 }
3308
3309 /* enable/disable eDP PSR without specify stream for eDP */
3310 bool dc_set_psr_allow_active(struct dc *dc, bool enable)
3311 {
3312         int i;
3313
3314         for (i = 0; i < dc->current_state->stream_count ; i++) {
3315                 struct dc_link *link;
3316                 struct dc_stream_state *stream = dc->current_state->streams[i];
3317
3318                 link = stream->link;
3319                 if (!link)
3320                         continue;
3321
3322                 if (link->psr_settings.psr_feature_enabled) {
3323                         if (enable && !link->psr_settings.psr_allow_active) {
3324                                 if (!dc_link_set_psr_allow_active(link, true, false, false))
3325                                         return false;
3326                         } else if (!enable && link->psr_settings.psr_allow_active) {
3327                                 if (!dc_link_set_psr_allow_active(link, false, true, false))
3328                                         return false;
3329                         }
3330                 }
3331         }
3332
3333         return true;
3334 }
3335
3336 #if defined(CONFIG_DRM_AMD_DC_DCN)
3337
3338 void dc_allow_idle_optimizations(struct dc *dc, bool allow)
3339 {
3340         if (dc->debug.disable_idle_power_optimizations)
3341                 return;
3342
3343         if (dc->clk_mgr != NULL && dc->clk_mgr->funcs->is_smu_present)
3344                 if (!dc->clk_mgr->funcs->is_smu_present(dc->clk_mgr))
3345                         return;
3346
3347         if (allow == dc->idle_optimizations_allowed)
3348                 return;
3349
3350         if (dc->hwss.apply_idle_power_optimizations && dc->hwss.apply_idle_power_optimizations(dc, allow))
3351                 dc->idle_optimizations_allowed = allow;
3352 }
3353
3354 /*
3355  * blank all streams, and set min and max memory clock to
3356  * lowest and highest DPM level, respectively
3357  */
3358 void dc_unlock_memory_clock_frequency(struct dc *dc)
3359 {
3360         unsigned int i;
3361
3362         for (i = 0; i < MAX_PIPES; i++)
3363                 if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)
3364                         core_link_disable_stream(&dc->current_state->res_ctx.pipe_ctx[i]);
3365
3366         dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, false);
3367         dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
3368 }
3369
3370 /*
3371  * set min memory clock to the min required for current mode,
3372  * max to maxDPM, and unblank streams
3373  */
3374 void dc_lock_memory_clock_frequency(struct dc *dc)
3375 {
3376         unsigned int i;
3377
3378         dc->clk_mgr->funcs->get_memclk_states_from_smu(dc->clk_mgr);
3379         dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, true);
3380         dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
3381
3382         for (i = 0; i < MAX_PIPES; i++)
3383                 if (dc->current_state->res_ctx.pipe_ctx[i].plane_state)
3384                         core_link_enable_stream(dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i]);
3385 }
3386
3387 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane,
3388                 struct dc_cursor_attributes *cursor_attr)
3389 {
3390         if (dc->hwss.does_plane_fit_in_mall && dc->hwss.does_plane_fit_in_mall(dc, plane, cursor_attr))
3391                 return true;
3392         return false;
3393 }
3394
3395 /* cleanup on driver unload */
3396 void dc_hardware_release(struct dc *dc)
3397 {
3398         if (dc->hwss.hardware_release)
3399                 dc->hwss.hardware_release(dc);
3400 }
3401 #endif
3402
3403 /**
3404  * dc_enable_dmub_notifications - Returns whether dmub notification can be enabled
3405  * @dc: dc structure
3406  *
3407  * Returns: True to enable dmub notifications, False otherwise
3408  */
3409 bool dc_enable_dmub_notifications(struct dc *dc)
3410 {
3411         /* dmub aux needs dmub notifications to be enabled */
3412         return dc->debug.enable_dmub_aux_for_legacy_ddc;
3413 }
3414
3415 /**
3416  * dc_process_dmub_aux_transfer_async - Submits aux command to dmub via inbox message
3417  *                                      Sets port index appropriately for legacy DDC
3418  * @dc: dc structure
3419  * @link_index: link index
3420  * @payload: aux payload
3421  *
3422  * Returns: True if successful, False if failure
3423  */
3424 bool dc_process_dmub_aux_transfer_async(struct dc *dc,
3425                                 uint32_t link_index,
3426                                 struct aux_payload *payload)
3427 {
3428         uint8_t action;
3429         union dmub_rb_cmd cmd = {0};
3430         struct dc_dmub_srv *dmub_srv = dc->ctx->dmub_srv;
3431
3432         ASSERT(payload->length <= 16);
3433
3434         cmd.dp_aux_access.header.type = DMUB_CMD__DP_AUX_ACCESS;
3435         cmd.dp_aux_access.header.payload_bytes = 0;
3436         cmd.dp_aux_access.aux_control.type = AUX_CHANNEL_LEGACY_DDC;
3437         cmd.dp_aux_access.aux_control.instance = dc->links[link_index]->ddc_hw_inst;
3438         cmd.dp_aux_access.aux_control.sw_crc_enabled = 0;
3439         cmd.dp_aux_access.aux_control.timeout = 0;
3440         cmd.dp_aux_access.aux_control.dpaux.address = payload->address;
3441         cmd.dp_aux_access.aux_control.dpaux.is_i2c_over_aux = payload->i2c_over_aux;
3442         cmd.dp_aux_access.aux_control.dpaux.length = payload->length;
3443
3444         /* set aux action */
3445         if (payload->i2c_over_aux) {
3446                 if (payload->write) {
3447                         if (payload->mot)
3448                                 action = DP_AUX_REQ_ACTION_I2C_WRITE_MOT;
3449                         else
3450                                 action = DP_AUX_REQ_ACTION_I2C_WRITE;
3451                 } else {
3452                         if (payload->mot)
3453                                 action = DP_AUX_REQ_ACTION_I2C_READ_MOT;
3454                         else
3455                                 action = DP_AUX_REQ_ACTION_I2C_READ;
3456                         }
3457         } else {
3458                 if (payload->write)
3459                         action = DP_AUX_REQ_ACTION_DPCD_WRITE;
3460                 else
3461                         action = DP_AUX_REQ_ACTION_DPCD_READ;
3462         }
3463
3464         cmd.dp_aux_access.aux_control.dpaux.action = action;
3465
3466         if (payload->length && payload->write) {
3467                 memcpy(cmd.dp_aux_access.aux_control.dpaux.data,
3468                         payload->data,
3469                         payload->length
3470                         );
3471         }
3472
3473         dc_dmub_srv_cmd_queue(dmub_srv, &cmd);
3474         dc_dmub_srv_cmd_execute(dmub_srv);
3475         dc_dmub_srv_wait_idle(dmub_srv);
3476
3477         return true;
3478 }
3479
3480 /**
3481  * dc_disable_accelerated_mode - disable accelerated mode
3482  * @dc: dc structure
3483  */
3484 void dc_disable_accelerated_mode(struct dc *dc)
3485 {
3486         bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 0);
3487 }