1 /* SPDX-License-Identifier: MIT */
3 * Copyright 2022 Advanced Micro Devices, Inc.
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6 * copy of this software and associated documentation files (the "Software"),
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9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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27 #ifndef DAL_DC_314_SMU_H_
28 #define DAL_DC_314_SMU_H_
30 #include "smu13_driver_if_v13_0_4.h"
33 WCK_RATIO_1_1 = 0, // DDR5, Wck:ck is always 1:1;
39 struct dcn314_watermarks {
41 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
42 uint32_t MmHubPadding[7]; // SMU internal use
45 struct dcn314_smu_dpm_clks {
46 DpmClocks_t *dpm_clks;
47 union large_integer mc_address;
50 struct display_idle_optimization {
51 unsigned int df_request_disabled : 1;
52 unsigned int phy_ref_clk_off : 1;
53 unsigned int s0i2_rdy : 1;
54 unsigned int reserved : 29;
57 union display_idle_optimization_u {
58 struct display_idle_optimization idle_info;
62 int dcn314_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
63 int dcn314_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
64 int dcn314_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
65 int dcn314_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
66 int dcn314_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz);
67 int dcn314_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
68 void dcn314_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
69 void dcn314_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
70 void dcn314_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
71 void dcn314_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
72 void dcn314_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);
73 void dcn314_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);
74 void dcn314_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
76 void dcn314_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zstate_support_state support);
77 void dcn314_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable);
79 #endif /* DAL_DC_314_SMU_H_ */