drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

   1 /*
   2  * Copyright 2012-16 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/delay.h>
  27 #include "core_types.h"
  28 #include "clk_mgr_internal.h"
  29 #include "reg_helper.h"
  30 #include "dm_helpers.h"
  31 #include "dcn31_smu.h"
  32
  33 #include "yellow_carp_offset.h"
  34 #include "mp/mp_13_0_2_offset.h"
  35 #include "mp/mp_13_0_2_sh_mask.h"
  36
  37 #define REG(reg_name) \
  38         (MP0_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
  39
  40 #define FN(reg_name, field) \
  41         FD(reg_name##__##field)
  42
  43 #define VBIOSSMC_MSG_TestMessage                  0x1
  44 #define VBIOSSMC_MSG_GetSmuVersion                0x2
  45 #define VBIOSSMC_MSG_PowerUpGfx                   0x3
  46 #define VBIOSSMC_MSG_SetDispclkFreq               0x4
  47 #define VBIOSSMC_MSG_SetDprefclkFreq              0x5   //Not used. DPRef is constant
  48 #define VBIOSSMC_MSG_SetDppclkFreq                0x6
  49 #define VBIOSSMC_MSG_SetHardMinDcfclkByFreq       0x7
  50 #define VBIOSSMC_MSG_SetMinDeepSleepDcfclk        0x8
  51 #define VBIOSSMC_MSG_SetPhyclkVoltageByFreq       0x9   //Keep it in case VMIN dees not support phy clk
  52 #define VBIOSSMC_MSG_GetFclkFrequency             0xA
  53 #define VBIOSSMC_MSG_SetDisplayCount              0xB   //Not used anymore
  54 #define VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown 0xC   //Not used anymore
  55 #define VBIOSSMC_MSG_UpdatePmeRestore             0xD
  56 #define VBIOSSMC_MSG_SetVbiosDramAddrHigh         0xE   //Used for WM table txfr
  57 #define VBIOSSMC_MSG_SetVbiosDramAddrLow          0xF
  58 #define VBIOSSMC_MSG_TransferTableSmu2Dram        0x10
  59 #define VBIOSSMC_MSG_TransferTableDram2Smu        0x11
  60 #define VBIOSSMC_MSG_SetDisplayIdleOptimizations  0x12
  61 #define VBIOSSMC_MSG_GetDprefclkFreq              0x13
  62 #define VBIOSSMC_MSG_GetDtbclkFreq                0x14
  63 #define VBIOSSMC_MSG_AllowZstatesEntry            0x15
  64 #define VBIOSSMC_MSG_DisallowZstatesEntry         0x16
  65 #define VBIOSSMC_MSG_SetDtbClk                    0x17
  66 #define VBIOSSMC_Message_Count                    0x18
  67
  68 #define VBIOSSMC_Status_BUSY                      0x0
  69 #define VBIOSSMC_Result_OK                        0x1
  70 #define VBIOSSMC_Result_Failed                    0xFF
  71 #define VBIOSSMC_Result_UnknownCmd                0xFE
  72 #define VBIOSSMC_Result_CmdRejectedPrereq         0xFD
  73 #define VBIOSSMC_Result_CmdRejectedBusy           0xFC
  74
  75 /*
  76  * Function to be used instead of REG_WAIT macro because the wait ends when
  77  * the register is NOT EQUAL to zero, and because the translation in msg_if.h
  78  * won't work with REG_WAIT.
  79  */
  80 static uint32_t dcn31_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)
  81 {
  82         uint32_t res_val = VBIOSSMC_Status_BUSY;
  83
  84         do {
  85                 res_val = REG_READ(MP1_SMN_C2PMSG_91);
  86                 if (res_val != VBIOSSMC_Status_BUSY)
  87                         break;
  88
  89                 if (delay_us >= 1000)
  90                         msleep(delay_us/1000);
  91                 else if (delay_us > 0)
  92                         udelay(delay_us);
  93         } while (max_retries--);
  94
  95         return res_val;
  96 }
  97
  98 int dcn31_smu_send_msg_with_param(
  99                 struct clk_mgr_internal *clk_mgr,
 100                 unsigned int msg_id, unsigned int param)
 101 {
 102         uint32_t result;
 103
 104         result = dcn31_smu_wait_for_response(clk_mgr, 10, 200000);
 105         ASSERT(result == VBIOSSMC_Result_OK);
 106
 107         if (result == VBIOSSMC_Status_BUSY) {
 108                 return -1;
 109         }
 110
 111         /* First clear response register */
 112         REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY);
 113
 114         /* Set the parameter register for the SMU message, unit is Mhz */
 115         REG_WRITE(MP1_SMN_C2PMSG_83, param);
 116
 117         /* Trigger the message transaction by writing the message ID */
 118         REG_WRITE(MP1_SMN_C2PMSG_67, msg_id);
 119
 120         result = dcn31_smu_wait_for_response(clk_mgr, 10, 200000);
 121
 122         if (IS_SMU_TIMEOUT(result)) {
 123                 ASSERT(0);
 124                 dm_helpers_smu_timeout(CTX, msg_id, param, 10 * 200000);
 125         }
 126
 127         return REG_READ(MP1_SMN_C2PMSG_83);
 128 }
 129
 130 int dcn31_smu_get_smu_version(struct clk_mgr_internal *clk_mgr)
 131 {
 132         return dcn31_smu_send_msg_with_param(
 133                         clk_mgr,
 134                         VBIOSSMC_MSG_GetSmuVersion,
 135                         0);
 136 }
 137
 138
 139 int dcn31_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)
 140 {
 141         int actual_dispclk_set_mhz = -1;
 142
 143         if (!clk_mgr->smu_present)
 144                 return requested_dispclk_khz;
 145
 146         /*  Unit of SMU msg parameter is Mhz */
 147         actual_dispclk_set_mhz = dcn31_smu_send_msg_with_param(
 148                         clk_mgr,
 149                         VBIOSSMC_MSG_SetDispclkFreq,
 150                         (requested_dispclk_khz + 999) / 1000);
 151
 152         return actual_dispclk_set_mhz * 1000;
 153 }
 154
 155 int dcn31_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr)
 156 {
 157         int actual_dprefclk_set_mhz = -1;
 158
 159         if (!clk_mgr->smu_present)
 160                 return clk_mgr->base.dprefclk_khz;
 161
 162         actual_dprefclk_set_mhz = dcn31_smu_send_msg_with_param(
 163                         clk_mgr,
 164                         VBIOSSMC_MSG_SetDprefclkFreq,
 165                         (clk_mgr->base.dprefclk_khz + 999) / 1000);
 166
 167         /* TODO: add code for programing DP DTO, currently this is down by command table */
 168
 169         return actual_dprefclk_set_mhz * 1000;
 170 }
 171
 172 int dcn31_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz)
 173 {
 174         int actual_dcfclk_set_mhz = -1;
 175
 176         if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)
 177                 return -1;
 178
 179         if (!clk_mgr->smu_present)
 180                 return requested_dcfclk_khz;
 181
 182         actual_dcfclk_set_mhz = dcn31_smu_send_msg_with_param(
 183                         clk_mgr,
 184                         VBIOSSMC_MSG_SetHardMinDcfclkByFreq,
 185                         (requested_dcfclk_khz + 999) / 1000);
 186
 187         return actual_dcfclk_set_mhz * 1000;
 188 }
 189
 190 int dcn31_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz)
 191 {
 192         int actual_min_ds_dcfclk_mhz = -1;
 193
 194         if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)
 195                 return -1;
 196
 197         if (!clk_mgr->smu_present)
 198                 return requested_min_ds_dcfclk_khz;
 199
 200         actual_min_ds_dcfclk_mhz = dcn31_smu_send_msg_with_param(
 201                         clk_mgr,
 202                         VBIOSSMC_MSG_SetMinDeepSleepDcfclk,
 203                         (requested_min_ds_dcfclk_khz + 999) / 1000);
 204
 205         return actual_min_ds_dcfclk_mhz * 1000;
 206 }
 207
 208 int dcn31_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz)
 209 {
 210         int actual_dppclk_set_mhz = -1;
 211
 212         if (!clk_mgr->smu_present)
 213                 return requested_dpp_khz;
 214
 215         actual_dppclk_set_mhz = dcn31_smu_send_msg_with_param(
 216                         clk_mgr,
 217                         VBIOSSMC_MSG_SetDppclkFreq,
 218                         (requested_dpp_khz + 999) / 1000);
 219
 220         return actual_dppclk_set_mhz * 1000;
 221 }
 222
 223 void dcn31_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info)
 224 {
 225         if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)
 226                 return;
 227
 228         if (!clk_mgr->smu_present)
 229                 return;
 230
 231         //TODO: Work with smu team to define optimization options.
 232         dcn31_smu_send_msg_with_param(
 233                 clk_mgr,
 234                 VBIOSSMC_MSG_SetDisplayIdleOptimizations,
 235                 idle_info);
 236 }
 237
 238 void dcn31_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)
 239 {
 240         union display_idle_optimization_u idle_info = { 0 };
 241
 242         if (!clk_mgr->smu_present)
 243                 return;
 244
 245         if (enable) {
 246                 idle_info.idle_info.df_request_disabled = 1;
 247                 idle_info.idle_info.phy_ref_clk_off = 1;
 248         }
 249
 250         dcn31_smu_send_msg_with_param(
 251                         clk_mgr,
 252                         VBIOSSMC_MSG_SetDisplayIdleOptimizations,
 253                         idle_info.data);
 254 }
 255
 256 void dcn31_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr)
 257 {
 258         if (!clk_mgr->smu_present)
 259                 return;
 260
 261         dcn31_smu_send_msg_with_param(
 262                         clk_mgr,
 263                         VBIOSSMC_MSG_UpdatePmeRestore,
 264                         0);
 265 }
 266
 267 void dcn31_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)
 268 {
 269         if (!clk_mgr->smu_present)
 270                 return;
 271
 272         dcn31_smu_send_msg_with_param(clk_mgr,
 273                         VBIOSSMC_MSG_SetVbiosDramAddrHigh, addr_high);
 274 }
 275
 276 void dcn31_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)
 277 {
 278         if (!clk_mgr->smu_present)
 279                 return;
 280
 281         dcn31_smu_send_msg_with_param(clk_mgr,
 282                         VBIOSSMC_MSG_SetVbiosDramAddrLow, addr_low);
 283 }
 284
 285 void dcn31_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr)
 286 {
 287         if (!clk_mgr->smu_present)
 288                 return;
 289
 290         dcn31_smu_send_msg_with_param(clk_mgr,
 291                         VBIOSSMC_MSG_TransferTableSmu2Dram, TABLE_DPMCLOCKS);
 292 }
 293
 294 void dcn31_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)
 295 {
 296         if (!clk_mgr->smu_present)
 297                 return;
 298
 299         dcn31_smu_send_msg_with_param(clk_mgr,
 300                         VBIOSSMC_MSG_TransferTableDram2Smu, TABLE_WATERMARKS);
 301 }
 302
 303 void dcn31_smu_set_Z9_support(struct clk_mgr_internal *clk_mgr, bool support)
 304 {
 305         //TODO: Work with smu team to define optimization options.
 306         unsigned int msg_id;
 307
 308         if (!clk_mgr->smu_present)
 309                 return;
 310
 311         if (support)
 312                 msg_id = VBIOSSMC_MSG_AllowZstatesEntry;
 313         else
 314                 msg_id = VBIOSSMC_MSG_DisallowZstatesEntry;
 315
 316         dcn31_smu_send_msg_with_param(
 317                 clk_mgr,
 318                 msg_id,
 319                 0);
 320
 321 }
 322
 323 /* Arg = 1: Turn DTB on; 0: Turn DTB CLK OFF. when it is on, it is 600MHZ */
 324 void dcn31_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable)
 325 {
 326         if (!clk_mgr->smu_present)
 327                 return;
 328
 329         dcn31_smu_send_msg_with_param(
 330                         clk_mgr,
 331                         VBIOSSMC_MSG_SetDtbClk,
 332                         enable);
 333 }