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26 #ifndef __DAL_AMDGPU_DM_MST_TYPES_H__
27 #define __DAL_AMDGPU_DM_MST_TYPES_H__
29 #define DP_BRANCH_DEVICE_ID_90CC24 0x90CC24
31 #define SYNAPTICS_RC_COMMAND 0x4B2
32 #define SYNAPTICS_RC_RESULT 0x4B3
33 #define SYNAPTICS_RC_LENGTH 0x4B8
34 #define SYNAPTICS_RC_OFFSET 0x4BC
35 #define SYNAPTICS_RC_DATA 0x4C0
37 #define DP_BRANCH_VENDOR_SPECIFIC_START 0x50C
40 * Panamera MST Hub detection
41 * Offset DPCD 050Eh == 0x5A indicates cascaded MST hub case
42 * Check from beginning of branch device vendor specific field (050Ch)
44 #define IS_SYNAPTICS_PANAMERA(branchDevName) (((int)branchDevName[4] & 0xF0) == 0x50 ? 1 : 0)
45 #define BRANCH_HW_REVISION_PANAMERA_A2 0x10
46 #define SYNAPTICS_CASCADED_HUB_ID 0x5A
47 #define IS_SYNAPTICS_CASCADED_PANAMERA(devName, data) ((IS_SYNAPTICS_PANAMERA(devName) && ((int)data[2] == SYNAPTICS_CASCADED_HUB_ID)) ? 1 : 0)
49 struct amdgpu_display_manager;
50 struct amdgpu_dm_connector;
52 int dm_mst_get_pbn_divider(struct dc_link *link);
54 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
55 struct amdgpu_dm_connector *aconnector,
59 dm_dp_create_fake_mst_encoders(struct amdgpu_device *adev);
61 struct dsc_mst_fairness_vars {
65 struct amdgpu_dm_connector *aconnector;
68 int compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
69 struct dc_state *dc_state,
70 struct dsc_mst_fairness_vars *vars);
72 bool needs_dsc_aux_workaround(struct dc_link *link);
74 int pre_validate_dsc(struct drm_atomic_state *state,
75 struct dm_atomic_state **dm_state_ptr,
76 struct dsc_mst_fairness_vars *vars);
78 enum dc_status dm_dp_mst_is_port_support_mode(
79 struct amdgpu_dm_connector *aconnector,
80 struct dc_stream_state *stream);