2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <drm/display/drm_dp_helper.h>
27 #include <drm/display/drm_dp_mst_helper.h>
28 #include <drm/drm_atomic.h>
29 #include <drm/drm_atomic_helper.h>
30 #include "dm_services.h"
32 #include "amdgpu_dm.h"
33 #include "amdgpu_dm_mst_types.h"
34 #include "amdgpu_dm_hdcp.h"
37 #include "dm_helpers.h"
39 #include "ddc_service_types.h"
40 #include "dpcd_defs.h"
43 #if defined(CONFIG_DEBUG_FS)
44 #include "amdgpu_dm_debugfs.h"
47 #include "dc/dcn20/dcn20_resource.h"
49 #define PEAK_FACTOR_X1000 1006
51 static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
52 struct drm_dp_aux_msg *msg)
55 struct aux_payload payload;
56 enum aux_return_code_type operation_result;
57 struct amdgpu_device *adev;
58 struct ddc_service *ddc;
60 if (WARN_ON(msg->size > 16))
63 payload.address = msg->address;
64 payload.data = msg->buffer;
65 payload.length = msg->size;
66 payload.reply = &msg->reply;
67 payload.i2c_over_aux = (msg->request & DP_AUX_NATIVE_WRITE) == 0;
68 payload.write = (msg->request & DP_AUX_I2C_READ) == 0;
69 payload.mot = (msg->request & DP_AUX_I2C_MOT) != 0;
70 payload.write_status_update =
71 (msg->request & DP_AUX_I2C_WRITE_STATUS_UPDATE) != 0;
72 payload.defer_delay = 0;
74 result = dc_link_aux_transfer_raw(TO_DM_AUX(aux)->ddc_service, &payload,
78 * w/a on certain intel platform where hpd is unexpected to pull low during
79 * 1st sideband message transaction by return AUX_RET_ERROR_HPD_DISCON
80 * aux transaction is succuess in such case, therefore bypass the error
82 ddc = TO_DM_AUX(aux)->ddc_service;
83 adev = ddc->ctx->driver_context;
84 if (adev->dm.aux_hpd_discon_quirk) {
85 if (msg->address == DP_SIDEBAND_MSG_DOWN_REQ_BASE &&
86 operation_result == AUX_RET_ERROR_HPD_DISCON) {
88 operation_result = AUX_RET_SUCCESS;
92 if (payload.write && result >= 0)
96 switch (operation_result) {
99 case AUX_RET_ERROR_HPD_DISCON:
100 case AUX_RET_ERROR_UNKNOWN:
101 case AUX_RET_ERROR_INVALID_OPERATION:
102 case AUX_RET_ERROR_PROTOCOL_ERROR:
105 case AUX_RET_ERROR_INVALID_REPLY:
106 case AUX_RET_ERROR_ENGINE_ACQUIRE:
109 case AUX_RET_ERROR_TIMEOUT:
118 dm_dp_mst_connector_destroy(struct drm_connector *connector)
120 struct amdgpu_dm_connector *aconnector =
121 to_amdgpu_dm_connector(connector);
123 if (aconnector->dc_sink) {
124 dc_link_remove_remote_sink(aconnector->dc_link,
125 aconnector->dc_sink);
126 dc_sink_release(aconnector->dc_sink);
129 kfree(aconnector->edid);
131 drm_connector_cleanup(connector);
132 drm_dp_mst_put_port_malloc(aconnector->mst_output_port);
137 amdgpu_dm_mst_connector_late_register(struct drm_connector *connector)
139 struct amdgpu_dm_connector *amdgpu_dm_connector =
140 to_amdgpu_dm_connector(connector);
143 r = drm_dp_mst_connector_late_register(connector,
144 amdgpu_dm_connector->mst_output_port);
148 #if defined(CONFIG_DEBUG_FS)
149 connector_debugfs_init(amdgpu_dm_connector);
156 amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector)
158 struct amdgpu_dm_connector *aconnector =
159 to_amdgpu_dm_connector(connector);
160 struct drm_dp_mst_port *port = aconnector->mst_output_port;
161 struct amdgpu_dm_connector *root = aconnector->mst_root;
162 struct dc_link *dc_link = aconnector->dc_link;
163 struct dc_sink *dc_sink = aconnector->dc_sink;
165 drm_dp_mst_connector_early_unregister(connector, port);
168 * Release dc_sink for connector which its attached port is
169 * no longer in the mst topology
171 drm_modeset_lock(&root->mst_mgr.base.lock, NULL);
173 if (dc_link->sink_count)
174 dc_link_remove_remote_sink(dc_link, dc_sink);
176 DC_LOG_MST("DM_MST: remove remote sink 0x%p, %d remaining\n",
177 dc_sink, dc_link->sink_count);
179 dc_sink_release(dc_sink);
180 aconnector->dc_sink = NULL;
181 aconnector->edid = NULL;
184 aconnector->mst_status = MST_STATUS_DEFAULT;
185 drm_modeset_unlock(&root->mst_mgr.base.lock);
188 static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
189 .fill_modes = drm_helper_probe_single_connector_modes,
190 .destroy = dm_dp_mst_connector_destroy,
191 .reset = amdgpu_dm_connector_funcs_reset,
192 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
193 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
194 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
195 .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
196 .late_register = amdgpu_dm_mst_connector_late_register,
197 .early_unregister = amdgpu_dm_mst_connector_early_unregister,
200 bool needs_dsc_aux_workaround(struct dc_link *link)
202 if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
203 (link->dpcd_caps.dpcd_rev.raw == DPCD_REV_14 || link->dpcd_caps.dpcd_rev.raw == DPCD_REV_12) &&
204 link->dpcd_caps.sink_count.bits.SINK_COUNT >= 2)
210 static bool is_synaptics_cascaded_panamera(struct dc_link *link, struct drm_dp_mst_port *port)
212 u8 branch_vendor_data[4] = { 0 }; // Vendor data 0x50C ~ 0x50F
214 if (drm_dp_dpcd_read(port->mgr->aux, DP_BRANCH_VENDOR_SPECIFIC_START, &branch_vendor_data, 4) == 4) {
215 if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
216 IS_SYNAPTICS_CASCADED_PANAMERA(link->dpcd_caps.branch_dev_name, branch_vendor_data)) {
217 DRM_INFO("Synaptics Cascaded MST hub\n");
225 static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector)
227 struct dc_sink *dc_sink = aconnector->dc_sink;
228 struct drm_dp_mst_port *port = aconnector->mst_output_port;
229 u8 dsc_caps[16] = { 0 };
230 u8 dsc_branch_dec_caps_raw[3] = { 0 }; // DSC branch decoder caps 0xA0 ~ 0xA2
231 u8 *dsc_branch_dec_caps = NULL;
233 aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port);
236 * drm_dp_mst_dsc_aux_for_port() will return NULL for certain configs
237 * because it only check the dsc/fec caps of the "port variable" and not the dock
239 * This case will return NULL: DSC capabe MST dock connected to a non fec/dsc capable display
241 * Workaround: explicitly check the use case above and use the mst dock's aux as dsc_aux
244 if (!aconnector->dsc_aux && !port->parent->port_parent &&
245 needs_dsc_aux_workaround(aconnector->dc_link))
246 aconnector->dsc_aux = &aconnector->mst_root->dm_dp_aux.aux;
248 /* synaptics cascaded MST hub case */
249 if (!aconnector->dsc_aux && is_synaptics_cascaded_panamera(aconnector->dc_link, port))
250 aconnector->dsc_aux = port->mgr->aux;
252 if (!aconnector->dsc_aux)
255 if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DSC_SUPPORT, dsc_caps, 16) < 0)
258 if (drm_dp_dpcd_read(aconnector->dsc_aux,
259 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0, dsc_branch_dec_caps_raw, 3) == 3)
260 dsc_branch_dec_caps = dsc_branch_dec_caps_raw;
262 if (!dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
263 dsc_caps, dsc_branch_dec_caps,
264 &dc_sink->dsc_caps.dsc_dec_caps))
270 static bool retrieve_downstream_port_device(struct amdgpu_dm_connector *aconnector)
272 union dp_downstream_port_present ds_port_present;
274 if (!aconnector->dsc_aux)
277 if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DOWNSTREAMPORT_PRESENT, &ds_port_present, 1) < 0) {
278 DRM_INFO("Failed to read downstream_port_present 0x05 from DFP of branch device\n");
282 aconnector->mst_downstream_port_present = ds_port_present;
283 DRM_INFO("Downstream port present %d, type %d\n",
284 ds_port_present.fields.PORT_PRESENT, ds_port_present.fields.PORT_TYPE);
289 static int dm_dp_mst_get_modes(struct drm_connector *connector)
291 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
295 return drm_add_edid_modes(connector, NULL);
297 if (!aconnector->edid) {
299 edid = drm_dp_mst_get_edid(connector, &aconnector->mst_root->mst_mgr, aconnector->mst_output_port);
302 amdgpu_dm_set_mst_status(&aconnector->mst_status,
303 MST_REMOTE_EDID, false);
305 drm_connector_update_edid_property(
309 DRM_DEBUG_KMS("Can't get EDID of %s. Add default remote sink.", connector->name);
310 if (!aconnector->dc_sink) {
311 struct dc_sink *dc_sink;
312 struct dc_sink_init_data init_params = {
313 .link = aconnector->dc_link,
314 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
316 dc_sink = dc_link_add_remote_sink(
323 DRM_ERROR("Unable to add a remote sink\n");
327 DC_LOG_MST("DM_MST: add remote sink 0x%p, %d remaining\n",
328 dc_sink, aconnector->dc_link->sink_count);
330 dc_sink->priv = aconnector;
331 aconnector->dc_sink = dc_sink;
337 aconnector->edid = edid;
338 amdgpu_dm_set_mst_status(&aconnector->mst_status,
339 MST_REMOTE_EDID, true);
342 if (aconnector->dc_sink && aconnector->dc_sink->sink_signal == SIGNAL_TYPE_VIRTUAL) {
343 dc_sink_release(aconnector->dc_sink);
344 aconnector->dc_sink = NULL;
347 if (!aconnector->dc_sink) {
348 struct dc_sink *dc_sink;
349 struct dc_sink_init_data init_params = {
350 .link = aconnector->dc_link,
351 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
352 dc_sink = dc_link_add_remote_sink(
354 (uint8_t *)aconnector->edid,
355 (aconnector->edid->extensions + 1) * EDID_LENGTH,
359 DRM_ERROR("Unable to add a remote sink\n");
363 DC_LOG_MST("DM_MST: add remote sink 0x%p, %d remaining\n",
364 dc_sink, aconnector->dc_link->sink_count);
366 dc_sink->priv = aconnector;
367 /* dc_link_add_remote_sink returns a new reference */
368 aconnector->dc_sink = dc_sink;
370 /* when display is unplugged from mst hub, connctor will be
371 * destroyed within dm_dp_mst_connector_destroy. connector
372 * hdcp perperties, like type, undesired, desired, enabled,
373 * will be lost. So, save hdcp properties into hdcp_work within
374 * amdgpu_dm_atomic_commit_tail. if the same display is
375 * plugged back with same display index, its hdcp properties
376 * will be retrieved from hdcp_work within dm_dp_mst_get_modes
378 if (aconnector->dc_sink && connector->state) {
379 struct drm_device *dev = connector->dev;
380 struct amdgpu_device *adev = drm_to_adev(dev);
382 if (adev->dm.hdcp_workqueue) {
383 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
384 struct hdcp_workqueue *hdcp_w =
385 &hdcp_work[aconnector->dc_link->link_index];
387 connector->state->hdcp_content_type =
388 hdcp_w->hdcp_content_type[connector->index];
389 connector->state->content_protection =
390 hdcp_w->content_protection[connector->index];
394 if (aconnector->dc_sink) {
395 amdgpu_dm_update_freesync_caps(
396 connector, aconnector->edid);
398 if (!validate_dsc_caps_on_connector(aconnector))
399 memset(&aconnector->dc_sink->dsc_caps,
400 0, sizeof(aconnector->dc_sink->dsc_caps));
402 if (!retrieve_downstream_port_device(aconnector))
403 memset(&aconnector->mst_downstream_port_present,
404 0, sizeof(aconnector->mst_downstream_port_present));
408 drm_connector_update_edid_property(
409 &aconnector->base, aconnector->edid);
411 ret = drm_add_edid_modes(connector, aconnector->edid);
416 static struct drm_encoder *
417 dm_mst_atomic_best_encoder(struct drm_connector *connector,
418 struct drm_atomic_state *state)
420 struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state,
422 struct drm_device *dev = connector->dev;
423 struct amdgpu_device *adev = drm_to_adev(dev);
424 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(connector_state->crtc);
426 return &adev->dm.mst_encoders[acrtc->crtc_id].base;
430 dm_dp_mst_detect(struct drm_connector *connector,
431 struct drm_modeset_acquire_ctx *ctx, bool force)
433 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
434 struct amdgpu_dm_connector *master = aconnector->mst_root;
435 struct drm_dp_mst_port *port = aconnector->mst_output_port;
436 int connection_status;
438 if (drm_connector_is_unregistered(connector))
439 return connector_status_disconnected;
441 connection_status = drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr,
442 aconnector->mst_output_port);
444 if (port->pdt != DP_PEER_DEVICE_NONE && !port->dpcd_rev) {
448 ret = drm_dp_dpcd_readb(&port->aux, DP_DP13_DPCD_REV, &dpcd_rev);
451 port->dpcd_rev = dpcd_rev;
453 /* Could be DP1.2 DP Rx case*/
455 ret = drm_dp_dpcd_readb(&port->aux, DP_DPCD_REV, &dpcd_rev);
458 port->dpcd_rev = dpcd_rev;
462 DRM_DEBUG_KMS("Can't decide DPCD revision number!");
466 * Could be legacy sink, logical port etc on DP1.2.
467 * Will get Nack under these cases when issue remote
471 DRM_DEBUG_KMS("Can't access DPCD");
472 } else if (port->pdt == DP_PEER_DEVICE_NONE) {
477 * Release dc_sink for connector which unplug event is notified by CSN msg
479 if (connection_status == connector_status_disconnected && aconnector->dc_sink) {
480 if (aconnector->dc_link->sink_count)
481 dc_link_remove_remote_sink(aconnector->dc_link, aconnector->dc_sink);
483 DC_LOG_MST("DM_MST: remove remote sink 0x%p, %d remaining\n",
484 aconnector->dc_link, aconnector->dc_link->sink_count);
486 dc_sink_release(aconnector->dc_sink);
487 aconnector->dc_sink = NULL;
488 aconnector->edid = NULL;
490 amdgpu_dm_set_mst_status(&aconnector->mst_status,
491 MST_REMOTE_EDID | MST_ALLOCATE_NEW_PAYLOAD | MST_CLEAR_ALLOCATED_PAYLOAD,
495 return connection_status;
498 static int dm_dp_mst_atomic_check(struct drm_connector *connector,
499 struct drm_atomic_state *state)
501 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
502 struct drm_dp_mst_topology_mgr *mst_mgr = &aconnector->mst_root->mst_mgr;
503 struct drm_dp_mst_port *mst_port = aconnector->mst_output_port;
505 return drm_dp_atomic_release_time_slots(state, mst_mgr, mst_port);
508 static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = {
509 .get_modes = dm_dp_mst_get_modes,
510 .mode_valid = amdgpu_dm_connector_mode_valid,
511 .atomic_best_encoder = dm_mst_atomic_best_encoder,
512 .detect_ctx = dm_dp_mst_detect,
513 .atomic_check = dm_dp_mst_atomic_check,
516 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
518 drm_encoder_cleanup(encoder);
521 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
522 .destroy = amdgpu_dm_encoder_destroy,
526 dm_dp_create_fake_mst_encoders(struct amdgpu_device *adev)
528 struct drm_device *dev = adev_to_drm(adev);
531 for (i = 0; i < adev->dm.display_indexes_num; i++) {
532 struct amdgpu_encoder *amdgpu_encoder = &adev->dm.mst_encoders[i];
533 struct drm_encoder *encoder = &amdgpu_encoder->base;
535 encoder->possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
539 &amdgpu_encoder->base,
540 &amdgpu_dm_encoder_funcs,
541 DRM_MODE_ENCODER_DPMST,
544 drm_encoder_helper_add(encoder, &amdgpu_dm_encoder_helper_funcs);
548 static struct drm_connector *
549 dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
550 struct drm_dp_mst_port *port,
551 const char *pathprop)
553 struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr);
554 struct drm_device *dev = master->base.dev;
555 struct amdgpu_device *adev = drm_to_adev(dev);
556 struct amdgpu_dm_connector *aconnector;
557 struct drm_connector *connector;
560 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
564 connector = &aconnector->base;
565 aconnector->mst_output_port = port;
566 aconnector->mst_root = master;
567 amdgpu_dm_set_mst_status(&aconnector->mst_status,
570 if (drm_connector_init(
573 &dm_dp_mst_connector_funcs,
574 DRM_MODE_CONNECTOR_DisplayPort)) {
578 drm_connector_helper_add(connector, &dm_dp_mst_connector_helper_funcs);
580 amdgpu_dm_connector_init_helper(
583 DRM_MODE_CONNECTOR_DisplayPort,
585 master->connector_id);
587 for (i = 0; i < adev->dm.display_indexes_num; i++) {
588 drm_connector_attach_encoder(&aconnector->base,
589 &adev->dm.mst_encoders[i].base);
592 connector->max_bpc_property = master->base.max_bpc_property;
593 if (connector->max_bpc_property)
594 drm_connector_attach_max_bpc_property(connector, 8, 16);
596 connector->vrr_capable_property = master->base.vrr_capable_property;
597 if (connector->vrr_capable_property)
598 drm_connector_attach_vrr_capable_property(connector);
600 drm_object_attach_property(
602 dev->mode_config.path_property,
604 drm_object_attach_property(
606 dev->mode_config.tile_property,
609 drm_connector_set_path_property(connector, pathprop);
612 * Initialize connector state before adding the connectror to drm and
615 amdgpu_dm_connector_funcs_reset(connector);
617 drm_dp_mst_get_port_malloc(port);
622 void dm_handle_mst_sideband_msg_ready_event(
623 struct drm_dp_mst_topology_mgr *mgr,
624 enum mst_msg_ready_type msg_rdy_type)
626 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
628 bool new_irq_handled = false;
630 uint8_t dpcd_bytes_to_read;
631 const uint8_t max_process_count = 30;
632 uint8_t process_count = 0;
634 struct amdgpu_dm_connector *aconnector =
635 container_of(mgr, struct amdgpu_dm_connector, mst_mgr);
638 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
640 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
641 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
642 /* DPCD 0x200 - 0x201 for downstream IRQ */
643 dpcd_addr = DP_SINK_COUNT;
645 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
646 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
647 dpcd_addr = DP_SINK_COUNT_ESI;
650 mutex_lock(&aconnector->handle_mst_msg_ready);
652 while (process_count < max_process_count) {
653 u8 ack[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = {};
657 dret = drm_dp_dpcd_read(
658 &aconnector->dm_dp_aux.aux,
663 if (dret != dpcd_bytes_to_read) {
664 DRM_DEBUG_KMS("DPCD read and acked number is not as expected!");
668 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
670 switch (msg_rdy_type) {
671 case DOWN_REP_MSG_RDY_EVENT:
672 /* Only handle DOWN_REP_MSG_RDY case*/
673 esi[1] &= DP_DOWN_REP_MSG_RDY;
675 case UP_REQ_MSG_RDY_EVENT:
676 /* Only handle UP_REQ_MSG_RDY case*/
677 esi[1] &= DP_UP_REQ_MSG_RDY;
680 /* Handle both cases*/
681 esi[1] &= (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY);
689 if (aconnector->mst_mgr.mst_state)
690 drm_dp_mst_hpd_irq_handle_event(&aconnector->mst_mgr,
695 if (new_irq_handled) {
696 /* ACK at DPCD to notify down stream */
697 for (retry = 0; retry < 3; retry++) {
700 wret = drm_dp_dpcd_writeb(&aconnector->dm_dp_aux.aux,
708 DRM_ERROR("Failed to ack MST event.\n");
712 drm_dp_mst_hpd_irq_send_new_request(&aconnector->mst_mgr);
714 new_irq_handled = false;
720 mutex_unlock(&aconnector->handle_mst_msg_ready);
722 if (process_count == max_process_count)
723 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
726 static void dm_handle_mst_down_rep_msg_ready(struct drm_dp_mst_topology_mgr *mgr)
728 dm_handle_mst_sideband_msg_ready_event(mgr, DOWN_REP_MSG_RDY_EVENT);
731 static const struct drm_dp_mst_topology_cbs dm_mst_cbs = {
732 .add_connector = dm_dp_add_mst_connector,
733 .poll_hpd_irq = dm_handle_mst_down_rep_msg_ready,
736 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
737 struct amdgpu_dm_connector *aconnector,
740 struct dc_link_settings max_link_enc_cap = {0};
742 aconnector->dm_dp_aux.aux.name =
743 kasprintf(GFP_KERNEL, "AMDGPU DM aux hw bus %d",
745 aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer;
746 aconnector->dm_dp_aux.aux.drm_dev = dm->ddev;
747 aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc;
749 drm_dp_aux_init(&aconnector->dm_dp_aux.aux);
750 drm_dp_cec_register_connector(&aconnector->dm_dp_aux.aux,
753 if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
756 dc_link_dp_get_max_link_enc_cap(aconnector->dc_link, &max_link_enc_cap);
757 aconnector->mst_mgr.cbs = &dm_mst_cbs;
758 drm_dp_mst_topology_mgr_init(&aconnector->mst_mgr, adev_to_drm(dm->adev),
759 &aconnector->dm_dp_aux.aux, 16, 4, aconnector->connector_id);
761 drm_connector_attach_dp_subconnector_property(&aconnector->base);
764 int dm_mst_get_pbn_divider(struct dc_link *link)
769 return dc_link_bandwidth_kbps(link,
770 dc_link_get_link_cap(link)) / (8 * 1000 * 54);
773 struct dsc_mst_fairness_params {
774 struct dc_crtc_timing *timing;
775 struct dc_sink *sink;
776 struct dc_dsc_bw_range bw_range;
777 bool compression_possible;
778 struct drm_dp_mst_port *port;
779 enum dsc_clock_force_state clock_force_enable;
780 uint32_t num_slices_h;
781 uint32_t num_slices_v;
782 uint32_t bpp_overwrite;
783 struct amdgpu_dm_connector *aconnector;
786 static uint16_t get_fec_overhead_multiplier(struct dc_link *dc_link)
789 uint16_t fec_overhead_multiplier_x1000 = PBN_FEC_OVERHEAD_MULTIPLIER_8B_10B;
791 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(dc_link);
792 if (link_coding_cap == DP_128b_132b_ENCODING)
793 fec_overhead_multiplier_x1000 = PBN_FEC_OVERHEAD_MULTIPLIER_128B_132B;
795 return fec_overhead_multiplier_x1000;
798 static int kbps_to_peak_pbn(int kbps, uint16_t fec_overhead_multiplier_x1000)
800 u64 peak_kbps = kbps;
803 peak_kbps *= fec_overhead_multiplier_x1000;
804 peak_kbps = div_u64(peak_kbps, 1000 * 1000);
805 return (int) DIV64_U64_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000));
808 static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params,
809 struct dsc_mst_fairness_vars *vars,
813 struct drm_connector *drm_connector;
815 struct dc_dsc_config_options dsc_options = {0};
817 for (i = 0; i < count; i++) {
818 drm_connector = ¶ms[i].aconnector->base;
820 dc_dsc_get_default_config_option(params[i].sink->ctx->dc, &dsc_options);
821 dsc_options.max_target_bpp_limit_override_x16 = drm_connector->display_info.max_dsc_bpp * 16;
823 memset(¶ms[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg));
824 if (vars[i + k].dsc_enabled && dc_dsc_compute_config(
825 params[i].sink->ctx->dc->res_pool->dscs[0],
826 ¶ms[i].sink->dsc_caps.dsc_dec_caps,
830 ¶ms[i].timing->dsc_cfg)) {
831 params[i].timing->flags.DSC = 1;
833 if (params[i].bpp_overwrite)
834 params[i].timing->dsc_cfg.bits_per_pixel = params[i].bpp_overwrite;
836 params[i].timing->dsc_cfg.bits_per_pixel = vars[i + k].bpp_x16;
838 if (params[i].num_slices_h)
839 params[i].timing->dsc_cfg.num_slices_h = params[i].num_slices_h;
841 if (params[i].num_slices_v)
842 params[i].timing->dsc_cfg.num_slices_v = params[i].num_slices_v;
844 params[i].timing->flags.DSC = 0;
846 params[i].timing->dsc_cfg.mst_pbn = vars[i + k].pbn;
849 for (i = 0; i < count; i++) {
850 if (params[i].sink) {
851 if (params[i].sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
852 params[i].sink->sink_signal != SIGNAL_TYPE_NONE)
853 DRM_DEBUG_DRIVER("%s i=%d dispname=%s\n", __func__, i,
854 params[i].sink->edid_caps.display_name);
857 DRM_DEBUG_DRIVER("dsc=%d bits_per_pixel=%d pbn=%d\n",
858 params[i].timing->flags.DSC,
859 params[i].timing->dsc_cfg.bits_per_pixel,
864 static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn)
866 struct dc_dsc_config dsc_config;
869 struct drm_connector *drm_connector = ¶m.aconnector->base;
870 struct dc_dsc_config_options dsc_options = {0};
872 dc_dsc_get_default_config_option(param.sink->ctx->dc, &dsc_options);
873 dsc_options.max_target_bpp_limit_override_x16 = drm_connector->display_info.max_dsc_bpp * 16;
875 kbps = div_u64((u64)pbn * 994 * 8 * 54, 64);
876 dc_dsc_compute_config(
877 param.sink->ctx->dc->res_pool->dscs[0],
878 ¶m.sink->dsc_caps.dsc_dec_caps,
880 (int) kbps, param.timing, &dsc_config);
882 return dsc_config.bits_per_pixel;
885 static int increase_dsc_bpp(struct drm_atomic_state *state,
886 struct drm_dp_mst_topology_state *mst_state,
887 struct dc_link *dc_link,
888 struct dsc_mst_fairness_params *params,
889 struct dsc_mst_fairness_vars *vars,
894 bool bpp_increased[MAX_PIPES];
895 int initial_slack[MAX_PIPES];
896 int min_initial_slack;
898 int remaining_to_increase = 0;
899 int link_timeslots_used;
902 uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link);
904 for (i = 0; i < count; i++) {
905 if (vars[i + k].dsc_enabled) {
907 kbps_to_peak_pbn(params[i].bw_range.max_kbps, fec_overhead_multiplier_x1000) - vars[i + k].pbn;
908 bpp_increased[i] = false;
909 remaining_to_increase += 1;
911 initial_slack[i] = 0;
912 bpp_increased[i] = true;
916 while (remaining_to_increase) {
918 min_initial_slack = -1;
919 for (i = 0; i < count; i++) {
920 if (!bpp_increased[i]) {
921 if (min_initial_slack == -1 || min_initial_slack > initial_slack[i]) {
922 min_initial_slack = initial_slack[i];
928 if (next_index == -1)
931 link_timeslots_used = 0;
933 for (i = 0; i < count; i++)
934 link_timeslots_used += DIV_ROUND_UP(vars[i + k].pbn, mst_state->pbn_div);
937 (63 - link_timeslots_used) / remaining_to_increase * mst_state->pbn_div;
939 if (initial_slack[next_index] > fair_pbn_alloc) {
940 vars[next_index].pbn += fair_pbn_alloc;
941 ret = drm_dp_atomic_find_time_slots(state,
942 params[next_index].port->mgr,
943 params[next_index].port,
944 vars[next_index].pbn);
948 ret = drm_dp_mst_atomic_check(state);
950 vars[next_index].bpp_x16 = bpp_x16_from_pbn(params[next_index], vars[next_index].pbn);
952 vars[next_index].pbn -= fair_pbn_alloc;
953 ret = drm_dp_atomic_find_time_slots(state,
954 params[next_index].port->mgr,
955 params[next_index].port,
956 vars[next_index].pbn);
961 vars[next_index].pbn += initial_slack[next_index];
962 ret = drm_dp_atomic_find_time_slots(state,
963 params[next_index].port->mgr,
964 params[next_index].port,
965 vars[next_index].pbn);
969 ret = drm_dp_mst_atomic_check(state);
971 vars[next_index].bpp_x16 = params[next_index].bw_range.max_target_bpp_x16;
973 vars[next_index].pbn -= initial_slack[next_index];
974 ret = drm_dp_atomic_find_time_slots(state,
975 params[next_index].port->mgr,
976 params[next_index].port,
977 vars[next_index].pbn);
983 bpp_increased[next_index] = true;
984 remaining_to_increase--;
989 static int try_disable_dsc(struct drm_atomic_state *state,
990 struct dc_link *dc_link,
991 struct dsc_mst_fairness_params *params,
992 struct dsc_mst_fairness_vars *vars,
997 bool tried[MAX_PIPES];
998 int kbps_increase[MAX_PIPES];
999 int max_kbps_increase;
1001 int remaining_to_try = 0;
1003 uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link);
1005 for (i = 0; i < count; i++) {
1006 if (vars[i + k].dsc_enabled
1007 && vars[i + k].bpp_x16 == params[i].bw_range.max_target_bpp_x16
1008 && params[i].clock_force_enable == DSC_CLK_FORCE_DEFAULT) {
1009 kbps_increase[i] = params[i].bw_range.stream_kbps - params[i].bw_range.max_kbps;
1011 remaining_to_try += 1;
1013 kbps_increase[i] = 0;
1018 while (remaining_to_try) {
1020 max_kbps_increase = -1;
1021 for (i = 0; i < count; i++) {
1023 if (max_kbps_increase == -1 || max_kbps_increase < kbps_increase[i]) {
1024 max_kbps_increase = kbps_increase[i];
1030 if (next_index == -1)
1033 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps, fec_overhead_multiplier_x1000);
1034 ret = drm_dp_atomic_find_time_slots(state,
1035 params[next_index].port->mgr,
1036 params[next_index].port,
1037 vars[next_index].pbn);
1041 ret = drm_dp_mst_atomic_check(state);
1043 vars[next_index].dsc_enabled = false;
1044 vars[next_index].bpp_x16 = 0;
1046 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.max_kbps, fec_overhead_multiplier_x1000);
1047 ret = drm_dp_atomic_find_time_slots(state,
1048 params[next_index].port->mgr,
1049 params[next_index].port,
1050 vars[next_index].pbn);
1055 tried[next_index] = true;
1061 static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
1062 struct dc_state *dc_state,
1063 struct dc_link *dc_link,
1064 struct dsc_mst_fairness_vars *vars,
1065 struct drm_dp_mst_topology_mgr *mgr,
1066 int *link_vars_start_index)
1068 struct dc_stream_state *stream;
1069 struct dsc_mst_fairness_params params[MAX_PIPES];
1070 struct amdgpu_dm_connector *aconnector;
1071 struct drm_dp_mst_topology_state *mst_state = drm_atomic_get_mst_topology_state(state, mgr);
1074 bool debugfs_overwrite = false;
1075 uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link);
1077 memset(params, 0, sizeof(params));
1079 if (IS_ERR(mst_state))
1080 return PTR_ERR(mst_state);
1083 for (i = 0; i < dc_state->stream_count; i++) {
1084 struct dc_dsc_policy dsc_policy = {0};
1086 stream = dc_state->streams[i];
1088 if (stream->link != dc_link)
1091 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
1095 if (!aconnector->mst_output_port)
1098 stream->timing.flags.DSC = 0;
1100 params[count].timing = &stream->timing;
1101 params[count].sink = stream->sink;
1102 params[count].aconnector = aconnector;
1103 params[count].port = aconnector->mst_output_port;
1104 params[count].clock_force_enable = aconnector->dsc_settings.dsc_force_enable;
1105 if (params[count].clock_force_enable == DSC_CLK_FORCE_ENABLE)
1106 debugfs_overwrite = true;
1107 params[count].num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
1108 params[count].num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
1109 params[count].bpp_overwrite = aconnector->dsc_settings.dsc_bits_per_pixel;
1110 params[count].compression_possible = stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported;
1111 dc_dsc_get_policy_for_timing(params[count].timing, 0, &dsc_policy);
1112 if (!dc_dsc_compute_bandwidth_range(
1113 stream->sink->ctx->dc->res_pool->dscs[0],
1114 stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
1115 dsc_policy.min_target_bpp * 16,
1116 dsc_policy.max_target_bpp * 16,
1117 &stream->sink->dsc_caps.dsc_dec_caps,
1118 &stream->timing, ¶ms[count].bw_range))
1119 params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
1129 /* k is start index of vars for current phy link used by mst hub */
1130 k = *link_vars_start_index;
1131 /* set vars start index for next mst hub phy link */
1132 *link_vars_start_index += count;
1134 /* Try no compression */
1135 for (i = 0; i < count; i++) {
1136 vars[i + k].aconnector = params[i].aconnector;
1137 vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps, fec_overhead_multiplier_x1000);
1138 vars[i + k].dsc_enabled = false;
1139 vars[i + k].bpp_x16 = 0;
1140 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr, params[i].port,
1145 ret = drm_dp_mst_atomic_check(state);
1146 if (ret == 0 && !debugfs_overwrite) {
1147 set_dsc_configs_from_fairness_vars(params, vars, count, k);
1149 } else if (ret != -ENOSPC) {
1153 /* Try max compression */
1154 for (i = 0; i < count; i++) {
1155 if (params[i].compression_possible && params[i].clock_force_enable != DSC_CLK_FORCE_DISABLE) {
1156 vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps, fec_overhead_multiplier_x1000);
1157 vars[i + k].dsc_enabled = true;
1158 vars[i + k].bpp_x16 = params[i].bw_range.min_target_bpp_x16;
1159 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr,
1160 params[i].port, vars[i + k].pbn);
1164 vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps, fec_overhead_multiplier_x1000);
1165 vars[i + k].dsc_enabled = false;
1166 vars[i + k].bpp_x16 = 0;
1167 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr,
1168 params[i].port, vars[i + k].pbn);
1173 ret = drm_dp_mst_atomic_check(state);
1177 /* Optimize degree of compression */
1178 ret = increase_dsc_bpp(state, mst_state, dc_link, params, vars, count, k);
1182 ret = try_disable_dsc(state, dc_link, params, vars, count, k);
1186 set_dsc_configs_from_fairness_vars(params, vars, count, k);
1191 static bool is_dsc_need_re_compute(
1192 struct drm_atomic_state *state,
1193 struct dc_state *dc_state,
1194 struct dc_link *dc_link)
1197 bool is_dsc_need_re_compute = false;
1198 struct amdgpu_dm_connector *stream_on_link[MAX_PIPES];
1199 int new_stream_on_link_num = 0;
1200 struct amdgpu_dm_connector *aconnector;
1201 struct dc_stream_state *stream;
1202 const struct dc *dc = dc_link->dc;
1204 /* only check phy used by dsc mst branch */
1205 if (dc_link->type != dc_connection_mst_branch)
1208 if (!(dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT ||
1209 dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT))
1212 for (i = 0; i < MAX_PIPES; i++)
1213 stream_on_link[i] = NULL;
1215 /* check if there is mode change in new request */
1216 for (i = 0; i < dc_state->stream_count; i++) {
1217 struct drm_crtc_state *new_crtc_state;
1218 struct drm_connector_state *new_conn_state;
1220 stream = dc_state->streams[i];
1224 /* check if stream using the same link for mst */
1225 if (stream->link != dc_link)
1228 aconnector = (struct amdgpu_dm_connector *) stream->dm_stream_context;
1232 stream_on_link[new_stream_on_link_num] = aconnector;
1233 new_stream_on_link_num++;
1235 new_conn_state = drm_atomic_get_new_connector_state(state, &aconnector->base);
1236 if (!new_conn_state)
1239 if (IS_ERR(new_conn_state))
1242 if (!new_conn_state->crtc)
1245 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
1246 if (!new_crtc_state)
1249 if (IS_ERR(new_crtc_state))
1252 if (new_crtc_state->enable && new_crtc_state->active) {
1253 if (new_crtc_state->mode_changed || new_crtc_state->active_changed ||
1254 new_crtc_state->connectors_changed)
1259 /* check current_state if there stream on link but it is not in
1262 for (i = 0; i < dc->current_state->stream_count; i++) {
1263 stream = dc->current_state->streams[i];
1264 /* only check stream on the mst hub */
1265 if (stream->link != dc_link)
1268 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
1272 for (j = 0; j < new_stream_on_link_num; j++) {
1273 if (stream_on_link[j]) {
1274 if (aconnector == stream_on_link[j])
1279 if (j == new_stream_on_link_num) {
1280 /* not in new state */
1281 is_dsc_need_re_compute = true;
1286 return is_dsc_need_re_compute;
1289 int compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
1290 struct dc_state *dc_state,
1291 struct dsc_mst_fairness_vars *vars)
1294 struct dc_stream_state *stream;
1295 bool computed_streams[MAX_PIPES];
1296 struct amdgpu_dm_connector *aconnector;
1297 struct drm_dp_mst_topology_mgr *mst_mgr;
1298 struct resource_pool *res_pool;
1299 int link_vars_start_index = 0;
1302 for (i = 0; i < dc_state->stream_count; i++)
1303 computed_streams[i] = false;
1305 for (i = 0; i < dc_state->stream_count; i++) {
1306 stream = dc_state->streams[i];
1307 res_pool = stream->ctx->dc->res_pool;
1309 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
1312 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
1314 if (!aconnector || !aconnector->dc_sink || !aconnector->mst_output_port)
1317 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported)
1320 if (computed_streams[i])
1323 if (!res_pool->funcs->remove_stream_from_ctx ||
1324 res_pool->funcs->remove_stream_from_ctx(stream->ctx->dc, dc_state, stream) != DC_OK)
1327 if (!is_dsc_need_re_compute(state, dc_state, stream->link))
1330 mst_mgr = aconnector->mst_output_port->mgr;
1331 ret = compute_mst_dsc_configs_for_link(state, dc_state, stream->link, vars, mst_mgr,
1332 &link_vars_start_index);
1336 for (j = 0; j < dc_state->stream_count; j++) {
1337 if (dc_state->streams[j]->link == stream->link)
1338 computed_streams[j] = true;
1342 for (i = 0; i < dc_state->stream_count; i++) {
1343 stream = dc_state->streams[i];
1345 if (stream->timing.flags.DSC == 1)
1346 if (dc_stream_add_dsc_to_resource(stream->ctx->dc, dc_state, stream) != DC_OK)
1353 static int pre_compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
1354 struct dc_state *dc_state,
1355 struct dsc_mst_fairness_vars *vars)
1358 struct dc_stream_state *stream;
1359 bool computed_streams[MAX_PIPES];
1360 struct amdgpu_dm_connector *aconnector;
1361 struct drm_dp_mst_topology_mgr *mst_mgr;
1362 int link_vars_start_index = 0;
1365 for (i = 0; i < dc_state->stream_count; i++)
1366 computed_streams[i] = false;
1368 for (i = 0; i < dc_state->stream_count; i++) {
1369 stream = dc_state->streams[i];
1371 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
1374 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
1376 if (!aconnector || !aconnector->dc_sink || !aconnector->mst_output_port)
1379 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported)
1382 if (computed_streams[i])
1385 if (!is_dsc_need_re_compute(state, dc_state, stream->link))
1388 mst_mgr = aconnector->mst_output_port->mgr;
1389 ret = compute_mst_dsc_configs_for_link(state, dc_state, stream->link, vars, mst_mgr,
1390 &link_vars_start_index);
1394 for (j = 0; j < dc_state->stream_count; j++) {
1395 if (dc_state->streams[j]->link == stream->link)
1396 computed_streams[j] = true;
1403 static int find_crtc_index_in_state_by_stream(struct drm_atomic_state *state,
1404 struct dc_stream_state *stream)
1407 struct drm_crtc *crtc;
1408 struct drm_crtc_state *new_state, *old_state;
1410 for_each_oldnew_crtc_in_state(state, crtc, old_state, new_state, i) {
1411 struct dm_crtc_state *dm_state = to_dm_crtc_state(new_state);
1413 if (dm_state->stream == stream)
1419 static bool is_link_to_dschub(struct dc_link *dc_link)
1421 union dpcd_dsc_basic_capabilities *dsc_caps =
1422 &dc_link->dpcd_caps.dsc_caps.dsc_basic_caps;
1424 /* only check phy used by dsc mst branch */
1425 if (dc_link->type != dc_connection_mst_branch)
1428 if (!(dsc_caps->fields.dsc_support.DSC_SUPPORT ||
1429 dsc_caps->fields.dsc_support.DSC_PASSTHROUGH_SUPPORT))
1434 static bool is_dsc_precompute_needed(struct drm_atomic_state *state)
1437 struct drm_crtc *crtc;
1438 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
1441 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1442 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(new_crtc_state);
1444 if (!amdgpu_dm_find_first_crtc_matching_connector(state, crtc)) {
1448 if (dm_crtc_state->stream && dm_crtc_state->stream->link)
1449 if (is_link_to_dschub(dm_crtc_state->stream->link))
1455 int pre_validate_dsc(struct drm_atomic_state *state,
1456 struct dm_atomic_state **dm_state_ptr,
1457 struct dsc_mst_fairness_vars *vars)
1460 struct dm_atomic_state *dm_state;
1461 struct dc_state *local_dc_state = NULL;
1464 if (!is_dsc_precompute_needed(state)) {
1465 DRM_INFO_ONCE("DSC precompute is not needed.\n");
1468 ret = dm_atomic_get_state(state, dm_state_ptr);
1470 DRM_INFO_ONCE("dm_atomic_get_state() failed\n");
1473 dm_state = *dm_state_ptr;
1476 * create local vailable for dc_state. copy content of streams of dm_state->context
1477 * to local variable. make sure stream pointer of local variable not the same as stream
1478 * from dm_state->context.
1481 local_dc_state = kmemdup(dm_state->context, sizeof(struct dc_state), GFP_KERNEL);
1482 if (!local_dc_state)
1485 for (i = 0; i < local_dc_state->stream_count; i++) {
1486 struct dc_stream_state *stream = dm_state->context->streams[i];
1487 int ind = find_crtc_index_in_state_by_stream(state, stream);
1490 struct amdgpu_dm_connector *aconnector;
1491 struct drm_connector_state *drm_new_conn_state;
1492 struct dm_connector_state *dm_new_conn_state;
1493 struct dm_crtc_state *dm_old_crtc_state;
1496 amdgpu_dm_find_first_crtc_matching_connector(state,
1497 state->crtcs[ind].ptr);
1498 drm_new_conn_state =
1499 drm_atomic_get_new_connector_state(state,
1501 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
1502 dm_old_crtc_state = to_dm_crtc_state(state->crtcs[ind].old_state);
1504 local_dc_state->streams[i] =
1505 create_validate_stream_for_sink(aconnector,
1506 &state->crtcs[ind].new_state->mode,
1508 dm_old_crtc_state->stream);
1509 if (local_dc_state->streams[i] == NULL) {
1519 ret = pre_compute_mst_dsc_configs_for_state(state, local_dc_state, vars);
1521 DRM_INFO_ONCE("pre_compute_mst_dsc_configs_for_state() failed\n");
1527 * compare local_streams -> timing with dm_state->context,
1528 * if the same set crtc_state->mode-change = 0;
1530 for (i = 0; i < local_dc_state->stream_count; i++) {
1531 struct dc_stream_state *stream = dm_state->context->streams[i];
1533 if (local_dc_state->streams[i] &&
1534 dc_is_timing_changed(stream, local_dc_state->streams[i])) {
1535 DRM_INFO_ONCE("crtc[%d] needs mode_changed\n", i);
1537 int ind = find_crtc_index_in_state_by_stream(state, stream);
1540 state->crtcs[ind].new_state->mode_changed = 0;
1544 for (i = 0; i < local_dc_state->stream_count; i++) {
1545 struct dc_stream_state *stream = dm_state->context->streams[i];
1547 if (local_dc_state->streams[i] != stream)
1548 dc_stream_release(local_dc_state->streams[i]);
1551 kfree(local_dc_state);
1556 static unsigned int kbps_from_pbn(unsigned int pbn)
1558 unsigned int kbps = pbn;
1560 kbps *= (1000000 / PEAK_FACTOR_X1000);
1568 static bool is_dsc_common_config_possible(struct dc_stream_state *stream,
1569 struct dc_dsc_bw_range *bw_range)
1571 struct dc_dsc_policy dsc_policy = {0};
1573 dc_dsc_get_policy_for_timing(&stream->timing, 0, &dsc_policy);
1574 dc_dsc_compute_bandwidth_range(stream->sink->ctx->dc->res_pool->dscs[0],
1575 stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
1576 dsc_policy.min_target_bpp * 16,
1577 dsc_policy.max_target_bpp * 16,
1578 &stream->sink->dsc_caps.dsc_dec_caps,
1579 &stream->timing, bw_range);
1581 return bw_range->max_target_bpp_x16 && bw_range->min_target_bpp_x16;
1584 enum dc_status dm_dp_mst_is_port_support_mode(
1585 struct amdgpu_dm_connector *aconnector,
1586 struct dc_stream_state *stream)
1588 int bpp, pbn, branch_max_throughput_mps = 0;
1589 struct dc_link_settings cur_link_settings;
1590 unsigned int end_to_end_bw_in_kbps = 0;
1591 unsigned int upper_link_bw_in_kbps = 0, down_link_bw_in_kbps = 0;
1592 unsigned int max_compressed_bw_in_kbps = 0;
1593 struct dc_dsc_bw_range bw_range = {0};
1594 struct drm_dp_mst_topology_mgr *mst_mgr;
1597 * check if the mode could be supported if DSC pass-through is supported
1598 * AND check if there enough bandwidth available to support the mode
1601 if (is_dsc_common_config_possible(stream, &bw_range) &&
1602 aconnector->mst_output_port->passthrough_aux) {
1603 mst_mgr = aconnector->mst_output_port->mgr;
1604 mutex_lock(&mst_mgr->lock);
1606 cur_link_settings = stream->link->verified_link_cap;
1608 upper_link_bw_in_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
1611 down_link_bw_in_kbps = kbps_from_pbn(aconnector->mst_output_port->full_pbn);
1613 /* pick the bottleneck */
1614 end_to_end_bw_in_kbps = min(upper_link_bw_in_kbps,
1615 down_link_bw_in_kbps);
1617 mutex_unlock(&mst_mgr->lock);
1620 * use the maximum dsc compression bandwidth as the required
1621 * bandwidth for the mode
1623 max_compressed_bw_in_kbps = bw_range.min_kbps;
1625 if (end_to_end_bw_in_kbps < max_compressed_bw_in_kbps) {
1626 DRM_DEBUG_DRIVER("Mode does not fit into DSC pass-through bandwidth validation\n");
1627 return DC_FAIL_BANDWIDTH_VALIDATE;
1630 /* check if mode could be supported within full_pbn */
1631 bpp = convert_dc_color_depth_into_bpc(stream->timing.display_color_depth) * 3;
1632 pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp, false);
1634 if (pbn > aconnector->mst_output_port->full_pbn)
1635 return DC_FAIL_BANDWIDTH_VALIDATE;
1638 /* check is mst dsc output bandwidth branch_overall_throughput_0_mps */
1639 switch (stream->timing.pixel_encoding) {
1640 case PIXEL_ENCODING_RGB:
1641 case PIXEL_ENCODING_YCBCR444:
1642 branch_max_throughput_mps =
1643 aconnector->dc_sink->dsc_caps.dsc_dec_caps.branch_overall_throughput_0_mps;
1645 case PIXEL_ENCODING_YCBCR422:
1646 case PIXEL_ENCODING_YCBCR420:
1647 branch_max_throughput_mps =
1648 aconnector->dc_sink->dsc_caps.dsc_dec_caps.branch_overall_throughput_1_mps;
1654 if (branch_max_throughput_mps != 0 &&
1655 ((stream->timing.pix_clk_100hz / 10) > branch_max_throughput_mps * 1000))
1656 return DC_FAIL_BANDWIDTH_VALIDATE;