drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/version.h>
  27 #include <drm/drm_atomic.h>
  28 #include <drm/drm_atomic_helper.h>
  29 #include <drm/drm_dp_mst_helper.h>
  30 #include <drm/drm_dp_helper.h>
  31 #include "dm_services.h"
  32 #include "amdgpu.h"
  33 #include "amdgpu_dm.h"
  34 #include "amdgpu_dm_mst_types.h"
  35
  36 #include "dc.h"
  37 #include "dm_helpers.h"
  38
  39 #include "dc_link_ddc.h"
  40
  41 #include "i2caux_interface.h"
  42 #if defined(CONFIG_DEBUG_FS)
  43 #include "amdgpu_dm_debugfs.h"
  44 #endif
  45
  46 #if defined(CONFIG_DRM_AMD_DC_DCN)
  47 #include "dc/dcn20/dcn20_resource.h"
  48 #endif
  49
  50 static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
  51                                   struct drm_dp_aux_msg *msg)
  52 {
  53         ssize_t result = 0;
  54         struct aux_payload payload;
  55         enum aux_channel_operation_result operation_result;
  56
  57         if (WARN_ON(msg->size > 16))
  58                 return -E2BIG;
  59
  60         payload.address = msg->address;
  61         payload.data = msg->buffer;
  62         payload.length = msg->size;
  63         payload.reply = &msg->reply;
  64         payload.i2c_over_aux = (msg->request & DP_AUX_NATIVE_WRITE) == 0;
  65         payload.write = (msg->request & DP_AUX_I2C_READ) == 0;
  66         payload.mot = (msg->request & DP_AUX_I2C_MOT) != 0;
  67         payload.defer_delay = 0;
  68
  69         result = dc_link_aux_transfer_raw(TO_DM_AUX(aux)->ddc_service, &payload,
  70                                       &operation_result);
  71
  72         if (payload.write && result >= 0)
  73                 result = msg->size;
  74
  75         if (result < 0)
  76                 switch (operation_result) {
  77                 case AUX_CHANNEL_OPERATION_SUCCEEDED:
  78                         break;
  79                 case AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON:
  80                 case AUX_CHANNEL_OPERATION_FAILED_REASON_UNKNOWN:
  81                         result = -EIO;
  82                         break;
  83                 case AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY:
  84                 case AUX_CHANNEL_OPERATION_FAILED_ENGINE_ACQUIRE:
  85                         result = -EBUSY;
  86                         break;
  87                 case AUX_CHANNEL_OPERATION_FAILED_TIMEOUT:
  88                         result = -ETIMEDOUT;
  89                         break;
  90                 }
  91
  92         return result;
  93 }
  94
  95 static void
  96 dm_dp_mst_connector_destroy(struct drm_connector *connector)
  97 {
  98         struct amdgpu_dm_connector *aconnector =
  99                 to_amdgpu_dm_connector(connector);
 100
 101         if (aconnector->dc_sink) {
 102                 dc_link_remove_remote_sink(aconnector->dc_link,
 103                                            aconnector->dc_sink);
 104                 dc_sink_release(aconnector->dc_sink);
 105         }
 106
 107         kfree(aconnector->edid);
 108
 109         drm_connector_cleanup(connector);
 110         drm_dp_mst_put_port_malloc(aconnector->port);
 111         kfree(aconnector);
 112 }
 113
 114 static int
 115 amdgpu_dm_mst_connector_late_register(struct drm_connector *connector)
 116 {
 117         struct amdgpu_dm_connector *amdgpu_dm_connector =
 118                 to_amdgpu_dm_connector(connector);
 119         int r;
 120
 121         r = drm_dp_mst_connector_late_register(connector,
 122                                                amdgpu_dm_connector->port);
 123         if (r < 0)
 124                 return r;
 125
 126 #if defined(CONFIG_DEBUG_FS)
 127         connector_debugfs_init(amdgpu_dm_connector);
 128 #endif
 129
 130         return 0;
 131 }
 132
 133 static void
 134 amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector)
 135 {
 136         struct amdgpu_dm_connector *amdgpu_dm_connector =
 137                 to_amdgpu_dm_connector(connector);
 138         struct drm_dp_mst_port *port = amdgpu_dm_connector->port;
 139
 140         drm_dp_mst_connector_early_unregister(connector, port);
 141 }
 142
 143 static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
 144         .fill_modes = drm_helper_probe_single_connector_modes,
 145         .destroy = dm_dp_mst_connector_destroy,
 146         .reset = amdgpu_dm_connector_funcs_reset,
 147         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
 148         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 149         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
 150         .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
 151         .late_register = amdgpu_dm_mst_connector_late_register,
 152         .early_unregister = amdgpu_dm_mst_connector_early_unregister,
 153 };
 154
 155 #if defined(CONFIG_DRM_AMD_DC_DCN)
 156 static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector)
 157 {
 158         struct dc_sink *dc_sink = aconnector->dc_sink;
 159         struct drm_dp_mst_port *port = aconnector->port;
 160         u8 dsc_caps[16] = { 0 };
 161
 162         aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port);
 163 #if defined(CONFIG_HP_HOOK_WORKAROUND)
 164         /*
 165          * drm_dp_mst_dsc_aux_for_port() will return NULL for certain configs
 166          * because it only check the dsc/fec caps of the "port variable" and not the dock
 167          *
 168          * This case will return NULL: DSC capabe MST dock connected to a non fec/dsc capable display
 169          *
 170          * Workaround: explicitly check the use case above and use the mst dock's aux as dsc_aux
 171          *
 172          */
 173
 174         if (!aconnector->dsc_aux && !port->parent->port_parent)
 175                 aconnector->dsc_aux = &aconnector->mst_port->dm_dp_aux.aux;
 176 #endif
 177         if (!aconnector->dsc_aux)
 178                 return false;
 179
 180         if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DSC_SUPPORT, dsc_caps, 16) < 0)
 181                 return false;
 182
 183         if (!dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
 184                                    dsc_caps, NULL,
 185                                    &dc_sink->dsc_caps.dsc_dec_caps))
 186                 return false;
 187
 188         return true;
 189 }
 190 #endif
 191
 192 static int dm_dp_mst_get_modes(struct drm_connector *connector)
 193 {
 194         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 195         int ret = 0;
 196
 197         if (!aconnector)
 198                 return drm_add_edid_modes(connector, NULL);
 199
 200         if (!aconnector->edid) {
 201                 struct edid *edid;
 202                 edid = drm_dp_mst_get_edid(connector, &aconnector->mst_port->mst_mgr, aconnector->port);
 203
 204                 if (!edid) {
 205                         drm_connector_update_edid_property(
 206                                 &aconnector->base,
 207                                 NULL);
 208                         return ret;
 209                 }
 210
 211                 aconnector->edid = edid;
 212         }
 213
 214         if (aconnector->dc_sink && aconnector->dc_sink->sink_signal == SIGNAL_TYPE_VIRTUAL) {
 215                 dc_sink_release(aconnector->dc_sink);
 216                 aconnector->dc_sink = NULL;
 217         }
 218
 219         if (!aconnector->dc_sink) {
 220                 struct dc_sink *dc_sink;
 221                 struct dc_sink_init_data init_params = {
 222                                 .link = aconnector->dc_link,
 223                                 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
 224                 dc_sink = dc_link_add_remote_sink(
 225                         aconnector->dc_link,
 226                         (uint8_t *)aconnector->edid,
 227                         (aconnector->edid->extensions + 1) * EDID_LENGTH,
 228                         &init_params);
 229
 230                 dc_sink->priv = aconnector;
 231                 /* dc_link_add_remote_sink returns a new reference */
 232                 aconnector->dc_sink = dc_sink;
 233
 234                 if (aconnector->dc_sink) {
 235                         amdgpu_dm_update_freesync_caps(
 236                                         connector, aconnector->edid);
 237
 238 #if defined(CONFIG_DRM_AMD_DC_DCN)
 239                         if (!validate_dsc_caps_on_connector(aconnector))
 240                                 memset(&aconnector->dc_sink->dsc_caps,
 241                                        0, sizeof(aconnector->dc_sink->dsc_caps));
 242 #endif
 243                 }
 244         }
 245
 246         drm_connector_update_edid_property(
 247                                         &aconnector->base, aconnector->edid);
 248
 249         ret = drm_add_edid_modes(connector, aconnector->edid);
 250
 251         return ret;
 252 }
 253
 254 static struct drm_encoder *
 255 dm_mst_atomic_best_encoder(struct drm_connector *connector,
 256                            struct drm_atomic_state *state)
 257 {
 258         struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state,
 259                                                                                          connector);
 260         struct drm_device *dev = connector->dev;
 261         struct amdgpu_device *adev = drm_to_adev(dev);
 262         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(connector_state->crtc);
 263
 264         return &adev->dm.mst_encoders[acrtc->crtc_id].base;
 265 }
 266
 267 static int
 268 dm_dp_mst_detect(struct drm_connector *connector,
 269                  struct drm_modeset_acquire_ctx *ctx, bool force)
 270 {
 271         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 272         struct amdgpu_dm_connector *master = aconnector->mst_port;
 273
 274         return drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr,
 275                                       aconnector->port);
 276 }
 277
 278 static int dm_dp_mst_atomic_check(struct drm_connector *connector,
 279                                 struct drm_atomic_state *state)
 280 {
 281         struct drm_connector_state *new_conn_state =
 282                         drm_atomic_get_new_connector_state(state, connector);
 283         struct drm_connector_state *old_conn_state =
 284                         drm_atomic_get_old_connector_state(state, connector);
 285         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 286         struct drm_crtc_state *new_crtc_state;
 287         struct drm_dp_mst_topology_mgr *mst_mgr;
 288         struct drm_dp_mst_port *mst_port;
 289
 290         mst_port = aconnector->port;
 291         mst_mgr = &aconnector->mst_port->mst_mgr;
 292
 293         if (!old_conn_state->crtc)
 294                 return 0;
 295
 296         if (new_conn_state->crtc) {
 297                 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
 298                 if (!new_crtc_state ||
 299                     !drm_atomic_crtc_needs_modeset(new_crtc_state) ||
 300                     new_crtc_state->enable)
 301                         return 0;
 302                 }
 303
 304         return drm_dp_atomic_release_vcpi_slots(state,
 305                                                 mst_mgr,
 306                                                 mst_port);
 307 }
 308
 309 static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = {
 310         .get_modes = dm_dp_mst_get_modes,
 311         .mode_valid = amdgpu_dm_connector_mode_valid,
 312         .atomic_best_encoder = dm_mst_atomic_best_encoder,
 313         .detect_ctx = dm_dp_mst_detect,
 314         .atomic_check = dm_dp_mst_atomic_check,
 315 };
 316
 317 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
 318 {
 319         drm_encoder_cleanup(encoder);
 320         kfree(encoder);
 321 }
 322
 323 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
 324         .destroy = amdgpu_dm_encoder_destroy,
 325 };
 326
 327 void
 328 dm_dp_create_fake_mst_encoders(struct amdgpu_device *adev)
 329 {
 330         struct drm_device *dev = adev_to_drm(adev);
 331         int i;
 332
 333         for (i = 0; i < adev->dm.display_indexes_num; i++) {
 334                 struct amdgpu_encoder *amdgpu_encoder = &adev->dm.mst_encoders[i];
 335                 struct drm_encoder *encoder = &amdgpu_encoder->base;
 336
 337                 encoder->possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
 338
 339                 drm_encoder_init(
 340                         dev,
 341                         &amdgpu_encoder->base,
 342                         &amdgpu_dm_encoder_funcs,
 343                         DRM_MODE_ENCODER_DPMST,
 344                         NULL);
 345
 346                 drm_encoder_helper_add(encoder, &amdgpu_dm_encoder_helper_funcs);
 347         }
 348 }
 349
 350 static struct drm_connector *
 351 dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
 352                         struct drm_dp_mst_port *port,
 353                         const char *pathprop)
 354 {
 355         struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr);
 356         struct drm_device *dev = master->base.dev;
 357         struct amdgpu_device *adev = drm_to_adev(dev);
 358         struct amdgpu_dm_connector *aconnector;
 359         struct drm_connector *connector;
 360         int i;
 361
 362         aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
 363         if (!aconnector)
 364                 return NULL;
 365
 366         connector = &aconnector->base;
 367         aconnector->port = port;
 368         aconnector->mst_port = master;
 369
 370         if (drm_connector_init(
 371                 dev,
 372                 connector,
 373                 &dm_dp_mst_connector_funcs,
 374                 DRM_MODE_CONNECTOR_DisplayPort)) {
 375                 kfree(aconnector);
 376                 return NULL;
 377         }
 378         drm_connector_helper_add(connector, &dm_dp_mst_connector_helper_funcs);
 379
 380         amdgpu_dm_connector_init_helper(
 381                 &adev->dm,
 382                 aconnector,
 383                 DRM_MODE_CONNECTOR_DisplayPort,
 384                 master->dc_link,
 385                 master->connector_id);
 386
 387         for (i = 0; i < adev->dm.display_indexes_num; i++) {
 388                 drm_connector_attach_encoder(&aconnector->base,
 389                                              &adev->dm.mst_encoders[i].base);
 390         }
 391
 392         connector->max_bpc_property = master->base.max_bpc_property;
 393         if (connector->max_bpc_property)
 394                 drm_connector_attach_max_bpc_property(connector, 8, 16);
 395
 396         connector->vrr_capable_property = master->base.vrr_capable_property;
 397         if (connector->vrr_capable_property)
 398                 drm_connector_attach_vrr_capable_property(connector);
 399
 400         drm_object_attach_property(
 401                 &connector->base,
 402                 dev->mode_config.path_property,
 403                 0);
 404         drm_object_attach_property(
 405                 &connector->base,
 406                 dev->mode_config.tile_property,
 407                 0);
 408
 409         drm_connector_set_path_property(connector, pathprop);
 410
 411         /*
 412          * Initialize connector state before adding the connectror to drm and
 413          * framebuffer lists
 414          */
 415         amdgpu_dm_connector_funcs_reset(connector);
 416
 417         drm_dp_mst_get_port_malloc(port);
 418
 419         return connector;
 420 }
 421
 422 static const struct drm_dp_mst_topology_cbs dm_mst_cbs = {
 423         .add_connector = dm_dp_add_mst_connector,
 424 };
 425
 426 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
 427                                        struct amdgpu_dm_connector *aconnector,
 428                                        int link_index)
 429 {
 430         aconnector->dm_dp_aux.aux.name =
 431                 kasprintf(GFP_KERNEL, "AMDGPU DM aux hw bus %d",
 432                           link_index);
 433         aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer;
 434         aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc;
 435
 436         drm_dp_aux_init(&aconnector->dm_dp_aux.aux);
 437         drm_dp_cec_register_connector(&aconnector->dm_dp_aux.aux,
 438                                       &aconnector->base);
 439
 440         if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
 441                 return;
 442
 443         aconnector->mst_mgr.cbs = &dm_mst_cbs;
 444         drm_dp_mst_topology_mgr_init(
 445                 &aconnector->mst_mgr,
 446                 adev_to_drm(dm->adev),
 447                 &aconnector->dm_dp_aux.aux,
 448                 16,
 449                 4,
 450                 aconnector->connector_id);
 451
 452         drm_connector_attach_dp_subconnector_property(&aconnector->base);
 453 }
 454
 455 int dm_mst_get_pbn_divider(struct dc_link *link)
 456 {
 457         if (!link)
 458                 return 0;
 459
 460         return dc_link_bandwidth_kbps(link,
 461                         dc_link_get_link_cap(link)) / (8 * 1000 * 54);
 462 }
 463
 464 #if defined(CONFIG_DRM_AMD_DC_DCN)
 465
 466 struct dsc_mst_fairness_params {
 467         struct dc_crtc_timing *timing;
 468         struct dc_sink *sink;
 469         struct dc_dsc_bw_range bw_range;
 470         bool compression_possible;
 471         struct drm_dp_mst_port *port;
 472         enum dsc_clock_force_state clock_force_enable;
 473         uint32_t num_slices_h;
 474         uint32_t num_slices_v;
 475         uint32_t bpp_overwrite;
 476 };
 477
 478 struct dsc_mst_fairness_vars {
 479         int pbn;
 480         bool dsc_enabled;
 481         int bpp_x16;
 482 };
 483
 484 static int kbps_to_peak_pbn(int kbps)
 485 {
 486         u64 peak_kbps = kbps;
 487
 488         peak_kbps *= 1006;
 489         peak_kbps = div_u64(peak_kbps, 1000);
 490         return (int) DIV64_U64_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000));
 491 }
 492
 493 static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params,
 494                 struct dsc_mst_fairness_vars *vars,
 495                 int count)
 496 {
 497         int i;
 498
 499         for (i = 0; i < count; i++) {
 500                 memset(&params[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg));
 501                 if (vars[i].dsc_enabled && dc_dsc_compute_config(
 502                                         params[i].sink->ctx->dc->res_pool->dscs[0],
 503                                         &params[i].sink->dsc_caps.dsc_dec_caps,
 504                                         params[i].sink->ctx->dc->debug.dsc_min_slice_height_override,
 505                                         0,
 506                                         0,
 507                                         params[i].timing,
 508                                         &params[i].timing->dsc_cfg)) {
 509                         params[i].timing->flags.DSC = 1;
 510
 511                         if (params[i].bpp_overwrite)
 512                                 params[i].timing->dsc_cfg.bits_per_pixel = params[i].bpp_overwrite;
 513                         else
 514                                 params[i].timing->dsc_cfg.bits_per_pixel = vars[i].bpp_x16;
 515
 516                         if (params[i].num_slices_h)
 517                                 params[i].timing->dsc_cfg.num_slices_h = params[i].num_slices_h;
 518
 519                         if (params[i].num_slices_v)
 520                                 params[i].timing->dsc_cfg.num_slices_v = params[i].num_slices_v;
 521                 } else {
 522                         params[i].timing->flags.DSC = 0;
 523                 }
 524         }
 525 }
 526
 527 static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn)
 528 {
 529         struct dc_dsc_config dsc_config;
 530         u64 kbps;
 531
 532         kbps = div_u64((u64)pbn * 994 * 8 * 54, 64);
 533         dc_dsc_compute_config(
 534                         param.sink->ctx->dc->res_pool->dscs[0],
 535                         &param.sink->dsc_caps.dsc_dec_caps,
 536                         param.sink->ctx->dc->debug.dsc_min_slice_height_override,
 537                         0,
 538                         (int) kbps, param.timing, &dsc_config);
 539
 540         return dsc_config.bits_per_pixel;
 541 }
 542
 543 static void increase_dsc_bpp(struct drm_atomic_state *state,
 544                              struct dc_link *dc_link,
 545                              struct dsc_mst_fairness_params *params,
 546                              struct dsc_mst_fairness_vars *vars,
 547                              int count)
 548 {
 549         int i;
 550         bool bpp_increased[MAX_PIPES];
 551         int initial_slack[MAX_PIPES];
 552         int min_initial_slack;
 553         int next_index;
 554         int remaining_to_increase = 0;
 555         int pbn_per_timeslot;
 556         int link_timeslots_used;
 557         int fair_pbn_alloc;
 558
 559         pbn_per_timeslot = dm_mst_get_pbn_divider(dc_link);
 560
 561         for (i = 0; i < count; i++) {
 562                 if (vars[i].dsc_enabled) {
 563                         initial_slack[i] = kbps_to_peak_pbn(params[i].bw_range.max_kbps) - vars[i].pbn;
 564                         bpp_increased[i] = false;
 565                         remaining_to_increase += 1;
 566                 } else {
 567                         initial_slack[i] = 0;
 568                         bpp_increased[i] = true;
 569                 }
 570         }
 571
 572         while (remaining_to_increase) {
 573                 next_index = -1;
 574                 min_initial_slack = -1;
 575                 for (i = 0; i < count; i++) {
 576                         if (!bpp_increased[i]) {
 577                                 if (min_initial_slack == -1 || min_initial_slack > initial_slack[i]) {
 578                                         min_initial_slack = initial_slack[i];
 579                                         next_index = i;
 580                                 }
 581                         }
 582                 }
 583
 584                 if (next_index == -1)
 585                         break;
 586
 587                 link_timeslots_used = 0;
 588
 589                 for (i = 0; i < count; i++)
 590                         link_timeslots_used += DIV_ROUND_UP(vars[i].pbn, pbn_per_timeslot);
 591
 592                 fair_pbn_alloc = (63 - link_timeslots_used) / remaining_to_increase * pbn_per_timeslot;
 593
 594                 if (initial_slack[next_index] > fair_pbn_alloc) {
 595                         vars[next_index].pbn += fair_pbn_alloc;
 596                         if (drm_dp_atomic_find_vcpi_slots(state,
 597                                                           params[next_index].port->mgr,
 598                                                           params[next_index].port,
 599                                                           vars[next_index].pbn,
 600                                                           pbn_per_timeslot) < 0)
 601                                 return;
 602                         if (!drm_dp_mst_atomic_check(state)) {
 603                                 vars[next_index].bpp_x16 = bpp_x16_from_pbn(params[next_index], vars[next_index].pbn);
 604                         } else {
 605                                 vars[next_index].pbn -= fair_pbn_alloc;
 606                                 if (drm_dp_atomic_find_vcpi_slots(state,
 607                                                                   params[next_index].port->mgr,
 608                                                                   params[next_index].port,
 609                                                                   vars[next_index].pbn,
 610                                                                   pbn_per_timeslot) < 0)
 611                                         return;
 612                         }
 613                 } else {
 614                         vars[next_index].pbn += initial_slack[next_index];
 615                         if (drm_dp_atomic_find_vcpi_slots(state,
 616                                                           params[next_index].port->mgr,
 617                                                           params[next_index].port,
 618                                                           vars[next_index].pbn,
 619                                                           pbn_per_timeslot) < 0)
 620                                 return;
 621                         if (!drm_dp_mst_atomic_check(state)) {
 622                                 vars[next_index].bpp_x16 = params[next_index].bw_range.max_target_bpp_x16;
 623                         } else {
 624                                 vars[next_index].pbn -= initial_slack[next_index];
 625                                 if (drm_dp_atomic_find_vcpi_slots(state,
 626                                                                   params[next_index].port->mgr,
 627                                                                   params[next_index].port,
 628                                                                   vars[next_index].pbn,
 629                                                                   pbn_per_timeslot) < 0)
 630                                         return;
 631                         }
 632                 }
 633
 634                 bpp_increased[next_index] = true;
 635                 remaining_to_increase--;
 636         }
 637 }
 638
 639 static void try_disable_dsc(struct drm_atomic_state *state,
 640                             struct dc_link *dc_link,
 641                             struct dsc_mst_fairness_params *params,
 642                             struct dsc_mst_fairness_vars *vars,
 643                             int count)
 644 {
 645         int i;
 646         bool tried[MAX_PIPES];
 647         int kbps_increase[MAX_PIPES];
 648         int max_kbps_increase;
 649         int next_index;
 650         int remaining_to_try = 0;
 651
 652         for (i = 0; i < count; i++) {
 653                 if (vars[i].dsc_enabled
 654                                 && vars[i].bpp_x16 == params[i].bw_range.max_target_bpp_x16
 655                                 && params[i].clock_force_enable == DSC_CLK_FORCE_DEFAULT) {
 656                         kbps_increase[i] = params[i].bw_range.stream_kbps - params[i].bw_range.max_kbps;
 657                         tried[i] = false;
 658                         remaining_to_try += 1;
 659                 } else {
 660                         kbps_increase[i] = 0;
 661                         tried[i] = true;
 662                 }
 663         }
 664
 665         while (remaining_to_try) {
 666                 next_index = -1;
 667                 max_kbps_increase = -1;
 668                 for (i = 0; i < count; i++) {
 669                         if (!tried[i]) {
 670                                 if (max_kbps_increase == -1 || max_kbps_increase < kbps_increase[i]) {
 671                                         max_kbps_increase = kbps_increase[i];
 672                                         next_index = i;
 673                                 }
 674                         }
 675                 }
 676
 677                 if (next_index == -1)
 678                         break;
 679
 680                 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps);
 681                 if (drm_dp_atomic_find_vcpi_slots(state,
 682                                                   params[next_index].port->mgr,
 683                                                   params[next_index].port,
 684                                                   vars[next_index].pbn,
 685                                                   dm_mst_get_pbn_divider(dc_link)) < 0)
 686                         return;
 687
 688                 if (!drm_dp_mst_atomic_check(state)) {
 689                         vars[next_index].dsc_enabled = false;
 690                         vars[next_index].bpp_x16 = 0;
 691                 } else {
 692                         vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.max_kbps);
 693                         if (drm_dp_atomic_find_vcpi_slots(state,
 694                                                           params[next_index].port->mgr,
 695                                                           params[next_index].port,
 696                                                           vars[next_index].pbn,
 697                                                           dm_mst_get_pbn_divider(dc_link)) < 0)
 698                                 return;
 699                 }
 700
 701                 tried[next_index] = true;
 702                 remaining_to_try--;
 703         }
 704 }
 705
 706 static bool compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
 707                                              struct dc_state *dc_state,
 708                                              struct dc_link *dc_link)
 709 {
 710         int i;
 711         struct dc_stream_state *stream;
 712         struct dsc_mst_fairness_params params[MAX_PIPES];
 713         struct dsc_mst_fairness_vars vars[MAX_PIPES];
 714         struct amdgpu_dm_connector *aconnector;
 715         int count = 0;
 716         bool debugfs_overwrite = false;
 717
 718         memset(params, 0, sizeof(params));
 719
 720         /* Set up params */
 721         for (i = 0; i < dc_state->stream_count; i++) {
 722                 struct dc_dsc_policy dsc_policy = {0};
 723
 724                 stream = dc_state->streams[i];
 725
 726                 if (stream->link != dc_link)
 727                         continue;
 728
 729                 stream->timing.flags.DSC = 0;
 730
 731                 params[count].timing = &stream->timing;
 732                 params[count].sink = stream->sink;
 733                 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 734                 params[count].port = aconnector->port;
 735                 params[count].clock_force_enable = aconnector->dsc_settings.dsc_force_enable;
 736                 if (params[count].clock_force_enable == DSC_CLK_FORCE_ENABLE)
 737                         debugfs_overwrite = true;
 738                 params[count].num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
 739                 params[count].num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
 740                 params[count].bpp_overwrite = aconnector->dsc_settings.dsc_bits_per_pixel;
 741                 params[count].compression_possible = stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported;
 742                 dc_dsc_get_policy_for_timing(params[count].timing, 0, &dsc_policy);
 743                 if (!dc_dsc_compute_bandwidth_range(
 744                                 stream->sink->ctx->dc->res_pool->dscs[0],
 745                                 stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
 746                                 dsc_policy.min_target_bpp,
 747                                 dsc_policy.max_target_bpp,
 748                                 &stream->sink->dsc_caps.dsc_dec_caps,
 749                                 &stream->timing, &params[count].bw_range))
 750                         params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
 751
 752                 count++;
 753         }
 754         /* Try no compression */
 755         for (i = 0; i < count; i++) {
 756                 vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
 757                 vars[i].dsc_enabled = false;
 758                 vars[i].bpp_x16 = 0;
 759                 if (drm_dp_atomic_find_vcpi_slots(state,
 760                                                  params[i].port->mgr,
 761                                                  params[i].port,
 762                                                  vars[i].pbn,
 763                                                  dm_mst_get_pbn_divider(dc_link)) < 0)
 764                         return false;
 765         }
 766         if (!drm_dp_mst_atomic_check(state) && !debugfs_overwrite) {
 767                 set_dsc_configs_from_fairness_vars(params, vars, count);
 768                 return true;
 769         }
 770
 771         /* Try max compression */
 772         for (i = 0; i < count; i++) {
 773                 if (params[i].compression_possible && params[i].clock_force_enable != DSC_CLK_FORCE_DISABLE) {
 774                         vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps);
 775                         vars[i].dsc_enabled = true;
 776                         vars[i].bpp_x16 = params[i].bw_range.min_target_bpp_x16;
 777                         if (drm_dp_atomic_find_vcpi_slots(state,
 778                                                           params[i].port->mgr,
 779                                                           params[i].port,
 780                                                           vars[i].pbn,
 781                                                           dm_mst_get_pbn_divider(dc_link)) < 0)
 782                                 return false;
 783                 } else {
 784                         vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
 785                         vars[i].dsc_enabled = false;
 786                         vars[i].bpp_x16 = 0;
 787                         if (drm_dp_atomic_find_vcpi_slots(state,
 788                                                           params[i].port->mgr,
 789                                                           params[i].port,
 790                                                           vars[i].pbn,
 791                                                           dm_mst_get_pbn_divider(dc_link)) < 0)
 792                                 return false;
 793                 }
 794         }
 795         if (drm_dp_mst_atomic_check(state))
 796                 return false;
 797
 798         /* Optimize degree of compression */
 799         increase_dsc_bpp(state, dc_link, params, vars, count);
 800
 801         try_disable_dsc(state, dc_link, params, vars, count);
 802
 803         set_dsc_configs_from_fairness_vars(params, vars, count);
 804
 805         return true;
 806 }
 807
 808 bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
 809                                        struct dc_state *dc_state)
 810 {
 811         int i, j;
 812         struct dc_stream_state *stream;
 813         bool computed_streams[MAX_PIPES];
 814         struct amdgpu_dm_connector *aconnector;
 815
 816         for (i = 0; i < dc_state->stream_count; i++)
 817                 computed_streams[i] = false;
 818
 819         for (i = 0; i < dc_state->stream_count; i++) {
 820                 stream = dc_state->streams[i];
 821
 822                 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
 823                         continue;
 824
 825                 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 826
 827                 if (!aconnector || !aconnector->dc_sink)
 828                         continue;
 829
 830                 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported)
 831                         continue;
 832
 833                 if (computed_streams[i])
 834                         continue;
 835
 836                 mutex_lock(&aconnector->mst_mgr.lock);
 837                 if (!compute_mst_dsc_configs_for_link(state, dc_state, stream->link)) {
 838                         mutex_unlock(&aconnector->mst_mgr.lock);
 839                         return false;
 840                 }
 841                 mutex_unlock(&aconnector->mst_mgr.lock);
 842
 843                 for (j = 0; j < dc_state->stream_count; j++) {
 844                         if (dc_state->streams[j]->link == stream->link)
 845                                 computed_streams[j] = true;
 846                 }
 847         }
 848
 849         for (i = 0; i < dc_state->stream_count; i++) {
 850                 stream = dc_state->streams[i];
 851
 852                 if (stream->timing.flags.DSC == 1)
 853                         dc_stream_add_dsc_to_resource(stream->ctx->dc, dc_state, stream);
 854         }
 855
 856         return true;
 857 }
 858
 859 #endif