2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <drm/drm_atomic_helper.h>
27 #include <drm/drm_dp_mst_helper.h>
28 #include <drm/drm_dp_helper.h>
29 #include "dm_services.h"
31 #include "amdgpu_dm.h"
32 #include "amdgpu_dm_mst_types.h"
35 #include "dm_helpers.h"
37 #include "dc_link_ddc.h"
39 #include "i2caux_interface.h"
40 #if defined(CONFIG_DEBUG_FS)
41 #include "amdgpu_dm_debugfs.h"
44 #if defined(CONFIG_DRM_AMD_DC_DCN)
45 #include "dc/dcn20/dcn20_resource.h"
48 static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
49 struct drm_dp_aux_msg *msg)
52 struct aux_payload payload;
53 enum aux_channel_operation_result operation_result;
55 if (WARN_ON(msg->size > 16))
58 payload.address = msg->address;
59 payload.data = msg->buffer;
60 payload.length = msg->size;
61 payload.reply = &msg->reply;
62 payload.i2c_over_aux = (msg->request & DP_AUX_NATIVE_WRITE) == 0;
63 payload.write = (msg->request & DP_AUX_I2C_READ) == 0;
64 payload.mot = (msg->request & DP_AUX_I2C_MOT) != 0;
65 payload.defer_delay = 0;
67 result = dc_link_aux_transfer_raw(TO_DM_AUX(aux)->ddc_service, &payload,
70 if (payload.write && result >= 0)
74 switch (operation_result) {
75 case AUX_CHANNEL_OPERATION_SUCCEEDED:
77 case AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON:
78 case AUX_CHANNEL_OPERATION_FAILED_REASON_UNKNOWN:
81 case AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY:
82 case AUX_CHANNEL_OPERATION_FAILED_ENGINE_ACQUIRE:
85 case AUX_CHANNEL_OPERATION_FAILED_TIMEOUT:
94 dm_dp_mst_connector_destroy(struct drm_connector *connector)
96 struct amdgpu_dm_connector *aconnector =
97 to_amdgpu_dm_connector(connector);
99 if (aconnector->dc_sink) {
100 dc_link_remove_remote_sink(aconnector->dc_link,
101 aconnector->dc_sink);
102 dc_sink_release(aconnector->dc_sink);
105 kfree(aconnector->edid);
107 drm_connector_cleanup(connector);
108 drm_dp_mst_put_port_malloc(aconnector->port);
113 amdgpu_dm_mst_connector_late_register(struct drm_connector *connector)
115 struct amdgpu_dm_connector *amdgpu_dm_connector =
116 to_amdgpu_dm_connector(connector);
119 r = drm_dp_mst_connector_late_register(connector,
120 amdgpu_dm_connector->port);
124 #if defined(CONFIG_DEBUG_FS)
125 connector_debugfs_init(amdgpu_dm_connector);
132 amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector)
134 struct amdgpu_dm_connector *amdgpu_dm_connector =
135 to_amdgpu_dm_connector(connector);
136 struct drm_dp_mst_port *port = amdgpu_dm_connector->port;
138 drm_dp_mst_connector_early_unregister(connector, port);
141 static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
142 .fill_modes = drm_helper_probe_single_connector_modes,
143 .destroy = dm_dp_mst_connector_destroy,
144 .reset = amdgpu_dm_connector_funcs_reset,
145 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
146 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
147 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
148 .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
149 .late_register = amdgpu_dm_mst_connector_late_register,
150 .early_unregister = amdgpu_dm_mst_connector_early_unregister,
153 #if defined(CONFIG_DRM_AMD_DC_DCN)
154 static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector)
156 struct dc_sink *dc_sink = aconnector->dc_sink;
157 struct drm_dp_mst_port *port = aconnector->port;
158 u8 dsc_caps[16] = { 0 };
160 aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port);
161 #if defined(CONFIG_HP_HOOK_WORKAROUND)
163 * drm_dp_mst_dsc_aux_for_port() will return NULL for certain configs
164 * because it only check the dsc/fec caps of the "port variable" and not the dock
166 * This case will return NULL: DSC capabe MST dock connected to a non fec/dsc capable display
168 * Workaround: explicitly check the use case above and use the mst dock's aux as dsc_aux
172 if (!aconnector->dsc_aux && !port->parent->port_parent)
173 aconnector->dsc_aux = &aconnector->mst_port->dm_dp_aux.aux;
175 if (!aconnector->dsc_aux)
178 if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DSC_SUPPORT, dsc_caps, 16) < 0)
181 if (!dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
183 &dc_sink->dsc_caps.dsc_dec_caps))
190 static int dm_dp_mst_get_modes(struct drm_connector *connector)
192 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
196 return drm_add_edid_modes(connector, NULL);
198 if (!aconnector->edid) {
200 edid = drm_dp_mst_get_edid(connector, &aconnector->mst_port->mst_mgr, aconnector->port);
203 drm_connector_update_edid_property(
209 aconnector->edid = edid;
212 if (aconnector->dc_sink && aconnector->dc_sink->sink_signal == SIGNAL_TYPE_VIRTUAL) {
213 dc_sink_release(aconnector->dc_sink);
214 aconnector->dc_sink = NULL;
217 if (!aconnector->dc_sink) {
218 struct dc_sink *dc_sink;
219 struct dc_sink_init_data init_params = {
220 .link = aconnector->dc_link,
221 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
222 dc_sink = dc_link_add_remote_sink(
224 (uint8_t *)aconnector->edid,
225 (aconnector->edid->extensions + 1) * EDID_LENGTH,
228 dc_sink->priv = aconnector;
229 /* dc_link_add_remote_sink returns a new reference */
230 aconnector->dc_sink = dc_sink;
232 if (aconnector->dc_sink) {
233 amdgpu_dm_update_freesync_caps(
234 connector, aconnector->edid);
236 #if defined(CONFIG_DRM_AMD_DC_DCN)
237 if (!validate_dsc_caps_on_connector(aconnector))
238 memset(&aconnector->dc_sink->dsc_caps,
239 0, sizeof(aconnector->dc_sink->dsc_caps));
244 drm_connector_update_edid_property(
245 &aconnector->base, aconnector->edid);
247 ret = drm_add_edid_modes(connector, aconnector->edid);
252 static struct drm_encoder *
253 dm_mst_atomic_best_encoder(struct drm_connector *connector,
254 struct drm_connector_state *connector_state)
256 struct drm_device *dev = connector->dev;
257 struct amdgpu_device *adev = drm_to_adev(dev);
258 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(connector_state->crtc);
260 return &adev->dm.mst_encoders[acrtc->crtc_id].base;
264 dm_dp_mst_detect(struct drm_connector *connector,
265 struct drm_modeset_acquire_ctx *ctx, bool force)
267 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
268 struct amdgpu_dm_connector *master = aconnector->mst_port;
270 return drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr,
274 static int dm_dp_mst_atomic_check(struct drm_connector *connector,
275 struct drm_atomic_state *state)
277 struct drm_connector_state *new_conn_state =
278 drm_atomic_get_new_connector_state(state, connector);
279 struct drm_connector_state *old_conn_state =
280 drm_atomic_get_old_connector_state(state, connector);
281 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
282 struct drm_crtc_state *new_crtc_state;
283 struct drm_dp_mst_topology_mgr *mst_mgr;
284 struct drm_dp_mst_port *mst_port;
286 mst_port = aconnector->port;
287 mst_mgr = &aconnector->mst_port->mst_mgr;
289 if (!old_conn_state->crtc)
292 if (new_conn_state->crtc) {
293 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
294 if (!new_crtc_state ||
295 !drm_atomic_crtc_needs_modeset(new_crtc_state) ||
296 new_crtc_state->enable)
300 return drm_dp_atomic_release_vcpi_slots(state,
305 static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = {
306 .get_modes = dm_dp_mst_get_modes,
307 .mode_valid = amdgpu_dm_connector_mode_valid,
308 .atomic_best_encoder = dm_mst_atomic_best_encoder,
309 .detect_ctx = dm_dp_mst_detect,
310 .atomic_check = dm_dp_mst_atomic_check,
313 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
315 drm_encoder_cleanup(encoder);
319 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
320 .destroy = amdgpu_dm_encoder_destroy,
324 dm_dp_create_fake_mst_encoders(struct amdgpu_device *adev)
326 struct drm_device *dev = adev_to_drm(adev);
329 for (i = 0; i < adev->dm.display_indexes_num; i++) {
330 struct amdgpu_encoder *amdgpu_encoder = &adev->dm.mst_encoders[i];
331 struct drm_encoder *encoder = &amdgpu_encoder->base;
333 encoder->possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
337 &amdgpu_encoder->base,
338 &amdgpu_dm_encoder_funcs,
339 DRM_MODE_ENCODER_DPMST,
342 drm_encoder_helper_add(encoder, &amdgpu_dm_encoder_helper_funcs);
346 static struct drm_connector *
347 dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
348 struct drm_dp_mst_port *port,
349 const char *pathprop)
351 struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr);
352 struct drm_device *dev = master->base.dev;
353 struct amdgpu_device *adev = drm_to_adev(dev);
354 struct amdgpu_dm_connector *aconnector;
355 struct drm_connector *connector;
358 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
362 connector = &aconnector->base;
363 aconnector->port = port;
364 aconnector->mst_port = master;
366 if (drm_connector_init(
369 &dm_dp_mst_connector_funcs,
370 DRM_MODE_CONNECTOR_DisplayPort)) {
374 drm_connector_helper_add(connector, &dm_dp_mst_connector_helper_funcs);
376 amdgpu_dm_connector_init_helper(
379 DRM_MODE_CONNECTOR_DisplayPort,
381 master->connector_id);
383 for (i = 0; i < adev->dm.display_indexes_num; i++) {
384 drm_connector_attach_encoder(&aconnector->base,
385 &adev->dm.mst_encoders[i].base);
388 connector->max_bpc_property = master->base.max_bpc_property;
389 if (connector->max_bpc_property)
390 drm_connector_attach_max_bpc_property(connector, 8, 16);
392 connector->vrr_capable_property = master->base.vrr_capable_property;
393 if (connector->vrr_capable_property)
394 drm_connector_attach_vrr_capable_property(connector);
396 drm_object_attach_property(
398 dev->mode_config.path_property,
400 drm_object_attach_property(
402 dev->mode_config.tile_property,
405 drm_connector_set_path_property(connector, pathprop);
408 * Initialize connector state before adding the connectror to drm and
411 amdgpu_dm_connector_funcs_reset(connector);
413 drm_dp_mst_get_port_malloc(port);
418 static const struct drm_dp_mst_topology_cbs dm_mst_cbs = {
419 .add_connector = dm_dp_add_mst_connector,
422 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
423 struct amdgpu_dm_connector *aconnector,
426 aconnector->dm_dp_aux.aux.name =
427 kasprintf(GFP_KERNEL, "AMDGPU DM aux hw bus %d",
429 aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer;
430 aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc;
432 drm_dp_aux_init(&aconnector->dm_dp_aux.aux);
433 drm_dp_cec_register_connector(&aconnector->dm_dp_aux.aux,
436 if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
439 aconnector->mst_mgr.cbs = &dm_mst_cbs;
440 drm_dp_mst_topology_mgr_init(
441 &aconnector->mst_mgr,
442 adev_to_drm(dm->adev),
443 &aconnector->dm_dp_aux.aux,
446 aconnector->connector_id);
448 drm_connector_attach_dp_subconnector_property(&aconnector->base);
451 int dm_mst_get_pbn_divider(struct dc_link *link)
456 return dc_link_bandwidth_kbps(link,
457 dc_link_get_link_cap(link)) / (8 * 1000 * 54);
460 #if defined(CONFIG_DRM_AMD_DC_DCN)
462 struct dsc_mst_fairness_params {
463 struct dc_crtc_timing *timing;
464 struct dc_sink *sink;
465 struct dc_dsc_bw_range bw_range;
466 bool compression_possible;
467 struct drm_dp_mst_port *port;
468 enum dsc_clock_force_state clock_force_enable;
469 uint32_t num_slices_h;
470 uint32_t num_slices_v;
471 uint32_t bpp_overwrite;
474 struct dsc_mst_fairness_vars {
480 static int kbps_to_peak_pbn(int kbps)
482 u64 peak_kbps = kbps;
485 peak_kbps = div_u64(peak_kbps, 1000);
486 return (int) DIV64_U64_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000));
489 static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params,
490 struct dsc_mst_fairness_vars *vars,
495 for (i = 0; i < count; i++) {
496 memset(¶ms[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg));
497 if (vars[i].dsc_enabled && dc_dsc_compute_config(
498 params[i].sink->ctx->dc->res_pool->dscs[0],
499 ¶ms[i].sink->dsc_caps.dsc_dec_caps,
500 params[i].sink->ctx->dc->debug.dsc_min_slice_height_override,
504 ¶ms[i].timing->dsc_cfg)) {
505 params[i].timing->flags.DSC = 1;
507 if (params[i].bpp_overwrite)
508 params[i].timing->dsc_cfg.bits_per_pixel = params[i].bpp_overwrite;
510 params[i].timing->dsc_cfg.bits_per_pixel = vars[i].bpp_x16;
512 if (params[i].num_slices_h)
513 params[i].timing->dsc_cfg.num_slices_h = params[i].num_slices_h;
515 if (params[i].num_slices_v)
516 params[i].timing->dsc_cfg.num_slices_v = params[i].num_slices_v;
518 params[i].timing->flags.DSC = 0;
523 static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn)
525 struct dc_dsc_config dsc_config;
528 kbps = div_u64((u64)pbn * 994 * 8 * 54, 64);
529 dc_dsc_compute_config(
530 param.sink->ctx->dc->res_pool->dscs[0],
531 ¶m.sink->dsc_caps.dsc_dec_caps,
532 param.sink->ctx->dc->debug.dsc_min_slice_height_override,
534 (int) kbps, param.timing, &dsc_config);
536 return dsc_config.bits_per_pixel;
539 static void increase_dsc_bpp(struct drm_atomic_state *state,
540 struct dc_link *dc_link,
541 struct dsc_mst_fairness_params *params,
542 struct dsc_mst_fairness_vars *vars,
546 bool bpp_increased[MAX_PIPES];
547 int initial_slack[MAX_PIPES];
548 int min_initial_slack;
550 int remaining_to_increase = 0;
551 int pbn_per_timeslot;
552 int link_timeslots_used;
555 pbn_per_timeslot = dm_mst_get_pbn_divider(dc_link);
557 for (i = 0; i < count; i++) {
558 if (vars[i].dsc_enabled) {
559 initial_slack[i] = kbps_to_peak_pbn(params[i].bw_range.max_kbps) - vars[i].pbn;
560 bpp_increased[i] = false;
561 remaining_to_increase += 1;
563 initial_slack[i] = 0;
564 bpp_increased[i] = true;
568 while (remaining_to_increase) {
570 min_initial_slack = -1;
571 for (i = 0; i < count; i++) {
572 if (!bpp_increased[i]) {
573 if (min_initial_slack == -1 || min_initial_slack > initial_slack[i]) {
574 min_initial_slack = initial_slack[i];
580 if (next_index == -1)
583 link_timeslots_used = 0;
585 for (i = 0; i < count; i++)
586 link_timeslots_used += DIV_ROUND_UP(vars[i].pbn, pbn_per_timeslot);
588 fair_pbn_alloc = (63 - link_timeslots_used) / remaining_to_increase * pbn_per_timeslot;
590 if (initial_slack[next_index] > fair_pbn_alloc) {
591 vars[next_index].pbn += fair_pbn_alloc;
592 if (drm_dp_atomic_find_vcpi_slots(state,
593 params[next_index].port->mgr,
594 params[next_index].port,
595 vars[next_index].pbn,
596 pbn_per_timeslot) < 0)
598 if (!drm_dp_mst_atomic_check(state)) {
599 vars[next_index].bpp_x16 = bpp_x16_from_pbn(params[next_index], vars[next_index].pbn);
601 vars[next_index].pbn -= fair_pbn_alloc;
602 if (drm_dp_atomic_find_vcpi_slots(state,
603 params[next_index].port->mgr,
604 params[next_index].port,
605 vars[next_index].pbn,
606 pbn_per_timeslot) < 0)
610 vars[next_index].pbn += initial_slack[next_index];
611 if (drm_dp_atomic_find_vcpi_slots(state,
612 params[next_index].port->mgr,
613 params[next_index].port,
614 vars[next_index].pbn,
615 pbn_per_timeslot) < 0)
617 if (!drm_dp_mst_atomic_check(state)) {
618 vars[next_index].bpp_x16 = params[next_index].bw_range.max_target_bpp_x16;
620 vars[next_index].pbn -= initial_slack[next_index];
621 if (drm_dp_atomic_find_vcpi_slots(state,
622 params[next_index].port->mgr,
623 params[next_index].port,
624 vars[next_index].pbn,
625 pbn_per_timeslot) < 0)
630 bpp_increased[next_index] = true;
631 remaining_to_increase--;
635 static void try_disable_dsc(struct drm_atomic_state *state,
636 struct dc_link *dc_link,
637 struct dsc_mst_fairness_params *params,
638 struct dsc_mst_fairness_vars *vars,
642 bool tried[MAX_PIPES];
643 int kbps_increase[MAX_PIPES];
644 int max_kbps_increase;
646 int remaining_to_try = 0;
648 for (i = 0; i < count; i++) {
649 if (vars[i].dsc_enabled
650 && vars[i].bpp_x16 == params[i].bw_range.max_target_bpp_x16
651 && params[i].clock_force_enable == DSC_CLK_FORCE_DEFAULT) {
652 kbps_increase[i] = params[i].bw_range.stream_kbps - params[i].bw_range.max_kbps;
654 remaining_to_try += 1;
656 kbps_increase[i] = 0;
661 while (remaining_to_try) {
663 max_kbps_increase = -1;
664 for (i = 0; i < count; i++) {
666 if (max_kbps_increase == -1 || max_kbps_increase < kbps_increase[i]) {
667 max_kbps_increase = kbps_increase[i];
673 if (next_index == -1)
676 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps);
677 if (drm_dp_atomic_find_vcpi_slots(state,
678 params[next_index].port->mgr,
679 params[next_index].port,
680 vars[next_index].pbn,
681 dm_mst_get_pbn_divider(dc_link)) < 0)
684 if (!drm_dp_mst_atomic_check(state)) {
685 vars[next_index].dsc_enabled = false;
686 vars[next_index].bpp_x16 = 0;
688 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.max_kbps);
689 if (drm_dp_atomic_find_vcpi_slots(state,
690 params[next_index].port->mgr,
691 params[next_index].port,
692 vars[next_index].pbn,
693 dm_mst_get_pbn_divider(dc_link)) < 0)
697 tried[next_index] = true;
702 static bool compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
703 struct dc_state *dc_state,
704 struct dc_link *dc_link)
707 struct dc_stream_state *stream;
708 struct dsc_mst_fairness_params params[MAX_PIPES];
709 struct dsc_mst_fairness_vars vars[MAX_PIPES];
710 struct amdgpu_dm_connector *aconnector;
712 bool debugfs_overwrite = false;
714 memset(params, 0, sizeof(params));
717 for (i = 0; i < dc_state->stream_count; i++) {
718 struct dc_dsc_policy dsc_policy = {0};
720 stream = dc_state->streams[i];
722 if (stream->link != dc_link)
725 stream->timing.flags.DSC = 0;
727 params[count].timing = &stream->timing;
728 params[count].sink = stream->sink;
729 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
730 params[count].port = aconnector->port;
731 params[count].clock_force_enable = aconnector->dsc_settings.dsc_force_enable;
732 if (params[count].clock_force_enable == DSC_CLK_FORCE_ENABLE)
733 debugfs_overwrite = true;
734 params[count].num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
735 params[count].num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
736 params[count].bpp_overwrite = aconnector->dsc_settings.dsc_bits_per_pixel;
737 params[count].compression_possible = stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported;
738 dc_dsc_get_policy_for_timing(params[count].timing, 0, &dsc_policy);
739 if (!dc_dsc_compute_bandwidth_range(
740 stream->sink->ctx->dc->res_pool->dscs[0],
741 stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
742 dsc_policy.min_target_bpp,
743 dsc_policy.max_target_bpp,
744 &stream->sink->dsc_caps.dsc_dec_caps,
745 &stream->timing, ¶ms[count].bw_range))
746 params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
750 /* Try no compression */
751 for (i = 0; i < count; i++) {
752 vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
753 vars[i].dsc_enabled = false;
755 if (drm_dp_atomic_find_vcpi_slots(state,
759 dm_mst_get_pbn_divider(dc_link)) < 0)
762 if (!drm_dp_mst_atomic_check(state) && !debugfs_overwrite) {
763 set_dsc_configs_from_fairness_vars(params, vars, count);
767 /* Try max compression */
768 for (i = 0; i < count; i++) {
769 if (params[i].compression_possible && params[i].clock_force_enable != DSC_CLK_FORCE_DISABLE) {
770 vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps);
771 vars[i].dsc_enabled = true;
772 vars[i].bpp_x16 = params[i].bw_range.min_target_bpp_x16;
773 if (drm_dp_atomic_find_vcpi_slots(state,
777 dm_mst_get_pbn_divider(dc_link)) < 0)
780 vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
781 vars[i].dsc_enabled = false;
783 if (drm_dp_atomic_find_vcpi_slots(state,
787 dm_mst_get_pbn_divider(dc_link)) < 0)
791 if (drm_dp_mst_atomic_check(state))
794 /* Optimize degree of compression */
795 increase_dsc_bpp(state, dc_link, params, vars, count);
797 try_disable_dsc(state, dc_link, params, vars, count);
799 set_dsc_configs_from_fairness_vars(params, vars, count);
804 bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
805 struct dc_state *dc_state)
808 struct dc_stream_state *stream;
809 bool computed_streams[MAX_PIPES];
810 struct amdgpu_dm_connector *aconnector;
812 for (i = 0; i < dc_state->stream_count; i++)
813 computed_streams[i] = false;
815 for (i = 0; i < dc_state->stream_count; i++) {
816 stream = dc_state->streams[i];
818 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
821 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
823 if (!aconnector || !aconnector->dc_sink)
826 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported)
829 if (computed_streams[i])
832 mutex_lock(&aconnector->mst_mgr.lock);
833 if (!compute_mst_dsc_configs_for_link(state, dc_state, stream->link)) {
834 mutex_unlock(&aconnector->mst_mgr.lock);
837 mutex_unlock(&aconnector->mst_mgr.lock);
839 for (j = 0; j < dc_state->stream_count; j++) {
840 if (dc_state->streams[j]->link == stream->link)
841 computed_streams[j] = true;
845 for (i = 0; i < dc_state->stream_count; i++) {
846 stream = dc_state->streams[i];
848 if (stream->timing.flags.DSC == 1)
849 dc_stream_add_dsc_to_resource(stream->ctx->dc, dc_state, stream);