drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/string.h>
  27 #include <linux/acpi.h>
  28 #include <linux/i2c.h>
  29
  30 #include <drm/drm_atomic.h>
  31 #include <drm/drm_probe_helper.h>
  32 #include <drm/amdgpu_drm.h>
  33 #include <drm/drm_edid.h>
  34
  35 #include "dm_services.h"
  36 #include "amdgpu.h"
  37 #include "dc.h"
  38 #include "amdgpu_dm.h"
  39 #include "amdgpu_dm_irq.h"
  40 #include "amdgpu_dm_mst_types.h"
  41 #include "dpcd_defs.h"
  42 #include "dc/inc/core_types.h"
  43
  44 #include "dm_helpers.h"
  45 #include "ddc_service_types.h"
  46
  47 static u32 edid_extract_panel_id(struct edid *edid)
  48 {
  49         return (u32)edid->mfg_id[0] << 24   |
  50                (u32)edid->mfg_id[1] << 16   |
  51                (u32)EDID_PRODUCT_ID(edid);
  52 }
  53
  54 static void apply_edid_quirks(struct edid *edid, struct dc_edid_caps *edid_caps)
  55 {
  56         uint32_t panel_id = edid_extract_panel_id(edid);
  57
  58         switch (panel_id) {
  59         /* Workaround for some monitors which does not work well with FAMS */
  60         case drm_edid_encode_panel_id('S', 'A', 'M', 0x0E5E):
  61         case drm_edid_encode_panel_id('S', 'A', 'M', 0x7053):
  62         case drm_edid_encode_panel_id('S', 'A', 'M', 0x71AC):
  63                 DRM_DEBUG_DRIVER("Disabling FAMS on monitor with panel id %X\n", panel_id);
  64                 edid_caps->panel_patch.disable_fams = true;
  65                 break;
  66         /* Workaround for some monitors that do not clear DPCD 0x317 if FreeSync is unsupported */
  67         case drm_edid_encode_panel_id('A', 'U', 'O', 0xA7AB):
  68         case drm_edid_encode_panel_id('A', 'U', 'O', 0xE69B):
  69                 DRM_DEBUG_DRIVER("Clearing DPCD 0x317 on monitor with panel id %X\n", panel_id);
  70                 edid_caps->panel_patch.remove_sink_ext_caps = true;
  71                 break;
  72         default:
  73                 return;
  74         }
  75 }
  76
  77 /**
  78  * dm_helpers_parse_edid_caps() - Parse edid caps
  79  *
  80  * @link: current detected link
  81  * @edid:       [in] pointer to edid
  82  * @edid_caps:  [in] pointer to edid caps
  83  *
  84  * Return: void
  85  */
  86 enum dc_edid_status dm_helpers_parse_edid_caps(
  87                 struct dc_link *link,
  88                 const struct dc_edid *edid,
  89                 struct dc_edid_caps *edid_caps)
  90 {
  91         struct amdgpu_dm_connector *aconnector = link->priv;
  92         struct drm_connector *connector = &aconnector->base;
  93         struct edid *edid_buf = edid ? (struct edid *) edid->raw_edid : NULL;
  94         struct cea_sad *sads;
  95         int sad_count = -1;
  96         int sadb_count = -1;
  97         int i = 0;
  98         uint8_t *sadb = NULL;
  99
 100         enum dc_edid_status result = EDID_OK;
 101
 102         if (!edid_caps || !edid)
 103                 return EDID_BAD_INPUT;
 104
 105         if (!drm_edid_is_valid(edid_buf))
 106                 result = EDID_BAD_CHECKSUM;
 107
 108         edid_caps->manufacturer_id = (uint16_t) edid_buf->mfg_id[0] |
 109                                         ((uint16_t) edid_buf->mfg_id[1])<<8;
 110         edid_caps->product_id = (uint16_t) edid_buf->prod_code[0] |
 111                                         ((uint16_t) edid_buf->prod_code[1])<<8;
 112         edid_caps->serial_number = edid_buf->serial;
 113         edid_caps->manufacture_week = edid_buf->mfg_week;
 114         edid_caps->manufacture_year = edid_buf->mfg_year;
 115
 116         drm_edid_get_monitor_name(edid_buf,
 117                                   edid_caps->display_name,
 118                                   AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
 119
 120         edid_caps->edid_hdmi = connector->display_info.is_hdmi;
 121
 122         sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads);
 123         if (sad_count <= 0)
 124                 return result;
 125
 126         edid_caps->audio_mode_count = min(sad_count, DC_MAX_AUDIO_DESC_COUNT);
 127         for (i = 0; i < edid_caps->audio_mode_count; ++i) {
 128                 struct cea_sad *sad = &sads[i];
 129
 130                 edid_caps->audio_modes[i].format_code = sad->format;
 131                 edid_caps->audio_modes[i].channel_count = sad->channels + 1;
 132                 edid_caps->audio_modes[i].sample_rate = sad->freq;
 133                 edid_caps->audio_modes[i].sample_size = sad->byte2;
 134         }
 135
 136         sadb_count = drm_edid_to_speaker_allocation((struct edid *) edid->raw_edid, &sadb);
 137
 138         if (sadb_count < 0) {
 139                 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sadb_count);
 140                 sadb_count = 0;
 141         }
 142
 143         if (sadb_count)
 144                 edid_caps->speaker_flags = sadb[0];
 145         else
 146                 edid_caps->speaker_flags = DEFAULT_SPEAKER_LOCATION;
 147
 148         apply_edid_quirks(edid_buf, edid_caps);
 149
 150         kfree(sads);
 151         kfree(sadb);
 152
 153         return result;
 154 }
 155
 156 static void
 157 fill_dc_mst_payload_table_from_drm(struct dc_link *link,
 158                                    bool enable,
 159                                    struct drm_dp_mst_atomic_payload *target_payload,
 160                                    struct dc_dp_mst_stream_allocation_table *table)
 161 {
 162         struct dc_dp_mst_stream_allocation_table new_table = { 0 };
 163         struct dc_dp_mst_stream_allocation *sa;
 164         struct link_mst_stream_allocation_table copy_of_link_table =
 165                                                                                 link->mst_stream_alloc_table;
 166
 167         int i;
 168         int current_hw_table_stream_cnt = copy_of_link_table.stream_count;
 169         struct link_mst_stream_allocation *dc_alloc;
 170
 171         /* TODO: refactor to set link->mst_stream_alloc_table directly if possible.*/
 172         if (enable) {
 173                 dc_alloc =
 174                 &copy_of_link_table.stream_allocations[current_hw_table_stream_cnt];
 175                 dc_alloc->vcp_id = target_payload->vcpi;
 176                 dc_alloc->slot_count = target_payload->time_slots;
 177         } else {
 178                 for (i = 0; i < copy_of_link_table.stream_count; i++) {
 179                         dc_alloc =
 180                         &copy_of_link_table.stream_allocations[i];
 181
 182                         if (dc_alloc->vcp_id == target_payload->vcpi) {
 183                                 dc_alloc->vcp_id = 0;
 184                                 dc_alloc->slot_count = 0;
 185                                 break;
 186                         }
 187                 }
 188                 ASSERT(i != copy_of_link_table.stream_count);
 189         }
 190
 191         /* Fill payload info*/
 192         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
 193                 dc_alloc =
 194                         &copy_of_link_table.stream_allocations[i];
 195                 if (dc_alloc->vcp_id > 0 && dc_alloc->slot_count > 0) {
 196                         sa = &new_table.stream_allocations[new_table.stream_count];
 197                         sa->slot_count = dc_alloc->slot_count;
 198                         sa->vcp_id = dc_alloc->vcp_id;
 199                         new_table.stream_count++;
 200                 }
 201         }
 202
 203         /* Overwrite the old table */
 204         *table = new_table;
 205 }
 206
 207 void dm_helpers_dp_update_branch_info(
 208         struct dc_context *ctx,
 209         const struct dc_link *link)
 210 {}
 211
 212 static void dm_helpers_construct_old_payload(
 213                         struct dc_link *link,
 214                         int pbn_per_slot,
 215                         struct drm_dp_mst_atomic_payload *new_payload,
 216                         struct drm_dp_mst_atomic_payload *old_payload)
 217 {
 218         struct link_mst_stream_allocation_table current_link_table =
 219                                                                         link->mst_stream_alloc_table;
 220         struct link_mst_stream_allocation *dc_alloc;
 221         int i;
 222
 223         *old_payload = *new_payload;
 224
 225         /* Set correct time_slots/PBN of old payload.
 226          * other fields (delete & dsc_enabled) in
 227          * struct drm_dp_mst_atomic_payload are don't care fields
 228          * while calling drm_dp_remove_payload()
 229          */
 230         for (i = 0; i < current_link_table.stream_count; i++) {
 231                 dc_alloc =
 232                         &current_link_table.stream_allocations[i];
 233
 234                 if (dc_alloc->vcp_id == new_payload->vcpi) {
 235                         old_payload->time_slots = dc_alloc->slot_count;
 236                         old_payload->pbn = dc_alloc->slot_count * pbn_per_slot;
 237                         break;
 238                 }
 239         }
 240
 241         /* make sure there is an old payload*/
 242         ASSERT(i != current_link_table.stream_count);
 243
 244 }
 245
 246 /*
 247  * Writes payload allocation table in immediate downstream device.
 248  */
 249 bool dm_helpers_dp_mst_write_payload_allocation_table(
 250                 struct dc_context *ctx,
 251                 const struct dc_stream_state *stream,
 252                 struct dc_dp_mst_stream_allocation_table *proposed_table,
 253                 bool enable)
 254 {
 255         struct amdgpu_dm_connector *aconnector;
 256         struct drm_dp_mst_topology_state *mst_state;
 257         struct drm_dp_mst_atomic_payload *target_payload, *new_payload, old_payload;
 258         struct drm_dp_mst_topology_mgr *mst_mgr;
 259
 260         aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 261         /* Accessing the connector state is required for vcpi_slots allocation
 262          * and directly relies on behaviour in commit check
 263          * that blocks before commit guaranteeing that the state
 264          * is not gonna be swapped while still in use in commit tail
 265          */
 266
 267         if (!aconnector || !aconnector->mst_root)
 268                 return false;
 269
 270         mst_mgr = &aconnector->mst_root->mst_mgr;
 271         mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state);
 272
 273         /* It's OK for this to fail */
 274         new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port);
 275
 276         if (enable) {
 277                 target_payload = new_payload;
 278
 279                 drm_dp_add_payload_part1(mst_mgr, mst_state, new_payload);
 280         } else {
 281                 /* construct old payload by VCPI*/
 282                 dm_helpers_construct_old_payload(stream->link, mst_state->pbn_div,
 283                                                 new_payload, &old_payload);
 284                 target_payload = &old_payload;
 285
 286                 drm_dp_remove_payload(mst_mgr, mst_state, &old_payload, new_payload);
 287         }
 288
 289         /* mst_mgr->->payloads are VC payload notify MST branch using DPCD or
 290          * AUX message. The sequence is slot 1-63 allocated sequence for each
 291          * stream. AMD ASIC stream slot allocation should follow the same
 292          * sequence. copy DRM MST allocation to dc
 293          */
 294         fill_dc_mst_payload_table_from_drm(stream->link, enable, target_payload, proposed_table);
 295
 296         return true;
 297 }
 298
 299 /*
 300  * poll pending down reply
 301  */
 302 void dm_helpers_dp_mst_poll_pending_down_reply(
 303         struct dc_context *ctx,
 304         const struct dc_link *link)
 305 {}
 306
 307 /*
 308  * Clear payload allocation table before enable MST DP link.
 309  */
 310 void dm_helpers_dp_mst_clear_payload_allocation_table(
 311         struct dc_context *ctx,
 312         const struct dc_link *link)
 313 {}
 314
 315 /*
 316  * Polls for ACT (allocation change trigger) handled and sends
 317  * ALLOCATE_PAYLOAD message.
 318  */
 319 enum act_return_status dm_helpers_dp_mst_poll_for_allocation_change_trigger(
 320                 struct dc_context *ctx,
 321                 const struct dc_stream_state *stream)
 322 {
 323         struct amdgpu_dm_connector *aconnector;
 324         struct drm_dp_mst_topology_mgr *mst_mgr;
 325         int ret;
 326
 327         aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 328
 329         if (!aconnector || !aconnector->mst_root)
 330                 return ACT_FAILED;
 331
 332         mst_mgr = &aconnector->mst_root->mst_mgr;
 333
 334         if (!mst_mgr->mst_state)
 335                 return ACT_FAILED;
 336
 337         ret = drm_dp_check_act_status(mst_mgr);
 338
 339         if (ret)
 340                 return ACT_FAILED;
 341
 342         return ACT_SUCCESS;
 343 }
 344
 345 bool dm_helpers_dp_mst_send_payload_allocation(
 346                 struct dc_context *ctx,
 347                 const struct dc_stream_state *stream,
 348                 bool enable)
 349 {
 350         struct amdgpu_dm_connector *aconnector;
 351         struct drm_dp_mst_topology_state *mst_state;
 352         struct drm_dp_mst_topology_mgr *mst_mgr;
 353         struct drm_dp_mst_atomic_payload *payload;
 354         enum mst_progress_status set_flag = MST_ALLOCATE_NEW_PAYLOAD;
 355         enum mst_progress_status clr_flag = MST_CLEAR_ALLOCATED_PAYLOAD;
 356         int ret = 0;
 357
 358         aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 359
 360         if (!aconnector || !aconnector->mst_root)
 361                 return false;
 362
 363         mst_mgr = &aconnector->mst_root->mst_mgr;
 364         mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state);
 365
 366         payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port);
 367
 368         if (!enable) {
 369                 set_flag = MST_CLEAR_ALLOCATED_PAYLOAD;
 370                 clr_flag = MST_ALLOCATE_NEW_PAYLOAD;
 371         }
 372
 373         if (enable)
 374                 ret = drm_dp_add_payload_part2(mst_mgr, mst_state->base.state, payload);
 375
 376         if (ret) {
 377                 amdgpu_dm_set_mst_status(&aconnector->mst_status,
 378                         set_flag, false);
 379         } else {
 380                 amdgpu_dm_set_mst_status(&aconnector->mst_status,
 381                         set_flag, true);
 382                 amdgpu_dm_set_mst_status(&aconnector->mst_status,
 383                         clr_flag, false);
 384         }
 385
 386         return true;
 387 }
 388
 389 void dm_dtn_log_begin(struct dc_context *ctx,
 390         struct dc_log_buffer_ctx *log_ctx)
 391 {
 392         static const char msg[] = "[dtn begin]\n";
 393
 394         if (!log_ctx) {
 395                 pr_info("%s", msg);
 396                 return;
 397         }
 398
 399         dm_dtn_log_append_v(ctx, log_ctx, "%s", msg);
 400 }
 401
 402 __printf(3, 4)
 403 void dm_dtn_log_append_v(struct dc_context *ctx,
 404         struct dc_log_buffer_ctx *log_ctx,
 405         const char *msg, ...)
 406 {
 407         va_list args;
 408         size_t total;
 409         int n;
 410
 411         if (!log_ctx) {
 412                 /* No context, redirect to dmesg. */
 413                 struct va_format vaf;
 414
 415                 vaf.fmt = msg;
 416                 vaf.va = &args;
 417
 418                 va_start(args, msg);
 419                 pr_info("%pV", &vaf);
 420                 va_end(args);
 421
 422                 return;
 423         }
 424
 425         /* Measure the output. */
 426         va_start(args, msg);
 427         n = vsnprintf(NULL, 0, msg, args);
 428         va_end(args);
 429
 430         if (n <= 0)
 431                 return;
 432
 433         /* Reallocate the string buffer as needed. */
 434         total = log_ctx->pos + n + 1;
 435
 436         if (total > log_ctx->size) {
 437                 char *buf = kvcalloc(total, sizeof(char), GFP_KERNEL);
 438
 439                 if (buf) {
 440                         memcpy(buf, log_ctx->buf, log_ctx->pos);
 441                         kfree(log_ctx->buf);
 442
 443                         log_ctx->buf = buf;
 444                         log_ctx->size = total;
 445                 }
 446         }
 447
 448         if (!log_ctx->buf)
 449                 return;
 450
 451         /* Write the formatted string to the log buffer. */
 452         va_start(args, msg);
 453         n = vscnprintf(
 454                 log_ctx->buf + log_ctx->pos,
 455                 log_ctx->size - log_ctx->pos,
 456                 msg,
 457                 args);
 458         va_end(args);
 459
 460         if (n > 0)
 461                 log_ctx->pos += n;
 462 }
 463
 464 void dm_dtn_log_end(struct dc_context *ctx,
 465         struct dc_log_buffer_ctx *log_ctx)
 466 {
 467         static const char msg[] = "[dtn end]\n";
 468
 469         if (!log_ctx) {
 470                 pr_info("%s", msg);
 471                 return;
 472         }
 473
 474         dm_dtn_log_append_v(ctx, log_ctx, "%s", msg);
 475 }
 476
 477 bool dm_helpers_dp_mst_start_top_mgr(
 478                 struct dc_context *ctx,
 479                 const struct dc_link *link,
 480                 bool boot)
 481 {
 482         struct amdgpu_dm_connector *aconnector = link->priv;
 483         int ret;
 484
 485         if (!aconnector) {
 486                 DRM_ERROR("Failed to find connector for link!");
 487                 return false;
 488         }
 489
 490         if (boot) {
 491                 DRM_INFO("DM_MST: Differing MST start on aconnector: %p [id: %d]\n",
 492                                         aconnector, aconnector->base.base.id);
 493                 return true;
 494         }
 495
 496         DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n",
 497                         aconnector, aconnector->base.base.id);
 498
 499         ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
 500         if (ret < 0) {
 501                 DRM_ERROR("DM_MST: Failed to set the device into MST mode!");
 502                 return false;
 503         }
 504
 505         DRM_INFO("DM_MST: DP%x, %d-lane link detected\n", aconnector->mst_mgr.dpcd[0],
 506                 aconnector->mst_mgr.dpcd[2] & DP_MAX_LANE_COUNT_MASK);
 507
 508         return true;
 509 }
 510
 511 bool dm_helpers_dp_mst_stop_top_mgr(
 512                 struct dc_context *ctx,
 513                 struct dc_link *link)
 514 {
 515         struct amdgpu_dm_connector *aconnector = link->priv;
 516
 517         if (!aconnector) {
 518                 DRM_ERROR("Failed to find connector for link!");
 519                 return false;
 520         }
 521
 522         DRM_INFO("DM_MST: stopping TM on aconnector: %p [id: %d]\n",
 523                         aconnector, aconnector->base.base.id);
 524
 525         if (aconnector->mst_mgr.mst_state == true) {
 526                 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false);
 527                 link->cur_link_settings.lane_count = 0;
 528         }
 529
 530         return false;
 531 }
 532
 533 bool dm_helpers_dp_read_dpcd(
 534                 struct dc_context *ctx,
 535                 const struct dc_link *link,
 536                 uint32_t address,
 537                 uint8_t *data,
 538                 uint32_t size)
 539 {
 540
 541         struct amdgpu_dm_connector *aconnector = link->priv;
 542
 543         if (!aconnector) {
 544                 DC_LOG_DC("Failed to find connector for link!\n");
 545                 return false;
 546         }
 547
 548         return drm_dp_dpcd_read(&aconnector->dm_dp_aux.aux, address, data,
 549                                 size) == size;
 550 }
 551
 552 bool dm_helpers_dp_write_dpcd(
 553                 struct dc_context *ctx,
 554                 const struct dc_link *link,
 555                 uint32_t address,
 556                 const uint8_t *data,
 557                 uint32_t size)
 558 {
 559         struct amdgpu_dm_connector *aconnector = link->priv;
 560
 561         if (!aconnector) {
 562                 DRM_ERROR("Failed to find connector for link!");
 563                 return false;
 564         }
 565
 566         return drm_dp_dpcd_write(&aconnector->dm_dp_aux.aux,
 567                         address, (uint8_t *)data, size) > 0;
 568 }
 569
 570 bool dm_helpers_submit_i2c(
 571                 struct dc_context *ctx,
 572                 const struct dc_link *link,
 573                 struct i2c_command *cmd)
 574 {
 575         struct amdgpu_dm_connector *aconnector = link->priv;
 576         struct i2c_msg *msgs;
 577         int i = 0;
 578         int num = cmd->number_of_payloads;
 579         bool result;
 580
 581         if (!aconnector) {
 582                 DRM_ERROR("Failed to find connector for link!");
 583                 return false;
 584         }
 585
 586         msgs = kcalloc(num, sizeof(struct i2c_msg), GFP_KERNEL);
 587
 588         if (!msgs)
 589                 return false;
 590
 591         for (i = 0; i < num; i++) {
 592                 msgs[i].flags = cmd->payloads[i].write ? 0 : I2C_M_RD;
 593                 msgs[i].addr = cmd->payloads[i].address;
 594                 msgs[i].len = cmd->payloads[i].length;
 595                 msgs[i].buf = cmd->payloads[i].data;
 596         }
 597
 598         result = i2c_transfer(&aconnector->i2c->base, msgs, num) == num;
 599
 600         kfree(msgs);
 601
 602         return result;
 603 }
 604
 605 static bool execute_synaptics_rc_command(struct drm_dp_aux *aux,
 606                 bool is_write_cmd,
 607                 unsigned char cmd,
 608                 unsigned int length,
 609                 unsigned int offset,
 610                 unsigned char *data)
 611 {
 612         bool success = false;
 613         unsigned char rc_data[16] = {0};
 614         unsigned char rc_offset[4] = {0};
 615         unsigned char rc_length[2] = {0};
 616         unsigned char rc_cmd = 0;
 617         unsigned char rc_result = 0xFF;
 618         unsigned char i = 0;
 619         int ret;
 620
 621         if (is_write_cmd) {
 622                 // write rc data
 623                 memmove(rc_data, data, length);
 624                 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_DATA, rc_data, sizeof(rc_data));
 625         }
 626
 627         // write rc offset
 628         rc_offset[0] = (unsigned char) offset & 0xFF;
 629         rc_offset[1] = (unsigned char) (offset >> 8) & 0xFF;
 630         rc_offset[2] = (unsigned char) (offset >> 16) & 0xFF;
 631         rc_offset[3] = (unsigned char) (offset >> 24) & 0xFF;
 632         ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_OFFSET, rc_offset, sizeof(rc_offset));
 633
 634         // write rc length
 635         rc_length[0] = (unsigned char) length & 0xFF;
 636         rc_length[1] = (unsigned char) (length >> 8) & 0xFF;
 637         ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_LENGTH, rc_length, sizeof(rc_length));
 638
 639         // write rc cmd
 640         rc_cmd = cmd | 0x80;
 641         ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd));
 642
 643         if (ret < 0) {
 644                 DRM_ERROR("%s: write cmd ..., err = %d\n",  __func__, ret);
 645                 return false;
 646         }
 647
 648         // poll until active is 0
 649         for (i = 0; i < 10; i++) {
 650                 drm_dp_dpcd_read(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd));
 651                 if (rc_cmd == cmd)
 652                         // active is 0
 653                         break;
 654                 msleep(10);
 655         }
 656
 657         // read rc result
 658         drm_dp_dpcd_read(aux, SYNAPTICS_RC_RESULT, &rc_result, sizeof(rc_result));
 659         success = (rc_result == 0);
 660
 661         if (success && !is_write_cmd) {
 662                 // read rc data
 663                 drm_dp_dpcd_read(aux, SYNAPTICS_RC_DATA, data, length);
 664         }
 665
 666         DC_LOG_DC("%s: success = %d\n", __func__, success);
 667
 668         return success;
 669 }
 670
 671 static void apply_synaptics_fifo_reset_wa(struct drm_dp_aux *aux)
 672 {
 673         unsigned char data[16] = {0};
 674
 675         DC_LOG_DC("Start %s\n", __func__);
 676
 677         // Step 2
 678         data[0] = 'P';
 679         data[1] = 'R';
 680         data[2] = 'I';
 681         data[3] = 'U';
 682         data[4] = 'S';
 683
 684         if (!execute_synaptics_rc_command(aux, true, 0x01, 5, 0, data))
 685                 return;
 686
 687         // Step 3 and 4
 688         if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data))
 689                 return;
 690
 691         data[0] &= (~(1 << 1)); // set bit 1 to 0
 692         if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data))
 693                 return;
 694
 695         if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data))
 696                 return;
 697
 698         data[0] &= (~(1 << 1)); // set bit 1 to 0
 699         if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220D98, data))
 700                 return;
 701
 702         if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data))
 703                 return;
 704
 705         data[0] &= (~(1 << 1)); // set bit 1 to 0
 706         if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data))
 707                 return;
 708
 709         // Step 3 and 5
 710         if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data))
 711                 return;
 712
 713         data[0] |= (1 << 1); // set bit 1 to 1
 714         if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data))
 715                 return;
 716
 717         if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data))
 718                 return;
 719
 720         data[0] |= (1 << 1); // set bit 1 to 1
 721
 722         if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data))
 723                 return;
 724
 725         data[0] |= (1 << 1); // set bit 1 to 1
 726         if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data))
 727                 return;
 728
 729         // Step 6
 730         if (!execute_synaptics_rc_command(aux, true, 0x02, 0, 0, NULL))
 731                 return;
 732
 733         DC_LOG_DC("Done %s\n", __func__);
 734 }
 735
 736 /* MST Dock */
 737 static const uint8_t SYNAPTICS_DEVICE_ID[] = "SYNA";
 738
 739 static uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst(
 740                 struct drm_dp_aux *aux,
 741                 const struct dc_stream_state *stream,
 742                 bool enable)
 743 {
 744         uint8_t ret = 0;
 745
 746         DC_LOG_DC("Configure DSC to non-virtual dpcd synaptics\n");
 747
 748         if (enable) {
 749                 /* When DSC is enabled on previous boot and reboot with the hub,
 750                  * there is a chance that Synaptics hub gets stuck during reboot sequence.
 751                  * Applying a workaround to reset Synaptics SDP fifo before enabling the first stream
 752                  */
 753                 if (!stream->link->link_status.link_active &&
 754                         memcmp(stream->link->dpcd_caps.branch_dev_name,
 755                                 (int8_t *)SYNAPTICS_DEVICE_ID, 4) == 0)
 756                         apply_synaptics_fifo_reset_wa(aux);
 757
 758                 ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1);
 759                 DRM_INFO("Send DSC enable to synaptics\n");
 760
 761         } else {
 762                 /* Synaptics hub not support virtual dpcd,
 763                  * external monitor occur garbage while disable DSC,
 764                  * Disable DSC only when entire link status turn to false,
 765                  */
 766                 if (!stream->link->link_status.link_active) {
 767                         ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1);
 768                         DRM_INFO("Send DSC disable to synaptics\n");
 769                 }
 770         }
 771
 772         return ret;
 773 }
 774
 775 bool dm_helpers_dp_write_dsc_enable(
 776                 struct dc_context *ctx,
 777                 const struct dc_stream_state *stream,
 778                 bool enable)
 779 {
 780         static const uint8_t DSC_DISABLE;
 781         static const uint8_t DSC_DECODING = 0x01;
 782         static const uint8_t DSC_PASSTHROUGH = 0x02;
 783
 784         struct amdgpu_dm_connector *aconnector;
 785         struct drm_dp_mst_port *port;
 786         uint8_t enable_dsc = enable ? DSC_DECODING : DSC_DISABLE;
 787         uint8_t enable_passthrough = enable ? DSC_PASSTHROUGH : DSC_DISABLE;
 788         uint8_t ret = 0;
 789
 790         if (!stream)
 791                 return false;
 792
 793         if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
 794                 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 795
 796                 if (!aconnector->dsc_aux)
 797                         return false;
 798
 799                 // apply w/a to synaptics
 800                 if (needs_dsc_aux_workaround(aconnector->dc_link) &&
 801                     (aconnector->mst_downstream_port_present.byte & 0x7) != 0x3)
 802                         return write_dsc_enable_synaptics_non_virtual_dpcd_mst(
 803                                 aconnector->dsc_aux, stream, enable_dsc);
 804
 805                 port = aconnector->mst_output_port;
 806
 807                 if (enable) {
 808                         if (port->passthrough_aux) {
 809                                 ret = drm_dp_dpcd_write(port->passthrough_aux,
 810                                                         DP_DSC_ENABLE,
 811                                                         &enable_passthrough, 1);
 812                                 DC_LOG_DC("Sent DSC pass-through enable to virtual dpcd port, ret = %u\n",
 813                                           ret);
 814                         }
 815
 816                         ret = drm_dp_dpcd_write(aconnector->dsc_aux,
 817                                                 DP_DSC_ENABLE, &enable_dsc, 1);
 818                         DC_LOG_DC("Sent DSC decoding enable to %s port, ret = %u\n",
 819                                   (port->passthrough_aux) ? "remote RX" :
 820                                   "virtual dpcd",
 821                                   ret);
 822                 } else {
 823                         ret = drm_dp_dpcd_write(aconnector->dsc_aux,
 824                                                 DP_DSC_ENABLE, &enable_dsc, 1);
 825                         DC_LOG_DC("Sent DSC decoding disable to %s port, ret = %u\n",
 826                                   (port->passthrough_aux) ? "remote RX" :
 827                                   "virtual dpcd",
 828                                   ret);
 829
 830                         if (port->passthrough_aux) {
 831                                 ret = drm_dp_dpcd_write(port->passthrough_aux,
 832                                                         DP_DSC_ENABLE,
 833                                                         &enable_passthrough, 1);
 834                                 DC_LOG_DC("Sent DSC pass-through disable to virtual dpcd port, ret = %u\n",
 835                                           ret);
 836                         }
 837                 }
 838         }
 839
 840         if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || stream->signal == SIGNAL_TYPE_EDP) {
 841                 if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
 842                         ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1);
 843                         DC_LOG_DC("Send DSC %s to SST RX\n", enable_dsc ? "enable" : "disable");
 844                 } else if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
 845                         ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1);
 846                         DC_LOG_DC("Send DSC %s to DP-HDMI PCON\n", enable_dsc ? "enable" : "disable");
 847                 }
 848         }
 849
 850         return ret;
 851 }
 852
 853 bool dm_helpers_is_dp_sink_present(struct dc_link *link)
 854 {
 855         bool dp_sink_present;
 856         struct amdgpu_dm_connector *aconnector = link->priv;
 857
 858         if (!aconnector) {
 859                 BUG_ON("Failed to find connector for link!");
 860                 return true;
 861         }
 862
 863         mutex_lock(&aconnector->dm_dp_aux.aux.hw_mutex);
 864         dp_sink_present = dc_link_is_dp_sink_present(link);
 865         mutex_unlock(&aconnector->dm_dp_aux.aux.hw_mutex);
 866         return dp_sink_present;
 867 }
 868
 869 enum dc_edid_status dm_helpers_read_local_edid(
 870                 struct dc_context *ctx,
 871                 struct dc_link *link,
 872                 struct dc_sink *sink)
 873 {
 874         struct amdgpu_dm_connector *aconnector = link->priv;
 875         struct drm_connector *connector = &aconnector->base;
 876         struct i2c_adapter *ddc;
 877         int retry = 3;
 878         enum dc_edid_status edid_status;
 879         struct edid *edid;
 880
 881         if (link->aux_mode)
 882                 ddc = &aconnector->dm_dp_aux.aux.ddc;
 883         else
 884                 ddc = &aconnector->i2c->base;
 885
 886         /* some dongles read edid incorrectly the first time,
 887          * do check sum and retry to make sure read correct edid.
 888          */
 889         do {
 890
 891                 edid = drm_get_edid(&aconnector->base, ddc);
 892
 893                 /* DP Compliance Test 4.2.2.6 */
 894                 if (link->aux_mode && connector->edid_corrupt)
 895                         drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux, connector->real_edid_checksum);
 896
 897                 if (!edid && connector->edid_corrupt) {
 898                         connector->edid_corrupt = false;
 899                         return EDID_BAD_CHECKSUM;
 900                 }
 901
 902                 if (!edid)
 903                         return EDID_NO_RESPONSE;
 904
 905                 sink->dc_edid.length = EDID_LENGTH * (edid->extensions + 1);
 906                 memmove(sink->dc_edid.raw_edid, (uint8_t *)edid, sink->dc_edid.length);
 907
 908                 /* We don't need the original edid anymore */
 909                 kfree(edid);
 910
 911                 edid_status = dm_helpers_parse_edid_caps(
 912                                                 link,
 913                                                 &sink->dc_edid,
 914                                                 &sink->edid_caps);
 915
 916         } while (edid_status == EDID_BAD_CHECKSUM && --retry > 0);
 917
 918         if (edid_status != EDID_OK)
 919                 DRM_ERROR("EDID err: %d, on connector: %s",
 920                                 edid_status,
 921                                 aconnector->base.name);
 922         if (link->aux_mode) {
 923                 union test_request test_request = {0};
 924                 union test_response test_response = {0};
 925
 926                 dm_helpers_dp_read_dpcd(ctx,
 927                                         link,
 928                                         DP_TEST_REQUEST,
 929                                         &test_request.raw,
 930                                         sizeof(union test_request));
 931
 932                 if (!test_request.bits.EDID_READ)
 933                         return edid_status;
 934
 935                 test_response.bits.EDID_CHECKSUM_WRITE = 1;
 936
 937                 dm_helpers_dp_write_dpcd(ctx,
 938                                         link,
 939                                         DP_TEST_EDID_CHECKSUM,
 940                                         &sink->dc_edid.raw_edid[sink->dc_edid.length-1],
 941                                         1);
 942
 943                 dm_helpers_dp_write_dpcd(ctx,
 944                                         link,
 945                                         DP_TEST_RESPONSE,
 946                                         &test_response.raw,
 947                                         sizeof(test_response));
 948
 949         }
 950
 951         return edid_status;
 952 }
 953 int dm_helper_dmub_aux_transfer_sync(
 954                 struct dc_context *ctx,
 955                 const struct dc_link *link,
 956                 struct aux_payload *payload,
 957                 enum aux_return_code_type *operation_result)
 958 {
 959         if (!link->hpd_status) {
 960                 *operation_result = AUX_RET_ERROR_HPD_DISCON;
 961                 return -1;
 962         }
 963
 964         return amdgpu_dm_process_dmub_aux_transfer_sync(ctx, link->link_index, payload,
 965                         operation_result);
 966 }
 967
 968 int dm_helpers_dmub_set_config_sync(struct dc_context *ctx,
 969                 const struct dc_link *link,
 970                 struct set_config_cmd_payload *payload,
 971                 enum set_config_status *operation_result)
 972 {
 973         return amdgpu_dm_process_dmub_set_config_sync(ctx, link->link_index, payload,
 974                         operation_result);
 975 }
 976
 977 void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks)
 978 {
 979         /* TODO: something */
 980 }
 981
 982 void dm_helpers_smu_timeout(struct dc_context *ctx, unsigned int msg_id, unsigned int param, unsigned int timeout_us)
 983 {
 984         // TODO:
 985         //amdgpu_device_gpu_recover(dc_context->driver-context, NULL);
 986 }
 987
 988 void dm_helpers_init_panel_settings(
 989         struct dc_context *ctx,
 990         struct dc_panel_config *panel_config,
 991         struct dc_sink *sink)
 992 {
 993         // Extra Panel Power Sequence
 994         panel_config->pps.extra_t3_ms = sink->edid_caps.panel_patch.extra_t3_ms;
 995         panel_config->pps.extra_t7_ms = sink->edid_caps.panel_patch.extra_t7_ms;
 996         panel_config->pps.extra_delay_backlight_off = sink->edid_caps.panel_patch.extra_delay_backlight_off;
 997         panel_config->pps.extra_post_t7_ms = 0;
 998         panel_config->pps.extra_pre_t11_ms = 0;
 999         panel_config->pps.extra_t12_ms = sink->edid_caps.panel_patch.extra_t12_ms;
1000         panel_config->pps.extra_post_OUI_ms = 0;
1001         // Feature DSC
1002         panel_config->dsc.disable_dsc_edp = false;
1003         panel_config->dsc.force_dsc_edp_policy = 0;
1004 }
1005
1006 void dm_helpers_override_panel_settings(
1007         struct dc_context *ctx,
1008         struct dc_panel_config *panel_config)
1009 {
1010         // Feature DSC
1011         if (amdgpu_dc_debug_mask & DC_DISABLE_DSC)
1012                 panel_config->dsc.disable_dsc_edp = true;
1013 }
1014
1015 void *dm_helpers_allocate_gpu_mem(
1016                 struct dc_context *ctx,
1017                 enum dc_gpu_mem_alloc_type type,
1018                 size_t size,
1019                 long long *addr)
1020 {
1021         struct amdgpu_device *adev = ctx->driver_context;
1022         struct dal_allocation *da;
1023         u32 domain = (type == DC_MEM_ALLOC_TYPE_GART) ?
1024                 AMDGPU_GEM_DOMAIN_GTT : AMDGPU_GEM_DOMAIN_VRAM;
1025         int ret;
1026
1027         da = kzalloc(sizeof(struct dal_allocation), GFP_KERNEL);
1028         if (!da)
1029                 return NULL;
1030
1031         ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
1032                                       domain, &da->bo,
1033                                       &da->gpu_addr, &da->cpu_ptr);
1034
1035         *addr = da->gpu_addr;
1036
1037         if (ret) {
1038                 kfree(da);
1039                 return NULL;
1040         }
1041
1042         /* add da to list in dm */
1043         list_add(&da->list, &adev->dm.da_list);
1044
1045         return da->cpu_ptr;
1046 }
1047
1048 void dm_helpers_free_gpu_mem(
1049                 struct dc_context *ctx,
1050                 enum dc_gpu_mem_alloc_type type,
1051                 void *pvMem)
1052 {
1053         struct amdgpu_device *adev = ctx->driver_context;
1054         struct dal_allocation *da;
1055
1056         /* walk the da list in DM */
1057         list_for_each_entry(da, &adev->dm.da_list, list) {
1058                 if (pvMem == da->cpu_ptr) {
1059                         amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr);
1060                         list_del(&da->list);
1061                         kfree(da);
1062                         break;
1063                 }
1064         }
1065 }
1066
1067 bool dm_helpers_dmub_outbox_interrupt_control(struct dc_context *ctx, bool enable)
1068 {
1069         enum dc_irq_source irq_source;
1070         bool ret;
1071
1072         irq_source = DC_IRQ_SOURCE_DMCUB_OUTBOX;
1073
1074         ret = dc_interrupt_set(ctx->dc, irq_source, enable);
1075
1076         DRM_DEBUG_DRIVER("Dmub trace irq %sabling: r=%d\n",
1077                          enable ? "en" : "dis", ret);
1078         return ret;
1079 }
1080
1081 void dm_helpers_mst_enable_stream_features(const struct dc_stream_state *stream)
1082 {
1083         /* TODO: virtual DPCD */
1084         struct dc_link *link = stream->link;
1085         union down_spread_ctrl old_downspread;
1086         union down_spread_ctrl new_downspread;
1087
1088         if (link->aux_access_disabled)
1089                 return;
1090
1091         if (!dm_helpers_dp_read_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL,
1092                                      &old_downspread.raw,
1093                                      sizeof(old_downspread)))
1094                 return;
1095
1096         new_downspread.raw = old_downspread.raw;
1097         new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
1098                 (stream->ignore_msa_timing_param) ? 1 : 0;
1099
1100         if (new_downspread.raw != old_downspread.raw)
1101                 dm_helpers_dp_write_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL,
1102                                          &new_downspread.raw,
1103                                          sizeof(new_downspread));
1104 }
1105
1106 bool dm_helpers_dp_handle_test_pattern_request(
1107                 struct dc_context *ctx,
1108                 const struct dc_link *link,
1109                 union link_test_pattern dpcd_test_pattern,
1110                 union test_misc dpcd_test_params)
1111 {
1112         enum dp_test_pattern test_pattern;
1113         enum dp_test_pattern_color_space test_pattern_color_space =
1114                         DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED;
1115         enum dc_color_depth requestColorDepth = COLOR_DEPTH_UNDEFINED;
1116         enum dc_pixel_encoding requestPixelEncoding = PIXEL_ENCODING_UNDEFINED;
1117         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
1118         struct pipe_ctx *pipe_ctx = NULL;
1119         struct amdgpu_dm_connector *aconnector = link->priv;
1120         int i;
1121
1122         for (i = 0; i < MAX_PIPES; i++) {
1123                 if (pipes[i].stream == NULL)
1124                         continue;
1125
1126                 if (pipes[i].stream->link == link && !pipes[i].top_pipe &&
1127                         !pipes[i].prev_odm_pipe) {
1128                         pipe_ctx = &pipes[i];
1129                         break;
1130                 }
1131         }
1132
1133         if (pipe_ctx == NULL)
1134                 return false;
1135
1136         switch (dpcd_test_pattern.bits.PATTERN) {
1137         case LINK_TEST_PATTERN_COLOR_RAMP:
1138                 test_pattern = DP_TEST_PATTERN_COLOR_RAMP;
1139         break;
1140         case LINK_TEST_PATTERN_VERTICAL_BARS:
1141                 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;
1142         break; /* black and white */
1143         case LINK_TEST_PATTERN_COLOR_SQUARES:
1144                 test_pattern = (dpcd_test_params.bits.DYN_RANGE ==
1145                                 TEST_DYN_RANGE_VESA ?
1146                                 DP_TEST_PATTERN_COLOR_SQUARES :
1147                                 DP_TEST_PATTERN_COLOR_SQUARES_CEA);
1148         break;
1149         default:
1150                 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
1151         break;
1152         }
1153
1154         if (dpcd_test_params.bits.CLR_FORMAT == 0)
1155                 test_pattern_color_space = DP_TEST_PATTERN_COLOR_SPACE_RGB;
1156         else
1157                 test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ?
1158                                 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 :
1159                                 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601;
1160
1161         switch (dpcd_test_params.bits.BPC) {
1162         case 0: // 6 bits
1163                 requestColorDepth = COLOR_DEPTH_666;
1164                 break;
1165         case 1: // 8 bits
1166                 requestColorDepth = COLOR_DEPTH_888;
1167                 break;
1168         case 2: // 10 bits
1169                 requestColorDepth = COLOR_DEPTH_101010;
1170                 break;
1171         case 3: // 12 bits
1172                 requestColorDepth = COLOR_DEPTH_121212;
1173                 break;
1174         default:
1175                 break;
1176         }
1177
1178         switch (dpcd_test_params.bits.CLR_FORMAT) {
1179         case 0:
1180                 requestPixelEncoding = PIXEL_ENCODING_RGB;
1181                 break;
1182         case 1:
1183                 requestPixelEncoding = PIXEL_ENCODING_YCBCR422;
1184                 break;
1185         case 2:
1186                 requestPixelEncoding = PIXEL_ENCODING_YCBCR444;
1187                 break;
1188         default:
1189                 requestPixelEncoding = PIXEL_ENCODING_RGB;
1190                 break;
1191         }
1192
1193         if ((requestColorDepth != COLOR_DEPTH_UNDEFINED
1194                 && pipe_ctx->stream->timing.display_color_depth != requestColorDepth)
1195                 || (requestPixelEncoding != PIXEL_ENCODING_UNDEFINED
1196                 && pipe_ctx->stream->timing.pixel_encoding != requestPixelEncoding)) {
1197                 DC_LOG_DEBUG("%s: original bpc %d pix encoding %d, changing to %d  %d\n",
1198                                 __func__,
1199                                 pipe_ctx->stream->timing.display_color_depth,
1200                                 pipe_ctx->stream->timing.pixel_encoding,
1201                                 requestColorDepth,
1202                                 requestPixelEncoding);
1203                 pipe_ctx->stream->timing.display_color_depth = requestColorDepth;
1204                 pipe_ctx->stream->timing.pixel_encoding = requestPixelEncoding;
1205
1206                 dc_link_update_dsc_config(pipe_ctx);
1207
1208                 aconnector->timing_changed = true;
1209                 /* store current timing */
1210                 if (aconnector->timing_requested)
1211                         *aconnector->timing_requested = pipe_ctx->stream->timing;
1212                 else
1213                         DC_LOG_ERROR("%s: timing storage failed\n", __func__);
1214
1215         }
1216
1217         dc_link_dp_set_test_pattern(
1218                 (struct dc_link *) link,
1219                 test_pattern,
1220                 test_pattern_color_space,
1221                 NULL,
1222                 NULL,
1223                 0);
1224
1225         return false;
1226 }
1227
1228 void dm_set_phyd32clk(struct dc_context *ctx, int freq_khz)
1229 {
1230        // TODO
1231 }
1232
1233 void dm_helpers_enable_periodic_detection(struct dc_context *ctx, bool enable)
1234 {
1235         /* TODO: add periodic detection implementation */
1236 }
1237
1238 void dm_helpers_dp_mst_update_branch_bandwidth(
1239                 struct dc_context *ctx,
1240                 struct dc_link *link)
1241 {
1242         // TODO
1243 }
1244
1245 static bool dm_is_freesync_pcon_whitelist(const uint32_t branch_dev_id)
1246 {
1247         bool ret_val = false;
1248
1249         switch (branch_dev_id) {
1250         case DP_BRANCH_DEVICE_ID_0060AD:
1251         case DP_BRANCH_DEVICE_ID_00E04C:
1252         case DP_BRANCH_DEVICE_ID_90CC24:
1253                 ret_val = true;
1254                 break;
1255         default:
1256                 break;
1257         }
1258
1259         return ret_val;
1260 }
1261
1262 enum adaptive_sync_type dm_get_adaptive_sync_support_type(struct dc_link *link)
1263 {
1264         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
1265         enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE;
1266
1267         switch (dpcd_caps->dongle_type) {
1268         case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
1269                 if (dpcd_caps->adaptive_sync_caps.dp_adap_sync_caps.bits.ADAPTIVE_SYNC_SDP_SUPPORT == true &&
1270                         dpcd_caps->allow_invalid_MSA_timing_param == true &&
1271                         dm_is_freesync_pcon_whitelist(dpcd_caps->branch_dev_id))
1272                         as_type = FREESYNC_TYPE_PCON_IN_WHITELIST;
1273                 break;
1274         default:
1275                 break;
1276         }
1277
1278         return as_type;
1279 }