drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/string.h>
  27 #include <linux/acpi.h>
  28 #include <linux/i2c.h>
  29
  30 #include <drm/drm_atomic.h>
  31 #include <drm/drm_probe_helper.h>
  32 #include <drm/amdgpu_drm.h>
  33 #include <drm/drm_edid.h>
  34
  35 #include "dm_services.h"
  36 #include "amdgpu.h"
  37 #include "dc.h"
  38 #include "amdgpu_dm.h"
  39 #include "amdgpu_dm_irq.h"
  40 #include "amdgpu_dm_mst_types.h"
  41 #include "dpcd_defs.h"
  42 #include "dc/inc/core_types.h"
  43
  44 #include "dm_helpers.h"
  45 #include "ddc_service_types.h"
  46
  47 static u32 edid_extract_panel_id(struct edid *edid)
  48 {
  49         return (u32)edid->mfg_id[0] << 24   |
  50                (u32)edid->mfg_id[1] << 16   |
  51                (u32)EDID_PRODUCT_ID(edid);
  52 }
  53
  54 static void apply_edid_quirks(struct edid *edid, struct dc_edid_caps *edid_caps)
  55 {
  56         uint32_t panel_id = edid_extract_panel_id(edid);
  57
  58         switch (panel_id) {
  59         /* Workaround for some monitors which does not work well with FAMS */
  60         case drm_edid_encode_panel_id('S', 'A', 'M', 0x0E5E):
  61         case drm_edid_encode_panel_id('S', 'A', 'M', 0x7053):
  62         case drm_edid_encode_panel_id('S', 'A', 'M', 0x71AC):
  63                 DRM_DEBUG_DRIVER("Disabling FAMS on monitor with panel id %X\n", panel_id);
  64                 edid_caps->panel_patch.disable_fams = true;
  65                 break;
  66         default:
  67                 return;
  68         }
  69 }
  70
  71 /**
  72  * dm_helpers_parse_edid_caps() - Parse edid caps
  73  *
  74  * @link: current detected link
  75  * @edid:       [in] pointer to edid
  76  * @edid_caps:  [in] pointer to edid caps
  77  *
  78  * Return: void
  79  */
  80 enum dc_edid_status dm_helpers_parse_edid_caps(
  81                 struct dc_link *link,
  82                 const struct dc_edid *edid,
  83                 struct dc_edid_caps *edid_caps)
  84 {
  85         struct amdgpu_dm_connector *aconnector = link->priv;
  86         struct drm_connector *connector = &aconnector->base;
  87         struct edid *edid_buf = edid ? (struct edid *) edid->raw_edid : NULL;
  88         struct cea_sad *sads;
  89         int sad_count = -1;
  90         int sadb_count = -1;
  91         int i = 0;
  92         uint8_t *sadb = NULL;
  93
  94         enum dc_edid_status result = EDID_OK;
  95
  96         if (!edid_caps || !edid)
  97                 return EDID_BAD_INPUT;
  98
  99         if (!drm_edid_is_valid(edid_buf))
 100                 result = EDID_BAD_CHECKSUM;
 101
 102         edid_caps->manufacturer_id = (uint16_t) edid_buf->mfg_id[0] |
 103                                         ((uint16_t) edid_buf->mfg_id[1])<<8;
 104         edid_caps->product_id = (uint16_t) edid_buf->prod_code[0] |
 105                                         ((uint16_t) edid_buf->prod_code[1])<<8;
 106         edid_caps->serial_number = edid_buf->serial;
 107         edid_caps->manufacture_week = edid_buf->mfg_week;
 108         edid_caps->manufacture_year = edid_buf->mfg_year;
 109
 110         drm_edid_get_monitor_name(edid_buf,
 111                                   edid_caps->display_name,
 112                                   AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
 113
 114         edid_caps->edid_hdmi = connector->display_info.is_hdmi;
 115
 116         sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads);
 117         if (sad_count <= 0)
 118                 return result;
 119
 120         edid_caps->audio_mode_count = min(sad_count, DC_MAX_AUDIO_DESC_COUNT);
 121         for (i = 0; i < edid_caps->audio_mode_count; ++i) {
 122                 struct cea_sad *sad = &sads[i];
 123
 124                 edid_caps->audio_modes[i].format_code = sad->format;
 125                 edid_caps->audio_modes[i].channel_count = sad->channels + 1;
 126                 edid_caps->audio_modes[i].sample_rate = sad->freq;
 127                 edid_caps->audio_modes[i].sample_size = sad->byte2;
 128         }
 129
 130         sadb_count = drm_edid_to_speaker_allocation((struct edid *) edid->raw_edid, &sadb);
 131
 132         if (sadb_count < 0) {
 133                 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sadb_count);
 134                 sadb_count = 0;
 135         }
 136
 137         if (sadb_count)
 138                 edid_caps->speaker_flags = sadb[0];
 139         else
 140                 edid_caps->speaker_flags = DEFAULT_SPEAKER_LOCATION;
 141
 142         apply_edid_quirks(edid_buf, edid_caps);
 143
 144         kfree(sads);
 145         kfree(sadb);
 146
 147         return result;
 148 }
 149
 150 static void
 151 fill_dc_mst_payload_table_from_drm(struct dc_link *link,
 152                                    bool enable,
 153                                    struct drm_dp_mst_atomic_payload *target_payload,
 154                                    struct dc_dp_mst_stream_allocation_table *table)
 155 {
 156         struct dc_dp_mst_stream_allocation_table new_table = { 0 };
 157         struct dc_dp_mst_stream_allocation *sa;
 158         struct link_mst_stream_allocation_table copy_of_link_table =
 159                                                                                 link->mst_stream_alloc_table;
 160
 161         int i;
 162         int current_hw_table_stream_cnt = copy_of_link_table.stream_count;
 163         struct link_mst_stream_allocation *dc_alloc;
 164
 165         /* TODO: refactor to set link->mst_stream_alloc_table directly if possible.*/
 166         if (enable) {
 167                 dc_alloc =
 168                 &copy_of_link_table.stream_allocations[current_hw_table_stream_cnt];
 169                 dc_alloc->vcp_id = target_payload->vcpi;
 170                 dc_alloc->slot_count = target_payload->time_slots;
 171         } else {
 172                 for (i = 0; i < copy_of_link_table.stream_count; i++) {
 173                         dc_alloc =
 174                         &copy_of_link_table.stream_allocations[i];
 175
 176                         if (dc_alloc->vcp_id == target_payload->vcpi) {
 177                                 dc_alloc->vcp_id = 0;
 178                                 dc_alloc->slot_count = 0;
 179                                 break;
 180                         }
 181                 }
 182                 ASSERT(i != copy_of_link_table.stream_count);
 183         }
 184
 185         /* Fill payload info*/
 186         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
 187                 dc_alloc =
 188                         &copy_of_link_table.stream_allocations[i];
 189                 if (dc_alloc->vcp_id > 0 && dc_alloc->slot_count > 0) {
 190                         sa = &new_table.stream_allocations[new_table.stream_count];
 191                         sa->slot_count = dc_alloc->slot_count;
 192                         sa->vcp_id = dc_alloc->vcp_id;
 193                         new_table.stream_count++;
 194                 }
 195         }
 196
 197         /* Overwrite the old table */
 198         *table = new_table;
 199 }
 200
 201 void dm_helpers_dp_update_branch_info(
 202         struct dc_context *ctx,
 203         const struct dc_link *link)
 204 {}
 205
 206 static void dm_helpers_construct_old_payload(
 207                         struct dc_link *link,
 208                         int pbn_per_slot,
 209                         struct drm_dp_mst_atomic_payload *new_payload,
 210                         struct drm_dp_mst_atomic_payload *old_payload)
 211 {
 212         struct link_mst_stream_allocation_table current_link_table =
 213                                                                         link->mst_stream_alloc_table;
 214         struct link_mst_stream_allocation *dc_alloc;
 215         int i;
 216
 217         *old_payload = *new_payload;
 218
 219         /* Set correct time_slots/PBN of old payload.
 220          * other fields (delete & dsc_enabled) in
 221          * struct drm_dp_mst_atomic_payload are don't care fields
 222          * while calling drm_dp_remove_payload()
 223          */
 224         for (i = 0; i < current_link_table.stream_count; i++) {
 225                 dc_alloc =
 226                         &current_link_table.stream_allocations[i];
 227
 228                 if (dc_alloc->vcp_id == new_payload->vcpi) {
 229                         old_payload->time_slots = dc_alloc->slot_count;
 230                         old_payload->pbn = dc_alloc->slot_count * pbn_per_slot;
 231                         break;
 232                 }
 233         }
 234
 235         /* make sure there is an old payload*/
 236         ASSERT(i != current_link_table.stream_count);
 237
 238 }
 239
 240 /*
 241  * Writes payload allocation table in immediate downstream device.
 242  */
 243 bool dm_helpers_dp_mst_write_payload_allocation_table(
 244                 struct dc_context *ctx,
 245                 const struct dc_stream_state *stream,
 246                 struct dc_dp_mst_stream_allocation_table *proposed_table,
 247                 bool enable)
 248 {
 249         struct amdgpu_dm_connector *aconnector;
 250         struct drm_dp_mst_topology_state *mst_state;
 251         struct drm_dp_mst_atomic_payload *target_payload, *new_payload, old_payload;
 252         struct drm_dp_mst_topology_mgr *mst_mgr;
 253
 254         aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 255         /* Accessing the connector state is required for vcpi_slots allocation
 256          * and directly relies on behaviour in commit check
 257          * that blocks before commit guaranteeing that the state
 258          * is not gonna be swapped while still in use in commit tail
 259          */
 260
 261         if (!aconnector || !aconnector->mst_root)
 262                 return false;
 263
 264         mst_mgr = &aconnector->mst_root->mst_mgr;
 265         mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state);
 266
 267         /* It's OK for this to fail */
 268         new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port);
 269
 270         if (enable) {
 271                 target_payload = new_payload;
 272
 273                 drm_dp_add_payload_part1(mst_mgr, mst_state, new_payload);
 274         } else {
 275                 /* construct old payload by VCPI*/
 276                 dm_helpers_construct_old_payload(stream->link, mst_state->pbn_div,
 277                                                 new_payload, &old_payload);
 278                 target_payload = &old_payload;
 279
 280                 drm_dp_remove_payload(mst_mgr, mst_state, &old_payload, new_payload);
 281         }
 282
 283         /* mst_mgr->->payloads are VC payload notify MST branch using DPCD or
 284          * AUX message. The sequence is slot 1-63 allocated sequence for each
 285          * stream. AMD ASIC stream slot allocation should follow the same
 286          * sequence. copy DRM MST allocation to dc
 287          */
 288         fill_dc_mst_payload_table_from_drm(stream->link, enable, target_payload, proposed_table);
 289
 290         return true;
 291 }
 292
 293 /*
 294  * poll pending down reply
 295  */
 296 void dm_helpers_dp_mst_poll_pending_down_reply(
 297         struct dc_context *ctx,
 298         const struct dc_link *link)
 299 {}
 300
 301 /*
 302  * Clear payload allocation table before enable MST DP link.
 303  */
 304 void dm_helpers_dp_mst_clear_payload_allocation_table(
 305         struct dc_context *ctx,
 306         const struct dc_link *link)
 307 {}
 308
 309 /*
 310  * Polls for ACT (allocation change trigger) handled and sends
 311  * ALLOCATE_PAYLOAD message.
 312  */
 313 enum act_return_status dm_helpers_dp_mst_poll_for_allocation_change_trigger(
 314                 struct dc_context *ctx,
 315                 const struct dc_stream_state *stream)
 316 {
 317         struct amdgpu_dm_connector *aconnector;
 318         struct drm_dp_mst_topology_mgr *mst_mgr;
 319         int ret;
 320
 321         aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 322
 323         if (!aconnector || !aconnector->mst_root)
 324                 return ACT_FAILED;
 325
 326         mst_mgr = &aconnector->mst_root->mst_mgr;
 327
 328         if (!mst_mgr->mst_state)
 329                 return ACT_FAILED;
 330
 331         ret = drm_dp_check_act_status(mst_mgr);
 332
 333         if (ret)
 334                 return ACT_FAILED;
 335
 336         return ACT_SUCCESS;
 337 }
 338
 339 bool dm_helpers_dp_mst_send_payload_allocation(
 340                 struct dc_context *ctx,
 341                 const struct dc_stream_state *stream,
 342                 bool enable)
 343 {
 344         struct amdgpu_dm_connector *aconnector;
 345         struct drm_dp_mst_topology_state *mst_state;
 346         struct drm_dp_mst_topology_mgr *mst_mgr;
 347         struct drm_dp_mst_atomic_payload *payload;
 348         enum mst_progress_status set_flag = MST_ALLOCATE_NEW_PAYLOAD;
 349         enum mst_progress_status clr_flag = MST_CLEAR_ALLOCATED_PAYLOAD;
 350         int ret = 0;
 351
 352         aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 353
 354         if (!aconnector || !aconnector->mst_root)
 355                 return false;
 356
 357         mst_mgr = &aconnector->mst_root->mst_mgr;
 358         mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state);
 359
 360         payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port);
 361
 362         if (!enable) {
 363                 set_flag = MST_CLEAR_ALLOCATED_PAYLOAD;
 364                 clr_flag = MST_ALLOCATE_NEW_PAYLOAD;
 365         }
 366
 367         if (enable)
 368                 ret = drm_dp_add_payload_part2(mst_mgr, mst_state->base.state, payload);
 369
 370         if (ret) {
 371                 amdgpu_dm_set_mst_status(&aconnector->mst_status,
 372                         set_flag, false);
 373         } else {
 374                 amdgpu_dm_set_mst_status(&aconnector->mst_status,
 375                         set_flag, true);
 376                 amdgpu_dm_set_mst_status(&aconnector->mst_status,
 377                         clr_flag, false);
 378         }
 379
 380         return true;
 381 }
 382
 383 void dm_dtn_log_begin(struct dc_context *ctx,
 384         struct dc_log_buffer_ctx *log_ctx)
 385 {
 386         static const char msg[] = "[dtn begin]\n";
 387
 388         if (!log_ctx) {
 389                 pr_info("%s", msg);
 390                 return;
 391         }
 392
 393         dm_dtn_log_append_v(ctx, log_ctx, "%s", msg);
 394 }
 395
 396 __printf(3, 4)
 397 void dm_dtn_log_append_v(struct dc_context *ctx,
 398         struct dc_log_buffer_ctx *log_ctx,
 399         const char *msg, ...)
 400 {
 401         va_list args;
 402         size_t total;
 403         int n;
 404
 405         if (!log_ctx) {
 406                 /* No context, redirect to dmesg. */
 407                 struct va_format vaf;
 408
 409                 vaf.fmt = msg;
 410                 vaf.va = &args;
 411
 412                 va_start(args, msg);
 413                 pr_info("%pV", &vaf);
 414                 va_end(args);
 415
 416                 return;
 417         }
 418
 419         /* Measure the output. */
 420         va_start(args, msg);
 421         n = vsnprintf(NULL, 0, msg, args);
 422         va_end(args);
 423
 424         if (n <= 0)
 425                 return;
 426
 427         /* Reallocate the string buffer as needed. */
 428         total = log_ctx->pos + n + 1;
 429
 430         if (total > log_ctx->size) {
 431                 char *buf = kvcalloc(total, sizeof(char), GFP_KERNEL);
 432
 433                 if (buf) {
 434                         memcpy(buf, log_ctx->buf, log_ctx->pos);
 435                         kfree(log_ctx->buf);
 436
 437                         log_ctx->buf = buf;
 438                         log_ctx->size = total;
 439                 }
 440         }
 441
 442         if (!log_ctx->buf)
 443                 return;
 444
 445         /* Write the formatted string to the log buffer. */
 446         va_start(args, msg);
 447         n = vscnprintf(
 448                 log_ctx->buf + log_ctx->pos,
 449                 log_ctx->size - log_ctx->pos,
 450                 msg,
 451                 args);
 452         va_end(args);
 453
 454         if (n > 0)
 455                 log_ctx->pos += n;
 456 }
 457
 458 void dm_dtn_log_end(struct dc_context *ctx,
 459         struct dc_log_buffer_ctx *log_ctx)
 460 {
 461         static const char msg[] = "[dtn end]\n";
 462
 463         if (!log_ctx) {
 464                 pr_info("%s", msg);
 465                 return;
 466         }
 467
 468         dm_dtn_log_append_v(ctx, log_ctx, "%s", msg);
 469 }
 470
 471 bool dm_helpers_dp_mst_start_top_mgr(
 472                 struct dc_context *ctx,
 473                 const struct dc_link *link,
 474                 bool boot)
 475 {
 476         struct amdgpu_dm_connector *aconnector = link->priv;
 477         int ret;
 478
 479         if (!aconnector) {
 480                 DRM_ERROR("Failed to find connector for link!");
 481                 return false;
 482         }
 483
 484         if (boot) {
 485                 DRM_INFO("DM_MST: Differing MST start on aconnector: %p [id: %d]\n",
 486                                         aconnector, aconnector->base.base.id);
 487                 return true;
 488         }
 489
 490         DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n",
 491                         aconnector, aconnector->base.base.id);
 492
 493         ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
 494         if (ret < 0) {
 495                 DRM_ERROR("DM_MST: Failed to set the device into MST mode!");
 496                 return false;
 497         }
 498
 499         DRM_INFO("DM_MST: DP%x, %d-lane link detected\n", aconnector->mst_mgr.dpcd[0],
 500                 aconnector->mst_mgr.dpcd[2] & DP_MAX_LANE_COUNT_MASK);
 501
 502         return true;
 503 }
 504
 505 bool dm_helpers_dp_mst_stop_top_mgr(
 506                 struct dc_context *ctx,
 507                 struct dc_link *link)
 508 {
 509         struct amdgpu_dm_connector *aconnector = link->priv;
 510
 511         if (!aconnector) {
 512                 DRM_ERROR("Failed to find connector for link!");
 513                 return false;
 514         }
 515
 516         DRM_INFO("DM_MST: stopping TM on aconnector: %p [id: %d]\n",
 517                         aconnector, aconnector->base.base.id);
 518
 519         if (aconnector->mst_mgr.mst_state == true) {
 520                 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false);
 521                 link->cur_link_settings.lane_count = 0;
 522         }
 523
 524         return false;
 525 }
 526
 527 bool dm_helpers_dp_read_dpcd(
 528                 struct dc_context *ctx,
 529                 const struct dc_link *link,
 530                 uint32_t address,
 531                 uint8_t *data,
 532                 uint32_t size)
 533 {
 534
 535         struct amdgpu_dm_connector *aconnector = link->priv;
 536
 537         if (!aconnector) {
 538                 DC_LOG_DC("Failed to find connector for link!\n");
 539                 return false;
 540         }
 541
 542         return drm_dp_dpcd_read(&aconnector->dm_dp_aux.aux, address, data,
 543                                 size) == size;
 544 }
 545
 546 bool dm_helpers_dp_write_dpcd(
 547                 struct dc_context *ctx,
 548                 const struct dc_link *link,
 549                 uint32_t address,
 550                 const uint8_t *data,
 551                 uint32_t size)
 552 {
 553         struct amdgpu_dm_connector *aconnector = link->priv;
 554
 555         if (!aconnector) {
 556                 DRM_ERROR("Failed to find connector for link!");
 557                 return false;
 558         }
 559
 560         return drm_dp_dpcd_write(&aconnector->dm_dp_aux.aux,
 561                         address, (uint8_t *)data, size) > 0;
 562 }
 563
 564 bool dm_helpers_submit_i2c(
 565                 struct dc_context *ctx,
 566                 const struct dc_link *link,
 567                 struct i2c_command *cmd)
 568 {
 569         struct amdgpu_dm_connector *aconnector = link->priv;
 570         struct i2c_msg *msgs;
 571         int i = 0;
 572         int num = cmd->number_of_payloads;
 573         bool result;
 574
 575         if (!aconnector) {
 576                 DRM_ERROR("Failed to find connector for link!");
 577                 return false;
 578         }
 579
 580         msgs = kcalloc(num, sizeof(struct i2c_msg), GFP_KERNEL);
 581
 582         if (!msgs)
 583                 return false;
 584
 585         for (i = 0; i < num; i++) {
 586                 msgs[i].flags = cmd->payloads[i].write ? 0 : I2C_M_RD;
 587                 msgs[i].addr = cmd->payloads[i].address;
 588                 msgs[i].len = cmd->payloads[i].length;
 589                 msgs[i].buf = cmd->payloads[i].data;
 590         }
 591
 592         result = i2c_transfer(&aconnector->i2c->base, msgs, num) == num;
 593
 594         kfree(msgs);
 595
 596         return result;
 597 }
 598
 599 static bool execute_synaptics_rc_command(struct drm_dp_aux *aux,
 600                 bool is_write_cmd,
 601                 unsigned char cmd,
 602                 unsigned int length,
 603                 unsigned int offset,
 604                 unsigned char *data)
 605 {
 606         bool success = false;
 607         unsigned char rc_data[16] = {0};
 608         unsigned char rc_offset[4] = {0};
 609         unsigned char rc_length[2] = {0};
 610         unsigned char rc_cmd = 0;
 611         unsigned char rc_result = 0xFF;
 612         unsigned char i = 0;
 613         int ret;
 614
 615         if (is_write_cmd) {
 616                 // write rc data
 617                 memmove(rc_data, data, length);
 618                 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_DATA, rc_data, sizeof(rc_data));
 619         }
 620
 621         // write rc offset
 622         rc_offset[0] = (unsigned char) offset & 0xFF;
 623         rc_offset[1] = (unsigned char) (offset >> 8) & 0xFF;
 624         rc_offset[2] = (unsigned char) (offset >> 16) & 0xFF;
 625         rc_offset[3] = (unsigned char) (offset >> 24) & 0xFF;
 626         ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_OFFSET, rc_offset, sizeof(rc_offset));
 627
 628         // write rc length
 629         rc_length[0] = (unsigned char) length & 0xFF;
 630         rc_length[1] = (unsigned char) (length >> 8) & 0xFF;
 631         ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_LENGTH, rc_length, sizeof(rc_length));
 632
 633         // write rc cmd
 634         rc_cmd = cmd | 0x80;
 635         ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd));
 636
 637         if (ret < 0) {
 638                 DRM_ERROR("%s: write cmd ..., err = %d\n",  __func__, ret);
 639                 return false;
 640         }
 641
 642         // poll until active is 0
 643         for (i = 0; i < 10; i++) {
 644                 drm_dp_dpcd_read(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd));
 645                 if (rc_cmd == cmd)
 646                         // active is 0
 647                         break;
 648                 msleep(10);
 649         }
 650
 651         // read rc result
 652         drm_dp_dpcd_read(aux, SYNAPTICS_RC_RESULT, &rc_result, sizeof(rc_result));
 653         success = (rc_result == 0);
 654
 655         if (success && !is_write_cmd) {
 656                 // read rc data
 657                 drm_dp_dpcd_read(aux, SYNAPTICS_RC_DATA, data, length);
 658         }
 659
 660         DC_LOG_DC("%s: success = %d\n", __func__, success);
 661
 662         return success;
 663 }
 664
 665 static void apply_synaptics_fifo_reset_wa(struct drm_dp_aux *aux)
 666 {
 667         unsigned char data[16] = {0};
 668
 669         DC_LOG_DC("Start %s\n", __func__);
 670
 671         // Step 2
 672         data[0] = 'P';
 673         data[1] = 'R';
 674         data[2] = 'I';
 675         data[3] = 'U';
 676         data[4] = 'S';
 677
 678         if (!execute_synaptics_rc_command(aux, true, 0x01, 5, 0, data))
 679                 return;
 680
 681         // Step 3 and 4
 682         if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data))
 683                 return;
 684
 685         data[0] &= (~(1 << 1)); // set bit 1 to 0
 686         if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data))
 687                 return;
 688
 689         if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data))
 690                 return;
 691
 692         data[0] &= (~(1 << 1)); // set bit 1 to 0
 693         if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220D98, data))
 694                 return;
 695
 696         if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data))
 697                 return;
 698
 699         data[0] &= (~(1 << 1)); // set bit 1 to 0
 700         if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data))
 701                 return;
 702
 703         // Step 3 and 5
 704         if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data))
 705                 return;
 706
 707         data[0] |= (1 << 1); // set bit 1 to 1
 708         if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data))
 709                 return;
 710
 711         if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data))
 712                 return;
 713
 714         data[0] |= (1 << 1); // set bit 1 to 1
 715
 716         if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data))
 717                 return;
 718
 719         data[0] |= (1 << 1); // set bit 1 to 1
 720         if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data))
 721                 return;
 722
 723         // Step 6
 724         if (!execute_synaptics_rc_command(aux, true, 0x02, 0, 0, NULL))
 725                 return;
 726
 727         DC_LOG_DC("Done %s\n", __func__);
 728 }
 729
 730 /* MST Dock */
 731 static const uint8_t SYNAPTICS_DEVICE_ID[] = "SYNA";
 732
 733 static uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst(
 734                 struct drm_dp_aux *aux,
 735                 const struct dc_stream_state *stream,
 736                 bool enable)
 737 {
 738         uint8_t ret = 0;
 739
 740         DC_LOG_DC("Configure DSC to non-virtual dpcd synaptics\n");
 741
 742         if (enable) {
 743                 /* When DSC is enabled on previous boot and reboot with the hub,
 744                  * there is a chance that Synaptics hub gets stuck during reboot sequence.
 745                  * Applying a workaround to reset Synaptics SDP fifo before enabling the first stream
 746                  */
 747                 if (!stream->link->link_status.link_active &&
 748                         memcmp(stream->link->dpcd_caps.branch_dev_name,
 749                                 (int8_t *)SYNAPTICS_DEVICE_ID, 4) == 0)
 750                         apply_synaptics_fifo_reset_wa(aux);
 751
 752                 ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1);
 753                 DRM_INFO("Send DSC enable to synaptics\n");
 754
 755         } else {
 756                 /* Synaptics hub not support virtual dpcd,
 757                  * external monitor occur garbage while disable DSC,
 758                  * Disable DSC only when entire link status turn to false,
 759                  */
 760                 if (!stream->link->link_status.link_active) {
 761                         ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1);
 762                         DRM_INFO("Send DSC disable to synaptics\n");
 763                 }
 764         }
 765
 766         return ret;
 767 }
 768
 769 bool dm_helpers_dp_write_dsc_enable(
 770                 struct dc_context *ctx,
 771                 const struct dc_stream_state *stream,
 772                 bool enable)
 773 {
 774         static const uint8_t DSC_DISABLE;
 775         static const uint8_t DSC_DECODING = 0x01;
 776         static const uint8_t DSC_PASSTHROUGH = 0x02;
 777
 778         struct amdgpu_dm_connector *aconnector;
 779         struct drm_dp_mst_port *port;
 780         uint8_t enable_dsc = enable ? DSC_DECODING : DSC_DISABLE;
 781         uint8_t enable_passthrough = enable ? DSC_PASSTHROUGH : DSC_DISABLE;
 782         uint8_t ret = 0;
 783
 784         if (!stream)
 785                 return false;
 786
 787         if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
 788                 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 789
 790                 if (!aconnector->dsc_aux)
 791                         return false;
 792
 793                 // apply w/a to synaptics
 794                 if (needs_dsc_aux_workaround(aconnector->dc_link) &&
 795                     (aconnector->mst_downstream_port_present.byte & 0x7) != 0x3)
 796                         return write_dsc_enable_synaptics_non_virtual_dpcd_mst(
 797                                 aconnector->dsc_aux, stream, enable_dsc);
 798
 799                 port = aconnector->mst_output_port;
 800
 801                 if (enable) {
 802                         if (port->passthrough_aux) {
 803                                 ret = drm_dp_dpcd_write(port->passthrough_aux,
 804                                                         DP_DSC_ENABLE,
 805                                                         &enable_passthrough, 1);
 806                                 DC_LOG_DC("Sent DSC pass-through enable to virtual dpcd port, ret = %u\n",
 807                                           ret);
 808                         }
 809
 810                         ret = drm_dp_dpcd_write(aconnector->dsc_aux,
 811                                                 DP_DSC_ENABLE, &enable_dsc, 1);
 812                         DC_LOG_DC("Sent DSC decoding enable to %s port, ret = %u\n",
 813                                   (port->passthrough_aux) ? "remote RX" :
 814                                   "virtual dpcd",
 815                                   ret);
 816                 } else {
 817                         ret = drm_dp_dpcd_write(aconnector->dsc_aux,
 818                                                 DP_DSC_ENABLE, &enable_dsc, 1);
 819                         DC_LOG_DC("Sent DSC decoding disable to %s port, ret = %u\n",
 820                                   (port->passthrough_aux) ? "remote RX" :
 821                                   "virtual dpcd",
 822                                   ret);
 823
 824                         if (port->passthrough_aux) {
 825                                 ret = drm_dp_dpcd_write(port->passthrough_aux,
 826                                                         DP_DSC_ENABLE,
 827                                                         &enable_passthrough, 1);
 828                                 DC_LOG_DC("Sent DSC pass-through disable to virtual dpcd port, ret = %u\n",
 829                                           ret);
 830                         }
 831                 }
 832         }
 833
 834         if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || stream->signal == SIGNAL_TYPE_EDP) {
 835                 if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
 836                         ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1);
 837                         DC_LOG_DC("Send DSC %s to SST RX\n", enable_dsc ? "enable" : "disable");
 838                 } else if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
 839                         ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1);
 840                         DC_LOG_DC("Send DSC %s to DP-HDMI PCON\n", enable_dsc ? "enable" : "disable");
 841                 }
 842         }
 843
 844         return ret;
 845 }
 846
 847 bool dm_helpers_is_dp_sink_present(struct dc_link *link)
 848 {
 849         bool dp_sink_present;
 850         struct amdgpu_dm_connector *aconnector = link->priv;
 851
 852         if (!aconnector) {
 853                 BUG_ON("Failed to find connector for link!");
 854                 return true;
 855         }
 856
 857         mutex_lock(&aconnector->dm_dp_aux.aux.hw_mutex);
 858         dp_sink_present = dc_link_is_dp_sink_present(link);
 859         mutex_unlock(&aconnector->dm_dp_aux.aux.hw_mutex);
 860         return dp_sink_present;
 861 }
 862
 863 enum dc_edid_status dm_helpers_read_local_edid(
 864                 struct dc_context *ctx,
 865                 struct dc_link *link,
 866                 struct dc_sink *sink)
 867 {
 868         struct amdgpu_dm_connector *aconnector = link->priv;
 869         struct drm_connector *connector = &aconnector->base;
 870         struct i2c_adapter *ddc;
 871         int retry = 3;
 872         enum dc_edid_status edid_status;
 873         struct edid *edid;
 874
 875         if (link->aux_mode)
 876                 ddc = &aconnector->dm_dp_aux.aux.ddc;
 877         else
 878                 ddc = &aconnector->i2c->base;
 879
 880         /* some dongles read edid incorrectly the first time,
 881          * do check sum and retry to make sure read correct edid.
 882          */
 883         do {
 884
 885                 edid = drm_get_edid(&aconnector->base, ddc);
 886
 887                 /* DP Compliance Test 4.2.2.6 */
 888                 if (link->aux_mode && connector->edid_corrupt)
 889                         drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux, connector->real_edid_checksum);
 890
 891                 if (!edid && connector->edid_corrupt) {
 892                         connector->edid_corrupt = false;
 893                         return EDID_BAD_CHECKSUM;
 894                 }
 895
 896                 if (!edid)
 897                         return EDID_NO_RESPONSE;
 898
 899                 sink->dc_edid.length = EDID_LENGTH * (edid->extensions + 1);
 900                 memmove(sink->dc_edid.raw_edid, (uint8_t *)edid, sink->dc_edid.length);
 901
 902                 /* We don't need the original edid anymore */
 903                 kfree(edid);
 904
 905                 edid_status = dm_helpers_parse_edid_caps(
 906                                                 link,
 907                                                 &sink->dc_edid,
 908                                                 &sink->edid_caps);
 909
 910         } while (edid_status == EDID_BAD_CHECKSUM && --retry > 0);
 911
 912         if (edid_status != EDID_OK)
 913                 DRM_ERROR("EDID err: %d, on connector: %s",
 914                                 edid_status,
 915                                 aconnector->base.name);
 916         if (link->aux_mode) {
 917                 union test_request test_request = {0};
 918                 union test_response test_response = {0};
 919
 920                 dm_helpers_dp_read_dpcd(ctx,
 921                                         link,
 922                                         DP_TEST_REQUEST,
 923                                         &test_request.raw,
 924                                         sizeof(union test_request));
 925
 926                 if (!test_request.bits.EDID_READ)
 927                         return edid_status;
 928
 929                 test_response.bits.EDID_CHECKSUM_WRITE = 1;
 930
 931                 dm_helpers_dp_write_dpcd(ctx,
 932                                         link,
 933                                         DP_TEST_EDID_CHECKSUM,
 934                                         &sink->dc_edid.raw_edid[sink->dc_edid.length-1],
 935                                         1);
 936
 937                 dm_helpers_dp_write_dpcd(ctx,
 938                                         link,
 939                                         DP_TEST_RESPONSE,
 940                                         &test_response.raw,
 941                                         sizeof(test_response));
 942
 943         }
 944
 945         return edid_status;
 946 }
 947 int dm_helper_dmub_aux_transfer_sync(
 948                 struct dc_context *ctx,
 949                 const struct dc_link *link,
 950                 struct aux_payload *payload,
 951                 enum aux_return_code_type *operation_result)
 952 {
 953         return amdgpu_dm_process_dmub_aux_transfer_sync(ctx, link->link_index, payload,
 954                         operation_result);
 955 }
 956
 957 int dm_helpers_dmub_set_config_sync(struct dc_context *ctx,
 958                 const struct dc_link *link,
 959                 struct set_config_cmd_payload *payload,
 960                 enum set_config_status *operation_result)
 961 {
 962         return amdgpu_dm_process_dmub_set_config_sync(ctx, link->link_index, payload,
 963                         operation_result);
 964 }
 965
 966 void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks)
 967 {
 968         /* TODO: something */
 969 }
 970
 971 void dm_helpers_smu_timeout(struct dc_context *ctx, unsigned int msg_id, unsigned int param, unsigned int timeout_us)
 972 {
 973         // TODO:
 974         //amdgpu_device_gpu_recover(dc_context->driver-context, NULL);
 975 }
 976
 977 void dm_helpers_init_panel_settings(
 978         struct dc_context *ctx,
 979         struct dc_panel_config *panel_config,
 980         struct dc_sink *sink)
 981 {
 982         // Extra Panel Power Sequence
 983         panel_config->pps.extra_t3_ms = sink->edid_caps.panel_patch.extra_t3_ms;
 984         panel_config->pps.extra_t7_ms = sink->edid_caps.panel_patch.extra_t7_ms;
 985         panel_config->pps.extra_delay_backlight_off = sink->edid_caps.panel_patch.extra_delay_backlight_off;
 986         panel_config->pps.extra_post_t7_ms = 0;
 987         panel_config->pps.extra_pre_t11_ms = 0;
 988         panel_config->pps.extra_t12_ms = sink->edid_caps.panel_patch.extra_t12_ms;
 989         panel_config->pps.extra_post_OUI_ms = 0;
 990         // Feature DSC
 991         panel_config->dsc.disable_dsc_edp = false;
 992         panel_config->dsc.force_dsc_edp_policy = 0;
 993 }
 994
 995 void dm_helpers_override_panel_settings(
 996         struct dc_context *ctx,
 997         struct dc_panel_config *panel_config)
 998 {
 999         // Feature DSC
1000         if (amdgpu_dc_debug_mask & DC_DISABLE_DSC)
1001                 panel_config->dsc.disable_dsc_edp = true;
1002 }
1003
1004 void *dm_helpers_allocate_gpu_mem(
1005                 struct dc_context *ctx,
1006                 enum dc_gpu_mem_alloc_type type,
1007                 size_t size,
1008                 long long *addr)
1009 {
1010         struct amdgpu_device *adev = ctx->driver_context;
1011         struct dal_allocation *da;
1012         u32 domain = (type == DC_MEM_ALLOC_TYPE_GART) ?
1013                 AMDGPU_GEM_DOMAIN_GTT : AMDGPU_GEM_DOMAIN_VRAM;
1014         int ret;
1015
1016         da = kzalloc(sizeof(struct dal_allocation), GFP_KERNEL);
1017         if (!da)
1018                 return NULL;
1019
1020         ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
1021                                       domain, &da->bo,
1022                                       &da->gpu_addr, &da->cpu_ptr);
1023
1024         *addr = da->gpu_addr;
1025
1026         if (ret) {
1027                 kfree(da);
1028                 return NULL;
1029         }
1030
1031         /* add da to list in dm */
1032         list_add(&da->list, &adev->dm.da_list);
1033
1034         return da->cpu_ptr;
1035 }
1036
1037 void dm_helpers_free_gpu_mem(
1038                 struct dc_context *ctx,
1039                 enum dc_gpu_mem_alloc_type type,
1040                 void *pvMem)
1041 {
1042         struct amdgpu_device *adev = ctx->driver_context;
1043         struct dal_allocation *da;
1044
1045         /* walk the da list in DM */
1046         list_for_each_entry(da, &adev->dm.da_list, list) {
1047                 if (pvMem == da->cpu_ptr) {
1048                         amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr);
1049                         list_del(&da->list);
1050                         kfree(da);
1051                         break;
1052                 }
1053         }
1054 }
1055
1056 bool dm_helpers_dmub_outbox_interrupt_control(struct dc_context *ctx, bool enable)
1057 {
1058         enum dc_irq_source irq_source;
1059         bool ret;
1060
1061         irq_source = DC_IRQ_SOURCE_DMCUB_OUTBOX;
1062
1063         ret = dc_interrupt_set(ctx->dc, irq_source, enable);
1064
1065         DRM_DEBUG_DRIVER("Dmub trace irq %sabling: r=%d\n",
1066                          enable ? "en" : "dis", ret);
1067         return ret;
1068 }
1069
1070 void dm_helpers_mst_enable_stream_features(const struct dc_stream_state *stream)
1071 {
1072         /* TODO: virtual DPCD */
1073         struct dc_link *link = stream->link;
1074         union down_spread_ctrl old_downspread;
1075         union down_spread_ctrl new_downspread;
1076
1077         if (link->aux_access_disabled)
1078                 return;
1079
1080         if (!dm_helpers_dp_read_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL,
1081                                      &old_downspread.raw,
1082                                      sizeof(old_downspread)))
1083                 return;
1084
1085         new_downspread.raw = old_downspread.raw;
1086         new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
1087                 (stream->ignore_msa_timing_param) ? 1 : 0;
1088
1089         if (new_downspread.raw != old_downspread.raw)
1090                 dm_helpers_dp_write_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL,
1091                                          &new_downspread.raw,
1092                                          sizeof(new_downspread));
1093 }
1094
1095 bool dm_helpers_dp_handle_test_pattern_request(
1096                 struct dc_context *ctx,
1097                 const struct dc_link *link,
1098                 union link_test_pattern dpcd_test_pattern,
1099                 union test_misc dpcd_test_params)
1100 {
1101         enum dp_test_pattern test_pattern;
1102         enum dp_test_pattern_color_space test_pattern_color_space =
1103                         DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED;
1104         enum dc_color_depth requestColorDepth = COLOR_DEPTH_UNDEFINED;
1105         enum dc_pixel_encoding requestPixelEncoding = PIXEL_ENCODING_UNDEFINED;
1106         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
1107         struct pipe_ctx *pipe_ctx = NULL;
1108         struct amdgpu_dm_connector *aconnector = link->priv;
1109         int i;
1110
1111         for (i = 0; i < MAX_PIPES; i++) {
1112                 if (pipes[i].stream == NULL)
1113                         continue;
1114
1115                 if (pipes[i].stream->link == link && !pipes[i].top_pipe &&
1116                         !pipes[i].prev_odm_pipe) {
1117                         pipe_ctx = &pipes[i];
1118                         break;
1119                 }
1120         }
1121
1122         if (pipe_ctx == NULL)
1123                 return false;
1124
1125         switch (dpcd_test_pattern.bits.PATTERN) {
1126         case LINK_TEST_PATTERN_COLOR_RAMP:
1127                 test_pattern = DP_TEST_PATTERN_COLOR_RAMP;
1128         break;
1129         case LINK_TEST_PATTERN_VERTICAL_BARS:
1130                 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;
1131         break; /* black and white */
1132         case LINK_TEST_PATTERN_COLOR_SQUARES:
1133                 test_pattern = (dpcd_test_params.bits.DYN_RANGE ==
1134                                 TEST_DYN_RANGE_VESA ?
1135                                 DP_TEST_PATTERN_COLOR_SQUARES :
1136                                 DP_TEST_PATTERN_COLOR_SQUARES_CEA);
1137         break;
1138         default:
1139                 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
1140         break;
1141         }
1142
1143         if (dpcd_test_params.bits.CLR_FORMAT == 0)
1144                 test_pattern_color_space = DP_TEST_PATTERN_COLOR_SPACE_RGB;
1145         else
1146                 test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ?
1147                                 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 :
1148                                 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601;
1149
1150         switch (dpcd_test_params.bits.BPC) {
1151         case 0: // 6 bits
1152                 requestColorDepth = COLOR_DEPTH_666;
1153                 break;
1154         case 1: // 8 bits
1155                 requestColorDepth = COLOR_DEPTH_888;
1156                 break;
1157         case 2: // 10 bits
1158                 requestColorDepth = COLOR_DEPTH_101010;
1159                 break;
1160         case 3: // 12 bits
1161                 requestColorDepth = COLOR_DEPTH_121212;
1162                 break;
1163         default:
1164                 break;
1165         }
1166
1167         switch (dpcd_test_params.bits.CLR_FORMAT) {
1168         case 0:
1169                 requestPixelEncoding = PIXEL_ENCODING_RGB;
1170                 break;
1171         case 1:
1172                 requestPixelEncoding = PIXEL_ENCODING_YCBCR422;
1173                 break;
1174         case 2:
1175                 requestPixelEncoding = PIXEL_ENCODING_YCBCR444;
1176                 break;
1177         default:
1178                 requestPixelEncoding = PIXEL_ENCODING_RGB;
1179                 break;
1180         }
1181
1182         if ((requestColorDepth != COLOR_DEPTH_UNDEFINED
1183                 && pipe_ctx->stream->timing.display_color_depth != requestColorDepth)
1184                 || (requestPixelEncoding != PIXEL_ENCODING_UNDEFINED
1185                 && pipe_ctx->stream->timing.pixel_encoding != requestPixelEncoding)) {
1186                 DC_LOG_DEBUG("%s: original bpc %d pix encoding %d, changing to %d  %d\n",
1187                                 __func__,
1188                                 pipe_ctx->stream->timing.display_color_depth,
1189                                 pipe_ctx->stream->timing.pixel_encoding,
1190                                 requestColorDepth,
1191                                 requestPixelEncoding);
1192                 pipe_ctx->stream->timing.display_color_depth = requestColorDepth;
1193                 pipe_ctx->stream->timing.pixel_encoding = requestPixelEncoding;
1194
1195                 dc_link_update_dsc_config(pipe_ctx);
1196
1197                 aconnector->timing_changed = true;
1198                 /* store current timing */
1199                 if (aconnector->timing_requested)
1200                         *aconnector->timing_requested = pipe_ctx->stream->timing;
1201                 else
1202                         DC_LOG_ERROR("%s: timing storage failed\n", __func__);
1203
1204         }
1205
1206         dc_link_dp_set_test_pattern(
1207                 (struct dc_link *) link,
1208                 test_pattern,
1209                 test_pattern_color_space,
1210                 NULL,
1211                 NULL,
1212                 0);
1213
1214         return false;
1215 }
1216
1217 void dm_set_phyd32clk(struct dc_context *ctx, int freq_khz)
1218 {
1219        // TODO
1220 }
1221
1222 void dm_helpers_enable_periodic_detection(struct dc_context *ctx, bool enable)
1223 {
1224         /* TODO: add periodic detection implementation */
1225 }
1226
1227 void dm_helpers_dp_mst_update_branch_bandwidth(
1228                 struct dc_context *ctx,
1229                 struct dc_link *link)
1230 {
1231         // TODO
1232 }
1233
1234 static bool dm_is_freesync_pcon_whitelist(const uint32_t branch_dev_id)
1235 {
1236         bool ret_val = false;
1237
1238         switch (branch_dev_id) {
1239         case DP_BRANCH_DEVICE_ID_0060AD:
1240         case DP_BRANCH_DEVICE_ID_00E04C:
1241         case DP_BRANCH_DEVICE_ID_90CC24:
1242                 ret_val = true;
1243                 break;
1244         default:
1245                 break;
1246         }
1247
1248         return ret_val;
1249 }
1250
1251 enum adaptive_sync_type dm_get_adaptive_sync_support_type(struct dc_link *link)
1252 {
1253         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
1254         enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE;
1255
1256         switch (dpcd_caps->dongle_type) {
1257         case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
1258                 if (dpcd_caps->adaptive_sync_caps.dp_adap_sync_caps.bits.ADAPTIVE_SYNC_SDP_SUPPORT == true &&
1259                         dpcd_caps->allow_invalid_MSA_timing_param == true &&
1260                         dm_is_freesync_pcon_whitelist(dpcd_caps->branch_dev_id))
1261                         as_type = FREESYNC_TYPE_PCON_IN_WHITELIST;
1262                 break;
1263         default:
1264                 break;
1265         }
1266
1267         return as_type;
1268 }