drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 /* The caprices of the preprocessor require that this be declared right here */
  27 #define CREATE_TRACE_POINTS
  28
  29 #include "dm_services_types.h"
  30 #include "dc.h"
  31 #include "dc/inc/core_types.h"
  32 #include "dal_asic_id.h"
  33 #include "dmub/dmub_srv.h"
  34 #include "dc/inc/hw/dmcu.h"
  35 #include "dc/inc/hw/abm.h"
  36 #include "dc/dc_dmub_srv.h"
  37 #include "dc/dc_edid_parser.h"
  38 #include "amdgpu_dm_trace.h"
  39
  40 #include "vid.h"
  41 #include "amdgpu.h"
  42 #include "amdgpu_display.h"
  43 #include "amdgpu_ucode.h"
  44 #include "atom.h"
  45 #include "amdgpu_dm.h"
  46 #ifdef CONFIG_DRM_AMD_DC_HDCP
  47 #include "amdgpu_dm_hdcp.h"
  48 #include <drm/drm_hdcp.h>
  49 #endif
  50 #include "amdgpu_pm.h"
  51
  52 #include "amd_shared.h"
  53 #include "amdgpu_dm_irq.h"
  54 #include "dm_helpers.h"
  55 #include "amdgpu_dm_mst_types.h"
  56 #if defined(CONFIG_DEBUG_FS)
  57 #include "amdgpu_dm_debugfs.h"
  58 #endif
  59
  60 #include "ivsrcid/ivsrcid_vislands30.h"
  61
  62 #include <linux/module.h>
  63 #include <linux/moduleparam.h>
  64 #include <linux/types.h>
  65 #include <linux/pm_runtime.h>
  66 #include <linux/pci.h>
  67 #include <linux/firmware.h>
  68 #include <linux/component.h>
  69
  70 #include <drm/drm_atomic.h>
  71 #include <drm/drm_atomic_uapi.h>
  72 #include <drm/drm_atomic_helper.h>
  73 #include <drm/drm_dp_mst_helper.h>
  74 #include <drm/drm_fb_helper.h>
  75 #include <drm/drm_fourcc.h>
  76 #include <drm/drm_edid.h>
  77 #include <drm/drm_vblank.h>
  78 #include <drm/drm_audio_component.h>
  79
  80 #if defined(CONFIG_DRM_AMD_DC_DCN)
  81 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
  82
  83 #include "dcn/dcn_1_0_offset.h"
  84 #include "dcn/dcn_1_0_sh_mask.h"
  85 #include "soc15_hw_ip.h"
  86 #include "vega10_ip_offset.h"
  87
  88 #include "soc15_common.h"
  89 #endif
  90
  91 #include "modules/inc/mod_freesync.h"
  92 #include "modules/power/power_helpers.h"
  93 #include "modules/inc/mod_info_packet.h"
  94
  95 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
  96 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
  97 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"
  98 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
  99 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
 100 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
 101 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
 102 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
 103 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
 104 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
 105 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"
 106 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
 107
 108 #define FIRMWARE_RAVEN_DMCU             "amdgpu/raven_dmcu.bin"
 109 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
 110
 111 #define FIRMWARE_NAVI12_DMCU            "amdgpu/navi12_dmcu.bin"
 112 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);
 113
 114 /* Number of bytes in PSP header for firmware. */
 115 #define PSP_HEADER_BYTES 0x100
 116
 117 /* Number of bytes in PSP footer for firmware. */
 118 #define PSP_FOOTER_BYTES 0x100
 119
 120 /**
 121  * DOC: overview
 122  *
 123  * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
 124  * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM
 125  * requests into DC requests, and DC responses into DRM responses.
 126  *
 127  * The root control structure is &struct amdgpu_display_manager.
 128  */
 129
 130 /* basic init/fini API */
 131 static int amdgpu_dm_init(struct amdgpu_device *adev);
 132 static void amdgpu_dm_fini(struct amdgpu_device *adev);
 133 static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector);
 134
 135 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)
 136 {
 137         switch (link->dpcd_caps.dongle_type) {
 138         case DISPLAY_DONGLE_NONE:
 139                 return DRM_MODE_SUBCONNECTOR_Native;
 140         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
 141                 return DRM_MODE_SUBCONNECTOR_VGA;
 142         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
 143         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 144                 return DRM_MODE_SUBCONNECTOR_DVID;
 145         case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
 146         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 147                 return DRM_MODE_SUBCONNECTOR_HDMIA;
 148         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 149         default:
 150                 return DRM_MODE_SUBCONNECTOR_Unknown;
 151         }
 152 }
 153
 154 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector)
 155 {
 156         struct dc_link *link = aconnector->dc_link;
 157         struct drm_connector *connector = &aconnector->base;
 158         enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
 159
 160         if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
 161                 return;
 162
 163         if (aconnector->dc_sink)
 164                 subconnector = get_subconnector_type(link);
 165
 166         drm_object_property_set_value(&connector->base,
 167                         connector->dev->mode_config.dp_subconnector_property,
 168                         subconnector);
 169 }
 170
 171 /*
 172  * initializes drm_device display related structures, based on the information
 173  * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
 174  * drm_encoder, drm_mode_config
 175  *
 176  * Returns 0 on success
 177  */
 178 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
 179 /* removes and deallocates the drm structures, created by the above function */
 180 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
 181
 182 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
 183                                 struct drm_plane *plane,
 184                                 unsigned long possible_crtcs,
 185                                 const struct dc_plane_cap *plane_cap);
 186 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
 187                                struct drm_plane *plane,
 188                                uint32_t link_index);
 189 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
 190                                     struct amdgpu_dm_connector *amdgpu_dm_connector,
 191                                     uint32_t link_index,
 192                                     struct amdgpu_encoder *amdgpu_encoder);
 193 static int amdgpu_dm_encoder_init(struct drm_device *dev,
 194                                   struct amdgpu_encoder *aencoder,
 195                                   uint32_t link_index);
 196
 197 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
 198
 199 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
 200
 201 static int amdgpu_dm_atomic_check(struct drm_device *dev,
 202                                   struct drm_atomic_state *state);
 203
 204 static void handle_cursor_update(struct drm_plane *plane,
 205                                  struct drm_plane_state *old_plane_state);
 206
 207 static void amdgpu_dm_set_psr_caps(struct dc_link *link);
 208 static bool amdgpu_dm_psr_enable(struct dc_stream_state *stream);
 209 static bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream);
 210 static bool amdgpu_dm_psr_disable(struct dc_stream_state *stream);
 211 static bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm);
 212
 213 static const struct drm_format_info *
 214 amd_get_format_info(const struct drm_mode_fb_cmd2 *cmd);
 215
 216 static bool
 217 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
 218                                  struct drm_crtc_state *new_crtc_state);
 219 /*
 220  * dm_vblank_get_counter
 221  *
 222  * @brief
 223  * Get counter for number of vertical blanks
 224  *
 225  * @param
 226  * struct amdgpu_device *adev - [in] desired amdgpu device
 227  * int disp_idx - [in] which CRTC to get the counter from
 228  *
 229  * @return
 230  * Counter for vertical blanks
 231  */
 232 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 233 {
 234         if (crtc >= adev->mode_info.num_crtc)
 235                 return 0;
 236         else {
 237                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 238
 239                 if (acrtc->dm_irq_params.stream == NULL) {
 240                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 241                                   crtc);
 242                         return 0;
 243                 }
 244
 245                 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);
 246         }
 247 }
 248
 249 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 250                                   u32 *vbl, u32 *position)
 251 {
 252         uint32_t v_blank_start, v_blank_end, h_position, v_position;
 253
 254         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 255                 return -EINVAL;
 256         else {
 257                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 258
 259                 if (acrtc->dm_irq_params.stream ==  NULL) {
 260                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 261                                   crtc);
 262                         return 0;
 263                 }
 264
 265                 /*
 266                  * TODO rework base driver to use values directly.
 267                  * for now parse it back into reg-format
 268                  */
 269                 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream,
 270                                          &v_blank_start,
 271                                          &v_blank_end,
 272                                          &h_position,
 273                                          &v_position);
 274
 275                 *position = v_position | (h_position << 16);
 276                 *vbl = v_blank_start | (v_blank_end << 16);
 277         }
 278
 279         return 0;
 280 }
 281
 282 static bool dm_is_idle(void *handle)
 283 {
 284         /* XXX todo */
 285         return true;
 286 }
 287
 288 static int dm_wait_for_idle(void *handle)
 289 {
 290         /* XXX todo */
 291         return 0;
 292 }
 293
 294 static bool dm_check_soft_reset(void *handle)
 295 {
 296         return false;
 297 }
 298
 299 static int dm_soft_reset(void *handle)
 300 {
 301         /* XXX todo */
 302         return 0;
 303 }
 304
 305 static struct amdgpu_crtc *
 306 get_crtc_by_otg_inst(struct amdgpu_device *adev,
 307                      int otg_inst)
 308 {
 309         struct drm_device *dev = adev_to_drm(adev);
 310         struct drm_crtc *crtc;
 311         struct amdgpu_crtc *amdgpu_crtc;
 312
 313         if (otg_inst == -1) {
 314                 WARN_ON(1);
 315                 return adev->mode_info.crtcs[0];
 316         }
 317
 318         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 319                 amdgpu_crtc = to_amdgpu_crtc(crtc);
 320
 321                 if (amdgpu_crtc->otg_inst == otg_inst)
 322                         return amdgpu_crtc;
 323         }
 324
 325         return NULL;
 326 }
 327
 328 static inline bool amdgpu_dm_vrr_active_irq(struct amdgpu_crtc *acrtc)
 329 {
 330         return acrtc->dm_irq_params.freesync_config.state ==
 331                        VRR_STATE_ACTIVE_VARIABLE ||
 332                acrtc->dm_irq_params.freesync_config.state ==
 333                        VRR_STATE_ACTIVE_FIXED;
 334 }
 335
 336 static inline bool amdgpu_dm_vrr_active(struct dm_crtc_state *dm_state)
 337 {
 338         return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE ||
 339                dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
 340 }
 341
 342 static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,
 343                                               struct dm_crtc_state *new_state)
 344 {
 345         if (new_state->freesync_config.state ==  VRR_STATE_ACTIVE_FIXED)
 346                 return true;
 347         else if (amdgpu_dm_vrr_active(old_state) != amdgpu_dm_vrr_active(new_state))
 348                 return true;
 349         else
 350                 return false;
 351 }
 352
 353 /**
 354  * dm_pflip_high_irq() - Handle pageflip interrupt
 355  * @interrupt_params: ignored
 356  *
 357  * Handles the pageflip interrupt by notifying all interested parties
 358  * that the pageflip has been completed.
 359  */
 360 static void dm_pflip_high_irq(void *interrupt_params)
 361 {
 362         struct amdgpu_crtc *amdgpu_crtc;
 363         struct common_irq_params *irq_params = interrupt_params;
 364         struct amdgpu_device *adev = irq_params->adev;
 365         unsigned long flags;
 366         struct drm_pending_vblank_event *e;
 367         uint32_t vpos, hpos, v_blank_start, v_blank_end;
 368         bool vrr_active;
 369
 370         amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
 371
 372         /* IRQ could occur when in initial stage */
 373         /* TODO work and BO cleanup */
 374         if (amdgpu_crtc == NULL) {
 375                 DC_LOG_PFLIP("CRTC is null, returning.\n");
 376                 return;
 377         }
 378
 379         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 380
 381         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
 382                 DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
 383                                                  amdgpu_crtc->pflip_status,
 384                                                  AMDGPU_FLIP_SUBMITTED,
 385                                                  amdgpu_crtc->crtc_id,
 386                                                  amdgpu_crtc);
 387                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 388                 return;
 389         }
 390
 391         /* page flip completed. */
 392         e = amdgpu_crtc->event;
 393         amdgpu_crtc->event = NULL;
 394
 395         if (!e)
 396                 WARN_ON(1);
 397
 398         vrr_active = amdgpu_dm_vrr_active_irq(amdgpu_crtc);
 399
 400         /* Fixed refresh rate, or VRR scanout position outside front-porch? */
 401         if (!vrr_active ||
 402             !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start,
 403                                       &v_blank_end, &hpos, &vpos) ||
 404             (vpos < v_blank_start)) {
 405                 /* Update to correct count and vblank timestamp if racing with
 406                  * vblank irq. This also updates to the correct vblank timestamp
 407                  * even in VRR mode, as scanout is past the front-porch atm.
 408                  */
 409                 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
 410
 411                 /* Wake up userspace by sending the pageflip event with proper
 412                  * count and timestamp of vblank of flip completion.
 413                  */
 414                 if (e) {
 415                         drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
 416
 417                         /* Event sent, so done with vblank for this flip */
 418                         drm_crtc_vblank_put(&amdgpu_crtc->base);
 419                 }
 420         } else if (e) {
 421                 /* VRR active and inside front-porch: vblank count and
 422                  * timestamp for pageflip event will only be up to date after
 423                  * drm_crtc_handle_vblank() has been executed from late vblank
 424                  * irq handler after start of back-porch (vline 0). We queue the
 425                  * pageflip event for send-out by drm_crtc_handle_vblank() with
 426                  * updated timestamp and count, once it runs after us.
 427                  *
 428                  * We need to open-code this instead of using the helper
 429                  * drm_crtc_arm_vblank_event(), as that helper would
 430                  * call drm_crtc_accurate_vblank_count(), which we must
 431                  * not call in VRR mode while we are in front-porch!
 432                  */
 433
 434                 /* sequence will be replaced by real count during send-out. */
 435                 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
 436                 e->pipe = amdgpu_crtc->crtc_id;
 437
 438                 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list);
 439                 e = NULL;
 440         }
 441
 442         /* Keep track of vblank of this flip for flip throttling. We use the
 443          * cooked hw counter, as that one incremented at start of this vblank
 444          * of pageflip completion, so last_flip_vblank is the forbidden count
 445          * for queueing new pageflips if vsync + VRR is enabled.
 446          */
 447         amdgpu_crtc->dm_irq_params.last_flip_vblank =
 448                 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base);
 449
 450         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
 451         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 452
 453         DC_LOG_PFLIP("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
 454                      amdgpu_crtc->crtc_id, amdgpu_crtc,
 455                      vrr_active, (int) !e);
 456 }
 457
 458 static void dm_vupdate_high_irq(void *interrupt_params)
 459 {
 460         struct common_irq_params *irq_params = interrupt_params;
 461         struct amdgpu_device *adev = irq_params->adev;
 462         struct amdgpu_crtc *acrtc;
 463         struct drm_device *drm_dev;
 464         struct drm_vblank_crtc *vblank;
 465         ktime_t frame_duration_ns, previous_timestamp;
 466         unsigned long flags;
 467         int vrr_active;
 468
 469         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
 470
 471         if (acrtc) {
 472                 vrr_active = amdgpu_dm_vrr_active_irq(acrtc);
 473                 drm_dev = acrtc->base.dev;
 474                 vblank = &drm_dev->vblank[acrtc->base.index];
 475                 previous_timestamp = atomic64_read(&irq_params->previous_timestamp);
 476                 frame_duration_ns = vblank->time - previous_timestamp;
 477
 478                 if (frame_duration_ns > 0) {
 479                         trace_amdgpu_refresh_rate_track(acrtc->base.index,
 480                                                 frame_duration_ns,
 481                                                 ktime_divns(NSEC_PER_SEC, frame_duration_ns));
 482                         atomic64_set(&irq_params->previous_timestamp, vblank->time);
 483                 }
 484
 485                 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d\n",
 486                               acrtc->crtc_id,
 487                               vrr_active);
 488
 489                 /* Core vblank handling is done here after end of front-porch in
 490                  * vrr mode, as vblank timestamping will give valid results
 491                  * while now done after front-porch. This will also deliver
 492                  * page-flip completion events that have been queued to us
 493                  * if a pageflip happened inside front-porch.
 494                  */
 495                 if (vrr_active) {
 496                         drm_crtc_handle_vblank(&acrtc->base);
 497
 498                         /* BTR processing for pre-DCE12 ASICs */
 499                         if (acrtc->dm_irq_params.stream &&
 500                             adev->family < AMDGPU_FAMILY_AI) {
 501                                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 502                                 mod_freesync_handle_v_update(
 503                                     adev->dm.freesync_module,
 504                                     acrtc->dm_irq_params.stream,
 505                                     &acrtc->dm_irq_params.vrr_params);
 506
 507                                 dc_stream_adjust_vmin_vmax(
 508                                     adev->dm.dc,
 509                                     acrtc->dm_irq_params.stream,
 510                                     &acrtc->dm_irq_params.vrr_params.adjust);
 511                                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 512                         }
 513                 }
 514         }
 515 }
 516
 517 /**
 518  * dm_crtc_high_irq() - Handles CRTC interrupt
 519  * @interrupt_params: used for determining the CRTC instance
 520  *
 521  * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
 522  * event handler.
 523  */
 524 static void dm_crtc_high_irq(void *interrupt_params)
 525 {
 526         struct common_irq_params *irq_params = interrupt_params;
 527         struct amdgpu_device *adev = irq_params->adev;
 528         struct amdgpu_crtc *acrtc;
 529         unsigned long flags;
 530         int vrr_active;
 531
 532         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
 533         if (!acrtc)
 534                 return;
 535
 536         vrr_active = amdgpu_dm_vrr_active_irq(acrtc);
 537
 538         DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,
 539                       vrr_active, acrtc->dm_irq_params.active_planes);
 540
 541         /**
 542          * Core vblank handling at start of front-porch is only possible
 543          * in non-vrr mode, as only there vblank timestamping will give
 544          * valid results while done in front-porch. Otherwise defer it
 545          * to dm_vupdate_high_irq after end of front-porch.
 546          */
 547         if (!vrr_active)
 548                 drm_crtc_handle_vblank(&acrtc->base);
 549
 550         /**
 551          * Following stuff must happen at start of vblank, for crc
 552          * computation and below-the-range btr support in vrr mode.
 553          */
 554         amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
 555
 556         /* BTR updates need to happen before VUPDATE on Vega and above. */
 557         if (adev->family < AMDGPU_FAMILY_AI)
 558                 return;
 559
 560         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 561
 562         if (acrtc->dm_irq_params.stream &&
 563             acrtc->dm_irq_params.vrr_params.supported &&
 564             acrtc->dm_irq_params.freesync_config.state ==
 565                     VRR_STATE_ACTIVE_VARIABLE) {
 566                 mod_freesync_handle_v_update(adev->dm.freesync_module,
 567                                              acrtc->dm_irq_params.stream,
 568                                              &acrtc->dm_irq_params.vrr_params);
 569
 570                 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,
 571                                            &acrtc->dm_irq_params.vrr_params.adjust);
 572         }
 573
 574         /*
 575          * If there aren't any active_planes then DCH HUBP may be clock-gated.
 576          * In that case, pageflip completion interrupts won't fire and pageflip
 577          * completion events won't get delivered. Prevent this by sending
 578          * pending pageflip events from here if a flip is still pending.
 579          *
 580          * If any planes are enabled, use dm_pflip_high_irq() instead, to
 581          * avoid race conditions between flip programming and completion,
 582          * which could cause too early flip completion events.
 583          */
 584         if (adev->family >= AMDGPU_FAMILY_RV &&
 585             acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
 586             acrtc->dm_irq_params.active_planes == 0) {
 587                 if (acrtc->event) {
 588                         drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
 589                         acrtc->event = NULL;
 590                         drm_crtc_vblank_put(&acrtc->base);
 591                 }
 592                 acrtc->pflip_status = AMDGPU_FLIP_NONE;
 593         }
 594
 595         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 596 }
 597
 598 #if defined(CONFIG_DRM_AMD_DC_DCN)
 599 /**
 600  * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for
 601  * DCN generation ASICs
 602  * @interrupt params - interrupt parameters
 603  *
 604  * Used to set crc window/read out crc value at vertical line 0 position
 605  */
 606 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
 607 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)
 608 {
 609         struct common_irq_params *irq_params = interrupt_params;
 610         struct amdgpu_device *adev = irq_params->adev;
 611         struct amdgpu_crtc *acrtc;
 612
 613         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0);
 614
 615         if (!acrtc)
 616                 return;
 617
 618         amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base);
 619 }
 620 #endif
 621 #endif
 622
 623 static int dm_set_clockgating_state(void *handle,
 624                   enum amd_clockgating_state state)
 625 {
 626         return 0;
 627 }
 628
 629 static int dm_set_powergating_state(void *handle,
 630                   enum amd_powergating_state state)
 631 {
 632         return 0;
 633 }
 634
 635 /* Prototypes of private functions */
 636 static int dm_early_init(void* handle);
 637
 638 /* Allocate memory for FBC compressed data  */
 639 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
 640 {
 641         struct drm_device *dev = connector->dev;
 642         struct amdgpu_device *adev = drm_to_adev(dev);
 643         struct dm_compressor_info *compressor = &adev->dm.compressor;
 644         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
 645         struct drm_display_mode *mode;
 646         unsigned long max_size = 0;
 647
 648         if (adev->dm.dc->fbc_compressor == NULL)
 649                 return;
 650
 651         if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
 652                 return;
 653
 654         if (compressor->bo_ptr)
 655                 return;
 656
 657
 658         list_for_each_entry(mode, &connector->modes, head) {
 659                 if (max_size < mode->htotal * mode->vtotal)
 660                         max_size = mode->htotal * mode->vtotal;
 661         }
 662
 663         if (max_size) {
 664                 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
 665                             AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
 666                             &compressor->gpu_addr, &compressor->cpu_addr);
 667
 668                 if (r)
 669                         DRM_ERROR("DM: Failed to initialize FBC\n");
 670                 else {
 671                         adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
 672                         DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
 673                 }
 674
 675         }
 676
 677 }
 678
 679 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
 680                                           int pipe, bool *enabled,
 681                                           unsigned char *buf, int max_bytes)
 682 {
 683         struct drm_device *dev = dev_get_drvdata(kdev);
 684         struct amdgpu_device *adev = drm_to_adev(dev);
 685         struct drm_connector *connector;
 686         struct drm_connector_list_iter conn_iter;
 687         struct amdgpu_dm_connector *aconnector;
 688         int ret = 0;
 689
 690         *enabled = false;
 691
 692         mutex_lock(&adev->dm.audio_lock);
 693
 694         drm_connector_list_iter_begin(dev, &conn_iter);
 695         drm_for_each_connector_iter(connector, &conn_iter) {
 696                 aconnector = to_amdgpu_dm_connector(connector);
 697                 if (aconnector->audio_inst != port)
 698                         continue;
 699
 700                 *enabled = true;
 701                 ret = drm_eld_size(connector->eld);
 702                 memcpy(buf, connector->eld, min(max_bytes, ret));
 703
 704                 break;
 705         }
 706         drm_connector_list_iter_end(&conn_iter);
 707
 708         mutex_unlock(&adev->dm.audio_lock);
 709
 710         DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
 711
 712         return ret;
 713 }
 714
 715 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
 716         .get_eld = amdgpu_dm_audio_component_get_eld,
 717 };
 718
 719 static int amdgpu_dm_audio_component_bind(struct device *kdev,
 720                                        struct device *hda_kdev, void *data)
 721 {
 722         struct drm_device *dev = dev_get_drvdata(kdev);
 723         struct amdgpu_device *adev = drm_to_adev(dev);
 724         struct drm_audio_component *acomp = data;
 725
 726         acomp->ops = &amdgpu_dm_audio_component_ops;
 727         acomp->dev = kdev;
 728         adev->dm.audio_component = acomp;
 729
 730         return 0;
 731 }
 732
 733 static void amdgpu_dm_audio_component_unbind(struct device *kdev,
 734                                           struct device *hda_kdev, void *data)
 735 {
 736         struct drm_device *dev = dev_get_drvdata(kdev);
 737         struct amdgpu_device *adev = drm_to_adev(dev);
 738         struct drm_audio_component *acomp = data;
 739
 740         acomp->ops = NULL;
 741         acomp->dev = NULL;
 742         adev->dm.audio_component = NULL;
 743 }
 744
 745 static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
 746         .bind   = amdgpu_dm_audio_component_bind,
 747         .unbind = amdgpu_dm_audio_component_unbind,
 748 };
 749
 750 static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
 751 {
 752         int i, ret;
 753
 754         if (!amdgpu_audio)
 755                 return 0;
 756
 757         adev->mode_info.audio.enabled = true;
 758
 759         adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
 760
 761         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
 762                 adev->mode_info.audio.pin[i].channels = -1;
 763                 adev->mode_info.audio.pin[i].rate = -1;
 764                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
 765                 adev->mode_info.audio.pin[i].status_bits = 0;
 766                 adev->mode_info.audio.pin[i].category_code = 0;
 767                 adev->mode_info.audio.pin[i].connected = false;
 768                 adev->mode_info.audio.pin[i].id =
 769                         adev->dm.dc->res_pool->audios[i]->inst;
 770                 adev->mode_info.audio.pin[i].offset = 0;
 771         }
 772
 773         ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
 774         if (ret < 0)
 775                 return ret;
 776
 777         adev->dm.audio_registered = true;
 778
 779         return 0;
 780 }
 781
 782 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
 783 {
 784         if (!amdgpu_audio)
 785                 return;
 786
 787         if (!adev->mode_info.audio.enabled)
 788                 return;
 789
 790         if (adev->dm.audio_registered) {
 791                 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
 792                 adev->dm.audio_registered = false;
 793         }
 794
 795         /* TODO: Disable audio? */
 796
 797         adev->mode_info.audio.enabled = false;
 798 }
 799
 800 static  void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
 801 {
 802         struct drm_audio_component *acomp = adev->dm.audio_component;
 803
 804         if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
 805                 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
 806
 807                 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
 808                                                  pin, -1);
 809         }
 810 }
 811
 812 static int dm_dmub_hw_init(struct amdgpu_device *adev)
 813 {
 814         const struct dmcub_firmware_header_v1_0 *hdr;
 815         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
 816         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
 817         const struct firmware *dmub_fw = adev->dm.dmub_fw;
 818         struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
 819         struct abm *abm = adev->dm.dc->res_pool->abm;
 820         struct dmub_srv_hw_params hw_params;
 821         enum dmub_status status;
 822         const unsigned char *fw_inst_const, *fw_bss_data;
 823         uint32_t i, fw_inst_const_size, fw_bss_data_size;
 824         bool has_hw_support;
 825
 826         if (!dmub_srv)
 827                 /* DMUB isn't supported on the ASIC. */
 828                 return 0;
 829
 830         if (!fb_info) {
 831                 DRM_ERROR("No framebuffer info for DMUB service.\n");
 832                 return -EINVAL;
 833         }
 834
 835         if (!dmub_fw) {
 836                 /* Firmware required for DMUB support. */
 837                 DRM_ERROR("No firmware provided for DMUB.\n");
 838                 return -EINVAL;
 839         }
 840
 841         status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
 842         if (status != DMUB_STATUS_OK) {
 843                 DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
 844                 return -EINVAL;
 845         }
 846
 847         if (!has_hw_support) {
 848                 DRM_INFO("DMUB unsupported on ASIC\n");
 849                 return 0;
 850         }
 851
 852         hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
 853
 854         fw_inst_const = dmub_fw->data +
 855                         le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
 856                         PSP_HEADER_BYTES;
 857
 858         fw_bss_data = dmub_fw->data +
 859                       le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
 860                       le32_to_cpu(hdr->inst_const_bytes);
 861
 862         /* Copy firmware and bios info into FB memory. */
 863         fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
 864                              PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
 865
 866         fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
 867
 868         /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP,
 869          * amdgpu_ucode_init_single_fw will load dmub firmware
 870          * fw_inst_const part to cw0; otherwise, the firmware back door load
 871          * will be done by dm_dmub_hw_init
 872          */
 873         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 874                 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
 875                                 fw_inst_const_size);
 876         }
 877
 878         if (fw_bss_data_size)
 879                 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr,
 880                        fw_bss_data, fw_bss_data_size);
 881
 882         /* Copy firmware bios info into FB memory. */
 883         memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,
 884                adev->bios_size);
 885
 886         /* Reset regions that need to be reset. */
 887         memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,
 888         fb_info->fb[DMUB_WINDOW_4_MAILBOX].size);
 889
 890         memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,
 891                fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size);
 892
 893         memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,
 894                fb_info->fb[DMUB_WINDOW_6_FW_STATE].size);
 895
 896         /* Initialize hardware. */
 897         memset(&hw_params, 0, sizeof(hw_params));
 898         hw_params.fb_base = adev->gmc.fb_start;
 899         hw_params.fb_offset = adev->gmc.aper_base;
 900
 901         /* backdoor load firmware and trigger dmub running */
 902         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 903                 hw_params.load_inst_const = true;
 904
 905         if (dmcu)
 906                 hw_params.psp_version = dmcu->psp_version;
 907
 908         for (i = 0; i < fb_info->num_fb; ++i)
 909                 hw_params.fb[i] = &fb_info->fb[i];
 910
 911         status = dmub_srv_hw_init(dmub_srv, &hw_params);
 912         if (status != DMUB_STATUS_OK) {
 913                 DRM_ERROR("Error initializing DMUB HW: %d\n", status);
 914                 return -EINVAL;
 915         }
 916
 917         /* Wait for firmware load to finish. */
 918         status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
 919         if (status != DMUB_STATUS_OK)
 920                 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
 921
 922         /* Init DMCU and ABM if available. */
 923         if (dmcu && abm) {
 924                 dmcu->funcs->dmcu_init(dmcu);
 925                 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
 926         }
 927
 928         adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
 929         if (!adev->dm.dc->ctx->dmub_srv) {
 930                 DRM_ERROR("Couldn't allocate DC DMUB server!\n");
 931                 return -ENOMEM;
 932         }
 933
 934         DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
 935                  adev->dm.dmcub_fw_version);
 936
 937         return 0;
 938 }
 939
 940 #if defined(CONFIG_DRM_AMD_DC_DCN)
 941 #define DMUB_TRACE_MAX_READ 64
 942 static void dm_dmub_trace_high_irq(void *interrupt_params)
 943 {
 944         struct common_irq_params *irq_params = interrupt_params;
 945         struct amdgpu_device *adev = irq_params->adev;
 946         struct amdgpu_display_manager *dm = &adev->dm;
 947         struct dmcub_trace_buf_entry entry = { 0 };
 948         uint32_t count = 0;
 949
 950         do {
 951                 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {
 952                         trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,
 953                                                         entry.param0, entry.param1);
 954
 955                         DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",
 956                                  entry.trace_code, entry.tick_count, entry.param0, entry.param1);
 957                 } else
 958                         break;
 959
 960                 count++;
 961
 962         } while (count <= DMUB_TRACE_MAX_READ);
 963
 964         ASSERT(count <= DMUB_TRACE_MAX_READ);
 965 }
 966
 967 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
 968 {
 969         uint64_t pt_base;
 970         uint32_t logical_addr_low;
 971         uint32_t logical_addr_high;
 972         uint32_t agp_base, agp_bot, agp_top;
 973         PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;
 974
 975         logical_addr_low  = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
 976         pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
 977
 978         if (adev->apu_flags & AMD_APU_IS_RAVEN2)
 979                 /*
 980                  * Raven2 has a HW issue that it is unable to use the vram which
 981                  * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
 982                  * workaround that increase system aperture high address (add 1)
 983                  * to get rid of the VM fault and hardware hang.
 984                  */
 985                 logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
 986         else
 987                 logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
 988
 989         agp_base = 0;
 990         agp_bot = adev->gmc.agp_start >> 24;
 991         agp_top = adev->gmc.agp_end >> 24;
 992
 993
 994         page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF;
 995         page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12);
 996         page_table_end.high_part = (u32)(adev->gmc.gart_end >> 44) & 0xF;
 997         page_table_end.low_part = (u32)(adev->gmc.gart_end >> 12);
 998         page_table_base.high_part = upper_32_bits(pt_base) & 0xF;
 999         page_table_base.low_part = lower_32_bits(pt_base);
1000
1001         pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
1002         pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18;
1003
1004         pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24 ;
1005         pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24;
1006         pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24;
1007
1008         pa_config->system_aperture.fb_base = adev->gmc.fb_start;
1009         pa_config->system_aperture.fb_offset = adev->gmc.aper_base;
1010         pa_config->system_aperture.fb_top = adev->gmc.fb_end;
1011
1012         pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12;
1013         pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12;
1014         pa_config->gart_config.page_table_base_addr = page_table_base.quad_part;
1015
1016         pa_config->is_hvm_enabled = 0;
1017
1018 }
1019 #endif
1020 #if defined(CONFIG_DRM_AMD_DC_DCN)
1021 static void event_mall_stutter(struct work_struct *work)
1022 {
1023
1024         struct vblank_workqueue *vblank_work = container_of(work, struct vblank_workqueue, mall_work);
1025         struct amdgpu_display_manager *dm = vblank_work->dm;
1026
1027         mutex_lock(&dm->dc_lock);
1028
1029         if (vblank_work->enable)
1030                 dm->active_vblank_irq_count++;
1031         else if(dm->active_vblank_irq_count)
1032                 dm->active_vblank_irq_count--;
1033
1034         dc_allow_idle_optimizations(dm->dc, dm->active_vblank_irq_count == 0);
1035
1036         DRM_DEBUG_KMS("Allow idle optimizations (MALL): %d\n", dm->active_vblank_irq_count == 0);
1037
1038         mutex_unlock(&dm->dc_lock);
1039 }
1040
1041 static struct vblank_workqueue *vblank_create_workqueue(struct amdgpu_device *adev, struct dc *dc)
1042 {
1043
1044         int max_caps = dc->caps.max_links;
1045         struct vblank_workqueue *vblank_work;
1046         int i = 0;
1047
1048         vblank_work = kcalloc(max_caps, sizeof(*vblank_work), GFP_KERNEL);
1049         if (ZERO_OR_NULL_PTR(vblank_work)) {
1050                 kfree(vblank_work);
1051                 return NULL;
1052         }
1053
1054         for (i = 0; i < max_caps; i++)
1055                 INIT_WORK(&vblank_work[i].mall_work, event_mall_stutter);
1056
1057         return vblank_work;
1058 }
1059 #endif
1060 static int amdgpu_dm_init(struct amdgpu_device *adev)
1061 {
1062         struct dc_init_data init_data;
1063 #ifdef CONFIG_DRM_AMD_DC_HDCP
1064         struct dc_callback_init init_params;
1065 #endif
1066         int r;
1067
1068         adev->dm.ddev = adev_to_drm(adev);
1069         adev->dm.adev = adev;
1070
1071         /* Zero all the fields */
1072         memset(&init_data, 0, sizeof(init_data));
1073 #ifdef CONFIG_DRM_AMD_DC_HDCP
1074         memset(&init_params, 0, sizeof(init_params));
1075 #endif
1076
1077         mutex_init(&adev->dm.dc_lock);
1078         mutex_init(&adev->dm.audio_lock);
1079 #if defined(CONFIG_DRM_AMD_DC_DCN)
1080         spin_lock_init(&adev->dm.vblank_lock);
1081 #endif
1082
1083         if(amdgpu_dm_irq_init(adev)) {
1084                 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
1085                 goto error;
1086         }
1087
1088         init_data.asic_id.chip_family = adev->family;
1089
1090         init_data.asic_id.pci_revision_id = adev->pdev->revision;
1091         init_data.asic_id.hw_internal_rev = adev->external_rev_id;
1092
1093         init_data.asic_id.vram_width = adev->gmc.vram_width;
1094         /* TODO: initialize init_data.asic_id.vram_type here!!!! */
1095         init_data.asic_id.atombios_base_address =
1096                 adev->mode_info.atom_context->bios;
1097
1098         init_data.driver = adev;
1099
1100         adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
1101
1102         if (!adev->dm.cgs_device) {
1103                 DRM_ERROR("amdgpu: failed to create cgs device.\n");
1104                 goto error;
1105         }
1106
1107         init_data.cgs_device = adev->dm.cgs_device;
1108
1109         init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
1110
1111         switch (adev->asic_type) {
1112         case CHIP_CARRIZO:
1113         case CHIP_STONEY:
1114         case CHIP_RAVEN:
1115         case CHIP_RENOIR:
1116                 init_data.flags.gpu_vm_support = true;
1117                 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
1118                         init_data.flags.disable_dmcu = true;
1119                 break;
1120 #if defined(CONFIG_DRM_AMD_DC_DCN)
1121         case CHIP_VANGOGH:
1122                 init_data.flags.gpu_vm_support = true;
1123                 break;
1124 #endif
1125         default:
1126                 break;
1127         }
1128
1129         if (amdgpu_dc_feature_mask & DC_FBC_MASK)
1130                 init_data.flags.fbc_support = true;
1131
1132         if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
1133                 init_data.flags.multi_mon_pp_mclk_switch = true;
1134
1135         if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
1136                 init_data.flags.disable_fractional_pwm = true;
1137
1138         init_data.flags.power_down_display_on_boot = true;
1139
1140         INIT_LIST_HEAD(&adev->dm.da_list);
1141         /* Display Core create. */
1142         adev->dm.dc = dc_create(&init_data);
1143
1144         if (adev->dm.dc) {
1145                 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
1146         } else {
1147                 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
1148                 goto error;
1149         }
1150
1151         if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
1152                 adev->dm.dc->debug.force_single_disp_pipe_split = false;
1153                 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
1154         }
1155
1156         if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
1157                 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
1158
1159         if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
1160                 adev->dm.dc->debug.disable_stutter = true;
1161
1162         if (amdgpu_dc_debug_mask & DC_DISABLE_DSC)
1163                 adev->dm.dc->debug.disable_dsc = true;
1164
1165         if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
1166                 adev->dm.dc->debug.disable_clock_gate = true;
1167
1168         r = dm_dmub_hw_init(adev);
1169         if (r) {
1170                 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
1171                 goto error;
1172         }
1173
1174         dc_hardware_init(adev->dm.dc);
1175
1176 #if defined(CONFIG_DRM_AMD_DC_DCN)
1177         if (adev->apu_flags) {
1178                 struct dc_phy_addr_space_config pa_config;
1179
1180                 mmhub_read_system_context(adev, &pa_config);
1181
1182                 // Call the DC init_memory func
1183                 dc_setup_system_context(adev->dm.dc, &pa_config);
1184         }
1185 #endif
1186
1187         adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
1188         if (!adev->dm.freesync_module) {
1189                 DRM_ERROR(
1190                 "amdgpu: failed to initialize freesync_module.\n");
1191         } else
1192                 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
1193                                 adev->dm.freesync_module);
1194
1195         amdgpu_dm_init_color_mod();
1196
1197 #if defined(CONFIG_DRM_AMD_DC_DCN)
1198         if (adev->dm.dc->caps.max_links > 0) {
1199                 adev->dm.vblank_workqueue = vblank_create_workqueue(adev, adev->dm.dc);
1200
1201                 if (!adev->dm.vblank_workqueue)
1202                         DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n");
1203                 else
1204                         DRM_DEBUG_DRIVER("amdgpu: vblank_workqueue init done %p.\n", adev->dm.vblank_workqueue);
1205         }
1206 #endif
1207
1208 #ifdef CONFIG_DRM_AMD_DC_HDCP
1209         if (adev->dm.dc->caps.max_links > 0 && adev->asic_type >= CHIP_RAVEN) {
1210                 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
1211
1212                 if (!adev->dm.hdcp_workqueue)
1213                         DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
1214                 else
1215                         DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
1216
1217                 dc_init_callbacks(adev->dm.dc, &init_params);
1218         }
1219 #endif
1220 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1221         adev->dm.crc_rd_wrk = amdgpu_dm_crtc_secure_display_create_work();
1222 #endif
1223         if (amdgpu_dm_initialize_drm_device(adev)) {
1224                 DRM_ERROR(
1225                 "amdgpu: failed to initialize sw for display support.\n");
1226                 goto error;
1227         }
1228
1229         /* create fake encoders for MST */
1230         dm_dp_create_fake_mst_encoders(adev);
1231
1232         /* TODO: Add_display_info? */
1233
1234         /* TODO use dynamic cursor width */
1235         adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
1236         adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
1237
1238         if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
1239                 DRM_ERROR(
1240                 "amdgpu: failed to initialize sw for display support.\n");
1241                 goto error;
1242         }
1243
1244
1245         DRM_DEBUG_DRIVER("KMS initialized.\n");
1246
1247         return 0;
1248 error:
1249         amdgpu_dm_fini(adev);
1250
1251         return -EINVAL;
1252 }
1253
1254 static void amdgpu_dm_fini(struct amdgpu_device *adev)
1255 {
1256         int i;
1257
1258         for (i = 0; i < adev->dm.display_indexes_num; i++) {
1259                 drm_encoder_cleanup(&adev->dm.mst_encoders[i].base);
1260         }
1261
1262         amdgpu_dm_audio_fini(adev);
1263
1264         amdgpu_dm_destroy_drm_device(&adev->dm);
1265
1266 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1267         if (adev->dm.crc_rd_wrk) {
1268                 flush_work(&adev->dm.crc_rd_wrk->notify_ta_work);
1269                 kfree(adev->dm.crc_rd_wrk);
1270                 adev->dm.crc_rd_wrk = NULL;
1271         }
1272 #endif
1273 #ifdef CONFIG_DRM_AMD_DC_HDCP
1274         if (adev->dm.hdcp_workqueue) {
1275                 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue);
1276                 adev->dm.hdcp_workqueue = NULL;
1277         }
1278
1279         if (adev->dm.dc)
1280                 dc_deinit_callbacks(adev->dm.dc);
1281 #endif
1282
1283 #if defined(CONFIG_DRM_AMD_DC_DCN)
1284         if (adev->dm.vblank_workqueue) {
1285                 adev->dm.vblank_workqueue->dm = NULL;
1286                 kfree(adev->dm.vblank_workqueue);
1287                 adev->dm.vblank_workqueue = NULL;
1288         }
1289 #endif
1290
1291         if (adev->dm.dc->ctx->dmub_srv) {
1292                 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
1293                 adev->dm.dc->ctx->dmub_srv = NULL;
1294         }
1295
1296         if (adev->dm.dmub_bo)
1297                 amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
1298                                       &adev->dm.dmub_bo_gpu_addr,
1299                                       &adev->dm.dmub_bo_cpu_addr);
1300
1301         /* DC Destroy TODO: Replace destroy DAL */
1302         if (adev->dm.dc)
1303                 dc_destroy(&adev->dm.dc);
1304         /*
1305          * TODO: pageflip, vlank interrupt
1306          *
1307          * amdgpu_dm_irq_fini(adev);
1308          */
1309
1310         if (adev->dm.cgs_device) {
1311                 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
1312                 adev->dm.cgs_device = NULL;
1313         }
1314         if (adev->dm.freesync_module) {
1315                 mod_freesync_destroy(adev->dm.freesync_module);
1316                 adev->dm.freesync_module = NULL;
1317         }
1318
1319         mutex_destroy(&adev->dm.audio_lock);
1320         mutex_destroy(&adev->dm.dc_lock);
1321
1322         return;
1323 }
1324
1325 static int load_dmcu_fw(struct amdgpu_device *adev)
1326 {
1327         const char *fw_name_dmcu = NULL;
1328         int r;
1329         const struct dmcu_firmware_header_v1_0 *hdr;
1330
1331         switch(adev->asic_type) {
1332 #if defined(CONFIG_DRM_AMD_DC_SI)
1333         case CHIP_TAHITI:
1334         case CHIP_PITCAIRN:
1335         case CHIP_VERDE:
1336         case CHIP_OLAND:
1337 #endif
1338         case CHIP_BONAIRE:
1339         case CHIP_HAWAII:
1340         case CHIP_KAVERI:
1341         case CHIP_KABINI:
1342         case CHIP_MULLINS:
1343         case CHIP_TONGA:
1344         case CHIP_FIJI:
1345         case CHIP_CARRIZO:
1346         case CHIP_STONEY:
1347         case CHIP_POLARIS11:
1348         case CHIP_POLARIS10:
1349         case CHIP_POLARIS12:
1350         case CHIP_VEGAM:
1351         case CHIP_VEGA10:
1352         case CHIP_VEGA12:
1353         case CHIP_VEGA20:
1354         case CHIP_NAVI10:
1355         case CHIP_NAVI14:
1356         case CHIP_RENOIR:
1357         case CHIP_SIENNA_CICHLID:
1358         case CHIP_NAVY_FLOUNDER:
1359         case CHIP_DIMGREY_CAVEFISH:
1360         case CHIP_VANGOGH:
1361                 return 0;
1362         case CHIP_NAVI12:
1363                 fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
1364                 break;
1365         case CHIP_RAVEN:
1366                 if (ASICREV_IS_PICASSO(adev->external_rev_id))
1367                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1368                 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
1369                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1370                 else
1371                         return 0;
1372                 break;
1373         default:
1374                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
1375                 return -EINVAL;
1376         }
1377
1378         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1379                 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
1380                 return 0;
1381         }
1382
1383         r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev);
1384         if (r == -ENOENT) {
1385                 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
1386                 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
1387                 adev->dm.fw_dmcu = NULL;
1388                 return 0;
1389         }
1390         if (r) {
1391                 dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n",
1392                         fw_name_dmcu);
1393                 return r;
1394         }
1395
1396         r = amdgpu_ucode_validate(adev->dm.fw_dmcu);
1397         if (r) {
1398                 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
1399                         fw_name_dmcu);
1400                 release_firmware(adev->dm.fw_dmcu);
1401                 adev->dm.fw_dmcu = NULL;
1402                 return r;
1403         }
1404
1405         hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
1406         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
1407         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
1408         adev->firmware.fw_size +=
1409                 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
1410
1411         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
1412         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
1413         adev->firmware.fw_size +=
1414                 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
1415
1416         adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
1417
1418         DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
1419
1420         return 0;
1421 }
1422
1423 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
1424 {
1425         struct amdgpu_device *adev = ctx;
1426
1427         return dm_read_reg(adev->dm.dc->ctx, address);
1428 }
1429
1430 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
1431                                      uint32_t value)
1432 {
1433         struct amdgpu_device *adev = ctx;
1434
1435         return dm_write_reg(adev->dm.dc->ctx, address, value);
1436 }
1437
1438 static int dm_dmub_sw_init(struct amdgpu_device *adev)
1439 {
1440         struct dmub_srv_create_params create_params;
1441         struct dmub_srv_region_params region_params;
1442         struct dmub_srv_region_info region_info;
1443         struct dmub_srv_fb_params fb_params;
1444         struct dmub_srv_fb_info *fb_info;
1445         struct dmub_srv *dmub_srv;
1446         const struct dmcub_firmware_header_v1_0 *hdr;
1447         const char *fw_name_dmub;
1448         enum dmub_asic dmub_asic;
1449         enum dmub_status status;
1450         int r;
1451
1452         switch (adev->asic_type) {
1453         case CHIP_RENOIR:
1454                 dmub_asic = DMUB_ASIC_DCN21;
1455                 fw_name_dmub = FIRMWARE_RENOIR_DMUB;
1456                 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
1457                         fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
1458                 break;
1459         case CHIP_SIENNA_CICHLID:
1460                 dmub_asic = DMUB_ASIC_DCN30;
1461                 fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
1462                 break;
1463         case CHIP_NAVY_FLOUNDER:
1464                 dmub_asic = DMUB_ASIC_DCN30;
1465                 fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
1466                 break;
1467         case CHIP_VANGOGH:
1468                 dmub_asic = DMUB_ASIC_DCN301;
1469                 fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
1470                 break;
1471         case CHIP_DIMGREY_CAVEFISH:
1472                 dmub_asic = DMUB_ASIC_DCN302;
1473                 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
1474                 break;
1475
1476         default:
1477                 /* ASIC doesn't support DMUB. */
1478                 return 0;
1479         }
1480
1481         r = request_firmware_direct(&adev->dm.dmub_fw, fw_name_dmub, adev->dev);
1482         if (r) {
1483                 DRM_ERROR("DMUB firmware loading failed: %d\n", r);
1484                 return 0;
1485         }
1486
1487         r = amdgpu_ucode_validate(adev->dm.dmub_fw);
1488         if (r) {
1489                 DRM_ERROR("Couldn't validate DMUB firmware: %d\n", r);
1490                 return 0;
1491         }
1492
1493         hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
1494
1495         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1496                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
1497                         AMDGPU_UCODE_ID_DMCUB;
1498                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw =
1499                         adev->dm.dmub_fw;
1500                 adev->firmware.fw_size +=
1501                         ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
1502
1503                 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
1504                          adev->dm.dmcub_fw_version);
1505         }
1506
1507         adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
1508
1509         adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
1510         dmub_srv = adev->dm.dmub_srv;
1511
1512         if (!dmub_srv) {
1513                 DRM_ERROR("Failed to allocate DMUB service!\n");
1514                 return -ENOMEM;
1515         }
1516
1517         memset(&create_params, 0, sizeof(create_params));
1518         create_params.user_ctx = adev;
1519         create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
1520         create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
1521         create_params.asic = dmub_asic;
1522
1523         /* Create the DMUB service. */
1524         status = dmub_srv_create(dmub_srv, &create_params);
1525         if (status != DMUB_STATUS_OK) {
1526                 DRM_ERROR("Error creating DMUB service: %d\n", status);
1527                 return -EINVAL;
1528         }
1529
1530         /* Calculate the size of all the regions for the DMUB service. */
1531         memset(&region_params, 0, sizeof(region_params));
1532
1533         region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
1534                                         PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
1535         region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
1536         region_params.vbios_size = adev->bios_size;
1537         region_params.fw_bss_data = region_params.bss_data_size ?
1538                 adev->dm.dmub_fw->data +
1539                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1540                 le32_to_cpu(hdr->inst_const_bytes) : NULL;
1541         region_params.fw_inst_const =
1542                 adev->dm.dmub_fw->data +
1543                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1544                 PSP_HEADER_BYTES;
1545
1546         status = dmub_srv_calc_region_info(dmub_srv, &region_params,
1547                                            &region_info);
1548
1549         if (status != DMUB_STATUS_OK) {
1550                 DRM_ERROR("Error calculating DMUB region info: %d\n", status);
1551                 return -EINVAL;
1552         }
1553
1554         /*
1555          * Allocate a framebuffer based on the total size of all the regions.
1556          * TODO: Move this into GART.
1557          */
1558         r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
1559                                     AMDGPU_GEM_DOMAIN_VRAM, &adev->dm.dmub_bo,
1560                                     &adev->dm.dmub_bo_gpu_addr,
1561                                     &adev->dm.dmub_bo_cpu_addr);
1562         if (r)
1563                 return r;
1564
1565         /* Rebase the regions on the framebuffer address. */
1566         memset(&fb_params, 0, sizeof(fb_params));
1567         fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr;
1568         fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr;
1569         fb_params.region_info = &region_info;
1570
1571         adev->dm.dmub_fb_info =
1572                 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);
1573         fb_info = adev->dm.dmub_fb_info;
1574
1575         if (!fb_info) {
1576                 DRM_ERROR(
1577                         "Failed to allocate framebuffer info for DMUB service!\n");
1578                 return -ENOMEM;
1579         }
1580
1581         status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info);
1582         if (status != DMUB_STATUS_OK) {
1583                 DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
1584                 return -EINVAL;
1585         }
1586
1587         return 0;
1588 }
1589
1590 static int dm_sw_init(void *handle)
1591 {
1592         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1593         int r;
1594
1595         r = dm_dmub_sw_init(adev);
1596         if (r)
1597                 return r;
1598
1599         return load_dmcu_fw(adev);
1600 }
1601
1602 static int dm_sw_fini(void *handle)
1603 {
1604         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1605
1606         kfree(adev->dm.dmub_fb_info);
1607         adev->dm.dmub_fb_info = NULL;
1608
1609         if (adev->dm.dmub_srv) {
1610                 dmub_srv_destroy(adev->dm.dmub_srv);
1611                 adev->dm.dmub_srv = NULL;
1612         }
1613
1614         release_firmware(adev->dm.dmub_fw);
1615         adev->dm.dmub_fw = NULL;
1616
1617         release_firmware(adev->dm.fw_dmcu);
1618         adev->dm.fw_dmcu = NULL;
1619
1620         return 0;
1621 }
1622
1623 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
1624 {
1625         struct amdgpu_dm_connector *aconnector;
1626         struct drm_connector *connector;
1627         struct drm_connector_list_iter iter;
1628         int ret = 0;
1629
1630         drm_connector_list_iter_begin(dev, &iter);
1631         drm_for_each_connector_iter(connector, &iter) {
1632                 aconnector = to_amdgpu_dm_connector(connector);
1633                 if (aconnector->dc_link->type == dc_connection_mst_branch &&
1634                     aconnector->mst_mgr.aux) {
1635                         DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
1636                                          aconnector,
1637                                          aconnector->base.base.id);
1638
1639                         ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
1640                         if (ret < 0) {
1641                                 DRM_ERROR("DM_MST: Failed to start MST\n");
1642                                 aconnector->dc_link->type =
1643                                         dc_connection_single;
1644                                 break;
1645                         }
1646                 }
1647         }
1648         drm_connector_list_iter_end(&iter);
1649
1650         return ret;
1651 }
1652
1653 static int dm_late_init(void *handle)
1654 {
1655         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1656
1657         struct dmcu_iram_parameters params;
1658         unsigned int linear_lut[16];
1659         int i;
1660         struct dmcu *dmcu = NULL;
1661         bool ret = true;
1662
1663         dmcu = adev->dm.dc->res_pool->dmcu;
1664
1665         for (i = 0; i < 16; i++)
1666                 linear_lut[i] = 0xFFFF * i / 15;
1667
1668         params.set = 0;
1669         params.backlight_ramping_start = 0xCCCC;
1670         params.backlight_ramping_reduction = 0xCCCCCCCC;
1671         params.backlight_lut_array_size = 16;
1672         params.backlight_lut_array = linear_lut;
1673
1674         /* Min backlight level after ABM reduction,  Don't allow below 1%
1675          * 0xFFFF x 0.01 = 0x28F
1676          */
1677         params.min_abm_backlight = 0x28F;
1678
1679         /* In the case where abm is implemented on dmcub,
1680          * dmcu object will be null.
1681          * ABM 2.4 and up are implemented on dmcub.
1682          */
1683         if (dmcu)
1684                 ret = dmcu_load_iram(dmcu, params);
1685         else if (adev->dm.dc->ctx->dmub_srv)
1686                 ret = dmub_init_abm_config(adev->dm.dc->res_pool, params);
1687
1688         if (!ret)
1689                 return -EINVAL;
1690
1691         return detect_mst_link_for_all_connectors(adev_to_drm(adev));
1692 }
1693
1694 static void s3_handle_mst(struct drm_device *dev, bool suspend)
1695 {
1696         struct amdgpu_dm_connector *aconnector;
1697         struct drm_connector *connector;
1698         struct drm_connector_list_iter iter;
1699         struct drm_dp_mst_topology_mgr *mgr;
1700         int ret;
1701         bool need_hotplug = false;
1702
1703         drm_connector_list_iter_begin(dev, &iter);
1704         drm_for_each_connector_iter(connector, &iter) {
1705                 aconnector = to_amdgpu_dm_connector(connector);
1706                 if (aconnector->dc_link->type != dc_connection_mst_branch ||
1707                     aconnector->mst_port)
1708                         continue;
1709
1710                 mgr = &aconnector->mst_mgr;
1711
1712                 if (suspend) {
1713                         drm_dp_mst_topology_mgr_suspend(mgr);
1714                 } else {
1715                         ret = drm_dp_mst_topology_mgr_resume(mgr, true);
1716                         if (ret < 0) {
1717                                 drm_dp_mst_topology_mgr_set_mst(mgr, false);
1718                                 need_hotplug = true;
1719                         }
1720                 }
1721         }
1722         drm_connector_list_iter_end(&iter);
1723
1724         if (need_hotplug)
1725                 drm_kms_helper_hotplug_event(dev);
1726 }
1727
1728 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
1729 {
1730         struct smu_context *smu = &adev->smu;
1731         int ret = 0;
1732
1733         if (!is_support_sw_smu(adev))
1734                 return 0;
1735
1736         /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
1737          * on window driver dc implementation.
1738          * For Navi1x, clock settings of dcn watermarks are fixed. the settings
1739          * should be passed to smu during boot up and resume from s3.
1740          * boot up: dc calculate dcn watermark clock settings within dc_create,
1741          * dcn20_resource_construct
1742          * then call pplib functions below to pass the settings to smu:
1743          * smu_set_watermarks_for_clock_ranges
1744          * smu_set_watermarks_table
1745          * navi10_set_watermarks_table
1746          * smu_write_watermarks_table
1747          *
1748          * For Renoir, clock settings of dcn watermark are also fixed values.
1749          * dc has implemented different flow for window driver:
1750          * dc_hardware_init / dc_set_power_state
1751          * dcn10_init_hw
1752          * notify_wm_ranges
1753          * set_wm_ranges
1754          * -- Linux
1755          * smu_set_watermarks_for_clock_ranges
1756          * renoir_set_watermarks_table
1757          * smu_write_watermarks_table
1758          *
1759          * For Linux,
1760          * dc_hardware_init -> amdgpu_dm_init
1761          * dc_set_power_state --> dm_resume
1762          *
1763          * therefore, this function apply to navi10/12/14 but not Renoir
1764          * *
1765          */
1766         switch(adev->asic_type) {
1767         case CHIP_NAVI10:
1768         case CHIP_NAVI14:
1769         case CHIP_NAVI12:
1770                 break;
1771         default:
1772                 return 0;
1773         }
1774
1775         ret = smu_write_watermarks_table(smu);
1776         if (ret) {
1777                 DRM_ERROR("Failed to update WMTABLE!\n");
1778                 return ret;
1779         }
1780
1781         return 0;
1782 }
1783
1784 /**
1785  * dm_hw_init() - Initialize DC device
1786  * @handle: The base driver device containing the amdgpu_dm device.
1787  *
1788  * Initialize the &struct amdgpu_display_manager device. This involves calling
1789  * the initializers of each DM component, then populating the struct with them.
1790  *
1791  * Although the function implies hardware initialization, both hardware and
1792  * software are initialized here. Splitting them out to their relevant init
1793  * hooks is a future TODO item.
1794  *
1795  * Some notable things that are initialized here:
1796  *
1797  * - Display Core, both software and hardware
1798  * - DC modules that we need (freesync and color management)
1799  * - DRM software states
1800  * - Interrupt sources and handlers
1801  * - Vblank support
1802  * - Debug FS entries, if enabled
1803  */
1804 static int dm_hw_init(void *handle)
1805 {
1806         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1807         /* Create DAL display manager */
1808         amdgpu_dm_init(adev);
1809         amdgpu_dm_hpd_init(adev);
1810
1811         return 0;
1812 }
1813
1814 /**
1815  * dm_hw_fini() - Teardown DC device
1816  * @handle: The base driver device containing the amdgpu_dm device.
1817  *
1818  * Teardown components within &struct amdgpu_display_manager that require
1819  * cleanup. This involves cleaning up the DRM device, DC, and any modules that
1820  * were loaded. Also flush IRQ workqueues and disable them.
1821  */
1822 static int dm_hw_fini(void *handle)
1823 {
1824         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1825
1826         amdgpu_dm_hpd_fini(adev);
1827
1828         amdgpu_dm_irq_fini(adev);
1829         amdgpu_dm_fini(adev);
1830         return 0;
1831 }
1832
1833
1834 static int dm_enable_vblank(struct drm_crtc *crtc);
1835 static void dm_disable_vblank(struct drm_crtc *crtc);
1836
1837 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
1838                                  struct dc_state *state, bool enable)
1839 {
1840         enum dc_irq_source irq_source;
1841         struct amdgpu_crtc *acrtc;
1842         int rc = -EBUSY;
1843         int i = 0;
1844
1845         for (i = 0; i < state->stream_count; i++) {
1846                 acrtc = get_crtc_by_otg_inst(
1847                                 adev, state->stream_status[i].primary_otg_inst);
1848
1849                 if (acrtc && state->stream_status[i].plane_count != 0) {
1850                         irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst;
1851                         rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
1852                         DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n",
1853                                       acrtc->crtc_id, enable ? "en" : "dis", rc);
1854                         if (rc)
1855                                 DRM_WARN("Failed to %s pflip interrupts\n",
1856                                          enable ? "enable" : "disable");
1857
1858                         if (enable) {
1859                                 rc = dm_enable_vblank(&acrtc->base);
1860                                 if (rc)
1861                                         DRM_WARN("Failed to enable vblank interrupts\n");
1862                         } else {
1863                                 dm_disable_vblank(&acrtc->base);
1864                         }
1865
1866                 }
1867         }
1868
1869 }
1870
1871 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
1872 {
1873         struct dc_state *context = NULL;
1874         enum dc_status res = DC_ERROR_UNEXPECTED;
1875         int i;
1876         struct dc_stream_state *del_streams[MAX_PIPES];
1877         int del_streams_count = 0;
1878
1879         memset(del_streams, 0, sizeof(del_streams));
1880
1881         context = dc_create_state(dc);
1882         if (context == NULL)
1883                 goto context_alloc_fail;
1884
1885         dc_resource_state_copy_construct_current(dc, context);
1886
1887         /* First remove from context all streams */
1888         for (i = 0; i < context->stream_count; i++) {
1889                 struct dc_stream_state *stream = context->streams[i];
1890
1891                 del_streams[del_streams_count++] = stream;
1892         }
1893
1894         /* Remove all planes for removed streams and then remove the streams */
1895         for (i = 0; i < del_streams_count; i++) {
1896                 if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) {
1897                         res = DC_FAIL_DETACH_SURFACES;
1898                         goto fail;
1899                 }
1900
1901                 res = dc_remove_stream_from_ctx(dc, context, del_streams[i]);
1902                 if (res != DC_OK)
1903                         goto fail;
1904         }
1905
1906
1907         res = dc_validate_global_state(dc, context, false);
1908
1909         if (res != DC_OK) {
1910                 DRM_ERROR("%s:resource validation failed, dc_status:%d\n", __func__, res);
1911                 goto fail;
1912         }
1913
1914         res = dc_commit_state(dc, context);
1915
1916 fail:
1917         dc_release_state(context);
1918
1919 context_alloc_fail:
1920         return res;
1921 }
1922
1923 static int dm_suspend(void *handle)
1924 {
1925         struct amdgpu_device *adev = handle;
1926         struct amdgpu_display_manager *dm = &adev->dm;
1927         int ret = 0;
1928
1929         if (amdgpu_in_reset(adev)) {
1930                 mutex_lock(&dm->dc_lock);
1931
1932 #if defined(CONFIG_DRM_AMD_DC_DCN)
1933                 dc_allow_idle_optimizations(adev->dm.dc, false);
1934 #endif
1935
1936                 dm->cached_dc_state = dc_copy_state(dm->dc->current_state);
1937
1938                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
1939
1940                 amdgpu_dm_commit_zero_streams(dm->dc);
1941
1942                 amdgpu_dm_irq_suspend(adev);
1943
1944                 return ret;
1945         }
1946
1947 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
1948         amdgpu_dm_crtc_secure_display_suspend(adev);
1949 #endif
1950         WARN_ON(adev->dm.cached_state);
1951         adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));
1952
1953         s3_handle_mst(adev_to_drm(adev), true);
1954
1955         amdgpu_dm_irq_suspend(adev);
1956
1957
1958         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
1959
1960         return 0;
1961 }
1962
1963 static struct amdgpu_dm_connector *
1964 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
1965                                              struct drm_crtc *crtc)
1966 {
1967         uint32_t i;
1968         struct drm_connector_state *new_con_state;
1969         struct drm_connector *connector;
1970         struct drm_crtc *crtc_from_state;
1971
1972         for_each_new_connector_in_state(state, connector, new_con_state, i) {
1973                 crtc_from_state = new_con_state->crtc;
1974
1975                 if (crtc_from_state == crtc)
1976                         return to_amdgpu_dm_connector(connector);
1977         }
1978
1979         return NULL;
1980 }
1981
1982 static void emulated_link_detect(struct dc_link *link)
1983 {
1984         struct dc_sink_init_data sink_init_data = { 0 };
1985         struct display_sink_capability sink_caps = { 0 };
1986         enum dc_edid_status edid_status;
1987         struct dc_context *dc_ctx = link->ctx;
1988         struct dc_sink *sink = NULL;
1989         struct dc_sink *prev_sink = NULL;
1990
1991         link->type = dc_connection_none;
1992         prev_sink = link->local_sink;
1993
1994         if (prev_sink)
1995                 dc_sink_release(prev_sink);
1996
1997         switch (link->connector_signal) {
1998         case SIGNAL_TYPE_HDMI_TYPE_A: {
1999                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2000                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
2001                 break;
2002         }
2003
2004         case SIGNAL_TYPE_DVI_SINGLE_LINK: {
2005                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2006                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
2007                 break;
2008         }
2009
2010         case SIGNAL_TYPE_DVI_DUAL_LINK: {
2011                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2012                 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
2013                 break;
2014         }
2015
2016         case SIGNAL_TYPE_LVDS: {
2017                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2018                 sink_caps.signal = SIGNAL_TYPE_LVDS;
2019                 break;
2020         }
2021
2022         case SIGNAL_TYPE_EDP: {
2023                 sink_caps.transaction_type =
2024                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2025                 sink_caps.signal = SIGNAL_TYPE_EDP;
2026                 break;
2027         }
2028
2029         case SIGNAL_TYPE_DISPLAY_PORT: {
2030                 sink_caps.transaction_type =
2031                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2032                 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
2033                 break;
2034         }
2035
2036         default:
2037                 DC_ERROR("Invalid connector type! signal:%d\n",
2038                         link->connector_signal);
2039                 return;
2040         }
2041
2042         sink_init_data.link = link;
2043         sink_init_data.sink_signal = sink_caps.signal;
2044
2045         sink = dc_sink_create(&sink_init_data);
2046         if (!sink) {
2047                 DC_ERROR("Failed to create sink!\n");
2048                 return;
2049         }
2050
2051         /* dc_sink_create returns a new reference */
2052         link->local_sink = sink;
2053
2054         edid_status = dm_helpers_read_local_edid(
2055                         link->ctx,
2056                         link,
2057                         sink);
2058
2059         if (edid_status != EDID_OK)
2060                 DC_ERROR("Failed to read EDID");
2061
2062 }
2063
2064 static void dm_gpureset_commit_state(struct dc_state *dc_state,
2065                                      struct amdgpu_display_manager *dm)
2066 {
2067         struct {
2068                 struct dc_surface_update surface_updates[MAX_SURFACES];
2069                 struct dc_plane_info plane_infos[MAX_SURFACES];
2070                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
2071                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
2072                 struct dc_stream_update stream_update;
2073         } * bundle;
2074         int k, m;
2075
2076         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
2077
2078         if (!bundle) {
2079                 dm_error("Failed to allocate update bundle\n");
2080                 goto cleanup;
2081         }
2082
2083         for (k = 0; k < dc_state->stream_count; k++) {
2084                 bundle->stream_update.stream = dc_state->streams[k];
2085
2086                 for (m = 0; m < dc_state->stream_status->plane_count; m++) {
2087                         bundle->surface_updates[m].surface =
2088                                 dc_state->stream_status->plane_states[m];
2089                         bundle->surface_updates[m].surface->force_full_update =
2090                                 true;
2091                 }
2092                 dc_commit_updates_for_stream(
2093                         dm->dc, bundle->surface_updates,
2094                         dc_state->stream_status->plane_count,
2095                         dc_state->streams[k], &bundle->stream_update, dc_state);
2096         }
2097
2098 cleanup:
2099         kfree(bundle);
2100
2101         return;
2102 }
2103
2104 static void dm_set_dpms_off(struct dc_link *link)
2105 {
2106         struct dc_stream_state *stream_state;
2107         struct amdgpu_dm_connector *aconnector = link->priv;
2108         struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
2109         struct dc_stream_update stream_update;
2110         bool dpms_off = true;
2111
2112         memset(&stream_update, 0, sizeof(stream_update));
2113         stream_update.dpms_off = &dpms_off;
2114
2115         mutex_lock(&adev->dm.dc_lock);
2116         stream_state = dc_stream_find_from_link(link);
2117
2118         if (stream_state == NULL) {
2119                 DRM_DEBUG_DRIVER("Error finding stream state associated with link!\n");
2120                 mutex_unlock(&adev->dm.dc_lock);
2121                 return;
2122         }
2123
2124         stream_update.stream = stream_state;
2125         dc_commit_updates_for_stream(stream_state->ctx->dc, NULL, 0,
2126                                      stream_state, &stream_update,
2127                                      stream_state->ctx->dc->current_state);
2128         mutex_unlock(&adev->dm.dc_lock);
2129 }
2130
2131 static int dm_resume(void *handle)
2132 {
2133         struct amdgpu_device *adev = handle;
2134         struct drm_device *ddev = adev_to_drm(adev);
2135         struct amdgpu_display_manager *dm = &adev->dm;
2136         struct amdgpu_dm_connector *aconnector;
2137         struct drm_connector *connector;
2138         struct drm_connector_list_iter iter;
2139         struct drm_crtc *crtc;
2140         struct drm_crtc_state *new_crtc_state;
2141         struct dm_crtc_state *dm_new_crtc_state;
2142         struct drm_plane *plane;
2143         struct drm_plane_state *new_plane_state;
2144         struct dm_plane_state *dm_new_plane_state;
2145         struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
2146         enum dc_connection_type new_connection_type = dc_connection_none;
2147         struct dc_state *dc_state;
2148         int i, r, j;
2149
2150         if (amdgpu_in_reset(adev)) {
2151                 dc_state = dm->cached_dc_state;
2152
2153                 r = dm_dmub_hw_init(adev);
2154                 if (r)
2155                         DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
2156
2157                 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2158                 dc_resume(dm->dc);
2159
2160                 amdgpu_dm_irq_resume_early(adev);
2161
2162                 for (i = 0; i < dc_state->stream_count; i++) {
2163                         dc_state->streams[i]->mode_changed = true;
2164                         for (j = 0; j < dc_state->stream_status->plane_count; j++) {
2165                                 dc_state->stream_status->plane_states[j]->update_flags.raw
2166                                         = 0xffffffff;
2167                         }
2168                 }
2169
2170                 WARN_ON(!dc_commit_state(dm->dc, dc_state));
2171
2172                 dm_gpureset_commit_state(dm->cached_dc_state, dm);
2173
2174                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true);
2175
2176                 dc_release_state(dm->cached_dc_state);
2177                 dm->cached_dc_state = NULL;
2178
2179                 amdgpu_dm_irq_resume_late(adev);
2180
2181                 mutex_unlock(&dm->dc_lock);
2182
2183                 return 0;
2184         }
2185         /* Recreate dc_state - DC invalidates it when setting power state to S3. */
2186         dc_release_state(dm_state->context);
2187         dm_state->context = dc_create_state(dm->dc);
2188         /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
2189         dc_resource_state_construct(dm->dc, dm_state->context);
2190
2191         /* Before powering on DC we need to re-initialize DMUB. */
2192         r = dm_dmub_hw_init(adev);
2193         if (r)
2194                 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
2195
2196         /* power on hardware */
2197         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2198
2199         /* program HPD filter */
2200         dc_resume(dm->dc);
2201
2202         /*
2203          * early enable HPD Rx IRQ, should be done before set mode as short
2204          * pulse interrupts are used for MST
2205          */
2206         amdgpu_dm_irq_resume_early(adev);
2207
2208         /* On resume we need to rewrite the MSTM control bits to enable MST*/
2209         s3_handle_mst(ddev, false);
2210
2211         /* Do detection*/
2212         drm_connector_list_iter_begin(ddev, &iter);
2213         drm_for_each_connector_iter(connector, &iter) {
2214                 aconnector = to_amdgpu_dm_connector(connector);
2215
2216                 /*
2217                  * this is the case when traversing through already created
2218                  * MST connectors, should be skipped
2219                  */
2220                 if (aconnector->mst_port)
2221                         continue;
2222
2223                 mutex_lock(&aconnector->hpd_lock);
2224                 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
2225                         DRM_ERROR("KMS: Failed to detect connector\n");
2226
2227                 if (aconnector->base.force && new_connection_type == dc_connection_none)
2228                         emulated_link_detect(aconnector->dc_link);
2229                 else
2230                         dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
2231
2232                 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
2233                         aconnector->fake_enable = false;
2234
2235                 if (aconnector->dc_sink)
2236                         dc_sink_release(aconnector->dc_sink);
2237                 aconnector->dc_sink = NULL;
2238                 amdgpu_dm_update_connector_after_detect(aconnector);
2239                 mutex_unlock(&aconnector->hpd_lock);
2240         }
2241         drm_connector_list_iter_end(&iter);
2242
2243         /* Force mode set in atomic commit */
2244         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
2245                 new_crtc_state->active_changed = true;
2246
2247         /*
2248          * atomic_check is expected to create the dc states. We need to release
2249          * them here, since they were duplicated as part of the suspend
2250          * procedure.
2251          */
2252         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
2253                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
2254                 if (dm_new_crtc_state->stream) {
2255                         WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
2256                         dc_stream_release(dm_new_crtc_state->stream);
2257                         dm_new_crtc_state->stream = NULL;
2258                 }
2259         }
2260
2261         for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
2262                 dm_new_plane_state = to_dm_plane_state(new_plane_state);
2263                 if (dm_new_plane_state->dc_state) {
2264                         WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
2265                         dc_plane_state_release(dm_new_plane_state->dc_state);
2266                         dm_new_plane_state->dc_state = NULL;
2267                 }
2268         }
2269
2270         drm_atomic_helper_resume(ddev, dm->cached_state);
2271
2272         dm->cached_state = NULL;
2273
2274 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
2275         amdgpu_dm_crtc_secure_display_resume(adev);
2276 #endif
2277
2278         amdgpu_dm_irq_resume_late(adev);
2279
2280         amdgpu_dm_smu_write_watermarks_table(adev);
2281
2282         return 0;
2283 }
2284
2285 /**
2286  * DOC: DM Lifecycle
2287  *
2288  * DM (and consequently DC) is registered in the amdgpu base driver as a IP
2289  * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
2290  * the base driver's device list to be initialized and torn down accordingly.
2291  *
2292  * The functions to do so are provided as hooks in &struct amd_ip_funcs.
2293  */
2294
2295 static const struct amd_ip_funcs amdgpu_dm_funcs = {
2296         .name = "dm",
2297         .early_init = dm_early_init,
2298         .late_init = dm_late_init,
2299         .sw_init = dm_sw_init,
2300         .sw_fini = dm_sw_fini,
2301         .hw_init = dm_hw_init,
2302         .hw_fini = dm_hw_fini,
2303         .suspend = dm_suspend,
2304         .resume = dm_resume,
2305         .is_idle = dm_is_idle,
2306         .wait_for_idle = dm_wait_for_idle,
2307         .check_soft_reset = dm_check_soft_reset,
2308         .soft_reset = dm_soft_reset,
2309         .set_clockgating_state = dm_set_clockgating_state,
2310         .set_powergating_state = dm_set_powergating_state,
2311 };
2312
2313 const struct amdgpu_ip_block_version dm_ip_block =
2314 {
2315         .type = AMD_IP_BLOCK_TYPE_DCE,
2316         .major = 1,
2317         .minor = 0,
2318         .rev = 0,
2319         .funcs = &amdgpu_dm_funcs,
2320 };
2321
2322
2323 /**
2324  * DOC: atomic
2325  *
2326  * *WIP*
2327  */
2328
2329 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
2330         .fb_create = amdgpu_display_user_framebuffer_create,
2331         .get_format_info = amd_get_format_info,
2332         .output_poll_changed = drm_fb_helper_output_poll_changed,
2333         .atomic_check = amdgpu_dm_atomic_check,
2334         .atomic_commit = drm_atomic_helper_commit,
2335 };
2336
2337 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
2338         .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
2339 };
2340
2341 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
2342 {
2343         u32 max_cll, min_cll, max, min, q, r;
2344         struct amdgpu_dm_backlight_caps *caps;
2345         struct amdgpu_display_manager *dm;
2346         struct drm_connector *conn_base;
2347         struct amdgpu_device *adev;
2348         struct dc_link *link = NULL;
2349         static const u8 pre_computed_values[] = {
2350                 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69,
2351                 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98};
2352
2353         if (!aconnector || !aconnector->dc_link)
2354                 return;
2355
2356         link = aconnector->dc_link;
2357         if (link->connector_signal != SIGNAL_TYPE_EDP)
2358                 return;
2359
2360         conn_base = &aconnector->base;
2361         adev = drm_to_adev(conn_base->dev);
2362         dm = &adev->dm;
2363         caps = &dm->backlight_caps;
2364         caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
2365         caps->aux_support = false;
2366         max_cll = conn_base->hdr_sink_metadata.hdmi_type1.max_cll;
2367         min_cll = conn_base->hdr_sink_metadata.hdmi_type1.min_cll;
2368
2369         if (caps->ext_caps->bits.oled == 1 ||
2370             caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
2371             caps->ext_caps->bits.hdr_aux_backlight_control == 1)
2372                 caps->aux_support = true;
2373
2374         if (amdgpu_backlight == 0)
2375                 caps->aux_support = false;
2376         else if (amdgpu_backlight == 1)
2377                 caps->aux_support = true;
2378
2379         /* From the specification (CTA-861-G), for calculating the maximum
2380          * luminance we need to use:
2381          *      Luminance = 50*2**(CV/32)
2382          * Where CV is a one-byte value.
2383          * For calculating this expression we may need float point precision;
2384          * to avoid this complexity level, we take advantage that CV is divided
2385          * by a constant. From the Euclids division algorithm, we know that CV
2386          * can be written as: CV = 32*q + r. Next, we replace CV in the
2387          * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just
2388          * need to pre-compute the value of r/32. For pre-computing the values
2389          * We just used the following Ruby line:
2390          *      (0...32).each {|cv| puts (50*2**(cv/32.0)).round}
2391          * The results of the above expressions can be verified at
2392          * pre_computed_values.
2393          */
2394         q = max_cll >> 5;
2395         r = max_cll % 32;
2396         max = (1 << q) * pre_computed_values[r];
2397
2398         // min luminance: maxLum * (CV/255)^2 / 100
2399         q = DIV_ROUND_CLOSEST(min_cll, 255);
2400         min = max * DIV_ROUND_CLOSEST((q * q), 100);
2401
2402         caps->aux_max_input_signal = max;
2403         caps->aux_min_input_signal = min;
2404 }
2405
2406 void amdgpu_dm_update_connector_after_detect(
2407                 struct amdgpu_dm_connector *aconnector)
2408 {
2409         struct drm_connector *connector = &aconnector->base;
2410         struct drm_device *dev = connector->dev;
2411         struct dc_sink *sink;
2412
2413         /* MST handled by drm_mst framework */
2414         if (aconnector->mst_mgr.mst_state == true)
2415                 return;
2416
2417         sink = aconnector->dc_link->local_sink;
2418         if (sink)
2419                 dc_sink_retain(sink);
2420
2421         /*
2422          * Edid mgmt connector gets first update only in mode_valid hook and then
2423          * the connector sink is set to either fake or physical sink depends on link status.
2424          * Skip if already done during boot.
2425          */
2426         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
2427                         && aconnector->dc_em_sink) {
2428
2429                 /*
2430                  * For S3 resume with headless use eml_sink to fake stream
2431                  * because on resume connector->sink is set to NULL
2432                  */
2433                 mutex_lock(&dev->mode_config.mutex);
2434
2435                 if (sink) {
2436                         if (aconnector->dc_sink) {
2437                                 amdgpu_dm_update_freesync_caps(connector, NULL);
2438                                 /*
2439                                  * retain and release below are used to
2440                                  * bump up refcount for sink because the link doesn't point
2441                                  * to it anymore after disconnect, so on next crtc to connector
2442                                  * reshuffle by UMD we will get into unwanted dc_sink release
2443                                  */
2444                                 dc_sink_release(aconnector->dc_sink);
2445                         }
2446                         aconnector->dc_sink = sink;
2447                         dc_sink_retain(aconnector->dc_sink);
2448                         amdgpu_dm_update_freesync_caps(connector,
2449                                         aconnector->edid);
2450                 } else {
2451                         amdgpu_dm_update_freesync_caps(connector, NULL);
2452                         if (!aconnector->dc_sink) {
2453                                 aconnector->dc_sink = aconnector->dc_em_sink;
2454                                 dc_sink_retain(aconnector->dc_sink);
2455                         }
2456                 }
2457
2458                 mutex_unlock(&dev->mode_config.mutex);
2459
2460                 if (sink)
2461                         dc_sink_release(sink);
2462                 return;
2463         }
2464
2465         /*
2466          * TODO: temporary guard to look for proper fix
2467          * if this sink is MST sink, we should not do anything
2468          */
2469         if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2470                 dc_sink_release(sink);
2471                 return;
2472         }
2473
2474         if (aconnector->dc_sink == sink) {
2475                 /*
2476                  * We got a DP short pulse (Link Loss, DP CTS, etc...).
2477                  * Do nothing!!
2478                  */
2479                 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
2480                                 aconnector->connector_id);
2481                 if (sink)
2482                         dc_sink_release(sink);
2483                 return;
2484         }
2485
2486         DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
2487                 aconnector->connector_id, aconnector->dc_sink, sink);
2488
2489         mutex_lock(&dev->mode_config.mutex);
2490
2491         /*
2492          * 1. Update status of the drm connector
2493          * 2. Send an event and let userspace tell us what to do
2494          */
2495         if (sink) {
2496                 /*
2497                  * TODO: check if we still need the S3 mode update workaround.
2498                  * If yes, put it here.
2499                  */
2500                 if (aconnector->dc_sink) {
2501                         amdgpu_dm_update_freesync_caps(connector, NULL);
2502                         dc_sink_release(aconnector->dc_sink);
2503                 }
2504
2505                 aconnector->dc_sink = sink;
2506                 dc_sink_retain(aconnector->dc_sink);
2507                 if (sink->dc_edid.length == 0) {
2508                         aconnector->edid = NULL;
2509                         if (aconnector->dc_link->aux_mode) {
2510                                 drm_dp_cec_unset_edid(
2511                                         &aconnector->dm_dp_aux.aux);
2512                         }
2513                 } else {
2514                         aconnector->edid =
2515                                 (struct edid *)sink->dc_edid.raw_edid;
2516
2517                         drm_connector_update_edid_property(connector,
2518                                                            aconnector->edid);
2519                         if (aconnector->dc_link->aux_mode)
2520                                 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
2521                                                     aconnector->edid);
2522                 }
2523
2524                 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
2525                 update_connector_ext_caps(aconnector);
2526         } else {
2527                 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
2528                 amdgpu_dm_update_freesync_caps(connector, NULL);
2529                 drm_connector_update_edid_property(connector, NULL);
2530                 aconnector->num_modes = 0;
2531                 dc_sink_release(aconnector->dc_sink);
2532                 aconnector->dc_sink = NULL;
2533                 aconnector->edid = NULL;
2534 #ifdef CONFIG_DRM_AMD_DC_HDCP
2535                 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
2536                 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
2537                         connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
2538 #endif
2539         }
2540
2541         mutex_unlock(&dev->mode_config.mutex);
2542
2543         update_subconnector_property(aconnector);
2544
2545         if (sink)
2546                 dc_sink_release(sink);
2547 }
2548
2549 static void handle_hpd_irq(void *param)
2550 {
2551         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
2552         struct drm_connector *connector = &aconnector->base;
2553         struct drm_device *dev = connector->dev;
2554         enum dc_connection_type new_connection_type = dc_connection_none;
2555         struct amdgpu_device *adev = drm_to_adev(dev);
2556 #ifdef CONFIG_DRM_AMD_DC_HDCP
2557         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
2558 #endif
2559
2560         if (adev->dm.disable_hpd_irq)
2561                 return;
2562
2563         /*
2564          * In case of failure or MST no need to update connector status or notify the OS
2565          * since (for MST case) MST does this in its own context.
2566          */
2567         mutex_lock(&aconnector->hpd_lock);
2568
2569 #ifdef CONFIG_DRM_AMD_DC_HDCP
2570         if (adev->dm.hdcp_workqueue) {
2571                 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
2572                 dm_con_state->update_hdcp = true;
2573         }
2574 #endif
2575         if (aconnector->fake_enable)
2576                 aconnector->fake_enable = false;
2577
2578         if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
2579                 DRM_ERROR("KMS: Failed to detect connector\n");
2580
2581         if (aconnector->base.force && new_connection_type == dc_connection_none) {
2582                 emulated_link_detect(aconnector->dc_link);
2583
2584
2585                 drm_modeset_lock_all(dev);
2586                 dm_restore_drm_connector_state(dev, connector);
2587                 drm_modeset_unlock_all(dev);
2588
2589                 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
2590                         drm_kms_helper_hotplug_event(dev);
2591
2592         } else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
2593                 if (new_connection_type == dc_connection_none &&
2594                     aconnector->dc_link->type == dc_connection_none)
2595                         dm_set_dpms_off(aconnector->dc_link);
2596
2597                 amdgpu_dm_update_connector_after_detect(aconnector);
2598
2599                 drm_modeset_lock_all(dev);
2600                 dm_restore_drm_connector_state(dev, connector);
2601                 drm_modeset_unlock_all(dev);
2602
2603                 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
2604                         drm_kms_helper_hotplug_event(dev);
2605         }
2606         mutex_unlock(&aconnector->hpd_lock);
2607
2608 }
2609
2610 static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
2611 {
2612         uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
2613         uint8_t dret;
2614         bool new_irq_handled = false;
2615         int dpcd_addr;
2616         int dpcd_bytes_to_read;
2617
2618         const int max_process_count = 30;
2619         int process_count = 0;
2620
2621         const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
2622
2623         if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
2624                 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
2625                 /* DPCD 0x200 - 0x201 for downstream IRQ */
2626                 dpcd_addr = DP_SINK_COUNT;
2627         } else {
2628                 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
2629                 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
2630                 dpcd_addr = DP_SINK_COUNT_ESI;
2631         }
2632
2633         dret = drm_dp_dpcd_read(
2634                 &aconnector->dm_dp_aux.aux,
2635                 dpcd_addr,
2636                 esi,
2637                 dpcd_bytes_to_read);
2638
2639         while (dret == dpcd_bytes_to_read &&
2640                 process_count < max_process_count) {
2641                 uint8_t retry;
2642                 dret = 0;
2643
2644                 process_count++;
2645
2646                 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
2647                 /* handle HPD short pulse irq */
2648                 if (aconnector->mst_mgr.mst_state)
2649                         drm_dp_mst_hpd_irq(
2650                                 &aconnector->mst_mgr,
2651                                 esi,
2652                                 &new_irq_handled);
2653
2654                 if (new_irq_handled) {
2655                         /* ACK at DPCD to notify down stream */
2656                         const int ack_dpcd_bytes_to_write =
2657                                 dpcd_bytes_to_read - 1;
2658
2659                         for (retry = 0; retry < 3; retry++) {
2660                                 uint8_t wret;
2661
2662                                 wret = drm_dp_dpcd_write(
2663                                         &aconnector->dm_dp_aux.aux,
2664                                         dpcd_addr + 1,
2665                                         &esi[1],
2666                                         ack_dpcd_bytes_to_write);
2667                                 if (wret == ack_dpcd_bytes_to_write)
2668                                         break;
2669                         }
2670
2671                         /* check if there is new irq to be handled */
2672                         dret = drm_dp_dpcd_read(
2673                                 &aconnector->dm_dp_aux.aux,
2674                                 dpcd_addr,
2675                                 esi,
2676                                 dpcd_bytes_to_read);
2677
2678                         new_irq_handled = false;
2679                 } else {
2680                         break;
2681                 }
2682         }
2683
2684         if (process_count == max_process_count)
2685                 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
2686 }
2687
2688 static void handle_hpd_rx_irq(void *param)
2689 {
2690         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
2691         struct drm_connector *connector = &aconnector->base;
2692         struct drm_device *dev = connector->dev;
2693         struct dc_link *dc_link = aconnector->dc_link;
2694         bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
2695         bool result = false;
2696         enum dc_connection_type new_connection_type = dc_connection_none;
2697         struct amdgpu_device *adev = drm_to_adev(dev);
2698         union hpd_irq_data hpd_irq_data;
2699
2700         memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
2701
2702         if (adev->dm.disable_hpd_irq)
2703                 return;
2704
2705
2706         /*
2707          * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
2708          * conflict, after implement i2c helper, this mutex should be
2709          * retired.
2710          */
2711         mutex_lock(&aconnector->hpd_lock);
2712
2713         read_hpd_rx_irq_data(dc_link, &hpd_irq_data);
2714
2715         if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
2716                 (dc_link->type == dc_connection_mst_branch)) {
2717                 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY) {
2718                         result = true;
2719                         dm_handle_hpd_rx_irq(aconnector);
2720                         goto out;
2721                 } else if (hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
2722                         result = false;
2723                         dm_handle_hpd_rx_irq(aconnector);
2724                         goto out;
2725                 }
2726         }
2727
2728         if (!amdgpu_in_reset(adev))
2729                 mutex_lock(&adev->dm.dc_lock);
2730 #ifdef CONFIG_DRM_AMD_DC_HDCP
2731         result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data, NULL);
2732 #else
2733         result = dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL);
2734 #endif
2735         if (!amdgpu_in_reset(adev))
2736                 mutex_unlock(&adev->dm.dc_lock);
2737
2738 out:
2739         if (result && !is_mst_root_connector) {
2740                 /* Downstream Port status changed. */
2741                 if (!dc_link_detect_sink(dc_link, &new_connection_type))
2742                         DRM_ERROR("KMS: Failed to detect connector\n");
2743
2744                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2745                         emulated_link_detect(dc_link);
2746
2747                         if (aconnector->fake_enable)
2748                                 aconnector->fake_enable = false;
2749
2750                         amdgpu_dm_update_connector_after_detect(aconnector);
2751
2752
2753                         drm_modeset_lock_all(dev);
2754                         dm_restore_drm_connector_state(dev, connector);
2755                         drm_modeset_unlock_all(dev);
2756
2757                         drm_kms_helper_hotplug_event(dev);
2758                 } else if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
2759
2760                         if (aconnector->fake_enable)
2761                                 aconnector->fake_enable = false;
2762
2763                         amdgpu_dm_update_connector_after_detect(aconnector);
2764
2765
2766                         drm_modeset_lock_all(dev);
2767                         dm_restore_drm_connector_state(dev, connector);
2768                         drm_modeset_unlock_all(dev);
2769
2770                         drm_kms_helper_hotplug_event(dev);
2771                 }
2772         }
2773 #ifdef CONFIG_DRM_AMD_DC_HDCP
2774         if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
2775                 if (adev->dm.hdcp_workqueue)
2776                         hdcp_handle_cpirq(adev->dm.hdcp_workqueue,  aconnector->base.index);
2777         }
2778 #endif
2779
2780         if (dc_link->type != dc_connection_mst_branch)
2781                 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
2782
2783         mutex_unlock(&aconnector->hpd_lock);
2784 }
2785
2786 static void register_hpd_handlers(struct amdgpu_device *adev)
2787 {
2788         struct drm_device *dev = adev_to_drm(adev);
2789         struct drm_connector *connector;
2790         struct amdgpu_dm_connector *aconnector;
2791         const struct dc_link *dc_link;
2792         struct dc_interrupt_params int_params = {0};
2793
2794         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
2795         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
2796
2797         list_for_each_entry(connector,
2798                         &dev->mode_config.connector_list, head) {
2799
2800                 aconnector = to_amdgpu_dm_connector(connector);
2801                 dc_link = aconnector->dc_link;
2802
2803                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
2804                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
2805                         int_params.irq_source = dc_link->irq_source_hpd;
2806
2807                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
2808                                         handle_hpd_irq,
2809                                         (void *) aconnector);
2810                 }
2811
2812                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
2813
2814                         /* Also register for DP short pulse (hpd_rx). */
2815                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
2816                         int_params.irq_source = dc_link->irq_source_hpd_rx;
2817
2818                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
2819                                         handle_hpd_rx_irq,
2820                                         (void *) aconnector);
2821                 }
2822         }
2823 }
2824
2825 #if defined(CONFIG_DRM_AMD_DC_SI)
2826 /* Register IRQ sources and initialize IRQ callbacks */
2827 static int dce60_register_irq_handlers(struct amdgpu_device *adev)
2828 {
2829         struct dc *dc = adev->dm.dc;
2830         struct common_irq_params *c_irq_params;
2831         struct dc_interrupt_params int_params = {0};
2832         int r;
2833         int i;
2834         unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
2835
2836         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
2837         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
2838
2839         /*
2840          * Actions of amdgpu_irq_add_id():
2841          * 1. Register a set() function with base driver.
2842          *    Base driver will call set() function to enable/disable an
2843          *    interrupt in DC hardware.
2844          * 2. Register amdgpu_dm_irq_handler().
2845          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
2846          *    coming from DC hardware.
2847          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
2848          *    for acknowledging and handling. */
2849
2850         /* Use VBLANK interrupt */
2851         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2852                 r = amdgpu_irq_add_id(adev, client_id, i+1 , &adev->crtc_irq);
2853                 if (r) {
2854                         DRM_ERROR("Failed to add crtc irq id!\n");
2855                         return r;
2856                 }
2857
2858                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
2859                 int_params.irq_source =
2860                         dc_interrupt_to_irq_source(dc, i+1 , 0);
2861
2862                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
2863
2864                 c_irq_params->adev = adev;
2865                 c_irq_params->irq_src = int_params.irq_source;
2866
2867                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
2868                                 dm_crtc_high_irq, c_irq_params);
2869         }
2870
2871         /* Use GRPH_PFLIP interrupt */
2872         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
2873                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
2874                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
2875                 if (r) {
2876                         DRM_ERROR("Failed to add page flip irq id!\n");
2877                         return r;
2878                 }
2879
2880                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
2881                 int_params.irq_source =
2882                         dc_interrupt_to_irq_source(dc, i, 0);
2883
2884                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
2885
2886                 c_irq_params->adev = adev;
2887                 c_irq_params->irq_src = int_params.irq_source;
2888
2889                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
2890                                 dm_pflip_high_irq, c_irq_params);
2891
2892         }
2893
2894         /* HPD */
2895         r = amdgpu_irq_add_id(adev, client_id,
2896                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
2897         if (r) {
2898                 DRM_ERROR("Failed to add hpd irq id!\n");
2899                 return r;
2900         }
2901
2902         register_hpd_handlers(adev);
2903
2904         return 0;
2905 }
2906 #endif
2907
2908 /* Register IRQ sources and initialize IRQ callbacks */
2909 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
2910 {
2911         struct dc *dc = adev->dm.dc;
2912         struct common_irq_params *c_irq_params;
2913         struct dc_interrupt_params int_params = {0};
2914         int r;
2915         int i;
2916         unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
2917
2918         if (adev->asic_type >= CHIP_VEGA10)
2919                 client_id = SOC15_IH_CLIENTID_DCE;
2920
2921         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
2922         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
2923
2924         /*
2925          * Actions of amdgpu_irq_add_id():
2926          * 1. Register a set() function with base driver.
2927          *    Base driver will call set() function to enable/disable an
2928          *    interrupt in DC hardware.
2929          * 2. Register amdgpu_dm_irq_handler().
2930          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
2931          *    coming from DC hardware.
2932          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
2933          *    for acknowledging and handling. */
2934
2935         /* Use VBLANK interrupt */
2936         for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
2937                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
2938                 if (r) {
2939                         DRM_ERROR("Failed to add crtc irq id!\n");
2940                         return r;
2941                 }
2942
2943                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
2944                 int_params.irq_source =
2945                         dc_interrupt_to_irq_source(dc, i, 0);
2946
2947                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
2948
2949                 c_irq_params->adev = adev;
2950                 c_irq_params->irq_src = int_params.irq_source;
2951
2952                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
2953                                 dm_crtc_high_irq, c_irq_params);
2954         }
2955
2956         /* Use VUPDATE interrupt */
2957         for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
2958                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
2959                 if (r) {
2960                         DRM_ERROR("Failed to add vupdate irq id!\n");
2961                         return r;
2962                 }
2963
2964                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
2965                 int_params.irq_source =
2966                         dc_interrupt_to_irq_source(dc, i, 0);
2967
2968                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
2969
2970                 c_irq_params->adev = adev;
2971                 c_irq_params->irq_src = int_params.irq_source;
2972
2973                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
2974                                 dm_vupdate_high_irq, c_irq_params);
2975         }
2976
2977         /* Use GRPH_PFLIP interrupt */
2978         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
2979                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
2980                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
2981                 if (r) {
2982                         DRM_ERROR("Failed to add page flip irq id!\n");
2983                         return r;
2984                 }
2985
2986                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
2987                 int_params.irq_source =
2988                         dc_interrupt_to_irq_source(dc, i, 0);
2989
2990                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
2991
2992                 c_irq_params->adev = adev;
2993                 c_irq_params->irq_src = int_params.irq_source;
2994
2995                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
2996                                 dm_pflip_high_irq, c_irq_params);
2997
2998         }
2999
3000         /* HPD */
3001         r = amdgpu_irq_add_id(adev, client_id,
3002                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3003         if (r) {
3004                 DRM_ERROR("Failed to add hpd irq id!\n");
3005                 return r;
3006         }
3007
3008         register_hpd_handlers(adev);
3009
3010         return 0;
3011 }
3012
3013 #if defined(CONFIG_DRM_AMD_DC_DCN)
3014 /* Register IRQ sources and initialize IRQ callbacks */
3015 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
3016 {
3017         struct dc *dc = adev->dm.dc;
3018         struct common_irq_params *c_irq_params;
3019         struct dc_interrupt_params int_params = {0};
3020         int r;
3021         int i;
3022 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3023         static const unsigned int vrtl_int_srcid[] = {
3024                 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL,
3025                 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL,
3026                 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL,
3027                 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL,
3028                 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL,
3029                 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL
3030         };
3031 #endif
3032
3033         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3034         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3035
3036         /*
3037          * Actions of amdgpu_irq_add_id():
3038          * 1. Register a set() function with base driver.
3039          *    Base driver will call set() function to enable/disable an
3040          *    interrupt in DC hardware.
3041          * 2. Register amdgpu_dm_irq_handler().
3042          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3043          *    coming from DC hardware.
3044          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3045          *    for acknowledging and handling.
3046          */
3047
3048         /* Use VSTARTUP interrupt */
3049         for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
3050                         i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
3051                         i++) {
3052                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
3053
3054                 if (r) {
3055                         DRM_ERROR("Failed to add crtc irq id!\n");
3056                         return r;
3057                 }
3058
3059                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3060                 int_params.irq_source =
3061                         dc_interrupt_to_irq_source(dc, i, 0);
3062
3063                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3064
3065                 c_irq_params->adev = adev;
3066                 c_irq_params->irq_src = int_params.irq_source;
3067
3068                 amdgpu_dm_irq_register_interrupt(
3069                         adev, &int_params, dm_crtc_high_irq, c_irq_params);
3070         }
3071
3072         /* Use otg vertical line interrupt */
3073 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3074         for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) {
3075                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE,
3076                                 vrtl_int_srcid[i], &adev->vline0_irq);
3077
3078                 if (r) {
3079                         DRM_ERROR("Failed to add vline0 irq id!\n");
3080                         return r;
3081                 }
3082
3083                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3084                 int_params.irq_source =
3085                         dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0);
3086
3087                 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) {
3088                         DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]);
3089                         break;
3090                 }
3091
3092                 c_irq_params = &adev->dm.vline0_params[int_params.irq_source
3093                                         - DC_IRQ_SOURCE_DC1_VLINE0];
3094
3095                 c_irq_params->adev = adev;
3096                 c_irq_params->irq_src = int_params.irq_source;
3097
3098                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3099                                 dm_dcn_vertical_interrupt0_high_irq, c_irq_params);
3100         }
3101 #endif
3102
3103         /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
3104          * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
3105          * to trigger at end of each vblank, regardless of state of the lock,
3106          * matching DCE behaviour.
3107          */
3108         for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
3109              i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
3110              i++) {
3111                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
3112
3113                 if (r) {
3114                         DRM_ERROR("Failed to add vupdate irq id!\n");
3115                         return r;
3116                 }
3117
3118                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3119                 int_params.irq_source =
3120                         dc_interrupt_to_irq_source(dc, i, 0);
3121
3122                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3123
3124                 c_irq_params->adev = adev;
3125                 c_irq_params->irq_src = int_params.irq_source;
3126
3127                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3128                                 dm_vupdate_high_irq, c_irq_params);
3129         }
3130
3131         /* Use GRPH_PFLIP interrupt */
3132         for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
3133                         i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
3134                         i++) {
3135                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
3136                 if (r) {
3137                         DRM_ERROR("Failed to add page flip irq id!\n");
3138                         return r;
3139                 }
3140
3141                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3142                 int_params.irq_source =
3143                         dc_interrupt_to_irq_source(dc, i, 0);
3144
3145                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3146
3147                 c_irq_params->adev = adev;
3148                 c_irq_params->irq_src = int_params.irq_source;
3149
3150                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3151                                 dm_pflip_high_irq, c_irq_params);
3152
3153         }
3154
3155         if (dc->ctx->dmub_srv) {
3156                 i = DCN_1_0__SRCID__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INT;
3157                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->dmub_trace_irq);
3158
3159                 if (r) {
3160                         DRM_ERROR("Failed to add dmub trace irq id!\n");
3161                         return r;
3162                 }
3163
3164                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3165                 int_params.irq_source =
3166                         dc_interrupt_to_irq_source(dc, i, 0);
3167
3168                 c_irq_params = &adev->dm.dmub_trace_params[0];
3169
3170                 c_irq_params->adev = adev;
3171                 c_irq_params->irq_src = int_params.irq_source;
3172
3173                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3174                                 dm_dmub_trace_high_irq, c_irq_params);
3175         }
3176
3177         /* HPD */
3178         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
3179                         &adev->hpd_irq);
3180         if (r) {
3181                 DRM_ERROR("Failed to add hpd irq id!\n");
3182                 return r;
3183         }
3184
3185         register_hpd_handlers(adev);
3186
3187         return 0;
3188 }
3189 #endif
3190
3191 /*
3192  * Acquires the lock for the atomic state object and returns
3193  * the new atomic state.
3194  *
3195  * This should only be called during atomic check.
3196  */
3197 static int dm_atomic_get_state(struct drm_atomic_state *state,
3198                                struct dm_atomic_state **dm_state)
3199 {
3200         struct drm_device *dev = state->dev;
3201         struct amdgpu_device *adev = drm_to_adev(dev);
3202         struct amdgpu_display_manager *dm = &adev->dm;
3203         struct drm_private_state *priv_state;
3204
3205         if (*dm_state)
3206                 return 0;
3207
3208         priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
3209         if (IS_ERR(priv_state))
3210                 return PTR_ERR(priv_state);
3211
3212         *dm_state = to_dm_atomic_state(priv_state);
3213
3214         return 0;
3215 }
3216
3217 static struct dm_atomic_state *
3218 dm_atomic_get_new_state(struct drm_atomic_state *state)
3219 {
3220         struct drm_device *dev = state->dev;
3221         struct amdgpu_device *adev = drm_to_adev(dev);
3222         struct amdgpu_display_manager *dm = &adev->dm;
3223         struct drm_private_obj *obj;
3224         struct drm_private_state *new_obj_state;
3225         int i;
3226
3227         for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
3228                 if (obj->funcs == dm->atomic_obj.funcs)
3229                         return to_dm_atomic_state(new_obj_state);
3230         }
3231
3232         return NULL;
3233 }
3234
3235 static struct drm_private_state *
3236 dm_atomic_duplicate_state(struct drm_private_obj *obj)
3237 {
3238         struct dm_atomic_state *old_state, *new_state;
3239
3240         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
3241         if (!new_state)
3242                 return NULL;
3243
3244         __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
3245
3246         old_state = to_dm_atomic_state(obj->state);
3247
3248         if (old_state && old_state->context)
3249                 new_state->context = dc_copy_state(old_state->context);
3250
3251         if (!new_state->context) {
3252                 kfree(new_state);
3253                 return NULL;
3254         }
3255
3256         return &new_state->base;
3257 }
3258
3259 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
3260                                     struct drm_private_state *state)
3261 {
3262         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
3263
3264         if (dm_state && dm_state->context)
3265                 dc_release_state(dm_state->context);
3266
3267         kfree(dm_state);
3268 }
3269
3270 static struct drm_private_state_funcs dm_atomic_state_funcs = {
3271         .atomic_duplicate_state = dm_atomic_duplicate_state,
3272         .atomic_destroy_state = dm_atomic_destroy_state,
3273 };
3274
3275 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
3276 {
3277         struct dm_atomic_state *state;
3278         int r;
3279
3280         adev->mode_info.mode_config_initialized = true;
3281
3282         adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
3283         adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
3284
3285         adev_to_drm(adev)->mode_config.max_width = 16384;
3286         adev_to_drm(adev)->mode_config.max_height = 16384;
3287
3288         adev_to_drm(adev)->mode_config.preferred_depth = 24;
3289         adev_to_drm(adev)->mode_config.prefer_shadow = 1;
3290         /* indicates support for immediate flip */
3291         adev_to_drm(adev)->mode_config.async_page_flip = true;
3292
3293         adev_to_drm(adev)->mode_config.fb_base = adev->gmc.aper_base;
3294
3295         state = kzalloc(sizeof(*state), GFP_KERNEL);
3296         if (!state)
3297                 return -ENOMEM;
3298
3299         state->context = dc_create_state(adev->dm.dc);
3300         if (!state->context) {
3301                 kfree(state);
3302                 return -ENOMEM;
3303         }
3304
3305         dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
3306
3307         drm_atomic_private_obj_init(adev_to_drm(adev),
3308                                     &adev->dm.atomic_obj,
3309                                     &state->base,
3310                                     &dm_atomic_state_funcs);
3311
3312         r = amdgpu_display_modeset_create_props(adev);
3313         if (r) {
3314                 dc_release_state(state->context);
3315                 kfree(state);
3316                 return r;
3317         }
3318
3319         r = amdgpu_dm_audio_init(adev);
3320         if (r) {
3321                 dc_release_state(state->context);
3322                 kfree(state);
3323                 return r;
3324         }
3325
3326         return 0;
3327 }
3328
3329 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
3330 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
3331 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
3332
3333 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
3334         defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
3335
3336 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm)
3337 {
3338 #if defined(CONFIG_ACPI)
3339         struct amdgpu_dm_backlight_caps caps;
3340
3341         memset(&caps, 0, sizeof(caps));
3342
3343         if (dm->backlight_caps.caps_valid)
3344                 return;
3345
3346         amdgpu_acpi_get_backlight_caps(dm->adev, &caps);
3347         if (caps.caps_valid) {
3348                 dm->backlight_caps.caps_valid = true;
3349                 if (caps.aux_support)
3350                         return;
3351                 dm->backlight_caps.min_input_signal = caps.min_input_signal;
3352                 dm->backlight_caps.max_input_signal = caps.max_input_signal;
3353         } else {
3354                 dm->backlight_caps.min_input_signal =
3355                                 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
3356                 dm->backlight_caps.max_input_signal =
3357                                 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
3358         }
3359 #else
3360         if (dm->backlight_caps.aux_support)
3361                 return;
3362
3363         dm->backlight_caps.min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
3364         dm->backlight_caps.max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
3365 #endif
3366 }
3367
3368 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
3369                                 unsigned *min, unsigned *max)
3370 {
3371         if (!caps)
3372                 return 0;
3373
3374         if (caps->aux_support) {
3375                 // Firmware limits are in nits, DC API wants millinits.
3376                 *max = 1000 * caps->aux_max_input_signal;
3377                 *min = 1000 * caps->aux_min_input_signal;
3378         } else {
3379                 // Firmware limits are 8-bit, PWM control is 16-bit.
3380                 *max = 0x101 * caps->max_input_signal;
3381                 *min = 0x101 * caps->min_input_signal;
3382         }
3383         return 1;
3384 }
3385
3386 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
3387                                         uint32_t brightness)
3388 {
3389         unsigned min, max;
3390
3391         if (!get_brightness_range(caps, &min, &max))
3392                 return brightness;
3393
3394         // Rescale 0..255 to min..max
3395         return min + DIV_ROUND_CLOSEST((max - min) * brightness,
3396                                        AMDGPU_MAX_BL_LEVEL);
3397 }
3398
3399 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
3400                                       uint32_t brightness)
3401 {
3402         unsigned min, max;
3403
3404         if (!get_brightness_range(caps, &min, &max))
3405                 return brightness;
3406
3407         if (brightness < min)
3408                 return 0;
3409         // Rescale min..max to 0..255
3410         return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),
3411                                  max - min);
3412 }
3413
3414 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
3415 {
3416         struct amdgpu_display_manager *dm = bl_get_data(bd);
3417         struct amdgpu_dm_backlight_caps caps;
3418         struct dc_link *link = NULL;
3419         u32 brightness;
3420         bool rc;
3421
3422         amdgpu_dm_update_backlight_caps(dm);
3423         caps = dm->backlight_caps;
3424
3425         link = (struct dc_link *)dm->backlight_link;
3426
3427         brightness = convert_brightness_from_user(&caps, bd->props.brightness);
3428         // Change brightness based on AUX property
3429         if (caps.aux_support)
3430                 rc = dc_link_set_backlight_level_nits(link, true, brightness,
3431                                                       AUX_BL_DEFAULT_TRANSITION_TIME_MS);
3432         else
3433                 rc = dc_link_set_backlight_level(dm->backlight_link, brightness, 0);
3434
3435         return rc ? 0 : 1;
3436 }
3437
3438 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
3439 {
3440         struct amdgpu_display_manager *dm = bl_get_data(bd);
3441         struct amdgpu_dm_backlight_caps caps;
3442
3443         amdgpu_dm_update_backlight_caps(dm);
3444         caps = dm->backlight_caps;
3445
3446         if (caps.aux_support) {
3447                 struct dc_link *link = (struct dc_link *)dm->backlight_link;
3448                 u32 avg, peak;
3449                 bool rc;
3450
3451                 rc = dc_link_get_backlight_level_nits(link, &avg, &peak);
3452                 if (!rc)
3453                         return bd->props.brightness;
3454                 return convert_brightness_to_user(&caps, avg);
3455         } else {
3456                 int ret = dc_link_get_backlight_level(dm->backlight_link);
3457
3458                 if (ret == DC_ERROR_UNEXPECTED)
3459                         return bd->props.brightness;
3460                 return convert_brightness_to_user(&caps, ret);
3461         }
3462 }
3463
3464 static const struct backlight_ops amdgpu_dm_backlight_ops = {
3465         .options = BL_CORE_SUSPENDRESUME,
3466         .get_brightness = amdgpu_dm_backlight_get_brightness,
3467         .update_status  = amdgpu_dm_backlight_update_status,
3468 };
3469
3470 static void
3471 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
3472 {
3473         char bl_name[16];
3474         struct backlight_properties props = { 0 };
3475
3476         amdgpu_dm_update_backlight_caps(dm);
3477
3478         props.max_brightness = AMDGPU_MAX_BL_LEVEL;
3479         props.brightness = AMDGPU_MAX_BL_LEVEL;
3480         props.type = BACKLIGHT_RAW;
3481
3482         snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
3483                  adev_to_drm(dm->adev)->primary->index);
3484
3485         dm->backlight_dev = backlight_device_register(bl_name,
3486                                                       adev_to_drm(dm->adev)->dev,
3487                                                       dm,
3488                                                       &amdgpu_dm_backlight_ops,
3489                                                       &props);
3490
3491         if (IS_ERR(dm->backlight_dev))
3492                 DRM_ERROR("DM: Backlight registration failed!\n");
3493         else
3494                 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
3495 }
3496
3497 #endif
3498
3499 static int initialize_plane(struct amdgpu_display_manager *dm,
3500                             struct amdgpu_mode_info *mode_info, int plane_id,
3501                             enum drm_plane_type plane_type,
3502                             const struct dc_plane_cap *plane_cap)
3503 {
3504         struct drm_plane *plane;
3505         unsigned long possible_crtcs;
3506         int ret = 0;
3507
3508         plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
3509         if (!plane) {
3510                 DRM_ERROR("KMS: Failed to allocate plane\n");
3511                 return -ENOMEM;
3512         }
3513         plane->type = plane_type;
3514
3515         /*
3516          * HACK: IGT tests expect that the primary plane for a CRTC
3517          * can only have one possible CRTC. Only expose support for
3518          * any CRTC if they're not going to be used as a primary plane
3519          * for a CRTC - like overlay or underlay planes.
3520          */
3521         possible_crtcs = 1 << plane_id;
3522         if (plane_id >= dm->dc->caps.max_streams)
3523                 possible_crtcs = 0xff;
3524
3525         ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
3526
3527         if (ret) {
3528                 DRM_ERROR("KMS: Failed to initialize plane\n");
3529                 kfree(plane);
3530                 return ret;
3531         }
3532
3533         if (mode_info)
3534                 mode_info->planes[plane_id] = plane;
3535
3536         return ret;
3537 }
3538
3539
3540 static void register_backlight_device(struct amdgpu_display_manager *dm,
3541                                       struct dc_link *link)
3542 {
3543 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
3544         defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
3545
3546         if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
3547             link->type != dc_connection_none) {
3548                 /*
3549                  * Event if registration failed, we should continue with
3550                  * DM initialization because not having a backlight control
3551                  * is better then a black screen.
3552                  */
3553                 amdgpu_dm_register_backlight_device(dm);
3554
3555                 if (dm->backlight_dev)
3556                         dm->backlight_link = link;
3557         }
3558 #endif
3559 }
3560
3561
3562 /*
3563  * In this architecture, the association
3564  * connector -> encoder -> crtc
3565  * id not really requried. The crtc and connector will hold the
3566  * display_index as an abstraction to use with DAL component
3567  *
3568  * Returns 0 on success
3569  */
3570 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
3571 {
3572         struct amdgpu_display_manager *dm = &adev->dm;
3573         int32_t i;
3574         struct amdgpu_dm_connector *aconnector = NULL;
3575         struct amdgpu_encoder *aencoder = NULL;
3576         struct amdgpu_mode_info *mode_info = &adev->mode_info;
3577         uint32_t link_cnt;
3578         int32_t primary_planes;
3579         enum dc_connection_type new_connection_type = dc_connection_none;
3580         const struct dc_plane_cap *plane;
3581
3582         dm->display_indexes_num = dm->dc->caps.max_streams;
3583         /* Update the actual used number of crtc */
3584         adev->mode_info.num_crtc = adev->dm.display_indexes_num;
3585
3586         link_cnt = dm->dc->caps.max_links;
3587         if (amdgpu_dm_mode_config_init(dm->adev)) {
3588                 DRM_ERROR("DM: Failed to initialize mode config\n");
3589                 return -EINVAL;
3590         }
3591
3592         /* There is one primary plane per CRTC */
3593         primary_planes = dm->dc->caps.max_streams;
3594         ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
3595
3596         /*
3597          * Initialize primary planes, implicit planes for legacy IOCTLS.
3598          * Order is reversed to match iteration order in atomic check.
3599          */
3600         for (i = (primary_planes - 1); i >= 0; i--) {
3601                 plane = &dm->dc->caps.planes[i];
3602
3603                 if (initialize_plane(dm, mode_info, i,
3604                                      DRM_PLANE_TYPE_PRIMARY, plane)) {
3605                         DRM_ERROR("KMS: Failed to initialize primary plane\n");
3606                         goto fail;
3607                 }
3608         }
3609
3610         /*
3611          * Initialize overlay planes, index starting after primary planes.
3612          * These planes have a higher DRM index than the primary planes since
3613          * they should be considered as having a higher z-order.
3614          * Order is reversed to match iteration order in atomic check.
3615          *
3616          * Only support DCN for now, and only expose one so we don't encourage
3617          * userspace to use up all the pipes.
3618          */
3619         for (i = 0; i < dm->dc->caps.max_planes; ++i) {
3620                 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
3621
3622                 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
3623                         continue;
3624
3625                 if (!plane->blends_with_above || !plane->blends_with_below)
3626                         continue;
3627
3628                 if (!plane->pixel_format_support.argb8888)
3629                         continue;
3630
3631                 if (initialize_plane(dm, NULL, primary_planes + i,
3632                                      DRM_PLANE_TYPE_OVERLAY, plane)) {
3633                         DRM_ERROR("KMS: Failed to initialize overlay plane\n");
3634                         goto fail;
3635                 }
3636
3637                 /* Only create one overlay plane. */
3638                 break;
3639         }
3640
3641         for (i = 0; i < dm->dc->caps.max_streams; i++)
3642                 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
3643                         DRM_ERROR("KMS: Failed to initialize crtc\n");
3644                         goto fail;
3645                 }
3646
3647         /* loops over all connectors on the board */
3648         for (i = 0; i < link_cnt; i++) {
3649                 struct dc_link *link = NULL;
3650
3651                 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
3652                         DRM_ERROR(
3653                                 "KMS: Cannot support more than %d display indexes\n",
3654                                         AMDGPU_DM_MAX_DISPLAY_INDEX);
3655                         continue;
3656                 }
3657
3658                 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
3659                 if (!aconnector)
3660                         goto fail;
3661
3662                 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
3663                 if (!aencoder)
3664                         goto fail;
3665
3666                 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
3667                         DRM_ERROR("KMS: Failed to initialize encoder\n");
3668                         goto fail;
3669                 }
3670
3671                 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
3672                         DRM_ERROR("KMS: Failed to initialize connector\n");
3673                         goto fail;
3674                 }
3675
3676                 link = dc_get_link_at_index(dm->dc, i);
3677
3678                 if (!dc_link_detect_sink(link, &new_connection_type))
3679                         DRM_ERROR("KMS: Failed to detect connector\n");
3680
3681                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3682                         emulated_link_detect(link);
3683                         amdgpu_dm_update_connector_after_detect(aconnector);
3684
3685                 } else if (dc_link_detect(link, DETECT_REASON_BOOT)) {
3686                         amdgpu_dm_update_connector_after_detect(aconnector);
3687                         register_backlight_device(dm, link);
3688                         if (amdgpu_dc_feature_mask & DC_PSR_MASK)
3689                                 amdgpu_dm_set_psr_caps(link);
3690                 }
3691
3692
3693         }
3694
3695         /* Software is initialized. Now we can register interrupt handlers. */
3696         switch (adev->asic_type) {
3697 #if defined(CONFIG_DRM_AMD_DC_SI)
3698         case CHIP_TAHITI:
3699         case CHIP_PITCAIRN:
3700         case CHIP_VERDE:
3701         case CHIP_OLAND:
3702                 if (dce60_register_irq_handlers(dm->adev)) {
3703                         DRM_ERROR("DM: Failed to initialize IRQ\n");
3704                         goto fail;
3705                 }
3706                 break;
3707 #endif
3708         case CHIP_BONAIRE:
3709         case CHIP_HAWAII:
3710         case CHIP_KAVERI:
3711         case CHIP_KABINI:
3712         case CHIP_MULLINS:
3713         case CHIP_TONGA:
3714         case CHIP_FIJI:
3715         case CHIP_CARRIZO:
3716         case CHIP_STONEY:
3717         case CHIP_POLARIS11:
3718         case CHIP_POLARIS10:
3719         case CHIP_POLARIS12:
3720         case CHIP_VEGAM:
3721         case CHIP_VEGA10:
3722         case CHIP_VEGA12:
3723         case CHIP_VEGA20:
3724                 if (dce110_register_irq_handlers(dm->adev)) {
3725                         DRM_ERROR("DM: Failed to initialize IRQ\n");
3726                         goto fail;
3727                 }
3728                 break;
3729 #if defined(CONFIG_DRM_AMD_DC_DCN)
3730         case CHIP_RAVEN:
3731         case CHIP_NAVI12:
3732         case CHIP_NAVI10:
3733         case CHIP_NAVI14:
3734         case CHIP_RENOIR:
3735         case CHIP_SIENNA_CICHLID:
3736         case CHIP_NAVY_FLOUNDER:
3737         case CHIP_DIMGREY_CAVEFISH:
3738         case CHIP_VANGOGH:
3739                 if (dcn10_register_irq_handlers(dm->adev)) {
3740                         DRM_ERROR("DM: Failed to initialize IRQ\n");
3741                         goto fail;
3742                 }
3743                 break;
3744 #endif
3745         default:
3746                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
3747                 goto fail;
3748         }
3749
3750         return 0;
3751 fail:
3752         kfree(aencoder);
3753         kfree(aconnector);
3754
3755         return -EINVAL;
3756 }
3757
3758 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
3759 {
3760         drm_mode_config_cleanup(dm->ddev);
3761         drm_atomic_private_obj_fini(&dm->atomic_obj);
3762         return;
3763 }
3764
3765 /******************************************************************************
3766  * amdgpu_display_funcs functions
3767  *****************************************************************************/
3768
3769 /*
3770  * dm_bandwidth_update - program display watermarks
3771  *
3772  * @adev: amdgpu_device pointer
3773  *
3774  * Calculate and program the display watermarks and line buffer allocation.
3775  */
3776 static void dm_bandwidth_update(struct amdgpu_device *adev)
3777 {
3778         /* TODO: implement later */
3779 }
3780
3781 static const struct amdgpu_display_funcs dm_display_funcs = {
3782         .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
3783         .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
3784         .backlight_set_level = NULL, /* never called for DC */
3785         .backlight_get_level = NULL, /* never called for DC */
3786         .hpd_sense = NULL,/* called unconditionally */
3787         .hpd_set_polarity = NULL, /* called unconditionally */
3788         .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
3789         .page_flip_get_scanoutpos =
3790                 dm_crtc_get_scanoutpos,/* called unconditionally */
3791         .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
3792         .add_connector = NULL, /* VBIOS parsing. DAL does it. */
3793 };
3794
3795 #if defined(CONFIG_DEBUG_KERNEL_DC)
3796
3797 static ssize_t s3_debug_store(struct device *device,
3798                               struct device_attribute *attr,
3799                               const char *buf,
3800                               size_t count)
3801 {
3802         int ret;
3803         int s3_state;
3804         struct drm_device *drm_dev = dev_get_drvdata(device);
3805         struct amdgpu_device *adev = drm_to_adev(drm_dev);
3806
3807         ret = kstrtoint(buf, 0, &s3_state);
3808
3809         if (ret == 0) {
3810                 if (s3_state) {
3811                         dm_resume(adev);
3812                         drm_kms_helper_hotplug_event(adev_to_drm(adev));
3813                 } else
3814                         dm_suspend(adev);
3815         }
3816
3817         return ret == 0 ? count : 0;
3818 }
3819
3820 DEVICE_ATTR_WO(s3_debug);
3821
3822 #endif
3823
3824 static int dm_early_init(void *handle)
3825 {
3826         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3827
3828         switch (adev->asic_type) {
3829 #if defined(CONFIG_DRM_AMD_DC_SI)
3830         case CHIP_TAHITI:
3831         case CHIP_PITCAIRN:
3832         case CHIP_VERDE:
3833                 adev->mode_info.num_crtc = 6;
3834                 adev->mode_info.num_hpd = 6;
3835                 adev->mode_info.num_dig = 6;
3836                 break;
3837         case CHIP_OLAND:
3838                 adev->mode_info.num_crtc = 2;
3839                 adev->mode_info.num_hpd = 2;
3840                 adev->mode_info.num_dig = 2;
3841                 break;
3842 #endif
3843         case CHIP_BONAIRE:
3844         case CHIP_HAWAII:
3845                 adev->mode_info.num_crtc = 6;
3846                 adev->mode_info.num_hpd = 6;
3847                 adev->mode_info.num_dig = 6;
3848                 break;
3849         case CHIP_KAVERI:
3850                 adev->mode_info.num_crtc = 4;
3851                 adev->mode_info.num_hpd = 6;
3852                 adev->mode_info.num_dig = 7;
3853                 break;
3854         case CHIP_KABINI:
3855         case CHIP_MULLINS:
3856                 adev->mode_info.num_crtc = 2;
3857                 adev->mode_info.num_hpd = 6;
3858                 adev->mode_info.num_dig = 6;
3859                 break;
3860         case CHIP_FIJI:
3861         case CHIP_TONGA:
3862                 adev->mode_info.num_crtc = 6;
3863                 adev->mode_info.num_hpd = 6;
3864                 adev->mode_info.num_dig = 7;
3865                 break;
3866         case CHIP_CARRIZO:
3867                 adev->mode_info.num_crtc = 3;
3868                 adev->mode_info.num_hpd = 6;
3869                 adev->mode_info.num_dig = 9;
3870                 break;
3871         case CHIP_STONEY:
3872                 adev->mode_info.num_crtc = 2;
3873                 adev->mode_info.num_hpd = 6;
3874                 adev->mode_info.num_dig = 9;
3875                 break;
3876         case CHIP_POLARIS11:
3877         case CHIP_POLARIS12:
3878                 adev->mode_info.num_crtc = 5;
3879                 adev->mode_info.num_hpd = 5;
3880                 adev->mode_info.num_dig = 5;
3881                 break;
3882         case CHIP_POLARIS10:
3883         case CHIP_VEGAM:
3884                 adev->mode_info.num_crtc = 6;
3885                 adev->mode_info.num_hpd = 6;
3886                 adev->mode_info.num_dig = 6;
3887                 break;
3888         case CHIP_VEGA10:
3889         case CHIP_VEGA12:
3890         case CHIP_VEGA20:
3891                 adev->mode_info.num_crtc = 6;
3892                 adev->mode_info.num_hpd = 6;
3893                 adev->mode_info.num_dig = 6;
3894                 break;
3895 #if defined(CONFIG_DRM_AMD_DC_DCN)
3896         case CHIP_RAVEN:
3897         case CHIP_RENOIR:
3898         case CHIP_VANGOGH:
3899                 adev->mode_info.num_crtc = 4;
3900                 adev->mode_info.num_hpd = 4;
3901                 adev->mode_info.num_dig = 4;
3902                 break;
3903         case CHIP_NAVI10:
3904         case CHIP_NAVI12:
3905         case CHIP_SIENNA_CICHLID:
3906         case CHIP_NAVY_FLOUNDER:
3907                 adev->mode_info.num_crtc = 6;
3908                 adev->mode_info.num_hpd = 6;
3909                 adev->mode_info.num_dig = 6;
3910                 break;
3911         case CHIP_NAVI14:
3912         case CHIP_DIMGREY_CAVEFISH:
3913                 adev->mode_info.num_crtc = 5;
3914                 adev->mode_info.num_hpd = 5;
3915                 adev->mode_info.num_dig = 5;
3916                 break;
3917 #endif
3918         default:
3919                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
3920                 return -EINVAL;
3921         }
3922
3923         amdgpu_dm_set_irq_funcs(adev);
3924
3925         if (adev->mode_info.funcs == NULL)
3926                 adev->mode_info.funcs = &dm_display_funcs;
3927
3928         /*
3929          * Note: Do NOT change adev->audio_endpt_rreg and
3930          * adev->audio_endpt_wreg because they are initialised in
3931          * amdgpu_device_init()
3932          */
3933 #if defined(CONFIG_DEBUG_KERNEL_DC)
3934         device_create_file(
3935                 adev_to_drm(adev)->dev,
3936                 &dev_attr_s3_debug);
3937 #endif
3938
3939         return 0;
3940 }
3941
3942 static bool modeset_required(struct drm_crtc_state *crtc_state,
3943                              struct dc_stream_state *new_stream,
3944                              struct dc_stream_state *old_stream)
3945 {
3946         return crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
3947 }
3948
3949 static bool modereset_required(struct drm_crtc_state *crtc_state)
3950 {
3951         return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
3952 }
3953
3954 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
3955 {
3956         drm_encoder_cleanup(encoder);
3957         kfree(encoder);
3958 }
3959
3960 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
3961         .destroy = amdgpu_dm_encoder_destroy,
3962 };
3963
3964
3965 static void get_min_max_dc_plane_scaling(struct drm_device *dev,
3966                                          struct drm_framebuffer *fb,
3967                                          int *min_downscale, int *max_upscale)
3968 {
3969         struct amdgpu_device *adev = drm_to_adev(dev);
3970         struct dc *dc = adev->dm.dc;
3971         /* Caps for all supported planes are the same on DCE and DCN 1 - 3 */
3972         struct dc_plane_cap *plane_cap = &dc->caps.planes[0];
3973
3974         switch (fb->format->format) {
3975         case DRM_FORMAT_P010:
3976         case DRM_FORMAT_NV12:
3977         case DRM_FORMAT_NV21:
3978                 *max_upscale = plane_cap->max_upscale_factor.nv12;
3979                 *min_downscale = plane_cap->max_downscale_factor.nv12;
3980                 break;
3981
3982         case DRM_FORMAT_XRGB16161616F:
3983         case DRM_FORMAT_ARGB16161616F:
3984         case DRM_FORMAT_XBGR16161616F:
3985         case DRM_FORMAT_ABGR16161616F:
3986                 *max_upscale = plane_cap->max_upscale_factor.fp16;
3987                 *min_downscale = plane_cap->max_downscale_factor.fp16;
3988                 break;
3989
3990         default:
3991                 *max_upscale = plane_cap->max_upscale_factor.argb8888;
3992                 *min_downscale = plane_cap->max_downscale_factor.argb8888;
3993                 break;
3994         }
3995
3996         /*
3997          * A factor of 1 in the plane_cap means to not allow scaling, ie. use a
3998          * scaling factor of 1.0 == 1000 units.
3999          */
4000         if (*max_upscale == 1)
4001                 *max_upscale = 1000;
4002
4003         if (*min_downscale == 1)
4004                 *min_downscale = 1000;
4005 }
4006
4007
4008 static int fill_dc_scaling_info(const struct drm_plane_state *state,
4009                                 struct dc_scaling_info *scaling_info)
4010 {
4011         int scale_w, scale_h, min_downscale, max_upscale;
4012
4013         memset(scaling_info, 0, sizeof(*scaling_info));
4014
4015         /* Source is fixed 16.16 but we ignore mantissa for now... */
4016         scaling_info->src_rect.x = state->src_x >> 16;
4017         scaling_info->src_rect.y = state->src_y >> 16;
4018
4019         /*
4020          * For reasons we don't (yet) fully understand a non-zero
4021          * src_y coordinate into an NV12 buffer can cause a
4022          * system hang. To avoid hangs (and maybe be overly cautious)
4023          * let's reject both non-zero src_x and src_y.
4024          *
4025          * We currently know of only one use-case to reproduce a
4026          * scenario with non-zero src_x and src_y for NV12, which
4027          * is to gesture the YouTube Android app into full screen
4028          * on ChromeOS.
4029          */
4030         if (state->fb &&
4031             state->fb->format->format == DRM_FORMAT_NV12 &&
4032             (scaling_info->src_rect.x != 0 ||
4033              scaling_info->src_rect.y != 0))
4034                 return -EINVAL;
4035
4036         scaling_info->src_rect.width = state->src_w >> 16;
4037         if (scaling_info->src_rect.width == 0)
4038                 return -EINVAL;
4039
4040         scaling_info->src_rect.height = state->src_h >> 16;
4041         if (scaling_info->src_rect.height == 0)
4042                 return -EINVAL;
4043
4044         scaling_info->dst_rect.x = state->crtc_x;
4045         scaling_info->dst_rect.y = state->crtc_y;
4046
4047         if (state->crtc_w == 0)
4048                 return -EINVAL;
4049
4050         scaling_info->dst_rect.width = state->crtc_w;
4051
4052         if (state->crtc_h == 0)
4053                 return -EINVAL;
4054
4055         scaling_info->dst_rect.height = state->crtc_h;
4056
4057         /* DRM doesn't specify clipping on destination output. */
4058         scaling_info->clip_rect = scaling_info->dst_rect;
4059
4060         /* Validate scaling per-format with DC plane caps */
4061         if (state->plane && state->plane->dev && state->fb) {
4062                 get_min_max_dc_plane_scaling(state->plane->dev, state->fb,
4063                                              &min_downscale, &max_upscale);
4064         } else {
4065                 min_downscale = 250;
4066                 max_upscale = 16000;
4067         }
4068
4069         scale_w = scaling_info->dst_rect.width * 1000 /
4070                   scaling_info->src_rect.width;
4071
4072         if (scale_w < min_downscale || scale_w > max_upscale)
4073                 return -EINVAL;
4074
4075         scale_h = scaling_info->dst_rect.height * 1000 /
4076                   scaling_info->src_rect.height;
4077
4078         if (scale_h < min_downscale || scale_h > max_upscale)
4079                 return -EINVAL;
4080
4081         /*
4082          * The "scaling_quality" can be ignored for now, quality = 0 has DC
4083          * assume reasonable defaults based on the format.
4084          */
4085
4086         return 0;
4087 }
4088
4089 static void
4090 fill_gfx8_tiling_info_from_flags(union dc_tiling_info *tiling_info,
4091                                  uint64_t tiling_flags)
4092 {
4093         /* Fill GFX8 params */
4094         if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
4095                 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
4096
4097                 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
4098                 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
4099                 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
4100                 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
4101                 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
4102
4103                 /* XXX fix me for VI */
4104                 tiling_info->gfx8.num_banks = num_banks;
4105                 tiling_info->gfx8.array_mode =
4106                                 DC_ARRAY_2D_TILED_THIN1;
4107                 tiling_info->gfx8.tile_split = tile_split;
4108                 tiling_info->gfx8.bank_width = bankw;
4109                 tiling_info->gfx8.bank_height = bankh;
4110                 tiling_info->gfx8.tile_aspect = mtaspect;
4111                 tiling_info->gfx8.tile_mode =
4112                                 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
4113         } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
4114                         == DC_ARRAY_1D_TILED_THIN1) {
4115                 tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
4116         }
4117
4118         tiling_info->gfx8.pipe_config =
4119                         AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
4120 }
4121
4122 static void
4123 fill_gfx9_tiling_info_from_device(const struct amdgpu_device *adev,
4124                                   union dc_tiling_info *tiling_info)
4125 {
4126         tiling_info->gfx9.num_pipes =
4127                 adev->gfx.config.gb_addr_config_fields.num_pipes;
4128         tiling_info->gfx9.num_banks =
4129                 adev->gfx.config.gb_addr_config_fields.num_banks;
4130         tiling_info->gfx9.pipe_interleave =
4131                 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
4132         tiling_info->gfx9.num_shader_engines =
4133                 adev->gfx.config.gb_addr_config_fields.num_se;
4134         tiling_info->gfx9.max_compressed_frags =
4135                 adev->gfx.config.gb_addr_config_fields.max_compress_frags;
4136         tiling_info->gfx9.num_rb_per_se =
4137                 adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
4138         tiling_info->gfx9.shaderEnable = 1;
4139         if (adev->asic_type == CHIP_SIENNA_CICHLID ||
4140             adev->asic_type == CHIP_NAVY_FLOUNDER ||
4141             adev->asic_type == CHIP_DIMGREY_CAVEFISH ||
4142             adev->asic_type == CHIP_VANGOGH)
4143                 tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;
4144 }
4145
4146 static int
4147 validate_dcc(struct amdgpu_device *adev,
4148              const enum surface_pixel_format format,
4149              const enum dc_rotation_angle rotation,
4150              const union dc_tiling_info *tiling_info,
4151              const struct dc_plane_dcc_param *dcc,
4152              const struct dc_plane_address *address,
4153              const struct plane_size *plane_size)
4154 {
4155         struct dc *dc = adev->dm.dc;
4156         struct dc_dcc_surface_param input;
4157         struct dc_surface_dcc_cap output;
4158
4159         memset(&input, 0, sizeof(input));
4160         memset(&output, 0, sizeof(output));
4161
4162         if (!dcc->enable)
4163                 return 0;
4164
4165         if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN ||
4166             !dc->cap_funcs.get_dcc_compression_cap)
4167                 return -EINVAL;
4168
4169         input.format = format;
4170         input.surface_size.width = plane_size->surface_size.width;
4171         input.surface_size.height = plane_size->surface_size.height;
4172         input.swizzle_mode = tiling_info->gfx9.swizzle;
4173
4174         if (rotation == ROTATION_ANGLE_0 || rotation == ROTATION_ANGLE_180)
4175                 input.scan = SCAN_DIRECTION_HORIZONTAL;
4176         else if (rotation == ROTATION_ANGLE_90 || rotation == ROTATION_ANGLE_270)
4177                 input.scan = SCAN_DIRECTION_VERTICAL;
4178
4179         if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output))
4180                 return -EINVAL;
4181
4182         if (!output.capable)
4183                 return -EINVAL;
4184
4185         if (dcc->independent_64b_blks == 0 &&
4186             output.grph.rgb.independent_64b_blks != 0)
4187                 return -EINVAL;
4188
4189         return 0;
4190 }
4191
4192 static bool
4193 modifier_has_dcc(uint64_t modifier)
4194 {
4195         return IS_AMD_FMT_MOD(modifier) && AMD_FMT_MOD_GET(DCC, modifier);
4196 }
4197
4198 static unsigned
4199 modifier_gfx9_swizzle_mode(uint64_t modifier)
4200 {
4201         if (modifier == DRM_FORMAT_MOD_LINEAR)
4202                 return 0;
4203
4204         return AMD_FMT_MOD_GET(TILE, modifier);
4205 }
4206
4207 static const struct drm_format_info *
4208 amd_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
4209 {
4210         return amdgpu_lookup_format_info(cmd->pixel_format, cmd->modifier[0]);
4211 }
4212
4213 static void
4214 fill_gfx9_tiling_info_from_modifier(const struct amdgpu_device *adev,
4215                                     union dc_tiling_info *tiling_info,
4216                                     uint64_t modifier)
4217 {
4218         unsigned int mod_bank_xor_bits = AMD_FMT_MOD_GET(BANK_XOR_BITS, modifier);
4219         unsigned int mod_pipe_xor_bits = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier);
4220         unsigned int pkrs_log2 = AMD_FMT_MOD_GET(PACKERS, modifier);
4221         unsigned int pipes_log2 = min(4u, mod_pipe_xor_bits);
4222
4223         fill_gfx9_tiling_info_from_device(adev, tiling_info);
4224
4225         if (!IS_AMD_FMT_MOD(modifier))
4226                 return;
4227
4228         tiling_info->gfx9.num_pipes = 1u << pipes_log2;
4229         tiling_info->gfx9.num_shader_engines = 1u << (mod_pipe_xor_bits - pipes_log2);
4230
4231         if (adev->family >= AMDGPU_FAMILY_NV) {
4232                 tiling_info->gfx9.num_pkrs = 1u << pkrs_log2;
4233         } else {
4234                 tiling_info->gfx9.num_banks = 1u << mod_bank_xor_bits;
4235
4236                 /* for DCC we know it isn't rb aligned, so rb_per_se doesn't matter. */
4237         }
4238 }
4239
4240 enum dm_micro_swizzle {
4241         MICRO_SWIZZLE_Z = 0,
4242         MICRO_SWIZZLE_S = 1,
4243         MICRO_SWIZZLE_D = 2,
4244         MICRO_SWIZZLE_R = 3
4245 };
4246
4247 static bool dm_plane_format_mod_supported(struct drm_plane *plane,
4248                                           uint32_t format,
4249                                           uint64_t modifier)
4250 {
4251         struct amdgpu_device *adev = drm_to_adev(plane->dev);
4252         const struct drm_format_info *info = drm_format_info(format);
4253         int i;
4254
4255         enum dm_micro_swizzle microtile = modifier_gfx9_swizzle_mode(modifier) & 3;
4256
4257         if (!info)
4258                 return false;
4259
4260         /*
4261          * We always have to allow these modifiers:
4262          * 1. Core DRM checks for LINEAR support if userspace does not provide modifiers.
4263          * 2. Not passing any modifiers is the same as explicitly passing INVALID.
4264          */
4265         if (modifier == DRM_FORMAT_MOD_LINEAR ||
4266             modifier == DRM_FORMAT_MOD_INVALID) {
4267                 return true;
4268         }
4269
4270         /* Check that the modifier is on the list of the plane's supported modifiers. */
4271         for (i = 0; i < plane->modifier_count; i++) {
4272                 if (modifier == plane->modifiers[i])
4273                         break;
4274         }
4275         if (i == plane->modifier_count)
4276                 return false;
4277
4278         /*
4279          * For D swizzle the canonical modifier depends on the bpp, so check
4280          * it here.
4281          */
4282         if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) == AMD_FMT_MOD_TILE_VER_GFX9 &&
4283             adev->family >= AMDGPU_FAMILY_NV) {
4284                 if (microtile == MICRO_SWIZZLE_D && info->cpp[0] == 4)
4285                         return false;
4286         }
4287
4288         if (adev->family >= AMDGPU_FAMILY_RV && microtile == MICRO_SWIZZLE_D &&
4289             info->cpp[0] < 8)
4290                 return false;
4291
4292         if (modifier_has_dcc(modifier)) {
4293                 /* Per radeonsi comments 16/64 bpp are more complicated. */
4294                 if (info->cpp[0] != 4)
4295                         return false;
4296                 /* We support multi-planar formats, but not when combined with
4297                  * additional DCC metadata planes. */
4298                 if (info->num_planes > 1)
4299                         return false;
4300         }
4301
4302         return true;
4303 }
4304
4305 static void
4306 add_modifier(uint64_t **mods, uint64_t *size, uint64_t *cap, uint64_t mod)
4307 {
4308         if (!*mods)
4309                 return;
4310
4311         if (*cap - *size < 1) {
4312                 uint64_t new_cap = *cap * 2;
4313                 uint64_t *new_mods = kmalloc(new_cap * sizeof(uint64_t), GFP_KERNEL);
4314
4315                 if (!new_mods) {
4316                         kfree(*mods);
4317                         *mods = NULL;
4318                         return;
4319                 }
4320
4321                 memcpy(new_mods, *mods, sizeof(uint64_t) * *size);
4322                 kfree(*mods);
4323                 *mods = new_mods;
4324                 *cap = new_cap;
4325         }
4326
4327         (*mods)[*size] = mod;
4328         *size += 1;
4329 }
4330
4331 static void
4332 add_gfx9_modifiers(const struct amdgpu_device *adev,
4333                    uint64_t **mods, uint64_t *size, uint64_t *capacity)
4334 {
4335         int pipes = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes);
4336         int pipe_xor_bits = min(8, pipes +
4337                                 ilog2(adev->gfx.config.gb_addr_config_fields.num_se));
4338         int bank_xor_bits = min(8 - pipe_xor_bits,
4339                                 ilog2(adev->gfx.config.gb_addr_config_fields.num_banks));
4340         int rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) +
4341                  ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se);
4342
4343
4344         if (adev->family == AMDGPU_FAMILY_RV) {
4345                 /* Raven2 and later */
4346                 bool has_constant_encode = adev->asic_type > CHIP_RAVEN || adev->external_rev_id >= 0x81;
4347
4348                 /*
4349                  * No _D DCC swizzles yet because we only allow 32bpp, which
4350                  * doesn't support _D on DCN
4351                  */
4352
4353                 if (has_constant_encode) {
4354                         add_modifier(mods, size, capacity, AMD_FMT_MOD |
4355                                     AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
4356                                     AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
4357                                     AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4358                                     AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
4359                                     AMD_FMT_MOD_SET(DCC, 1) |
4360                                     AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
4361                                     AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) |
4362                                     AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1));
4363                 }
4364
4365                 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4366                             AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
4367                             AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
4368                             AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4369                             AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
4370                             AMD_FMT_MOD_SET(DCC, 1) |
4371                             AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
4372                             AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) |
4373                             AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 0));
4374
4375                 if (has_constant_encode) {
4376                         add_modifier(mods, size, capacity, AMD_FMT_MOD |
4377                                     AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
4378                                     AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
4379                                     AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4380                                     AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
4381                                     AMD_FMT_MOD_SET(DCC, 1) |
4382                                     AMD_FMT_MOD_SET(DCC_RETILE, 1) |
4383                                     AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
4384                                     AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) |
4385
4386                                     AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
4387                                     AMD_FMT_MOD_SET(RB, rb) |
4388                                     AMD_FMT_MOD_SET(PIPE, pipes));
4389                 }
4390
4391                 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4392                             AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
4393                             AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
4394                             AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4395                             AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
4396                             AMD_FMT_MOD_SET(DCC, 1) |
4397                             AMD_FMT_MOD_SET(DCC_RETILE, 1) |
4398                             AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
4399                             AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) |
4400                             AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 0) |
4401                             AMD_FMT_MOD_SET(RB, rb) |
4402                             AMD_FMT_MOD_SET(PIPE, pipes));
4403         }
4404
4405         /*
4406          * Only supported for 64bpp on Raven, will be filtered on format in
4407          * dm_plane_format_mod_supported.
4408          */
4409         add_modifier(mods, size, capacity, AMD_FMT_MOD |
4410                     AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D_X) |
4411                     AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
4412                     AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4413                     AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits));
4414
4415         if (adev->family == AMDGPU_FAMILY_RV) {
4416                 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4417                             AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
4418                             AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
4419                             AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4420                             AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits));
4421         }
4422
4423         /*
4424          * Only supported for 64bpp on Raven, will be filtered on format in
4425          * dm_plane_format_mod_supported.
4426          */
4427         add_modifier(mods, size, capacity, AMD_FMT_MOD |
4428                     AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) |
4429                     AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
4430
4431         if (adev->family == AMDGPU_FAMILY_RV) {
4432                 add_modifier(mods, size, capacity, AMD_FMT_MOD |
4433                             AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) |
4434                             AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
4435         }
4436 }
4437
4438 static void
4439 add_gfx10_1_modifiers(const struct amdgpu_device *adev,
4440                       uint64_t **mods, uint64_t *size, uint64_t *capacity)
4441 {
4442         int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes);
4443
4444         add_modifier(mods, size, capacity, AMD_FMT_MOD |
4445                     AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
4446                     AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) |
4447                     AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4448                     AMD_FMT_MOD_SET(DCC, 1) |
4449                     AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
4450                     AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
4451                     AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
4452
4453         add_modifier(mods, size, capacity, AMD_FMT_MOD |
4454                     AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
4455                     AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) |
4456                     AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4457                     AMD_FMT_MOD_SET(DCC, 1) |
4458                     AMD_FMT_MOD_SET(DCC_RETILE, 1) |
4459                     AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
4460                     AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
4461                     AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
4462
4463         add_modifier(mods, size, capacity, AMD_FMT_MOD |
4464                     AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
4465                     AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) |
4466                     AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits));
4467
4468         add_modifier(mods, size, capacity, AMD_FMT_MOD |
4469                     AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
4470                     AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) |
4471                     AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits));
4472
4473
4474         /* Only supported for 64bpp, will be filtered in dm_plane_format_mod_supported */
4475         add_modifier(mods, size, capacity, AMD_FMT_MOD |
4476                     AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) |
4477                     AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
4478
4479         add_modifier(mods, size, capacity, AMD_FMT_MOD |
4480                     AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) |
4481                     AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
4482 }
4483
4484 static void
4485 add_gfx10_3_modifiers(const struct amdgpu_device *adev,
4486                       uint64_t **mods, uint64_t *size, uint64_t *capacity)
4487 {
4488         int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes);
4489         int pkrs = ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs);
4490
4491         add_modifier(mods, size, capacity, AMD_FMT_MOD |
4492                     AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
4493                     AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
4494                     AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4495                     AMD_FMT_MOD_SET(PACKERS, pkrs) |
4496                     AMD_FMT_MOD_SET(DCC, 1) |
4497                     AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
4498                     AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
4499                     AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
4500                     AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
4501
4502         add_modifier(mods, size, capacity, AMD_FMT_MOD |
4503                     AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
4504                     AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
4505                     AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4506                     AMD_FMT_MOD_SET(PACKERS, pkrs) |
4507                     AMD_FMT_MOD_SET(DCC, 1) |
4508                     AMD_FMT_MOD_SET(DCC_RETILE, 1) |
4509                     AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
4510                     AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
4511                     AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
4512                     AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
4513
4514         add_modifier(mods, size, capacity, AMD_FMT_MOD |
4515                     AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
4516                     AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
4517                     AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4518                     AMD_FMT_MOD_SET(PACKERS, pkrs));
4519
4520         add_modifier(mods, size, capacity, AMD_FMT_MOD |
4521                     AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
4522                     AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
4523                     AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
4524                     AMD_FMT_MOD_SET(PACKERS, pkrs));
4525
4526         /* Only supported for 64bpp, will be filtered in dm_plane_format_mod_supported */
4527         add_modifier(mods, size, capacity, AMD_FMT_MOD |
4528                     AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) |
4529                     AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
4530
4531         add_modifier(mods, size, capacity, AMD_FMT_MOD |
4532                     AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) |
4533                     AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
4534 }
4535
4536 static int
4537 get_plane_modifiers(const struct amdgpu_device *adev, unsigned int plane_type, uint64_t **mods)
4538 {
4539         uint64_t size = 0, capacity = 128;
4540         *mods = NULL;
4541
4542         /* We have not hooked up any pre-GFX9 modifiers. */
4543         if (adev->family < AMDGPU_FAMILY_AI)
4544                 return 0;
4545
4546         *mods = kmalloc(capacity * sizeof(uint64_t), GFP_KERNEL);
4547
4548         if (plane_type == DRM_PLANE_TYPE_CURSOR) {
4549                 add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_LINEAR);
4550                 add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_INVALID);
4551                 return *mods ? 0 : -ENOMEM;
4552         }
4553
4554         switch (adev->family) {
4555         case AMDGPU_FAMILY_AI:
4556         case AMDGPU_FAMILY_RV:
4557                 add_gfx9_modifiers(adev, mods, &size, &capacity);
4558                 break;
4559         case AMDGPU_FAMILY_NV:
4560         case AMDGPU_FAMILY_VGH:
4561                 if (adev->asic_type >= CHIP_SIENNA_CICHLID)
4562                         add_gfx10_3_modifiers(adev, mods, &size, &capacity);
4563                 else
4564                         add_gfx10_1_modifiers(adev, mods, &size, &capacity);
4565                 break;
4566         }
4567
4568         add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_LINEAR);
4569
4570         /* INVALID marks the end of the list. */
4571         add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_INVALID);
4572
4573         if (!*mods)
4574                 return -ENOMEM;
4575
4576         return 0;
4577 }
4578
4579 static int
4580 fill_gfx9_plane_attributes_from_modifiers(struct amdgpu_device *adev,
4581                                           const struct amdgpu_framebuffer *afb,
4582                                           const enum surface_pixel_format format,
4583                                           const enum dc_rotation_angle rotation,
4584                                           const struct plane_size *plane_size,
4585                                           union dc_tiling_info *tiling_info,
4586                                           struct dc_plane_dcc_param *dcc,
4587                                           struct dc_plane_address *address,
4588                                           const bool force_disable_dcc)
4589 {
4590         const uint64_t modifier = afb->base.modifier;
4591         int ret;
4592
4593         fill_gfx9_tiling_info_from_modifier(adev, tiling_info, modifier);
4594         tiling_info->gfx9.swizzle = modifier_gfx9_swizzle_mode(modifier);
4595
4596         if (modifier_has_dcc(modifier) && !force_disable_dcc) {
4597                 uint64_t dcc_address = afb->address + afb->base.offsets[1];
4598
4599                 dcc->enable = 1;
4600                 dcc->meta_pitch = afb->base.pitches[1];
4601                 dcc->independent_64b_blks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier);
4602
4603                 address->grph.meta_addr.low_part = lower_32_bits(dcc_address);
4604                 address->grph.meta_addr.high_part = upper_32_bits(dcc_address);
4605         }
4606
4607         ret = validate_dcc(adev, format, rotation, tiling_info, dcc, address, plane_size);
4608         if (ret)
4609                 return ret;
4610
4611         return 0;
4612 }
4613
4614 static int
4615 fill_plane_buffer_attributes(struct amdgpu_device *adev,
4616                              const struct amdgpu_framebuffer *afb,
4617                              const enum surface_pixel_format format,
4618                              const enum dc_rotation_angle rotation,
4619                              const uint64_t tiling_flags,
4620                              union dc_tiling_info *tiling_info,
4621                              struct plane_size *plane_size,
4622                              struct dc_plane_dcc_param *dcc,
4623                              struct dc_plane_address *address,
4624                              bool tmz_surface,
4625                              bool force_disable_dcc)
4626 {
4627         const struct drm_framebuffer *fb = &afb->base;
4628         int ret;
4629
4630         memset(tiling_info, 0, sizeof(*tiling_info));
4631         memset(plane_size, 0, sizeof(*plane_size));
4632         memset(dcc, 0, sizeof(*dcc));
4633         memset(address, 0, sizeof(*address));
4634
4635         address->tmz_surface = tmz_surface;
4636
4637         if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
4638                 uint64_t addr = afb->address + fb->offsets[0];
4639
4640                 plane_size->surface_size.x = 0;
4641                 plane_size->surface_size.y = 0;
4642                 plane_size->surface_size.width = fb->width;
4643                 plane_size->surface_size.height = fb->height;
4644                 plane_size->surface_pitch =
4645                         fb->pitches[0] / fb->format->cpp[0];
4646
4647                 address->type = PLN_ADDR_TYPE_GRAPHICS;
4648                 address->grph.addr.low_part = lower_32_bits(addr);
4649                 address->grph.addr.high_part = upper_32_bits(addr);
4650         } else if (format < SURFACE_PIXEL_FORMAT_INVALID) {
4651                 uint64_t luma_addr = afb->address + fb->offsets[0];
4652                 uint64_t chroma_addr = afb->address + fb->offsets[1];
4653
4654                 plane_size->surface_size.x = 0;
4655                 plane_size->surface_size.y = 0;
4656                 plane_size->surface_size.width = fb->width;
4657                 plane_size->surface_size.height = fb->height;
4658                 plane_size->surface_pitch =
4659                         fb->pitches[0] / fb->format->cpp[0];
4660
4661                 plane_size->chroma_size.x = 0;
4662                 plane_size->chroma_size.y = 0;
4663                 /* TODO: set these based on surface format */
4664                 plane_size->chroma_size.width = fb->width / 2;
4665                 plane_size->chroma_size.height = fb->height / 2;
4666
4667                 plane_size->chroma_pitch =
4668                         fb->pitches[1] / fb->format->cpp[1];
4669
4670                 address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
4671                 address->video_progressive.luma_addr.low_part =
4672                         lower_32_bits(luma_addr);
4673                 address->video_progressive.luma_addr.high_part =
4674                         upper_32_bits(luma_addr);
4675                 address->video_progressive.chroma_addr.low_part =
4676                         lower_32_bits(chroma_addr);
4677                 address->video_progressive.chroma_addr.high_part =
4678                         upper_32_bits(chroma_addr);
4679         }
4680
4681         if (adev->family >= AMDGPU_FAMILY_AI) {
4682                 ret = fill_gfx9_plane_attributes_from_modifiers(adev, afb, format,
4683                                                                 rotation, plane_size,
4684                                                                 tiling_info, dcc,
4685                                                                 address,
4686                                                                 force_disable_dcc);
4687                 if (ret)
4688                         return ret;
4689         } else {
4690                 fill_gfx8_tiling_info_from_flags(tiling_info, tiling_flags);
4691         }
4692
4693         return 0;
4694 }
4695
4696 static void
4697 fill_blending_from_plane_state(const struct drm_plane_state *plane_state,
4698                                bool *per_pixel_alpha, bool *global_alpha,
4699                                int *global_alpha_value)
4700 {
4701         *per_pixel_alpha = false;
4702         *global_alpha = false;
4703         *global_alpha_value = 0xff;
4704
4705         if (plane_state->plane->type != DRM_PLANE_TYPE_OVERLAY)
4706                 return;
4707
4708         if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) {
4709                 static const uint32_t alpha_formats[] = {
4710                         DRM_FORMAT_ARGB8888,
4711                         DRM_FORMAT_RGBA8888,
4712                         DRM_FORMAT_ABGR8888,
4713                 };
4714                 uint32_t format = plane_state->fb->format->format;
4715                 unsigned int i;
4716
4717                 for (i = 0; i < ARRAY_SIZE(alpha_formats); ++i) {
4718                         if (format == alpha_formats[i]) {
4719                                 *per_pixel_alpha = true;
4720                                 break;
4721                         }
4722                 }
4723         }
4724
4725         if (plane_state->alpha < 0xffff) {
4726                 *global_alpha = true;
4727                 *global_alpha_value = plane_state->alpha >> 8;
4728         }
4729 }
4730
4731 static int
4732 fill_plane_color_attributes(const struct drm_plane_state *plane_state,
4733                             const enum surface_pixel_format format,
4734                             enum dc_color_space *color_space)
4735 {
4736         bool full_range;
4737
4738         *color_space = COLOR_SPACE_SRGB;
4739
4740         /* DRM color properties only affect non-RGB formats. */
4741         if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
4742                 return 0;
4743
4744         full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
4745
4746         switch (plane_state->color_encoding) {
4747         case DRM_COLOR_YCBCR_BT601:
4748                 if (full_range)
4749                         *color_space = COLOR_SPACE_YCBCR601;
4750                 else
4751                         *color_space = COLOR_SPACE_YCBCR601_LIMITED;
4752                 break;
4753
4754         case DRM_COLOR_YCBCR_BT709:
4755                 if (full_range)
4756                         *color_space = COLOR_SPACE_YCBCR709;
4757                 else
4758                         *color_space = COLOR_SPACE_YCBCR709_LIMITED;
4759                 break;
4760
4761         case DRM_COLOR_YCBCR_BT2020:
4762                 if (full_range)
4763                         *color_space = COLOR_SPACE_2020_YCBCR;
4764                 else
4765                         return -EINVAL;
4766                 break;
4767
4768         default:
4769                 return -EINVAL;
4770         }
4771
4772         return 0;
4773 }
4774
4775 static int
4776 fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
4777                             const struct drm_plane_state *plane_state,
4778                             const uint64_t tiling_flags,
4779                             struct dc_plane_info *plane_info,
4780                             struct dc_plane_address *address,
4781                             bool tmz_surface,
4782                             bool force_disable_dcc)
4783 {
4784         const struct drm_framebuffer *fb = plane_state->fb;
4785         const struct amdgpu_framebuffer *afb =
4786                 to_amdgpu_framebuffer(plane_state->fb);
4787         int ret;
4788
4789         memset(plane_info, 0, sizeof(*plane_info));
4790
4791         switch (fb->format->format) {
4792         case DRM_FORMAT_C8:
4793                 plane_info->format =
4794                         SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
4795                 break;
4796         case DRM_FORMAT_RGB565:
4797                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
4798                 break;
4799         case DRM_FORMAT_XRGB8888:
4800         case DRM_FORMAT_ARGB8888:
4801                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
4802                 break;
4803         case DRM_FORMAT_XRGB2101010:
4804         case DRM_FORMAT_ARGB2101010:
4805                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
4806                 break;
4807         case DRM_FORMAT_XBGR2101010:
4808         case DRM_FORMAT_ABGR2101010:
4809                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
4810                 break;
4811         case DRM_FORMAT_XBGR8888:
4812         case DRM_FORMAT_ABGR8888:
4813                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
4814                 break;
4815         case DRM_FORMAT_NV21:
4816                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
4817                 break;
4818         case DRM_FORMAT_NV12:
4819                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
4820                 break;
4821         case DRM_FORMAT_P010:
4822                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb;
4823                 break;
4824         case DRM_FORMAT_XRGB16161616F:
4825         case DRM_FORMAT_ARGB16161616F:
4826                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F;
4827                 break;
4828         case DRM_FORMAT_XBGR16161616F:
4829         case DRM_FORMAT_ABGR16161616F:
4830                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;
4831                 break;
4832         default:
4833                 DRM_ERROR(
4834                         "Unsupported screen format %p4cc\n",
4835                         &fb->format->format);
4836                 return -EINVAL;
4837         }
4838
4839         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
4840         case DRM_MODE_ROTATE_0:
4841                 plane_info->rotation = ROTATION_ANGLE_0;
4842                 break;
4843         case DRM_MODE_ROTATE_90:
4844                 plane_info->rotation = ROTATION_ANGLE_90;
4845                 break;
4846         case DRM_MODE_ROTATE_180:
4847                 plane_info->rotation = ROTATION_ANGLE_180;
4848                 break;
4849         case DRM_MODE_ROTATE_270:
4850                 plane_info->rotation = ROTATION_ANGLE_270;
4851                 break;
4852         default:
4853                 plane_info->rotation = ROTATION_ANGLE_0;
4854                 break;
4855         }
4856
4857         plane_info->visible = true;
4858         plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
4859
4860         plane_info->layer_index = 0;
4861
4862         ret = fill_plane_color_attributes(plane_state, plane_info->format,
4863                                           &plane_info->color_space);
4864         if (ret)
4865                 return ret;
4866
4867         ret = fill_plane_buffer_attributes(adev, afb, plane_info->format,
4868                                            plane_info->rotation, tiling_flags,
4869                                            &plane_info->tiling_info,
4870                                            &plane_info->plane_size,
4871                                            &plane_info->dcc, address, tmz_surface,
4872                                            force_disable_dcc);
4873         if (ret)
4874                 return ret;
4875
4876         fill_blending_from_plane_state(
4877                 plane_state, &plane_info->per_pixel_alpha,
4878                 &plane_info->global_alpha, &plane_info->global_alpha_value);
4879
4880         return 0;
4881 }
4882
4883 static int fill_dc_plane_attributes(struct amdgpu_device *adev,
4884                                     struct dc_plane_state *dc_plane_state,
4885                                     struct drm_plane_state *plane_state,
4886                                     struct drm_crtc_state *crtc_state)
4887 {
4888         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
4889         struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb;
4890         struct dc_scaling_info scaling_info;
4891         struct dc_plane_info plane_info;
4892         int ret;
4893         bool force_disable_dcc = false;
4894
4895         ret = fill_dc_scaling_info(plane_state, &scaling_info);
4896         if (ret)
4897                 return ret;
4898
4899         dc_plane_state->src_rect = scaling_info.src_rect;
4900         dc_plane_state->dst_rect = scaling_info.dst_rect;
4901         dc_plane_state->clip_rect = scaling_info.clip_rect;
4902         dc_plane_state->scaling_quality = scaling_info.scaling_quality;
4903
4904         force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
4905         ret = fill_dc_plane_info_and_addr(adev, plane_state,
4906                                           afb->tiling_flags,
4907                                           &plane_info,
4908                                           &dc_plane_state->address,
4909                                           afb->tmz_surface,
4910                                           force_disable_dcc);
4911         if (ret)
4912                 return ret;
4913
4914         dc_plane_state->format = plane_info.format;
4915         dc_plane_state->color_space = plane_info.color_space;
4916         dc_plane_state->format = plane_info.format;
4917         dc_plane_state->plane_size = plane_info.plane_size;
4918         dc_plane_state->rotation = plane_info.rotation;
4919         dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
4920         dc_plane_state->stereo_format = plane_info.stereo_format;
4921         dc_plane_state->tiling_info = plane_info.tiling_info;
4922         dc_plane_state->visible = plane_info.visible;
4923         dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
4924         dc_plane_state->global_alpha = plane_info.global_alpha;
4925         dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
4926         dc_plane_state->dcc = plane_info.dcc;
4927         dc_plane_state->layer_index = plane_info.layer_index; // Always returns 0
4928         dc_plane_state->flip_int_enabled = true;
4929
4930         /*
4931          * Always set input transfer function, since plane state is refreshed
4932          * every time.
4933          */
4934         ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
4935         if (ret)
4936                 return ret;
4937
4938         return 0;
4939 }
4940
4941 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
4942                                            const struct dm_connector_state *dm_state,
4943                                            struct dc_stream_state *stream)
4944 {
4945         enum amdgpu_rmx_type rmx_type;
4946
4947         struct rect src = { 0 }; /* viewport in composition space*/
4948         struct rect dst = { 0 }; /* stream addressable area */
4949
4950         /* no mode. nothing to be done */
4951         if (!mode)
4952                 return;
4953
4954         /* Full screen scaling by default */
4955         src.width = mode->hdisplay;
4956         src.height = mode->vdisplay;
4957         dst.width = stream->timing.h_addressable;
4958         dst.height = stream->timing.v_addressable;
4959
4960         if (dm_state) {
4961                 rmx_type = dm_state->scaling;
4962                 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
4963                         if (src.width * dst.height <
4964                                         src.height * dst.width) {
4965                                 /* height needs less upscaling/more downscaling */
4966                                 dst.width = src.width *
4967                                                 dst.height / src.height;
4968                         } else {
4969                                 /* width needs less upscaling/more downscaling */
4970                                 dst.height = src.height *
4971                                                 dst.width / src.width;
4972                         }
4973                 } else if (rmx_type == RMX_CENTER) {
4974                         dst = src;
4975                 }
4976
4977                 dst.x = (stream->timing.h_addressable - dst.width) / 2;
4978                 dst.y = (stream->timing.v_addressable - dst.height) / 2;
4979
4980                 if (dm_state->underscan_enable) {
4981                         dst.x += dm_state->underscan_hborder / 2;
4982                         dst.y += dm_state->underscan_vborder / 2;
4983                         dst.width -= dm_state->underscan_hborder;
4984                         dst.height -= dm_state->underscan_vborder;
4985                 }
4986         }
4987
4988         stream->src = src;
4989         stream->dst = dst;
4990
4991         DRM_DEBUG_KMS("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",
4992                       dst.x, dst.y, dst.width, dst.height);
4993
4994 }
4995
4996 static enum dc_color_depth
4997 convert_color_depth_from_display_info(const struct drm_connector *connector,
4998                                       bool is_y420, int requested_bpc)
4999 {
5000         uint8_t bpc;
5001
5002         if (is_y420) {
5003                 bpc = 8;
5004
5005                 /* Cap display bpc based on HDMI 2.0 HF-VSDB */
5006                 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)
5007                         bpc = 16;
5008                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
5009                         bpc = 12;
5010                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
5011                         bpc = 10;
5012         } else {
5013                 bpc = (uint8_t)connector->display_info.bpc;
5014                 /* Assume 8 bpc by default if no bpc is specified. */
5015                 bpc = bpc ? bpc : 8;
5016         }
5017
5018         if (requested_bpc > 0) {
5019                 /*
5020                  * Cap display bpc based on the user requested value.
5021                  *
5022                  * The value for state->max_bpc may not correctly updated
5023                  * depending on when the connector gets added to the state
5024                  * or if this was called outside of atomic check, so it
5025                  * can't be used directly.
5026                  */
5027                 bpc = min_t(u8, bpc, requested_bpc);
5028
5029                 /* Round down to the nearest even number. */
5030                 bpc = bpc - (bpc & 1);
5031         }
5032
5033         switch (bpc) {
5034         case 0:
5035                 /*
5036                  * Temporary Work around, DRM doesn't parse color depth for
5037                  * EDID revision before 1.4
5038                  * TODO: Fix edid parsing
5039                  */
5040                 return COLOR_DEPTH_888;
5041         case 6:
5042                 return COLOR_DEPTH_666;
5043         case 8:
5044                 return COLOR_DEPTH_888;
5045         case 10:
5046                 return COLOR_DEPTH_101010;
5047         case 12:
5048                 return COLOR_DEPTH_121212;
5049         case 14:
5050                 return COLOR_DEPTH_141414;
5051         case 16:
5052                 return COLOR_DEPTH_161616;
5053         default:
5054                 return COLOR_DEPTH_UNDEFINED;
5055         }
5056 }
5057
5058 static enum dc_aspect_ratio
5059 get_aspect_ratio(const struct drm_display_mode *mode_in)
5060 {
5061         /* 1-1 mapping, since both enums follow the HDMI spec. */
5062         return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
5063 }
5064
5065 static enum dc_color_space
5066 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
5067 {
5068         enum dc_color_space color_space = COLOR_SPACE_SRGB;
5069
5070         switch (dc_crtc_timing->pixel_encoding) {
5071         case PIXEL_ENCODING_YCBCR422:
5072         case PIXEL_ENCODING_YCBCR444:
5073         case PIXEL_ENCODING_YCBCR420:
5074         {
5075                 /*
5076                  * 27030khz is the separation point between HDTV and SDTV
5077                  * according to HDMI spec, we use YCbCr709 and YCbCr601
5078                  * respectively
5079                  */
5080                 if (dc_crtc_timing->pix_clk_100hz > 270300) {
5081                         if (dc_crtc_timing->flags.Y_ONLY)
5082                                 color_space =
5083                                         COLOR_SPACE_YCBCR709_LIMITED;
5084                         else
5085                                 color_space = COLOR_SPACE_YCBCR709;
5086                 } else {
5087                         if (dc_crtc_timing->flags.Y_ONLY)
5088                                 color_space =
5089                                         COLOR_SPACE_YCBCR601_LIMITED;
5090                         else
5091                                 color_space = COLOR_SPACE_YCBCR601;
5092                 }
5093
5094         }
5095         break;
5096         case PIXEL_ENCODING_RGB:
5097                 color_space = COLOR_SPACE_SRGB;
5098                 break;
5099
5100         default:
5101                 WARN_ON(1);
5102                 break;
5103         }
5104
5105         return color_space;
5106 }
5107
5108 static bool adjust_colour_depth_from_display_info(
5109         struct dc_crtc_timing *timing_out,
5110         const struct drm_display_info *info)
5111 {
5112         enum dc_color_depth depth = timing_out->display_color_depth;
5113         int normalized_clk;
5114         do {
5115                 normalized_clk = timing_out->pix_clk_100hz / 10;
5116                 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
5117                 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
5118                         normalized_clk /= 2;
5119                 /* Adjusting pix clock following on HDMI spec based on colour depth */
5120                 switch (depth) {
5121                 case COLOR_DEPTH_888:
5122                         break;
5123                 case COLOR_DEPTH_101010:
5124                         normalized_clk = (normalized_clk * 30) / 24;
5125                         break;
5126                 case COLOR_DEPTH_121212:
5127                         normalized_clk = (normalized_clk * 36) / 24;
5128                         break;
5129                 case COLOR_DEPTH_161616:
5130                         normalized_clk = (normalized_clk * 48) / 24;
5131                         break;
5132                 default:
5133                         /* The above depths are the only ones valid for HDMI. */
5134                         return false;
5135                 }
5136                 if (normalized_clk <= info->max_tmds_clock) {
5137                         timing_out->display_color_depth = depth;
5138                         return true;
5139                 }
5140         } while (--depth > COLOR_DEPTH_666);
5141         return false;
5142 }
5143
5144 static void fill_stream_properties_from_drm_display_mode(
5145         struct dc_stream_state *stream,
5146         const struct drm_display_mode *mode_in,
5147         const struct drm_connector *connector,
5148         const struct drm_connector_state *connector_state,
5149         const struct dc_stream_state *old_stream,
5150         int requested_bpc)
5151 {
5152         struct dc_crtc_timing *timing_out = &stream->timing;
5153         const struct drm_display_info *info = &connector->display_info;
5154         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5155         struct hdmi_vendor_infoframe hv_frame;
5156         struct hdmi_avi_infoframe avi_frame;
5157
5158         memset(&hv_frame, 0, sizeof(hv_frame));
5159         memset(&avi_frame, 0, sizeof(avi_frame));
5160
5161         timing_out->h_border_left = 0;
5162         timing_out->h_border_right = 0;
5163         timing_out->v_border_top = 0;
5164         timing_out->v_border_bottom = 0;
5165         /* TODO: un-hardcode */
5166         if (drm_mode_is_420_only(info, mode_in)
5167                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5168                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5169         else if (drm_mode_is_420_also(info, mode_in)
5170                         && aconnector->force_yuv420_output)
5171                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5172         else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
5173                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5174                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
5175         else
5176                 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
5177
5178         timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
5179         timing_out->display_color_depth = convert_color_depth_from_display_info(
5180                 connector,
5181                 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420),
5182                 requested_bpc);
5183         timing_out->scan_type = SCANNING_TYPE_NODATA;
5184         timing_out->hdmi_vic = 0;
5185
5186         if(old_stream) {
5187                 timing_out->vic = old_stream->timing.vic;
5188                 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
5189                 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
5190         } else {
5191                 timing_out->vic = drm_match_cea_mode(mode_in);
5192                 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
5193                         timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
5194                 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
5195                         timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
5196         }
5197
5198         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5199                 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
5200                 timing_out->vic = avi_frame.video_code;
5201                 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
5202                 timing_out->hdmi_vic = hv_frame.vic;
5203         }
5204
5205         if (is_freesync_video_mode(mode_in, aconnector)) {
5206                 timing_out->h_addressable = mode_in->hdisplay;
5207                 timing_out->h_total = mode_in->htotal;
5208                 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start;
5209                 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay;
5210                 timing_out->v_total = mode_in->vtotal;
5211                 timing_out->v_addressable = mode_in->vdisplay;
5212                 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay;
5213                 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start;
5214                 timing_out->pix_clk_100hz = mode_in->clock * 10;
5215         } else {
5216                 timing_out->h_addressable = mode_in->crtc_hdisplay;
5217                 timing_out->h_total = mode_in->crtc_htotal;
5218                 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
5219                 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
5220                 timing_out->v_total = mode_in->crtc_vtotal;
5221                 timing_out->v_addressable = mode_in->crtc_vdisplay;
5222                 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
5223                 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
5224                 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
5225         }
5226
5227         timing_out->aspect_ratio = get_aspect_ratio(mode_in);
5228
5229         stream->output_color_space = get_output_color_space(timing_out);
5230
5231         stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
5232         stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
5233         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5234                 if (!adjust_colour_depth_from_display_info(timing_out, info) &&
5235                     drm_mode_is_420_also(info, mode_in) &&
5236                     timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
5237                         timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5238                         adjust_colour_depth_from_display_info(timing_out, info);
5239                 }
5240         }
5241 }
5242
5243 static void fill_audio_info(struct audio_info *audio_info,
5244                             const struct drm_connector *drm_connector,
5245                             const struct dc_sink *dc_sink)
5246 {
5247         int i = 0;
5248         int cea_revision = 0;
5249         const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
5250
5251         audio_info->manufacture_id = edid_caps->manufacturer_id;
5252         audio_info->product_id = edid_caps->product_id;
5253
5254         cea_revision = drm_connector->display_info.cea_rev;
5255
5256         strscpy(audio_info->display_name,
5257                 edid_caps->display_name,
5258                 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
5259
5260         if (cea_revision >= 3) {
5261                 audio_info->mode_count = edid_caps->audio_mode_count;
5262
5263                 for (i = 0; i < audio_info->mode_count; ++i) {
5264                         audio_info->modes[i].format_code =
5265                                         (enum audio_format_code)
5266                                         (edid_caps->audio_modes[i].format_code);
5267                         audio_info->modes[i].channel_count =
5268                                         edid_caps->audio_modes[i].channel_count;
5269                         audio_info->modes[i].sample_rates.all =
5270                                         edid_caps->audio_modes[i].sample_rate;
5271                         audio_info->modes[i].sample_size =
5272                                         edid_caps->audio_modes[i].sample_size;
5273                 }
5274         }
5275
5276         audio_info->flags.all = edid_caps->speaker_flags;
5277
5278         /* TODO: We only check for the progressive mode, check for interlace mode too */
5279         if (drm_connector->latency_present[0]) {
5280                 audio_info->video_latency = drm_connector->video_latency[0];
5281                 audio_info->audio_latency = drm_connector->audio_latency[0];
5282         }
5283
5284         /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
5285
5286 }
5287
5288 static void
5289 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
5290                                       struct drm_display_mode *dst_mode)
5291 {
5292         dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
5293         dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
5294         dst_mode->crtc_clock = src_mode->crtc_clock;
5295         dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
5296         dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
5297         dst_mode->crtc_hsync_start =  src_mode->crtc_hsync_start;
5298         dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
5299         dst_mode->crtc_htotal = src_mode->crtc_htotal;
5300         dst_mode->crtc_hskew = src_mode->crtc_hskew;
5301         dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
5302         dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
5303         dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
5304         dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
5305         dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
5306 }
5307
5308 static void
5309 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
5310                                         const struct drm_display_mode *native_mode,
5311                                         bool scale_enabled)
5312 {
5313         if (scale_enabled) {
5314                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5315         } else if (native_mode->clock == drm_mode->clock &&
5316                         native_mode->htotal == drm_mode->htotal &&
5317                         native_mode->vtotal == drm_mode->vtotal) {
5318                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5319         } else {
5320                 /* no scaling nor amdgpu inserted, no need to patch */
5321         }
5322 }
5323
5324 static struct dc_sink *
5325 create_fake_sink(struct amdgpu_dm_connector *aconnector)
5326 {
5327         struct dc_sink_init_data sink_init_data = { 0 };
5328         struct dc_sink *sink = NULL;
5329         sink_init_data.link = aconnector->dc_link;
5330         sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
5331
5332         sink = dc_sink_create(&sink_init_data);
5333         if (!sink) {
5334                 DRM_ERROR("Failed to create sink!\n");
5335                 return NULL;
5336         }
5337         sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
5338
5339         return sink;
5340 }
5341
5342 static void set_multisync_trigger_params(
5343                 struct dc_stream_state *stream)
5344 {
5345         struct dc_stream_state *master = NULL;
5346
5347         if (stream->triggered_crtc_reset.enabled) {
5348                 master = stream->triggered_crtc_reset.event_source;
5349                 stream->triggered_crtc_reset.event =
5350                         master->timing.flags.VSYNC_POSITIVE_POLARITY ?
5351                         CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING;
5352                 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL;
5353         }
5354 }
5355
5356 static void set_master_stream(struct dc_stream_state *stream_set[],
5357                               int stream_count)
5358 {
5359         int j, highest_rfr = 0, master_stream = 0;
5360
5361         for (j = 0;  j < stream_count; j++) {
5362                 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
5363                         int refresh_rate = 0;
5364
5365                         refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
5366                                 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
5367                         if (refresh_rate > highest_rfr) {
5368                                 highest_rfr = refresh_rate;
5369                                 master_stream = j;
5370                         }
5371                 }
5372         }
5373         for (j = 0;  j < stream_count; j++) {
5374                 if (stream_set[j])
5375                         stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
5376         }
5377 }
5378
5379 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
5380 {
5381         int i = 0;
5382         struct dc_stream_state *stream;
5383
5384         if (context->stream_count < 2)
5385                 return;
5386         for (i = 0; i < context->stream_count ; i++) {
5387                 if (!context->streams[i])
5388                         continue;
5389                 /*
5390                  * TODO: add a function to read AMD VSDB bits and set
5391                  * crtc_sync_master.multi_sync_enabled flag
5392                  * For now it's set to false
5393                  */
5394         }
5395
5396         set_master_stream(context->streams, context->stream_count);
5397
5398         for (i = 0; i < context->stream_count ; i++) {
5399                 stream = context->streams[i];
5400
5401                 if (!stream)
5402                         continue;
5403
5404                 set_multisync_trigger_params(stream);
5405         }
5406 }
5407
5408 static struct drm_display_mode *
5409 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
5410                           bool use_probed_modes)
5411 {
5412         struct drm_display_mode *m, *m_pref = NULL;
5413         u16 current_refresh, highest_refresh;
5414         struct list_head *list_head = use_probed_modes ?
5415                                                     &aconnector->base.probed_modes :
5416                                                     &aconnector->base.modes;
5417
5418         if (aconnector->freesync_vid_base.clock != 0)
5419                 return &aconnector->freesync_vid_base;
5420
5421         /* Find the preferred mode */
5422         list_for_each_entry (m, list_head, head) {
5423                 if (m->type & DRM_MODE_TYPE_PREFERRED) {
5424                         m_pref = m;
5425                         break;
5426                 }
5427         }
5428
5429         if (!m_pref) {
5430                 /* Probably an EDID with no preferred mode. Fallback to first entry */
5431                 m_pref = list_first_entry_or_null(
5432                         &aconnector->base.modes, struct drm_display_mode, head);
5433                 if (!m_pref) {
5434                         DRM_DEBUG_DRIVER("No preferred mode found in EDID\n");
5435                         return NULL;
5436                 }
5437         }
5438
5439         highest_refresh = drm_mode_vrefresh(m_pref);
5440
5441         /*
5442          * Find the mode with highest refresh rate with same resolution.
5443          * For some monitors, preferred mode is not the mode with highest
5444          * supported refresh rate.
5445          */
5446         list_for_each_entry (m, list_head, head) {
5447                 current_refresh  = drm_mode_vrefresh(m);
5448
5449                 if (m->hdisplay == m_pref->hdisplay &&
5450                     m->vdisplay == m_pref->vdisplay &&
5451                     highest_refresh < current_refresh) {
5452                         highest_refresh = current_refresh;
5453                         m_pref = m;
5454                 }
5455         }
5456
5457         aconnector->freesync_vid_base = *m_pref;
5458         return m_pref;
5459 }
5460
5461 static bool is_freesync_video_mode(const struct drm_display_mode *mode,
5462                                    struct amdgpu_dm_connector *aconnector)
5463 {
5464         struct drm_display_mode *high_mode;
5465         int timing_diff;
5466
5467         high_mode = get_highest_refresh_rate_mode(aconnector, false);
5468         if (!high_mode || !mode)
5469                 return false;
5470
5471         timing_diff = high_mode->vtotal - mode->vtotal;
5472
5473         if (high_mode->clock == 0 || high_mode->clock != mode->clock ||
5474             high_mode->hdisplay != mode->hdisplay ||
5475             high_mode->vdisplay != mode->vdisplay ||
5476             high_mode->hsync_start != mode->hsync_start ||
5477             high_mode->hsync_end != mode->hsync_end ||
5478             high_mode->htotal != mode->htotal ||
5479             high_mode->hskew != mode->hskew ||
5480             high_mode->vscan != mode->vscan ||
5481             high_mode->vsync_start - mode->vsync_start != timing_diff ||
5482             high_mode->vsync_end - mode->vsync_end != timing_diff)
5483                 return false;
5484         else
5485                 return true;
5486 }
5487
5488 static struct dc_stream_state *
5489 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
5490                        const struct drm_display_mode *drm_mode,
5491                        const struct dm_connector_state *dm_state,
5492                        const struct dc_stream_state *old_stream,
5493                        int requested_bpc)
5494 {
5495         struct drm_display_mode *preferred_mode = NULL;
5496         struct drm_connector *drm_connector;
5497         const struct drm_connector_state *con_state =
5498                 dm_state ? &dm_state->base : NULL;
5499         struct dc_stream_state *stream = NULL;
5500         struct drm_display_mode mode = *drm_mode;
5501         struct drm_display_mode saved_mode;
5502         struct drm_display_mode *freesync_mode = NULL;
5503         bool native_mode_found = false;
5504         bool recalculate_timing = dm_state ? (dm_state->scaling != RMX_OFF) : false;
5505         int mode_refresh;
5506         int preferred_refresh = 0;
5507 #if defined(CONFIG_DRM_AMD_DC_DCN)
5508         struct dsc_dec_dpcd_caps dsc_caps;
5509         uint32_t link_bandwidth_kbps;
5510 #endif
5511         struct dc_sink *sink = NULL;
5512
5513         memset(&saved_mode, 0, sizeof(saved_mode));
5514
5515         if (aconnector == NULL) {
5516                 DRM_ERROR("aconnector is NULL!\n");
5517                 return stream;
5518         }
5519
5520         drm_connector = &aconnector->base;
5521
5522         if (!aconnector->dc_sink) {
5523                 sink = create_fake_sink(aconnector);
5524                 if (!sink)
5525                         return stream;
5526         } else {
5527                 sink = aconnector->dc_sink;
5528                 dc_sink_retain(sink);
5529         }
5530
5531         stream = dc_create_stream_for_sink(sink);
5532
5533         if (stream == NULL) {
5534                 DRM_ERROR("Failed to create stream for sink!\n");
5535                 goto finish;
5536         }
5537
5538         stream->dm_stream_context = aconnector;
5539
5540         stream->timing.flags.LTE_340MCSC_SCRAMBLE =
5541                 drm_connector->display_info.hdmi.scdc.scrambling.low_rates;
5542
5543         list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
5544                 /* Search for preferred mode */
5545                 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
5546                         native_mode_found = true;
5547                         break;
5548                 }
5549         }
5550         if (!native_mode_found)
5551                 preferred_mode = list_first_entry_or_null(
5552                                 &aconnector->base.modes,
5553                                 struct drm_display_mode,
5554                                 head);
5555
5556         mode_refresh = drm_mode_vrefresh(&mode);
5557
5558         if (preferred_mode == NULL) {
5559                 /*
5560                  * This may not be an error, the use case is when we have no
5561                  * usermode calls to reset and set mode upon hotplug. In this
5562                  * case, we call set mode ourselves to restore the previous mode
5563                  * and the modelist may not be filled in in time.
5564                  */
5565                 DRM_DEBUG_DRIVER("No preferred mode found\n");
5566         } else {
5567                 recalculate_timing |= amdgpu_freesync_vid_mode &&
5568                                  is_freesync_video_mode(&mode, aconnector);
5569                 if (recalculate_timing) {
5570                         freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
5571                         saved_mode = mode;
5572                         mode = *freesync_mode;
5573                 } else {
5574                         decide_crtc_timing_for_drm_display_mode(
5575                                 &mode, preferred_mode,
5576                                 dm_state ? (dm_state->scaling != RMX_OFF) : false);
5577                 }
5578
5579                 preferred_refresh = drm_mode_vrefresh(preferred_mode);
5580         }
5581
5582         if (recalculate_timing)
5583                 drm_mode_set_crtcinfo(&saved_mode, 0);
5584         else if (!dm_state)
5585                 drm_mode_set_crtcinfo(&mode, 0);
5586
5587        /*
5588         * If scaling is enabled and refresh rate didn't change
5589         * we copy the vic and polarities of the old timings
5590         */
5591         if (!recalculate_timing || mode_refresh != preferred_refresh)
5592                 fill_stream_properties_from_drm_display_mode(
5593                         stream, &mode, &aconnector->base, con_state, NULL,
5594                         requested_bpc);
5595         else
5596                 fill_stream_properties_from_drm_display_mode(
5597                         stream, &mode, &aconnector->base, con_state, old_stream,
5598                         requested_bpc);
5599
5600         stream->timing.flags.DSC = 0;
5601
5602         if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
5603 #if defined(CONFIG_DRM_AMD_DC_DCN)
5604                 dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
5605                                       aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
5606                                       aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
5607                                       &dsc_caps);
5608                 link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
5609                                                              dc_link_get_link_cap(aconnector->dc_link));
5610
5611                 if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported) {
5612                         /* Set DSC policy according to dsc_clock_en */
5613                         dc_dsc_policy_set_enable_dsc_when_not_needed(
5614                                 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);
5615
5616                         if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5617                                                   &dsc_caps,
5618                                                   aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override,
5619                                                   0,
5620                                                   link_bandwidth_kbps,
5621                                                   &stream->timing,
5622                                                   &stream->timing.dsc_cfg))
5623                                 stream->timing.flags.DSC = 1;
5624                         /* Overwrite the stream flag if DSC is enabled through debugfs */
5625                         if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
5626                                 stream->timing.flags.DSC = 1;
5627
5628                         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
5629                                 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
5630
5631                         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
5632                                 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
5633
5634                         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
5635                                 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
5636                 }
5637 #endif
5638         }
5639
5640         update_stream_scaling_settings(&mode, dm_state, stream);
5641
5642         fill_audio_info(
5643                 &stream->audio_info,
5644                 drm_connector,
5645                 sink);
5646
5647         update_stream_signal(stream, sink);
5648
5649         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5650                 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);
5651
5652         if (stream->link->psr_settings.psr_feature_enabled) {
5653                 //
5654                 // should decide stream support vsc sdp colorimetry capability
5655                 // before building vsc info packet
5656                 //
5657                 stream->use_vsc_sdp_for_colorimetry = false;
5658                 if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
5659                         stream->use_vsc_sdp_for_colorimetry =
5660                                 aconnector->dc_sink->is_vsc_sdp_colorimetry_supported;
5661                 } else {
5662                         if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
5663                                 stream->use_vsc_sdp_for_colorimetry = true;
5664                 }
5665                 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket);
5666         }
5667 finish:
5668         dc_sink_release(sink);
5669
5670         return stream;
5671 }
5672
5673 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
5674 {
5675         drm_crtc_cleanup(crtc);
5676         kfree(crtc);
5677 }
5678
5679 static void dm_crtc_destroy_state(struct drm_crtc *crtc,
5680                                   struct drm_crtc_state *state)
5681 {
5682         struct dm_crtc_state *cur = to_dm_crtc_state(state);
5683
5684         /* TODO Destroy dc_stream objects are stream object is flattened */
5685         if (cur->stream)
5686                 dc_stream_release(cur->stream);
5687
5688
5689         __drm_atomic_helper_crtc_destroy_state(state);
5690
5691
5692         kfree(state);
5693 }
5694
5695 static void dm_crtc_reset_state(struct drm_crtc *crtc)
5696 {
5697         struct dm_crtc_state *state;
5698
5699         if (crtc->state)
5700                 dm_crtc_destroy_state(crtc, crtc->state);
5701
5702         state = kzalloc(sizeof(*state), GFP_KERNEL);
5703         if (WARN_ON(!state))
5704                 return;
5705
5706         __drm_atomic_helper_crtc_reset(crtc, &state->base);
5707 }
5708
5709 static struct drm_crtc_state *
5710 dm_crtc_duplicate_state(struct drm_crtc *crtc)
5711 {
5712         struct dm_crtc_state *state, *cur;
5713
5714         cur = to_dm_crtc_state(crtc->state);
5715
5716         if (WARN_ON(!crtc->state))
5717                 return NULL;
5718
5719         state = kzalloc(sizeof(*state), GFP_KERNEL);
5720         if (!state)
5721                 return NULL;
5722
5723         __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
5724
5725         if (cur->stream) {
5726                 state->stream = cur->stream;
5727                 dc_stream_retain(state->stream);
5728         }
5729
5730         state->active_planes = cur->active_planes;
5731         state->vrr_infopacket = cur->vrr_infopacket;
5732         state->abm_level = cur->abm_level;
5733         state->vrr_supported = cur->vrr_supported;
5734         state->freesync_config = cur->freesync_config;
5735         state->cm_has_degamma = cur->cm_has_degamma;
5736         state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
5737         /* TODO Duplicate dc_stream after objects are stream object is flattened */
5738
5739         return &state->base;
5740 }
5741
5742 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
5743 static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc)
5744 {
5745         crtc_debugfs_init(crtc);
5746
5747         return 0;
5748 }
5749 #endif
5750
5751 static inline int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
5752 {
5753         enum dc_irq_source irq_source;
5754         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
5755         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
5756         int rc;
5757
5758         irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst;
5759
5760         rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
5761
5762         DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n",
5763                       acrtc->crtc_id, enable ? "en" : "dis", rc);
5764         return rc;
5765 }
5766
5767 static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
5768 {
5769         enum dc_irq_source irq_source;
5770         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
5771         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
5772         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
5773 #if defined(CONFIG_DRM_AMD_DC_DCN)
5774         struct amdgpu_display_manager *dm = &adev->dm;
5775         unsigned long flags;
5776 #endif
5777         int rc = 0;
5778
5779         if (enable) {
5780                 /* vblank irq on -> Only need vupdate irq in vrr mode */
5781                 if (amdgpu_dm_vrr_active(acrtc_state))
5782                         rc = dm_set_vupdate_irq(crtc, true);
5783         } else {
5784                 /* vblank irq off -> vupdate irq off */
5785                 rc = dm_set_vupdate_irq(crtc, false);
5786         }
5787
5788         if (rc)
5789                 return rc;
5790
5791         irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
5792
5793         if (!dc_interrupt_set(adev->dm.dc, irq_source, enable))
5794                 return -EBUSY;
5795
5796         if (amdgpu_in_reset(adev))
5797                 return 0;
5798
5799 #if defined(CONFIG_DRM_AMD_DC_DCN)
5800         spin_lock_irqsave(&dm->vblank_lock, flags);
5801         dm->vblank_workqueue->dm = dm;
5802         dm->vblank_workqueue->otg_inst = acrtc->otg_inst;
5803         dm->vblank_workqueue->enable = enable;
5804         spin_unlock_irqrestore(&dm->vblank_lock, flags);
5805         schedule_work(&dm->vblank_workqueue->mall_work);
5806 #endif
5807
5808         return 0;
5809 }
5810
5811 static int dm_enable_vblank(struct drm_crtc *crtc)
5812 {
5813         return dm_set_vblank(crtc, true);
5814 }
5815
5816 static void dm_disable_vblank(struct drm_crtc *crtc)
5817 {
5818         dm_set_vblank(crtc, false);
5819 }
5820
5821 /* Implemented only the options currently availible for the driver */
5822 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
5823         .reset = dm_crtc_reset_state,
5824         .destroy = amdgpu_dm_crtc_destroy,
5825         .set_config = drm_atomic_helper_set_config,
5826         .page_flip = drm_atomic_helper_page_flip,
5827         .atomic_duplicate_state = dm_crtc_duplicate_state,
5828         .atomic_destroy_state = dm_crtc_destroy_state,
5829         .set_crc_source = amdgpu_dm_crtc_set_crc_source,
5830         .verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
5831         .get_crc_sources = amdgpu_dm_crtc_get_crc_sources,
5832         .get_vblank_counter = amdgpu_get_vblank_counter_kms,
5833         .enable_vblank = dm_enable_vblank,
5834         .disable_vblank = dm_disable_vblank,
5835         .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
5836 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
5837         .late_register = amdgpu_dm_crtc_late_register,
5838 #endif
5839 };
5840
5841 static enum drm_connector_status
5842 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
5843 {
5844         bool connected;
5845         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5846
5847         /*
5848          * Notes:
5849          * 1. This interface is NOT called in context of HPD irq.
5850          * 2. This interface *is called* in context of user-mode ioctl. Which
5851          * makes it a bad place for *any* MST-related activity.
5852          */
5853
5854         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
5855             !aconnector->fake_enable)
5856                 connected = (aconnector->dc_sink != NULL);
5857         else
5858                 connected = (aconnector->base.force == DRM_FORCE_ON);
5859
5860         update_subconnector_property(aconnector);
5861
5862         return (connected ? connector_status_connected :
5863                         connector_status_disconnected);
5864 }
5865
5866 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
5867                                             struct drm_connector_state *connector_state,
5868                                             struct drm_property *property,
5869                                             uint64_t val)
5870 {
5871         struct drm_device *dev = connector->dev;
5872         struct amdgpu_device *adev = drm_to_adev(dev);
5873         struct dm_connector_state *dm_old_state =
5874                 to_dm_connector_state(connector->state);
5875         struct dm_connector_state *dm_new_state =
5876                 to_dm_connector_state(connector_state);
5877
5878         int ret = -EINVAL;
5879
5880         if (property == dev->mode_config.scaling_mode_property) {
5881                 enum amdgpu_rmx_type rmx_type;
5882
5883                 switch (val) {
5884                 case DRM_MODE_SCALE_CENTER:
5885                         rmx_type = RMX_CENTER;
5886                         break;
5887                 case DRM_MODE_SCALE_ASPECT:
5888                         rmx_type = RMX_ASPECT;
5889                         break;
5890                 case DRM_MODE_SCALE_FULLSCREEN:
5891                         rmx_type = RMX_FULL;
5892                         break;
5893                 case DRM_MODE_SCALE_NONE:
5894                 default:
5895                         rmx_type = RMX_OFF;
5896                         break;
5897                 }
5898
5899                 if (dm_old_state->scaling == rmx_type)
5900                         return 0;
5901
5902                 dm_new_state->scaling = rmx_type;
5903                 ret = 0;
5904         } else if (property == adev->mode_info.underscan_hborder_property) {
5905                 dm_new_state->underscan_hborder = val;
5906                 ret = 0;
5907         } else if (property == adev->mode_info.underscan_vborder_property) {
5908                 dm_new_state->underscan_vborder = val;
5909                 ret = 0;
5910         } else if (property == adev->mode_info.underscan_property) {
5911                 dm_new_state->underscan_enable = val;
5912                 ret = 0;
5913         } else if (property == adev->mode_info.abm_level_property) {
5914                 dm_new_state->abm_level = val;
5915                 ret = 0;
5916         }
5917
5918         return ret;
5919 }
5920
5921 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
5922                                             const struct drm_connector_state *state,
5923                                             struct drm_property *property,
5924                                             uint64_t *val)
5925 {
5926         struct drm_device *dev = connector->dev;
5927         struct amdgpu_device *adev = drm_to_adev(dev);
5928         struct dm_connector_state *dm_state =
5929                 to_dm_connector_state(state);
5930         int ret = -EINVAL;
5931
5932         if (property == dev->mode_config.scaling_mode_property) {
5933                 switch (dm_state->scaling) {
5934                 case RMX_CENTER:
5935                         *val = DRM_MODE_SCALE_CENTER;
5936                         break;
5937                 case RMX_ASPECT:
5938                         *val = DRM_MODE_SCALE_ASPECT;
5939                         break;
5940                 case RMX_FULL:
5941                         *val = DRM_MODE_SCALE_FULLSCREEN;
5942                         break;
5943                 case RMX_OFF:
5944                 default:
5945                         *val = DRM_MODE_SCALE_NONE;
5946                         break;
5947                 }
5948                 ret = 0;
5949         } else if (property == adev->mode_info.underscan_hborder_property) {
5950                 *val = dm_state->underscan_hborder;
5951                 ret = 0;
5952         } else if (property == adev->mode_info.underscan_vborder_property) {
5953                 *val = dm_state->underscan_vborder;
5954                 ret = 0;
5955         } else if (property == adev->mode_info.underscan_property) {
5956                 *val = dm_state->underscan_enable;
5957                 ret = 0;
5958         } else if (property == adev->mode_info.abm_level_property) {
5959                 *val = dm_state->abm_level;
5960                 ret = 0;
5961         }
5962
5963         return ret;
5964 }
5965
5966 static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
5967 {
5968         struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
5969
5970         drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
5971 }
5972
5973 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
5974 {
5975         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5976         const struct dc_link *link = aconnector->dc_link;
5977         struct amdgpu_device *adev = drm_to_adev(connector->dev);
5978         struct amdgpu_display_manager *dm = &adev->dm;
5979
5980         /*
5981          * Call only if mst_mgr was iniitalized before since it's not done
5982          * for all connector types.
5983          */
5984         if (aconnector->mst_mgr.dev)
5985                 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);
5986
5987 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
5988         defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
5989
5990         if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
5991             link->type != dc_connection_none &&
5992             dm->backlight_dev) {
5993                 backlight_device_unregister(dm->backlight_dev);
5994                 dm->backlight_dev = NULL;
5995         }
5996 #endif
5997
5998         if (aconnector->dc_em_sink)
5999                 dc_sink_release(aconnector->dc_em_sink);
6000         aconnector->dc_em_sink = NULL;
6001         if (aconnector->dc_sink)
6002                 dc_sink_release(aconnector->dc_sink);
6003         aconnector->dc_sink = NULL;
6004
6005         drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
6006         drm_connector_unregister(connector);
6007         drm_connector_cleanup(connector);
6008         if (aconnector->i2c) {
6009                 i2c_del_adapter(&aconnector->i2c->base);
6010                 kfree(aconnector->i2c);
6011         }
6012         kfree(aconnector->dm_dp_aux.aux.name);
6013
6014         kfree(connector);
6015 }
6016
6017 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
6018 {
6019         struct dm_connector_state *state =
6020                 to_dm_connector_state(connector->state);
6021
6022         if (connector->state)
6023                 __drm_atomic_helper_connector_destroy_state(connector->state);
6024
6025         kfree(state);
6026
6027         state = kzalloc(sizeof(*state), GFP_KERNEL);
6028
6029         if (state) {
6030                 state->scaling = RMX_OFF;
6031                 state->underscan_enable = false;
6032                 state->underscan_hborder = 0;
6033                 state->underscan_vborder = 0;
6034                 state->base.max_requested_bpc = 8;
6035                 state->vcpi_slots = 0;
6036                 state->pbn = 0;
6037                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
6038                         state->abm_level = amdgpu_dm_abm_level;
6039
6040                 __drm_atomic_helper_connector_reset(connector, &state->base);
6041         }
6042 }
6043
6044 struct drm_connector_state *
6045 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
6046 {
6047         struct dm_connector_state *state =
6048                 to_dm_connector_state(connector->state);
6049
6050         struct dm_connector_state *new_state =
6051                         kmemdup(state, sizeof(*state), GFP_KERNEL);
6052
6053         if (!new_state)
6054                 return NULL;
6055
6056         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
6057
6058         new_state->freesync_capable = state->freesync_capable;
6059         new_state->abm_level = state->abm_level;
6060         new_state->scaling = state->scaling;
6061         new_state->underscan_enable = state->underscan_enable;
6062         new_state->underscan_hborder = state->underscan_hborder;
6063         new_state->underscan_vborder = state->underscan_vborder;
6064         new_state->vcpi_slots = state->vcpi_slots;
6065         new_state->pbn = state->pbn;
6066         return &new_state->base;
6067 }
6068
6069 static int
6070 amdgpu_dm_connector_late_register(struct drm_connector *connector)
6071 {
6072         struct amdgpu_dm_connector *amdgpu_dm_connector =
6073                 to_amdgpu_dm_connector(connector);
6074         int r;
6075
6076         if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
6077             (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
6078                 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
6079                 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
6080                 if (r)
6081                         return r;
6082         }
6083
6084 #if defined(CONFIG_DEBUG_FS)
6085         connector_debugfs_init(amdgpu_dm_connector);
6086 #endif
6087
6088         return 0;
6089 }
6090
6091 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
6092         .reset = amdgpu_dm_connector_funcs_reset,
6093         .detect = amdgpu_dm_connector_detect,
6094         .fill_modes = drm_helper_probe_single_connector_modes,
6095         .destroy = amdgpu_dm_connector_destroy,
6096         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
6097         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6098         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
6099         .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
6100         .late_register = amdgpu_dm_connector_late_register,
6101         .early_unregister = amdgpu_dm_connector_unregister
6102 };
6103
6104 static int get_modes(struct drm_connector *connector)
6105 {
6106         return amdgpu_dm_connector_get_modes(connector);
6107 }
6108
6109 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
6110 {
6111         struct dc_sink_init_data init_params = {
6112                         .link = aconnector->dc_link,
6113                         .sink_signal = SIGNAL_TYPE_VIRTUAL
6114         };
6115         struct edid *edid;
6116
6117         if (!aconnector->base.edid_blob_ptr) {
6118                 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
6119                                 aconnector->base.name);
6120
6121                 aconnector->base.force = DRM_FORCE_OFF;
6122                 aconnector->base.override_edid = false;
6123                 return;
6124         }
6125
6126         edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
6127
6128         aconnector->edid = edid;
6129
6130         aconnector->dc_em_sink = dc_link_add_remote_sink(
6131                 aconnector->dc_link,
6132                 (uint8_t *)edid,
6133                 (edid->extensions + 1) * EDID_LENGTH,
6134                 &init_params);
6135
6136         if (aconnector->base.force == DRM_FORCE_ON) {
6137                 aconnector->dc_sink = aconnector->dc_link->local_sink ?
6138                 aconnector->dc_link->local_sink :
6139                 aconnector->dc_em_sink;
6140                 dc_sink_retain(aconnector->dc_sink);
6141         }
6142 }
6143
6144 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
6145 {
6146         struct dc_link *link = (struct dc_link *)aconnector->dc_link;
6147
6148         /*
6149          * In case of headless boot with force on for DP managed connector
6150          * Those settings have to be != 0 to get initial modeset
6151          */
6152         if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
6153                 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
6154                 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
6155         }
6156
6157
6158         aconnector->base.override_edid = true;
6159         create_eml_sink(aconnector);
6160 }
6161
6162 static struct dc_stream_state *
6163 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6164                                 const struct drm_display_mode *drm_mode,
6165                                 const struct dm_connector_state *dm_state,
6166                                 const struct dc_stream_state *old_stream)
6167 {
6168         struct drm_connector *connector = &aconnector->base;
6169         struct amdgpu_device *adev = drm_to_adev(connector->dev);
6170         struct dc_stream_state *stream;
6171         const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL;
6172         int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8;
6173         enum dc_status dc_result = DC_OK;
6174
6175         do {
6176                 stream = create_stream_for_sink(aconnector, drm_mode,
6177                                                 dm_state, old_stream,
6178                                                 requested_bpc);
6179                 if (stream == NULL) {
6180                         DRM_ERROR("Failed to create stream for sink!\n");
6181                         break;
6182                 }
6183
6184                 dc_result = dc_validate_stream(adev->dm.dc, stream);
6185
6186                 if (dc_result != DC_OK) {
6187                         DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",
6188                                       drm_mode->hdisplay,
6189                                       drm_mode->vdisplay,
6190                                       drm_mode->clock,
6191                                       dc_result,
6192                                       dc_status_to_str(dc_result));
6193
6194                         dc_stream_release(stream);
6195                         stream = NULL;
6196                         requested_bpc -= 2; /* lower bpc to retry validation */
6197                 }
6198
6199         } while (stream == NULL && requested_bpc >= 6);
6200
6201         if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) {
6202                 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n");
6203
6204                 aconnector->force_yuv420_output = true;
6205                 stream = create_validate_stream_for_sink(aconnector, drm_mode,
6206                                                 dm_state, old_stream);
6207                 aconnector->force_yuv420_output = false;
6208         }
6209
6210         return stream;
6211 }
6212
6213 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
6214                                    struct drm_display_mode *mode)
6215 {
6216         int result = MODE_ERROR;
6217         struct dc_sink *dc_sink;
6218         /* TODO: Unhardcode stream count */
6219         struct dc_stream_state *stream;
6220         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6221
6222         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
6223                         (mode->flags & DRM_MODE_FLAG_DBLSCAN))
6224                 return result;
6225
6226         /*
6227          * Only run this the first time mode_valid is called to initilialize
6228          * EDID mgmt
6229          */
6230         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
6231                 !aconnector->dc_em_sink)
6232                 handle_edid_mgmt(aconnector);
6233
6234         dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
6235
6236         if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL &&
6237                                 aconnector->base.force != DRM_FORCE_ON) {
6238                 DRM_ERROR("dc_sink is NULL!\n");
6239                 goto fail;
6240         }
6241
6242         stream = create_validate_stream_for_sink(aconnector, mode, NULL, NULL);
6243         if (stream) {
6244                 dc_stream_release(stream);
6245                 result = MODE_OK;
6246         }
6247
6248 fail:
6249         /* TODO: error handling*/
6250         return result;
6251 }
6252
6253 static int fill_hdr_info_packet(const struct drm_connector_state *state,
6254                                 struct dc_info_packet *out)
6255 {
6256         struct hdmi_drm_infoframe frame;
6257         unsigned char buf[30]; /* 26 + 4 */
6258         ssize_t len;
6259         int ret, i;
6260
6261         memset(out, 0, sizeof(*out));
6262
6263         if (!state->hdr_output_metadata)
6264                 return 0;
6265
6266         ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
6267         if (ret)
6268                 return ret;
6269
6270         len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
6271         if (len < 0)
6272                 return (int)len;
6273
6274         /* Static metadata is a fixed 26 bytes + 4 byte header. */
6275         if (len != 30)
6276                 return -EINVAL;
6277
6278         /* Prepare the infopacket for DC. */
6279         switch (state->connector->connector_type) {
6280         case DRM_MODE_CONNECTOR_HDMIA:
6281                 out->hb0 = 0x87; /* type */
6282                 out->hb1 = 0x01; /* version */
6283                 out->hb2 = 0x1A; /* length */
6284                 out->sb[0] = buf[3]; /* checksum */
6285                 i = 1;
6286                 break;
6287
6288         case DRM_MODE_CONNECTOR_DisplayPort:
6289         case DRM_MODE_CONNECTOR_eDP:
6290                 out->hb0 = 0x00; /* sdp id, zero */
6291                 out->hb1 = 0x87; /* type */
6292                 out->hb2 = 0x1D; /* payload len - 1 */
6293                 out->hb3 = (0x13 << 2); /* sdp version */
6294                 out->sb[0] = 0x01; /* version */
6295                 out->sb[1] = 0x1A; /* length */
6296                 i = 2;
6297                 break;
6298
6299         default:
6300                 return -EINVAL;
6301         }
6302
6303         memcpy(&out->sb[i], &buf[4], 26);
6304         out->valid = true;
6305
6306         print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
6307                        sizeof(out->sb), false);
6308
6309         return 0;
6310 }
6311
6312 static bool
6313 is_hdr_metadata_different(const struct drm_connector_state *old_state,
6314                           const struct drm_connector_state *new_state)
6315 {
6316         struct drm_property_blob *old_blob = old_state->hdr_output_metadata;
6317         struct drm_property_blob *new_blob = new_state->hdr_output_metadata;
6318
6319         if (old_blob != new_blob) {
6320                 if (old_blob && new_blob &&
6321                     old_blob->length == new_blob->length)
6322                         return memcmp(old_blob->data, new_blob->data,
6323                                       old_blob->length);
6324
6325                 return true;
6326         }
6327
6328         return false;
6329 }
6330
6331 static int
6332 amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
6333                                  struct drm_atomic_state *state)
6334 {
6335         struct drm_connector_state *new_con_state =
6336                 drm_atomic_get_new_connector_state(state, conn);
6337         struct drm_connector_state *old_con_state =
6338                 drm_atomic_get_old_connector_state(state, conn);
6339         struct drm_crtc *crtc = new_con_state->crtc;
6340         struct drm_crtc_state *new_crtc_state;
6341         int ret;
6342
6343         trace_amdgpu_dm_connector_atomic_check(new_con_state);
6344
6345         if (!crtc)
6346                 return 0;
6347
6348         if (is_hdr_metadata_different(old_con_state, new_con_state)) {
6349                 struct dc_info_packet hdr_infopacket;
6350
6351                 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
6352                 if (ret)
6353                         return ret;
6354
6355                 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6356                 if (IS_ERR(new_crtc_state))
6357                         return PTR_ERR(new_crtc_state);
6358
6359                 /*
6360                  * DC considers the stream backends changed if the
6361                  * static metadata changes. Forcing the modeset also
6362                  * gives a simple way for userspace to switch from
6363                  * 8bpc to 10bpc when setting the metadata to enter
6364                  * or exit HDR.
6365                  *
6366                  * Changing the static metadata after it's been
6367                  * set is permissible, however. So only force a
6368                  * modeset if we're entering or exiting HDR.
6369                  */
6370                 new_crtc_state->mode_changed =
6371                         !old_con_state->hdr_output_metadata ||
6372                         !new_con_state->hdr_output_metadata;
6373         }
6374
6375         return 0;
6376 }
6377
6378 static const struct drm_connector_helper_funcs
6379 amdgpu_dm_connector_helper_funcs = {
6380         /*
6381          * If hotplugging a second bigger display in FB Con mode, bigger resolution
6382          * modes will be filtered by drm_mode_validate_size(), and those modes
6383          * are missing after user start lightdm. So we need to renew modes list.
6384          * in get_modes call back, not just return the modes count
6385          */
6386         .get_modes = get_modes,
6387         .mode_valid = amdgpu_dm_connector_mode_valid,
6388         .atomic_check = amdgpu_dm_connector_atomic_check,
6389 };
6390
6391 static void dm_crtc_helper_disable(struct drm_crtc *crtc)
6392 {
6393 }
6394
6395 static int count_crtc_active_planes(struct drm_crtc_state *new_crtc_state)
6396 {
6397         struct drm_atomic_state *state = new_crtc_state->state;
6398         struct drm_plane *plane;
6399         int num_active = 0;
6400
6401         drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) {
6402                 struct drm_plane_state *new_plane_state;
6403
6404                 /* Cursor planes are "fake". */
6405                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
6406                         continue;
6407
6408                 new_plane_state = drm_atomic_get_new_plane_state(state, plane);
6409
6410                 if (!new_plane_state) {
6411                         /*
6412                          * The plane is enable on the CRTC and hasn't changed
6413                          * state. This means that it previously passed
6414                          * validation and is therefore enabled.
6415                          */
6416                         num_active += 1;
6417                         continue;
6418                 }
6419
6420                 /* We need a framebuffer to be considered enabled. */
6421                 num_active += (new_plane_state->fb != NULL);
6422         }
6423
6424         return num_active;
6425 }
6426
6427 static void dm_update_crtc_active_planes(struct drm_crtc *crtc,
6428                                          struct drm_crtc_state *new_crtc_state)
6429 {
6430         struct dm_crtc_state *dm_new_crtc_state =
6431                 to_dm_crtc_state(new_crtc_state);
6432
6433         dm_new_crtc_state->active_planes = 0;
6434
6435         if (!dm_new_crtc_state->stream)
6436                 return;
6437
6438         dm_new_crtc_state->active_planes =
6439                 count_crtc_active_planes(new_crtc_state);
6440 }
6441
6442 static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
6443                                        struct drm_atomic_state *state)
6444 {
6445         struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
6446                                                                           crtc);
6447         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
6448         struct dc *dc = adev->dm.dc;
6449         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
6450         int ret = -EINVAL;
6451
6452         trace_amdgpu_dm_crtc_atomic_check(crtc_state);
6453
6454         dm_update_crtc_active_planes(crtc, crtc_state);
6455
6456         if (unlikely(!dm_crtc_state->stream &&
6457                      modeset_required(crtc_state, NULL, dm_crtc_state->stream))) {
6458                 WARN_ON(1);
6459                 return ret;
6460         }
6461
6462         /*
6463          * We require the primary plane to be enabled whenever the CRTC is, otherwise
6464          * drm_mode_cursor_universal may end up trying to enable the cursor plane while all other
6465          * planes are disabled, which is not supported by the hardware. And there is legacy
6466          * userspace which stops using the HW cursor altogether in response to the resulting EINVAL.
6467          */
6468         if (crtc_state->enable &&
6469             !(crtc_state->plane_mask & drm_plane_mask(crtc->primary))) {
6470                 DRM_DEBUG_ATOMIC("Can't enable a CRTC without enabling the primary plane\n");
6471                 return -EINVAL;
6472         }
6473
6474         /* In some use cases, like reset, no stream is attached */
6475         if (!dm_crtc_state->stream)
6476                 return 0;
6477
6478         if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
6479                 return 0;
6480
6481         DRM_DEBUG_ATOMIC("Failed DC stream validation\n");
6482         return ret;
6483 }
6484
6485 static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
6486                                       const struct drm_display_mode *mode,
6487                                       struct drm_display_mode *adjusted_mode)
6488 {
6489         return true;
6490 }
6491
6492 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
6493         .disable = dm_crtc_helper_disable,
6494         .atomic_check = dm_crtc_helper_atomic_check,
6495         .mode_fixup = dm_crtc_helper_mode_fixup,
6496         .get_scanout_position = amdgpu_crtc_get_scanout_position,
6497 };
6498
6499 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
6500 {
6501
6502 }
6503
6504 static int convert_dc_color_depth_into_bpc (enum dc_color_depth display_color_depth)
6505 {
6506         switch (display_color_depth) {
6507                 case COLOR_DEPTH_666:
6508                         return 6;
6509                 case COLOR_DEPTH_888:
6510                         return 8;
6511                 case COLOR_DEPTH_101010:
6512                         return 10;
6513                 case COLOR_DEPTH_121212:
6514                         return 12;
6515                 case COLOR_DEPTH_141414:
6516                         return 14;
6517                 case COLOR_DEPTH_161616:
6518                         return 16;
6519                 default:
6520                         break;
6521                 }
6522         return 0;
6523 }
6524
6525 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
6526                                           struct drm_crtc_state *crtc_state,
6527                                           struct drm_connector_state *conn_state)
6528 {
6529         struct drm_atomic_state *state = crtc_state->state;
6530         struct drm_connector *connector = conn_state->connector;
6531         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6532         struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state);
6533         const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
6534         struct drm_dp_mst_topology_mgr *mst_mgr;
6535         struct drm_dp_mst_port *mst_port;
6536         enum dc_color_depth color_depth;
6537         int clock, bpp = 0;
6538         bool is_y420 = false;
6539
6540         if (!aconnector->port || !aconnector->dc_sink)
6541                 return 0;
6542
6543         mst_port = aconnector->port;
6544         mst_mgr = &aconnector->mst_port->mst_mgr;
6545
6546         if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
6547                 return 0;
6548
6549         if (!state->duplicated) {
6550                 int max_bpc = conn_state->max_requested_bpc;
6551                 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
6552                                 aconnector->force_yuv420_output;
6553                 color_depth = convert_color_depth_from_display_info(connector,
6554                                                                     is_y420,
6555                                                                     max_bpc);
6556                 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
6557                 clock = adjusted_mode->clock;
6558                 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
6559         }
6560         dm_new_connector_state->vcpi_slots = drm_dp_atomic_find_vcpi_slots(state,
6561                                                                            mst_mgr,
6562                                                                            mst_port,
6563                                                                            dm_new_connector_state->pbn,
6564                                                                            dm_mst_get_pbn_divider(aconnector->dc_link));
6565         if (dm_new_connector_state->vcpi_slots < 0) {
6566                 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
6567                 return dm_new_connector_state->vcpi_slots;
6568         }
6569         return 0;
6570 }
6571
6572 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
6573         .disable = dm_encoder_helper_disable,
6574         .atomic_check = dm_encoder_helper_atomic_check
6575 };
6576
6577 #if defined(CONFIG_DRM_AMD_DC_DCN)
6578 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
6579                                             struct dc_state *dc_state)
6580 {
6581         struct dc_stream_state *stream = NULL;
6582         struct drm_connector *connector;
6583         struct drm_connector_state *new_con_state;
6584         struct amdgpu_dm_connector *aconnector;
6585         struct dm_connector_state *dm_conn_state;
6586         int i, j, clock, bpp;
6587         int vcpi, pbn_div, pbn = 0;
6588
6589         for_each_new_connector_in_state(state, connector, new_con_state, i) {
6590
6591                 aconnector = to_amdgpu_dm_connector(connector);
6592
6593                 if (!aconnector->port)
6594                         continue;
6595
6596                 if (!new_con_state || !new_con_state->crtc)
6597                         continue;
6598
6599                 dm_conn_state = to_dm_connector_state(new_con_state);
6600
6601                 for (j = 0; j < dc_state->stream_count; j++) {
6602                         stream = dc_state->streams[j];
6603                         if (!stream)
6604                                 continue;
6605
6606                         if ((struct amdgpu_dm_connector*)stream->dm_stream_context == aconnector)
6607                                 break;
6608
6609                         stream = NULL;
6610                 }
6611
6612                 if (!stream)
6613                         continue;
6614
6615                 if (stream->timing.flags.DSC != 1) {
6616                         drm_dp_mst_atomic_enable_dsc(state,
6617                                                      aconnector->port,
6618                                                      dm_conn_state->pbn,
6619                                                      0,
6620                                                      false);
6621                         continue;
6622                 }
6623
6624                 pbn_div = dm_mst_get_pbn_divider(stream->link);
6625                 bpp = stream->timing.dsc_cfg.bits_per_pixel;
6626                 clock = stream->timing.pix_clk_100hz / 10;
6627                 pbn = drm_dp_calc_pbn_mode(clock, bpp, true);
6628                 vcpi = drm_dp_mst_atomic_enable_dsc(state,
6629                                                     aconnector->port,
6630                                                     pbn, pbn_div,
6631                                                     true);
6632                 if (vcpi < 0)
6633                         return vcpi;
6634
6635                 dm_conn_state->pbn = pbn;
6636                 dm_conn_state->vcpi_slots = vcpi;
6637         }
6638         return 0;
6639 }
6640 #endif
6641
6642 static void dm_drm_plane_reset(struct drm_plane *plane)
6643 {
6644         struct dm_plane_state *amdgpu_state = NULL;
6645
6646         if (plane->state)
6647                 plane->funcs->atomic_destroy_state(plane, plane->state);
6648
6649         amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
6650         WARN_ON(amdgpu_state == NULL);
6651
6652         if (amdgpu_state)
6653                 __drm_atomic_helper_plane_reset(plane, &amdgpu_state->base);
6654 }
6655
6656 static struct drm_plane_state *
6657 dm_drm_plane_duplicate_state(struct drm_plane *plane)
6658 {
6659         struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
6660
6661         old_dm_plane_state = to_dm_plane_state(plane->state);
6662         dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
6663         if (!dm_plane_state)
6664                 return NULL;
6665
6666         __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
6667
6668         if (old_dm_plane_state->dc_state) {
6669                 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
6670                 dc_plane_state_retain(dm_plane_state->dc_state);
6671         }
6672
6673         return &dm_plane_state->base;
6674 }
6675
6676 static void dm_drm_plane_destroy_state(struct drm_plane *plane,
6677                                 struct drm_plane_state *state)
6678 {
6679         struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
6680
6681         if (dm_plane_state->dc_state)
6682                 dc_plane_state_release(dm_plane_state->dc_state);
6683
6684         drm_atomic_helper_plane_destroy_state(plane, state);
6685 }
6686
6687 static const struct drm_plane_funcs dm_plane_funcs = {
6688         .update_plane   = drm_atomic_helper_update_plane,
6689         .disable_plane  = drm_atomic_helper_disable_plane,
6690         .destroy        = drm_primary_helper_destroy,
6691         .reset = dm_drm_plane_reset,
6692         .atomic_duplicate_state = dm_drm_plane_duplicate_state,
6693         .atomic_destroy_state = dm_drm_plane_destroy_state,
6694         .format_mod_supported = dm_plane_format_mod_supported,
6695 };
6696
6697 static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
6698                                       struct drm_plane_state *new_state)
6699 {
6700         struct amdgpu_framebuffer *afb;
6701         struct drm_gem_object *obj;
6702         struct amdgpu_device *adev;
6703         struct amdgpu_bo *rbo;
6704         struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
6705         struct list_head list;
6706         struct ttm_validate_buffer tv;
6707         struct ww_acquire_ctx ticket;
6708         uint32_t domain;
6709         int r;
6710
6711         if (!new_state->fb) {
6712                 DRM_DEBUG_KMS("No FB bound\n");
6713                 return 0;
6714         }
6715
6716         afb = to_amdgpu_framebuffer(new_state->fb);
6717         obj = new_state->fb->obj[0];
6718         rbo = gem_to_amdgpu_bo(obj);
6719         adev = amdgpu_ttm_adev(rbo->tbo.bdev);
6720         INIT_LIST_HEAD(&list);
6721
6722         tv.bo = &rbo->tbo;
6723         tv.num_shared = 1;
6724         list_add(&tv.head, &list);
6725
6726         r = ttm_eu_reserve_buffers(&ticket, &list, false, NULL);
6727         if (r) {
6728                 dev_err(adev->dev, "fail to reserve bo (%d)\n", r);
6729                 return r;
6730         }
6731
6732         if (plane->type != DRM_PLANE_TYPE_CURSOR)
6733                 domain = amdgpu_display_supported_domains(adev, rbo->flags);
6734         else
6735                 domain = AMDGPU_GEM_DOMAIN_VRAM;
6736
6737         r = amdgpu_bo_pin(rbo, domain);
6738         if (unlikely(r != 0)) {
6739                 if (r != -ERESTARTSYS)
6740                         DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
6741                 ttm_eu_backoff_reservation(&ticket, &list);
6742                 return r;
6743         }
6744
6745         r = amdgpu_ttm_alloc_gart(&rbo->tbo);
6746         if (unlikely(r != 0)) {
6747                 amdgpu_bo_unpin(rbo);
6748                 ttm_eu_backoff_reservation(&ticket, &list);
6749                 DRM_ERROR("%p bind failed\n", rbo);
6750                 return r;
6751         }
6752
6753         ttm_eu_backoff_reservation(&ticket, &list);
6754
6755         afb->address = amdgpu_bo_gpu_offset(rbo);
6756
6757         amdgpu_bo_ref(rbo);
6758
6759         /**
6760          * We don't do surface updates on planes that have been newly created,
6761          * but we also don't have the afb->address during atomic check.
6762          *
6763          * Fill in buffer attributes depending on the address here, but only on
6764          * newly created planes since they're not being used by DC yet and this
6765          * won't modify global state.
6766          */
6767         dm_plane_state_old = to_dm_plane_state(plane->state);
6768         dm_plane_state_new = to_dm_plane_state(new_state);
6769
6770         if (dm_plane_state_new->dc_state &&
6771             dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
6772                 struct dc_plane_state *plane_state =
6773                         dm_plane_state_new->dc_state;
6774                 bool force_disable_dcc = !plane_state->dcc.enable;
6775
6776                 fill_plane_buffer_attributes(
6777                         adev, afb, plane_state->format, plane_state->rotation,
6778                         afb->tiling_flags,
6779                         &plane_state->tiling_info, &plane_state->plane_size,
6780                         &plane_state->dcc, &plane_state->address,
6781                         afb->tmz_surface, force_disable_dcc);
6782         }
6783
6784         return 0;
6785 }
6786
6787 static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
6788                                        struct drm_plane_state *old_state)
6789 {
6790         struct amdgpu_bo *rbo;
6791         int r;
6792
6793         if (!old_state->fb)
6794                 return;
6795
6796         rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]);
6797         r = amdgpu_bo_reserve(rbo, false);
6798         if (unlikely(r)) {
6799                 DRM_ERROR("failed to reserve rbo before unpin\n");
6800                 return;
6801         }
6802
6803         amdgpu_bo_unpin(rbo);
6804         amdgpu_bo_unreserve(rbo);
6805         amdgpu_bo_unref(&rbo);
6806 }
6807
6808 static int dm_plane_helper_check_state(struct drm_plane_state *state,
6809                                        struct drm_crtc_state *new_crtc_state)
6810 {
6811         struct drm_framebuffer *fb = state->fb;
6812         int min_downscale, max_upscale;
6813         int min_scale = 0;
6814         int max_scale = INT_MAX;
6815
6816         /* Plane enabled? Validate viewport and get scaling factors from plane caps. */
6817         if (fb && state->crtc) {
6818                 /* Validate viewport to cover the case when only the position changes */
6819                 if (state->plane->type != DRM_PLANE_TYPE_CURSOR) {
6820                         int viewport_width = state->crtc_w;
6821                         int viewport_height = state->crtc_h;
6822
6823                         if (state->crtc_x < 0)
6824                                 viewport_width += state->crtc_x;
6825                         else if (state->crtc_x + state->crtc_w > new_crtc_state->mode.crtc_hdisplay)
6826                                 viewport_width = new_crtc_state->mode.crtc_hdisplay - state->crtc_x;
6827
6828                         if (state->crtc_y < 0)
6829                                 viewport_height += state->crtc_y;
6830                         else if (state->crtc_y + state->crtc_h > new_crtc_state->mode.crtc_vdisplay)
6831                                 viewport_height = new_crtc_state->mode.crtc_vdisplay - state->crtc_y;
6832
6833                         if (viewport_width < 0 || viewport_height < 0) {
6834                                 DRM_DEBUG_ATOMIC("Plane completely outside of screen\n");
6835                                 return -EINVAL;
6836                         } else if (viewport_width < MIN_VIEWPORT_SIZE*2) { /* x2 for width is because of pipe-split. */
6837                                 DRM_DEBUG_ATOMIC("Viewport width %d smaller than %d\n", viewport_width, MIN_VIEWPORT_SIZE*2);
6838                                 return -EINVAL;
6839                         } else if (viewport_height < MIN_VIEWPORT_SIZE) {
6840                                 DRM_DEBUG_ATOMIC("Viewport height %d smaller than %d\n", viewport_height, MIN_VIEWPORT_SIZE);
6841                                 return -EINVAL;
6842                         }
6843
6844                 }
6845
6846                 /* Get min/max allowed scaling factors from plane caps. */
6847                 get_min_max_dc_plane_scaling(state->crtc->dev, fb,
6848                                              &min_downscale, &max_upscale);
6849                 /*
6850                  * Convert to drm convention: 16.16 fixed point, instead of dc's
6851                  * 1.0 == 1000. Also drm scaling is src/dst instead of dc's
6852                  * dst/src, so min_scale = 1.0 / max_upscale, etc.
6853                  */
6854                 min_scale = (1000 << 16) / max_upscale;
6855                 max_scale = (1000 << 16) / min_downscale;
6856         }
6857
6858         return drm_atomic_helper_check_plane_state(
6859                 state, new_crtc_state, min_scale, max_scale, true, true);
6860 }
6861
6862 static int dm_plane_atomic_check(struct drm_plane *plane,
6863                                  struct drm_atomic_state *state)
6864 {
6865         struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
6866                                                                                  plane);
6867         struct amdgpu_device *adev = drm_to_adev(plane->dev);
6868         struct dc *dc = adev->dm.dc;
6869         struct dm_plane_state *dm_plane_state;
6870         struct dc_scaling_info scaling_info;
6871         struct drm_crtc_state *new_crtc_state;
6872         int ret;
6873
6874         trace_amdgpu_dm_plane_atomic_check(new_plane_state);
6875
6876         dm_plane_state = to_dm_plane_state(new_plane_state);
6877
6878         if (!dm_plane_state->dc_state)
6879                 return 0;
6880
6881         new_crtc_state =
6882                 drm_atomic_get_new_crtc_state(state,
6883                                               new_plane_state->crtc);
6884         if (!new_crtc_state)
6885                 return -EINVAL;
6886
6887         ret = dm_plane_helper_check_state(new_plane_state, new_crtc_state);
6888         if (ret)
6889                 return ret;
6890
6891         ret = fill_dc_scaling_info(new_plane_state, &scaling_info);
6892         if (ret)
6893                 return ret;
6894
6895         if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
6896                 return 0;
6897
6898         return -EINVAL;
6899 }
6900
6901 static int dm_plane_atomic_async_check(struct drm_plane *plane,
6902                                        struct drm_atomic_state *state)
6903 {
6904         /* Only support async updates on cursor planes. */
6905         if (plane->type != DRM_PLANE_TYPE_CURSOR)
6906                 return -EINVAL;
6907
6908         return 0;
6909 }
6910
6911 static void dm_plane_atomic_async_update(struct drm_plane *plane,
6912                                          struct drm_atomic_state *state)
6913 {
6914         struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
6915                                                                            plane);
6916         struct drm_plane_state *old_state =
6917                 drm_atomic_get_old_plane_state(state, plane);
6918
6919         trace_amdgpu_dm_atomic_update_cursor(new_state);
6920
6921         swap(plane->state->fb, new_state->fb);
6922
6923         plane->state->src_x = new_state->src_x;
6924         plane->state->src_y = new_state->src_y;
6925         plane->state->src_w = new_state->src_w;
6926         plane->state->src_h = new_state->src_h;
6927         plane->state->crtc_x = new_state->crtc_x;
6928         plane->state->crtc_y = new_state->crtc_y;
6929         plane->state->crtc_w = new_state->crtc_w;
6930         plane->state->crtc_h = new_state->crtc_h;
6931
6932         handle_cursor_update(plane, old_state);
6933 }
6934
6935 static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
6936         .prepare_fb = dm_plane_helper_prepare_fb,
6937         .cleanup_fb = dm_plane_helper_cleanup_fb,
6938         .atomic_check = dm_plane_atomic_check,
6939         .atomic_async_check = dm_plane_atomic_async_check,
6940         .atomic_async_update = dm_plane_atomic_async_update
6941 };
6942
6943 /*
6944  * TODO: these are currently initialized to rgb formats only.
6945  * For future use cases we should either initialize them dynamically based on
6946  * plane capabilities, or initialize this array to all formats, so internal drm
6947  * check will succeed, and let DC implement proper check
6948  */
6949 static const uint32_t rgb_formats[] = {
6950         DRM_FORMAT_XRGB8888,
6951         DRM_FORMAT_ARGB8888,
6952         DRM_FORMAT_RGBA8888,
6953         DRM_FORMAT_XRGB2101010,
6954         DRM_FORMAT_XBGR2101010,
6955         DRM_FORMAT_ARGB2101010,
6956         DRM_FORMAT_ABGR2101010,
6957         DRM_FORMAT_XBGR8888,
6958         DRM_FORMAT_ABGR8888,
6959         DRM_FORMAT_RGB565,
6960 };
6961
6962 static const uint32_t overlay_formats[] = {
6963         DRM_FORMAT_XRGB8888,
6964         DRM_FORMAT_ARGB8888,
6965         DRM_FORMAT_RGBA8888,
6966         DRM_FORMAT_XBGR8888,
6967         DRM_FORMAT_ABGR8888,
6968         DRM_FORMAT_RGB565
6969 };
6970
6971 static const u32 cursor_formats[] = {
6972         DRM_FORMAT_ARGB8888
6973 };
6974
6975 static int get_plane_formats(const struct drm_plane *plane,
6976                              const struct dc_plane_cap *plane_cap,
6977                              uint32_t *formats, int max_formats)
6978 {
6979         int i, num_formats = 0;
6980
6981         /*
6982          * TODO: Query support for each group of formats directly from
6983          * DC plane caps. This will require adding more formats to the
6984          * caps list.
6985          */
6986
6987         switch (plane->type) {
6988         case DRM_PLANE_TYPE_PRIMARY:
6989                 for (i = 0; i < ARRAY_SIZE(rgb_formats); ++i) {
6990                         if (num_formats >= max_formats)
6991                                 break;
6992
6993                         formats[num_formats++] = rgb_formats[i];
6994                 }
6995
6996                 if (plane_cap && plane_cap->pixel_format_support.nv12)
6997                         formats[num_formats++] = DRM_FORMAT_NV12;
6998                 if (plane_cap && plane_cap->pixel_format_support.p010)
6999                         formats[num_formats++] = DRM_FORMAT_P010;
7000                 if (plane_cap && plane_cap->pixel_format_support.fp16) {
7001                         formats[num_formats++] = DRM_FORMAT_XRGB16161616F;
7002                         formats[num_formats++] = DRM_FORMAT_ARGB16161616F;
7003                         formats[num_formats++] = DRM_FORMAT_XBGR16161616F;
7004                         formats[num_formats++] = DRM_FORMAT_ABGR16161616F;
7005                 }
7006                 break;
7007
7008         case DRM_PLANE_TYPE_OVERLAY:
7009                 for (i = 0; i < ARRAY_SIZE(overlay_formats); ++i) {
7010                         if (num_formats >= max_formats)
7011                                 break;
7012
7013                         formats[num_formats++] = overlay_formats[i];
7014                 }
7015                 break;
7016
7017         case DRM_PLANE_TYPE_CURSOR:
7018                 for (i = 0; i < ARRAY_SIZE(cursor_formats); ++i) {
7019                         if (num_formats >= max_formats)
7020                                 break;
7021
7022                         formats[num_formats++] = cursor_formats[i];
7023                 }
7024                 break;
7025         }
7026
7027         return num_formats;
7028 }
7029
7030 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
7031                                 struct drm_plane *plane,
7032                                 unsigned long possible_crtcs,
7033                                 const struct dc_plane_cap *plane_cap)
7034 {
7035         uint32_t formats[32];
7036         int num_formats;
7037         int res = -EPERM;
7038         unsigned int supported_rotations;
7039         uint64_t *modifiers = NULL;
7040
7041         num_formats = get_plane_formats(plane, plane_cap, formats,
7042                                         ARRAY_SIZE(formats));
7043
7044         res = get_plane_modifiers(dm->adev, plane->type, &modifiers);
7045         if (res)
7046                 return res;
7047
7048         res = drm_universal_plane_init(adev_to_drm(dm->adev), plane, possible_crtcs,
7049                                        &dm_plane_funcs, formats, num_formats,
7050                                        modifiers, plane->type, NULL);
7051         kfree(modifiers);
7052         if (res)
7053                 return res;
7054
7055         if (plane->type == DRM_PLANE_TYPE_OVERLAY &&
7056             plane_cap && plane_cap->per_pixel_alpha) {
7057                 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
7058                                           BIT(DRM_MODE_BLEND_PREMULTI);
7059
7060                 drm_plane_create_alpha_property(plane);
7061                 drm_plane_create_blend_mode_property(plane, blend_caps);
7062         }
7063
7064         if (plane->type == DRM_PLANE_TYPE_PRIMARY &&
7065             plane_cap &&
7066             (plane_cap->pixel_format_support.nv12 ||
7067              plane_cap->pixel_format_support.p010)) {
7068                 /* This only affects YUV formats. */
7069                 drm_plane_create_color_properties(
7070                         plane,
7071                         BIT(DRM_COLOR_YCBCR_BT601) |
7072                         BIT(DRM_COLOR_YCBCR_BT709) |
7073                         BIT(DRM_COLOR_YCBCR_BT2020),
7074                         BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
7075                         BIT(DRM_COLOR_YCBCR_FULL_RANGE),
7076                         DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE);
7077         }
7078
7079         supported_rotations =
7080                 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
7081                 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
7082
7083         if (dm->adev->asic_type >= CHIP_BONAIRE &&
7084             plane->type != DRM_PLANE_TYPE_CURSOR)
7085                 drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0,
7086                                                    supported_rotations);
7087
7088         drm_plane_helper_add(plane, &dm_plane_helper_funcs);
7089
7090         /* Create (reset) the plane state */
7091         if (plane->funcs->reset)
7092                 plane->funcs->reset(plane);
7093
7094         return 0;
7095 }
7096
7097 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
7098                                struct drm_plane *plane,
7099                                uint32_t crtc_index)
7100 {
7101         struct amdgpu_crtc *acrtc = NULL;
7102         struct drm_plane *cursor_plane;
7103
7104         int res = -ENOMEM;
7105
7106         cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
7107         if (!cursor_plane)
7108                 goto fail;
7109
7110         cursor_plane->type = DRM_PLANE_TYPE_CURSOR;
7111         res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL);
7112
7113         acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
7114         if (!acrtc)
7115                 goto fail;
7116
7117         res = drm_crtc_init_with_planes(
7118                         dm->ddev,
7119                         &acrtc->base,
7120                         plane,
7121                         cursor_plane,
7122                         &amdgpu_dm_crtc_funcs, NULL);
7123
7124         if (res)
7125                 goto fail;
7126
7127         drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
7128
7129         /* Create (reset) the plane state */
7130         if (acrtc->base.funcs->reset)
7131                 acrtc->base.funcs->reset(&acrtc->base);
7132
7133         acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
7134         acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
7135
7136         acrtc->crtc_id = crtc_index;
7137         acrtc->base.enabled = false;
7138         acrtc->otg_inst = -1;
7139
7140         dm->adev->mode_info.crtcs[crtc_index] = acrtc;
7141         drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
7142                                    true, MAX_COLOR_LUT_ENTRIES);
7143         drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
7144
7145         return 0;
7146
7147 fail:
7148         kfree(acrtc);
7149         kfree(cursor_plane);
7150         return res;
7151 }
7152
7153
7154 static int to_drm_connector_type(enum signal_type st)
7155 {
7156         switch (st) {
7157         case SIGNAL_TYPE_HDMI_TYPE_A:
7158                 return DRM_MODE_CONNECTOR_HDMIA;
7159         case SIGNAL_TYPE_EDP:
7160                 return DRM_MODE_CONNECTOR_eDP;
7161         case SIGNAL_TYPE_LVDS:
7162                 return DRM_MODE_CONNECTOR_LVDS;
7163         case SIGNAL_TYPE_RGB:
7164                 return DRM_MODE_CONNECTOR_VGA;
7165         case SIGNAL_TYPE_DISPLAY_PORT:
7166         case SIGNAL_TYPE_DISPLAY_PORT_MST:
7167                 return DRM_MODE_CONNECTOR_DisplayPort;
7168         case SIGNAL_TYPE_DVI_DUAL_LINK:
7169         case SIGNAL_TYPE_DVI_SINGLE_LINK:
7170                 return DRM_MODE_CONNECTOR_DVID;
7171         case SIGNAL_TYPE_VIRTUAL:
7172                 return DRM_MODE_CONNECTOR_VIRTUAL;
7173
7174         default:
7175                 return DRM_MODE_CONNECTOR_Unknown;
7176         }
7177 }
7178
7179 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
7180 {
7181         struct drm_encoder *encoder;
7182
7183         /* There is only one encoder per connector */
7184         drm_connector_for_each_possible_encoder(connector, encoder)
7185                 return encoder;
7186
7187         return NULL;
7188 }
7189
7190 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
7191 {
7192         struct drm_encoder *encoder;
7193         struct amdgpu_encoder *amdgpu_encoder;
7194
7195         encoder = amdgpu_dm_connector_to_encoder(connector);
7196
7197         if (encoder == NULL)
7198                 return;
7199
7200         amdgpu_encoder = to_amdgpu_encoder(encoder);
7201
7202         amdgpu_encoder->native_mode.clock = 0;
7203
7204         if (!list_empty(&connector->probed_modes)) {
7205                 struct drm_display_mode *preferred_mode = NULL;
7206
7207                 list_for_each_entry(preferred_mode,
7208                                     &connector->probed_modes,
7209                                     head) {
7210                         if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
7211                                 amdgpu_encoder->native_mode = *preferred_mode;
7212
7213                         break;
7214                 }
7215
7216         }
7217 }
7218
7219 static struct drm_display_mode *
7220 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
7221                              char *name,
7222                              int hdisplay, int vdisplay)
7223 {
7224         struct drm_device *dev = encoder->dev;
7225         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
7226         struct drm_display_mode *mode = NULL;
7227         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
7228
7229         mode = drm_mode_duplicate(dev, native_mode);
7230
7231         if (mode == NULL)
7232                 return NULL;
7233
7234         mode->hdisplay = hdisplay;
7235         mode->vdisplay = vdisplay;
7236         mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7237         strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
7238
7239         return mode;
7240
7241 }
7242
7243 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
7244                                                  struct drm_connector *connector)
7245 {
7246         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
7247         struct drm_display_mode *mode = NULL;
7248         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
7249         struct amdgpu_dm_connector *amdgpu_dm_connector =
7250                                 to_amdgpu_dm_connector(connector);
7251         int i;
7252         int n;
7253         struct mode_size {
7254                 char name[DRM_DISPLAY_MODE_LEN];
7255                 int w;
7256                 int h;
7257         } common_modes[] = {
7258                 {  "640x480",  640,  480},
7259                 {  "800x600",  800,  600},
7260                 { "1024x768", 1024,  768},
7261                 { "1280x720", 1280,  720},
7262                 { "1280x800", 1280,  800},
7263                 {"1280x1024", 1280, 1024},
7264                 { "1440x900", 1440,  900},
7265                 {"1680x1050", 1680, 1050},
7266                 {"1600x1200", 1600, 1200},
7267                 {"1920x1080", 1920, 1080},
7268                 {"1920x1200", 1920, 1200}
7269         };
7270
7271         n = ARRAY_SIZE(common_modes);
7272
7273         for (i = 0; i < n; i++) {
7274                 struct drm_display_mode *curmode = NULL;
7275                 bool mode_existed = false;
7276
7277                 if (common_modes[i].w > native_mode->hdisplay ||
7278                     common_modes[i].h > native_mode->vdisplay ||
7279                    (common_modes[i].w == native_mode->hdisplay &&
7280                     common_modes[i].h == native_mode->vdisplay))
7281                         continue;
7282
7283                 list_for_each_entry(curmode, &connector->probed_modes, head) {
7284                         if (common_modes[i].w == curmode->hdisplay &&
7285                             common_modes[i].h == curmode->vdisplay) {
7286                                 mode_existed = true;
7287                                 break;
7288                         }
7289                 }
7290
7291                 if (mode_existed)
7292                         continue;
7293
7294                 mode = amdgpu_dm_create_common_mode(encoder,
7295                                 common_modes[i].name, common_modes[i].w,
7296                                 common_modes[i].h);
7297                 drm_mode_probed_add(connector, mode);
7298                 amdgpu_dm_connector->num_modes++;
7299         }
7300 }
7301
7302 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
7303                                               struct edid *edid)
7304 {
7305         struct amdgpu_dm_connector *amdgpu_dm_connector =
7306                         to_amdgpu_dm_connector(connector);
7307
7308         if (edid) {
7309                 /* empty probed_modes */
7310                 INIT_LIST_HEAD(&connector->probed_modes);
7311                 amdgpu_dm_connector->num_modes =
7312                                 drm_add_edid_modes(connector, edid);
7313
7314                 /* sorting the probed modes before calling function
7315                  * amdgpu_dm_get_native_mode() since EDID can have
7316                  * more than one preferred mode. The modes that are
7317                  * later in the probed mode list could be of higher
7318                  * and preferred resolution. For example, 3840x2160
7319                  * resolution in base EDID preferred timing and 4096x2160
7320                  * preferred resolution in DID extension block later.
7321                  */
7322                 drm_mode_sort(&connector->probed_modes);
7323                 amdgpu_dm_get_native_mode(connector);
7324
7325                 /* Freesync capabilities are reset by calling
7326                  * drm_add_edid_modes() and need to be
7327                  * restored here.
7328                  */
7329                 amdgpu_dm_update_freesync_caps(connector, edid);
7330         } else {
7331                 amdgpu_dm_connector->num_modes = 0;
7332         }
7333 }
7334
7335 static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector,
7336                               struct drm_display_mode *mode)
7337 {
7338         struct drm_display_mode *m;
7339
7340         list_for_each_entry (m, &aconnector->base.probed_modes, head) {
7341                 if (drm_mode_equal(m, mode))
7342                         return true;
7343         }
7344
7345         return false;
7346 }
7347
7348 static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)
7349 {
7350         const struct drm_display_mode *m;
7351         struct drm_display_mode *new_mode;
7352         uint i;
7353         uint32_t new_modes_count = 0;
7354
7355         /* Standard FPS values
7356          *
7357          * 23.976   - TV/NTSC
7358          * 24       - Cinema
7359          * 25       - TV/PAL
7360          * 29.97    - TV/NTSC
7361          * 30       - TV/NTSC
7362          * 48       - Cinema HFR
7363          * 50       - TV/PAL
7364          * 60       - Commonly used
7365          * 48,72,96 - Multiples of 24
7366          */
7367         const uint32_t common_rates[] = { 23976, 24000, 25000, 29970, 30000,
7368                                          48000, 50000, 60000, 72000, 96000 };
7369
7370         /*
7371          * Find mode with highest refresh rate with the same resolution
7372          * as the preferred mode. Some monitors report a preferred mode
7373          * with lower resolution than the highest refresh rate supported.
7374          */
7375
7376         m = get_highest_refresh_rate_mode(aconnector, true);
7377         if (!m)
7378                 return 0;
7379
7380         for (i = 0; i < ARRAY_SIZE(common_rates); i++) {
7381                 uint64_t target_vtotal, target_vtotal_diff;
7382                 uint64_t num, den;
7383
7384                 if (drm_mode_vrefresh(m) * 1000 < common_rates[i])
7385                         continue;
7386
7387                 if (common_rates[i] < aconnector->min_vfreq * 1000 ||
7388                     common_rates[i] > aconnector->max_vfreq * 1000)
7389                         continue;
7390
7391                 num = (unsigned long long)m->clock * 1000 * 1000;
7392                 den = common_rates[i] * (unsigned long long)m->htotal;
7393                 target_vtotal = div_u64(num, den);
7394                 target_vtotal_diff = target_vtotal - m->vtotal;
7395
7396                 /* Check for illegal modes */
7397                 if (m->vsync_start + target_vtotal_diff < m->vdisplay ||
7398                     m->vsync_end + target_vtotal_diff < m->vsync_start ||
7399                     m->vtotal + target_vtotal_diff < m->vsync_end)
7400                         continue;
7401
7402                 new_mode = drm_mode_duplicate(aconnector->base.dev, m);
7403                 if (!new_mode)
7404                         goto out;
7405
7406                 new_mode->vtotal += (u16)target_vtotal_diff;
7407                 new_mode->vsync_start += (u16)target_vtotal_diff;
7408                 new_mode->vsync_end += (u16)target_vtotal_diff;
7409                 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7410                 new_mode->type |= DRM_MODE_TYPE_DRIVER;
7411
7412                 if (!is_duplicate_mode(aconnector, new_mode)) {
7413                         drm_mode_probed_add(&aconnector->base, new_mode);
7414                         new_modes_count += 1;
7415                 } else
7416                         drm_mode_destroy(aconnector->base.dev, new_mode);
7417         }
7418  out:
7419         return new_modes_count;
7420 }
7421
7422 static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector,
7423                                                    struct edid *edid)
7424 {
7425         struct amdgpu_dm_connector *amdgpu_dm_connector =
7426                 to_amdgpu_dm_connector(connector);
7427
7428         if (!(amdgpu_freesync_vid_mode && edid))
7429                 return;
7430
7431         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
7432                 amdgpu_dm_connector->num_modes +=
7433                         add_fs_modes(amdgpu_dm_connector);
7434 }
7435
7436 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
7437 {
7438         struct amdgpu_dm_connector *amdgpu_dm_connector =
7439                         to_amdgpu_dm_connector(connector);
7440         struct drm_encoder *encoder;
7441         struct edid *edid = amdgpu_dm_connector->edid;
7442
7443         encoder = amdgpu_dm_connector_to_encoder(connector);
7444
7445         if (!drm_edid_is_valid(edid)) {
7446                 amdgpu_dm_connector->num_modes =
7447                                 drm_add_modes_noedid(connector, 640, 480);
7448         } else {
7449                 amdgpu_dm_connector_ddc_get_modes(connector, edid);
7450                 amdgpu_dm_connector_add_common_modes(encoder, connector);
7451                 amdgpu_dm_connector_add_freesync_modes(connector, edid);
7452         }
7453         amdgpu_dm_fbc_init(connector);
7454
7455         return amdgpu_dm_connector->num_modes;
7456 }
7457
7458 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
7459                                      struct amdgpu_dm_connector *aconnector,
7460                                      int connector_type,
7461                                      struct dc_link *link,
7462                                      int link_index)
7463 {
7464         struct amdgpu_device *adev = drm_to_adev(dm->ddev);
7465
7466         /*
7467          * Some of the properties below require access to state, like bpc.
7468          * Allocate some default initial connector state with our reset helper.
7469          */
7470         if (aconnector->base.funcs->reset)
7471                 aconnector->base.funcs->reset(&aconnector->base);
7472
7473         aconnector->connector_id = link_index;
7474         aconnector->dc_link = link;
7475         aconnector->base.interlace_allowed = false;
7476         aconnector->base.doublescan_allowed = false;
7477         aconnector->base.stereo_allowed = false;
7478         aconnector->base.dpms = DRM_MODE_DPMS_OFF;
7479         aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
7480         aconnector->audio_inst = -1;
7481         mutex_init(&aconnector->hpd_lock);
7482
7483         /*
7484          * configure support HPD hot plug connector_>polled default value is 0
7485          * which means HPD hot plug not supported
7486          */
7487         switch (connector_type) {
7488         case DRM_MODE_CONNECTOR_HDMIA:
7489                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7490                 aconnector->base.ycbcr_420_allowed =
7491                         link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
7492                 break;
7493         case DRM_MODE_CONNECTOR_DisplayPort:
7494                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7495                 aconnector->base.ycbcr_420_allowed =
7496                         link->link_enc->features.dp_ycbcr420_supported ? true : false;
7497                 break;
7498         case DRM_MODE_CONNECTOR_DVID:
7499                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7500                 break;
7501         default:
7502                 break;
7503         }
7504
7505         drm_object_attach_property(&aconnector->base.base,
7506                                 dm->ddev->mode_config.scaling_mode_property,
7507                                 DRM_MODE_SCALE_NONE);
7508
7509         drm_object_attach_property(&aconnector->base.base,
7510                                 adev->mode_info.underscan_property,
7511                                 UNDERSCAN_OFF);
7512         drm_object_attach_property(&aconnector->base.base,
7513                                 adev->mode_info.underscan_hborder_property,
7514                                 0);
7515         drm_object_attach_property(&aconnector->base.base,
7516                                 adev->mode_info.underscan_vborder_property,
7517                                 0);
7518
7519         if (!aconnector->mst_port)
7520                 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
7521
7522         /* This defaults to the max in the range, but we want 8bpc for non-edp. */
7523         aconnector->base.state->max_bpc = (connector_type == DRM_MODE_CONNECTOR_eDP) ? 16 : 8;
7524         aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
7525
7526         if (connector_type == DRM_MODE_CONNECTOR_eDP &&
7527             (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) {
7528                 drm_object_attach_property(&aconnector->base.base,
7529                                 adev->mode_info.abm_level_property, 0);
7530         }
7531
7532         if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
7533             connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
7534             connector_type == DRM_MODE_CONNECTOR_eDP) {
7535                 drm_object_attach_property(
7536                         &aconnector->base.base,
7537                         dm->ddev->mode_config.hdr_output_metadata_property, 0);
7538
7539                 if (!aconnector->mst_port)
7540                         drm_connector_attach_vrr_capable_property(&aconnector->base);
7541
7542 #ifdef CONFIG_DRM_AMD_DC_HDCP
7543                 if (adev->dm.hdcp_workqueue)
7544                         drm_connector_attach_content_protection_property(&aconnector->base, true);
7545 #endif
7546         }
7547 }
7548
7549 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
7550                               struct i2c_msg *msgs, int num)
7551 {
7552         struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
7553         struct ddc_service *ddc_service = i2c->ddc_service;
7554         struct i2c_command cmd;
7555         int i;
7556         int result = -EIO;
7557
7558         cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
7559
7560         if (!cmd.payloads)
7561                 return result;
7562
7563         cmd.number_of_payloads = num;
7564         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
7565         cmd.speed = 100;
7566
7567         for (i = 0; i < num; i++) {
7568                 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
7569                 cmd.payloads[i].address = msgs[i].addr;
7570                 cmd.payloads[i].length = msgs[i].len;
7571                 cmd.payloads[i].data = msgs[i].buf;
7572         }
7573
7574         if (dc_submit_i2c(
7575                         ddc_service->ctx->dc,
7576                         ddc_service->ddc_pin->hw_info.ddc_channel,
7577                         &cmd))
7578                 result = num;
7579
7580         kfree(cmd.payloads);
7581         return result;
7582 }
7583
7584 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
7585 {
7586         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
7587 }
7588
7589 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
7590         .master_xfer = amdgpu_dm_i2c_xfer,
7591         .functionality = amdgpu_dm_i2c_func,
7592 };
7593
7594 static struct amdgpu_i2c_adapter *
7595 create_i2c(struct ddc_service *ddc_service,
7596            int link_index,
7597            int *res)
7598 {
7599         struct amdgpu_device *adev = ddc_service->ctx->driver_context;
7600         struct amdgpu_i2c_adapter *i2c;
7601
7602         i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
7603         if (!i2c)
7604                 return NULL;
7605         i2c->base.owner = THIS_MODULE;
7606         i2c->base.class = I2C_CLASS_DDC;
7607         i2c->base.dev.parent = &adev->pdev->dev;
7608         i2c->base.algo = &amdgpu_dm_i2c_algo;
7609         snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
7610         i2c_set_adapdata(&i2c->base, i2c);
7611         i2c->ddc_service = ddc_service;
7612         i2c->ddc_service->ddc_pin->hw_info.ddc_channel = link_index;
7613
7614         return i2c;
7615 }
7616
7617
7618 /*
7619  * Note: this function assumes that dc_link_detect() was called for the
7620  * dc_link which will be represented by this aconnector.
7621  */
7622 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
7623                                     struct amdgpu_dm_connector *aconnector,
7624                                     uint32_t link_index,
7625                                     struct amdgpu_encoder *aencoder)
7626 {
7627         int res = 0;
7628         int connector_type;
7629         struct dc *dc = dm->dc;
7630         struct dc_link *link = dc_get_link_at_index(dc, link_index);
7631         struct amdgpu_i2c_adapter *i2c;
7632
7633         link->priv = aconnector;
7634
7635         DRM_DEBUG_DRIVER("%s()\n", __func__);
7636
7637         i2c = create_i2c(link->ddc, link->link_index, &res);
7638         if (!i2c) {
7639                 DRM_ERROR("Failed to create i2c adapter data\n");
7640                 return -ENOMEM;
7641         }
7642
7643         aconnector->i2c = i2c;
7644         res = i2c_add_adapter(&i2c->base);
7645
7646         if (res) {
7647                 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
7648                 goto out_free;
7649         }
7650
7651         connector_type = to_drm_connector_type(link->connector_signal);
7652
7653         res = drm_connector_init_with_ddc(
7654                         dm->ddev,
7655                         &aconnector->base,
7656                         &amdgpu_dm_connector_funcs,
7657                         connector_type,
7658                         &i2c->base);
7659
7660         if (res) {
7661                 DRM_ERROR("connector_init failed\n");
7662                 aconnector->connector_id = -1;
7663                 goto out_free;
7664         }
7665
7666         drm_connector_helper_add(
7667                         &aconnector->base,
7668                         &amdgpu_dm_connector_helper_funcs);
7669
7670         amdgpu_dm_connector_init_helper(
7671                 dm,
7672                 aconnector,
7673                 connector_type,
7674                 link,
7675                 link_index);
7676
7677         drm_connector_attach_encoder(
7678                 &aconnector->base, &aencoder->base);
7679
7680         if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
7681                 || connector_type == DRM_MODE_CONNECTOR_eDP)
7682                 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);
7683
7684 out_free:
7685         if (res) {
7686                 kfree(i2c);
7687                 aconnector->i2c = NULL;
7688         }
7689         return res;
7690 }
7691
7692 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
7693 {
7694         switch (adev->mode_info.num_crtc) {
7695         case 1:
7696                 return 0x1;
7697         case 2:
7698                 return 0x3;
7699         case 3:
7700                 return 0x7;
7701         case 4:
7702                 return 0xf;
7703         case 5:
7704                 return 0x1f;
7705         case 6:
7706         default:
7707                 return 0x3f;
7708         }
7709 }
7710
7711 static int amdgpu_dm_encoder_init(struct drm_device *dev,
7712                                   struct amdgpu_encoder *aencoder,
7713                                   uint32_t link_index)
7714 {
7715         struct amdgpu_device *adev = drm_to_adev(dev);
7716
7717         int res = drm_encoder_init(dev,
7718                                    &aencoder->base,
7719                                    &amdgpu_dm_encoder_funcs,
7720                                    DRM_MODE_ENCODER_TMDS,
7721                                    NULL);
7722
7723         aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
7724
7725         if (!res)
7726                 aencoder->encoder_id = link_index;
7727         else
7728                 aencoder->encoder_id = -1;
7729
7730         drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
7731
7732         return res;
7733 }
7734
7735 static void manage_dm_interrupts(struct amdgpu_device *adev,
7736                                  struct amdgpu_crtc *acrtc,
7737                                  bool enable)
7738 {
7739         /*
7740          * We have no guarantee that the frontend index maps to the same
7741          * backend index - some even map to more than one.
7742          *
7743          * TODO: Use a different interrupt or check DC itself for the mapping.
7744          */
7745         int irq_type =
7746                 amdgpu_display_crtc_idx_to_irq_type(
7747                         adev,
7748                         acrtc->crtc_id);
7749
7750         if (enable) {
7751                 drm_crtc_vblank_on(&acrtc->base);
7752                 amdgpu_irq_get(
7753                         adev,
7754                         &adev->pageflip_irq,
7755                         irq_type);
7756 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7757                 amdgpu_irq_get(
7758                         adev,
7759                         &adev->vline0_irq,
7760                         irq_type);
7761 #endif
7762         } else {
7763 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7764                 amdgpu_irq_put(
7765                         adev,
7766                         &adev->vline0_irq,
7767                         irq_type);
7768 #endif
7769                 amdgpu_irq_put(
7770                         adev,
7771                         &adev->pageflip_irq,
7772                         irq_type);
7773                 drm_crtc_vblank_off(&acrtc->base);
7774         }
7775 }
7776
7777 static void dm_update_pflip_irq_state(struct amdgpu_device *adev,
7778                                       struct amdgpu_crtc *acrtc)
7779 {
7780         int irq_type =
7781                 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
7782
7783         /**
7784          * This reads the current state for the IRQ and force reapplies
7785          * the setting to hardware.
7786          */
7787         amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type);
7788 }
7789
7790 static bool
7791 is_scaling_state_different(const struct dm_connector_state *dm_state,
7792                            const struct dm_connector_state *old_dm_state)
7793 {
7794         if (dm_state->scaling != old_dm_state->scaling)
7795                 return true;
7796         if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
7797                 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
7798                         return true;
7799         } else  if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
7800                 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
7801                         return true;
7802         } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
7803                    dm_state->underscan_vborder != old_dm_state->underscan_vborder)
7804                 return true;
7805         return false;
7806 }
7807
7808 #ifdef CONFIG_DRM_AMD_DC_HDCP
7809 static bool is_content_protection_different(struct drm_connector_state *state,
7810                                             const struct drm_connector_state *old_state,
7811                                             const struct drm_connector *connector, struct hdcp_workqueue *hdcp_w)
7812 {
7813         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7814         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
7815
7816         /* Handle: Type0/1 change */
7817         if (old_state->hdcp_content_type != state->hdcp_content_type &&
7818             state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
7819                 state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7820                 return true;
7821         }
7822
7823         /* CP is being re enabled, ignore this
7824          *
7825          * Handles:     ENABLED -> DESIRED
7826          */
7827         if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
7828             state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7829                 state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
7830                 return false;
7831         }
7832
7833         /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED
7834          *
7835          * Handles:     UNDESIRED -> ENABLED
7836          */
7837         if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
7838             state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
7839                 state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7840
7841         /* Check if something is connected/enabled, otherwise we start hdcp but nothing is connected/enabled
7842          * hot-plug, headless s3, dpms
7843          *
7844          * Handles:     DESIRED -> DESIRED (Special case)
7845          */
7846         if (dm_con_state->update_hdcp && state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
7847             connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
7848                 dm_con_state->update_hdcp = false;
7849                 return true;
7850         }
7851
7852         /*
7853          * Handles:     UNDESIRED -> UNDESIRED
7854          *              DESIRED -> DESIRED
7855          *              ENABLED -> ENABLED
7856          */
7857         if (old_state->content_protection == state->content_protection)
7858                 return false;
7859
7860         /*
7861          * Handles:     UNDESIRED -> DESIRED
7862          *              DESIRED -> UNDESIRED
7863          *              ENABLED -> UNDESIRED
7864          */
7865         if (state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED)
7866                 return true;
7867
7868         /*
7869          * Handles:     DESIRED -> ENABLED
7870          */
7871         return false;
7872 }
7873
7874 #endif
7875 static void remove_stream(struct amdgpu_device *adev,
7876                           struct amdgpu_crtc *acrtc,
7877                           struct dc_stream_state *stream)
7878 {
7879         /* this is the update mode case */
7880
7881         acrtc->otg_inst = -1;
7882         acrtc->enabled = false;
7883 }
7884
7885 static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
7886                                struct dc_cursor_position *position)
7887 {
7888         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
7889         int x, y;
7890         int xorigin = 0, yorigin = 0;
7891
7892         if (!crtc || !plane->state->fb)
7893                 return 0;
7894
7895         if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
7896             (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
7897                 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
7898                           __func__,
7899                           plane->state->crtc_w,
7900                           plane->state->crtc_h);
7901                 return -EINVAL;
7902         }
7903
7904         x = plane->state->crtc_x;
7905         y = plane->state->crtc_y;
7906
7907         if (x <= -amdgpu_crtc->max_cursor_width ||
7908             y <= -amdgpu_crtc->max_cursor_height)
7909                 return 0;
7910
7911         if (x < 0) {
7912                 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
7913                 x = 0;
7914         }
7915         if (y < 0) {
7916                 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
7917                 y = 0;
7918         }
7919         position->enable = true;
7920         position->translate_by_source = true;
7921         position->x = x;
7922         position->y = y;
7923         position->x_hotspot = xorigin;
7924         position->y_hotspot = yorigin;
7925
7926         return 0;
7927 }
7928
7929 static void handle_cursor_update(struct drm_plane *plane,
7930                                  struct drm_plane_state *old_plane_state)
7931 {
7932         struct amdgpu_device *adev = drm_to_adev(plane->dev);
7933         struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
7934         struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
7935         struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
7936         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
7937         uint64_t address = afb ? afb->address : 0;
7938         struct dc_cursor_position position = {0};
7939         struct dc_cursor_attributes attributes;
7940         int ret;
7941
7942         if (!plane->state->fb && !old_plane_state->fb)
7943                 return;
7944
7945         DC_LOG_CURSOR("%s: crtc_id=%d with size %d to %d\n",
7946                       __func__,
7947                       amdgpu_crtc->crtc_id,
7948                       plane->state->crtc_w,
7949                       plane->state->crtc_h);
7950
7951         ret = get_cursor_position(plane, crtc, &position);
7952         if (ret)
7953                 return;
7954
7955         if (!position.enable) {
7956                 /* turn off cursor */
7957                 if (crtc_state && crtc_state->stream) {
7958                         mutex_lock(&adev->dm.dc_lock);
7959                         dc_stream_set_cursor_position(crtc_state->stream,
7960                                                       &position);
7961                         mutex_unlock(&adev->dm.dc_lock);
7962                 }
7963                 return;
7964         }
7965
7966         amdgpu_crtc->cursor_width = plane->state->crtc_w;
7967         amdgpu_crtc->cursor_height = plane->state->crtc_h;
7968
7969         memset(&attributes, 0, sizeof(attributes));
7970         attributes.address.high_part = upper_32_bits(address);
7971         attributes.address.low_part  = lower_32_bits(address);
7972         attributes.width             = plane->state->crtc_w;
7973         attributes.height            = plane->state->crtc_h;
7974         attributes.color_format      = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
7975         attributes.rotation_angle    = 0;
7976         attributes.attribute_flags.value = 0;
7977
7978         attributes.pitch = afb->base.pitches[0] / afb->base.format->cpp[0];
7979
7980         if (crtc_state->stream) {
7981                 mutex_lock(&adev->dm.dc_lock);
7982                 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
7983                                                          &attributes))
7984                         DRM_ERROR("DC failed to set cursor attributes\n");
7985
7986                 if (!dc_stream_set_cursor_position(crtc_state->stream,
7987                                                    &position))
7988                         DRM_ERROR("DC failed to set cursor position\n");
7989                 mutex_unlock(&adev->dm.dc_lock);
7990         }
7991 }
7992
7993 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
7994 {
7995
7996         assert_spin_locked(&acrtc->base.dev->event_lock);
7997         WARN_ON(acrtc->event);
7998
7999         acrtc->event = acrtc->base.state->event;
8000
8001         /* Set the flip status */
8002         acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
8003
8004         /* Mark this event as consumed */
8005         acrtc->base.state->event = NULL;
8006
8007         DC_LOG_PFLIP("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
8008                      acrtc->crtc_id);
8009 }
8010
8011 static void update_freesync_state_on_stream(
8012         struct amdgpu_display_manager *dm,
8013         struct dm_crtc_state *new_crtc_state,
8014         struct dc_stream_state *new_stream,
8015         struct dc_plane_state *surface,
8016         u32 flip_timestamp_in_us)
8017 {
8018         struct mod_vrr_params vrr_params;
8019         struct dc_info_packet vrr_infopacket = {0};
8020         struct amdgpu_device *adev = dm->adev;
8021         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
8022         unsigned long flags;
8023         bool pack_sdp_v1_3 = false;
8024
8025         if (!new_stream)
8026                 return;
8027
8028         /*
8029          * TODO: Determine why min/max totals and vrefresh can be 0 here.
8030          * For now it's sufficient to just guard against these conditions.
8031          */
8032
8033         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
8034                 return;
8035
8036         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8037         vrr_params = acrtc->dm_irq_params.vrr_params;
8038
8039         if (surface) {
8040                 mod_freesync_handle_preflip(
8041                         dm->freesync_module,
8042                         surface,
8043                         new_stream,
8044                         flip_timestamp_in_us,
8045                         &vrr_params);
8046
8047                 if (adev->family < AMDGPU_FAMILY_AI &&
8048                     amdgpu_dm_vrr_active(new_crtc_state)) {
8049                         mod_freesync_handle_v_update(dm->freesync_module,
8050                                                      new_stream, &vrr_params);
8051
8052                         /* Need to call this before the frame ends. */
8053                         dc_stream_adjust_vmin_vmax(dm->dc,
8054                                                    new_crtc_state->stream,
8055                                                    &vrr_params.adjust);
8056                 }
8057         }
8058
8059         mod_freesync_build_vrr_infopacket(
8060                 dm->freesync_module,
8061                 new_stream,
8062                 &vrr_params,
8063                 PACKET_TYPE_VRR,
8064                 TRANSFER_FUNC_UNKNOWN,
8065                 &vrr_infopacket,
8066                 pack_sdp_v1_3);
8067
8068         new_crtc_state->freesync_timing_changed |=
8069                 (memcmp(&acrtc->dm_irq_params.vrr_params.adjust,
8070                         &vrr_params.adjust,
8071                         sizeof(vrr_params.adjust)) != 0);
8072
8073         new_crtc_state->freesync_vrr_info_changed |=
8074                 (memcmp(&new_crtc_state->vrr_infopacket,
8075                         &vrr_infopacket,
8076                         sizeof(vrr_infopacket)) != 0);
8077
8078         acrtc->dm_irq_params.vrr_params = vrr_params;
8079         new_crtc_state->vrr_infopacket = vrr_infopacket;
8080
8081         new_stream->adjust = acrtc->dm_irq_params.vrr_params.adjust;
8082         new_stream->vrr_infopacket = vrr_infopacket;
8083
8084         if (new_crtc_state->freesync_vrr_info_changed)
8085                 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
8086                               new_crtc_state->base.crtc->base.id,
8087                               (int)new_crtc_state->base.vrr_enabled,
8088                               (int)vrr_params.state);
8089
8090         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8091 }
8092
8093 static void update_stream_irq_parameters(
8094         struct amdgpu_display_manager *dm,
8095         struct dm_crtc_state *new_crtc_state)
8096 {
8097         struct dc_stream_state *new_stream = new_crtc_state->stream;
8098         struct mod_vrr_params vrr_params;
8099         struct mod_freesync_config config = new_crtc_state->freesync_config;
8100         struct amdgpu_device *adev = dm->adev;
8101         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
8102         unsigned long flags;
8103
8104         if (!new_stream)
8105                 return;
8106
8107         /*
8108          * TODO: Determine why min/max totals and vrefresh can be 0 here.
8109          * For now it's sufficient to just guard against these conditions.
8110          */
8111         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
8112                 return;
8113
8114         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8115         vrr_params = acrtc->dm_irq_params.vrr_params;
8116
8117         if (new_crtc_state->vrr_supported &&
8118             config.min_refresh_in_uhz &&
8119             config.max_refresh_in_uhz) {
8120                 /*
8121                  * if freesync compatible mode was set, config.state will be set
8122                  * in atomic check
8123                  */
8124                 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz &&
8125                     (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) ||
8126                      new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) {
8127                         vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz;
8128                         vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz;
8129                         vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz;
8130                         vrr_params.state = VRR_STATE_ACTIVE_FIXED;
8131                 } else {
8132                         config.state = new_crtc_state->base.vrr_enabled ?
8133                                                      VRR_STATE_ACTIVE_VARIABLE :
8134                                                      VRR_STATE_INACTIVE;
8135                 }
8136         } else {
8137                 config.state = VRR_STATE_UNSUPPORTED;
8138         }
8139
8140         mod_freesync_build_vrr_params(dm->freesync_module,
8141                                       new_stream,
8142                                       &config, &vrr_params);
8143
8144         new_crtc_state->freesync_timing_changed |=
8145                 (memcmp(&acrtc->dm_irq_params.vrr_params.adjust,
8146                         &vrr_params.adjust, sizeof(vrr_params.adjust)) != 0);
8147
8148         new_crtc_state->freesync_config = config;
8149         /* Copy state for access from DM IRQ handler */
8150         acrtc->dm_irq_params.freesync_config = config;
8151         acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes;
8152         acrtc->dm_irq_params.vrr_params = vrr_params;
8153         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8154 }
8155
8156 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
8157                                             struct dm_crtc_state *new_state)
8158 {
8159         bool old_vrr_active = amdgpu_dm_vrr_active(old_state);
8160         bool new_vrr_active = amdgpu_dm_vrr_active(new_state);
8161
8162         if (!old_vrr_active && new_vrr_active) {
8163                 /* Transition VRR inactive -> active:
8164                  * While VRR is active, we must not disable vblank irq, as a
8165                  * reenable after disable would compute bogus vblank/pflip
8166                  * timestamps if it likely happened inside display front-porch.
8167                  *
8168                  * We also need vupdate irq for the actual core vblank handling
8169                  * at end of vblank.
8170                  */
8171                 dm_set_vupdate_irq(new_state->base.crtc, true);
8172                 drm_crtc_vblank_get(new_state->base.crtc);
8173                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
8174                                  __func__, new_state->base.crtc->base.id);
8175         } else if (old_vrr_active && !new_vrr_active) {
8176                 /* Transition VRR active -> inactive:
8177                  * Allow vblank irq disable again for fixed refresh rate.
8178                  */
8179                 dm_set_vupdate_irq(new_state->base.crtc, false);
8180                 drm_crtc_vblank_put(new_state->base.crtc);
8181                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
8182                                  __func__, new_state->base.crtc->base.id);
8183         }
8184 }
8185
8186 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
8187 {
8188         struct drm_plane *plane;
8189         struct drm_plane_state *old_plane_state;
8190         int i;
8191
8192         /*
8193          * TODO: Make this per-stream so we don't issue redundant updates for
8194          * commits with multiple streams.
8195          */
8196         for_each_old_plane_in_state(state, plane, old_plane_state, i)
8197                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
8198                         handle_cursor_update(plane, old_plane_state);
8199 }
8200
8201 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
8202                                     struct dc_state *dc_state,
8203                                     struct drm_device *dev,
8204                                     struct amdgpu_display_manager *dm,
8205                                     struct drm_crtc *pcrtc,
8206                                     bool wait_for_vblank)
8207 {
8208         uint32_t i;
8209         uint64_t timestamp_ns;
8210         struct drm_plane *plane;
8211         struct drm_plane_state *old_plane_state, *new_plane_state;
8212         struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
8213         struct drm_crtc_state *new_pcrtc_state =
8214                         drm_atomic_get_new_crtc_state(state, pcrtc);
8215         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
8216         struct dm_crtc_state *dm_old_crtc_state =
8217                         to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
8218         int planes_count = 0, vpos, hpos;
8219         long r;
8220         unsigned long flags;
8221         struct amdgpu_bo *abo;
8222         uint32_t target_vblank, last_flip_vblank;
8223         bool vrr_active = amdgpu_dm_vrr_active(acrtc_state);
8224         bool pflip_present = false;
8225         struct {
8226                 struct dc_surface_update surface_updates[MAX_SURFACES];
8227                 struct dc_plane_info plane_infos[MAX_SURFACES];
8228                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
8229                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
8230                 struct dc_stream_update stream_update;
8231         } *bundle;
8232
8233         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
8234
8235         if (!bundle) {
8236                 dm_error("Failed to allocate update bundle\n");
8237                 goto cleanup;
8238         }
8239
8240         /*
8241          * Disable the cursor first if we're disabling all the planes.
8242          * It'll remain on the screen after the planes are re-enabled
8243          * if we don't.
8244          */
8245         if (acrtc_state->active_planes == 0)
8246                 amdgpu_dm_commit_cursors(state);
8247
8248         /* update planes when needed */
8249         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
8250                 struct drm_crtc *crtc = new_plane_state->crtc;
8251                 struct drm_crtc_state *new_crtc_state;
8252                 struct drm_framebuffer *fb = new_plane_state->fb;
8253                 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb;
8254                 bool plane_needs_flip;
8255                 struct dc_plane_state *dc_plane;
8256                 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
8257
8258                 /* Cursor plane is handled after stream updates */
8259                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
8260                         continue;
8261
8262                 if (!fb || !crtc || pcrtc != crtc)
8263                         continue;
8264
8265                 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
8266                 if (!new_crtc_state->active)
8267                         continue;
8268
8269                 dc_plane = dm_new_plane_state->dc_state;
8270
8271                 bundle->surface_updates[planes_count].surface = dc_plane;
8272                 if (new_pcrtc_state->color_mgmt_changed) {
8273                         bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
8274                         bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
8275                         bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;
8276                 }
8277
8278                 fill_dc_scaling_info(new_plane_state,
8279                                      &bundle->scaling_infos[planes_count]);
8280
8281                 bundle->surface_updates[planes_count].scaling_info =
8282                         &bundle->scaling_infos[planes_count];
8283
8284                 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
8285
8286                 pflip_present = pflip_present || plane_needs_flip;
8287
8288                 if (!plane_needs_flip) {
8289                         planes_count += 1;
8290                         continue;
8291                 }
8292
8293                 abo = gem_to_amdgpu_bo(fb->obj[0]);
8294
8295                 /*
8296                  * Wait for all fences on this FB. Do limited wait to avoid
8297                  * deadlock during GPU reset when this fence will not signal
8298                  * but we hold reservation lock for the BO.
8299                  */
8300                 r = dma_resv_wait_timeout_rcu(abo->tbo.base.resv, true,
8301                                                         false,
8302                                                         msecs_to_jiffies(5000));
8303                 if (unlikely(r <= 0))
8304                         DRM_ERROR("Waiting for fences timed out!");
8305
8306                 fill_dc_plane_info_and_addr(
8307                         dm->adev, new_plane_state,
8308                         afb->tiling_flags,
8309                         &bundle->plane_infos[planes_count],
8310                         &bundle->flip_addrs[planes_count].address,
8311                         afb->tmz_surface, false);
8312
8313                 DRM_DEBUG_ATOMIC("plane: id=%d dcc_en=%d\n",
8314                                  new_plane_state->plane->index,
8315                                  bundle->plane_infos[planes_count].dcc.enable);
8316
8317                 bundle->surface_updates[planes_count].plane_info =
8318                         &bundle->plane_infos[planes_count];
8319
8320                 /*
8321                  * Only allow immediate flips for fast updates that don't
8322                  * change FB pitch, DCC state, rotation or mirroing.
8323                  */
8324                 bundle->flip_addrs[planes_count].flip_immediate =
8325                         crtc->state->async_flip &&
8326                         acrtc_state->update_type == UPDATE_TYPE_FAST;
8327
8328                 timestamp_ns = ktime_get_ns();
8329                 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
8330                 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
8331                 bundle->surface_updates[planes_count].surface = dc_plane;
8332
8333                 if (!bundle->surface_updates[planes_count].surface) {
8334                         DRM_ERROR("No surface for CRTC: id=%d\n",
8335                                         acrtc_attach->crtc_id);
8336                         continue;
8337                 }
8338
8339                 if (plane == pcrtc->primary)
8340                         update_freesync_state_on_stream(
8341                                 dm,
8342                                 acrtc_state,
8343                                 acrtc_state->stream,
8344                                 dc_plane,
8345                                 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
8346
8347                 DRM_DEBUG_ATOMIC("%s Flipping to hi: 0x%x, low: 0x%x\n",
8348                                  __func__,
8349                                  bundle->flip_addrs[planes_count].address.grph.addr.high_part,
8350                                  bundle->flip_addrs[planes_count].address.grph.addr.low_part);
8351
8352                 planes_count += 1;
8353
8354         }
8355
8356         if (pflip_present) {
8357                 if (!vrr_active) {
8358                         /* Use old throttling in non-vrr fixed refresh rate mode
8359                          * to keep flip scheduling based on target vblank counts
8360                          * working in a backwards compatible way, e.g., for
8361                          * clients using the GLX_OML_sync_control extension or
8362                          * DRI3/Present extension with defined target_msc.
8363                          */
8364                         last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);
8365                 }
8366                 else {
8367                         /* For variable refresh rate mode only:
8368                          * Get vblank of last completed flip to avoid > 1 vrr
8369                          * flips per video frame by use of throttling, but allow
8370                          * flip programming anywhere in the possibly large
8371                          * variable vrr vblank interval for fine-grained flip
8372                          * timing control and more opportunity to avoid stutter
8373                          * on late submission of flips.
8374                          */
8375                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8376                         last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank;
8377                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8378                 }
8379
8380                 target_vblank = last_flip_vblank + wait_for_vblank;
8381
8382                 /*
8383                  * Wait until we're out of the vertical blank period before the one
8384                  * targeted by the flip
8385                  */
8386                 while ((acrtc_attach->enabled &&
8387                         (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
8388                                                             0, &vpos, &hpos, NULL,
8389                                                             NULL, &pcrtc->hwmode)
8390                          & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
8391                         (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
8392                         (int)(target_vblank -
8393                           amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) {
8394                         usleep_range(1000, 1100);
8395                 }
8396
8397                 /**
8398                  * Prepare the flip event for the pageflip interrupt to handle.
8399                  *
8400                  * This only works in the case where we've already turned on the
8401                  * appropriate hardware blocks (eg. HUBP) so in the transition case
8402                  * from 0 -> n planes we have to skip a hardware generated event
8403                  * and rely on sending it from software.
8404                  */
8405                 if (acrtc_attach->base.state->event &&
8406                     acrtc_state->active_planes > 0) {
8407                         drm_crtc_vblank_get(pcrtc);
8408
8409                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8410
8411                         WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
8412                         prepare_flip_isr(acrtc_attach);
8413
8414                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8415                 }
8416
8417                 if (acrtc_state->stream) {
8418                         if (acrtc_state->freesync_vrr_info_changed)
8419                                 bundle->stream_update.vrr_infopacket =
8420                                         &acrtc_state->stream->vrr_infopacket;
8421                 }
8422         }
8423
8424         /* Update the planes if changed or disable if we don't have any. */
8425         if ((planes_count || acrtc_state->active_planes == 0) &&
8426                 acrtc_state->stream) {
8427                 bundle->stream_update.stream = acrtc_state->stream;
8428                 if (new_pcrtc_state->mode_changed) {
8429                         bundle->stream_update.src = acrtc_state->stream->src;
8430                         bundle->stream_update.dst = acrtc_state->stream->dst;
8431                 }
8432
8433                 if (new_pcrtc_state->color_mgmt_changed) {
8434                         /*
8435                          * TODO: This isn't fully correct since we've actually
8436                          * already modified the stream in place.
8437                          */
8438                         bundle->stream_update.gamut_remap =
8439                                 &acrtc_state->stream->gamut_remap_matrix;
8440                         bundle->stream_update.output_csc_transform =
8441                                 &acrtc_state->stream->csc_color_matrix;
8442                         bundle->stream_update.out_transfer_func =
8443                                 acrtc_state->stream->out_transfer_func;
8444                 }
8445
8446                 acrtc_state->stream->abm_level = acrtc_state->abm_level;
8447                 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
8448                         bundle->stream_update.abm_level = &acrtc_state->abm_level;
8449
8450                 /*
8451                  * If FreeSync state on the stream has changed then we need to
8452                  * re-adjust the min/max bounds now that DC doesn't handle this
8453                  * as part of commit.
8454                  */
8455                 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) {
8456                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8457                         dc_stream_adjust_vmin_vmax(
8458                                 dm->dc, acrtc_state->stream,
8459                                 &acrtc_attach->dm_irq_params.vrr_params.adjust);
8460                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8461                 }
8462                 mutex_lock(&dm->dc_lock);
8463                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8464                                 acrtc_state->stream->link->psr_settings.psr_allow_active)
8465                         amdgpu_dm_psr_disable(acrtc_state->stream);
8466
8467                 dc_commit_updates_for_stream(dm->dc,
8468                                                      bundle->surface_updates,
8469                                                      planes_count,
8470                                                      acrtc_state->stream,
8471                                                      &bundle->stream_update,
8472                                                      dc_state);
8473
8474                 /**
8475                  * Enable or disable the interrupts on the backend.
8476                  *
8477                  * Most pipes are put into power gating when unused.
8478                  *
8479                  * When power gating is enabled on a pipe we lose the
8480                  * interrupt enablement state when power gating is disabled.
8481                  *
8482                  * So we need to update the IRQ control state in hardware
8483                  * whenever the pipe turns on (since it could be previously
8484                  * power gated) or off (since some pipes can't be power gated
8485                  * on some ASICs).
8486                  */
8487                 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes)
8488                         dm_update_pflip_irq_state(drm_to_adev(dev),
8489                                                   acrtc_attach);
8490
8491                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8492                                 acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
8493                                 !acrtc_state->stream->link->psr_settings.psr_feature_enabled)
8494                         amdgpu_dm_link_setup_psr(acrtc_state->stream);
8495                 else if ((acrtc_state->update_type == UPDATE_TYPE_FAST) &&
8496                                 acrtc_state->stream->link->psr_settings.psr_feature_enabled &&
8497                                 !acrtc_state->stream->link->psr_settings.psr_allow_active) {
8498                         amdgpu_dm_psr_enable(acrtc_state->stream);
8499                 }
8500
8501                 mutex_unlock(&dm->dc_lock);
8502         }
8503
8504         /*
8505          * Update cursor state *after* programming all the planes.
8506          * This avoids redundant programming in the case where we're going
8507          * to be disabling a single plane - those pipes are being disabled.
8508          */
8509         if (acrtc_state->active_planes)
8510                 amdgpu_dm_commit_cursors(state);
8511
8512 cleanup:
8513         kfree(bundle);
8514 }
8515
8516 static void amdgpu_dm_commit_audio(struct drm_device *dev,
8517                                    struct drm_atomic_state *state)
8518 {
8519         struct amdgpu_device *adev = drm_to_adev(dev);
8520         struct amdgpu_dm_connector *aconnector;
8521         struct drm_connector *connector;
8522         struct drm_connector_state *old_con_state, *new_con_state;
8523         struct drm_crtc_state *new_crtc_state;
8524         struct dm_crtc_state *new_dm_crtc_state;
8525         const struct dc_stream_status *status;
8526         int i, inst;
8527
8528         /* Notify device removals. */
8529         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8530                 if (old_con_state->crtc != new_con_state->crtc) {
8531                         /* CRTC changes require notification. */
8532                         goto notify;
8533                 }
8534
8535                 if (!new_con_state->crtc)
8536                         continue;
8537
8538                 new_crtc_state = drm_atomic_get_new_crtc_state(
8539                         state, new_con_state->crtc);
8540
8541                 if (!new_crtc_state)
8542                         continue;
8543
8544                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8545                         continue;
8546
8547         notify:
8548                 aconnector = to_amdgpu_dm_connector(connector);
8549
8550                 mutex_lock(&adev->dm.audio_lock);
8551                 inst = aconnector->audio_inst;
8552                 aconnector->audio_inst = -1;
8553                 mutex_unlock(&adev->dm.audio_lock);
8554
8555                 amdgpu_dm_audio_eld_notify(adev, inst);
8556         }
8557
8558         /* Notify audio device additions. */
8559         for_each_new_connector_in_state(state, connector, new_con_state, i) {
8560                 if (!new_con_state->crtc)
8561                         continue;
8562
8563                 new_crtc_state = drm_atomic_get_new_crtc_state(
8564                         state, new_con_state->crtc);
8565
8566                 if (!new_crtc_state)
8567                         continue;
8568
8569                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8570                         continue;
8571
8572                 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
8573                 if (!new_dm_crtc_state->stream)
8574                         continue;
8575
8576                 status = dc_stream_get_status(new_dm_crtc_state->stream);
8577                 if (!status)
8578                         continue;
8579
8580                 aconnector = to_amdgpu_dm_connector(connector);
8581
8582                 mutex_lock(&adev->dm.audio_lock);
8583                 inst = status->audio_inst;
8584                 aconnector->audio_inst = inst;
8585                 mutex_unlock(&adev->dm.audio_lock);
8586
8587                 amdgpu_dm_audio_eld_notify(adev, inst);
8588         }
8589 }
8590
8591 /*
8592  * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
8593  * @crtc_state: the DRM CRTC state
8594  * @stream_state: the DC stream state.
8595  *
8596  * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
8597  * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
8598  */
8599 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
8600                                                 struct dc_stream_state *stream_state)
8601 {
8602         stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
8603 }
8604
8605 /**
8606  * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
8607  * @state: The atomic state to commit
8608  *
8609  * This will tell DC to commit the constructed DC state from atomic_check,
8610  * programming the hardware. Any failures here implies a hardware failure, since
8611  * atomic check should have filtered anything non-kosher.
8612  */
8613 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
8614 {
8615         struct drm_device *dev = state->dev;
8616         struct amdgpu_device *adev = drm_to_adev(dev);
8617         struct amdgpu_display_manager *dm = &adev->dm;
8618         struct dm_atomic_state *dm_state;
8619         struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
8620         uint32_t i, j;
8621         struct drm_crtc *crtc;
8622         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8623         unsigned long flags;
8624         bool wait_for_vblank = true;
8625         struct drm_connector *connector;
8626         struct drm_connector_state *old_con_state, *new_con_state;
8627         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8628         int crtc_disable_count = 0;
8629         bool mode_set_reset_required = false;
8630
8631         trace_amdgpu_dm_atomic_commit_tail_begin(state);
8632
8633         drm_atomic_helper_update_legacy_modeset_state(dev, state);
8634
8635         dm_state = dm_atomic_get_new_state(state);
8636         if (dm_state && dm_state->context) {
8637                 dc_state = dm_state->context;
8638         } else {
8639                 /* No state changes, retain current state. */
8640                 dc_state_temp = dc_create_state(dm->dc);
8641                 ASSERT(dc_state_temp);
8642                 dc_state = dc_state_temp;
8643                 dc_resource_state_copy_construct_current(dm->dc, dc_state);
8644         }
8645
8646         for_each_oldnew_crtc_in_state (state, crtc, old_crtc_state,
8647                                        new_crtc_state, i) {
8648                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8649
8650                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8651
8652                 if (old_crtc_state->active &&
8653                     (!new_crtc_state->active ||
8654                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8655                         manage_dm_interrupts(adev, acrtc, false);
8656                         dc_stream_release(dm_old_crtc_state->stream);
8657                 }
8658         }
8659
8660         drm_atomic_helper_calc_timestamping_constants(state);
8661
8662         /* update changed items */
8663         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8664                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8665
8666                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8667                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8668
8669                 DRM_DEBUG_ATOMIC(
8670                         "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
8671                         "planes_changed:%d, mode_changed:%d,active_changed:%d,"
8672                         "connectors_changed:%d\n",
8673                         acrtc->crtc_id,
8674                         new_crtc_state->enable,
8675                         new_crtc_state->active,
8676                         new_crtc_state->planes_changed,
8677                         new_crtc_state->mode_changed,
8678                         new_crtc_state->active_changed,
8679                         new_crtc_state->connectors_changed);
8680
8681                 /* Disable cursor if disabling crtc */
8682                 if (old_crtc_state->active && !new_crtc_state->active) {
8683                         struct dc_cursor_position position;
8684
8685                         memset(&position, 0, sizeof(position));
8686                         mutex_lock(&dm->dc_lock);
8687                         dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position);
8688                         mutex_unlock(&dm->dc_lock);
8689                 }
8690
8691                 /* Copy all transient state flags into dc state */
8692                 if (dm_new_crtc_state->stream) {
8693                         amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
8694                                                             dm_new_crtc_state->stream);
8695                 }
8696
8697                 /* handles headless hotplug case, updating new_state and
8698                  * aconnector as needed
8699                  */
8700
8701                 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
8702
8703                         DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
8704
8705                         if (!dm_new_crtc_state->stream) {
8706                                 /*
8707                                  * this could happen because of issues with
8708                                  * userspace notifications delivery.
8709                                  * In this case userspace tries to set mode on
8710                                  * display which is disconnected in fact.
8711                                  * dc_sink is NULL in this case on aconnector.
8712                                  * We expect reset mode will come soon.
8713                                  *
8714                                  * This can also happen when unplug is done
8715                                  * during resume sequence ended
8716                                  *
8717                                  * In this case, we want to pretend we still
8718                                  * have a sink to keep the pipe running so that
8719                                  * hw state is consistent with the sw state
8720                                  */
8721                                 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
8722                                                 __func__, acrtc->base.base.id);
8723                                 continue;
8724                         }
8725
8726                         if (dm_old_crtc_state->stream)
8727                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8728
8729                         pm_runtime_get_noresume(dev->dev);
8730
8731                         acrtc->enabled = true;
8732                         acrtc->hw_mode = new_crtc_state->mode;
8733                         crtc->hwmode = new_crtc_state->mode;
8734                         mode_set_reset_required = true;
8735                 } else if (modereset_required(new_crtc_state)) {
8736                         DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
8737                         /* i.e. reset mode */
8738                         if (dm_old_crtc_state->stream)
8739                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8740
8741                         mode_set_reset_required = true;
8742                 }
8743         } /* for_each_crtc_in_state() */
8744
8745         if (dc_state) {
8746                 /* if there mode set or reset, disable eDP PSR */
8747                 if (mode_set_reset_required)
8748                         amdgpu_dm_psr_disable_all(dm);
8749
8750                 dm_enable_per_frame_crtc_master_sync(dc_state);
8751                 mutex_lock(&dm->dc_lock);
8752                 WARN_ON(!dc_commit_state(dm->dc, dc_state));
8753 #if defined(CONFIG_DRM_AMD_DC_DCN)
8754                /* Allow idle optimization when vblank count is 0 for display off */
8755                if (dm->active_vblank_irq_count == 0)
8756                    dc_allow_idle_optimizations(dm->dc,true);
8757 #endif
8758                 mutex_unlock(&dm->dc_lock);
8759         }
8760
8761         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8762                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8763
8764                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8765
8766                 if (dm_new_crtc_state->stream != NULL) {
8767                         const struct dc_stream_status *status =
8768                                         dc_stream_get_status(dm_new_crtc_state->stream);
8769
8770                         if (!status)
8771                                 status = dc_stream_get_status_from_state(dc_state,
8772                                                                          dm_new_crtc_state->stream);
8773                         if (!status)
8774                                 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
8775                         else
8776                                 acrtc->otg_inst = status->primary_otg_inst;
8777                 }
8778         }
8779 #ifdef CONFIG_DRM_AMD_DC_HDCP
8780         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8781                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8782                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8783                 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8784
8785                 new_crtc_state = NULL;
8786
8787                 if (acrtc)
8788                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8789
8790                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8791
8792                 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
8793                     connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
8794                         hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
8795                         new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
8796                         dm_new_con_state->update_hdcp = true;
8797                         continue;
8798                 }
8799
8800                 if (is_content_protection_different(new_con_state, old_con_state, connector, adev->dm.hdcp_workqueue))
8801                         hdcp_update_display(
8802                                 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
8803                                 new_con_state->hdcp_content_type,
8804                                 new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED);
8805         }
8806 #endif
8807
8808         /* Handle connector state changes */
8809         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8810                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8811                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
8812                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8813                 struct dc_surface_update dummy_updates[MAX_SURFACES];
8814                 struct dc_stream_update stream_update;
8815                 struct dc_info_packet hdr_packet;
8816                 struct dc_stream_status *status = NULL;
8817                 bool abm_changed, hdr_changed, scaling_changed;
8818
8819                 memset(&dummy_updates, 0, sizeof(dummy_updates));
8820                 memset(&stream_update, 0, sizeof(stream_update));
8821
8822                 if (acrtc) {
8823                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8824                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8825                 }
8826
8827                 /* Skip any modesets/resets */
8828                 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
8829                         continue;
8830
8831                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8832                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8833
8834                 scaling_changed = is_scaling_state_different(dm_new_con_state,
8835                                                              dm_old_con_state);
8836
8837                 abm_changed = dm_new_crtc_state->abm_level !=
8838                               dm_old_crtc_state->abm_level;
8839
8840                 hdr_changed =
8841                         is_hdr_metadata_different(old_con_state, new_con_state);
8842
8843                 if (!scaling_changed && !abm_changed && !hdr_changed)
8844                         continue;
8845
8846                 stream_update.stream = dm_new_crtc_state->stream;
8847                 if (scaling_changed) {
8848                         update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
8849                                         dm_new_con_state, dm_new_crtc_state->stream);
8850
8851                         stream_update.src = dm_new_crtc_state->stream->src;
8852                         stream_update.dst = dm_new_crtc_state->stream->dst;
8853                 }
8854
8855                 if (abm_changed) {
8856                         dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
8857
8858                         stream_update.abm_level = &dm_new_crtc_state->abm_level;
8859                 }
8860
8861                 if (hdr_changed) {
8862                         fill_hdr_info_packet(new_con_state, &hdr_packet);
8863                         stream_update.hdr_static_metadata = &hdr_packet;
8864                 }
8865
8866                 status = dc_stream_get_status(dm_new_crtc_state->stream);
8867                 WARN_ON(!status);
8868                 WARN_ON(!status->plane_count);
8869
8870                 /*
8871                  * TODO: DC refuses to perform stream updates without a dc_surface_update.
8872                  * Here we create an empty update on each plane.
8873                  * To fix this, DC should permit updating only stream properties.
8874                  */
8875                 for (j = 0; j < status->plane_count; j++)
8876                         dummy_updates[j].surface = status->plane_states[0];
8877
8878
8879                 mutex_lock(&dm->dc_lock);
8880                 dc_commit_updates_for_stream(dm->dc,
8881                                                      dummy_updates,
8882                                                      status->plane_count,
8883                                                      dm_new_crtc_state->stream,
8884                                                      &stream_update,
8885                                                      dc_state);
8886                 mutex_unlock(&dm->dc_lock);
8887         }
8888
8889         /* Count number of newly disabled CRTCs for dropping PM refs later. */
8890         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
8891                                       new_crtc_state, i) {
8892                 if (old_crtc_state->active && !new_crtc_state->active)
8893                         crtc_disable_count++;
8894
8895                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8896                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8897
8898                 /* For freesync config update on crtc state and params for irq */
8899                 update_stream_irq_parameters(dm, dm_new_crtc_state);
8900
8901                 /* Handle vrr on->off / off->on transitions */
8902                 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state,
8903                                                 dm_new_crtc_state);
8904         }
8905
8906         /**
8907          * Enable interrupts for CRTCs that are newly enabled or went through
8908          * a modeset. It was intentionally deferred until after the front end
8909          * state was modified to wait until the OTG was on and so the IRQ
8910          * handlers didn't access stale or invalid state.
8911          */
8912         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8913                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8914 #ifdef CONFIG_DEBUG_FS
8915                 bool configure_crc = false;
8916                 enum amdgpu_dm_pipe_crc_source cur_crc_src;
8917 #endif
8918                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8919
8920                 if (new_crtc_state->active &&
8921                     (!old_crtc_state->active ||
8922                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8923                         dc_stream_retain(dm_new_crtc_state->stream);
8924                         acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
8925                         manage_dm_interrupts(adev, acrtc, true);
8926
8927 #ifdef CONFIG_DEBUG_FS
8928                         /**
8929                          * Frontend may have changed so reapply the CRC capture
8930                          * settings for the stream.
8931                          */
8932                         dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8933                         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8934                         cur_crc_src = acrtc->dm_irq_params.crc_src;
8935                         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8936
8937                         if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
8938                                 configure_crc = true;
8939 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
8940                                 if (amdgpu_dm_crc_window_is_activated(crtc))
8941                                         configure_crc = false;
8942 #endif
8943                         }
8944
8945                         if (configure_crc)
8946                                 amdgpu_dm_crtc_configure_crc_source(
8947                                         crtc, dm_new_crtc_state, cur_crc_src);
8948 #endif
8949                 }
8950         }
8951
8952         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
8953                 if (new_crtc_state->async_flip)
8954                         wait_for_vblank = false;
8955
8956         /* update planes when needed per crtc*/
8957         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
8958                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8959
8960                 if (dm_new_crtc_state->stream)
8961                         amdgpu_dm_commit_planes(state, dc_state, dev,
8962                                                 dm, crtc, wait_for_vblank);
8963         }
8964
8965         /* Update audio instances for each connector. */
8966         amdgpu_dm_commit_audio(dev, state);
8967
8968         /*
8969          * send vblank event on all events not handled in flip and
8970          * mark consumed event for drm_atomic_helper_commit_hw_done
8971          */
8972         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8973         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8974
8975                 if (new_crtc_state->event)
8976                         drm_send_event_locked(dev, &new_crtc_state->event->base);
8977
8978                 new_crtc_state->event = NULL;
8979         }
8980         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8981
8982         /* Signal HW programming completion */
8983         drm_atomic_helper_commit_hw_done(state);
8984
8985         if (wait_for_vblank)
8986                 drm_atomic_helper_wait_for_flip_done(dev, state);
8987
8988         drm_atomic_helper_cleanup_planes(dev, state);
8989
8990         /* return the stolen vga memory back to VRAM */
8991         if (!adev->mman.keep_stolen_vga_memory)
8992                 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
8993         amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
8994
8995         /*
8996          * Finally, drop a runtime PM reference for each newly disabled CRTC,
8997          * so we can put the GPU into runtime suspend if we're not driving any
8998          * displays anymore
8999          */
9000         for (i = 0; i < crtc_disable_count; i++)
9001                 pm_runtime_put_autosuspend(dev->dev);
9002         pm_runtime_mark_last_busy(dev->dev);
9003
9004         if (dc_state_temp)
9005                 dc_release_state(dc_state_temp);
9006 }
9007
9008
9009 static int dm_force_atomic_commit(struct drm_connector *connector)
9010 {
9011         int ret = 0;
9012         struct drm_device *ddev = connector->dev;
9013         struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
9014         struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
9015         struct drm_plane *plane = disconnected_acrtc->base.primary;
9016         struct drm_connector_state *conn_state;
9017         struct drm_crtc_state *crtc_state;
9018         struct drm_plane_state *plane_state;
9019
9020         if (!state)
9021                 return -ENOMEM;
9022
9023         state->acquire_ctx = ddev->mode_config.acquire_ctx;
9024
9025         /* Construct an atomic state to restore previous display setting */
9026
9027         /*
9028          * Attach connectors to drm_atomic_state
9029          */
9030         conn_state = drm_atomic_get_connector_state(state, connector);
9031
9032         ret = PTR_ERR_OR_ZERO(conn_state);
9033         if (ret)
9034                 goto out;
9035
9036         /* Attach crtc to drm_atomic_state*/
9037         crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
9038
9039         ret = PTR_ERR_OR_ZERO(crtc_state);
9040         if (ret)
9041                 goto out;
9042
9043         /* force a restore */
9044         crtc_state->mode_changed = true;
9045
9046         /* Attach plane to drm_atomic_state */
9047         plane_state = drm_atomic_get_plane_state(state, plane);
9048
9049         ret = PTR_ERR_OR_ZERO(plane_state);
9050         if (ret)
9051                 goto out;
9052
9053         /* Call commit internally with the state we just constructed */
9054         ret = drm_atomic_commit(state);
9055
9056 out:
9057         drm_atomic_state_put(state);
9058         if (ret)
9059                 DRM_ERROR("Restoring old state failed with %i\n", ret);
9060
9061         return ret;
9062 }
9063
9064 /*
9065  * This function handles all cases when set mode does not come upon hotplug.
9066  * This includes when a display is unplugged then plugged back into the
9067  * same port and when running without usermode desktop manager supprot
9068  */
9069 void dm_restore_drm_connector_state(struct drm_device *dev,
9070                                     struct drm_connector *connector)
9071 {
9072         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
9073         struct amdgpu_crtc *disconnected_acrtc;
9074         struct dm_crtc_state *acrtc_state;
9075
9076         if (!aconnector->dc_sink || !connector->state || !connector->encoder)
9077                 return;
9078
9079         disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
9080         if (!disconnected_acrtc)
9081                 return;
9082
9083         acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
9084         if (!acrtc_state->stream)
9085                 return;
9086
9087         /*
9088          * If the previous sink is not released and different from the current,
9089          * we deduce we are in a state where we can not rely on usermode call
9090          * to turn on the display, so we do it here
9091          */
9092         if (acrtc_state->stream->sink != aconnector->dc_sink)
9093                 dm_force_atomic_commit(&aconnector->base);
9094 }
9095
9096 /*
9097  * Grabs all modesetting locks to serialize against any blocking commits,
9098  * Waits for completion of all non blocking commits.
9099  */
9100 static int do_aquire_global_lock(struct drm_device *dev,
9101                                  struct drm_atomic_state *state)
9102 {
9103         struct drm_crtc *crtc;
9104         struct drm_crtc_commit *commit;
9105         long ret;
9106
9107         /*
9108          * Adding all modeset locks to aquire_ctx will
9109          * ensure that when the framework release it the
9110          * extra locks we are locking here will get released to
9111          */
9112         ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
9113         if (ret)
9114                 return ret;
9115
9116         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9117                 spin_lock(&crtc->commit_lock);
9118                 commit = list_first_entry_or_null(&crtc->commit_list,
9119                                 struct drm_crtc_commit, commit_entry);
9120                 if (commit)
9121                         drm_crtc_commit_get(commit);
9122                 spin_unlock(&crtc->commit_lock);
9123
9124                 if (!commit)
9125                         continue;
9126
9127                 /*
9128                  * Make sure all pending HW programming completed and
9129                  * page flips done
9130                  */
9131                 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
9132
9133                 if (ret > 0)
9134                         ret = wait_for_completion_interruptible_timeout(
9135                                         &commit->flip_done, 10*HZ);
9136
9137                 if (ret == 0)
9138                         DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
9139                                   "timed out\n", crtc->base.id, crtc->name);
9140
9141                 drm_crtc_commit_put(commit);
9142         }
9143
9144         return ret < 0 ? ret : 0;
9145 }
9146
9147 static void get_freesync_config_for_crtc(
9148         struct dm_crtc_state *new_crtc_state,
9149         struct dm_connector_state *new_con_state)
9150 {
9151         struct mod_freesync_config config = {0};
9152         struct amdgpu_dm_connector *aconnector =
9153                         to_amdgpu_dm_connector(new_con_state->base.connector);
9154         struct drm_display_mode *mode = &new_crtc_state->base.mode;
9155         int vrefresh = drm_mode_vrefresh(mode);
9156         bool fs_vid_mode = false;
9157
9158         new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
9159                                         vrefresh >= aconnector->min_vfreq &&
9160                                         vrefresh <= aconnector->max_vfreq;
9161
9162         if (new_crtc_state->vrr_supported) {
9163                 new_crtc_state->stream->ignore_msa_timing_param = true;
9164                 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
9165
9166                 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000;
9167                 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000;
9168                 config.vsif_supported = true;
9169                 config.btr = true;
9170
9171                 if (fs_vid_mode) {
9172                         config.state = VRR_STATE_ACTIVE_FIXED;
9173                         config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz;
9174                         goto out;
9175                 } else if (new_crtc_state->base.vrr_enabled) {
9176                         config.state = VRR_STATE_ACTIVE_VARIABLE;
9177                 } else {
9178                         config.state = VRR_STATE_INACTIVE;
9179                 }
9180         }
9181 out:
9182         new_crtc_state->freesync_config = config;
9183 }
9184
9185 static void reset_freesync_config_for_crtc(
9186         struct dm_crtc_state *new_crtc_state)
9187 {
9188         new_crtc_state->vrr_supported = false;
9189
9190         memset(&new_crtc_state->vrr_infopacket, 0,
9191                sizeof(new_crtc_state->vrr_infopacket));
9192 }
9193
9194 static bool
9195 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
9196                                  struct drm_crtc_state *new_crtc_state)
9197 {
9198         struct drm_display_mode old_mode, new_mode;
9199
9200         if (!old_crtc_state || !new_crtc_state)
9201                 return false;
9202
9203         old_mode = old_crtc_state->mode;
9204         new_mode = new_crtc_state->mode;
9205
9206         if (old_mode.clock       == new_mode.clock &&
9207             old_mode.hdisplay    == new_mode.hdisplay &&
9208             old_mode.vdisplay    == new_mode.vdisplay &&
9209             old_mode.htotal      == new_mode.htotal &&
9210             old_mode.vtotal      != new_mode.vtotal &&
9211             old_mode.hsync_start == new_mode.hsync_start &&
9212             old_mode.vsync_start != new_mode.vsync_start &&
9213             old_mode.hsync_end   == new_mode.hsync_end &&
9214             old_mode.vsync_end   != new_mode.vsync_end &&
9215             old_mode.hskew       == new_mode.hskew &&
9216             old_mode.vscan       == new_mode.vscan &&
9217             (old_mode.vsync_end - old_mode.vsync_start) ==
9218             (new_mode.vsync_end - new_mode.vsync_start))
9219                 return true;
9220
9221         return false;
9222 }
9223
9224 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) {
9225         uint64_t num, den, res;
9226         struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
9227
9228         dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;
9229
9230         num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000;
9231         den = (unsigned long long)new_crtc_state->mode.htotal *
9232               (unsigned long long)new_crtc_state->mode.vtotal;
9233
9234         res = div_u64(num, den);
9235         dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
9236 }
9237
9238 static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
9239                                 struct drm_atomic_state *state,
9240                                 struct drm_crtc *crtc,
9241                                 struct drm_crtc_state *old_crtc_state,
9242                                 struct drm_crtc_state *new_crtc_state,
9243                                 bool enable,
9244                                 bool *lock_and_validation_needed)
9245 {
9246         struct dm_atomic_state *dm_state = NULL;
9247         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9248         struct dc_stream_state *new_stream;
9249         int ret = 0;
9250
9251         /*
9252          * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
9253          * update changed items
9254          */
9255         struct amdgpu_crtc *acrtc = NULL;
9256         struct amdgpu_dm_connector *aconnector = NULL;
9257         struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
9258         struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
9259
9260         new_stream = NULL;
9261
9262         dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9263         dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9264         acrtc = to_amdgpu_crtc(crtc);
9265         aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
9266
9267         /* TODO This hack should go away */
9268         if (aconnector && enable) {
9269                 /* Make sure fake sink is created in plug-in scenario */
9270                 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
9271                                                             &aconnector->base);
9272                 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
9273                                                             &aconnector->base);
9274
9275                 if (IS_ERR(drm_new_conn_state)) {
9276                         ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
9277                         goto fail;
9278                 }
9279
9280                 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
9281                 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
9282
9283                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9284                         goto skip_modeset;
9285
9286                 new_stream = create_validate_stream_for_sink(aconnector,
9287                                                              &new_crtc_state->mode,
9288                                                              dm_new_conn_state,
9289                                                              dm_old_crtc_state->stream);
9290
9291                 /*
9292                  * we can have no stream on ACTION_SET if a display
9293                  * was disconnected during S3, in this case it is not an
9294                  * error, the OS will be updated after detection, and
9295                  * will do the right thing on next atomic commit
9296                  */
9297
9298                 if (!new_stream) {
9299                         DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
9300                                         __func__, acrtc->base.base.id);
9301                         ret = -ENOMEM;
9302                         goto fail;
9303                 }
9304
9305                 /*
9306                  * TODO: Check VSDB bits to decide whether this should
9307                  * be enabled or not.
9308                  */
9309                 new_stream->triggered_crtc_reset.enabled =
9310                         dm->force_timing_sync;
9311
9312                 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9313
9314                 ret = fill_hdr_info_packet(drm_new_conn_state,
9315                                            &new_stream->hdr_static_metadata);
9316                 if (ret)
9317                         goto fail;
9318
9319                 /*
9320                  * If we already removed the old stream from the context
9321                  * (and set the new stream to NULL) then we can't reuse
9322                  * the old stream even if the stream and scaling are unchanged.
9323                  * We'll hit the BUG_ON and black screen.
9324                  *
9325                  * TODO: Refactor this function to allow this check to work
9326                  * in all conditions.
9327                  */
9328                 if (amdgpu_freesync_vid_mode &&
9329                     dm_new_crtc_state->stream &&
9330                     is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))
9331                         goto skip_modeset;
9332
9333                 if (dm_new_crtc_state->stream &&
9334                     dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9335                     dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
9336                         new_crtc_state->mode_changed = false;
9337                         DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
9338                                          new_crtc_state->mode_changed);
9339                 }
9340         }
9341
9342         /* mode_changed flag may get updated above, need to check again */
9343         if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9344                 goto skip_modeset;
9345
9346         DRM_DEBUG_ATOMIC(
9347                 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
9348                 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
9349                 "connectors_changed:%d\n",
9350                 acrtc->crtc_id,
9351                 new_crtc_state->enable,
9352                 new_crtc_state->active,
9353                 new_crtc_state->planes_changed,
9354                 new_crtc_state->mode_changed,
9355                 new_crtc_state->active_changed,
9356                 new_crtc_state->connectors_changed);
9357
9358         /* Remove stream for any changed/disabled CRTC */
9359         if (!enable) {
9360
9361                 if (!dm_old_crtc_state->stream)
9362                         goto skip_modeset;
9363
9364                 if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream &&
9365                     is_timing_unchanged_for_freesync(new_crtc_state,
9366                                                      old_crtc_state)) {
9367                         new_crtc_state->mode_changed = false;
9368                         DRM_DEBUG_DRIVER(
9369                                 "Mode change not required for front porch change, "
9370                                 "setting mode_changed to %d",
9371                                 new_crtc_state->mode_changed);
9372
9373                         set_freesync_fixed_config(dm_new_crtc_state);
9374
9375                         goto skip_modeset;
9376                 } else if (amdgpu_freesync_vid_mode && aconnector &&
9377                            is_freesync_video_mode(&new_crtc_state->mode,
9378                                                   aconnector)) {
9379                         set_freesync_fixed_config(dm_new_crtc_state);
9380                 }
9381
9382                 ret = dm_atomic_get_state(state, &dm_state);
9383                 if (ret)
9384                         goto fail;
9385
9386                 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
9387                                 crtc->base.id);
9388
9389                 /* i.e. reset mode */
9390                 if (dc_remove_stream_from_ctx(
9391                                 dm->dc,
9392                                 dm_state->context,
9393                                 dm_old_crtc_state->stream) != DC_OK) {
9394                         ret = -EINVAL;
9395                         goto fail;
9396                 }
9397
9398                 dc_stream_release(dm_old_crtc_state->stream);
9399                 dm_new_crtc_state->stream = NULL;
9400
9401                 reset_freesync_config_for_crtc(dm_new_crtc_state);
9402
9403                 *lock_and_validation_needed = true;
9404
9405         } else {/* Add stream for any updated/enabled CRTC */
9406                 /*
9407                  * Quick fix to prevent NULL pointer on new_stream when
9408                  * added MST connectors not found in existing crtc_state in the chained mode
9409                  * TODO: need to dig out the root cause of that
9410                  */
9411                 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
9412                         goto skip_modeset;
9413
9414                 if (modereset_required(new_crtc_state))
9415                         goto skip_modeset;
9416
9417                 if (modeset_required(new_crtc_state, new_stream,
9418                                      dm_old_crtc_state->stream)) {
9419
9420                         WARN_ON(dm_new_crtc_state->stream);
9421
9422                         ret = dm_atomic_get_state(state, &dm_state);
9423                         if (ret)
9424                                 goto fail;
9425
9426                         dm_new_crtc_state->stream = new_stream;
9427
9428                         dc_stream_retain(new_stream);
9429
9430                         DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n",
9431                                          crtc->base.id);
9432
9433                         if (dc_add_stream_to_ctx(
9434                                         dm->dc,
9435                                         dm_state->context,
9436                                         dm_new_crtc_state->stream) != DC_OK) {
9437                                 ret = -EINVAL;
9438                                 goto fail;
9439                         }
9440
9441                         *lock_and_validation_needed = true;
9442                 }
9443         }
9444
9445 skip_modeset:
9446         /* Release extra reference */
9447         if (new_stream)
9448                  dc_stream_release(new_stream);
9449
9450         /*
9451          * We want to do dc stream updates that do not require a
9452          * full modeset below.
9453          */
9454         if (!(enable && aconnector && new_crtc_state->active))
9455                 return 0;
9456         /*
9457          * Given above conditions, the dc state cannot be NULL because:
9458          * 1. We're in the process of enabling CRTCs (just been added
9459          *    to the dc context, or already is on the context)
9460          * 2. Has a valid connector attached, and
9461          * 3. Is currently active and enabled.
9462          * => The dc stream state currently exists.
9463          */
9464         BUG_ON(dm_new_crtc_state->stream == NULL);
9465
9466         /* Scaling or underscan settings */
9467         if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state))
9468                 update_stream_scaling_settings(
9469                         &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
9470
9471         /* ABM settings */
9472         dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9473
9474         /*
9475          * Color management settings. We also update color properties
9476          * when a modeset is needed, to ensure it gets reprogrammed.
9477          */
9478         if (dm_new_crtc_state->base.color_mgmt_changed ||
9479             drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9480                 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
9481                 if (ret)
9482                         goto fail;
9483         }
9484
9485         /* Update Freesync settings. */
9486         get_freesync_config_for_crtc(dm_new_crtc_state,
9487                                      dm_new_conn_state);
9488
9489         return ret;
9490
9491 fail:
9492         if (new_stream)
9493                 dc_stream_release(new_stream);
9494         return ret;
9495 }
9496
9497 static bool should_reset_plane(struct drm_atomic_state *state,
9498                                struct drm_plane *plane,
9499                                struct drm_plane_state *old_plane_state,
9500                                struct drm_plane_state *new_plane_state)
9501 {
9502         struct drm_plane *other;
9503         struct drm_plane_state *old_other_state, *new_other_state;
9504         struct drm_crtc_state *new_crtc_state;
9505         int i;
9506
9507         /*
9508          * TODO: Remove this hack once the checks below are sufficient
9509          * enough to determine when we need to reset all the planes on
9510          * the stream.
9511          */
9512         if (state->allow_modeset)
9513                 return true;
9514
9515         /* Exit early if we know that we're adding or removing the plane. */
9516         if (old_plane_state->crtc != new_plane_state->crtc)
9517                 return true;
9518
9519         /* old crtc == new_crtc == NULL, plane not in context. */
9520         if (!new_plane_state->crtc)
9521                 return false;
9522
9523         new_crtc_state =
9524                 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
9525
9526         if (!new_crtc_state)
9527                 return true;
9528
9529         /* CRTC Degamma changes currently require us to recreate planes. */
9530         if (new_crtc_state->color_mgmt_changed)
9531                 return true;
9532
9533         if (drm_atomic_crtc_needs_modeset(new_crtc_state))
9534                 return true;
9535
9536         /*
9537          * If there are any new primary or overlay planes being added or
9538          * removed then the z-order can potentially change. To ensure
9539          * correct z-order and pipe acquisition the current DC architecture
9540          * requires us to remove and recreate all existing planes.
9541          *
9542          * TODO: Come up with a more elegant solution for this.
9543          */
9544         for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
9545                 struct amdgpu_framebuffer *old_afb, *new_afb;
9546                 if (other->type == DRM_PLANE_TYPE_CURSOR)
9547                         continue;
9548
9549                 if (old_other_state->crtc != new_plane_state->crtc &&
9550                     new_other_state->crtc != new_plane_state->crtc)
9551                         continue;
9552
9553                 if (old_other_state->crtc != new_other_state->crtc)
9554                         return true;
9555
9556                 /* Src/dst size and scaling updates. */
9557                 if (old_other_state->src_w != new_other_state->src_w ||
9558                     old_other_state->src_h != new_other_state->src_h ||
9559                     old_other_state->crtc_w != new_other_state->crtc_w ||
9560                     old_other_state->crtc_h != new_other_state->crtc_h)
9561                         return true;
9562
9563                 /* Rotation / mirroring updates. */
9564                 if (old_other_state->rotation != new_other_state->rotation)
9565                         return true;
9566
9567                 /* Blending updates. */
9568                 if (old_other_state->pixel_blend_mode !=
9569                     new_other_state->pixel_blend_mode)
9570                         return true;
9571
9572                 /* Alpha updates. */
9573                 if (old_other_state->alpha != new_other_state->alpha)
9574                         return true;
9575
9576                 /* Colorspace changes. */
9577                 if (old_other_state->color_range != new_other_state->color_range ||
9578                     old_other_state->color_encoding != new_other_state->color_encoding)
9579                         return true;
9580
9581                 /* Framebuffer checks fall at the end. */
9582                 if (!old_other_state->fb || !new_other_state->fb)
9583                         continue;
9584
9585                 /* Pixel format changes can require bandwidth updates. */
9586                 if (old_other_state->fb->format != new_other_state->fb->format)
9587                         return true;
9588
9589                 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb;
9590                 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb;
9591
9592                 /* Tiling and DCC changes also require bandwidth updates. */
9593                 if (old_afb->tiling_flags != new_afb->tiling_flags ||
9594                     old_afb->base.modifier != new_afb->base.modifier)
9595                         return true;
9596         }
9597
9598         return false;
9599 }
9600
9601 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,
9602                               struct drm_plane_state *new_plane_state,
9603                               struct drm_framebuffer *fb)
9604 {
9605         struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev);
9606         struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
9607         unsigned int pitch;
9608         bool linear;
9609
9610         if (fb->width > new_acrtc->max_cursor_width ||
9611             fb->height > new_acrtc->max_cursor_height) {
9612                 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n",
9613                                  new_plane_state->fb->width,
9614                                  new_plane_state->fb->height);
9615                 return -EINVAL;
9616         }
9617         if (new_plane_state->src_w != fb->width << 16 ||
9618             new_plane_state->src_h != fb->height << 16) {
9619                 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9620                 return -EINVAL;
9621         }
9622
9623         /* Pitch in pixels */
9624         pitch = fb->pitches[0] / fb->format->cpp[0];
9625
9626         if (fb->width != pitch) {
9627                 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d",
9628                                  fb->width, pitch);
9629                 return -EINVAL;
9630         }
9631
9632         switch (pitch) {
9633         case 64:
9634         case 128:
9635         case 256:
9636                 /* FB pitch is supported by cursor plane */
9637                 break;
9638         default:
9639                 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch);
9640                 return -EINVAL;
9641         }
9642
9643         /* Core DRM takes care of checking FB modifiers, so we only need to
9644          * check tiling flags when the FB doesn't have a modifier. */
9645         if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) {
9646                 if (adev->family < AMDGPU_FAMILY_AI) {
9647                         linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &&
9648                                  AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &&
9649                                  AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0;
9650                 } else {
9651                         linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;
9652                 }
9653                 if (!linear) {
9654                         DRM_DEBUG_ATOMIC("Cursor FB not linear");
9655                         return -EINVAL;
9656                 }
9657         }
9658
9659         return 0;
9660 }
9661
9662 static int dm_update_plane_state(struct dc *dc,
9663                                  struct drm_atomic_state *state,
9664                                  struct drm_plane *plane,
9665                                  struct drm_plane_state *old_plane_state,
9666                                  struct drm_plane_state *new_plane_state,
9667                                  bool enable,
9668                                  bool *lock_and_validation_needed)
9669 {
9670
9671         struct dm_atomic_state *dm_state = NULL;
9672         struct drm_crtc *new_plane_crtc, *old_plane_crtc;
9673         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9674         struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
9675         struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
9676         struct amdgpu_crtc *new_acrtc;
9677         bool needs_reset;
9678         int ret = 0;
9679
9680
9681         new_plane_crtc = new_plane_state->crtc;
9682         old_plane_crtc = old_plane_state->crtc;
9683         dm_new_plane_state = to_dm_plane_state(new_plane_state);
9684         dm_old_plane_state = to_dm_plane_state(old_plane_state);
9685
9686         if (plane->type == DRM_PLANE_TYPE_CURSOR) {
9687                 if (!enable || !new_plane_crtc ||
9688                         drm_atomic_plane_disabling(plane->state, new_plane_state))
9689                         return 0;
9690
9691                 new_acrtc = to_amdgpu_crtc(new_plane_crtc);
9692
9693                 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) {
9694                         DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9695                         return -EINVAL;
9696                 }
9697
9698                 if (new_plane_state->fb) {
9699                         ret = dm_check_cursor_fb(new_acrtc, new_plane_state,
9700                                                  new_plane_state->fb);
9701                         if (ret)
9702                                 return ret;
9703                 }
9704
9705                 return 0;
9706         }
9707
9708         needs_reset = should_reset_plane(state, plane, old_plane_state,
9709                                          new_plane_state);
9710
9711         /* Remove any changed/removed planes */
9712         if (!enable) {
9713                 if (!needs_reset)
9714                         return 0;
9715
9716                 if (!old_plane_crtc)
9717                         return 0;
9718
9719                 old_crtc_state = drm_atomic_get_old_crtc_state(
9720                                 state, old_plane_crtc);
9721                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9722
9723                 if (!dm_old_crtc_state->stream)
9724                         return 0;
9725
9726                 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
9727                                 plane->base.id, old_plane_crtc->base.id);
9728
9729                 ret = dm_atomic_get_state(state, &dm_state);
9730                 if (ret)
9731                         return ret;
9732
9733                 if (!dc_remove_plane_from_context(
9734                                 dc,
9735                                 dm_old_crtc_state->stream,
9736                                 dm_old_plane_state->dc_state,
9737                                 dm_state->context)) {
9738
9739                         return -EINVAL;
9740                 }
9741
9742
9743                 dc_plane_state_release(dm_old_plane_state->dc_state);
9744                 dm_new_plane_state->dc_state = NULL;
9745
9746                 *lock_and_validation_needed = true;
9747
9748         } else { /* Add new planes */
9749                 struct dc_plane_state *dc_new_plane_state;
9750
9751                 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
9752                         return 0;
9753
9754                 if (!new_plane_crtc)
9755                         return 0;
9756
9757                 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
9758                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9759
9760                 if (!dm_new_crtc_state->stream)
9761                         return 0;
9762
9763                 if (!needs_reset)
9764                         return 0;
9765
9766                 ret = dm_plane_helper_check_state(new_plane_state, new_crtc_state);
9767                 if (ret)
9768                         return ret;
9769
9770                 WARN_ON(dm_new_plane_state->dc_state);
9771
9772                 dc_new_plane_state = dc_create_plane_state(dc);
9773                 if (!dc_new_plane_state)
9774                         return -ENOMEM;
9775
9776                 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n",
9777                                  plane->base.id, new_plane_crtc->base.id);
9778
9779                 ret = fill_dc_plane_attributes(
9780                         drm_to_adev(new_plane_crtc->dev),
9781                         dc_new_plane_state,
9782                         new_plane_state,
9783                         new_crtc_state);
9784                 if (ret) {
9785                         dc_plane_state_release(dc_new_plane_state);
9786                         return ret;
9787                 }
9788
9789                 ret = dm_atomic_get_state(state, &dm_state);
9790                 if (ret) {
9791                         dc_plane_state_release(dc_new_plane_state);
9792                         return ret;
9793                 }
9794
9795                 /*
9796                  * Any atomic check errors that occur after this will
9797                  * not need a release. The plane state will be attached
9798                  * to the stream, and therefore part of the atomic
9799                  * state. It'll be released when the atomic state is
9800                  * cleaned.
9801                  */
9802                 if (!dc_add_plane_to_context(
9803                                 dc,
9804                                 dm_new_crtc_state->stream,
9805                                 dc_new_plane_state,
9806                                 dm_state->context)) {
9807
9808                         dc_plane_state_release(dc_new_plane_state);
9809                         return -EINVAL;
9810                 }
9811
9812                 dm_new_plane_state->dc_state = dc_new_plane_state;
9813
9814                 /* Tell DC to do a full surface update every time there
9815                  * is a plane change. Inefficient, but works for now.
9816                  */
9817                 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
9818
9819                 *lock_and_validation_needed = true;
9820         }
9821
9822
9823         return ret;
9824 }
9825
9826 static int dm_check_crtc_cursor(struct drm_atomic_state *state,
9827                                 struct drm_crtc *crtc,
9828                                 struct drm_crtc_state *new_crtc_state)
9829 {
9830         struct drm_plane_state *new_cursor_state, *new_primary_state;
9831         int cursor_scale_w, cursor_scale_h, primary_scale_w, primary_scale_h;
9832
9833         /* On DCE and DCN there is no dedicated hardware cursor plane. We get a
9834          * cursor per pipe but it's going to inherit the scaling and
9835          * positioning from the underlying pipe. Check the cursor plane's
9836          * blending properties match the primary plane's. */
9837
9838         new_cursor_state = drm_atomic_get_new_plane_state(state, crtc->cursor);
9839         new_primary_state = drm_atomic_get_new_plane_state(state, crtc->primary);
9840         if (!new_cursor_state || !new_primary_state ||
9841             !new_cursor_state->fb || !new_primary_state->fb) {
9842                 return 0;
9843         }
9844
9845         cursor_scale_w = new_cursor_state->crtc_w * 1000 /
9846                          (new_cursor_state->src_w >> 16);
9847         cursor_scale_h = new_cursor_state->crtc_h * 1000 /
9848                          (new_cursor_state->src_h >> 16);
9849
9850         primary_scale_w = new_primary_state->crtc_w * 1000 /
9851                          (new_primary_state->src_w >> 16);
9852         primary_scale_h = new_primary_state->crtc_h * 1000 /
9853                          (new_primary_state->src_h >> 16);
9854
9855         if (cursor_scale_w != primary_scale_w ||
9856             cursor_scale_h != primary_scale_h) {
9857                 DRM_DEBUG_ATOMIC("Cursor plane scaling doesn't match primary plane\n");
9858                 return -EINVAL;
9859         }
9860
9861         return 0;
9862 }
9863
9864 #if defined(CONFIG_DRM_AMD_DC_DCN)
9865 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
9866 {
9867         struct drm_connector *connector;
9868         struct drm_connector_state *conn_state;
9869         struct amdgpu_dm_connector *aconnector = NULL;
9870         int i;
9871         for_each_new_connector_in_state(state, connector, conn_state, i) {
9872                 if (conn_state->crtc != crtc)
9873                         continue;
9874
9875                 aconnector = to_amdgpu_dm_connector(connector);
9876                 if (!aconnector->port || !aconnector->mst_port)
9877                         aconnector = NULL;
9878                 else
9879                         break;
9880         }
9881
9882         if (!aconnector)
9883                 return 0;
9884
9885         return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_port->mst_mgr);
9886 }
9887 #endif
9888
9889 static int validate_overlay(struct drm_atomic_state *state)
9890 {
9891         int i;
9892         struct drm_plane *plane;
9893         struct drm_plane_state *old_plane_state, *new_plane_state;
9894         struct drm_plane_state *primary_state, *overlay_state = NULL;
9895
9896         /* Check if primary plane is contained inside overlay */
9897         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
9898                 if (plane->type == DRM_PLANE_TYPE_OVERLAY) {
9899                         if (drm_atomic_plane_disabling(plane->state, new_plane_state))
9900                                 return 0;
9901
9902                         overlay_state = new_plane_state;
9903                         continue;
9904                 }
9905         }
9906
9907         /* check if we're making changes to the overlay plane */
9908         if (!overlay_state)
9909                 return 0;
9910
9911         /* check if overlay plane is enabled */
9912         if (!overlay_state->crtc)
9913                 return 0;
9914
9915         /* find the primary plane for the CRTC that the overlay is enabled on */
9916         primary_state = drm_atomic_get_plane_state(state, overlay_state->crtc->primary);
9917         if (IS_ERR(primary_state))
9918                 return PTR_ERR(primary_state);
9919
9920         /* check if primary plane is enabled */
9921         if (!primary_state->crtc)
9922                 return 0;
9923
9924         /* Perform the bounds check to ensure the overlay plane covers the primary */
9925         if (primary_state->crtc_x < overlay_state->crtc_x ||
9926             primary_state->crtc_y < overlay_state->crtc_y ||
9927             primary_state->crtc_x + primary_state->crtc_w > overlay_state->crtc_x + overlay_state->crtc_w ||
9928             primary_state->crtc_y + primary_state->crtc_h > overlay_state->crtc_y + overlay_state->crtc_h) {
9929                 DRM_DEBUG_ATOMIC("Overlay plane is enabled with hardware cursor but does not fully cover primary plane\n");
9930                 return -EINVAL;
9931         }
9932
9933         return 0;
9934 }
9935
9936 /**
9937  * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
9938  * @dev: The DRM device
9939  * @state: The atomic state to commit
9940  *
9941  * Validate that the given atomic state is programmable by DC into hardware.
9942  * This involves constructing a &struct dc_state reflecting the new hardware
9943  * state we wish to commit, then querying DC to see if it is programmable. It's
9944  * important not to modify the existing DC state. Otherwise, atomic_check
9945  * may unexpectedly commit hardware changes.
9946  *
9947  * When validating the DC state, it's important that the right locks are
9948  * acquired. For full updates case which removes/adds/updates streams on one
9949  * CRTC while flipping on another CRTC, acquiring global lock will guarantee
9950  * that any such full update commit will wait for completion of any outstanding
9951  * flip using DRMs synchronization events.
9952  *
9953  * Note that DM adds the affected connectors for all CRTCs in state, when that
9954  * might not seem necessary. This is because DC stream creation requires the
9955  * DC sink, which is tied to the DRM connector state. Cleaning this up should
9956  * be possible but non-trivial - a possible TODO item.
9957  *
9958  * Return: -Error code if validation failed.
9959  */
9960 static int amdgpu_dm_atomic_check(struct drm_device *dev,
9961                                   struct drm_atomic_state *state)
9962 {
9963         struct amdgpu_device *adev = drm_to_adev(dev);
9964         struct dm_atomic_state *dm_state = NULL;
9965         struct dc *dc = adev->dm.dc;
9966         struct drm_connector *connector;
9967         struct drm_connector_state *old_con_state, *new_con_state;
9968         struct drm_crtc *crtc;
9969         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9970         struct drm_plane *plane;
9971         struct drm_plane_state *old_plane_state, *new_plane_state;
9972         enum dc_status status;
9973         int ret, i;
9974         bool lock_and_validation_needed = false;
9975         struct dm_crtc_state *dm_old_crtc_state;
9976
9977         trace_amdgpu_dm_atomic_check_begin(state);
9978
9979         ret = drm_atomic_helper_check_modeset(dev, state);
9980         if (ret)
9981                 goto fail;
9982
9983         /* Check connector changes */
9984         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9985                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
9986                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9987
9988                 /* Skip connectors that are disabled or part of modeset already. */
9989                 if (!old_con_state->crtc && !new_con_state->crtc)
9990                         continue;
9991
9992                 if (!new_con_state->crtc)
9993                         continue;
9994
9995                 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc);
9996                 if (IS_ERR(new_crtc_state)) {
9997                         ret = PTR_ERR(new_crtc_state);
9998                         goto fail;
9999                 }
10000
10001                 if (dm_old_con_state->abm_level !=
10002                     dm_new_con_state->abm_level)
10003                         new_crtc_state->connectors_changed = true;
10004         }
10005
10006 #if defined(CONFIG_DRM_AMD_DC_DCN)
10007         if (dc_resource_is_dsc_encoding_supported(dc)) {
10008                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10009                         if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
10010                                 ret = add_affected_mst_dsc_crtcs(state, crtc);
10011                                 if (ret)
10012                                         goto fail;
10013                         }
10014                 }
10015         }
10016 #endif
10017         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10018                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
10019
10020                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
10021                     !new_crtc_state->color_mgmt_changed &&
10022                     old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled &&
10023                         dm_old_crtc_state->dsc_force_changed == false)
10024                         continue;
10025
10026                 if (!new_crtc_state->enable)
10027                         continue;
10028
10029                 ret = drm_atomic_add_affected_connectors(state, crtc);
10030                 if (ret)
10031                         return ret;
10032
10033                 ret = drm_atomic_add_affected_planes(state, crtc);
10034                 if (ret)
10035                         goto fail;
10036
10037                 if (dm_old_crtc_state->dsc_force_changed)
10038                         new_crtc_state->mode_changed = true;
10039         }
10040
10041         /*
10042          * Add all primary and overlay planes on the CRTC to the state
10043          * whenever a plane is enabled to maintain correct z-ordering
10044          * and to enable fast surface updates.
10045          */
10046         drm_for_each_crtc(crtc, dev) {
10047                 bool modified = false;
10048
10049                 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
10050                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
10051                                 continue;
10052
10053                         if (new_plane_state->crtc == crtc ||
10054                             old_plane_state->crtc == crtc) {
10055                                 modified = true;
10056                                 break;
10057                         }
10058                 }
10059
10060                 if (!modified)
10061                         continue;
10062
10063                 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
10064                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
10065                                 continue;
10066
10067                         new_plane_state =
10068                                 drm_atomic_get_plane_state(state, plane);
10069
10070                         if (IS_ERR(new_plane_state)) {
10071                                 ret = PTR_ERR(new_plane_state);
10072                                 goto fail;
10073                         }
10074                 }
10075         }
10076
10077         /* Remove exiting planes if they are modified */
10078         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10079                 ret = dm_update_plane_state(dc, state, plane,
10080                                             old_plane_state,
10081                                             new_plane_state,
10082                                             false,
10083                                             &lock_and_validation_needed);
10084                 if (ret)
10085                         goto fail;
10086         }
10087
10088         /* Disable all crtcs which require disable */
10089         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10090                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10091                                            old_crtc_state,
10092                                            new_crtc_state,
10093                                            false,
10094                                            &lock_and_validation_needed);
10095                 if (ret)
10096                         goto fail;
10097         }
10098
10099         /* Enable all crtcs which require enable */
10100         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10101                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10102                                            old_crtc_state,
10103                                            new_crtc_state,
10104                                            true,
10105                                            &lock_and_validation_needed);
10106                 if (ret)
10107                         goto fail;
10108         }
10109
10110         ret = validate_overlay(state);
10111         if (ret)
10112                 goto fail;
10113
10114         /* Add new/modified planes */
10115         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10116                 ret = dm_update_plane_state(dc, state, plane,
10117                                             old_plane_state,
10118                                             new_plane_state,
10119                                             true,
10120                                             &lock_and_validation_needed);
10121                 if (ret)
10122                         goto fail;
10123         }
10124
10125         /* Run this here since we want to validate the streams we created */
10126         ret = drm_atomic_helper_check_planes(dev, state);
10127         if (ret)
10128                 goto fail;
10129
10130         /* Check cursor planes scaling */
10131         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10132                 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state);
10133                 if (ret)
10134                         goto fail;
10135         }
10136
10137         if (state->legacy_cursor_update) {
10138                 /*
10139                  * This is a fast cursor update coming from the plane update
10140                  * helper, check if it can be done asynchronously for better
10141                  * performance.
10142                  */
10143                 state->async_update =
10144                         !drm_atomic_helper_async_check(dev, state);
10145
10146                 /*
10147                  * Skip the remaining global validation if this is an async
10148                  * update. Cursor updates can be done without affecting
10149                  * state or bandwidth calcs and this avoids the performance
10150                  * penalty of locking the private state object and
10151                  * allocating a new dc_state.
10152                  */
10153                 if (state->async_update)
10154                         return 0;
10155         }
10156
10157         /* Check scaling and underscan changes*/
10158         /* TODO Removed scaling changes validation due to inability to commit
10159          * new stream into context w\o causing full reset. Need to
10160          * decide how to handle.
10161          */
10162         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
10163                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
10164                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10165                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
10166
10167                 /* Skip any modesets/resets */
10168                 if (!acrtc || drm_atomic_crtc_needs_modeset(
10169                                 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
10170                         continue;
10171
10172                 /* Skip any thing not scale or underscan changes */
10173                 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
10174                         continue;
10175
10176                 lock_and_validation_needed = true;
10177         }
10178
10179         /**
10180          * Streams and planes are reset when there are changes that affect
10181          * bandwidth. Anything that affects bandwidth needs to go through
10182          * DC global validation to ensure that the configuration can be applied
10183          * to hardware.
10184          *
10185          * We have to currently stall out here in atomic_check for outstanding
10186          * commits to finish in this case because our IRQ handlers reference
10187          * DRM state directly - we can end up disabling interrupts too early
10188          * if we don't.
10189          *
10190          * TODO: Remove this stall and drop DM state private objects.
10191          */
10192         if (lock_and_validation_needed) {
10193                 ret = dm_atomic_get_state(state, &dm_state);
10194                 if (ret)
10195                         goto fail;
10196
10197                 ret = do_aquire_global_lock(dev, state);
10198                 if (ret)
10199                         goto fail;
10200
10201 #if defined(CONFIG_DRM_AMD_DC_DCN)
10202                 if (!compute_mst_dsc_configs_for_state(state, dm_state->context))
10203                         goto fail;
10204
10205                 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context);
10206                 if (ret)
10207                         goto fail;
10208 #endif
10209
10210                 /*
10211                  * Perform validation of MST topology in the state:
10212                  * We need to perform MST atomic check before calling
10213                  * dc_validate_global_state(), or there is a chance
10214                  * to get stuck in an infinite loop and hang eventually.
10215                  */
10216                 ret = drm_dp_mst_atomic_check(state);
10217                 if (ret)
10218                         goto fail;
10219                 status = dc_validate_global_state(dc, dm_state->context, false);
10220                 if (status != DC_OK) {
10221                         DC_LOG_WARNING("DC global validation failure: %s (%d)",
10222                                        dc_status_to_str(status), status);
10223                         ret = -EINVAL;
10224                         goto fail;
10225                 }
10226         } else {
10227                 /*
10228                  * The commit is a fast update. Fast updates shouldn't change
10229                  * the DC context, affect global validation, and can have their
10230                  * commit work done in parallel with other commits not touching
10231                  * the same resource. If we have a new DC context as part of
10232                  * the DM atomic state from validation we need to free it and
10233                  * retain the existing one instead.
10234                  *
10235                  * Furthermore, since the DM atomic state only contains the DC
10236                  * context and can safely be annulled, we can free the state
10237                  * and clear the associated private object now to free
10238                  * some memory and avoid a possible use-after-free later.
10239                  */
10240
10241                 for (i = 0; i < state->num_private_objs; i++) {
10242                         struct drm_private_obj *obj = state->private_objs[i].ptr;
10243
10244                         if (obj->funcs == adev->dm.atomic_obj.funcs) {
10245                                 int j = state->num_private_objs-1;
10246
10247                                 dm_atomic_destroy_state(obj,
10248                                                 state->private_objs[i].state);
10249
10250                                 /* If i is not at the end of the array then the
10251                                  * last element needs to be moved to where i was
10252                                  * before the array can safely be truncated.
10253                                  */
10254                                 if (i != j)
10255                                         state->private_objs[i] =
10256                                                 state->private_objs[j];
10257
10258                                 state->private_objs[j].ptr = NULL;
10259                                 state->private_objs[j].state = NULL;
10260                                 state->private_objs[j].old_state = NULL;
10261                                 state->private_objs[j].new_state = NULL;
10262
10263                                 state->num_private_objs = j;
10264                                 break;
10265                         }
10266                 }
10267         }
10268
10269         /* Store the overall update type for use later in atomic check. */
10270         for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
10271                 struct dm_crtc_state *dm_new_crtc_state =
10272                         to_dm_crtc_state(new_crtc_state);
10273
10274                 dm_new_crtc_state->update_type = lock_and_validation_needed ?
10275                                                          UPDATE_TYPE_FULL :
10276                                                          UPDATE_TYPE_FAST;
10277         }
10278
10279         /* Must be success */
10280         WARN_ON(ret);
10281
10282         trace_amdgpu_dm_atomic_check_finish(state, ret);
10283
10284         return ret;
10285
10286 fail:
10287         if (ret == -EDEADLK)
10288                 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
10289         else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
10290                 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
10291         else
10292                 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
10293
10294         trace_amdgpu_dm_atomic_check_finish(state, ret);
10295
10296         return ret;
10297 }
10298
10299 static bool is_dp_capable_without_timing_msa(struct dc *dc,
10300                                              struct amdgpu_dm_connector *amdgpu_dm_connector)
10301 {
10302         uint8_t dpcd_data;
10303         bool capable = false;
10304
10305         if (amdgpu_dm_connector->dc_link &&
10306                 dm_helpers_dp_read_dpcd(
10307                                 NULL,
10308                                 amdgpu_dm_connector->dc_link,
10309                                 DP_DOWN_STREAM_PORT_COUNT,
10310                                 &dpcd_data,
10311                                 sizeof(dpcd_data))) {
10312                 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
10313         }
10314
10315         return capable;
10316 }
10317
10318 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
10319                 uint8_t *edid_ext, int len,
10320                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10321 {
10322         int i;
10323         struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
10324         struct dc *dc = adev->dm.dc;
10325
10326         /* send extension block to DMCU for parsing */
10327         for (i = 0; i < len; i += 8) {
10328                 bool res;
10329                 int offset;
10330
10331                 /* send 8 bytes a time */
10332                 if (!dc_edid_parser_send_cea(dc, i, len, &edid_ext[i], 8))
10333                         return false;
10334
10335                 if (i+8 == len) {
10336                         /* EDID block sent completed, expect result */
10337                         int version, min_rate, max_rate;
10338
10339                         res = dc_edid_parser_recv_amd_vsdb(dc, &version, &min_rate, &max_rate);
10340                         if (res) {
10341                                 /* amd vsdb found */
10342                                 vsdb_info->freesync_supported = 1;
10343                                 vsdb_info->amd_vsdb_version = version;
10344                                 vsdb_info->min_refresh_rate_hz = min_rate;
10345                                 vsdb_info->max_refresh_rate_hz = max_rate;
10346                                 return true;
10347                         }
10348                         /* not amd vsdb */
10349                         return false;
10350                 }
10351
10352                 /* check for ack*/
10353                 res = dc_edid_parser_recv_cea_ack(dc, &offset);
10354                 if (!res)
10355                         return false;
10356         }
10357
10358         return false;
10359 }
10360
10361 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
10362                 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
10363 {
10364         uint8_t *edid_ext = NULL;
10365         int i;
10366         bool valid_vsdb_found = false;
10367
10368         /*----- drm_find_cea_extension() -----*/
10369         /* No EDID or EDID extensions */
10370         if (edid == NULL || edid->extensions == 0)
10371                 return -ENODEV;
10372
10373         /* Find CEA extension */
10374         for (i = 0; i < edid->extensions; i++) {
10375                 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1);
10376                 if (edid_ext[0] == CEA_EXT)
10377                         break;
10378         }
10379
10380         if (i == edid->extensions)
10381                 return -ENODEV;
10382
10383         /*----- cea_db_offsets() -----*/
10384         if (edid_ext[0] != CEA_EXT)
10385                 return -ENODEV;
10386
10387         valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info);
10388
10389         return valid_vsdb_found ? i : -ENODEV;
10390 }
10391
10392 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
10393                                         struct edid *edid)
10394 {
10395         int i = 0;
10396         struct detailed_timing *timing;
10397         struct detailed_non_pixel *data;
10398         struct detailed_data_monitor_range *range;
10399         struct amdgpu_dm_connector *amdgpu_dm_connector =
10400                         to_amdgpu_dm_connector(connector);
10401         struct dm_connector_state *dm_con_state = NULL;
10402
10403         struct drm_device *dev = connector->dev;
10404         struct amdgpu_device *adev = drm_to_adev(dev);
10405         bool freesync_capable = false;
10406         struct amdgpu_hdmi_vsdb_info vsdb_info = {0};
10407
10408         if (!connector->state) {
10409                 DRM_ERROR("%s - Connector has no state", __func__);
10410                 goto update;
10411         }
10412
10413         if (!edid) {
10414                 dm_con_state = to_dm_connector_state(connector->state);
10415
10416                 amdgpu_dm_connector->min_vfreq = 0;
10417                 amdgpu_dm_connector->max_vfreq = 0;
10418                 amdgpu_dm_connector->pixel_clock_mhz = 0;
10419
10420                 goto update;
10421         }
10422
10423         dm_con_state = to_dm_connector_state(connector->state);
10424
10425         if (!amdgpu_dm_connector->dc_sink) {
10426                 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
10427                 goto update;
10428         }
10429         if (!adev->dm.freesync_module)
10430                 goto update;
10431
10432
10433         if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
10434                 || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
10435                 bool edid_check_required = false;
10436
10437                 if (edid) {
10438                         edid_check_required = is_dp_capable_without_timing_msa(
10439                                                 adev->dm.dc,
10440                                                 amdgpu_dm_connector);
10441                 }
10442
10443                 if (edid_check_required == true && (edid->version > 1 ||
10444                    (edid->version == 1 && edid->revision > 1))) {
10445                         for (i = 0; i < 4; i++) {
10446
10447                                 timing  = &edid->detailed_timings[i];
10448                                 data    = &timing->data.other_data;
10449                                 range   = &data->data.range;
10450                                 /*
10451                                  * Check if monitor has continuous frequency mode
10452                                  */
10453                                 if (data->type != EDID_DETAIL_MONITOR_RANGE)
10454                                         continue;
10455                                 /*
10456                                  * Check for flag range limits only. If flag == 1 then
10457                                  * no additional timing information provided.
10458                                  * Default GTF, GTF Secondary curve and CVT are not
10459                                  * supported
10460                                  */
10461                                 if (range->flags != 1)
10462                                         continue;
10463
10464                                 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
10465                                 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
10466                                 amdgpu_dm_connector->pixel_clock_mhz =
10467                                         range->pixel_clock_mhz * 10;
10468
10469                                 connector->display_info.monitor_range.min_vfreq = range->min_vfreq;
10470                                 connector->display_info.monitor_range.max_vfreq = range->max_vfreq;
10471
10472                                 break;
10473                         }
10474
10475                         if (amdgpu_dm_connector->max_vfreq -
10476                             amdgpu_dm_connector->min_vfreq > 10) {
10477
10478                                 freesync_capable = true;
10479                         }
10480                 }
10481         } else if (edid && amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
10482                 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10483                 if (i >= 0 && vsdb_info.freesync_supported) {
10484                         timing  = &edid->detailed_timings[i];
10485                         data    = &timing->data.other_data;
10486
10487                         amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10488                         amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10489                         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10490                                 freesync_capable = true;
10491
10492                         connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10493                         connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10494                 }
10495         }
10496
10497 update:
10498         if (dm_con_state)
10499                 dm_con_state->freesync_capable = freesync_capable;
10500
10501         if (connector->vrr_capable_property)
10502                 drm_connector_set_vrr_capable_property(connector,
10503                                                        freesync_capable);
10504 }
10505
10506 static void amdgpu_dm_set_psr_caps(struct dc_link *link)
10507 {
10508         uint8_t dpcd_data[EDP_PSR_RECEIVER_CAP_SIZE];
10509
10510         if (!(link->connector_signal & SIGNAL_TYPE_EDP))
10511                 return;
10512         if (link->type == dc_connection_none)
10513                 return;
10514         if (dm_helpers_dp_read_dpcd(NULL, link, DP_PSR_SUPPORT,
10515                                         dpcd_data, sizeof(dpcd_data))) {
10516                 link->dpcd_caps.psr_caps.psr_version = dpcd_data[0];
10517
10518                 if (dpcd_data[0] == 0) {
10519                         link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
10520                         link->psr_settings.psr_feature_enabled = false;
10521                 } else {
10522                         link->psr_settings.psr_version = DC_PSR_VERSION_1;
10523                         link->psr_settings.psr_feature_enabled = true;
10524                 }
10525
10526                 DRM_INFO("PSR support:%d\n", link->psr_settings.psr_feature_enabled);
10527         }
10528 }
10529
10530 /*
10531  * amdgpu_dm_link_setup_psr() - configure psr link
10532  * @stream: stream state
10533  *
10534  * Return: true if success
10535  */
10536 static bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream)
10537 {
10538         struct dc_link *link = NULL;
10539         struct psr_config psr_config = {0};
10540         struct psr_context psr_context = {0};
10541         bool ret = false;
10542
10543         if (stream == NULL)
10544                 return false;
10545
10546         link = stream->link;
10547
10548         psr_config.psr_version = link->dpcd_caps.psr_caps.psr_version;
10549
10550         if (psr_config.psr_version > 0) {
10551                 psr_config.psr_exit_link_training_required = 0x1;
10552                 psr_config.psr_frame_capture_indication_req = 0;
10553                 psr_config.psr_rfb_setup_time = 0x37;
10554                 psr_config.psr_sdp_transmit_line_num_deadline = 0x20;
10555                 psr_config.allow_smu_optimizations = 0x0;
10556
10557                 ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context);
10558
10559         }
10560         DRM_DEBUG_DRIVER("PSR link: %d\n",      link->psr_settings.psr_feature_enabled);
10561
10562         return ret;
10563 }
10564
10565 /*
10566  * amdgpu_dm_psr_enable() - enable psr f/w
10567  * @stream: stream state
10568  *
10569  * Return: true if success
10570  */
10571 bool amdgpu_dm_psr_enable(struct dc_stream_state *stream)
10572 {
10573         struct dc_link *link = stream->link;
10574         unsigned int vsync_rate_hz = 0;
10575         struct dc_static_screen_params params = {0};
10576         /* Calculate number of static frames before generating interrupt to
10577          * enter PSR.
10578          */
10579         // Init fail safe of 2 frames static
10580         unsigned int num_frames_static = 2;
10581
10582         DRM_DEBUG_DRIVER("Enabling psr...\n");
10583
10584         vsync_rate_hz = div64_u64(div64_u64((
10585                         stream->timing.pix_clk_100hz * 100),
10586                         stream->timing.v_total),
10587                         stream->timing.h_total);
10588
10589         /* Round up
10590          * Calculate number of frames such that at least 30 ms of time has
10591          * passed.
10592          */
10593         if (vsync_rate_hz != 0) {
10594                 unsigned int frame_time_microsec = 1000000 / vsync_rate_hz;
10595                 num_frames_static = (30000 / frame_time_microsec) + 1;
10596         }
10597
10598         params.triggers.cursor_update = true;
10599         params.triggers.overlay_update = true;
10600         params.triggers.surface_update = true;
10601         params.num_frames = num_frames_static;
10602
10603         dc_stream_set_static_screen_params(link->ctx->dc,
10604                                            &stream, 1,
10605                                            &params);
10606
10607         return dc_link_set_psr_allow_active(link, true, false, false);
10608 }
10609
10610 /*
10611  * amdgpu_dm_psr_disable() - disable psr f/w
10612  * @stream:  stream state
10613  *
10614  * Return: true if success
10615  */
10616 static bool amdgpu_dm_psr_disable(struct dc_stream_state *stream)
10617 {
10618
10619         DRM_DEBUG_DRIVER("Disabling psr...\n");
10620
10621         return dc_link_set_psr_allow_active(stream->link, false, true, false);
10622 }
10623
10624 /*
10625  * amdgpu_dm_psr_disable() - disable psr f/w
10626  * if psr is enabled on any stream
10627  *
10628  * Return: true if success
10629  */
10630 static bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm)
10631 {
10632         DRM_DEBUG_DRIVER("Disabling psr if psr is enabled on any stream\n");
10633         return dc_set_psr_allow_active(dm->dc, false);
10634 }
10635
10636 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
10637 {
10638         struct amdgpu_device *adev = drm_to_adev(dev);
10639         struct dc *dc = adev->dm.dc;
10640         int i;
10641
10642         mutex_lock(&adev->dm.dc_lock);
10643         if (dc->current_state) {
10644                 for (i = 0; i < dc->current_state->stream_count; ++i)
10645                         dc->current_state->streams[i]
10646                                 ->triggered_crtc_reset.enabled =
10647                                 adev->dm.force_timing_sync;
10648
10649                 dm_enable_per_frame_crtc_master_sync(dc->current_state);
10650                 dc_trigger_sync(dc, dc->current_state);
10651         }
10652         mutex_unlock(&adev->dm.dc_lock);
10653 }
10654
10655 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
10656                        uint32_t value, const char *func_name)
10657 {
10658 #ifdef DM_CHECK_ADDR_0
10659         if (address == 0) {
10660                 DC_ERR("invalid register write. address = 0");
10661                 return;
10662         }
10663 #endif
10664         cgs_write_register(ctx->cgs_device, address, value);
10665         trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
10666 }
10667
10668 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
10669                           const char *func_name)
10670 {
10671         uint32_t value;
10672 #ifdef DM_CHECK_ADDR_0
10673         if (address == 0) {
10674                 DC_ERR("invalid register read; address = 0\n");
10675                 return 0;
10676         }
10677 #endif
10678
10679         if (ctx->dmub_srv &&
10680             ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
10681             !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
10682                 ASSERT(false);
10683                 return 0;
10684         }
10685
10686         value = cgs_read_register(ctx->cgs_device, address);
10687
10688         trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
10689
10690         return value;
10691 }