drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 /* The caprices of the preprocessor require that this be declared right here */
  27 #define CREATE_TRACE_POINTS
  28
  29 #include "dm_services_types.h"
  30 #include "dc.h"
  31 #include "link_enc_cfg.h"
  32 #include "dc/inc/core_types.h"
  33 #include "dal_asic_id.h"
  34 #include "dmub/dmub_srv.h"
  35 #include "dc/inc/hw/dmcu.h"
  36 #include "dc/inc/hw/abm.h"
  37 #include "dc/dc_dmub_srv.h"
  38 #include "dc/dc_edid_parser.h"
  39 #include "dc/dc_stat.h"
  40 #include "amdgpu_dm_trace.h"
  41 #include "dpcd_defs.h"
  42 #include "link/protocols/link_dpcd.h"
  43 #include "link_service_types.h"
  44 #include "link/protocols/link_dp_capability.h"
  45 #include "link/protocols/link_ddc.h"
  46
  47 #include "vid.h"
  48 #include "amdgpu.h"
  49 #include "amdgpu_display.h"
  50 #include "amdgpu_ucode.h"
  51 #include "atom.h"
  52 #include "amdgpu_dm.h"
  53 #include "amdgpu_dm_plane.h"
  54 #include "amdgpu_dm_crtc.h"
  55 #include "amdgpu_dm_hdcp.h"
  56 #include <drm/display/drm_hdcp_helper.h>
  57 #include "amdgpu_pm.h"
  58 #include "amdgpu_atombios.h"
  59
  60 #include "amd_shared.h"
  61 #include "amdgpu_dm_irq.h"
  62 #include "dm_helpers.h"
  63 #include "amdgpu_dm_mst_types.h"
  64 #if defined(CONFIG_DEBUG_FS)
  65 #include "amdgpu_dm_debugfs.h"
  66 #endif
  67 #include "amdgpu_dm_psr.h"
  68 #include "amdgpu_dm_replay.h"
  69
  70 #include "ivsrcid/ivsrcid_vislands30.h"
  71
  72 #include <linux/backlight.h>
  73 #include <linux/module.h>
  74 #include <linux/moduleparam.h>
  75 #include <linux/types.h>
  76 #include <linux/pm_runtime.h>
  77 #include <linux/pci.h>
  78 #include <linux/firmware.h>
  79 #include <linux/component.h>
  80 #include <linux/dmi.h>
  81
  82 #include <drm/display/drm_dp_mst_helper.h>
  83 #include <drm/display/drm_hdmi_helper.h>
  84 #include <drm/drm_atomic.h>
  85 #include <drm/drm_atomic_uapi.h>
  86 #include <drm/drm_atomic_helper.h>
  87 #include <drm/drm_blend.h>
  88 #include <drm/drm_fourcc.h>
  89 #include <drm/drm_edid.h>
  90 #include <drm/drm_vblank.h>
  91 #include <drm/drm_audio_component.h>
  92 #include <drm/drm_gem_atomic_helper.h>
  93 #include <drm/drm_plane_helper.h>
  94
  95 #include <acpi/video.h>
  96
  97 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
  98
  99 #include "dcn/dcn_1_0_offset.h"
 100 #include "dcn/dcn_1_0_sh_mask.h"
 101 #include "soc15_hw_ip.h"
 102 #include "soc15_common.h"
 103 #include "vega10_ip_offset.h"
 104
 105 #include "gc/gc_11_0_0_offset.h"
 106 #include "gc/gc_11_0_0_sh_mask.h"
 107
 108 #include "modules/inc/mod_freesync.h"
 109 #include "modules/power/power_helpers.h"
 110
 111 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
 112 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
 113 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"
 114 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
 115 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
 116 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
 117 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
 118 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
 119 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
 120 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
 121 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"
 122 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
 123 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin"
 124 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);
 125 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin"
 126 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);
 127 #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin"
 128 MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB);
 129 #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin"
 130 MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB);
 131 #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin"
 132 MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB);
 133
 134 #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin"
 135 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB);
 136 #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin"
 137 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB);
 138
 139 #define FIRMWARE_RAVEN_DMCU             "amdgpu/raven_dmcu.bin"
 140 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
 141
 142 #define FIRMWARE_NAVI12_DMCU            "amdgpu/navi12_dmcu.bin"
 143 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);
 144
 145 /* Number of bytes in PSP header for firmware. */
 146 #define PSP_HEADER_BYTES 0x100
 147
 148 /* Number of bytes in PSP footer for firmware. */
 149 #define PSP_FOOTER_BYTES 0x100
 150
 151 /**
 152  * DOC: overview
 153  *
 154  * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
 155  * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM
 156  * requests into DC requests, and DC responses into DRM responses.
 157  *
 158  * The root control structure is &struct amdgpu_display_manager.
 159  */
 160
 161 /* basic init/fini API */
 162 static int amdgpu_dm_init(struct amdgpu_device *adev);
 163 static void amdgpu_dm_fini(struct amdgpu_device *adev);
 164 static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector);
 165
 166 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)
 167 {
 168         switch (link->dpcd_caps.dongle_type) {
 169         case DISPLAY_DONGLE_NONE:
 170                 return DRM_MODE_SUBCONNECTOR_Native;
 171         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
 172                 return DRM_MODE_SUBCONNECTOR_VGA;
 173         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
 174         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 175                 return DRM_MODE_SUBCONNECTOR_DVID;
 176         case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
 177         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 178                 return DRM_MODE_SUBCONNECTOR_HDMIA;
 179         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 180         default:
 181                 return DRM_MODE_SUBCONNECTOR_Unknown;
 182         }
 183 }
 184
 185 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector)
 186 {
 187         struct dc_link *link = aconnector->dc_link;
 188         struct drm_connector *connector = &aconnector->base;
 189         enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
 190
 191         if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
 192                 return;
 193
 194         if (aconnector->dc_sink)
 195                 subconnector = get_subconnector_type(link);
 196
 197         drm_object_property_set_value(&connector->base,
 198                         connector->dev->mode_config.dp_subconnector_property,
 199                         subconnector);
 200 }
 201
 202 /*
 203  * initializes drm_device display related structures, based on the information
 204  * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
 205  * drm_encoder, drm_mode_config
 206  *
 207  * Returns 0 on success
 208  */
 209 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
 210 /* removes and deallocates the drm structures, created by the above function */
 211 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
 212
 213 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
 214                                     struct amdgpu_dm_connector *amdgpu_dm_connector,
 215                                     u32 link_index,
 216                                     struct amdgpu_encoder *amdgpu_encoder);
 217 static int amdgpu_dm_encoder_init(struct drm_device *dev,
 218                                   struct amdgpu_encoder *aencoder,
 219                                   uint32_t link_index);
 220
 221 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
 222
 223 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
 224
 225 static int amdgpu_dm_atomic_check(struct drm_device *dev,
 226                                   struct drm_atomic_state *state);
 227
 228 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector);
 229 static void handle_hpd_rx_irq(void *param);
 230
 231 static bool
 232 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
 233                                  struct drm_crtc_state *new_crtc_state);
 234 /*
 235  * dm_vblank_get_counter
 236  *
 237  * @brief
 238  * Get counter for number of vertical blanks
 239  *
 240  * @param
 241  * struct amdgpu_device *adev - [in] desired amdgpu device
 242  * int disp_idx - [in] which CRTC to get the counter from
 243  *
 244  * @return
 245  * Counter for vertical blanks
 246  */
 247 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 248 {
 249         struct amdgpu_crtc *acrtc = NULL;
 250
 251         if (crtc >= adev->mode_info.num_crtc)
 252                 return 0;
 253
 254         acrtc = adev->mode_info.crtcs[crtc];
 255
 256         if (!acrtc->dm_irq_params.stream) {
 257                 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 258                           crtc);
 259                 return 0;
 260         }
 261
 262         return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);
 263 }
 264
 265 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 266                                   u32 *vbl, u32 *position)
 267 {
 268         u32 v_blank_start, v_blank_end, h_position, v_position;
 269         struct amdgpu_crtc *acrtc = NULL;
 270
 271         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 272                 return -EINVAL;
 273
 274         acrtc = adev->mode_info.crtcs[crtc];
 275
 276         if (!acrtc->dm_irq_params.stream) {
 277                 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 278                           crtc);
 279                 return 0;
 280         }
 281
 282         /*
 283          * TODO rework base driver to use values directly.
 284          * for now parse it back into reg-format
 285          */
 286         dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream,
 287                                  &v_blank_start,
 288                                  &v_blank_end,
 289                                  &h_position,
 290                                  &v_position);
 291
 292         *position = v_position | (h_position << 16);
 293         *vbl = v_blank_start | (v_blank_end << 16);
 294
 295         return 0;
 296 }
 297
 298 static bool dm_is_idle(void *handle)
 299 {
 300         /* XXX todo */
 301         return true;
 302 }
 303
 304 static int dm_wait_for_idle(void *handle)
 305 {
 306         /* XXX todo */
 307         return 0;
 308 }
 309
 310 static bool dm_check_soft_reset(void *handle)
 311 {
 312         return false;
 313 }
 314
 315 static int dm_soft_reset(void *handle)
 316 {
 317         /* XXX todo */
 318         return 0;
 319 }
 320
 321 static struct amdgpu_crtc *
 322 get_crtc_by_otg_inst(struct amdgpu_device *adev,
 323                      int otg_inst)
 324 {
 325         struct drm_device *dev = adev_to_drm(adev);
 326         struct drm_crtc *crtc;
 327         struct amdgpu_crtc *amdgpu_crtc;
 328
 329         if (WARN_ON(otg_inst == -1))
 330                 return adev->mode_info.crtcs[0];
 331
 332         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 333                 amdgpu_crtc = to_amdgpu_crtc(crtc);
 334
 335                 if (amdgpu_crtc->otg_inst == otg_inst)
 336                         return amdgpu_crtc;
 337         }
 338
 339         return NULL;
 340 }
 341
 342 static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,
 343                                               struct dm_crtc_state *new_state)
 344 {
 345         if (new_state->freesync_config.state ==  VRR_STATE_ACTIVE_FIXED)
 346                 return true;
 347         else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state))
 348                 return true;
 349         else
 350                 return false;
 351 }
 352
 353 static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update,
 354                                         int planes_count)
 355 {
 356         int i, j;
 357
 358         for (i = 0, j = planes_count - 1; i < j; i++, j--)
 359                 swap(array_of_surface_update[i], array_of_surface_update[j]);
 360 }
 361
 362 /**
 363  * update_planes_and_stream_adapter() - Send planes to be updated in DC
 364  *
 365  * DC has a generic way to update planes and stream via
 366  * dc_update_planes_and_stream function; however, DM might need some
 367  * adjustments and preparation before calling it. This function is a wrapper
 368  * for the dc_update_planes_and_stream that does any required configuration
 369  * before passing control to DC.
 370  *
 371  * @dc: Display Core control structure
 372  * @update_type: specify whether it is FULL/MEDIUM/FAST update
 373  * @planes_count: planes count to update
 374  * @stream: stream state
 375  * @stream_update: stream update
 376  * @array_of_surface_update: dc surface update pointer
 377  *
 378  */
 379 static inline bool update_planes_and_stream_adapter(struct dc *dc,
 380                                                     int update_type,
 381                                                     int planes_count,
 382                                                     struct dc_stream_state *stream,
 383                                                     struct dc_stream_update *stream_update,
 384                                                     struct dc_surface_update *array_of_surface_update)
 385 {
 386         reverse_planes_order(array_of_surface_update, planes_count);
 387
 388         /*
 389          * Previous frame finished and HW is ready for optimization.
 390          */
 391         if (update_type == UPDATE_TYPE_FAST)
 392                 dc_post_update_surfaces_to_stream(dc);
 393
 394         return dc_update_planes_and_stream(dc,
 395                                            array_of_surface_update,
 396                                            planes_count,
 397                                            stream,
 398                                            stream_update);
 399 }
 400
 401 /**
 402  * dm_pflip_high_irq() - Handle pageflip interrupt
 403  * @interrupt_params: ignored
 404  *
 405  * Handles the pageflip interrupt by notifying all interested parties
 406  * that the pageflip has been completed.
 407  */
 408 static void dm_pflip_high_irq(void *interrupt_params)
 409 {
 410         struct amdgpu_crtc *amdgpu_crtc;
 411         struct common_irq_params *irq_params = interrupt_params;
 412         struct amdgpu_device *adev = irq_params->adev;
 413         unsigned long flags;
 414         struct drm_pending_vblank_event *e;
 415         u32 vpos, hpos, v_blank_start, v_blank_end;
 416         bool vrr_active;
 417
 418         amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
 419
 420         /* IRQ could occur when in initial stage */
 421         /* TODO work and BO cleanup */
 422         if (amdgpu_crtc == NULL) {
 423                 DC_LOG_PFLIP("CRTC is null, returning.\n");
 424                 return;
 425         }
 426
 427         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 428
 429         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
 430                 DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p]\n",
 431                              amdgpu_crtc->pflip_status,
 432                              AMDGPU_FLIP_SUBMITTED,
 433                              amdgpu_crtc->crtc_id,
 434                              amdgpu_crtc);
 435                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 436                 return;
 437         }
 438
 439         /* page flip completed. */
 440         e = amdgpu_crtc->event;
 441         amdgpu_crtc->event = NULL;
 442
 443         WARN_ON(!e);
 444
 445         vrr_active = amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc);
 446
 447         /* Fixed refresh rate, or VRR scanout position outside front-porch? */
 448         if (!vrr_active ||
 449             !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start,
 450                                       &v_blank_end, &hpos, &vpos) ||
 451             (vpos < v_blank_start)) {
 452                 /* Update to correct count and vblank timestamp if racing with
 453                  * vblank irq. This also updates to the correct vblank timestamp
 454                  * even in VRR mode, as scanout is past the front-porch atm.
 455                  */
 456                 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
 457
 458                 /* Wake up userspace by sending the pageflip event with proper
 459                  * count and timestamp of vblank of flip completion.
 460                  */
 461                 if (e) {
 462                         drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
 463
 464                         /* Event sent, so done with vblank for this flip */
 465                         drm_crtc_vblank_put(&amdgpu_crtc->base);
 466                 }
 467         } else if (e) {
 468                 /* VRR active and inside front-porch: vblank count and
 469                  * timestamp for pageflip event will only be up to date after
 470                  * drm_crtc_handle_vblank() has been executed from late vblank
 471                  * irq handler after start of back-porch (vline 0). We queue the
 472                  * pageflip event for send-out by drm_crtc_handle_vblank() with
 473                  * updated timestamp and count, once it runs after us.
 474                  *
 475                  * We need to open-code this instead of using the helper
 476                  * drm_crtc_arm_vblank_event(), as that helper would
 477                  * call drm_crtc_accurate_vblank_count(), which we must
 478                  * not call in VRR mode while we are in front-porch!
 479                  */
 480
 481                 /* sequence will be replaced by real count during send-out. */
 482                 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
 483                 e->pipe = amdgpu_crtc->crtc_id;
 484
 485                 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list);
 486                 e = NULL;
 487         }
 488
 489         /* Keep track of vblank of this flip for flip throttling. We use the
 490          * cooked hw counter, as that one incremented at start of this vblank
 491          * of pageflip completion, so last_flip_vblank is the forbidden count
 492          * for queueing new pageflips if vsync + VRR is enabled.
 493          */
 494         amdgpu_crtc->dm_irq_params.last_flip_vblank =
 495                 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base);
 496
 497         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
 498         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 499
 500         DC_LOG_PFLIP("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
 501                      amdgpu_crtc->crtc_id, amdgpu_crtc,
 502                      vrr_active, (int) !e);
 503 }
 504
 505 static void dm_vupdate_high_irq(void *interrupt_params)
 506 {
 507         struct common_irq_params *irq_params = interrupt_params;
 508         struct amdgpu_device *adev = irq_params->adev;
 509         struct amdgpu_crtc *acrtc;
 510         struct drm_device *drm_dev;
 511         struct drm_vblank_crtc *vblank;
 512         ktime_t frame_duration_ns, previous_timestamp;
 513         unsigned long flags;
 514         int vrr_active;
 515
 516         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
 517
 518         if (acrtc) {
 519                 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
 520                 drm_dev = acrtc->base.dev;
 521                 vblank = &drm_dev->vblank[acrtc->base.index];
 522                 previous_timestamp = atomic64_read(&irq_params->previous_timestamp);
 523                 frame_duration_ns = vblank->time - previous_timestamp;
 524
 525                 if (frame_duration_ns > 0) {
 526                         trace_amdgpu_refresh_rate_track(acrtc->base.index,
 527                                                 frame_duration_ns,
 528                                                 ktime_divns(NSEC_PER_SEC, frame_duration_ns));
 529                         atomic64_set(&irq_params->previous_timestamp, vblank->time);
 530                 }
 531
 532                 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d\n",
 533                               acrtc->crtc_id,
 534                               vrr_active);
 535
 536                 /* Core vblank handling is done here after end of front-porch in
 537                  * vrr mode, as vblank timestamping will give valid results
 538                  * while now done after front-porch. This will also deliver
 539                  * page-flip completion events that have been queued to us
 540                  * if a pageflip happened inside front-porch.
 541                  */
 542                 if (vrr_active) {
 543                         amdgpu_dm_crtc_handle_vblank(acrtc);
 544
 545                         /* BTR processing for pre-DCE12 ASICs */
 546                         if (acrtc->dm_irq_params.stream &&
 547                             adev->family < AMDGPU_FAMILY_AI) {
 548                                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 549                                 mod_freesync_handle_v_update(
 550                                     adev->dm.freesync_module,
 551                                     acrtc->dm_irq_params.stream,
 552                                     &acrtc->dm_irq_params.vrr_params);
 553
 554                                 dc_stream_adjust_vmin_vmax(
 555                                     adev->dm.dc,
 556                                     acrtc->dm_irq_params.stream,
 557                                     &acrtc->dm_irq_params.vrr_params.adjust);
 558                                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 559                         }
 560                 }
 561         }
 562 }
 563
 564 /**
 565  * dm_crtc_high_irq() - Handles CRTC interrupt
 566  * @interrupt_params: used for determining the CRTC instance
 567  *
 568  * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
 569  * event handler.
 570  */
 571 static void dm_crtc_high_irq(void *interrupt_params)
 572 {
 573         struct common_irq_params *irq_params = interrupt_params;
 574         struct amdgpu_device *adev = irq_params->adev;
 575         struct amdgpu_crtc *acrtc;
 576         unsigned long flags;
 577         int vrr_active;
 578
 579         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
 580         if (!acrtc)
 581                 return;
 582
 583         vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
 584
 585         DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,
 586                       vrr_active, acrtc->dm_irq_params.active_planes);
 587
 588         /**
 589          * Core vblank handling at start of front-porch is only possible
 590          * in non-vrr mode, as only there vblank timestamping will give
 591          * valid results while done in front-porch. Otherwise defer it
 592          * to dm_vupdate_high_irq after end of front-porch.
 593          */
 594         if (!vrr_active)
 595                 amdgpu_dm_crtc_handle_vblank(acrtc);
 596
 597         /**
 598          * Following stuff must happen at start of vblank, for crc
 599          * computation and below-the-range btr support in vrr mode.
 600          */
 601         amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
 602
 603         /* BTR updates need to happen before VUPDATE on Vega and above. */
 604         if (adev->family < AMDGPU_FAMILY_AI)
 605                 return;
 606
 607         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 608
 609         if (acrtc->dm_irq_params.stream &&
 610             acrtc->dm_irq_params.vrr_params.supported &&
 611             acrtc->dm_irq_params.freesync_config.state ==
 612                     VRR_STATE_ACTIVE_VARIABLE) {
 613                 mod_freesync_handle_v_update(adev->dm.freesync_module,
 614                                              acrtc->dm_irq_params.stream,
 615                                              &acrtc->dm_irq_params.vrr_params);
 616
 617                 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,
 618                                            &acrtc->dm_irq_params.vrr_params.adjust);
 619         }
 620
 621         /*
 622          * If there aren't any active_planes then DCH HUBP may be clock-gated.
 623          * In that case, pageflip completion interrupts won't fire and pageflip
 624          * completion events won't get delivered. Prevent this by sending
 625          * pending pageflip events from here if a flip is still pending.
 626          *
 627          * If any planes are enabled, use dm_pflip_high_irq() instead, to
 628          * avoid race conditions between flip programming and completion,
 629          * which could cause too early flip completion events.
 630          */
 631         if (adev->family >= AMDGPU_FAMILY_RV &&
 632             acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
 633             acrtc->dm_irq_params.active_planes == 0) {
 634                 if (acrtc->event) {
 635                         drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
 636                         acrtc->event = NULL;
 637                         drm_crtc_vblank_put(&acrtc->base);
 638                 }
 639                 acrtc->pflip_status = AMDGPU_FLIP_NONE;
 640         }
 641
 642         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 643 }
 644
 645 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
 646 /**
 647  * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for
 648  * DCN generation ASICs
 649  * @interrupt_params: interrupt parameters
 650  *
 651  * Used to set crc window/read out crc value at vertical line 0 position
 652  */
 653 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)
 654 {
 655         struct common_irq_params *irq_params = interrupt_params;
 656         struct amdgpu_device *adev = irq_params->adev;
 657         struct amdgpu_crtc *acrtc;
 658
 659         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0);
 660
 661         if (!acrtc)
 662                 return;
 663
 664         amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base);
 665 }
 666 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */
 667
 668 /**
 669  * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command.
 670  * @adev: amdgpu_device pointer
 671  * @notify: dmub notification structure
 672  *
 673  * Dmub AUX or SET_CONFIG command completion processing callback
 674  * Copies dmub notification to DM which is to be read by AUX command.
 675  * issuing thread and also signals the event to wake up the thread.
 676  */
 677 static void dmub_aux_setconfig_callback(struct amdgpu_device *adev,
 678                                         struct dmub_notification *notify)
 679 {
 680         if (adev->dm.dmub_notify)
 681                 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification));
 682         if (notify->type == DMUB_NOTIFICATION_AUX_REPLY)
 683                 complete(&adev->dm.dmub_aux_transfer_done);
 684 }
 685
 686 /**
 687  * dmub_hpd_callback - DMUB HPD interrupt processing callback.
 688  * @adev: amdgpu_device pointer
 689  * @notify: dmub notification structure
 690  *
 691  * Dmub Hpd interrupt processing callback. Gets displayindex through the
 692  * ink index and calls helper to do the processing.
 693  */
 694 static void dmub_hpd_callback(struct amdgpu_device *adev,
 695                               struct dmub_notification *notify)
 696 {
 697         struct amdgpu_dm_connector *aconnector;
 698         struct amdgpu_dm_connector *hpd_aconnector = NULL;
 699         struct drm_connector *connector;
 700         struct drm_connector_list_iter iter;
 701         struct dc_link *link;
 702         u8 link_index = 0;
 703         struct drm_device *dev;
 704
 705         if (adev == NULL)
 706                 return;
 707
 708         if (notify == NULL) {
 709                 DRM_ERROR("DMUB HPD callback notification was NULL");
 710                 return;
 711         }
 712
 713         if (notify->link_index > adev->dm.dc->link_count) {
 714                 DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index);
 715                 return;
 716         }
 717
 718         link_index = notify->link_index;
 719         link = adev->dm.dc->links[link_index];
 720         dev = adev->dm.ddev;
 721
 722         drm_connector_list_iter_begin(dev, &iter);
 723         drm_for_each_connector_iter(connector, &iter) {
 724                 aconnector = to_amdgpu_dm_connector(connector);
 725                 if (link && aconnector->dc_link == link) {
 726                         if (notify->type == DMUB_NOTIFICATION_HPD)
 727                                 DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index);
 728                         else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
 729                                 DRM_INFO("DMUB HPD IRQ callback: link_index=%u\n", link_index);
 730                         else
 731                                 DRM_WARN("DMUB Unknown HPD callback type %d, link_index=%u\n",
 732                                                 notify->type, link_index);
 733
 734                         hpd_aconnector = aconnector;
 735                         break;
 736                 }
 737         }
 738         drm_connector_list_iter_end(&iter);
 739
 740         if (hpd_aconnector) {
 741                 if (notify->type == DMUB_NOTIFICATION_HPD)
 742                         handle_hpd_irq_helper(hpd_aconnector);
 743                 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
 744                         handle_hpd_rx_irq(hpd_aconnector);
 745         }
 746 }
 747
 748 /**
 749  * register_dmub_notify_callback - Sets callback for DMUB notify
 750  * @adev: amdgpu_device pointer
 751  * @type: Type of dmub notification
 752  * @callback: Dmub interrupt callback function
 753  * @dmub_int_thread_offload: offload indicator
 754  *
 755  * API to register a dmub callback handler for a dmub notification
 756  * Also sets indicator whether callback processing to be offloaded.
 757  * to dmub interrupt handling thread
 758  * Return: true if successfully registered, false if there is existing registration
 759  */
 760 static bool register_dmub_notify_callback(struct amdgpu_device *adev,
 761                                           enum dmub_notification_type type,
 762                                           dmub_notify_interrupt_callback_t callback,
 763                                           bool dmub_int_thread_offload)
 764 {
 765         if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) {
 766                 adev->dm.dmub_callback[type] = callback;
 767                 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload;
 768         } else
 769                 return false;
 770
 771         return true;
 772 }
 773
 774 static void dm_handle_hpd_work(struct work_struct *work)
 775 {
 776         struct dmub_hpd_work *dmub_hpd_wrk;
 777
 778         dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work);
 779
 780         if (!dmub_hpd_wrk->dmub_notify) {
 781                 DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL");
 782                 return;
 783         }
 784
 785         if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) {
 786                 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev,
 787                 dmub_hpd_wrk->dmub_notify);
 788         }
 789
 790         kfree(dmub_hpd_wrk->dmub_notify);
 791         kfree(dmub_hpd_wrk);
 792
 793 }
 794
 795 #define DMUB_TRACE_MAX_READ 64
 796 /**
 797  * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt
 798  * @interrupt_params: used for determining the Outbox instance
 799  *
 800  * Handles the Outbox Interrupt
 801  * event handler.
 802  */
 803 static void dm_dmub_outbox1_low_irq(void *interrupt_params)
 804 {
 805         struct dmub_notification notify;
 806         struct common_irq_params *irq_params = interrupt_params;
 807         struct amdgpu_device *adev = irq_params->adev;
 808         struct amdgpu_display_manager *dm = &adev->dm;
 809         struct dmcub_trace_buf_entry entry = { 0 };
 810         u32 count = 0;
 811         struct dmub_hpd_work *dmub_hpd_wrk;
 812         struct dc_link *plink = NULL;
 813
 814         if (dc_enable_dmub_notifications(adev->dm.dc) &&
 815                 irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) {
 816
 817                 do {
 818                         dc_stat_get_dmub_notification(adev->dm.dc, &notify);
 819                         if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) {
 820                                 DRM_ERROR("DM: notify type %d invalid!", notify.type);
 821                                 continue;
 822                         }
 823                         if (!dm->dmub_callback[notify.type]) {
 824                                 DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type);
 825                                 continue;
 826                         }
 827                         if (dm->dmub_thread_offload[notify.type] == true) {
 828                                 dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC);
 829                                 if (!dmub_hpd_wrk) {
 830                                         DRM_ERROR("Failed to allocate dmub_hpd_wrk");
 831                                         return;
 832                                 }
 833                                 dmub_hpd_wrk->dmub_notify = kmemdup(&notify, sizeof(struct dmub_notification),
 834                                                                     GFP_ATOMIC);
 835                                 if (!dmub_hpd_wrk->dmub_notify) {
 836                                         kfree(dmub_hpd_wrk);
 837                                         DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify");
 838                                         return;
 839                                 }
 840                                 INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work);
 841                                 dmub_hpd_wrk->adev = adev;
 842                                 if (notify.type == DMUB_NOTIFICATION_HPD) {
 843                                         plink = adev->dm.dc->links[notify.link_index];
 844                                         if (plink) {
 845                                                 plink->hpd_status =
 846                                                         notify.hpd_status == DP_HPD_PLUG;
 847                                         }
 848                                 }
 849                                 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work);
 850                         } else {
 851                                 dm->dmub_callback[notify.type](adev, &notify);
 852                         }
 853                 } while (notify.pending_notification);
 854         }
 855
 856
 857         do {
 858                 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {
 859                         trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,
 860                                                         entry.param0, entry.param1);
 861
 862                         DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",
 863                                  entry.trace_code, entry.tick_count, entry.param0, entry.param1);
 864                 } else
 865                         break;
 866
 867                 count++;
 868
 869         } while (count <= DMUB_TRACE_MAX_READ);
 870
 871         if (count > DMUB_TRACE_MAX_READ)
 872                 DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ");
 873 }
 874
 875 static int dm_set_clockgating_state(void *handle,
 876                   enum amd_clockgating_state state)
 877 {
 878         return 0;
 879 }
 880
 881 static int dm_set_powergating_state(void *handle,
 882                   enum amd_powergating_state state)
 883 {
 884         return 0;
 885 }
 886
 887 /* Prototypes of private functions */
 888 static int dm_early_init(void *handle);
 889
 890 /* Allocate memory for FBC compressed data  */
 891 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
 892 {
 893         struct drm_device *dev = connector->dev;
 894         struct amdgpu_device *adev = drm_to_adev(dev);
 895         struct dm_compressor_info *compressor = &adev->dm.compressor;
 896         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
 897         struct drm_display_mode *mode;
 898         unsigned long max_size = 0;
 899
 900         if (adev->dm.dc->fbc_compressor == NULL)
 901                 return;
 902
 903         if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
 904                 return;
 905
 906         if (compressor->bo_ptr)
 907                 return;
 908
 909
 910         list_for_each_entry(mode, &connector->modes, head) {
 911                 if (max_size < mode->htotal * mode->vtotal)
 912                         max_size = mode->htotal * mode->vtotal;
 913         }
 914
 915         if (max_size) {
 916                 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
 917                             AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
 918                             &compressor->gpu_addr, &compressor->cpu_addr);
 919
 920                 if (r)
 921                         DRM_ERROR("DM: Failed to initialize FBC\n");
 922                 else {
 923                         adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
 924                         DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
 925                 }
 926
 927         }
 928
 929 }
 930
 931 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
 932                                           int pipe, bool *enabled,
 933                                           unsigned char *buf, int max_bytes)
 934 {
 935         struct drm_device *dev = dev_get_drvdata(kdev);
 936         struct amdgpu_device *adev = drm_to_adev(dev);
 937         struct drm_connector *connector;
 938         struct drm_connector_list_iter conn_iter;
 939         struct amdgpu_dm_connector *aconnector;
 940         int ret = 0;
 941
 942         *enabled = false;
 943
 944         mutex_lock(&adev->dm.audio_lock);
 945
 946         drm_connector_list_iter_begin(dev, &conn_iter);
 947         drm_for_each_connector_iter(connector, &conn_iter) {
 948                 aconnector = to_amdgpu_dm_connector(connector);
 949                 if (aconnector->audio_inst != port)
 950                         continue;
 951
 952                 *enabled = true;
 953                 ret = drm_eld_size(connector->eld);
 954                 memcpy(buf, connector->eld, min(max_bytes, ret));
 955
 956                 break;
 957         }
 958         drm_connector_list_iter_end(&conn_iter);
 959
 960         mutex_unlock(&adev->dm.audio_lock);
 961
 962         DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
 963
 964         return ret;
 965 }
 966
 967 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
 968         .get_eld = amdgpu_dm_audio_component_get_eld,
 969 };
 970
 971 static int amdgpu_dm_audio_component_bind(struct device *kdev,
 972                                        struct device *hda_kdev, void *data)
 973 {
 974         struct drm_device *dev = dev_get_drvdata(kdev);
 975         struct amdgpu_device *adev = drm_to_adev(dev);
 976         struct drm_audio_component *acomp = data;
 977
 978         acomp->ops = &amdgpu_dm_audio_component_ops;
 979         acomp->dev = kdev;
 980         adev->dm.audio_component = acomp;
 981
 982         return 0;
 983 }
 984
 985 static void amdgpu_dm_audio_component_unbind(struct device *kdev,
 986                                           struct device *hda_kdev, void *data)
 987 {
 988         struct drm_device *dev = dev_get_drvdata(kdev);
 989         struct amdgpu_device *adev = drm_to_adev(dev);
 990         struct drm_audio_component *acomp = data;
 991
 992         acomp->ops = NULL;
 993         acomp->dev = NULL;
 994         adev->dm.audio_component = NULL;
 995 }
 996
 997 static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
 998         .bind   = amdgpu_dm_audio_component_bind,
 999         .unbind = amdgpu_dm_audio_component_unbind,
1000 };
1001
1002 static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
1003 {
1004         int i, ret;
1005
1006         if (!amdgpu_audio)
1007                 return 0;
1008
1009         adev->mode_info.audio.enabled = true;
1010
1011         adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
1012
1013         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1014                 adev->mode_info.audio.pin[i].channels = -1;
1015                 adev->mode_info.audio.pin[i].rate = -1;
1016                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1017                 adev->mode_info.audio.pin[i].status_bits = 0;
1018                 adev->mode_info.audio.pin[i].category_code = 0;
1019                 adev->mode_info.audio.pin[i].connected = false;
1020                 adev->mode_info.audio.pin[i].id =
1021                         adev->dm.dc->res_pool->audios[i]->inst;
1022                 adev->mode_info.audio.pin[i].offset = 0;
1023         }
1024
1025         ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1026         if (ret < 0)
1027                 return ret;
1028
1029         adev->dm.audio_registered = true;
1030
1031         return 0;
1032 }
1033
1034 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
1035 {
1036         if (!amdgpu_audio)
1037                 return;
1038
1039         if (!adev->mode_info.audio.enabled)
1040                 return;
1041
1042         if (adev->dm.audio_registered) {
1043                 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1044                 adev->dm.audio_registered = false;
1045         }
1046
1047         /* TODO: Disable audio? */
1048
1049         adev->mode_info.audio.enabled = false;
1050 }
1051
1052 static  void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
1053 {
1054         struct drm_audio_component *acomp = adev->dm.audio_component;
1055
1056         if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
1057                 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
1058
1059                 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
1060                                                  pin, -1);
1061         }
1062 }
1063
1064 static int dm_dmub_hw_init(struct amdgpu_device *adev)
1065 {
1066         const struct dmcub_firmware_header_v1_0 *hdr;
1067         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1068         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
1069         const struct firmware *dmub_fw = adev->dm.dmub_fw;
1070         struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
1071         struct abm *abm = adev->dm.dc->res_pool->abm;
1072         struct dmub_srv_hw_params hw_params;
1073         enum dmub_status status;
1074         const unsigned char *fw_inst_const, *fw_bss_data;
1075         u32 i, fw_inst_const_size, fw_bss_data_size;
1076         bool has_hw_support;
1077
1078         if (!dmub_srv)
1079                 /* DMUB isn't supported on the ASIC. */
1080                 return 0;
1081
1082         if (!fb_info) {
1083                 DRM_ERROR("No framebuffer info for DMUB service.\n");
1084                 return -EINVAL;
1085         }
1086
1087         if (!dmub_fw) {
1088                 /* Firmware required for DMUB support. */
1089                 DRM_ERROR("No firmware provided for DMUB.\n");
1090                 return -EINVAL;
1091         }
1092
1093         status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
1094         if (status != DMUB_STATUS_OK) {
1095                 DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
1096                 return -EINVAL;
1097         }
1098
1099         if (!has_hw_support) {
1100                 DRM_INFO("DMUB unsupported on ASIC\n");
1101                 return 0;
1102         }
1103
1104         /* Reset DMCUB if it was previously running - before we overwrite its memory. */
1105         status = dmub_srv_hw_reset(dmub_srv);
1106         if (status != DMUB_STATUS_OK)
1107                 DRM_WARN("Error resetting DMUB HW: %d\n", status);
1108
1109         hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
1110
1111         fw_inst_const = dmub_fw->data +
1112                         le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1113                         PSP_HEADER_BYTES;
1114
1115         fw_bss_data = dmub_fw->data +
1116                       le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1117                       le32_to_cpu(hdr->inst_const_bytes);
1118
1119         /* Copy firmware and bios info into FB memory. */
1120         fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
1121                              PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
1122
1123         fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
1124
1125         /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP,
1126          * amdgpu_ucode_init_single_fw will load dmub firmware
1127          * fw_inst_const part to cw0; otherwise, the firmware back door load
1128          * will be done by dm_dmub_hw_init
1129          */
1130         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1131                 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
1132                                 fw_inst_const_size);
1133         }
1134
1135         if (fw_bss_data_size)
1136                 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr,
1137                        fw_bss_data, fw_bss_data_size);
1138
1139         /* Copy firmware bios info into FB memory. */
1140         memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,
1141                adev->bios_size);
1142
1143         /* Reset regions that need to be reset. */
1144         memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,
1145         fb_info->fb[DMUB_WINDOW_4_MAILBOX].size);
1146
1147         memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,
1148                fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size);
1149
1150         memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,
1151                fb_info->fb[DMUB_WINDOW_6_FW_STATE].size);
1152
1153         /* Initialize hardware. */
1154         memset(&hw_params, 0, sizeof(hw_params));
1155         hw_params.fb_base = adev->gmc.fb_start;
1156         hw_params.fb_offset = adev->vm_manager.vram_base_offset;
1157
1158         /* backdoor load firmware and trigger dmub running */
1159         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
1160                 hw_params.load_inst_const = true;
1161
1162         if (dmcu)
1163                 hw_params.psp_version = dmcu->psp_version;
1164
1165         for (i = 0; i < fb_info->num_fb; ++i)
1166                 hw_params.fb[i] = &fb_info->fb[i];
1167
1168         switch (adev->ip_versions[DCE_HWIP][0]) {
1169         case IP_VERSION(3, 1, 3):
1170         case IP_VERSION(3, 1, 4):
1171                 hw_params.dpia_supported = true;
1172                 hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia;
1173                 break;
1174         default:
1175                 break;
1176         }
1177
1178         status = dmub_srv_hw_init(dmub_srv, &hw_params);
1179         if (status != DMUB_STATUS_OK) {
1180                 DRM_ERROR("Error initializing DMUB HW: %d\n", status);
1181                 return -EINVAL;
1182         }
1183
1184         /* Wait for firmware load to finish. */
1185         status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1186         if (status != DMUB_STATUS_OK)
1187                 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1188
1189         /* Init DMCU and ABM if available. */
1190         if (dmcu && abm) {
1191                 dmcu->funcs->dmcu_init(dmcu);
1192                 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
1193         }
1194
1195         if (!adev->dm.dc->ctx->dmub_srv)
1196                 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
1197         if (!adev->dm.dc->ctx->dmub_srv) {
1198                 DRM_ERROR("Couldn't allocate DC DMUB server!\n");
1199                 return -ENOMEM;
1200         }
1201
1202         DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
1203                  adev->dm.dmcub_fw_version);
1204
1205         return 0;
1206 }
1207
1208 static void dm_dmub_hw_resume(struct amdgpu_device *adev)
1209 {
1210         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1211         enum dmub_status status;
1212         bool init;
1213
1214         if (!dmub_srv) {
1215                 /* DMUB isn't supported on the ASIC. */
1216                 return;
1217         }
1218
1219         status = dmub_srv_is_hw_init(dmub_srv, &init);
1220         if (status != DMUB_STATUS_OK)
1221                 DRM_WARN("DMUB hardware init check failed: %d\n", status);
1222
1223         if (status == DMUB_STATUS_OK && init) {
1224                 /* Wait for firmware load to finish. */
1225                 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1226                 if (status != DMUB_STATUS_OK)
1227                         DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1228         } else {
1229                 /* Perform the full hardware initialization. */
1230                 dm_dmub_hw_init(adev);
1231         }
1232 }
1233
1234 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
1235 {
1236         u64 pt_base;
1237         u32 logical_addr_low;
1238         u32 logical_addr_high;
1239         u32 agp_base, agp_bot, agp_top;
1240         PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;
1241
1242         memset(pa_config, 0, sizeof(*pa_config));
1243
1244         agp_base = 0;
1245         agp_bot = adev->gmc.agp_start >> 24;
1246         agp_top = adev->gmc.agp_end >> 24;
1247
1248         /* AGP aperture is disabled */
1249         if (agp_bot == agp_top) {
1250                 logical_addr_low = adev->gmc.fb_start >> 18;
1251                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1252                         /*
1253                          * Raven2 has a HW issue that it is unable to use the vram which
1254                          * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1255                          * workaround that increase system aperture high address (add 1)
1256                          * to get rid of the VM fault and hardware hang.
1257                          */
1258                         logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1;
1259                 else
1260                         logical_addr_high = adev->gmc.fb_end >> 18;
1261         } else {
1262                 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
1263                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1264                         /*
1265                          * Raven2 has a HW issue that it is unable to use the vram which
1266                          * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1267                          * workaround that increase system aperture high address (add 1)
1268                          * to get rid of the VM fault and hardware hang.
1269                          */
1270                         logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
1271                 else
1272                         logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
1273         }
1274
1275         pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
1276
1277         page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF;
1278         page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12);
1279         page_table_end.high_part = (u32)(adev->gmc.gart_end >> 44) & 0xF;
1280         page_table_end.low_part = (u32)(adev->gmc.gart_end >> 12);
1281         page_table_base.high_part = upper_32_bits(pt_base) & 0xF;
1282         page_table_base.low_part = lower_32_bits(pt_base);
1283
1284         pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
1285         pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18;
1286
1287         pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24;
1288         pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24;
1289         pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24;
1290
1291         pa_config->system_aperture.fb_base = adev->gmc.fb_start;
1292         pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset;
1293         pa_config->system_aperture.fb_top = adev->gmc.fb_end;
1294
1295         pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12;
1296         pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12;
1297         pa_config->gart_config.page_table_base_addr = page_table_base.quad_part;
1298
1299         pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support;
1300
1301 }
1302
1303 static void force_connector_state(
1304         struct amdgpu_dm_connector *aconnector,
1305         enum drm_connector_force force_state)
1306 {
1307         struct drm_connector *connector = &aconnector->base;
1308
1309         mutex_lock(&connector->dev->mode_config.mutex);
1310         aconnector->base.force = force_state;
1311         mutex_unlock(&connector->dev->mode_config.mutex);
1312
1313         mutex_lock(&aconnector->hpd_lock);
1314         drm_kms_helper_connector_hotplug_event(connector);
1315         mutex_unlock(&aconnector->hpd_lock);
1316 }
1317
1318 static void dm_handle_hpd_rx_offload_work(struct work_struct *work)
1319 {
1320         struct hpd_rx_irq_offload_work *offload_work;
1321         struct amdgpu_dm_connector *aconnector;
1322         struct dc_link *dc_link;
1323         struct amdgpu_device *adev;
1324         enum dc_connection_type new_connection_type = dc_connection_none;
1325         unsigned long flags;
1326         union test_response test_response;
1327
1328         memset(&test_response, 0, sizeof(test_response));
1329
1330         offload_work = container_of(work, struct hpd_rx_irq_offload_work, work);
1331         aconnector = offload_work->offload_wq->aconnector;
1332
1333         if (!aconnector) {
1334                 DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work");
1335                 goto skip;
1336         }
1337
1338         adev = drm_to_adev(aconnector->base.dev);
1339         dc_link = aconnector->dc_link;
1340
1341         mutex_lock(&aconnector->hpd_lock);
1342         if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
1343                 DRM_ERROR("KMS: Failed to detect connector\n");
1344         mutex_unlock(&aconnector->hpd_lock);
1345
1346         if (new_connection_type == dc_connection_none)
1347                 goto skip;
1348
1349         if (amdgpu_in_reset(adev))
1350                 goto skip;
1351
1352         if (offload_work->data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
1353                 offload_work->data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
1354                 dm_handle_mst_sideband_msg_ready_event(&aconnector->mst_mgr, DOWN_OR_UP_MSG_RDY_EVENT);
1355                 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1356                 offload_work->offload_wq->is_handling_mst_msg_rdy_event = false;
1357                 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1358                 goto skip;
1359         }
1360
1361         mutex_lock(&adev->dm.dc_lock);
1362         if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
1363                 dc_link_dp_handle_automated_test(dc_link);
1364
1365                 if (aconnector->timing_changed) {
1366                         /* force connector disconnect and reconnect */
1367                         force_connector_state(aconnector, DRM_FORCE_OFF);
1368                         msleep(100);
1369                         force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED);
1370                 }
1371
1372                 test_response.bits.ACK = 1;
1373
1374                 core_link_write_dpcd(
1375                 dc_link,
1376                 DP_TEST_RESPONSE,
1377                 &test_response.raw,
1378                 sizeof(test_response));
1379         } else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) &&
1380                         dc_link_check_link_loss_status(dc_link, &offload_work->data) &&
1381                         dc_link_dp_allow_hpd_rx_irq(dc_link)) {
1382                 /* offload_work->data is from handle_hpd_rx_irq->
1383                  * schedule_hpd_rx_offload_work.this is defer handle
1384                  * for hpd short pulse. upon here, link status may be
1385                  * changed, need get latest link status from dpcd
1386                  * registers. if link status is good, skip run link
1387                  * training again.
1388                  */
1389                 union hpd_irq_data irq_data;
1390
1391                 memset(&irq_data, 0, sizeof(irq_data));
1392
1393                 /* before dc_link_dp_handle_link_loss, allow new link lost handle
1394                  * request be added to work queue if link lost at end of dc_link_
1395                  * dp_handle_link_loss
1396                  */
1397                 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1398                 offload_work->offload_wq->is_handling_link_loss = false;
1399                 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1400
1401                 if ((dc_link_dp_read_hpd_rx_irq_data(dc_link, &irq_data) == DC_OK) &&
1402                         dc_link_check_link_loss_status(dc_link, &irq_data))
1403                         dc_link_dp_handle_link_loss(dc_link);
1404         }
1405         mutex_unlock(&adev->dm.dc_lock);
1406
1407 skip:
1408         kfree(offload_work);
1409
1410 }
1411
1412 static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc)
1413 {
1414         int max_caps = dc->caps.max_links;
1415         int i = 0;
1416         struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL;
1417
1418         hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL);
1419
1420         if (!hpd_rx_offload_wq)
1421                 return NULL;
1422
1423
1424         for (i = 0; i < max_caps; i++) {
1425                 hpd_rx_offload_wq[i].wq =
1426                                     create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq");
1427
1428                 if (hpd_rx_offload_wq[i].wq == NULL) {
1429                         DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!");
1430                         goto out_err;
1431                 }
1432
1433                 spin_lock_init(&hpd_rx_offload_wq[i].offload_lock);
1434         }
1435
1436         return hpd_rx_offload_wq;
1437
1438 out_err:
1439         for (i = 0; i < max_caps; i++) {
1440                 if (hpd_rx_offload_wq[i].wq)
1441                         destroy_workqueue(hpd_rx_offload_wq[i].wq);
1442         }
1443         kfree(hpd_rx_offload_wq);
1444         return NULL;
1445 }
1446
1447 struct amdgpu_stutter_quirk {
1448         u16 chip_vendor;
1449         u16 chip_device;
1450         u16 subsys_vendor;
1451         u16 subsys_device;
1452         u8 revision;
1453 };
1454
1455 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = {
1456         /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */
1457         { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },
1458         { 0, 0, 0, 0, 0 },
1459 };
1460
1461 static bool dm_should_disable_stutter(struct pci_dev *pdev)
1462 {
1463         const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list;
1464
1465         while (p && p->chip_device != 0) {
1466                 if (pdev->vendor == p->chip_vendor &&
1467                     pdev->device == p->chip_device &&
1468                     pdev->subsystem_vendor == p->subsys_vendor &&
1469                     pdev->subsystem_device == p->subsys_device &&
1470                     pdev->revision == p->revision) {
1471                         return true;
1472                 }
1473                 ++p;
1474         }
1475         return false;
1476 }
1477
1478 static const struct dmi_system_id hpd_disconnect_quirk_table[] = {
1479         {
1480                 .matches = {
1481                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1482                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"),
1483                 },
1484         },
1485         {
1486                 .matches = {
1487                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1488                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"),
1489                 },
1490         },
1491         {
1492                 .matches = {
1493                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1494                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"),
1495                 },
1496         },
1497         {
1498                 .matches = {
1499                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1500                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"),
1501                 },
1502         },
1503         {
1504                 .matches = {
1505                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1506                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"),
1507                 },
1508         },
1509         {
1510                 .matches = {
1511                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1512                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"),
1513                 },
1514         },
1515         {
1516                 .matches = {
1517                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1518                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"),
1519                 },
1520         },
1521         {
1522                 .matches = {
1523                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1524                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"),
1525                 },
1526         },
1527         {
1528                 .matches = {
1529                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1530                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"),
1531                 },
1532         },
1533         {}
1534         /* TODO: refactor this from a fixed table to a dynamic option */
1535 };
1536
1537 static void retrieve_dmi_info(struct amdgpu_display_manager *dm)
1538 {
1539         const struct dmi_system_id *dmi_id;
1540
1541         dm->aux_hpd_discon_quirk = false;
1542
1543         dmi_id = dmi_first_match(hpd_disconnect_quirk_table);
1544         if (dmi_id) {
1545                 dm->aux_hpd_discon_quirk = true;
1546                 DRM_INFO("aux_hpd_discon_quirk attached\n");
1547         }
1548 }
1549
1550 static int amdgpu_dm_init(struct amdgpu_device *adev)
1551 {
1552         struct dc_init_data init_data;
1553         struct dc_callback_init init_params;
1554         int r;
1555
1556         adev->dm.ddev = adev_to_drm(adev);
1557         adev->dm.adev = adev;
1558
1559         /* Zero all the fields */
1560         memset(&init_data, 0, sizeof(init_data));
1561         memset(&init_params, 0, sizeof(init_params));
1562
1563         mutex_init(&adev->dm.dpia_aux_lock);
1564         mutex_init(&adev->dm.dc_lock);
1565         mutex_init(&adev->dm.audio_lock);
1566
1567         if (amdgpu_dm_irq_init(adev)) {
1568                 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
1569                 goto error;
1570         }
1571
1572         init_data.asic_id.chip_family = adev->family;
1573
1574         init_data.asic_id.pci_revision_id = adev->pdev->revision;
1575         init_data.asic_id.hw_internal_rev = adev->external_rev_id;
1576         init_data.asic_id.chip_id = adev->pdev->device;
1577
1578         init_data.asic_id.vram_width = adev->gmc.vram_width;
1579         /* TODO: initialize init_data.asic_id.vram_type here!!!! */
1580         init_data.asic_id.atombios_base_address =
1581                 adev->mode_info.atom_context->bios;
1582
1583         init_data.driver = adev;
1584
1585         adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
1586
1587         if (!adev->dm.cgs_device) {
1588                 DRM_ERROR("amdgpu: failed to create cgs device.\n");
1589                 goto error;
1590         }
1591
1592         init_data.cgs_device = adev->dm.cgs_device;
1593
1594         init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
1595
1596         switch (adev->ip_versions[DCE_HWIP][0]) {
1597         case IP_VERSION(2, 1, 0):
1598                 switch (adev->dm.dmcub_fw_version) {
1599                 case 0: /* development */
1600                 case 0x1: /* linux-firmware.git hash 6d9f399 */
1601                 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */
1602                         init_data.flags.disable_dmcu = false;
1603                         break;
1604                 default:
1605                         init_data.flags.disable_dmcu = true;
1606                 }
1607                 break;
1608         case IP_VERSION(2, 0, 3):
1609                 init_data.flags.disable_dmcu = true;
1610                 break;
1611         default:
1612                 break;
1613         }
1614
1615         switch (adev->asic_type) {
1616         case CHIP_CARRIZO:
1617         case CHIP_STONEY:
1618                 init_data.flags.gpu_vm_support = true;
1619                 break;
1620         default:
1621                 switch (adev->ip_versions[DCE_HWIP][0]) {
1622                 case IP_VERSION(1, 0, 0):
1623                 case IP_VERSION(1, 0, 1):
1624                         /* enable S/G on PCO and RV2 */
1625                         if ((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
1626                             (adev->apu_flags & AMD_APU_IS_PICASSO))
1627                                 init_data.flags.gpu_vm_support = true;
1628                         break;
1629                 case IP_VERSION(2, 1, 0):
1630                 case IP_VERSION(3, 0, 1):
1631                 case IP_VERSION(3, 1, 2):
1632                 case IP_VERSION(3, 1, 3):
1633                 case IP_VERSION(3, 1, 4):
1634                 case IP_VERSION(3, 1, 5):
1635                 case IP_VERSION(3, 1, 6):
1636                         init_data.flags.gpu_vm_support = true;
1637                         break;
1638                 default:
1639                         break;
1640                 }
1641                 break;
1642         }
1643         if (init_data.flags.gpu_vm_support)
1644                 init_data.flags.gpu_vm_support = amdgpu_sg_display_supported(adev);
1645
1646         if (init_data.flags.gpu_vm_support)
1647                 adev->mode_info.gpu_vm_support = true;
1648
1649         if (amdgpu_dc_feature_mask & DC_FBC_MASK)
1650                 init_data.flags.fbc_support = true;
1651
1652         if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
1653                 init_data.flags.multi_mon_pp_mclk_switch = true;
1654
1655         if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
1656                 init_data.flags.disable_fractional_pwm = true;
1657
1658         if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING)
1659                 init_data.flags.edp_no_power_sequencing = true;
1660
1661         if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A)
1662                 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true;
1663         if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)
1664                 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;
1665
1666         init_data.flags.seamless_boot_edp_requested = false;
1667
1668         if (check_seamless_boot_capability(adev)) {
1669                 init_data.flags.seamless_boot_edp_requested = true;
1670                 init_data.flags.allow_seamless_boot_optimization = true;
1671                 DRM_INFO("Seamless boot condition check passed\n");
1672         }
1673
1674         init_data.flags.enable_mipi_converter_optimization = true;
1675
1676         init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];
1677         init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];
1678
1679         INIT_LIST_HEAD(&adev->dm.da_list);
1680
1681         retrieve_dmi_info(&adev->dm);
1682
1683         /* Display Core create. */
1684         adev->dm.dc = dc_create(&init_data);
1685
1686         if (adev->dm.dc) {
1687                 DRM_INFO("Display Core v%s initialized on %s\n", DC_VER,
1688                          dce_version_to_string(adev->dm.dc->ctx->dce_version));
1689         } else {
1690                 DRM_INFO("Display Core v%s failed to initialize on %s\n", DC_VER,
1691                          dce_version_to_string(adev->dm.dc->ctx->dce_version));
1692                 goto error;
1693         }
1694
1695         if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
1696                 adev->dm.dc->debug.force_single_disp_pipe_split = false;
1697                 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
1698         }
1699
1700         if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
1701                 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
1702         if (dm_should_disable_stutter(adev->pdev))
1703                 adev->dm.dc->debug.disable_stutter = true;
1704
1705         if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
1706                 adev->dm.dc->debug.disable_stutter = true;
1707
1708         if (amdgpu_dc_debug_mask & DC_DISABLE_DSC)
1709                 adev->dm.dc->debug.disable_dsc = true;
1710
1711         if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
1712                 adev->dm.dc->debug.disable_clock_gate = true;
1713
1714         if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH)
1715                 adev->dm.dc->debug.force_subvp_mclk_switch = true;
1716
1717         adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm;
1718
1719         /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */
1720         adev->dm.dc->debug.ignore_cable_id = true;
1721
1722         /* TODO: There is a new drm mst change where the freedom of
1723          * vc_next_start_slot update is revoked/moved into drm, instead of in
1724          * driver. This forces us to make sure to get vc_next_start_slot updated
1725          * in drm function each time without considering if mst_state is active
1726          * or not. Otherwise, next time hotplug will give wrong start_slot
1727          * number. We are implementing a temporary solution to even notify drm
1728          * mst deallocation when link is no longer of MST type when uncommitting
1729          * the stream so we will have more time to work on a proper solution.
1730          * Ideally when dm_helpers_dp_mst_stop_top_mgr message is triggered, we
1731          * should notify drm to do a complete "reset" of its states and stop
1732          * calling further drm mst functions when link is no longer of an MST
1733          * type. This could happen when we unplug an MST hubs/displays. When
1734          * uncommit stream comes later after unplug, we should just reset
1735          * hardware states only.
1736          */
1737         adev->dm.dc->debug.temp_mst_deallocation_sequence = true;
1738
1739         if (adev->dm.dc->caps.dp_hdmi21_pcon_support)
1740                 DRM_INFO("DP-HDMI FRL PCON supported\n");
1741
1742         r = dm_dmub_hw_init(adev);
1743         if (r) {
1744                 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
1745                 goto error;
1746         }
1747
1748         dc_hardware_init(adev->dm.dc);
1749
1750         adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc);
1751         if (!adev->dm.hpd_rx_offload_wq) {
1752                 DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n");
1753                 goto error;
1754         }
1755
1756         if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) {
1757                 struct dc_phy_addr_space_config pa_config;
1758
1759                 mmhub_read_system_context(adev, &pa_config);
1760
1761                 // Call the DC init_memory func
1762                 dc_setup_system_context(adev->dm.dc, &pa_config);
1763         }
1764
1765         adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
1766         if (!adev->dm.freesync_module) {
1767                 DRM_ERROR(
1768                 "amdgpu: failed to initialize freesync_module.\n");
1769         } else
1770                 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
1771                                 adev->dm.freesync_module);
1772
1773         amdgpu_dm_init_color_mod();
1774
1775         if (adev->dm.dc->caps.max_links > 0) {
1776                 adev->dm.vblank_control_workqueue =
1777                         create_singlethread_workqueue("dm_vblank_control_workqueue");
1778                 if (!adev->dm.vblank_control_workqueue)
1779                         DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n");
1780         }
1781
1782         if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
1783                 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
1784
1785                 if (!adev->dm.hdcp_workqueue)
1786                         DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
1787                 else
1788                         DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
1789
1790                 dc_init_callbacks(adev->dm.dc, &init_params);
1791         }
1792         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
1793                 init_completion(&adev->dm.dmub_aux_transfer_done);
1794                 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL);
1795                 if (!adev->dm.dmub_notify) {
1796                         DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify");
1797                         goto error;
1798                 }
1799
1800                 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq");
1801                 if (!adev->dm.delayed_hpd_wq) {
1802                         DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n");
1803                         goto error;
1804                 }
1805
1806                 amdgpu_dm_outbox_init(adev);
1807                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY,
1808                         dmub_aux_setconfig_callback, false)) {
1809                         DRM_ERROR("amdgpu: fail to register dmub aux callback");
1810                         goto error;
1811                 }
1812                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true)) {
1813                         DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1814                         goto error;
1815                 }
1816                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true)) {
1817                         DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1818                         goto error;
1819                 }
1820         }
1821
1822         /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive.
1823          * It is expected that DMUB will resend any pending notifications at this point, for
1824          * example HPD from DPIA.
1825          */
1826         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
1827                 dc_enable_dmub_outbox(adev->dm.dc);
1828
1829                 /* DPIA trace goes to dmesg logs only if outbox is enabled */
1830                 if (amdgpu_dc_debug_mask & DC_ENABLE_DPIA_TRACE)
1831                         dc_dmub_srv_enable_dpia_trace(adev->dm.dc);
1832         }
1833
1834         if (amdgpu_dm_initialize_drm_device(adev)) {
1835                 DRM_ERROR(
1836                 "amdgpu: failed to initialize sw for display support.\n");
1837                 goto error;
1838         }
1839
1840         /* create fake encoders for MST */
1841         dm_dp_create_fake_mst_encoders(adev);
1842
1843         /* TODO: Add_display_info? */
1844
1845         /* TODO use dynamic cursor width */
1846         adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
1847         adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
1848
1849         if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
1850                 DRM_ERROR(
1851                 "amdgpu: failed to initialize sw for display support.\n");
1852                 goto error;
1853         }
1854
1855 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1856         adev->dm.secure_display_ctxs = amdgpu_dm_crtc_secure_display_create_contexts(adev);
1857         if (!adev->dm.secure_display_ctxs)
1858                 DRM_ERROR("amdgpu: failed to initialize secure display contexts.\n");
1859 #endif
1860
1861         DRM_DEBUG_DRIVER("KMS initialized.\n");
1862
1863         return 0;
1864 error:
1865         amdgpu_dm_fini(adev);
1866
1867         return -EINVAL;
1868 }
1869
1870 static int amdgpu_dm_early_fini(void *handle)
1871 {
1872         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1873
1874         amdgpu_dm_audio_fini(adev);
1875
1876         return 0;
1877 }
1878
1879 static void amdgpu_dm_fini(struct amdgpu_device *adev)
1880 {
1881         int i;
1882
1883         if (adev->dm.vblank_control_workqueue) {
1884                 destroy_workqueue(adev->dm.vblank_control_workqueue);
1885                 adev->dm.vblank_control_workqueue = NULL;
1886         }
1887
1888         amdgpu_dm_destroy_drm_device(&adev->dm);
1889
1890 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1891         if (adev->dm.secure_display_ctxs) {
1892                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1893                         if (adev->dm.secure_display_ctxs[i].crtc) {
1894                                 flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work);
1895                                 flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work);
1896                         }
1897                 }
1898                 kfree(adev->dm.secure_display_ctxs);
1899                 adev->dm.secure_display_ctxs = NULL;
1900         }
1901 #endif
1902         if (adev->dm.hdcp_workqueue) {
1903                 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue);
1904                 adev->dm.hdcp_workqueue = NULL;
1905         }
1906
1907         if (adev->dm.dc)
1908                 dc_deinit_callbacks(adev->dm.dc);
1909
1910         if (adev->dm.dc)
1911                 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
1912
1913         if (dc_enable_dmub_notifications(adev->dm.dc)) {
1914                 kfree(adev->dm.dmub_notify);
1915                 adev->dm.dmub_notify = NULL;
1916                 destroy_workqueue(adev->dm.delayed_hpd_wq);
1917                 adev->dm.delayed_hpd_wq = NULL;
1918         }
1919
1920         if (adev->dm.dmub_bo)
1921                 amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
1922                                       &adev->dm.dmub_bo_gpu_addr,
1923                                       &adev->dm.dmub_bo_cpu_addr);
1924
1925         if (adev->dm.hpd_rx_offload_wq) {
1926                 for (i = 0; i < adev->dm.dc->caps.max_links; i++) {
1927                         if (adev->dm.hpd_rx_offload_wq[i].wq) {
1928                                 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq);
1929                                 adev->dm.hpd_rx_offload_wq[i].wq = NULL;
1930                         }
1931                 }
1932
1933                 kfree(adev->dm.hpd_rx_offload_wq);
1934                 adev->dm.hpd_rx_offload_wq = NULL;
1935         }
1936
1937         /* DC Destroy TODO: Replace destroy DAL */
1938         if (adev->dm.dc)
1939                 dc_destroy(&adev->dm.dc);
1940         /*
1941          * TODO: pageflip, vlank interrupt
1942          *
1943          * amdgpu_dm_irq_fini(adev);
1944          */
1945
1946         if (adev->dm.cgs_device) {
1947                 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
1948                 adev->dm.cgs_device = NULL;
1949         }
1950         if (adev->dm.freesync_module) {
1951                 mod_freesync_destroy(adev->dm.freesync_module);
1952                 adev->dm.freesync_module = NULL;
1953         }
1954
1955         mutex_destroy(&adev->dm.audio_lock);
1956         mutex_destroy(&adev->dm.dc_lock);
1957         mutex_destroy(&adev->dm.dpia_aux_lock);
1958 }
1959
1960 static int load_dmcu_fw(struct amdgpu_device *adev)
1961 {
1962         const char *fw_name_dmcu = NULL;
1963         int r;
1964         const struct dmcu_firmware_header_v1_0 *hdr;
1965
1966         switch (adev->asic_type) {
1967 #if defined(CONFIG_DRM_AMD_DC_SI)
1968         case CHIP_TAHITI:
1969         case CHIP_PITCAIRN:
1970         case CHIP_VERDE:
1971         case CHIP_OLAND:
1972 #endif
1973         case CHIP_BONAIRE:
1974         case CHIP_HAWAII:
1975         case CHIP_KAVERI:
1976         case CHIP_KABINI:
1977         case CHIP_MULLINS:
1978         case CHIP_TONGA:
1979         case CHIP_FIJI:
1980         case CHIP_CARRIZO:
1981         case CHIP_STONEY:
1982         case CHIP_POLARIS11:
1983         case CHIP_POLARIS10:
1984         case CHIP_POLARIS12:
1985         case CHIP_VEGAM:
1986         case CHIP_VEGA10:
1987         case CHIP_VEGA12:
1988         case CHIP_VEGA20:
1989                 return 0;
1990         case CHIP_NAVI12:
1991                 fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
1992                 break;
1993         case CHIP_RAVEN:
1994                 if (ASICREV_IS_PICASSO(adev->external_rev_id))
1995                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1996                 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
1997                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1998                 else
1999                         return 0;
2000                 break;
2001         default:
2002                 switch (adev->ip_versions[DCE_HWIP][0]) {
2003                 case IP_VERSION(2, 0, 2):
2004                 case IP_VERSION(2, 0, 3):
2005                 case IP_VERSION(2, 0, 0):
2006                 case IP_VERSION(2, 1, 0):
2007                 case IP_VERSION(3, 0, 0):
2008                 case IP_VERSION(3, 0, 2):
2009                 case IP_VERSION(3, 0, 3):
2010                 case IP_VERSION(3, 0, 1):
2011                 case IP_VERSION(3, 1, 2):
2012                 case IP_VERSION(3, 1, 3):
2013                 case IP_VERSION(3, 1, 4):
2014                 case IP_VERSION(3, 1, 5):
2015                 case IP_VERSION(3, 1, 6):
2016                 case IP_VERSION(3, 2, 0):
2017                 case IP_VERSION(3, 2, 1):
2018                         return 0;
2019                 default:
2020                         break;
2021                 }
2022                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2023                 return -EINVAL;
2024         }
2025
2026         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2027                 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
2028                 return 0;
2029         }
2030
2031         r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, fw_name_dmcu);
2032         if (r == -ENODEV) {
2033                 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
2034                 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
2035                 adev->dm.fw_dmcu = NULL;
2036                 return 0;
2037         }
2038         if (r) {
2039                 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
2040                         fw_name_dmcu);
2041                 amdgpu_ucode_release(&adev->dm.fw_dmcu);
2042                 return r;
2043         }
2044
2045         hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
2046         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
2047         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
2048         adev->firmware.fw_size +=
2049                 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2050
2051         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
2052         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
2053         adev->firmware.fw_size +=
2054                 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2055
2056         adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
2057
2058         DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
2059
2060         return 0;
2061 }
2062
2063 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
2064 {
2065         struct amdgpu_device *adev = ctx;
2066
2067         return dm_read_reg(adev->dm.dc->ctx, address);
2068 }
2069
2070 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
2071                                      uint32_t value)
2072 {
2073         struct amdgpu_device *adev = ctx;
2074
2075         return dm_write_reg(adev->dm.dc->ctx, address, value);
2076 }
2077
2078 static int dm_dmub_sw_init(struct amdgpu_device *adev)
2079 {
2080         struct dmub_srv_create_params create_params;
2081         struct dmub_srv_region_params region_params;
2082         struct dmub_srv_region_info region_info;
2083         struct dmub_srv_fb_params fb_params;
2084         struct dmub_srv_fb_info *fb_info;
2085         struct dmub_srv *dmub_srv;
2086         const struct dmcub_firmware_header_v1_0 *hdr;
2087         enum dmub_asic dmub_asic;
2088         enum dmub_status status;
2089         int r;
2090
2091         switch (adev->ip_versions[DCE_HWIP][0]) {
2092         case IP_VERSION(2, 1, 0):
2093                 dmub_asic = DMUB_ASIC_DCN21;
2094                 break;
2095         case IP_VERSION(3, 0, 0):
2096                 dmub_asic = DMUB_ASIC_DCN30;
2097                 break;
2098         case IP_VERSION(3, 0, 1):
2099                 dmub_asic = DMUB_ASIC_DCN301;
2100                 break;
2101         case IP_VERSION(3, 0, 2):
2102                 dmub_asic = DMUB_ASIC_DCN302;
2103                 break;
2104         case IP_VERSION(3, 0, 3):
2105                 dmub_asic = DMUB_ASIC_DCN303;
2106                 break;
2107         case IP_VERSION(3, 1, 2):
2108         case IP_VERSION(3, 1, 3):
2109                 dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31;
2110                 break;
2111         case IP_VERSION(3, 1, 4):
2112                 dmub_asic = DMUB_ASIC_DCN314;
2113                 break;
2114         case IP_VERSION(3, 1, 5):
2115                 dmub_asic = DMUB_ASIC_DCN315;
2116                 break;
2117         case IP_VERSION(3, 1, 6):
2118                 dmub_asic = DMUB_ASIC_DCN316;
2119                 break;
2120         case IP_VERSION(3, 2, 0):
2121                 dmub_asic = DMUB_ASIC_DCN32;
2122                 break;
2123         case IP_VERSION(3, 2, 1):
2124                 dmub_asic = DMUB_ASIC_DCN321;
2125                 break;
2126         default:
2127                 /* ASIC doesn't support DMUB. */
2128                 return 0;
2129         }
2130
2131         hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
2132         adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
2133
2134         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2135                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
2136                         AMDGPU_UCODE_ID_DMCUB;
2137                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw =
2138                         adev->dm.dmub_fw;
2139                 adev->firmware.fw_size +=
2140                         ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
2141
2142                 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
2143                          adev->dm.dmcub_fw_version);
2144         }
2145
2146
2147         adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
2148         dmub_srv = adev->dm.dmub_srv;
2149
2150         if (!dmub_srv) {
2151                 DRM_ERROR("Failed to allocate DMUB service!\n");
2152                 return -ENOMEM;
2153         }
2154
2155         memset(&create_params, 0, sizeof(create_params));
2156         create_params.user_ctx = adev;
2157         create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
2158         create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
2159         create_params.asic = dmub_asic;
2160
2161         /* Create the DMUB service. */
2162         status = dmub_srv_create(dmub_srv, &create_params);
2163         if (status != DMUB_STATUS_OK) {
2164                 DRM_ERROR("Error creating DMUB service: %d\n", status);
2165                 return -EINVAL;
2166         }
2167
2168         /* Calculate the size of all the regions for the DMUB service. */
2169         memset(&region_params, 0, sizeof(region_params));
2170
2171         region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
2172                                         PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
2173         region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
2174         region_params.vbios_size = adev->bios_size;
2175         region_params.fw_bss_data = region_params.bss_data_size ?
2176                 adev->dm.dmub_fw->data +
2177                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2178                 le32_to_cpu(hdr->inst_const_bytes) : NULL;
2179         region_params.fw_inst_const =
2180                 adev->dm.dmub_fw->data +
2181                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2182                 PSP_HEADER_BYTES;
2183
2184         status = dmub_srv_calc_region_info(dmub_srv, &region_params,
2185                                            &region_info);
2186
2187         if (status != DMUB_STATUS_OK) {
2188                 DRM_ERROR("Error calculating DMUB region info: %d\n", status);
2189                 return -EINVAL;
2190         }
2191
2192         /*
2193          * Allocate a framebuffer based on the total size of all the regions.
2194          * TODO: Move this into GART.
2195          */
2196         r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
2197                                     AMDGPU_GEM_DOMAIN_VRAM |
2198                                     AMDGPU_GEM_DOMAIN_GTT,
2199                                     &adev->dm.dmub_bo,
2200                                     &adev->dm.dmub_bo_gpu_addr,
2201                                     &adev->dm.dmub_bo_cpu_addr);
2202         if (r)
2203                 return r;
2204
2205         /* Rebase the regions on the framebuffer address. */
2206         memset(&fb_params, 0, sizeof(fb_params));
2207         fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr;
2208         fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr;
2209         fb_params.region_info = &region_info;
2210
2211         adev->dm.dmub_fb_info =
2212                 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);
2213         fb_info = adev->dm.dmub_fb_info;
2214
2215         if (!fb_info) {
2216                 DRM_ERROR(
2217                         "Failed to allocate framebuffer info for DMUB service!\n");
2218                 return -ENOMEM;
2219         }
2220
2221         status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info);
2222         if (status != DMUB_STATUS_OK) {
2223                 DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
2224                 return -EINVAL;
2225         }
2226
2227         return 0;
2228 }
2229
2230 static int dm_sw_init(void *handle)
2231 {
2232         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2233         int r;
2234
2235         r = dm_dmub_sw_init(adev);
2236         if (r)
2237                 return r;
2238
2239         return load_dmcu_fw(adev);
2240 }
2241
2242 static int dm_sw_fini(void *handle)
2243 {
2244         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2245
2246         kfree(adev->dm.dmub_fb_info);
2247         adev->dm.dmub_fb_info = NULL;
2248
2249         if (adev->dm.dmub_srv) {
2250                 dmub_srv_destroy(adev->dm.dmub_srv);
2251                 adev->dm.dmub_srv = NULL;
2252         }
2253
2254         amdgpu_ucode_release(&adev->dm.dmub_fw);
2255         amdgpu_ucode_release(&adev->dm.fw_dmcu);
2256
2257         return 0;
2258 }
2259
2260 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
2261 {
2262         struct amdgpu_dm_connector *aconnector;
2263         struct drm_connector *connector;
2264         struct drm_connector_list_iter iter;
2265         int ret = 0;
2266
2267         drm_connector_list_iter_begin(dev, &iter);
2268         drm_for_each_connector_iter(connector, &iter) {
2269                 aconnector = to_amdgpu_dm_connector(connector);
2270                 if (aconnector->dc_link->type == dc_connection_mst_branch &&
2271                     aconnector->mst_mgr.aux) {
2272                         DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
2273                                          aconnector,
2274                                          aconnector->base.base.id);
2275
2276                         ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
2277                         if (ret < 0) {
2278                                 DRM_ERROR("DM_MST: Failed to start MST\n");
2279                                 aconnector->dc_link->type =
2280                                         dc_connection_single;
2281                                 ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2282                                                                      aconnector->dc_link);
2283                                 break;
2284                         }
2285                 }
2286         }
2287         drm_connector_list_iter_end(&iter);
2288
2289         return ret;
2290 }
2291
2292 static int dm_late_init(void *handle)
2293 {
2294         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2295
2296         struct dmcu_iram_parameters params;
2297         unsigned int linear_lut[16];
2298         int i;
2299         struct dmcu *dmcu = NULL;
2300
2301         dmcu = adev->dm.dc->res_pool->dmcu;
2302
2303         for (i = 0; i < 16; i++)
2304                 linear_lut[i] = 0xFFFF * i / 15;
2305
2306         params.set = 0;
2307         params.backlight_ramping_override = false;
2308         params.backlight_ramping_start = 0xCCCC;
2309         params.backlight_ramping_reduction = 0xCCCCCCCC;
2310         params.backlight_lut_array_size = 16;
2311         params.backlight_lut_array = linear_lut;
2312
2313         /* Min backlight level after ABM reduction,  Don't allow below 1%
2314          * 0xFFFF x 0.01 = 0x28F
2315          */
2316         params.min_abm_backlight = 0x28F;
2317         /* In the case where abm is implemented on dmcub,
2318          * dmcu object will be null.
2319          * ABM 2.4 and up are implemented on dmcub.
2320          */
2321         if (dmcu) {
2322                 if (!dmcu_load_iram(dmcu, params))
2323                         return -EINVAL;
2324         } else if (adev->dm.dc->ctx->dmub_srv) {
2325                 struct dc_link *edp_links[MAX_NUM_EDP];
2326                 int edp_num;
2327
2328                 dc_get_edp_links(adev->dm.dc, edp_links, &edp_num);
2329                 for (i = 0; i < edp_num; i++) {
2330                         if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i))
2331                                 return -EINVAL;
2332                 }
2333         }
2334
2335         return detect_mst_link_for_all_connectors(adev_to_drm(adev));
2336 }
2337
2338 static void s3_handle_mst(struct drm_device *dev, bool suspend)
2339 {
2340         struct amdgpu_dm_connector *aconnector;
2341         struct drm_connector *connector;
2342         struct drm_connector_list_iter iter;
2343         struct drm_dp_mst_topology_mgr *mgr;
2344         int ret;
2345         bool need_hotplug = false;
2346
2347         drm_connector_list_iter_begin(dev, &iter);
2348         drm_for_each_connector_iter(connector, &iter) {
2349                 aconnector = to_amdgpu_dm_connector(connector);
2350                 if (aconnector->dc_link->type != dc_connection_mst_branch ||
2351                     aconnector->mst_root)
2352                         continue;
2353
2354                 mgr = &aconnector->mst_mgr;
2355
2356                 if (suspend) {
2357                         drm_dp_mst_topology_mgr_suspend(mgr);
2358                 } else {
2359                         /* if extended timeout is supported in hardware,
2360                          * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
2361                          * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
2362                          */
2363                         try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
2364                         if (!dp_is_lttpr_present(aconnector->dc_link))
2365                                 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
2366
2367                         ret = drm_dp_mst_topology_mgr_resume(mgr, true);
2368                         if (ret < 0) {
2369                                 dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2370                                         aconnector->dc_link);
2371                                 need_hotplug = true;
2372                         }
2373                 }
2374         }
2375         drm_connector_list_iter_end(&iter);
2376
2377         if (need_hotplug)
2378                 drm_kms_helper_hotplug_event(dev);
2379 }
2380
2381 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
2382 {
2383         int ret = 0;
2384
2385         /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
2386          * on window driver dc implementation.
2387          * For Navi1x, clock settings of dcn watermarks are fixed. the settings
2388          * should be passed to smu during boot up and resume from s3.
2389          * boot up: dc calculate dcn watermark clock settings within dc_create,
2390          * dcn20_resource_construct
2391          * then call pplib functions below to pass the settings to smu:
2392          * smu_set_watermarks_for_clock_ranges
2393          * smu_set_watermarks_table
2394          * navi10_set_watermarks_table
2395          * smu_write_watermarks_table
2396          *
2397          * For Renoir, clock settings of dcn watermark are also fixed values.
2398          * dc has implemented different flow for window driver:
2399          * dc_hardware_init / dc_set_power_state
2400          * dcn10_init_hw
2401          * notify_wm_ranges
2402          * set_wm_ranges
2403          * -- Linux
2404          * smu_set_watermarks_for_clock_ranges
2405          * renoir_set_watermarks_table
2406          * smu_write_watermarks_table
2407          *
2408          * For Linux,
2409          * dc_hardware_init -> amdgpu_dm_init
2410          * dc_set_power_state --> dm_resume
2411          *
2412          * therefore, this function apply to navi10/12/14 but not Renoir
2413          * *
2414          */
2415         switch (adev->ip_versions[DCE_HWIP][0]) {
2416         case IP_VERSION(2, 0, 2):
2417         case IP_VERSION(2, 0, 0):
2418                 break;
2419         default:
2420                 return 0;
2421         }
2422
2423         ret = amdgpu_dpm_write_watermarks_table(adev);
2424         if (ret) {
2425                 DRM_ERROR("Failed to update WMTABLE!\n");
2426                 return ret;
2427         }
2428
2429         return 0;
2430 }
2431
2432 /**
2433  * dm_hw_init() - Initialize DC device
2434  * @handle: The base driver device containing the amdgpu_dm device.
2435  *
2436  * Initialize the &struct amdgpu_display_manager device. This involves calling
2437  * the initializers of each DM component, then populating the struct with them.
2438  *
2439  * Although the function implies hardware initialization, both hardware and
2440  * software are initialized here. Splitting them out to their relevant init
2441  * hooks is a future TODO item.
2442  *
2443  * Some notable things that are initialized here:
2444  *
2445  * - Display Core, both software and hardware
2446  * - DC modules that we need (freesync and color management)
2447  * - DRM software states
2448  * - Interrupt sources and handlers
2449  * - Vblank support
2450  * - Debug FS entries, if enabled
2451  */
2452 static int dm_hw_init(void *handle)
2453 {
2454         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2455         /* Create DAL display manager */
2456         amdgpu_dm_init(adev);
2457         amdgpu_dm_hpd_init(adev);
2458
2459         return 0;
2460 }
2461
2462 /**
2463  * dm_hw_fini() - Teardown DC device
2464  * @handle: The base driver device containing the amdgpu_dm device.
2465  *
2466  * Teardown components within &struct amdgpu_display_manager that require
2467  * cleanup. This involves cleaning up the DRM device, DC, and any modules that
2468  * were loaded. Also flush IRQ workqueues and disable them.
2469  */
2470 static int dm_hw_fini(void *handle)
2471 {
2472         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2473
2474         amdgpu_dm_hpd_fini(adev);
2475
2476         amdgpu_dm_irq_fini(adev);
2477         amdgpu_dm_fini(adev);
2478         return 0;
2479 }
2480
2481
2482 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
2483                                  struct dc_state *state, bool enable)
2484 {
2485         enum dc_irq_source irq_source;
2486         struct amdgpu_crtc *acrtc;
2487         int rc = -EBUSY;
2488         int i = 0;
2489
2490         for (i = 0; i < state->stream_count; i++) {
2491                 acrtc = get_crtc_by_otg_inst(
2492                                 adev, state->stream_status[i].primary_otg_inst);
2493
2494                 if (acrtc && state->stream_status[i].plane_count != 0) {
2495                         irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst;
2496                         rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
2497                         if (rc)
2498                                 DRM_WARN("Failed to %s pflip interrupts\n",
2499                                          enable ? "enable" : "disable");
2500
2501                         if (enable) {
2502                                 if (amdgpu_dm_crtc_vrr_active(to_dm_crtc_state(acrtc->base.state)))
2503                                         rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, true);
2504                         } else
2505                                 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, false);
2506
2507                         if (rc)
2508                                 DRM_WARN("Failed to %sable vupdate interrupt\n", enable ? "en" : "dis");
2509
2510                         irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
2511                         /* During gpu-reset we disable and then enable vblank irq, so
2512                          * don't use amdgpu_irq_get/put() to avoid refcount change.
2513                          */
2514                         if (!dc_interrupt_set(adev->dm.dc, irq_source, enable))
2515                                 DRM_WARN("Failed to %sable vblank interrupt\n", enable ? "en" : "dis");
2516                 }
2517         }
2518
2519 }
2520
2521 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
2522 {
2523         struct dc_state *context = NULL;
2524         enum dc_status res = DC_ERROR_UNEXPECTED;
2525         int i;
2526         struct dc_stream_state *del_streams[MAX_PIPES];
2527         int del_streams_count = 0;
2528
2529         memset(del_streams, 0, sizeof(del_streams));
2530
2531         context = dc_create_state(dc);
2532         if (context == NULL)
2533                 goto context_alloc_fail;
2534
2535         dc_resource_state_copy_construct_current(dc, context);
2536
2537         /* First remove from context all streams */
2538         for (i = 0; i < context->stream_count; i++) {
2539                 struct dc_stream_state *stream = context->streams[i];
2540
2541                 del_streams[del_streams_count++] = stream;
2542         }
2543
2544         /* Remove all planes for removed streams and then remove the streams */
2545         for (i = 0; i < del_streams_count; i++) {
2546                 if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) {
2547                         res = DC_FAIL_DETACH_SURFACES;
2548                         goto fail;
2549                 }
2550
2551                 res = dc_remove_stream_from_ctx(dc, context, del_streams[i]);
2552                 if (res != DC_OK)
2553                         goto fail;
2554         }
2555
2556         res = dc_commit_streams(dc, context->streams, context->stream_count);
2557
2558 fail:
2559         dc_release_state(context);
2560
2561 context_alloc_fail:
2562         return res;
2563 }
2564
2565 static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm)
2566 {
2567         int i;
2568
2569         if (dm->hpd_rx_offload_wq) {
2570                 for (i = 0; i < dm->dc->caps.max_links; i++)
2571                         flush_workqueue(dm->hpd_rx_offload_wq[i].wq);
2572         }
2573 }
2574
2575 static int dm_suspend(void *handle)
2576 {
2577         struct amdgpu_device *adev = handle;
2578         struct amdgpu_display_manager *dm = &adev->dm;
2579         int ret = 0;
2580
2581         if (amdgpu_in_reset(adev)) {
2582                 mutex_lock(&dm->dc_lock);
2583
2584                 dc_allow_idle_optimizations(adev->dm.dc, false);
2585
2586                 dm->cached_dc_state = dc_copy_state(dm->dc->current_state);
2587
2588                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
2589
2590                 amdgpu_dm_commit_zero_streams(dm->dc);
2591
2592                 amdgpu_dm_irq_suspend(adev);
2593
2594                 hpd_rx_irq_work_suspend(dm);
2595
2596                 return ret;
2597         }
2598
2599         WARN_ON(adev->dm.cached_state);
2600         adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));
2601
2602         s3_handle_mst(adev_to_drm(adev), true);
2603
2604         amdgpu_dm_irq_suspend(adev);
2605
2606         hpd_rx_irq_work_suspend(dm);
2607
2608         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
2609
2610         return 0;
2611 }
2612
2613 struct amdgpu_dm_connector *
2614 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
2615                                              struct drm_crtc *crtc)
2616 {
2617         u32 i;
2618         struct drm_connector_state *new_con_state;
2619         struct drm_connector *connector;
2620         struct drm_crtc *crtc_from_state;
2621
2622         for_each_new_connector_in_state(state, connector, new_con_state, i) {
2623                 crtc_from_state = new_con_state->crtc;
2624
2625                 if (crtc_from_state == crtc)
2626                         return to_amdgpu_dm_connector(connector);
2627         }
2628
2629         return NULL;
2630 }
2631
2632 static void emulated_link_detect(struct dc_link *link)
2633 {
2634         struct dc_sink_init_data sink_init_data = { 0 };
2635         struct display_sink_capability sink_caps = { 0 };
2636         enum dc_edid_status edid_status;
2637         struct dc_context *dc_ctx = link->ctx;
2638         struct dc_sink *sink = NULL;
2639         struct dc_sink *prev_sink = NULL;
2640
2641         link->type = dc_connection_none;
2642         prev_sink = link->local_sink;
2643
2644         if (prev_sink)
2645                 dc_sink_release(prev_sink);
2646
2647         switch (link->connector_signal) {
2648         case SIGNAL_TYPE_HDMI_TYPE_A: {
2649                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2650                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
2651                 break;
2652         }
2653
2654         case SIGNAL_TYPE_DVI_SINGLE_LINK: {
2655                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2656                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
2657                 break;
2658         }
2659
2660         case SIGNAL_TYPE_DVI_DUAL_LINK: {
2661                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2662                 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
2663                 break;
2664         }
2665
2666         case SIGNAL_TYPE_LVDS: {
2667                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2668                 sink_caps.signal = SIGNAL_TYPE_LVDS;
2669                 break;
2670         }
2671
2672         case SIGNAL_TYPE_EDP: {
2673                 sink_caps.transaction_type =
2674                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2675                 sink_caps.signal = SIGNAL_TYPE_EDP;
2676                 break;
2677         }
2678
2679         case SIGNAL_TYPE_DISPLAY_PORT: {
2680                 sink_caps.transaction_type =
2681                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2682                 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
2683                 break;
2684         }
2685
2686         default:
2687                 DC_ERROR("Invalid connector type! signal:%d\n",
2688                         link->connector_signal);
2689                 return;
2690         }
2691
2692         sink_init_data.link = link;
2693         sink_init_data.sink_signal = sink_caps.signal;
2694
2695         sink = dc_sink_create(&sink_init_data);
2696         if (!sink) {
2697                 DC_ERROR("Failed to create sink!\n");
2698                 return;
2699         }
2700
2701         /* dc_sink_create returns a new reference */
2702         link->local_sink = sink;
2703
2704         edid_status = dm_helpers_read_local_edid(
2705                         link->ctx,
2706                         link,
2707                         sink);
2708
2709         if (edid_status != EDID_OK)
2710                 DC_ERROR("Failed to read EDID");
2711
2712 }
2713
2714 static void dm_gpureset_commit_state(struct dc_state *dc_state,
2715                                      struct amdgpu_display_manager *dm)
2716 {
2717         struct {
2718                 struct dc_surface_update surface_updates[MAX_SURFACES];
2719                 struct dc_plane_info plane_infos[MAX_SURFACES];
2720                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
2721                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
2722                 struct dc_stream_update stream_update;
2723         } *bundle;
2724         int k, m;
2725
2726         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
2727
2728         if (!bundle) {
2729                 dm_error("Failed to allocate update bundle\n");
2730                 goto cleanup;
2731         }
2732
2733         for (k = 0; k < dc_state->stream_count; k++) {
2734                 bundle->stream_update.stream = dc_state->streams[k];
2735
2736                 for (m = 0; m < dc_state->stream_status->plane_count; m++) {
2737                         bundle->surface_updates[m].surface =
2738                                 dc_state->stream_status->plane_states[m];
2739                         bundle->surface_updates[m].surface->force_full_update =
2740                                 true;
2741                 }
2742
2743                 update_planes_and_stream_adapter(dm->dc,
2744                                          UPDATE_TYPE_FULL,
2745                                          dc_state->stream_status->plane_count,
2746                                          dc_state->streams[k],
2747                                          &bundle->stream_update,
2748                                          bundle->surface_updates);
2749         }
2750
2751 cleanup:
2752         kfree(bundle);
2753 }
2754
2755 static int dm_resume(void *handle)
2756 {
2757         struct amdgpu_device *adev = handle;
2758         struct drm_device *ddev = adev_to_drm(adev);
2759         struct amdgpu_display_manager *dm = &adev->dm;
2760         struct amdgpu_dm_connector *aconnector;
2761         struct drm_connector *connector;
2762         struct drm_connector_list_iter iter;
2763         struct drm_crtc *crtc;
2764         struct drm_crtc_state *new_crtc_state;
2765         struct dm_crtc_state *dm_new_crtc_state;
2766         struct drm_plane *plane;
2767         struct drm_plane_state *new_plane_state;
2768         struct dm_plane_state *dm_new_plane_state;
2769         struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
2770         enum dc_connection_type new_connection_type = dc_connection_none;
2771         struct dc_state *dc_state;
2772         int i, r, j;
2773
2774         if (amdgpu_in_reset(adev)) {
2775                 dc_state = dm->cached_dc_state;
2776
2777                 /*
2778                  * The dc->current_state is backed up into dm->cached_dc_state
2779                  * before we commit 0 streams.
2780                  *
2781                  * DC will clear link encoder assignments on the real state
2782                  * but the changes won't propagate over to the copy we made
2783                  * before the 0 streams commit.
2784                  *
2785                  * DC expects that link encoder assignments are *not* valid
2786                  * when committing a state, so as a workaround we can copy
2787                  * off of the current state.
2788                  *
2789                  * We lose the previous assignments, but we had already
2790                  * commit 0 streams anyway.
2791                  */
2792                 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state);
2793
2794                 r = dm_dmub_hw_init(adev);
2795                 if (r)
2796                         DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
2797
2798                 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2799                 dc_resume(dm->dc);
2800
2801                 amdgpu_dm_irq_resume_early(adev);
2802
2803                 for (i = 0; i < dc_state->stream_count; i++) {
2804                         dc_state->streams[i]->mode_changed = true;
2805                         for (j = 0; j < dc_state->stream_status[i].plane_count; j++) {
2806                                 dc_state->stream_status[i].plane_states[j]->update_flags.raw
2807                                         = 0xffffffff;
2808                         }
2809                 }
2810
2811                 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2812                         amdgpu_dm_outbox_init(adev);
2813                         dc_enable_dmub_outbox(adev->dm.dc);
2814                 }
2815
2816                 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
2817
2818                 dm_gpureset_commit_state(dm->cached_dc_state, dm);
2819
2820                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true);
2821
2822                 dc_release_state(dm->cached_dc_state);
2823                 dm->cached_dc_state = NULL;
2824
2825                 amdgpu_dm_irq_resume_late(adev);
2826
2827                 mutex_unlock(&dm->dc_lock);
2828
2829                 return 0;
2830         }
2831         /* Recreate dc_state - DC invalidates it when setting power state to S3. */
2832         dc_release_state(dm_state->context);
2833         dm_state->context = dc_create_state(dm->dc);
2834         /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
2835         dc_resource_state_construct(dm->dc, dm_state->context);
2836
2837         /* Before powering on DC we need to re-initialize DMUB. */
2838         dm_dmub_hw_resume(adev);
2839
2840         /* Re-enable outbox interrupts for DPIA. */
2841         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2842                 amdgpu_dm_outbox_init(adev);
2843                 dc_enable_dmub_outbox(adev->dm.dc);
2844         }
2845
2846         /* power on hardware */
2847         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2848
2849         /* program HPD filter */
2850         dc_resume(dm->dc);
2851
2852         /*
2853          * early enable HPD Rx IRQ, should be done before set mode as short
2854          * pulse interrupts are used for MST
2855          */
2856         amdgpu_dm_irq_resume_early(adev);
2857
2858         /* On resume we need to rewrite the MSTM control bits to enable MST*/
2859         s3_handle_mst(ddev, false);
2860
2861         /* Do detection*/
2862         drm_connector_list_iter_begin(ddev, &iter);
2863         drm_for_each_connector_iter(connector, &iter) {
2864                 aconnector = to_amdgpu_dm_connector(connector);
2865
2866                 if (!aconnector->dc_link)
2867                         continue;
2868
2869                 /*
2870                  * this is the case when traversing through already created
2871                  * MST connectors, should be skipped
2872                  */
2873                 if (aconnector && aconnector->mst_root)
2874                         continue;
2875
2876                 mutex_lock(&aconnector->hpd_lock);
2877                 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
2878                         DRM_ERROR("KMS: Failed to detect connector\n");
2879
2880                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2881                         emulated_link_detect(aconnector->dc_link);
2882                 } else {
2883                         mutex_lock(&dm->dc_lock);
2884                         dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
2885                         mutex_unlock(&dm->dc_lock);
2886                 }
2887
2888                 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
2889                         aconnector->fake_enable = false;
2890
2891                 if (aconnector->dc_sink)
2892                         dc_sink_release(aconnector->dc_sink);
2893                 aconnector->dc_sink = NULL;
2894                 amdgpu_dm_update_connector_after_detect(aconnector);
2895                 mutex_unlock(&aconnector->hpd_lock);
2896         }
2897         drm_connector_list_iter_end(&iter);
2898
2899         /* Force mode set in atomic commit */
2900         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
2901                 new_crtc_state->active_changed = true;
2902
2903         /*
2904          * atomic_check is expected to create the dc states. We need to release
2905          * them here, since they were duplicated as part of the suspend
2906          * procedure.
2907          */
2908         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
2909                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
2910                 if (dm_new_crtc_state->stream) {
2911                         WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
2912                         dc_stream_release(dm_new_crtc_state->stream);
2913                         dm_new_crtc_state->stream = NULL;
2914                 }
2915         }
2916
2917         for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
2918                 dm_new_plane_state = to_dm_plane_state(new_plane_state);
2919                 if (dm_new_plane_state->dc_state) {
2920                         WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
2921                         dc_plane_state_release(dm_new_plane_state->dc_state);
2922                         dm_new_plane_state->dc_state = NULL;
2923                 }
2924         }
2925
2926         drm_atomic_helper_resume(ddev, dm->cached_state);
2927
2928         dm->cached_state = NULL;
2929
2930         amdgpu_dm_irq_resume_late(adev);
2931
2932         amdgpu_dm_smu_write_watermarks_table(adev);
2933
2934         return 0;
2935 }
2936
2937 /**
2938  * DOC: DM Lifecycle
2939  *
2940  * DM (and consequently DC) is registered in the amdgpu base driver as a IP
2941  * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
2942  * the base driver's device list to be initialized and torn down accordingly.
2943  *
2944  * The functions to do so are provided as hooks in &struct amd_ip_funcs.
2945  */
2946
2947 static const struct amd_ip_funcs amdgpu_dm_funcs = {
2948         .name = "dm",
2949         .early_init = dm_early_init,
2950         .late_init = dm_late_init,
2951         .sw_init = dm_sw_init,
2952         .sw_fini = dm_sw_fini,
2953         .early_fini = amdgpu_dm_early_fini,
2954         .hw_init = dm_hw_init,
2955         .hw_fini = dm_hw_fini,
2956         .suspend = dm_suspend,
2957         .resume = dm_resume,
2958         .is_idle = dm_is_idle,
2959         .wait_for_idle = dm_wait_for_idle,
2960         .check_soft_reset = dm_check_soft_reset,
2961         .soft_reset = dm_soft_reset,
2962         .set_clockgating_state = dm_set_clockgating_state,
2963         .set_powergating_state = dm_set_powergating_state,
2964 };
2965
2966 const struct amdgpu_ip_block_version dm_ip_block = {
2967         .type = AMD_IP_BLOCK_TYPE_DCE,
2968         .major = 1,
2969         .minor = 0,
2970         .rev = 0,
2971         .funcs = &amdgpu_dm_funcs,
2972 };
2973
2974
2975 /**
2976  * DOC: atomic
2977  *
2978  * *WIP*
2979  */
2980
2981 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
2982         .fb_create = amdgpu_display_user_framebuffer_create,
2983         .get_format_info = amdgpu_dm_plane_get_format_info,
2984         .atomic_check = amdgpu_dm_atomic_check,
2985         .atomic_commit = drm_atomic_helper_commit,
2986 };
2987
2988 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
2989         .atomic_commit_tail = amdgpu_dm_atomic_commit_tail,
2990         .atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
2991 };
2992
2993 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
2994 {
2995         struct amdgpu_dm_backlight_caps *caps;
2996         struct drm_connector *conn_base;
2997         struct amdgpu_device *adev;
2998         struct drm_luminance_range_info *luminance_range;
2999
3000         if (aconnector->bl_idx == -1 ||
3001             aconnector->dc_link->connector_signal != SIGNAL_TYPE_EDP)
3002                 return;
3003
3004         conn_base = &aconnector->base;
3005         adev = drm_to_adev(conn_base->dev);
3006
3007         caps = &adev->dm.backlight_caps[aconnector->bl_idx];
3008         caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
3009         caps->aux_support = false;
3010
3011         if (caps->ext_caps->bits.oled == 1
3012             /*
3013              * ||
3014              * caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
3015              * caps->ext_caps->bits.hdr_aux_backlight_control == 1
3016              */)
3017                 caps->aux_support = true;
3018
3019         if (amdgpu_backlight == 0)
3020                 caps->aux_support = false;
3021         else if (amdgpu_backlight == 1)
3022                 caps->aux_support = true;
3023
3024         luminance_range = &conn_base->display_info.luminance_range;
3025
3026         if (luminance_range->max_luminance) {
3027                 caps->aux_min_input_signal = luminance_range->min_luminance;
3028                 caps->aux_max_input_signal = luminance_range->max_luminance;
3029         } else {
3030                 caps->aux_min_input_signal = 0;
3031                 caps->aux_max_input_signal = 512;
3032         }
3033 }
3034
3035 void amdgpu_dm_update_connector_after_detect(
3036                 struct amdgpu_dm_connector *aconnector)
3037 {
3038         struct drm_connector *connector = &aconnector->base;
3039         struct drm_device *dev = connector->dev;
3040         struct dc_sink *sink;
3041
3042         /* MST handled by drm_mst framework */
3043         if (aconnector->mst_mgr.mst_state == true)
3044                 return;
3045
3046         sink = aconnector->dc_link->local_sink;
3047         if (sink)
3048                 dc_sink_retain(sink);
3049
3050         /*
3051          * Edid mgmt connector gets first update only in mode_valid hook and then
3052          * the connector sink is set to either fake or physical sink depends on link status.
3053          * Skip if already done during boot.
3054          */
3055         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
3056                         && aconnector->dc_em_sink) {
3057
3058                 /*
3059                  * For S3 resume with headless use eml_sink to fake stream
3060                  * because on resume connector->sink is set to NULL
3061                  */
3062                 mutex_lock(&dev->mode_config.mutex);
3063
3064                 if (sink) {
3065                         if (aconnector->dc_sink) {
3066                                 amdgpu_dm_update_freesync_caps(connector, NULL);
3067                                 /*
3068                                  * retain and release below are used to
3069                                  * bump up refcount for sink because the link doesn't point
3070                                  * to it anymore after disconnect, so on next crtc to connector
3071                                  * reshuffle by UMD we will get into unwanted dc_sink release
3072                                  */
3073                                 dc_sink_release(aconnector->dc_sink);
3074                         }
3075                         aconnector->dc_sink = sink;
3076                         dc_sink_retain(aconnector->dc_sink);
3077                         amdgpu_dm_update_freesync_caps(connector,
3078                                         aconnector->edid);
3079                 } else {
3080                         amdgpu_dm_update_freesync_caps(connector, NULL);
3081                         if (!aconnector->dc_sink) {
3082                                 aconnector->dc_sink = aconnector->dc_em_sink;
3083                                 dc_sink_retain(aconnector->dc_sink);
3084                         }
3085                 }
3086
3087                 mutex_unlock(&dev->mode_config.mutex);
3088
3089                 if (sink)
3090                         dc_sink_release(sink);
3091                 return;
3092         }
3093
3094         /*
3095          * TODO: temporary guard to look for proper fix
3096          * if this sink is MST sink, we should not do anything
3097          */
3098         if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3099                 dc_sink_release(sink);
3100                 return;
3101         }
3102
3103         if (aconnector->dc_sink == sink) {
3104                 /*
3105                  * We got a DP short pulse (Link Loss, DP CTS, etc...).
3106                  * Do nothing!!
3107                  */
3108                 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
3109                                 aconnector->connector_id);
3110                 if (sink)
3111                         dc_sink_release(sink);
3112                 return;
3113         }
3114
3115         DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
3116                 aconnector->connector_id, aconnector->dc_sink, sink);
3117
3118         mutex_lock(&dev->mode_config.mutex);
3119
3120         /*
3121          * 1. Update status of the drm connector
3122          * 2. Send an event and let userspace tell us what to do
3123          */
3124         if (sink) {
3125                 /*
3126                  * TODO: check if we still need the S3 mode update workaround.
3127                  * If yes, put it here.
3128                  */
3129                 if (aconnector->dc_sink) {
3130                         amdgpu_dm_update_freesync_caps(connector, NULL);
3131                         dc_sink_release(aconnector->dc_sink);
3132                 }
3133
3134                 aconnector->dc_sink = sink;
3135                 dc_sink_retain(aconnector->dc_sink);
3136                 if (sink->dc_edid.length == 0) {
3137                         aconnector->edid = NULL;
3138                         if (aconnector->dc_link->aux_mode) {
3139                                 drm_dp_cec_unset_edid(
3140                                         &aconnector->dm_dp_aux.aux);
3141                         }
3142                 } else {
3143                         aconnector->edid =
3144                                 (struct edid *)sink->dc_edid.raw_edid;
3145
3146                         if (aconnector->dc_link->aux_mode)
3147                                 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
3148                                                     aconnector->edid);
3149                 }
3150
3151                 if (!aconnector->timing_requested) {
3152                         aconnector->timing_requested =
3153                                 kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL);
3154                         if (!aconnector->timing_requested)
3155                                 dm_error("failed to create aconnector->requested_timing\n");
3156                 }
3157
3158                 drm_connector_update_edid_property(connector, aconnector->edid);
3159                 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
3160                 update_connector_ext_caps(aconnector);
3161         } else {
3162                 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
3163                 amdgpu_dm_update_freesync_caps(connector, NULL);
3164                 drm_connector_update_edid_property(connector, NULL);
3165                 aconnector->num_modes = 0;
3166                 dc_sink_release(aconnector->dc_sink);
3167                 aconnector->dc_sink = NULL;
3168                 aconnector->edid = NULL;
3169                 kfree(aconnector->timing_requested);
3170                 aconnector->timing_requested = NULL;
3171                 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
3172                 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
3173                         connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
3174         }
3175
3176         mutex_unlock(&dev->mode_config.mutex);
3177
3178         update_subconnector_property(aconnector);
3179
3180         if (sink)
3181                 dc_sink_release(sink);
3182 }
3183
3184 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)
3185 {
3186         struct drm_connector *connector = &aconnector->base;
3187         struct drm_device *dev = connector->dev;
3188         enum dc_connection_type new_connection_type = dc_connection_none;
3189         struct amdgpu_device *adev = drm_to_adev(dev);
3190         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
3191         bool ret = false;
3192
3193         if (adev->dm.disable_hpd_irq)
3194                 return;
3195
3196         /*
3197          * In case of failure or MST no need to update connector status or notify the OS
3198          * since (for MST case) MST does this in its own context.
3199          */
3200         mutex_lock(&aconnector->hpd_lock);
3201
3202         if (adev->dm.hdcp_workqueue) {
3203                 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
3204                 dm_con_state->update_hdcp = true;
3205         }
3206         if (aconnector->fake_enable)
3207                 aconnector->fake_enable = false;
3208
3209         aconnector->timing_changed = false;
3210
3211         if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
3212                 DRM_ERROR("KMS: Failed to detect connector\n");
3213
3214         if (aconnector->base.force && new_connection_type == dc_connection_none) {
3215                 emulated_link_detect(aconnector->dc_link);
3216
3217                 drm_modeset_lock_all(dev);
3218                 dm_restore_drm_connector_state(dev, connector);
3219                 drm_modeset_unlock_all(dev);
3220
3221                 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3222                         drm_kms_helper_connector_hotplug_event(connector);
3223         } else {
3224                 mutex_lock(&adev->dm.dc_lock);
3225                 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3226                 mutex_unlock(&adev->dm.dc_lock);
3227                 if (ret) {
3228                         amdgpu_dm_update_connector_after_detect(aconnector);
3229
3230                         drm_modeset_lock_all(dev);
3231                         dm_restore_drm_connector_state(dev, connector);
3232                         drm_modeset_unlock_all(dev);
3233
3234                         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3235                                 drm_kms_helper_connector_hotplug_event(connector);
3236                 }
3237         }
3238         mutex_unlock(&aconnector->hpd_lock);
3239
3240 }
3241
3242 static void handle_hpd_irq(void *param)
3243 {
3244         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3245
3246         handle_hpd_irq_helper(aconnector);
3247
3248 }
3249
3250 static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq,
3251                                                         union hpd_irq_data hpd_irq_data)
3252 {
3253         struct hpd_rx_irq_offload_work *offload_work =
3254                                 kzalloc(sizeof(*offload_work), GFP_KERNEL);
3255
3256         if (!offload_work) {
3257                 DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n");
3258                 return;
3259         }
3260
3261         INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work);
3262         offload_work->data = hpd_irq_data;
3263         offload_work->offload_wq = offload_wq;
3264
3265         queue_work(offload_wq->wq, &offload_work->work);
3266         DRM_DEBUG_KMS("queue work to handle hpd_rx offload work");
3267 }
3268
3269 static void handle_hpd_rx_irq(void *param)
3270 {
3271         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3272         struct drm_connector *connector = &aconnector->base;
3273         struct drm_device *dev = connector->dev;
3274         struct dc_link *dc_link = aconnector->dc_link;
3275         bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
3276         bool result = false;
3277         enum dc_connection_type new_connection_type = dc_connection_none;
3278         struct amdgpu_device *adev = drm_to_adev(dev);
3279         union hpd_irq_data hpd_irq_data;
3280         bool link_loss = false;
3281         bool has_left_work = false;
3282         int idx = dc_link->link_index;
3283         struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx];
3284
3285         memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
3286
3287         if (adev->dm.disable_hpd_irq)
3288                 return;
3289
3290         /*
3291          * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
3292          * conflict, after implement i2c helper, this mutex should be
3293          * retired.
3294          */
3295         mutex_lock(&aconnector->hpd_lock);
3296
3297         result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data,
3298                                                 &link_loss, true, &has_left_work);
3299
3300         if (!has_left_work)
3301                 goto out;
3302
3303         if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3304                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3305                 goto out;
3306         }
3307
3308         if (dc_link_dp_allow_hpd_rx_irq(dc_link)) {
3309                 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
3310                         hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
3311                         bool skip = false;
3312
3313                         /*
3314                          * DOWN_REP_MSG_RDY is also handled by polling method
3315                          * mgr->cbs->poll_hpd_irq()
3316                          */
3317                         spin_lock(&offload_wq->offload_lock);
3318                         skip = offload_wq->is_handling_mst_msg_rdy_event;
3319
3320                         if (!skip)
3321                                 offload_wq->is_handling_mst_msg_rdy_event = true;
3322
3323                         spin_unlock(&offload_wq->offload_lock);
3324
3325                         if (!skip)
3326                                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3327
3328                         goto out;
3329                 }
3330
3331                 if (link_loss) {
3332                         bool skip = false;
3333
3334                         spin_lock(&offload_wq->offload_lock);
3335                         skip = offload_wq->is_handling_link_loss;
3336
3337                         if (!skip)
3338                                 offload_wq->is_handling_link_loss = true;
3339
3340                         spin_unlock(&offload_wq->offload_lock);
3341
3342                         if (!skip)
3343                                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3344
3345                         goto out;
3346                 }
3347         }
3348
3349 out:
3350         if (result && !is_mst_root_connector) {
3351                 /* Downstream Port status changed. */
3352                 if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
3353                         DRM_ERROR("KMS: Failed to detect connector\n");
3354
3355                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3356                         emulated_link_detect(dc_link);
3357
3358                         if (aconnector->fake_enable)
3359                                 aconnector->fake_enable = false;
3360
3361                         amdgpu_dm_update_connector_after_detect(aconnector);
3362
3363
3364                         drm_modeset_lock_all(dev);
3365                         dm_restore_drm_connector_state(dev, connector);
3366                         drm_modeset_unlock_all(dev);
3367
3368                         drm_kms_helper_connector_hotplug_event(connector);
3369                 } else {
3370                         bool ret = false;
3371
3372                         mutex_lock(&adev->dm.dc_lock);
3373                         ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX);
3374                         mutex_unlock(&adev->dm.dc_lock);
3375
3376                         if (ret) {
3377                                 if (aconnector->fake_enable)
3378                                         aconnector->fake_enable = false;
3379
3380                                 amdgpu_dm_update_connector_after_detect(aconnector);
3381
3382                                 drm_modeset_lock_all(dev);
3383                                 dm_restore_drm_connector_state(dev, connector);
3384                                 drm_modeset_unlock_all(dev);
3385
3386                                 drm_kms_helper_connector_hotplug_event(connector);
3387                         }
3388                 }
3389         }
3390         if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
3391                 if (adev->dm.hdcp_workqueue)
3392                         hdcp_handle_cpirq(adev->dm.hdcp_workqueue,  aconnector->base.index);
3393         }
3394
3395         if (dc_link->type != dc_connection_mst_branch)
3396                 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
3397
3398         mutex_unlock(&aconnector->hpd_lock);
3399 }
3400
3401 static void register_hpd_handlers(struct amdgpu_device *adev)
3402 {
3403         struct drm_device *dev = adev_to_drm(adev);
3404         struct drm_connector *connector;
3405         struct amdgpu_dm_connector *aconnector;
3406         const struct dc_link *dc_link;
3407         struct dc_interrupt_params int_params = {0};
3408
3409         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3410         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3411
3412         list_for_each_entry(connector,
3413                         &dev->mode_config.connector_list, head) {
3414
3415                 aconnector = to_amdgpu_dm_connector(connector);
3416                 dc_link = aconnector->dc_link;
3417
3418                 if (dc_link->irq_source_hpd != DC_IRQ_SOURCE_INVALID) {
3419                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3420                         int_params.irq_source = dc_link->irq_source_hpd;
3421
3422                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
3423                                         handle_hpd_irq,
3424                                         (void *) aconnector);
3425                 }
3426
3427                 if (dc_link->irq_source_hpd_rx != DC_IRQ_SOURCE_INVALID) {
3428
3429                         /* Also register for DP short pulse (hpd_rx). */
3430                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3431                         int_params.irq_source = dc_link->irq_source_hpd_rx;
3432
3433                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
3434                                         handle_hpd_rx_irq,
3435                                         (void *) aconnector);
3436                 }
3437
3438                 if (adev->dm.hpd_rx_offload_wq)
3439                         adev->dm.hpd_rx_offload_wq[connector->index].aconnector =
3440                                 aconnector;
3441         }
3442 }
3443
3444 #if defined(CONFIG_DRM_AMD_DC_SI)
3445 /* Register IRQ sources and initialize IRQ callbacks */
3446 static int dce60_register_irq_handlers(struct amdgpu_device *adev)
3447 {
3448         struct dc *dc = adev->dm.dc;
3449         struct common_irq_params *c_irq_params;
3450         struct dc_interrupt_params int_params = {0};
3451         int r;
3452         int i;
3453         unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3454
3455         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3456         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3457
3458         /*
3459          * Actions of amdgpu_irq_add_id():
3460          * 1. Register a set() function with base driver.
3461          *    Base driver will call set() function to enable/disable an
3462          *    interrupt in DC hardware.
3463          * 2. Register amdgpu_dm_irq_handler().
3464          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3465          *    coming from DC hardware.
3466          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3467          *    for acknowledging and handling.
3468          */
3469
3470         /* Use VBLANK interrupt */
3471         for (i = 0; i < adev->mode_info.num_crtc; i++) {
3472                 r = amdgpu_irq_add_id(adev, client_id, i + 1, &adev->crtc_irq);
3473                 if (r) {
3474                         DRM_ERROR("Failed to add crtc irq id!\n");
3475                         return r;
3476                 }
3477
3478                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3479                 int_params.irq_source =
3480                         dc_interrupt_to_irq_source(dc, i + 1, 0);
3481
3482                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3483
3484                 c_irq_params->adev = adev;
3485                 c_irq_params->irq_src = int_params.irq_source;
3486
3487                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3488                                 dm_crtc_high_irq, c_irq_params);
3489         }
3490
3491         /* Use GRPH_PFLIP interrupt */
3492         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3493                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3494                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3495                 if (r) {
3496                         DRM_ERROR("Failed to add page flip irq id!\n");
3497                         return r;
3498                 }
3499
3500                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3501                 int_params.irq_source =
3502                         dc_interrupt_to_irq_source(dc, i, 0);
3503
3504                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3505
3506                 c_irq_params->adev = adev;
3507                 c_irq_params->irq_src = int_params.irq_source;
3508
3509                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3510                                 dm_pflip_high_irq, c_irq_params);
3511
3512         }
3513
3514         /* HPD */
3515         r = amdgpu_irq_add_id(adev, client_id,
3516                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3517         if (r) {
3518                 DRM_ERROR("Failed to add hpd irq id!\n");
3519                 return r;
3520         }
3521
3522         register_hpd_handlers(adev);
3523
3524         return 0;
3525 }
3526 #endif
3527
3528 /* Register IRQ sources and initialize IRQ callbacks */
3529 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
3530 {
3531         struct dc *dc = adev->dm.dc;
3532         struct common_irq_params *c_irq_params;
3533         struct dc_interrupt_params int_params = {0};
3534         int r;
3535         int i;
3536         unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3537
3538         if (adev->family >= AMDGPU_FAMILY_AI)
3539                 client_id = SOC15_IH_CLIENTID_DCE;
3540
3541         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3542         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3543
3544         /*
3545          * Actions of amdgpu_irq_add_id():
3546          * 1. Register a set() function with base driver.
3547          *    Base driver will call set() function to enable/disable an
3548          *    interrupt in DC hardware.
3549          * 2. Register amdgpu_dm_irq_handler().
3550          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3551          *    coming from DC hardware.
3552          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3553          *    for acknowledging and handling.
3554          */
3555
3556         /* Use VBLANK interrupt */
3557         for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
3558                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
3559                 if (r) {
3560                         DRM_ERROR("Failed to add crtc irq id!\n");
3561                         return r;
3562                 }
3563
3564                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3565                 int_params.irq_source =
3566                         dc_interrupt_to_irq_source(dc, i, 0);
3567
3568                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3569
3570                 c_irq_params->adev = adev;
3571                 c_irq_params->irq_src = int_params.irq_source;
3572
3573                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3574                                 dm_crtc_high_irq, c_irq_params);
3575         }
3576
3577         /* Use VUPDATE interrupt */
3578         for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
3579                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
3580                 if (r) {
3581                         DRM_ERROR("Failed to add vupdate irq id!\n");
3582                         return r;
3583                 }
3584
3585                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3586                 int_params.irq_source =
3587                         dc_interrupt_to_irq_source(dc, i, 0);
3588
3589                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3590
3591                 c_irq_params->adev = adev;
3592                 c_irq_params->irq_src = int_params.irq_source;
3593
3594                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3595                                 dm_vupdate_high_irq, c_irq_params);
3596         }
3597
3598         /* Use GRPH_PFLIP interrupt */
3599         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3600                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3601                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3602                 if (r) {
3603                         DRM_ERROR("Failed to add page flip irq id!\n");
3604                         return r;
3605                 }
3606
3607                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3608                 int_params.irq_source =
3609                         dc_interrupt_to_irq_source(dc, i, 0);
3610
3611                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3612
3613                 c_irq_params->adev = adev;
3614                 c_irq_params->irq_src = int_params.irq_source;
3615
3616                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3617                                 dm_pflip_high_irq, c_irq_params);
3618
3619         }
3620
3621         /* HPD */
3622         r = amdgpu_irq_add_id(adev, client_id,
3623                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3624         if (r) {
3625                 DRM_ERROR("Failed to add hpd irq id!\n");
3626                 return r;
3627         }
3628
3629         register_hpd_handlers(adev);
3630
3631         return 0;
3632 }
3633
3634 /* Register IRQ sources and initialize IRQ callbacks */
3635 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
3636 {
3637         struct dc *dc = adev->dm.dc;
3638         struct common_irq_params *c_irq_params;
3639         struct dc_interrupt_params int_params = {0};
3640         int r;
3641         int i;
3642 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3643         static const unsigned int vrtl_int_srcid[] = {
3644                 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL,
3645                 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL,
3646                 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL,
3647                 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL,
3648                 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL,
3649                 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL
3650         };
3651 #endif
3652
3653         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3654         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3655
3656         /*
3657          * Actions of amdgpu_irq_add_id():
3658          * 1. Register a set() function with base driver.
3659          *    Base driver will call set() function to enable/disable an
3660          *    interrupt in DC hardware.
3661          * 2. Register amdgpu_dm_irq_handler().
3662          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3663          *    coming from DC hardware.
3664          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3665          *    for acknowledging and handling.
3666          */
3667
3668         /* Use VSTARTUP interrupt */
3669         for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
3670                         i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
3671                         i++) {
3672                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
3673
3674                 if (r) {
3675                         DRM_ERROR("Failed to add crtc irq id!\n");
3676                         return r;
3677                 }
3678
3679                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3680                 int_params.irq_source =
3681                         dc_interrupt_to_irq_source(dc, i, 0);
3682
3683                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3684
3685                 c_irq_params->adev = adev;
3686                 c_irq_params->irq_src = int_params.irq_source;
3687
3688                 amdgpu_dm_irq_register_interrupt(
3689                         adev, &int_params, dm_crtc_high_irq, c_irq_params);
3690         }
3691
3692         /* Use otg vertical line interrupt */
3693 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3694         for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) {
3695                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE,
3696                                 vrtl_int_srcid[i], &adev->vline0_irq);
3697
3698                 if (r) {
3699                         DRM_ERROR("Failed to add vline0 irq id!\n");
3700                         return r;
3701                 }
3702
3703                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3704                 int_params.irq_source =
3705                         dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0);
3706
3707                 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) {
3708                         DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]);
3709                         break;
3710                 }
3711
3712                 c_irq_params = &adev->dm.vline0_params[int_params.irq_source
3713                                         - DC_IRQ_SOURCE_DC1_VLINE0];
3714
3715                 c_irq_params->adev = adev;
3716                 c_irq_params->irq_src = int_params.irq_source;
3717
3718                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3719                                 dm_dcn_vertical_interrupt0_high_irq, c_irq_params);
3720         }
3721 #endif
3722
3723         /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
3724          * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
3725          * to trigger at end of each vblank, regardless of state of the lock,
3726          * matching DCE behaviour.
3727          */
3728         for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
3729              i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
3730              i++) {
3731                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
3732
3733                 if (r) {
3734                         DRM_ERROR("Failed to add vupdate irq id!\n");
3735                         return r;
3736                 }
3737
3738                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3739                 int_params.irq_source =
3740                         dc_interrupt_to_irq_source(dc, i, 0);
3741
3742                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3743
3744                 c_irq_params->adev = adev;
3745                 c_irq_params->irq_src = int_params.irq_source;
3746
3747                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3748                                 dm_vupdate_high_irq, c_irq_params);
3749         }
3750
3751         /* Use GRPH_PFLIP interrupt */
3752         for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
3753                         i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1;
3754                         i++) {
3755                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
3756                 if (r) {
3757                         DRM_ERROR("Failed to add page flip irq id!\n");
3758                         return r;
3759                 }
3760
3761                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3762                 int_params.irq_source =
3763                         dc_interrupt_to_irq_source(dc, i, 0);
3764
3765                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3766
3767                 c_irq_params->adev = adev;
3768                 c_irq_params->irq_src = int_params.irq_source;
3769
3770                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3771                                 dm_pflip_high_irq, c_irq_params);
3772
3773         }
3774
3775         /* HPD */
3776         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
3777                         &adev->hpd_irq);
3778         if (r) {
3779                 DRM_ERROR("Failed to add hpd irq id!\n");
3780                 return r;
3781         }
3782
3783         register_hpd_handlers(adev);
3784
3785         return 0;
3786 }
3787 /* Register Outbox IRQ sources and initialize IRQ callbacks */
3788 static int register_outbox_irq_handlers(struct amdgpu_device *adev)
3789 {
3790         struct dc *dc = adev->dm.dc;
3791         struct common_irq_params *c_irq_params;
3792         struct dc_interrupt_params int_params = {0};
3793         int r, i;
3794
3795         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3796         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3797
3798         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT,
3799                         &adev->dmub_outbox_irq);
3800         if (r) {
3801                 DRM_ERROR("Failed to add outbox irq id!\n");
3802                 return r;
3803         }
3804
3805         if (dc->ctx->dmub_srv) {
3806                 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT;
3807                 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3808                 int_params.irq_source =
3809                 dc_interrupt_to_irq_source(dc, i, 0);
3810
3811                 c_irq_params = &adev->dm.dmub_outbox_params[0];
3812
3813                 c_irq_params->adev = adev;
3814                 c_irq_params->irq_src = int_params.irq_source;
3815
3816                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3817                                 dm_dmub_outbox1_low_irq, c_irq_params);
3818         }
3819
3820         return 0;
3821 }
3822
3823 /*
3824  * Acquires the lock for the atomic state object and returns
3825  * the new atomic state.
3826  *
3827  * This should only be called during atomic check.
3828  */
3829 int dm_atomic_get_state(struct drm_atomic_state *state,
3830                         struct dm_atomic_state **dm_state)
3831 {
3832         struct drm_device *dev = state->dev;
3833         struct amdgpu_device *adev = drm_to_adev(dev);
3834         struct amdgpu_display_manager *dm = &adev->dm;
3835         struct drm_private_state *priv_state;
3836
3837         if (*dm_state)
3838                 return 0;
3839
3840         priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
3841         if (IS_ERR(priv_state))
3842                 return PTR_ERR(priv_state);
3843
3844         *dm_state = to_dm_atomic_state(priv_state);
3845
3846         return 0;
3847 }
3848
3849 static struct dm_atomic_state *
3850 dm_atomic_get_new_state(struct drm_atomic_state *state)
3851 {
3852         struct drm_device *dev = state->dev;
3853         struct amdgpu_device *adev = drm_to_adev(dev);
3854         struct amdgpu_display_manager *dm = &adev->dm;
3855         struct drm_private_obj *obj;
3856         struct drm_private_state *new_obj_state;
3857         int i;
3858
3859         for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
3860                 if (obj->funcs == dm->atomic_obj.funcs)
3861                         return to_dm_atomic_state(new_obj_state);
3862         }
3863
3864         return NULL;
3865 }
3866
3867 static struct drm_private_state *
3868 dm_atomic_duplicate_state(struct drm_private_obj *obj)
3869 {
3870         struct dm_atomic_state *old_state, *new_state;
3871
3872         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
3873         if (!new_state)
3874                 return NULL;
3875
3876         __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
3877
3878         old_state = to_dm_atomic_state(obj->state);
3879
3880         if (old_state && old_state->context)
3881                 new_state->context = dc_copy_state(old_state->context);
3882
3883         if (!new_state->context) {
3884                 kfree(new_state);
3885                 return NULL;
3886         }
3887
3888         return &new_state->base;
3889 }
3890
3891 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
3892                                     struct drm_private_state *state)
3893 {
3894         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
3895
3896         if (dm_state && dm_state->context)
3897                 dc_release_state(dm_state->context);
3898
3899         kfree(dm_state);
3900 }
3901
3902 static struct drm_private_state_funcs dm_atomic_state_funcs = {
3903         .atomic_duplicate_state = dm_atomic_duplicate_state,
3904         .atomic_destroy_state = dm_atomic_destroy_state,
3905 };
3906
3907 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
3908 {
3909         struct dm_atomic_state *state;
3910         int r;
3911
3912         adev->mode_info.mode_config_initialized = true;
3913
3914         adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
3915         adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
3916
3917         adev_to_drm(adev)->mode_config.max_width = 16384;
3918         adev_to_drm(adev)->mode_config.max_height = 16384;
3919
3920         adev_to_drm(adev)->mode_config.preferred_depth = 24;
3921         if (adev->asic_type == CHIP_HAWAII)
3922                 /* disable prefer shadow for now due to hibernation issues */
3923                 adev_to_drm(adev)->mode_config.prefer_shadow = 0;
3924         else
3925                 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
3926         /* indicates support for immediate flip */
3927         adev_to_drm(adev)->mode_config.async_page_flip = true;
3928
3929         state = kzalloc(sizeof(*state), GFP_KERNEL);
3930         if (!state)
3931                 return -ENOMEM;
3932
3933         state->context = dc_create_state(adev->dm.dc);
3934         if (!state->context) {
3935                 kfree(state);
3936                 return -ENOMEM;
3937         }
3938
3939         dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
3940
3941         drm_atomic_private_obj_init(adev_to_drm(adev),
3942                                     &adev->dm.atomic_obj,
3943                                     &state->base,
3944                                     &dm_atomic_state_funcs);
3945
3946         r = amdgpu_display_modeset_create_props(adev);
3947         if (r) {
3948                 dc_release_state(state->context);
3949                 kfree(state);
3950                 return r;
3951         }
3952
3953         r = amdgpu_dm_audio_init(adev);
3954         if (r) {
3955                 dc_release_state(state->context);
3956                 kfree(state);
3957                 return r;
3958         }
3959
3960         return 0;
3961 }
3962
3963 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
3964 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
3965 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
3966
3967 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
3968                                             int bl_idx)
3969 {
3970 #if defined(CONFIG_ACPI)
3971         struct amdgpu_dm_backlight_caps caps;
3972
3973         memset(&caps, 0, sizeof(caps));
3974
3975         if (dm->backlight_caps[bl_idx].caps_valid)
3976                 return;
3977
3978         amdgpu_acpi_get_backlight_caps(&caps);
3979         if (caps.caps_valid) {
3980                 dm->backlight_caps[bl_idx].caps_valid = true;
3981                 if (caps.aux_support)
3982                         return;
3983                 dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal;
3984                 dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal;
3985         } else {
3986                 dm->backlight_caps[bl_idx].min_input_signal =
3987                                 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
3988                 dm->backlight_caps[bl_idx].max_input_signal =
3989                                 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
3990         }
3991 #else
3992         if (dm->backlight_caps[bl_idx].aux_support)
3993                 return;
3994
3995         dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
3996         dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
3997 #endif
3998 }
3999
4000 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
4001                                 unsigned int *min, unsigned int *max)
4002 {
4003         if (!caps)
4004                 return 0;
4005
4006         if (caps->aux_support) {
4007                 // Firmware limits are in nits, DC API wants millinits.
4008                 *max = 1000 * caps->aux_max_input_signal;
4009                 *min = 1000 * caps->aux_min_input_signal;
4010         } else {
4011                 // Firmware limits are 8-bit, PWM control is 16-bit.
4012                 *max = 0x101 * caps->max_input_signal;
4013                 *min = 0x101 * caps->min_input_signal;
4014         }
4015         return 1;
4016 }
4017
4018 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
4019                                         uint32_t brightness)
4020 {
4021         unsigned int min, max;
4022
4023         if (!get_brightness_range(caps, &min, &max))
4024                 return brightness;
4025
4026         // Rescale 0..255 to min..max
4027         return min + DIV_ROUND_CLOSEST((max - min) * brightness,
4028                                        AMDGPU_MAX_BL_LEVEL);
4029 }
4030
4031 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
4032                                       uint32_t brightness)
4033 {
4034         unsigned int min, max;
4035
4036         if (!get_brightness_range(caps, &min, &max))
4037                 return brightness;
4038
4039         if (brightness < min)
4040                 return 0;
4041         // Rescale min..max to 0..255
4042         return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),
4043                                  max - min);
4044 }
4045
4046 static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
4047                                          int bl_idx,
4048                                          u32 user_brightness)
4049 {
4050         struct amdgpu_dm_backlight_caps caps;
4051         struct dc_link *link;
4052         u32 brightness;
4053         bool rc;
4054
4055         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4056         caps = dm->backlight_caps[bl_idx];
4057
4058         dm->brightness[bl_idx] = user_brightness;
4059         /* update scratch register */
4060         if (bl_idx == 0)
4061                 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]);
4062         brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]);
4063         link = (struct dc_link *)dm->backlight_link[bl_idx];
4064
4065         /* Change brightness based on AUX property */
4066         if (caps.aux_support) {
4067                 rc = dc_link_set_backlight_level_nits(link, true, brightness,
4068                                                       AUX_BL_DEFAULT_TRANSITION_TIME_MS);
4069                 if (!rc)
4070                         DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx);
4071         } else {
4072                 rc = dc_link_set_backlight_level(link, brightness, 0);
4073                 if (!rc)
4074                         DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx);
4075         }
4076
4077         if (rc)
4078                 dm->actual_brightness[bl_idx] = user_brightness;
4079 }
4080
4081 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
4082 {
4083         struct amdgpu_display_manager *dm = bl_get_data(bd);
4084         int i;
4085
4086         for (i = 0; i < dm->num_of_edps; i++) {
4087                 if (bd == dm->backlight_dev[i])
4088                         break;
4089         }
4090         if (i >= AMDGPU_DM_MAX_NUM_EDP)
4091                 i = 0;
4092         amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness);
4093
4094         return 0;
4095 }
4096
4097 static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm,
4098                                          int bl_idx)
4099 {
4100         int ret;
4101         struct amdgpu_dm_backlight_caps caps;
4102         struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx];
4103
4104         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4105         caps = dm->backlight_caps[bl_idx];
4106
4107         if (caps.aux_support) {
4108                 u32 avg, peak;
4109                 bool rc;
4110
4111                 rc = dc_link_get_backlight_level_nits(link, &avg, &peak);
4112                 if (!rc)
4113                         return dm->brightness[bl_idx];
4114                 return convert_brightness_to_user(&caps, avg);
4115         }
4116
4117         ret = dc_link_get_backlight_level(link);
4118
4119         if (ret == DC_ERROR_UNEXPECTED)
4120                 return dm->brightness[bl_idx];
4121
4122         return convert_brightness_to_user(&caps, ret);
4123 }
4124
4125 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
4126 {
4127         struct amdgpu_display_manager *dm = bl_get_data(bd);
4128         int i;
4129
4130         for (i = 0; i < dm->num_of_edps; i++) {
4131                 if (bd == dm->backlight_dev[i])
4132                         break;
4133         }
4134         if (i >= AMDGPU_DM_MAX_NUM_EDP)
4135                 i = 0;
4136         return amdgpu_dm_backlight_get_level(dm, i);
4137 }
4138
4139 static const struct backlight_ops amdgpu_dm_backlight_ops = {
4140         .options = BL_CORE_SUSPENDRESUME,
4141         .get_brightness = amdgpu_dm_backlight_get_brightness,
4142         .update_status  = amdgpu_dm_backlight_update_status,
4143 };
4144
4145 static void
4146 amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector)
4147 {
4148         struct drm_device *drm = aconnector->base.dev;
4149         struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm;
4150         struct backlight_properties props = { 0 };
4151         char bl_name[16];
4152
4153         if (aconnector->bl_idx == -1)
4154                 return;
4155
4156         if (!acpi_video_backlight_use_native()) {
4157                 drm_info(drm, "Skipping amdgpu DM backlight registration\n");
4158                 /* Try registering an ACPI video backlight device instead. */
4159                 acpi_video_register_backlight();
4160                 return;
4161         }
4162
4163         props.max_brightness = AMDGPU_MAX_BL_LEVEL;
4164         props.brightness = AMDGPU_MAX_BL_LEVEL;
4165         props.type = BACKLIGHT_RAW;
4166
4167         snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
4168                  drm->primary->index + aconnector->bl_idx);
4169
4170         dm->backlight_dev[aconnector->bl_idx] =
4171                 backlight_device_register(bl_name, aconnector->base.kdev, dm,
4172                                           &amdgpu_dm_backlight_ops, &props);
4173
4174         if (IS_ERR(dm->backlight_dev[aconnector->bl_idx])) {
4175                 DRM_ERROR("DM: Backlight registration failed!\n");
4176                 dm->backlight_dev[aconnector->bl_idx] = NULL;
4177         } else
4178                 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4179 }
4180
4181 static int initialize_plane(struct amdgpu_display_manager *dm,
4182                             struct amdgpu_mode_info *mode_info, int plane_id,
4183                             enum drm_plane_type plane_type,
4184                             const struct dc_plane_cap *plane_cap)
4185 {
4186         struct drm_plane *plane;
4187         unsigned long possible_crtcs;
4188         int ret = 0;
4189
4190         plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
4191         if (!plane) {
4192                 DRM_ERROR("KMS: Failed to allocate plane\n");
4193                 return -ENOMEM;
4194         }
4195         plane->type = plane_type;
4196
4197         /*
4198          * HACK: IGT tests expect that the primary plane for a CRTC
4199          * can only have one possible CRTC. Only expose support for
4200          * any CRTC if they're not going to be used as a primary plane
4201          * for a CRTC - like overlay or underlay planes.
4202          */
4203         possible_crtcs = 1 << plane_id;
4204         if (plane_id >= dm->dc->caps.max_streams)
4205                 possible_crtcs = 0xff;
4206
4207         ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
4208
4209         if (ret) {
4210                 DRM_ERROR("KMS: Failed to initialize plane\n");
4211                 kfree(plane);
4212                 return ret;
4213         }
4214
4215         if (mode_info)
4216                 mode_info->planes[plane_id] = plane;
4217
4218         return ret;
4219 }
4220
4221
4222 static void setup_backlight_device(struct amdgpu_display_manager *dm,
4223                                    struct amdgpu_dm_connector *aconnector)
4224 {
4225         struct dc_link *link = aconnector->dc_link;
4226         int bl_idx = dm->num_of_edps;
4227
4228         if (!(link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) ||
4229             link->type == dc_connection_none)
4230                 return;
4231
4232         if (dm->num_of_edps >= AMDGPU_DM_MAX_NUM_EDP) {
4233                 drm_warn(adev_to_drm(dm->adev), "Too much eDP connections, skipping backlight setup for additional eDPs\n");
4234                 return;
4235         }
4236
4237         aconnector->bl_idx = bl_idx;
4238
4239         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4240         dm->brightness[bl_idx] = AMDGPU_MAX_BL_LEVEL;
4241         dm->backlight_link[bl_idx] = link;
4242         dm->num_of_edps++;
4243
4244         update_connector_ext_caps(aconnector);
4245 }
4246
4247 static void amdgpu_set_panel_orientation(struct drm_connector *connector);
4248
4249 /*
4250  * In this architecture, the association
4251  * connector -> encoder -> crtc
4252  * id not really requried. The crtc and connector will hold the
4253  * display_index as an abstraction to use with DAL component
4254  *
4255  * Returns 0 on success
4256  */
4257 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4258 {
4259         struct amdgpu_display_manager *dm = &adev->dm;
4260         s32 i;
4261         struct amdgpu_dm_connector *aconnector = NULL;
4262         struct amdgpu_encoder *aencoder = NULL;
4263         struct amdgpu_mode_info *mode_info = &adev->mode_info;
4264         u32 link_cnt;
4265         s32 primary_planes;
4266         enum dc_connection_type new_connection_type = dc_connection_none;
4267         const struct dc_plane_cap *plane;
4268         bool psr_feature_enabled = false;
4269         bool replay_feature_enabled = false;
4270         int max_overlay = dm->dc->caps.max_slave_planes;
4271
4272         dm->display_indexes_num = dm->dc->caps.max_streams;
4273         /* Update the actual used number of crtc */
4274         adev->mode_info.num_crtc = adev->dm.display_indexes_num;
4275
4276         amdgpu_dm_set_irq_funcs(adev);
4277
4278         link_cnt = dm->dc->caps.max_links;
4279         if (amdgpu_dm_mode_config_init(dm->adev)) {
4280                 DRM_ERROR("DM: Failed to initialize mode config\n");
4281                 return -EINVAL;
4282         }
4283
4284         /* There is one primary plane per CRTC */
4285         primary_planes = dm->dc->caps.max_streams;
4286         ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
4287
4288         /*
4289          * Initialize primary planes, implicit planes for legacy IOCTLS.
4290          * Order is reversed to match iteration order in atomic check.
4291          */
4292         for (i = (primary_planes - 1); i >= 0; i--) {
4293                 plane = &dm->dc->caps.planes[i];
4294
4295                 if (initialize_plane(dm, mode_info, i,
4296                                      DRM_PLANE_TYPE_PRIMARY, plane)) {
4297                         DRM_ERROR("KMS: Failed to initialize primary plane\n");
4298                         goto fail;
4299                 }
4300         }
4301
4302         /*
4303          * Initialize overlay planes, index starting after primary planes.
4304          * These planes have a higher DRM index than the primary planes since
4305          * they should be considered as having a higher z-order.
4306          * Order is reversed to match iteration order in atomic check.
4307          *
4308          * Only support DCN for now, and only expose one so we don't encourage
4309          * userspace to use up all the pipes.
4310          */
4311         for (i = 0; i < dm->dc->caps.max_planes; ++i) {
4312                 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
4313
4314                 /* Do not create overlay if MPO disabled */
4315                 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO)
4316                         break;
4317
4318                 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
4319                         continue;
4320
4321                 if (!plane->pixel_format_support.argb8888)
4322                         continue;
4323
4324                 if (max_overlay-- == 0)
4325                         break;
4326
4327                 if (initialize_plane(dm, NULL, primary_planes + i,
4328                                      DRM_PLANE_TYPE_OVERLAY, plane)) {
4329                         DRM_ERROR("KMS: Failed to initialize overlay plane\n");
4330                         goto fail;
4331                 }
4332         }
4333
4334         for (i = 0; i < dm->dc->caps.max_streams; i++)
4335                 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
4336                         DRM_ERROR("KMS: Failed to initialize crtc\n");
4337                         goto fail;
4338                 }
4339
4340         /* Use Outbox interrupt */
4341         switch (adev->ip_versions[DCE_HWIP][0]) {
4342         case IP_VERSION(3, 0, 0):
4343         case IP_VERSION(3, 1, 2):
4344         case IP_VERSION(3, 1, 3):
4345         case IP_VERSION(3, 1, 4):
4346         case IP_VERSION(3, 1, 5):
4347         case IP_VERSION(3, 1, 6):
4348         case IP_VERSION(3, 2, 0):
4349         case IP_VERSION(3, 2, 1):
4350         case IP_VERSION(2, 1, 0):
4351                 if (register_outbox_irq_handlers(dm->adev)) {
4352                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4353                         goto fail;
4354                 }
4355                 break;
4356         default:
4357                 DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",
4358                               adev->ip_versions[DCE_HWIP][0]);
4359         }
4360
4361         /* Determine whether to enable PSR support by default. */
4362         if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) {
4363                 switch (adev->ip_versions[DCE_HWIP][0]) {
4364                 case IP_VERSION(3, 1, 2):
4365                 case IP_VERSION(3, 1, 3):
4366                 case IP_VERSION(3, 1, 4):
4367                 case IP_VERSION(3, 1, 5):
4368                 case IP_VERSION(3, 1, 6):
4369                 case IP_VERSION(3, 2, 0):
4370                 case IP_VERSION(3, 2, 1):
4371                         psr_feature_enabled = true;
4372                         break;
4373                 default:
4374                         psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK;
4375                         break;
4376                 }
4377         }
4378
4379         if (!(amdgpu_dc_debug_mask & DC_DISABLE_REPLAY)) {
4380                 switch (adev->ip_versions[DCE_HWIP][0]) {
4381                 case IP_VERSION(3, 1, 4):
4382                 case IP_VERSION(3, 1, 5):
4383                 case IP_VERSION(3, 1, 6):
4384                 case IP_VERSION(3, 2, 0):
4385                 case IP_VERSION(3, 2, 1):
4386                         replay_feature_enabled = true;
4387                         break;
4388                 default:
4389                         replay_feature_enabled = amdgpu_dc_feature_mask & DC_REPLAY_MASK;
4390                         break;
4391                 }
4392         }
4393         /* loops over all connectors on the board */
4394         for (i = 0; i < link_cnt; i++) {
4395                 struct dc_link *link = NULL;
4396
4397                 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
4398                         DRM_ERROR(
4399                                 "KMS: Cannot support more than %d display indexes\n",
4400                                         AMDGPU_DM_MAX_DISPLAY_INDEX);
4401                         continue;
4402                 }
4403
4404                 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
4405                 if (!aconnector)
4406                         goto fail;
4407
4408                 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
4409                 if (!aencoder)
4410                         goto fail;
4411
4412                 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
4413                         DRM_ERROR("KMS: Failed to initialize encoder\n");
4414                         goto fail;
4415                 }
4416
4417                 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
4418                         DRM_ERROR("KMS: Failed to initialize connector\n");
4419                         goto fail;
4420                 }
4421
4422                 link = dc_get_link_at_index(dm->dc, i);
4423
4424                 if (!dc_link_detect_connection_type(link, &new_connection_type))
4425                         DRM_ERROR("KMS: Failed to detect connector\n");
4426
4427                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
4428                         emulated_link_detect(link);
4429                         amdgpu_dm_update_connector_after_detect(aconnector);
4430                 } else {
4431                         bool ret = false;
4432
4433                         mutex_lock(&dm->dc_lock);
4434                         ret = dc_link_detect(link, DETECT_REASON_BOOT);
4435                         mutex_unlock(&dm->dc_lock);
4436
4437                         if (ret) {
4438                                 amdgpu_dm_update_connector_after_detect(aconnector);
4439                                 setup_backlight_device(dm, aconnector);
4440
4441                                 /*
4442                                  * Disable psr if replay can be enabled
4443                                  */
4444                                 if (replay_feature_enabled && amdgpu_dm_setup_replay(link, aconnector))
4445                                         psr_feature_enabled = false;
4446
4447                                 if (psr_feature_enabled)
4448                                         amdgpu_dm_set_psr_caps(link);
4449
4450                                 /* TODO: Fix vblank control helpers to delay PSR entry to allow this when
4451                                  * PSR is also supported.
4452                                  */
4453                                 if (link->psr_settings.psr_feature_enabled)
4454                                         adev_to_drm(adev)->vblank_disable_immediate = false;
4455                         }
4456                 }
4457                 amdgpu_set_panel_orientation(&aconnector->base);
4458         }
4459
4460         /* Software is initialized. Now we can register interrupt handlers. */
4461         switch (adev->asic_type) {
4462 #if defined(CONFIG_DRM_AMD_DC_SI)
4463         case CHIP_TAHITI:
4464         case CHIP_PITCAIRN:
4465         case CHIP_VERDE:
4466         case CHIP_OLAND:
4467                 if (dce60_register_irq_handlers(dm->adev)) {
4468                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4469                         goto fail;
4470                 }
4471                 break;
4472 #endif
4473         case CHIP_BONAIRE:
4474         case CHIP_HAWAII:
4475         case CHIP_KAVERI:
4476         case CHIP_KABINI:
4477         case CHIP_MULLINS:
4478         case CHIP_TONGA:
4479         case CHIP_FIJI:
4480         case CHIP_CARRIZO:
4481         case CHIP_STONEY:
4482         case CHIP_POLARIS11:
4483         case CHIP_POLARIS10:
4484         case CHIP_POLARIS12:
4485         case CHIP_VEGAM:
4486         case CHIP_VEGA10:
4487         case CHIP_VEGA12:
4488         case CHIP_VEGA20:
4489                 if (dce110_register_irq_handlers(dm->adev)) {
4490                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4491                         goto fail;
4492                 }
4493                 break;
4494         default:
4495                 switch (adev->ip_versions[DCE_HWIP][0]) {
4496                 case IP_VERSION(1, 0, 0):
4497                 case IP_VERSION(1, 0, 1):
4498                 case IP_VERSION(2, 0, 2):
4499                 case IP_VERSION(2, 0, 3):
4500                 case IP_VERSION(2, 0, 0):
4501                 case IP_VERSION(2, 1, 0):
4502                 case IP_VERSION(3, 0, 0):
4503                 case IP_VERSION(3, 0, 2):
4504                 case IP_VERSION(3, 0, 3):
4505                 case IP_VERSION(3, 0, 1):
4506                 case IP_VERSION(3, 1, 2):
4507                 case IP_VERSION(3, 1, 3):
4508                 case IP_VERSION(3, 1, 4):
4509                 case IP_VERSION(3, 1, 5):
4510                 case IP_VERSION(3, 1, 6):
4511                 case IP_VERSION(3, 2, 0):
4512                 case IP_VERSION(3, 2, 1):
4513                         if (dcn10_register_irq_handlers(dm->adev)) {
4514                                 DRM_ERROR("DM: Failed to initialize IRQ\n");
4515                                 goto fail;
4516                         }
4517                         break;
4518                 default:
4519                         DRM_ERROR("Unsupported DCE IP versions: 0x%X\n",
4520                                         adev->ip_versions[DCE_HWIP][0]);
4521                         goto fail;
4522                 }
4523                 break;
4524         }
4525
4526         return 0;
4527 fail:
4528         kfree(aencoder);
4529         kfree(aconnector);
4530
4531         return -EINVAL;
4532 }
4533
4534 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4535 {
4536         drm_atomic_private_obj_fini(&dm->atomic_obj);
4537 }
4538
4539 /******************************************************************************
4540  * amdgpu_display_funcs functions
4541  *****************************************************************************/
4542
4543 /*
4544  * dm_bandwidth_update - program display watermarks
4545  *
4546  * @adev: amdgpu_device pointer
4547  *
4548  * Calculate and program the display watermarks and line buffer allocation.
4549  */
4550 static void dm_bandwidth_update(struct amdgpu_device *adev)
4551 {
4552         /* TODO: implement later */
4553 }
4554
4555 static const struct amdgpu_display_funcs dm_display_funcs = {
4556         .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
4557         .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
4558         .backlight_set_level = NULL, /* never called for DC */
4559         .backlight_get_level = NULL, /* never called for DC */
4560         .hpd_sense = NULL,/* called unconditionally */
4561         .hpd_set_polarity = NULL, /* called unconditionally */
4562         .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4563         .page_flip_get_scanoutpos =
4564                 dm_crtc_get_scanoutpos,/* called unconditionally */
4565         .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
4566         .add_connector = NULL, /* VBIOS parsing. DAL does it. */
4567 };
4568
4569 #if defined(CONFIG_DEBUG_KERNEL_DC)
4570
4571 static ssize_t s3_debug_store(struct device *device,
4572                               struct device_attribute *attr,
4573                               const char *buf,
4574                               size_t count)
4575 {
4576         int ret;
4577         int s3_state;
4578         struct drm_device *drm_dev = dev_get_drvdata(device);
4579         struct amdgpu_device *adev = drm_to_adev(drm_dev);
4580
4581         ret = kstrtoint(buf, 0, &s3_state);
4582
4583         if (ret == 0) {
4584                 if (s3_state) {
4585                         dm_resume(adev);
4586                         drm_kms_helper_hotplug_event(adev_to_drm(adev));
4587                 } else
4588                         dm_suspend(adev);
4589         }
4590
4591         return ret == 0 ? count : 0;
4592 }
4593
4594 DEVICE_ATTR_WO(s3_debug);
4595
4596 #endif
4597
4598 static int dm_init_microcode(struct amdgpu_device *adev)
4599 {
4600         char *fw_name_dmub;
4601         int r;
4602
4603         switch (adev->ip_versions[DCE_HWIP][0]) {
4604         case IP_VERSION(2, 1, 0):
4605                 fw_name_dmub = FIRMWARE_RENOIR_DMUB;
4606                 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
4607                         fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
4608                 break;
4609         case IP_VERSION(3, 0, 0):
4610                 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
4611                         fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
4612                 else
4613                         fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
4614                 break;
4615         case IP_VERSION(3, 0, 1):
4616                 fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
4617                 break;
4618         case IP_VERSION(3, 0, 2):
4619                 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
4620                 break;
4621         case IP_VERSION(3, 0, 3):
4622                 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;
4623                 break;
4624         case IP_VERSION(3, 1, 2):
4625         case IP_VERSION(3, 1, 3):
4626                 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
4627                 break;
4628         case IP_VERSION(3, 1, 4):
4629                 fw_name_dmub = FIRMWARE_DCN_314_DMUB;
4630                 break;
4631         case IP_VERSION(3, 1, 5):
4632                 fw_name_dmub = FIRMWARE_DCN_315_DMUB;
4633                 break;
4634         case IP_VERSION(3, 1, 6):
4635                 fw_name_dmub = FIRMWARE_DCN316_DMUB;
4636                 break;
4637         case IP_VERSION(3, 2, 0):
4638                 fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB;
4639                 break;
4640         case IP_VERSION(3, 2, 1):
4641                 fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB;
4642                 break;
4643         default:
4644                 /* ASIC doesn't support DMUB. */
4645                 return 0;
4646         }
4647         r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, fw_name_dmub);
4648         if (r)
4649                 DRM_ERROR("DMUB firmware loading failed: %d\n", r);
4650         return r;
4651 }
4652
4653 static int dm_early_init(void *handle)
4654 {
4655         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4656         struct amdgpu_mode_info *mode_info = &adev->mode_info;
4657         struct atom_context *ctx = mode_info->atom_context;
4658         int index = GetIndexIntoMasterTable(DATA, Object_Header);
4659         u16 data_offset;
4660
4661         /* if there is no object header, skip DM */
4662         if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
4663                 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
4664                 dev_info(adev->dev, "No object header, skipping DM\n");
4665                 return -ENOENT;
4666         }
4667
4668         switch (adev->asic_type) {
4669 #if defined(CONFIG_DRM_AMD_DC_SI)
4670         case CHIP_TAHITI:
4671         case CHIP_PITCAIRN:
4672         case CHIP_VERDE:
4673                 adev->mode_info.num_crtc = 6;
4674                 adev->mode_info.num_hpd = 6;
4675                 adev->mode_info.num_dig = 6;
4676                 break;
4677         case CHIP_OLAND:
4678                 adev->mode_info.num_crtc = 2;
4679                 adev->mode_info.num_hpd = 2;
4680                 adev->mode_info.num_dig = 2;
4681                 break;
4682 #endif
4683         case CHIP_BONAIRE:
4684         case CHIP_HAWAII:
4685                 adev->mode_info.num_crtc = 6;
4686                 adev->mode_info.num_hpd = 6;
4687                 adev->mode_info.num_dig = 6;
4688                 break;
4689         case CHIP_KAVERI:
4690                 adev->mode_info.num_crtc = 4;
4691                 adev->mode_info.num_hpd = 6;
4692                 adev->mode_info.num_dig = 7;
4693                 break;
4694         case CHIP_KABINI:
4695         case CHIP_MULLINS:
4696                 adev->mode_info.num_crtc = 2;
4697                 adev->mode_info.num_hpd = 6;
4698                 adev->mode_info.num_dig = 6;
4699                 break;
4700         case CHIP_FIJI:
4701         case CHIP_TONGA:
4702                 adev->mode_info.num_crtc = 6;
4703                 adev->mode_info.num_hpd = 6;
4704                 adev->mode_info.num_dig = 7;
4705                 break;
4706         case CHIP_CARRIZO:
4707                 adev->mode_info.num_crtc = 3;
4708                 adev->mode_info.num_hpd = 6;
4709                 adev->mode_info.num_dig = 9;
4710                 break;
4711         case CHIP_STONEY:
4712                 adev->mode_info.num_crtc = 2;
4713                 adev->mode_info.num_hpd = 6;
4714                 adev->mode_info.num_dig = 9;
4715                 break;
4716         case CHIP_POLARIS11:
4717         case CHIP_POLARIS12:
4718                 adev->mode_info.num_crtc = 5;
4719                 adev->mode_info.num_hpd = 5;
4720                 adev->mode_info.num_dig = 5;
4721                 break;
4722         case CHIP_POLARIS10:
4723         case CHIP_VEGAM:
4724                 adev->mode_info.num_crtc = 6;
4725                 adev->mode_info.num_hpd = 6;
4726                 adev->mode_info.num_dig = 6;
4727                 break;
4728         case CHIP_VEGA10:
4729         case CHIP_VEGA12:
4730         case CHIP_VEGA20:
4731                 adev->mode_info.num_crtc = 6;
4732                 adev->mode_info.num_hpd = 6;
4733                 adev->mode_info.num_dig = 6;
4734                 break;
4735         default:
4736
4737                 switch (adev->ip_versions[DCE_HWIP][0]) {
4738                 case IP_VERSION(2, 0, 2):
4739                 case IP_VERSION(3, 0, 0):
4740                         adev->mode_info.num_crtc = 6;
4741                         adev->mode_info.num_hpd = 6;
4742                         adev->mode_info.num_dig = 6;
4743                         break;
4744                 case IP_VERSION(2, 0, 0):
4745                 case IP_VERSION(3, 0, 2):
4746                         adev->mode_info.num_crtc = 5;
4747                         adev->mode_info.num_hpd = 5;
4748                         adev->mode_info.num_dig = 5;
4749                         break;
4750                 case IP_VERSION(2, 0, 3):
4751                 case IP_VERSION(3, 0, 3):
4752                         adev->mode_info.num_crtc = 2;
4753                         adev->mode_info.num_hpd = 2;
4754                         adev->mode_info.num_dig = 2;
4755                         break;
4756                 case IP_VERSION(1, 0, 0):
4757                 case IP_VERSION(1, 0, 1):
4758                 case IP_VERSION(3, 0, 1):
4759                 case IP_VERSION(2, 1, 0):
4760                 case IP_VERSION(3, 1, 2):
4761                 case IP_VERSION(3, 1, 3):
4762                 case IP_VERSION(3, 1, 4):
4763                 case IP_VERSION(3, 1, 5):
4764                 case IP_VERSION(3, 1, 6):
4765                 case IP_VERSION(3, 2, 0):
4766                 case IP_VERSION(3, 2, 1):
4767                         adev->mode_info.num_crtc = 4;
4768                         adev->mode_info.num_hpd = 4;
4769                         adev->mode_info.num_dig = 4;
4770                         break;
4771                 default:
4772                         DRM_ERROR("Unsupported DCE IP versions: 0x%x\n",
4773                                         adev->ip_versions[DCE_HWIP][0]);
4774                         return -EINVAL;
4775                 }
4776                 break;
4777         }
4778
4779         if (adev->mode_info.funcs == NULL)
4780                 adev->mode_info.funcs = &dm_display_funcs;
4781
4782         /*
4783          * Note: Do NOT change adev->audio_endpt_rreg and
4784          * adev->audio_endpt_wreg because they are initialised in
4785          * amdgpu_device_init()
4786          */
4787 #if defined(CONFIG_DEBUG_KERNEL_DC)
4788         device_create_file(
4789                 adev_to_drm(adev)->dev,
4790                 &dev_attr_s3_debug);
4791 #endif
4792         adev->dc_enabled = true;
4793
4794         return dm_init_microcode(adev);
4795 }
4796
4797 static bool modereset_required(struct drm_crtc_state *crtc_state)
4798 {
4799         return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
4800 }
4801
4802 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
4803 {
4804         drm_encoder_cleanup(encoder);
4805         kfree(encoder);
4806 }
4807
4808 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
4809         .destroy = amdgpu_dm_encoder_destroy,
4810 };
4811
4812 static int
4813 fill_plane_color_attributes(const struct drm_plane_state *plane_state,
4814                             const enum surface_pixel_format format,
4815                             enum dc_color_space *color_space)
4816 {
4817         bool full_range;
4818
4819         *color_space = COLOR_SPACE_SRGB;
4820
4821         /* DRM color properties only affect non-RGB formats. */
4822         if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
4823                 return 0;
4824
4825         full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
4826
4827         switch (plane_state->color_encoding) {
4828         case DRM_COLOR_YCBCR_BT601:
4829                 if (full_range)
4830                         *color_space = COLOR_SPACE_YCBCR601;
4831                 else
4832                         *color_space = COLOR_SPACE_YCBCR601_LIMITED;
4833                 break;
4834
4835         case DRM_COLOR_YCBCR_BT709:
4836                 if (full_range)
4837                         *color_space = COLOR_SPACE_YCBCR709;
4838                 else
4839                         *color_space = COLOR_SPACE_YCBCR709_LIMITED;
4840                 break;
4841
4842         case DRM_COLOR_YCBCR_BT2020:
4843                 if (full_range)
4844                         *color_space = COLOR_SPACE_2020_YCBCR;
4845                 else
4846                         return -EINVAL;
4847                 break;
4848
4849         default:
4850                 return -EINVAL;
4851         }
4852
4853         return 0;
4854 }
4855
4856 static int
4857 fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
4858                             const struct drm_plane_state *plane_state,
4859                             const u64 tiling_flags,
4860                             struct dc_plane_info *plane_info,
4861                             struct dc_plane_address *address,
4862                             bool tmz_surface,
4863                             bool force_disable_dcc)
4864 {
4865         const struct drm_framebuffer *fb = plane_state->fb;
4866         const struct amdgpu_framebuffer *afb =
4867                 to_amdgpu_framebuffer(plane_state->fb);
4868         int ret;
4869
4870         memset(plane_info, 0, sizeof(*plane_info));
4871
4872         switch (fb->format->format) {
4873         case DRM_FORMAT_C8:
4874                 plane_info->format =
4875                         SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
4876                 break;
4877         case DRM_FORMAT_RGB565:
4878                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
4879                 break;
4880         case DRM_FORMAT_XRGB8888:
4881         case DRM_FORMAT_ARGB8888:
4882                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
4883                 break;
4884         case DRM_FORMAT_XRGB2101010:
4885         case DRM_FORMAT_ARGB2101010:
4886                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
4887                 break;
4888         case DRM_FORMAT_XBGR2101010:
4889         case DRM_FORMAT_ABGR2101010:
4890                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
4891                 break;
4892         case DRM_FORMAT_XBGR8888:
4893         case DRM_FORMAT_ABGR8888:
4894                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
4895                 break;
4896         case DRM_FORMAT_NV21:
4897                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
4898                 break;
4899         case DRM_FORMAT_NV12:
4900                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
4901                 break;
4902         case DRM_FORMAT_P010:
4903                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb;
4904                 break;
4905         case DRM_FORMAT_XRGB16161616F:
4906         case DRM_FORMAT_ARGB16161616F:
4907                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F;
4908                 break;
4909         case DRM_FORMAT_XBGR16161616F:
4910         case DRM_FORMAT_ABGR16161616F:
4911                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;
4912                 break;
4913         case DRM_FORMAT_XRGB16161616:
4914         case DRM_FORMAT_ARGB16161616:
4915                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616;
4916                 break;
4917         case DRM_FORMAT_XBGR16161616:
4918         case DRM_FORMAT_ABGR16161616:
4919                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616;
4920                 break;
4921         default:
4922                 DRM_ERROR(
4923                         "Unsupported screen format %p4cc\n",
4924                         &fb->format->format);
4925                 return -EINVAL;
4926         }
4927
4928         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
4929         case DRM_MODE_ROTATE_0:
4930                 plane_info->rotation = ROTATION_ANGLE_0;
4931                 break;
4932         case DRM_MODE_ROTATE_90:
4933                 plane_info->rotation = ROTATION_ANGLE_90;
4934                 break;
4935         case DRM_MODE_ROTATE_180:
4936                 plane_info->rotation = ROTATION_ANGLE_180;
4937                 break;
4938         case DRM_MODE_ROTATE_270:
4939                 plane_info->rotation = ROTATION_ANGLE_270;
4940                 break;
4941         default:
4942                 plane_info->rotation = ROTATION_ANGLE_0;
4943                 break;
4944         }
4945
4946
4947         plane_info->visible = true;
4948         plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
4949
4950         plane_info->layer_index = plane_state->normalized_zpos;
4951
4952         ret = fill_plane_color_attributes(plane_state, plane_info->format,
4953                                           &plane_info->color_space);
4954         if (ret)
4955                 return ret;
4956
4957         ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format,
4958                                            plane_info->rotation, tiling_flags,
4959                                            &plane_info->tiling_info,
4960                                            &plane_info->plane_size,
4961                                            &plane_info->dcc, address,
4962                                            tmz_surface, force_disable_dcc);
4963         if (ret)
4964                 return ret;
4965
4966         amdgpu_dm_plane_fill_blending_from_plane_state(
4967                 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha,
4968                 &plane_info->global_alpha, &plane_info->global_alpha_value);
4969
4970         return 0;
4971 }
4972
4973 static int fill_dc_plane_attributes(struct amdgpu_device *adev,
4974                                     struct dc_plane_state *dc_plane_state,
4975                                     struct drm_plane_state *plane_state,
4976                                     struct drm_crtc_state *crtc_state)
4977 {
4978         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
4979         struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb;
4980         struct dc_scaling_info scaling_info;
4981         struct dc_plane_info plane_info;
4982         int ret;
4983         bool force_disable_dcc = false;
4984
4985         ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info);
4986         if (ret)
4987                 return ret;
4988
4989         dc_plane_state->src_rect = scaling_info.src_rect;
4990         dc_plane_state->dst_rect = scaling_info.dst_rect;
4991         dc_plane_state->clip_rect = scaling_info.clip_rect;
4992         dc_plane_state->scaling_quality = scaling_info.scaling_quality;
4993
4994         force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
4995         ret = fill_dc_plane_info_and_addr(adev, plane_state,
4996                                           afb->tiling_flags,
4997                                           &plane_info,
4998                                           &dc_plane_state->address,
4999                                           afb->tmz_surface,
5000                                           force_disable_dcc);
5001         if (ret)
5002                 return ret;
5003
5004         dc_plane_state->format = plane_info.format;
5005         dc_plane_state->color_space = plane_info.color_space;
5006         dc_plane_state->format = plane_info.format;
5007         dc_plane_state->plane_size = plane_info.plane_size;
5008         dc_plane_state->rotation = plane_info.rotation;
5009         dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
5010         dc_plane_state->stereo_format = plane_info.stereo_format;
5011         dc_plane_state->tiling_info = plane_info.tiling_info;
5012         dc_plane_state->visible = plane_info.visible;
5013         dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
5014         dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha;
5015         dc_plane_state->global_alpha = plane_info.global_alpha;
5016         dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
5017         dc_plane_state->dcc = plane_info.dcc;
5018         dc_plane_state->layer_index = plane_info.layer_index;
5019         dc_plane_state->flip_int_enabled = true;
5020
5021         /*
5022          * Always set input transfer function, since plane state is refreshed
5023          * every time.
5024          */
5025         ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
5026         if (ret)
5027                 return ret;
5028
5029         return 0;
5030 }
5031
5032 static inline void fill_dc_dirty_rect(struct drm_plane *plane,
5033                                       struct rect *dirty_rect, int32_t x,
5034                                       s32 y, s32 width, s32 height,
5035                                       int *i, bool ffu)
5036 {
5037         WARN_ON(*i >= DC_MAX_DIRTY_RECTS);
5038
5039         dirty_rect->x = x;
5040         dirty_rect->y = y;
5041         dirty_rect->width = width;
5042         dirty_rect->height = height;
5043
5044         if (ffu)
5045                 drm_dbg(plane->dev,
5046                         "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n",
5047                         plane->base.id, width, height);
5048         else
5049                 drm_dbg(plane->dev,
5050                         "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)",
5051                         plane->base.id, x, y, width, height);
5052
5053         (*i)++;
5054 }
5055
5056 /**
5057  * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates
5058  *
5059  * @plane: DRM plane containing dirty regions that need to be flushed to the eDP
5060  *         remote fb
5061  * @old_plane_state: Old state of @plane
5062  * @new_plane_state: New state of @plane
5063  * @crtc_state: New state of CRTC connected to the @plane
5064  * @flip_addrs: DC flip tracking struct, which also tracts dirty rects
5065  * @dirty_regions_changed: dirty regions changed
5066  *
5067  * For PSR SU, DC informs the DMUB uController of dirty rectangle regions
5068  * (referred to as "damage clips" in DRM nomenclature) that require updating on
5069  * the eDP remote buffer. The responsibility of specifying the dirty regions is
5070  * amdgpu_dm's.
5071  *
5072  * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the
5073  * plane with regions that require flushing to the eDP remote buffer. In
5074  * addition, certain use cases - such as cursor and multi-plane overlay (MPO) -
5075  * implicitly provide damage clips without any client support via the plane
5076  * bounds.
5077  */
5078 static void fill_dc_dirty_rects(struct drm_plane *plane,
5079                                 struct drm_plane_state *old_plane_state,
5080                                 struct drm_plane_state *new_plane_state,
5081                                 struct drm_crtc_state *crtc_state,
5082                                 struct dc_flip_addrs *flip_addrs,
5083                                 bool *dirty_regions_changed)
5084 {
5085         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5086         struct rect *dirty_rects = flip_addrs->dirty_rects;
5087         u32 num_clips;
5088         struct drm_mode_rect *clips;
5089         bool bb_changed;
5090         bool fb_changed;
5091         u32 i = 0;
5092         *dirty_regions_changed = false;
5093
5094         /*
5095          * Cursor plane has it's own dirty rect update interface. See
5096          * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data
5097          */
5098         if (plane->type == DRM_PLANE_TYPE_CURSOR)
5099                 return;
5100
5101         num_clips = drm_plane_get_damage_clips_count(new_plane_state);
5102         clips = drm_plane_get_damage_clips(new_plane_state);
5103
5104         if (!dm_crtc_state->mpo_requested) {
5105                 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS)
5106                         goto ffu;
5107
5108                 for (; flip_addrs->dirty_rect_count < num_clips; clips++)
5109                         fill_dc_dirty_rect(new_plane_state->plane,
5110                                            &dirty_rects[flip_addrs->dirty_rect_count],
5111                                            clips->x1, clips->y1,
5112                                            clips->x2 - clips->x1, clips->y2 - clips->y1,
5113                                            &flip_addrs->dirty_rect_count,
5114                                            false);
5115                 return;
5116         }
5117
5118         /*
5119          * MPO is requested. Add entire plane bounding box to dirty rects if
5120          * flipped to or damaged.
5121          *
5122          * If plane is moved or resized, also add old bounding box to dirty
5123          * rects.
5124          */
5125         fb_changed = old_plane_state->fb->base.id !=
5126                      new_plane_state->fb->base.id;
5127         bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x ||
5128                       old_plane_state->crtc_y != new_plane_state->crtc_y ||
5129                       old_plane_state->crtc_w != new_plane_state->crtc_w ||
5130                       old_plane_state->crtc_h != new_plane_state->crtc_h);
5131
5132         drm_dbg(plane->dev,
5133                 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n",
5134                 new_plane_state->plane->base.id,
5135                 bb_changed, fb_changed, num_clips);
5136
5137         *dirty_regions_changed = bb_changed;
5138
5139         if ((num_clips + (bb_changed ? 2 : 0)) > DC_MAX_DIRTY_RECTS)
5140                 goto ffu;
5141
5142         if (bb_changed) {
5143                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5144                                    new_plane_state->crtc_x,
5145                                    new_plane_state->crtc_y,
5146                                    new_plane_state->crtc_w,
5147                                    new_plane_state->crtc_h, &i, false);
5148
5149                 /* Add old plane bounding-box if plane is moved or resized */
5150                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5151                                    old_plane_state->crtc_x,
5152                                    old_plane_state->crtc_y,
5153                                    old_plane_state->crtc_w,
5154                                    old_plane_state->crtc_h, &i, false);
5155         }
5156
5157         if (num_clips) {
5158                 for (; i < num_clips; clips++)
5159                         fill_dc_dirty_rect(new_plane_state->plane,
5160                                            &dirty_rects[i], clips->x1,
5161                                            clips->y1, clips->x2 - clips->x1,
5162                                            clips->y2 - clips->y1, &i, false);
5163         } else if (fb_changed && !bb_changed) {
5164                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5165                                    new_plane_state->crtc_x,
5166                                    new_plane_state->crtc_y,
5167                                    new_plane_state->crtc_w,
5168                                    new_plane_state->crtc_h, &i, false);
5169         }
5170
5171         flip_addrs->dirty_rect_count = i;
5172         return;
5173
5174 ffu:
5175         fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0,
5176                            dm_crtc_state->base.mode.crtc_hdisplay,
5177                            dm_crtc_state->base.mode.crtc_vdisplay,
5178                            &flip_addrs->dirty_rect_count, true);
5179 }
5180
5181 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
5182                                            const struct dm_connector_state *dm_state,
5183                                            struct dc_stream_state *stream)
5184 {
5185         enum amdgpu_rmx_type rmx_type;
5186
5187         struct rect src = { 0 }; /* viewport in composition space*/
5188         struct rect dst = { 0 }; /* stream addressable area */
5189
5190         /* no mode. nothing to be done */
5191         if (!mode)
5192                 return;
5193
5194         /* Full screen scaling by default */
5195         src.width = mode->hdisplay;
5196         src.height = mode->vdisplay;
5197         dst.width = stream->timing.h_addressable;
5198         dst.height = stream->timing.v_addressable;
5199
5200         if (dm_state) {
5201                 rmx_type = dm_state->scaling;
5202                 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
5203                         if (src.width * dst.height <
5204                                         src.height * dst.width) {
5205                                 /* height needs less upscaling/more downscaling */
5206                                 dst.width = src.width *
5207                                                 dst.height / src.height;
5208                         } else {
5209                                 /* width needs less upscaling/more downscaling */
5210                                 dst.height = src.height *
5211                                                 dst.width / src.width;
5212                         }
5213                 } else if (rmx_type == RMX_CENTER) {
5214                         dst = src;
5215                 }
5216
5217                 dst.x = (stream->timing.h_addressable - dst.width) / 2;
5218                 dst.y = (stream->timing.v_addressable - dst.height) / 2;
5219
5220                 if (dm_state->underscan_enable) {
5221                         dst.x += dm_state->underscan_hborder / 2;
5222                         dst.y += dm_state->underscan_vborder / 2;
5223                         dst.width -= dm_state->underscan_hborder;
5224                         dst.height -= dm_state->underscan_vborder;
5225                 }
5226         }
5227
5228         stream->src = src;
5229         stream->dst = dst;
5230
5231         DRM_DEBUG_KMS("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",
5232                       dst.x, dst.y, dst.width, dst.height);
5233
5234 }
5235
5236 static enum dc_color_depth
5237 convert_color_depth_from_display_info(const struct drm_connector *connector,
5238                                       bool is_y420, int requested_bpc)
5239 {
5240         u8 bpc;
5241
5242         if (is_y420) {
5243                 bpc = 8;
5244
5245                 /* Cap display bpc based on HDMI 2.0 HF-VSDB */
5246                 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)
5247                         bpc = 16;
5248                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
5249                         bpc = 12;
5250                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
5251                         bpc = 10;
5252         } else {
5253                 bpc = (uint8_t)connector->display_info.bpc;
5254                 /* Assume 8 bpc by default if no bpc is specified. */
5255                 bpc = bpc ? bpc : 8;
5256         }
5257
5258         if (requested_bpc > 0) {
5259                 /*
5260                  * Cap display bpc based on the user requested value.
5261                  *
5262                  * The value for state->max_bpc may not correctly updated
5263                  * depending on when the connector gets added to the state
5264                  * or if this was called outside of atomic check, so it
5265                  * can't be used directly.
5266                  */
5267                 bpc = min_t(u8, bpc, requested_bpc);
5268
5269                 /* Round down to the nearest even number. */
5270                 bpc = bpc - (bpc & 1);
5271         }
5272
5273         switch (bpc) {
5274         case 0:
5275                 /*
5276                  * Temporary Work around, DRM doesn't parse color depth for
5277                  * EDID revision before 1.4
5278                  * TODO: Fix edid parsing
5279                  */
5280                 return COLOR_DEPTH_888;
5281         case 6:
5282                 return COLOR_DEPTH_666;
5283         case 8:
5284                 return COLOR_DEPTH_888;
5285         case 10:
5286                 return COLOR_DEPTH_101010;
5287         case 12:
5288                 return COLOR_DEPTH_121212;
5289         case 14:
5290                 return COLOR_DEPTH_141414;
5291         case 16:
5292                 return COLOR_DEPTH_161616;
5293         default:
5294                 return COLOR_DEPTH_UNDEFINED;
5295         }
5296 }
5297
5298 static enum dc_aspect_ratio
5299 get_aspect_ratio(const struct drm_display_mode *mode_in)
5300 {
5301         /* 1-1 mapping, since both enums follow the HDMI spec. */
5302         return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
5303 }
5304
5305 static enum dc_color_space
5306 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing,
5307                        const struct drm_connector_state *connector_state)
5308 {
5309         enum dc_color_space color_space = COLOR_SPACE_SRGB;
5310
5311         switch (connector_state->colorspace) {
5312         case DRM_MODE_COLORIMETRY_BT601_YCC:
5313                 if (dc_crtc_timing->flags.Y_ONLY)
5314                         color_space = COLOR_SPACE_YCBCR601_LIMITED;
5315                 else
5316                         color_space = COLOR_SPACE_YCBCR601;
5317                 break;
5318         case DRM_MODE_COLORIMETRY_BT709_YCC:
5319                 if (dc_crtc_timing->flags.Y_ONLY)
5320                         color_space = COLOR_SPACE_YCBCR709_LIMITED;
5321                 else
5322                         color_space = COLOR_SPACE_YCBCR709;
5323                 break;
5324         case DRM_MODE_COLORIMETRY_OPRGB:
5325                 color_space = COLOR_SPACE_ADOBERGB;
5326                 break;
5327         case DRM_MODE_COLORIMETRY_BT2020_RGB:
5328         case DRM_MODE_COLORIMETRY_BT2020_YCC:
5329                 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB)
5330                         color_space = COLOR_SPACE_2020_RGB_FULLRANGE;
5331                 else
5332                         color_space = COLOR_SPACE_2020_YCBCR;
5333                 break;
5334         case DRM_MODE_COLORIMETRY_DEFAULT: // ITU601
5335         default:
5336                 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) {
5337                         color_space = COLOR_SPACE_SRGB;
5338                 /*
5339                  * 27030khz is the separation point between HDTV and SDTV
5340                  * according to HDMI spec, we use YCbCr709 and YCbCr601
5341                  * respectively
5342                  */
5343                 } else if (dc_crtc_timing->pix_clk_100hz > 270300) {
5344                         if (dc_crtc_timing->flags.Y_ONLY)
5345                                 color_space =
5346                                         COLOR_SPACE_YCBCR709_LIMITED;
5347                         else
5348                                 color_space = COLOR_SPACE_YCBCR709;
5349                 } else {
5350                         if (dc_crtc_timing->flags.Y_ONLY)
5351                                 color_space =
5352                                         COLOR_SPACE_YCBCR601_LIMITED;
5353                         else
5354                                 color_space = COLOR_SPACE_YCBCR601;
5355                 }
5356                 break;
5357         }
5358
5359         return color_space;
5360 }
5361
5362 static bool adjust_colour_depth_from_display_info(
5363         struct dc_crtc_timing *timing_out,
5364         const struct drm_display_info *info)
5365 {
5366         enum dc_color_depth depth = timing_out->display_color_depth;
5367         int normalized_clk;
5368
5369         do {
5370                 normalized_clk = timing_out->pix_clk_100hz / 10;
5371                 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
5372                 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
5373                         normalized_clk /= 2;
5374                 /* Adjusting pix clock following on HDMI spec based on colour depth */
5375                 switch (depth) {
5376                 case COLOR_DEPTH_888:
5377                         break;
5378                 case COLOR_DEPTH_101010:
5379                         normalized_clk = (normalized_clk * 30) / 24;
5380                         break;
5381                 case COLOR_DEPTH_121212:
5382                         normalized_clk = (normalized_clk * 36) / 24;
5383                         break;
5384                 case COLOR_DEPTH_161616:
5385                         normalized_clk = (normalized_clk * 48) / 24;
5386                         break;
5387                 default:
5388                         /* The above depths are the only ones valid for HDMI. */
5389                         return false;
5390                 }
5391                 if (normalized_clk <= info->max_tmds_clock) {
5392                         timing_out->display_color_depth = depth;
5393                         return true;
5394                 }
5395         } while (--depth > COLOR_DEPTH_666);
5396         return false;
5397 }
5398
5399 static void fill_stream_properties_from_drm_display_mode(
5400         struct dc_stream_state *stream,
5401         const struct drm_display_mode *mode_in,
5402         const struct drm_connector *connector,
5403         const struct drm_connector_state *connector_state,
5404         const struct dc_stream_state *old_stream,
5405         int requested_bpc)
5406 {
5407         struct dc_crtc_timing *timing_out = &stream->timing;
5408         const struct drm_display_info *info = &connector->display_info;
5409         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5410         struct hdmi_vendor_infoframe hv_frame;
5411         struct hdmi_avi_infoframe avi_frame;
5412
5413         memset(&hv_frame, 0, sizeof(hv_frame));
5414         memset(&avi_frame, 0, sizeof(avi_frame));
5415
5416         timing_out->h_border_left = 0;
5417         timing_out->h_border_right = 0;
5418         timing_out->v_border_top = 0;
5419         timing_out->v_border_bottom = 0;
5420         /* TODO: un-hardcode */
5421         if (drm_mode_is_420_only(info, mode_in)
5422                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5423                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5424         else if (drm_mode_is_420_also(info, mode_in)
5425                         && aconnector->force_yuv420_output)
5426                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5427         else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444)
5428                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5429                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
5430         else
5431                 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
5432
5433         timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
5434         timing_out->display_color_depth = convert_color_depth_from_display_info(
5435                 connector,
5436                 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420),
5437                 requested_bpc);
5438         timing_out->scan_type = SCANNING_TYPE_NODATA;
5439         timing_out->hdmi_vic = 0;
5440
5441         if (old_stream) {
5442                 timing_out->vic = old_stream->timing.vic;
5443                 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
5444                 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
5445         } else {
5446                 timing_out->vic = drm_match_cea_mode(mode_in);
5447                 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
5448                         timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
5449                 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
5450                         timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
5451         }
5452
5453         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5454                 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
5455                 timing_out->vic = avi_frame.video_code;
5456                 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
5457                 timing_out->hdmi_vic = hv_frame.vic;
5458         }
5459
5460         if (is_freesync_video_mode(mode_in, aconnector)) {
5461                 timing_out->h_addressable = mode_in->hdisplay;
5462                 timing_out->h_total = mode_in->htotal;
5463                 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start;
5464                 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay;
5465                 timing_out->v_total = mode_in->vtotal;
5466                 timing_out->v_addressable = mode_in->vdisplay;
5467                 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay;
5468                 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start;
5469                 timing_out->pix_clk_100hz = mode_in->clock * 10;
5470         } else {
5471                 timing_out->h_addressable = mode_in->crtc_hdisplay;
5472                 timing_out->h_total = mode_in->crtc_htotal;
5473                 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
5474                 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
5475                 timing_out->v_total = mode_in->crtc_vtotal;
5476                 timing_out->v_addressable = mode_in->crtc_vdisplay;
5477                 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
5478                 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
5479                 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
5480         }
5481
5482         timing_out->aspect_ratio = get_aspect_ratio(mode_in);
5483
5484         stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
5485         stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
5486         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5487                 if (!adjust_colour_depth_from_display_info(timing_out, info) &&
5488                     drm_mode_is_420_also(info, mode_in) &&
5489                     timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
5490                         timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5491                         adjust_colour_depth_from_display_info(timing_out, info);
5492                 }
5493         }
5494
5495         stream->output_color_space = get_output_color_space(timing_out, connector_state);
5496 }
5497
5498 static void fill_audio_info(struct audio_info *audio_info,
5499                             const struct drm_connector *drm_connector,
5500                             const struct dc_sink *dc_sink)
5501 {
5502         int i = 0;
5503         int cea_revision = 0;
5504         const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
5505
5506         audio_info->manufacture_id = edid_caps->manufacturer_id;
5507         audio_info->product_id = edid_caps->product_id;
5508
5509         cea_revision = drm_connector->display_info.cea_rev;
5510
5511         strscpy(audio_info->display_name,
5512                 edid_caps->display_name,
5513                 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
5514
5515         if (cea_revision >= 3) {
5516                 audio_info->mode_count = edid_caps->audio_mode_count;
5517
5518                 for (i = 0; i < audio_info->mode_count; ++i) {
5519                         audio_info->modes[i].format_code =
5520                                         (enum audio_format_code)
5521                                         (edid_caps->audio_modes[i].format_code);
5522                         audio_info->modes[i].channel_count =
5523                                         edid_caps->audio_modes[i].channel_count;
5524                         audio_info->modes[i].sample_rates.all =
5525                                         edid_caps->audio_modes[i].sample_rate;
5526                         audio_info->modes[i].sample_size =
5527                                         edid_caps->audio_modes[i].sample_size;
5528                 }
5529         }
5530
5531         audio_info->flags.all = edid_caps->speaker_flags;
5532
5533         /* TODO: We only check for the progressive mode, check for interlace mode too */
5534         if (drm_connector->latency_present[0]) {
5535                 audio_info->video_latency = drm_connector->video_latency[0];
5536                 audio_info->audio_latency = drm_connector->audio_latency[0];
5537         }
5538
5539         /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
5540
5541 }
5542
5543 static void
5544 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
5545                                       struct drm_display_mode *dst_mode)
5546 {
5547         dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
5548         dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
5549         dst_mode->crtc_clock = src_mode->crtc_clock;
5550         dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
5551         dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
5552         dst_mode->crtc_hsync_start =  src_mode->crtc_hsync_start;
5553         dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
5554         dst_mode->crtc_htotal = src_mode->crtc_htotal;
5555         dst_mode->crtc_hskew = src_mode->crtc_hskew;
5556         dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
5557         dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
5558         dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
5559         dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
5560         dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
5561 }
5562
5563 static void
5564 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
5565                                         const struct drm_display_mode *native_mode,
5566                                         bool scale_enabled)
5567 {
5568         if (scale_enabled) {
5569                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5570         } else if (native_mode->clock == drm_mode->clock &&
5571                         native_mode->htotal == drm_mode->htotal &&
5572                         native_mode->vtotal == drm_mode->vtotal) {
5573                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5574         } else {
5575                 /* no scaling nor amdgpu inserted, no need to patch */
5576         }
5577 }
5578
5579 static struct dc_sink *
5580 create_fake_sink(struct amdgpu_dm_connector *aconnector)
5581 {
5582         struct dc_sink_init_data sink_init_data = { 0 };
5583         struct dc_sink *sink = NULL;
5584
5585         sink_init_data.link = aconnector->dc_link;
5586         sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
5587
5588         sink = dc_sink_create(&sink_init_data);
5589         if (!sink) {
5590                 DRM_ERROR("Failed to create sink!\n");
5591                 return NULL;
5592         }
5593         sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
5594
5595         return sink;
5596 }
5597
5598 static void set_multisync_trigger_params(
5599                 struct dc_stream_state *stream)
5600 {
5601         struct dc_stream_state *master = NULL;
5602
5603         if (stream->triggered_crtc_reset.enabled) {
5604                 master = stream->triggered_crtc_reset.event_source;
5605                 stream->triggered_crtc_reset.event =
5606                         master->timing.flags.VSYNC_POSITIVE_POLARITY ?
5607                         CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING;
5608                 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL;
5609         }
5610 }
5611
5612 static void set_master_stream(struct dc_stream_state *stream_set[],
5613                               int stream_count)
5614 {
5615         int j, highest_rfr = 0, master_stream = 0;
5616
5617         for (j = 0;  j < stream_count; j++) {
5618                 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
5619                         int refresh_rate = 0;
5620
5621                         refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
5622                                 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
5623                         if (refresh_rate > highest_rfr) {
5624                                 highest_rfr = refresh_rate;
5625                                 master_stream = j;
5626                         }
5627                 }
5628         }
5629         for (j = 0;  j < stream_count; j++) {
5630                 if (stream_set[j])
5631                         stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
5632         }
5633 }
5634
5635 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
5636 {
5637         int i = 0;
5638         struct dc_stream_state *stream;
5639
5640         if (context->stream_count < 2)
5641                 return;
5642         for (i = 0; i < context->stream_count ; i++) {
5643                 if (!context->streams[i])
5644                         continue;
5645                 /*
5646                  * TODO: add a function to read AMD VSDB bits and set
5647                  * crtc_sync_master.multi_sync_enabled flag
5648                  * For now it's set to false
5649                  */
5650         }
5651
5652         set_master_stream(context->streams, context->stream_count);
5653
5654         for (i = 0; i < context->stream_count ; i++) {
5655                 stream = context->streams[i];
5656
5657                 if (!stream)
5658                         continue;
5659
5660                 set_multisync_trigger_params(stream);
5661         }
5662 }
5663
5664 /**
5665  * DOC: FreeSync Video
5666  *
5667  * When a userspace application wants to play a video, the content follows a
5668  * standard format definition that usually specifies the FPS for that format.
5669  * The below list illustrates some video format and the expected FPS,
5670  * respectively:
5671  *
5672  * - TV/NTSC (23.976 FPS)
5673  * - Cinema (24 FPS)
5674  * - TV/PAL (25 FPS)
5675  * - TV/NTSC (29.97 FPS)
5676  * - TV/NTSC (30 FPS)
5677  * - Cinema HFR (48 FPS)
5678  * - TV/PAL (50 FPS)
5679  * - Commonly used (60 FPS)
5680  * - Multiples of 24 (48,72,96 FPS)
5681  *
5682  * The list of standards video format is not huge and can be added to the
5683  * connector modeset list beforehand. With that, userspace can leverage
5684  * FreeSync to extends the front porch in order to attain the target refresh
5685  * rate. Such a switch will happen seamlessly, without screen blanking or
5686  * reprogramming of the output in any other way. If the userspace requests a
5687  * modesetting change compatible with FreeSync modes that only differ in the
5688  * refresh rate, DC will skip the full update and avoid blink during the
5689  * transition. For example, the video player can change the modesetting from
5690  * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without
5691  * causing any display blink. This same concept can be applied to a mode
5692  * setting change.
5693  */
5694 static struct drm_display_mode *
5695 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
5696                 bool use_probed_modes)
5697 {
5698         struct drm_display_mode *m, *m_pref = NULL;
5699         u16 current_refresh, highest_refresh;
5700         struct list_head *list_head = use_probed_modes ?
5701                 &aconnector->base.probed_modes :
5702                 &aconnector->base.modes;
5703
5704         if (aconnector->freesync_vid_base.clock != 0)
5705                 return &aconnector->freesync_vid_base;
5706
5707         /* Find the preferred mode */
5708         list_for_each_entry(m, list_head, head) {
5709                 if (m->type & DRM_MODE_TYPE_PREFERRED) {
5710                         m_pref = m;
5711                         break;
5712                 }
5713         }
5714
5715         if (!m_pref) {
5716                 /* Probably an EDID with no preferred mode. Fallback to first entry */
5717                 m_pref = list_first_entry_or_null(
5718                                 &aconnector->base.modes, struct drm_display_mode, head);
5719                 if (!m_pref) {
5720                         DRM_DEBUG_DRIVER("No preferred mode found in EDID\n");
5721                         return NULL;
5722                 }
5723         }
5724
5725         highest_refresh = drm_mode_vrefresh(m_pref);
5726
5727         /*
5728          * Find the mode with highest refresh rate with same resolution.
5729          * For some monitors, preferred mode is not the mode with highest
5730          * supported refresh rate.
5731          */
5732         list_for_each_entry(m, list_head, head) {
5733                 current_refresh  = drm_mode_vrefresh(m);
5734
5735                 if (m->hdisplay == m_pref->hdisplay &&
5736                     m->vdisplay == m_pref->vdisplay &&
5737                     highest_refresh < current_refresh) {
5738                         highest_refresh = current_refresh;
5739                         m_pref = m;
5740                 }
5741         }
5742
5743         drm_mode_copy(&aconnector->freesync_vid_base, m_pref);
5744         return m_pref;
5745 }
5746
5747 static bool is_freesync_video_mode(const struct drm_display_mode *mode,
5748                 struct amdgpu_dm_connector *aconnector)
5749 {
5750         struct drm_display_mode *high_mode;
5751         int timing_diff;
5752
5753         high_mode = get_highest_refresh_rate_mode(aconnector, false);
5754         if (!high_mode || !mode)
5755                 return false;
5756
5757         timing_diff = high_mode->vtotal - mode->vtotal;
5758
5759         if (high_mode->clock == 0 || high_mode->clock != mode->clock ||
5760             high_mode->hdisplay != mode->hdisplay ||
5761             high_mode->vdisplay != mode->vdisplay ||
5762             high_mode->hsync_start != mode->hsync_start ||
5763             high_mode->hsync_end != mode->hsync_end ||
5764             high_mode->htotal != mode->htotal ||
5765             high_mode->hskew != mode->hskew ||
5766             high_mode->vscan != mode->vscan ||
5767             high_mode->vsync_start - mode->vsync_start != timing_diff ||
5768             high_mode->vsync_end - mode->vsync_end != timing_diff)
5769                 return false;
5770         else
5771                 return true;
5772 }
5773
5774 static void update_dsc_caps(struct amdgpu_dm_connector *aconnector,
5775                             struct dc_sink *sink, struct dc_stream_state *stream,
5776                             struct dsc_dec_dpcd_caps *dsc_caps)
5777 {
5778         stream->timing.flags.DSC = 0;
5779         dsc_caps->is_dsc_supported = false;
5780
5781         if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
5782             sink->sink_signal == SIGNAL_TYPE_EDP)) {
5783                 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE ||
5784                         sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
5785                         dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
5786                                 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
5787                                 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
5788                                 dsc_caps);
5789         }
5790 }
5791
5792
5793 static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
5794                                     struct dc_sink *sink, struct dc_stream_state *stream,
5795                                     struct dsc_dec_dpcd_caps *dsc_caps,
5796                                     uint32_t max_dsc_target_bpp_limit_override)
5797 {
5798         const struct dc_link_settings *verified_link_cap = NULL;
5799         u32 link_bw_in_kbps;
5800         u32 edp_min_bpp_x16, edp_max_bpp_x16;
5801         struct dc *dc = sink->ctx->dc;
5802         struct dc_dsc_bw_range bw_range = {0};
5803         struct dc_dsc_config dsc_cfg = {0};
5804         struct dc_dsc_config_options dsc_options = {0};
5805
5806         dc_dsc_get_default_config_option(dc, &dsc_options);
5807         dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5808
5809         verified_link_cap = dc_link_get_link_cap(stream->link);
5810         link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap);
5811         edp_min_bpp_x16 = 8 * 16;
5812         edp_max_bpp_x16 = 8 * 16;
5813
5814         if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel)
5815                 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel;
5816
5817         if (edp_max_bpp_x16 < edp_min_bpp_x16)
5818                 edp_min_bpp_x16 = edp_max_bpp_x16;
5819
5820         if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0],
5821                                 dc->debug.dsc_min_slice_height_override,
5822                                 edp_min_bpp_x16, edp_max_bpp_x16,
5823                                 dsc_caps,
5824                                 &stream->timing,
5825                                 dc_link_get_highest_encoding_format(aconnector->dc_link),
5826                                 &bw_range)) {
5827
5828                 if (bw_range.max_kbps < link_bw_in_kbps) {
5829                         if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5830                                         dsc_caps,
5831                                         &dsc_options,
5832                                         0,
5833                                         &stream->timing,
5834                                         dc_link_get_highest_encoding_format(aconnector->dc_link),
5835                                         &dsc_cfg)) {
5836                                 stream->timing.dsc_cfg = dsc_cfg;
5837                                 stream->timing.flags.DSC = 1;
5838                                 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16;
5839                         }
5840                         return;
5841                 }
5842         }
5843
5844         if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5845                                 dsc_caps,
5846                                 &dsc_options,
5847                                 link_bw_in_kbps,
5848                                 &stream->timing,
5849                                 dc_link_get_highest_encoding_format(aconnector->dc_link),
5850                                 &dsc_cfg)) {
5851                 stream->timing.dsc_cfg = dsc_cfg;
5852                 stream->timing.flags.DSC = 1;
5853         }
5854 }
5855
5856
5857 static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
5858                                         struct dc_sink *sink, struct dc_stream_state *stream,
5859                                         struct dsc_dec_dpcd_caps *dsc_caps)
5860 {
5861         struct drm_connector *drm_connector = &aconnector->base;
5862         u32 link_bandwidth_kbps;
5863         struct dc *dc = sink->ctx->dc;
5864         u32 max_supported_bw_in_kbps, timing_bw_in_kbps;
5865         u32 dsc_max_supported_bw_in_kbps;
5866         u32 max_dsc_target_bpp_limit_override =
5867                 drm_connector->display_info.max_dsc_bpp;
5868         struct dc_dsc_config_options dsc_options = {0};
5869
5870         dc_dsc_get_default_config_option(dc, &dsc_options);
5871         dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5872
5873         link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
5874                                                         dc_link_get_link_cap(aconnector->dc_link));
5875
5876         /* Set DSC policy according to dsc_clock_en */
5877         dc_dsc_policy_set_enable_dsc_when_not_needed(
5878                 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);
5879
5880         if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP &&
5881             !aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&
5882             dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
5883
5884                 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);
5885
5886         } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
5887                 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
5888                         if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5889                                                 dsc_caps,
5890                                                 &dsc_options,
5891                                                 link_bandwidth_kbps,
5892                                                 &stream->timing,
5893                                                 dc_link_get_highest_encoding_format(aconnector->dc_link),
5894                                                 &stream->timing.dsc_cfg)) {
5895                                 stream->timing.flags.DSC = 1;
5896                                 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name);
5897                         }
5898                 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
5899                         timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing,
5900                                         dc_link_get_highest_encoding_format(aconnector->dc_link));
5901                         max_supported_bw_in_kbps = link_bandwidth_kbps;
5902                         dsc_max_supported_bw_in_kbps = link_bandwidth_kbps;
5903
5904                         if (timing_bw_in_kbps > max_supported_bw_in_kbps &&
5905                                         max_supported_bw_in_kbps > 0 &&
5906                                         dsc_max_supported_bw_in_kbps > 0)
5907                                 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5908                                                 dsc_caps,
5909                                                 &dsc_options,
5910                                                 dsc_max_supported_bw_in_kbps,
5911                                                 &stream->timing,
5912                                                 dc_link_get_highest_encoding_format(aconnector->dc_link),
5913                                                 &stream->timing.dsc_cfg)) {
5914                                         stream->timing.flags.DSC = 1;
5915                                         DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n",
5916                                                                          __func__, drm_connector->name);
5917                                 }
5918                 }
5919         }
5920
5921         /* Overwrite the stream flag if DSC is enabled through debugfs */
5922         if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
5923                 stream->timing.flags.DSC = 1;
5924
5925         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
5926                 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
5927
5928         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
5929                 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
5930
5931         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
5932                 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
5933 }
5934
5935 static struct dc_stream_state *
5936 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
5937                        const struct drm_display_mode *drm_mode,
5938                        const struct dm_connector_state *dm_state,
5939                        const struct dc_stream_state *old_stream,
5940                        int requested_bpc)
5941 {
5942         struct drm_display_mode *preferred_mode = NULL;
5943         struct drm_connector *drm_connector;
5944         const struct drm_connector_state *con_state = &dm_state->base;
5945         struct dc_stream_state *stream = NULL;
5946         struct drm_display_mode mode;
5947         struct drm_display_mode saved_mode;
5948         struct drm_display_mode *freesync_mode = NULL;
5949         bool native_mode_found = false;
5950         bool recalculate_timing = false;
5951         bool scale = dm_state->scaling != RMX_OFF;
5952         int mode_refresh;
5953         int preferred_refresh = 0;
5954         enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN;
5955         struct dsc_dec_dpcd_caps dsc_caps;
5956
5957         struct dc_sink *sink = NULL;
5958
5959         drm_mode_init(&mode, drm_mode);
5960         memset(&saved_mode, 0, sizeof(saved_mode));
5961
5962         if (aconnector == NULL) {
5963                 DRM_ERROR("aconnector is NULL!\n");
5964                 return stream;
5965         }
5966
5967         drm_connector = &aconnector->base;
5968
5969         if (!aconnector->dc_sink) {
5970                 sink = create_fake_sink(aconnector);
5971                 if (!sink)
5972                         return stream;
5973         } else {
5974                 sink = aconnector->dc_sink;
5975                 dc_sink_retain(sink);
5976         }
5977
5978         stream = dc_create_stream_for_sink(sink);
5979
5980         if (stream == NULL) {
5981                 DRM_ERROR("Failed to create stream for sink!\n");
5982                 goto finish;
5983         }
5984
5985         stream->dm_stream_context = aconnector;
5986
5987         stream->timing.flags.LTE_340MCSC_SCRAMBLE =
5988                 drm_connector->display_info.hdmi.scdc.scrambling.low_rates;
5989
5990         list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
5991                 /* Search for preferred mode */
5992                 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
5993                         native_mode_found = true;
5994                         break;
5995                 }
5996         }
5997         if (!native_mode_found)
5998                 preferred_mode = list_first_entry_or_null(
5999                                 &aconnector->base.modes,
6000                                 struct drm_display_mode,
6001                                 head);
6002
6003         mode_refresh = drm_mode_vrefresh(&mode);
6004
6005         if (preferred_mode == NULL) {
6006                 /*
6007                  * This may not be an error, the use case is when we have no
6008                  * usermode calls to reset and set mode upon hotplug. In this
6009                  * case, we call set mode ourselves to restore the previous mode
6010                  * and the modelist may not be filled in time.
6011                  */
6012                 DRM_DEBUG_DRIVER("No preferred mode found\n");
6013         } else {
6014                 recalculate_timing = is_freesync_video_mode(&mode, aconnector);
6015                 if (recalculate_timing) {
6016                         freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
6017                         drm_mode_copy(&saved_mode, &mode);
6018                         drm_mode_copy(&mode, freesync_mode);
6019                 } else {
6020                         decide_crtc_timing_for_drm_display_mode(
6021                                         &mode, preferred_mode, scale);
6022
6023                         preferred_refresh = drm_mode_vrefresh(preferred_mode);
6024                 }
6025         }
6026
6027         if (recalculate_timing)
6028                 drm_mode_set_crtcinfo(&saved_mode, 0);
6029         else if (!old_stream)
6030                 drm_mode_set_crtcinfo(&mode, 0);
6031
6032         /*
6033          * If scaling is enabled and refresh rate didn't change
6034          * we copy the vic and polarities of the old timings
6035          */
6036         if (!scale || mode_refresh != preferred_refresh)
6037                 fill_stream_properties_from_drm_display_mode(
6038                         stream, &mode, &aconnector->base, con_state, NULL,
6039                         requested_bpc);
6040         else
6041                 fill_stream_properties_from_drm_display_mode(
6042                         stream, &mode, &aconnector->base, con_state, old_stream,
6043                         requested_bpc);
6044
6045         if (aconnector->timing_changed) {
6046                 DC_LOG_DEBUG("%s: overriding timing for automated test, bpc %d, changing to %d\n",
6047                                 __func__,
6048                                 stream->timing.display_color_depth,
6049                                 aconnector->timing_requested->display_color_depth);
6050                 stream->timing = *aconnector->timing_requested;
6051         }
6052
6053         /* SST DSC determination policy */
6054         update_dsc_caps(aconnector, sink, stream, &dsc_caps);
6055         if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported)
6056                 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps);
6057
6058         update_stream_scaling_settings(&mode, dm_state, stream);
6059
6060         fill_audio_info(
6061                 &stream->audio_info,
6062                 drm_connector,
6063                 sink);
6064
6065         update_stream_signal(stream, sink);
6066
6067         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
6068                 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);
6069
6070         if (stream->link->psr_settings.psr_feature_enabled || stream->link->replay_settings.replay_feature_enabled) {
6071                 //
6072                 // should decide stream support vsc sdp colorimetry capability
6073                 // before building vsc info packet
6074                 //
6075                 stream->use_vsc_sdp_for_colorimetry = false;
6076                 if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
6077                         stream->use_vsc_sdp_for_colorimetry =
6078                                 aconnector->dc_sink->is_vsc_sdp_colorimetry_supported;
6079                 } else {
6080                         if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
6081                                 stream->use_vsc_sdp_for_colorimetry = true;
6082                 }
6083                 if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22)
6084                         tf = TRANSFER_FUNC_GAMMA_22;
6085                 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);
6086                 aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
6087
6088         }
6089 finish:
6090         dc_sink_release(sink);
6091
6092         return stream;
6093 }
6094
6095 static enum drm_connector_status
6096 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
6097 {
6098         bool connected;
6099         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6100
6101         /*
6102          * Notes:
6103          * 1. This interface is NOT called in context of HPD irq.
6104          * 2. This interface *is called* in context of user-mode ioctl. Which
6105          * makes it a bad place for *any* MST-related activity.
6106          */
6107
6108         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
6109             !aconnector->fake_enable)
6110                 connected = (aconnector->dc_sink != NULL);
6111         else
6112                 connected = (aconnector->base.force == DRM_FORCE_ON ||
6113                                 aconnector->base.force == DRM_FORCE_ON_DIGITAL);
6114
6115         update_subconnector_property(aconnector);
6116
6117         return (connected ? connector_status_connected :
6118                         connector_status_disconnected);
6119 }
6120
6121 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
6122                                             struct drm_connector_state *connector_state,
6123                                             struct drm_property *property,
6124                                             uint64_t val)
6125 {
6126         struct drm_device *dev = connector->dev;
6127         struct amdgpu_device *adev = drm_to_adev(dev);
6128         struct dm_connector_state *dm_old_state =
6129                 to_dm_connector_state(connector->state);
6130         struct dm_connector_state *dm_new_state =
6131                 to_dm_connector_state(connector_state);
6132
6133         int ret = -EINVAL;
6134
6135         if (property == dev->mode_config.scaling_mode_property) {
6136                 enum amdgpu_rmx_type rmx_type;
6137
6138                 switch (val) {
6139                 case DRM_MODE_SCALE_CENTER:
6140                         rmx_type = RMX_CENTER;
6141                         break;
6142                 case DRM_MODE_SCALE_ASPECT:
6143                         rmx_type = RMX_ASPECT;
6144                         break;
6145                 case DRM_MODE_SCALE_FULLSCREEN:
6146                         rmx_type = RMX_FULL;
6147                         break;
6148                 case DRM_MODE_SCALE_NONE:
6149                 default:
6150                         rmx_type = RMX_OFF;
6151                         break;
6152                 }
6153
6154                 if (dm_old_state->scaling == rmx_type)
6155                         return 0;
6156
6157                 dm_new_state->scaling = rmx_type;
6158                 ret = 0;
6159         } else if (property == adev->mode_info.underscan_hborder_property) {
6160                 dm_new_state->underscan_hborder = val;
6161                 ret = 0;
6162         } else if (property == adev->mode_info.underscan_vborder_property) {
6163                 dm_new_state->underscan_vborder = val;
6164                 ret = 0;
6165         } else if (property == adev->mode_info.underscan_property) {
6166                 dm_new_state->underscan_enable = val;
6167                 ret = 0;
6168         } else if (property == adev->mode_info.abm_level_property) {
6169                 dm_new_state->abm_level = val;
6170                 ret = 0;
6171         }
6172
6173         return ret;
6174 }
6175
6176 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
6177                                             const struct drm_connector_state *state,
6178                                             struct drm_property *property,
6179                                             uint64_t *val)
6180 {
6181         struct drm_device *dev = connector->dev;
6182         struct amdgpu_device *adev = drm_to_adev(dev);
6183         struct dm_connector_state *dm_state =
6184                 to_dm_connector_state(state);
6185         int ret = -EINVAL;
6186
6187         if (property == dev->mode_config.scaling_mode_property) {
6188                 switch (dm_state->scaling) {
6189                 case RMX_CENTER:
6190                         *val = DRM_MODE_SCALE_CENTER;
6191                         break;
6192                 case RMX_ASPECT:
6193                         *val = DRM_MODE_SCALE_ASPECT;
6194                         break;
6195                 case RMX_FULL:
6196                         *val = DRM_MODE_SCALE_FULLSCREEN;
6197                         break;
6198                 case RMX_OFF:
6199                 default:
6200                         *val = DRM_MODE_SCALE_NONE;
6201                         break;
6202                 }
6203                 ret = 0;
6204         } else if (property == adev->mode_info.underscan_hborder_property) {
6205                 *val = dm_state->underscan_hborder;
6206                 ret = 0;
6207         } else if (property == adev->mode_info.underscan_vborder_property) {
6208                 *val = dm_state->underscan_vborder;
6209                 ret = 0;
6210         } else if (property == adev->mode_info.underscan_property) {
6211                 *val = dm_state->underscan_enable;
6212                 ret = 0;
6213         } else if (property == adev->mode_info.abm_level_property) {
6214                 *val = dm_state->abm_level;
6215                 ret = 0;
6216         }
6217
6218         return ret;
6219 }
6220
6221 static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
6222 {
6223         struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
6224
6225         drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
6226 }
6227
6228 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
6229 {
6230         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6231         struct amdgpu_device *adev = drm_to_adev(connector->dev);
6232         struct amdgpu_display_manager *dm = &adev->dm;
6233
6234         /*
6235          * Call only if mst_mgr was initialized before since it's not done
6236          * for all connector types.
6237          */
6238         if (aconnector->mst_mgr.dev)
6239                 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);
6240
6241         if (aconnector->bl_idx != -1) {
6242                 backlight_device_unregister(dm->backlight_dev[aconnector->bl_idx]);
6243                 dm->backlight_dev[aconnector->bl_idx] = NULL;
6244         }
6245
6246         if (aconnector->dc_em_sink)
6247                 dc_sink_release(aconnector->dc_em_sink);
6248         aconnector->dc_em_sink = NULL;
6249         if (aconnector->dc_sink)
6250                 dc_sink_release(aconnector->dc_sink);
6251         aconnector->dc_sink = NULL;
6252
6253         drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
6254         drm_connector_unregister(connector);
6255         drm_connector_cleanup(connector);
6256         if (aconnector->i2c) {
6257                 i2c_del_adapter(&aconnector->i2c->base);
6258                 kfree(aconnector->i2c);
6259         }
6260         kfree(aconnector->dm_dp_aux.aux.name);
6261
6262         kfree(connector);
6263 }
6264
6265 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
6266 {
6267         struct dm_connector_state *state =
6268                 to_dm_connector_state(connector->state);
6269
6270         if (connector->state)
6271                 __drm_atomic_helper_connector_destroy_state(connector->state);
6272
6273         kfree(state);
6274
6275         state = kzalloc(sizeof(*state), GFP_KERNEL);
6276
6277         if (state) {
6278                 state->scaling = RMX_OFF;
6279                 state->underscan_enable = false;
6280                 state->underscan_hborder = 0;
6281                 state->underscan_vborder = 0;
6282                 state->base.max_requested_bpc = 8;
6283                 state->vcpi_slots = 0;
6284                 state->pbn = 0;
6285
6286                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
6287                         state->abm_level = amdgpu_dm_abm_level;
6288
6289                 __drm_atomic_helper_connector_reset(connector, &state->base);
6290         }
6291 }
6292
6293 struct drm_connector_state *
6294 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
6295 {
6296         struct dm_connector_state *state =
6297                 to_dm_connector_state(connector->state);
6298
6299         struct dm_connector_state *new_state =
6300                         kmemdup(state, sizeof(*state), GFP_KERNEL);
6301
6302         if (!new_state)
6303                 return NULL;
6304
6305         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
6306
6307         new_state->freesync_capable = state->freesync_capable;
6308         new_state->abm_level = state->abm_level;
6309         new_state->scaling = state->scaling;
6310         new_state->underscan_enable = state->underscan_enable;
6311         new_state->underscan_hborder = state->underscan_hborder;
6312         new_state->underscan_vborder = state->underscan_vborder;
6313         new_state->vcpi_slots = state->vcpi_slots;
6314         new_state->pbn = state->pbn;
6315         return &new_state->base;
6316 }
6317
6318 static int
6319 amdgpu_dm_connector_late_register(struct drm_connector *connector)
6320 {
6321         struct amdgpu_dm_connector *amdgpu_dm_connector =
6322                 to_amdgpu_dm_connector(connector);
6323         int r;
6324
6325         amdgpu_dm_register_backlight_device(amdgpu_dm_connector);
6326
6327         if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
6328             (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
6329                 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
6330                 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
6331                 if (r)
6332                         return r;
6333         }
6334
6335 #if defined(CONFIG_DEBUG_FS)
6336         connector_debugfs_init(amdgpu_dm_connector);
6337 #endif
6338
6339         return 0;
6340 }
6341
6342 static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector)
6343 {
6344         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6345         struct dc_link *dc_link = aconnector->dc_link;
6346         struct dc_sink *dc_em_sink = aconnector->dc_em_sink;
6347         struct edid *edid;
6348
6349         if (!connector->edid_override)
6350                 return;
6351
6352         drm_edid_override_connector_update(&aconnector->base);
6353         edid = aconnector->base.edid_blob_ptr->data;
6354         aconnector->edid = edid;
6355
6356         /* Update emulated (virtual) sink's EDID */
6357         if (dc_em_sink && dc_link) {
6358                 memset(&dc_em_sink->edid_caps, 0, sizeof(struct dc_edid_caps));
6359                 memmove(dc_em_sink->dc_edid.raw_edid, edid, (edid->extensions + 1) * EDID_LENGTH);
6360                 dm_helpers_parse_edid_caps(
6361                         dc_link,
6362                         &dc_em_sink->dc_edid,
6363                         &dc_em_sink->edid_caps);
6364         }
6365 }
6366
6367 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
6368         .reset = amdgpu_dm_connector_funcs_reset,
6369         .detect = amdgpu_dm_connector_detect,
6370         .fill_modes = drm_helper_probe_single_connector_modes,
6371         .destroy = amdgpu_dm_connector_destroy,
6372         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
6373         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6374         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
6375         .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
6376         .late_register = amdgpu_dm_connector_late_register,
6377         .early_unregister = amdgpu_dm_connector_unregister,
6378         .force = amdgpu_dm_connector_funcs_force
6379 };
6380
6381 static int get_modes(struct drm_connector *connector)
6382 {
6383         return amdgpu_dm_connector_get_modes(connector);
6384 }
6385
6386 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
6387 {
6388         struct dc_sink_init_data init_params = {
6389                         .link = aconnector->dc_link,
6390                         .sink_signal = SIGNAL_TYPE_VIRTUAL
6391         };
6392         struct edid *edid;
6393
6394         if (!aconnector->base.edid_blob_ptr) {
6395                 /* if connector->edid_override valid, pass
6396                  * it to edid_override to edid_blob_ptr
6397                  */
6398
6399                 drm_edid_override_connector_update(&aconnector->base);
6400
6401                 if (!aconnector->base.edid_blob_ptr) {
6402                         DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
6403                                         aconnector->base.name);
6404
6405                         aconnector->base.force = DRM_FORCE_OFF;
6406                         return;
6407                 }
6408         }
6409
6410         edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
6411
6412         aconnector->edid = edid;
6413
6414         aconnector->dc_em_sink = dc_link_add_remote_sink(
6415                 aconnector->dc_link,
6416                 (uint8_t *)edid,
6417                 (edid->extensions + 1) * EDID_LENGTH,
6418                 &init_params);
6419
6420         if (aconnector->base.force == DRM_FORCE_ON) {
6421                 aconnector->dc_sink = aconnector->dc_link->local_sink ?
6422                 aconnector->dc_link->local_sink :
6423                 aconnector->dc_em_sink;
6424                 dc_sink_retain(aconnector->dc_sink);
6425         }
6426 }
6427
6428 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
6429 {
6430         struct dc_link *link = (struct dc_link *)aconnector->dc_link;
6431
6432         /*
6433          * In case of headless boot with force on for DP managed connector
6434          * Those settings have to be != 0 to get initial modeset
6435          */
6436         if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
6437                 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
6438                 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
6439         }
6440
6441         create_eml_sink(aconnector);
6442 }
6443
6444 static enum dc_status dm_validate_stream_and_context(struct dc *dc,
6445                                                 struct dc_stream_state *stream)
6446 {
6447         enum dc_status dc_result = DC_ERROR_UNEXPECTED;
6448         struct dc_plane_state *dc_plane_state = NULL;
6449         struct dc_state *dc_state = NULL;
6450
6451         if (!stream)
6452                 goto cleanup;
6453
6454         dc_plane_state = dc_create_plane_state(dc);
6455         if (!dc_plane_state)
6456                 goto cleanup;
6457
6458         dc_state = dc_create_state(dc);
6459         if (!dc_state)
6460                 goto cleanup;
6461
6462         /* populate stream to plane */
6463         dc_plane_state->src_rect.height  = stream->src.height;
6464         dc_plane_state->src_rect.width   = stream->src.width;
6465         dc_plane_state->dst_rect.height  = stream->src.height;
6466         dc_plane_state->dst_rect.width   = stream->src.width;
6467         dc_plane_state->clip_rect.height = stream->src.height;
6468         dc_plane_state->clip_rect.width  = stream->src.width;
6469         dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256;
6470         dc_plane_state->plane_size.surface_size.height = stream->src.height;
6471         dc_plane_state->plane_size.surface_size.width  = stream->src.width;
6472         dc_plane_state->plane_size.chroma_size.height  = stream->src.height;
6473         dc_plane_state->plane_size.chroma_size.width   = stream->src.width;
6474         dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
6475         dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN;
6476         dc_plane_state->rotation = ROTATION_ANGLE_0;
6477         dc_plane_state->is_tiling_rotated = false;
6478         dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL;
6479
6480         dc_result = dc_validate_stream(dc, stream);
6481         if (dc_result == DC_OK)
6482                 dc_result = dc_validate_plane(dc, dc_plane_state);
6483
6484         if (dc_result == DC_OK)
6485                 dc_result = dc_add_stream_to_ctx(dc, dc_state, stream);
6486
6487         if (dc_result == DC_OK && !dc_add_plane_to_context(
6488                                                 dc,
6489                                                 stream,
6490                                                 dc_plane_state,
6491                                                 dc_state))
6492                 dc_result = DC_FAIL_ATTACH_SURFACES;
6493
6494         if (dc_result == DC_OK)
6495                 dc_result = dc_validate_global_state(dc, dc_state, true);
6496
6497 cleanup:
6498         if (dc_state)
6499                 dc_release_state(dc_state);
6500
6501         if (dc_plane_state)
6502                 dc_plane_state_release(dc_plane_state);
6503
6504         return dc_result;
6505 }
6506
6507 struct dc_stream_state *
6508 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6509                                 const struct drm_display_mode *drm_mode,
6510                                 const struct dm_connector_state *dm_state,
6511                                 const struct dc_stream_state *old_stream)
6512 {
6513         struct drm_connector *connector = &aconnector->base;
6514         struct amdgpu_device *adev = drm_to_adev(connector->dev);
6515         struct dc_stream_state *stream;
6516         const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL;
6517         int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8;
6518         enum dc_status dc_result = DC_OK;
6519
6520         do {
6521                 stream = create_stream_for_sink(aconnector, drm_mode,
6522                                                 dm_state, old_stream,
6523                                                 requested_bpc);
6524                 if (stream == NULL) {
6525                         DRM_ERROR("Failed to create stream for sink!\n");
6526                         break;
6527                 }
6528
6529                 dc_result = dc_validate_stream(adev->dm.dc, stream);
6530                 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
6531                         dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream);
6532
6533                 if (dc_result == DC_OK)
6534                         dc_result = dm_validate_stream_and_context(adev->dm.dc, stream);
6535
6536                 if (dc_result != DC_OK) {
6537                         DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",
6538                                       drm_mode->hdisplay,
6539                                       drm_mode->vdisplay,
6540                                       drm_mode->clock,
6541                                       dc_result,
6542                                       dc_status_to_str(dc_result));
6543
6544                         dc_stream_release(stream);
6545                         stream = NULL;
6546                         requested_bpc -= 2; /* lower bpc to retry validation */
6547                 }
6548
6549         } while (stream == NULL && requested_bpc >= 6);
6550
6551         if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) {
6552                 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n");
6553
6554                 aconnector->force_yuv420_output = true;
6555                 stream = create_validate_stream_for_sink(aconnector, drm_mode,
6556                                                 dm_state, old_stream);
6557                 aconnector->force_yuv420_output = false;
6558         }
6559
6560         return stream;
6561 }
6562
6563 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
6564                                    struct drm_display_mode *mode)
6565 {
6566         int result = MODE_ERROR;
6567         struct dc_sink *dc_sink;
6568         /* TODO: Unhardcode stream count */
6569         struct dc_stream_state *stream;
6570         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6571
6572         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
6573                         (mode->flags & DRM_MODE_FLAG_DBLSCAN))
6574                 return result;
6575
6576         /*
6577          * Only run this the first time mode_valid is called to initilialize
6578          * EDID mgmt
6579          */
6580         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
6581                 !aconnector->dc_em_sink)
6582                 handle_edid_mgmt(aconnector);
6583
6584         dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
6585
6586         if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL &&
6587                                 aconnector->base.force != DRM_FORCE_ON) {
6588                 DRM_ERROR("dc_sink is NULL!\n");
6589                 goto fail;
6590         }
6591
6592         stream = create_validate_stream_for_sink(aconnector, mode,
6593                                                  to_dm_connector_state(connector->state),
6594                                                  NULL);
6595         if (stream) {
6596                 dc_stream_release(stream);
6597                 result = MODE_OK;
6598         }
6599
6600 fail:
6601         /* TODO: error handling*/
6602         return result;
6603 }
6604
6605 static int fill_hdr_info_packet(const struct drm_connector_state *state,
6606                                 struct dc_info_packet *out)
6607 {
6608         struct hdmi_drm_infoframe frame;
6609         unsigned char buf[30]; /* 26 + 4 */
6610         ssize_t len;
6611         int ret, i;
6612
6613         memset(out, 0, sizeof(*out));
6614
6615         if (!state->hdr_output_metadata)
6616                 return 0;
6617
6618         ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
6619         if (ret)
6620                 return ret;
6621
6622         len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
6623         if (len < 0)
6624                 return (int)len;
6625
6626         /* Static metadata is a fixed 26 bytes + 4 byte header. */
6627         if (len != 30)
6628                 return -EINVAL;
6629
6630         /* Prepare the infopacket for DC. */
6631         switch (state->connector->connector_type) {
6632         case DRM_MODE_CONNECTOR_HDMIA:
6633                 out->hb0 = 0x87; /* type */
6634                 out->hb1 = 0x01; /* version */
6635                 out->hb2 = 0x1A; /* length */
6636                 out->sb[0] = buf[3]; /* checksum */
6637                 i = 1;
6638                 break;
6639
6640         case DRM_MODE_CONNECTOR_DisplayPort:
6641         case DRM_MODE_CONNECTOR_eDP:
6642                 out->hb0 = 0x00; /* sdp id, zero */
6643                 out->hb1 = 0x87; /* type */
6644                 out->hb2 = 0x1D; /* payload len - 1 */
6645                 out->hb3 = (0x13 << 2); /* sdp version */
6646                 out->sb[0] = 0x01; /* version */
6647                 out->sb[1] = 0x1A; /* length */
6648                 i = 2;
6649                 break;
6650
6651         default:
6652                 return -EINVAL;
6653         }
6654
6655         memcpy(&out->sb[i], &buf[4], 26);
6656         out->valid = true;
6657
6658         print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
6659                        sizeof(out->sb), false);
6660
6661         return 0;
6662 }
6663
6664 static int
6665 amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
6666                                  struct drm_atomic_state *state)
6667 {
6668         struct drm_connector_state *new_con_state =
6669                 drm_atomic_get_new_connector_state(state, conn);
6670         struct drm_connector_state *old_con_state =
6671                 drm_atomic_get_old_connector_state(state, conn);
6672         struct drm_crtc *crtc = new_con_state->crtc;
6673         struct drm_crtc_state *new_crtc_state;
6674         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn);
6675         int ret;
6676
6677         trace_amdgpu_dm_connector_atomic_check(new_con_state);
6678
6679         if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
6680                 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr);
6681                 if (ret < 0)
6682                         return ret;
6683         }
6684
6685         if (!crtc)
6686                 return 0;
6687
6688         if (new_con_state->colorspace != old_con_state->colorspace) {
6689                 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6690                 if (IS_ERR(new_crtc_state))
6691                         return PTR_ERR(new_crtc_state);
6692
6693                 new_crtc_state->mode_changed = true;
6694         }
6695
6696         if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) {
6697                 struct dc_info_packet hdr_infopacket;
6698
6699                 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
6700                 if (ret)
6701                         return ret;
6702
6703                 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6704                 if (IS_ERR(new_crtc_state))
6705                         return PTR_ERR(new_crtc_state);
6706
6707                 /*
6708                  * DC considers the stream backends changed if the
6709                  * static metadata changes. Forcing the modeset also
6710                  * gives a simple way for userspace to switch from
6711                  * 8bpc to 10bpc when setting the metadata to enter
6712                  * or exit HDR.
6713                  *
6714                  * Changing the static metadata after it's been
6715                  * set is permissible, however. So only force a
6716                  * modeset if we're entering or exiting HDR.
6717                  */
6718                 new_crtc_state->mode_changed = new_crtc_state->mode_changed ||
6719                         !old_con_state->hdr_output_metadata ||
6720                         !new_con_state->hdr_output_metadata;
6721         }
6722
6723         return 0;
6724 }
6725
6726 static const struct drm_connector_helper_funcs
6727 amdgpu_dm_connector_helper_funcs = {
6728         /*
6729          * If hotplugging a second bigger display in FB Con mode, bigger resolution
6730          * modes will be filtered by drm_mode_validate_size(), and those modes
6731          * are missing after user start lightdm. So we need to renew modes list.
6732          * in get_modes call back, not just return the modes count
6733          */
6734         .get_modes = get_modes,
6735         .mode_valid = amdgpu_dm_connector_mode_valid,
6736         .atomic_check = amdgpu_dm_connector_atomic_check,
6737 };
6738
6739 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
6740 {
6741
6742 }
6743
6744 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth)
6745 {
6746         switch (display_color_depth) {
6747         case COLOR_DEPTH_666:
6748                 return 6;
6749         case COLOR_DEPTH_888:
6750                 return 8;
6751         case COLOR_DEPTH_101010:
6752                 return 10;
6753         case COLOR_DEPTH_121212:
6754                 return 12;
6755         case COLOR_DEPTH_141414:
6756                 return 14;
6757         case COLOR_DEPTH_161616:
6758                 return 16;
6759         default:
6760                 break;
6761         }
6762         return 0;
6763 }
6764
6765 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
6766                                           struct drm_crtc_state *crtc_state,
6767                                           struct drm_connector_state *conn_state)
6768 {
6769         struct drm_atomic_state *state = crtc_state->state;
6770         struct drm_connector *connector = conn_state->connector;
6771         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6772         struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state);
6773         const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
6774         struct drm_dp_mst_topology_mgr *mst_mgr;
6775         struct drm_dp_mst_port *mst_port;
6776         struct drm_dp_mst_topology_state *mst_state;
6777         enum dc_color_depth color_depth;
6778         int clock, bpp = 0;
6779         bool is_y420 = false;
6780
6781         if (!aconnector->mst_output_port)
6782                 return 0;
6783
6784         mst_port = aconnector->mst_output_port;
6785         mst_mgr = &aconnector->mst_root->mst_mgr;
6786
6787         if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
6788                 return 0;
6789
6790         mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr);
6791         if (IS_ERR(mst_state))
6792                 return PTR_ERR(mst_state);
6793
6794         if (!mst_state->pbn_div)
6795                 mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link);
6796
6797         if (!state->duplicated) {
6798                 int max_bpc = conn_state->max_requested_bpc;
6799
6800                 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
6801                           aconnector->force_yuv420_output;
6802                 color_depth = convert_color_depth_from_display_info(connector,
6803                                                                     is_y420,
6804                                                                     max_bpc);
6805                 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
6806                 clock = adjusted_mode->clock;
6807                 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
6808         }
6809
6810         dm_new_connector_state->vcpi_slots =
6811                 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port,
6812                                               dm_new_connector_state->pbn);
6813         if (dm_new_connector_state->vcpi_slots < 0) {
6814                 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
6815                 return dm_new_connector_state->vcpi_slots;
6816         }
6817         return 0;
6818 }
6819
6820 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
6821         .disable = dm_encoder_helper_disable,
6822         .atomic_check = dm_encoder_helper_atomic_check
6823 };
6824
6825 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
6826                                             struct dc_state *dc_state,
6827                                             struct dsc_mst_fairness_vars *vars)
6828 {
6829         struct dc_stream_state *stream = NULL;
6830         struct drm_connector *connector;
6831         struct drm_connector_state *new_con_state;
6832         struct amdgpu_dm_connector *aconnector;
6833         struct dm_connector_state *dm_conn_state;
6834         int i, j, ret;
6835         int vcpi, pbn_div, pbn, slot_num = 0;
6836
6837         for_each_new_connector_in_state(state, connector, new_con_state, i) {
6838
6839                 aconnector = to_amdgpu_dm_connector(connector);
6840
6841                 if (!aconnector->mst_output_port)
6842                         continue;
6843
6844                 if (!new_con_state || !new_con_state->crtc)
6845                         continue;
6846
6847                 dm_conn_state = to_dm_connector_state(new_con_state);
6848
6849                 for (j = 0; j < dc_state->stream_count; j++) {
6850                         stream = dc_state->streams[j];
6851                         if (!stream)
6852                                 continue;
6853
6854                         if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector)
6855                                 break;
6856
6857                         stream = NULL;
6858                 }
6859
6860                 if (!stream)
6861                         continue;
6862
6863                 pbn_div = dm_mst_get_pbn_divider(stream->link);
6864                 /* pbn is calculated by compute_mst_dsc_configs_for_state*/
6865                 for (j = 0; j < dc_state->stream_count; j++) {
6866                         if (vars[j].aconnector == aconnector) {
6867                                 pbn = vars[j].pbn;
6868                                 break;
6869                         }
6870                 }
6871
6872                 if (j == dc_state->stream_count)
6873                         continue;
6874
6875                 slot_num = DIV_ROUND_UP(pbn, pbn_div);
6876
6877                 if (stream->timing.flags.DSC != 1) {
6878                         dm_conn_state->pbn = pbn;
6879                         dm_conn_state->vcpi_slots = slot_num;
6880
6881                         ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port,
6882                                                            dm_conn_state->pbn, false);
6883                         if (ret < 0)
6884                                 return ret;
6885
6886                         continue;
6887                 }
6888
6889                 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true);
6890                 if (vcpi < 0)
6891                         return vcpi;
6892
6893                 dm_conn_state->pbn = pbn;
6894                 dm_conn_state->vcpi_slots = vcpi;
6895         }
6896         return 0;
6897 }
6898
6899 static int to_drm_connector_type(enum signal_type st)
6900 {
6901         switch (st) {
6902         case SIGNAL_TYPE_HDMI_TYPE_A:
6903                 return DRM_MODE_CONNECTOR_HDMIA;
6904         case SIGNAL_TYPE_EDP:
6905                 return DRM_MODE_CONNECTOR_eDP;
6906         case SIGNAL_TYPE_LVDS:
6907                 return DRM_MODE_CONNECTOR_LVDS;
6908         case SIGNAL_TYPE_RGB:
6909                 return DRM_MODE_CONNECTOR_VGA;
6910         case SIGNAL_TYPE_DISPLAY_PORT:
6911         case SIGNAL_TYPE_DISPLAY_PORT_MST:
6912                 return DRM_MODE_CONNECTOR_DisplayPort;
6913         case SIGNAL_TYPE_DVI_DUAL_LINK:
6914         case SIGNAL_TYPE_DVI_SINGLE_LINK:
6915                 return DRM_MODE_CONNECTOR_DVID;
6916         case SIGNAL_TYPE_VIRTUAL:
6917                 return DRM_MODE_CONNECTOR_VIRTUAL;
6918
6919         default:
6920                 return DRM_MODE_CONNECTOR_Unknown;
6921         }
6922 }
6923
6924 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
6925 {
6926         struct drm_encoder *encoder;
6927
6928         /* There is only one encoder per connector */
6929         drm_connector_for_each_possible_encoder(connector, encoder)
6930                 return encoder;
6931
6932         return NULL;
6933 }
6934
6935 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
6936 {
6937         struct drm_encoder *encoder;
6938         struct amdgpu_encoder *amdgpu_encoder;
6939
6940         encoder = amdgpu_dm_connector_to_encoder(connector);
6941
6942         if (encoder == NULL)
6943                 return;
6944
6945         amdgpu_encoder = to_amdgpu_encoder(encoder);
6946
6947         amdgpu_encoder->native_mode.clock = 0;
6948
6949         if (!list_empty(&connector->probed_modes)) {
6950                 struct drm_display_mode *preferred_mode = NULL;
6951
6952                 list_for_each_entry(preferred_mode,
6953                                     &connector->probed_modes,
6954                                     head) {
6955                         if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
6956                                 amdgpu_encoder->native_mode = *preferred_mode;
6957
6958                         break;
6959                 }
6960
6961         }
6962 }
6963
6964 static struct drm_display_mode *
6965 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
6966                              char *name,
6967                              int hdisplay, int vdisplay)
6968 {
6969         struct drm_device *dev = encoder->dev;
6970         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
6971         struct drm_display_mode *mode = NULL;
6972         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
6973
6974         mode = drm_mode_duplicate(dev, native_mode);
6975
6976         if (mode == NULL)
6977                 return NULL;
6978
6979         mode->hdisplay = hdisplay;
6980         mode->vdisplay = vdisplay;
6981         mode->type &= ~DRM_MODE_TYPE_PREFERRED;
6982         strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
6983
6984         return mode;
6985
6986 }
6987
6988 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
6989                                                  struct drm_connector *connector)
6990 {
6991         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
6992         struct drm_display_mode *mode = NULL;
6993         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
6994         struct amdgpu_dm_connector *amdgpu_dm_connector =
6995                                 to_amdgpu_dm_connector(connector);
6996         int i;
6997         int n;
6998         struct mode_size {
6999                 char name[DRM_DISPLAY_MODE_LEN];
7000                 int w;
7001                 int h;
7002         } common_modes[] = {
7003                 {  "640x480",  640,  480},
7004                 {  "800x600",  800,  600},
7005                 { "1024x768", 1024,  768},
7006                 { "1280x720", 1280,  720},
7007                 { "1280x800", 1280,  800},
7008                 {"1280x1024", 1280, 1024},
7009                 { "1440x900", 1440,  900},
7010                 {"1680x1050", 1680, 1050},
7011                 {"1600x1200", 1600, 1200},
7012                 {"1920x1080", 1920, 1080},
7013                 {"1920x1200", 1920, 1200}
7014         };
7015
7016         n = ARRAY_SIZE(common_modes);
7017
7018         for (i = 0; i < n; i++) {
7019                 struct drm_display_mode *curmode = NULL;
7020                 bool mode_existed = false;
7021
7022                 if (common_modes[i].w > native_mode->hdisplay ||
7023                     common_modes[i].h > native_mode->vdisplay ||
7024                    (common_modes[i].w == native_mode->hdisplay &&
7025                     common_modes[i].h == native_mode->vdisplay))
7026                         continue;
7027
7028                 list_for_each_entry(curmode, &connector->probed_modes, head) {
7029                         if (common_modes[i].w == curmode->hdisplay &&
7030                             common_modes[i].h == curmode->vdisplay) {
7031                                 mode_existed = true;
7032                                 break;
7033                         }
7034                 }
7035
7036                 if (mode_existed)
7037                         continue;
7038
7039                 mode = amdgpu_dm_create_common_mode(encoder,
7040                                 common_modes[i].name, common_modes[i].w,
7041                                 common_modes[i].h);
7042                 if (!mode)
7043                         continue;
7044
7045                 drm_mode_probed_add(connector, mode);
7046                 amdgpu_dm_connector->num_modes++;
7047         }
7048 }
7049
7050 static void amdgpu_set_panel_orientation(struct drm_connector *connector)
7051 {
7052         struct drm_encoder *encoder;
7053         struct amdgpu_encoder *amdgpu_encoder;
7054         const struct drm_display_mode *native_mode;
7055
7056         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
7057             connector->connector_type != DRM_MODE_CONNECTOR_LVDS)
7058                 return;
7059
7060         mutex_lock(&connector->dev->mode_config.mutex);
7061         amdgpu_dm_connector_get_modes(connector);
7062         mutex_unlock(&connector->dev->mode_config.mutex);
7063
7064         encoder = amdgpu_dm_connector_to_encoder(connector);
7065         if (!encoder)
7066                 return;
7067
7068         amdgpu_encoder = to_amdgpu_encoder(encoder);
7069
7070         native_mode = &amdgpu_encoder->native_mode;
7071         if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0)
7072                 return;
7073
7074         drm_connector_set_panel_orientation_with_quirk(connector,
7075                                                        DRM_MODE_PANEL_ORIENTATION_UNKNOWN,
7076                                                        native_mode->hdisplay,
7077                                                        native_mode->vdisplay);
7078 }
7079
7080 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
7081                                               struct edid *edid)
7082 {
7083         struct amdgpu_dm_connector *amdgpu_dm_connector =
7084                         to_amdgpu_dm_connector(connector);
7085
7086         if (edid) {
7087                 /* empty probed_modes */
7088                 INIT_LIST_HEAD(&connector->probed_modes);
7089                 amdgpu_dm_connector->num_modes =
7090                                 drm_add_edid_modes(connector, edid);
7091
7092                 /* sorting the probed modes before calling function
7093                  * amdgpu_dm_get_native_mode() since EDID can have
7094                  * more than one preferred mode. The modes that are
7095                  * later in the probed mode list could be of higher
7096                  * and preferred resolution. For example, 3840x2160
7097                  * resolution in base EDID preferred timing and 4096x2160
7098                  * preferred resolution in DID extension block later.
7099                  */
7100                 drm_mode_sort(&connector->probed_modes);
7101                 amdgpu_dm_get_native_mode(connector);
7102
7103                 /* Freesync capabilities are reset by calling
7104                  * drm_add_edid_modes() and need to be
7105                  * restored here.
7106                  */
7107                 amdgpu_dm_update_freesync_caps(connector, edid);
7108         } else {
7109                 amdgpu_dm_connector->num_modes = 0;
7110         }
7111 }
7112
7113 static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector,
7114                               struct drm_display_mode *mode)
7115 {
7116         struct drm_display_mode *m;
7117
7118         list_for_each_entry(m, &aconnector->base.probed_modes, head) {
7119                 if (drm_mode_equal(m, mode))
7120                         return true;
7121         }
7122
7123         return false;
7124 }
7125
7126 static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)
7127 {
7128         const struct drm_display_mode *m;
7129         struct drm_display_mode *new_mode;
7130         uint i;
7131         u32 new_modes_count = 0;
7132
7133         /* Standard FPS values
7134          *
7135          * 23.976       - TV/NTSC
7136          * 24           - Cinema
7137          * 25           - TV/PAL
7138          * 29.97        - TV/NTSC
7139          * 30           - TV/NTSC
7140          * 48           - Cinema HFR
7141          * 50           - TV/PAL
7142          * 60           - Commonly used
7143          * 48,72,96,120 - Multiples of 24
7144          */
7145         static const u32 common_rates[] = {
7146                 23976, 24000, 25000, 29970, 30000,
7147                 48000, 50000, 60000, 72000, 96000, 120000
7148         };
7149
7150         /*
7151          * Find mode with highest refresh rate with the same resolution
7152          * as the preferred mode. Some monitors report a preferred mode
7153          * with lower resolution than the highest refresh rate supported.
7154          */
7155
7156         m = get_highest_refresh_rate_mode(aconnector, true);
7157         if (!m)
7158                 return 0;
7159
7160         for (i = 0; i < ARRAY_SIZE(common_rates); i++) {
7161                 u64 target_vtotal, target_vtotal_diff;
7162                 u64 num, den;
7163
7164                 if (drm_mode_vrefresh(m) * 1000 < common_rates[i])
7165                         continue;
7166
7167                 if (common_rates[i] < aconnector->min_vfreq * 1000 ||
7168                     common_rates[i] > aconnector->max_vfreq * 1000)
7169                         continue;
7170
7171                 num = (unsigned long long)m->clock * 1000 * 1000;
7172                 den = common_rates[i] * (unsigned long long)m->htotal;
7173                 target_vtotal = div_u64(num, den);
7174                 target_vtotal_diff = target_vtotal - m->vtotal;
7175
7176                 /* Check for illegal modes */
7177                 if (m->vsync_start + target_vtotal_diff < m->vdisplay ||
7178                     m->vsync_end + target_vtotal_diff < m->vsync_start ||
7179                     m->vtotal + target_vtotal_diff < m->vsync_end)
7180                         continue;
7181
7182                 new_mode = drm_mode_duplicate(aconnector->base.dev, m);
7183                 if (!new_mode)
7184                         goto out;
7185
7186                 new_mode->vtotal += (u16)target_vtotal_diff;
7187                 new_mode->vsync_start += (u16)target_vtotal_diff;
7188                 new_mode->vsync_end += (u16)target_vtotal_diff;
7189                 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7190                 new_mode->type |= DRM_MODE_TYPE_DRIVER;
7191
7192                 if (!is_duplicate_mode(aconnector, new_mode)) {
7193                         drm_mode_probed_add(&aconnector->base, new_mode);
7194                         new_modes_count += 1;
7195                 } else
7196                         drm_mode_destroy(aconnector->base.dev, new_mode);
7197         }
7198  out:
7199         return new_modes_count;
7200 }
7201
7202 static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector,
7203                                                    struct edid *edid)
7204 {
7205         struct amdgpu_dm_connector *amdgpu_dm_connector =
7206                 to_amdgpu_dm_connector(connector);
7207
7208         if (!edid)
7209                 return;
7210
7211         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
7212                 amdgpu_dm_connector->num_modes +=
7213                         add_fs_modes(amdgpu_dm_connector);
7214 }
7215
7216 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
7217 {
7218         struct amdgpu_dm_connector *amdgpu_dm_connector =
7219                         to_amdgpu_dm_connector(connector);
7220         struct drm_encoder *encoder;
7221         struct edid *edid = amdgpu_dm_connector->edid;
7222         struct dc_link_settings *verified_link_cap =
7223                         &amdgpu_dm_connector->dc_link->verified_link_cap;
7224         const struct dc *dc = amdgpu_dm_connector->dc_link->dc;
7225
7226         encoder = amdgpu_dm_connector_to_encoder(connector);
7227
7228         if (!drm_edid_is_valid(edid)) {
7229                 amdgpu_dm_connector->num_modes =
7230                                 drm_add_modes_noedid(connector, 640, 480);
7231                 if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING)
7232                         amdgpu_dm_connector->num_modes +=
7233                                 drm_add_modes_noedid(connector, 1920, 1080);
7234         } else {
7235                 amdgpu_dm_connector_ddc_get_modes(connector, edid);
7236                 amdgpu_dm_connector_add_common_modes(encoder, connector);
7237                 amdgpu_dm_connector_add_freesync_modes(connector, edid);
7238         }
7239         amdgpu_dm_fbc_init(connector);
7240
7241         return amdgpu_dm_connector->num_modes;
7242 }
7243
7244 static const u32 supported_colorspaces =
7245         BIT(DRM_MODE_COLORIMETRY_BT709_YCC) |
7246         BIT(DRM_MODE_COLORIMETRY_OPRGB) |
7247         BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) |
7248         BIT(DRM_MODE_COLORIMETRY_BT2020_YCC);
7249
7250 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
7251                                      struct amdgpu_dm_connector *aconnector,
7252                                      int connector_type,
7253                                      struct dc_link *link,
7254                                      int link_index)
7255 {
7256         struct amdgpu_device *adev = drm_to_adev(dm->ddev);
7257
7258         /*
7259          * Some of the properties below require access to state, like bpc.
7260          * Allocate some default initial connector state with our reset helper.
7261          */
7262         if (aconnector->base.funcs->reset)
7263                 aconnector->base.funcs->reset(&aconnector->base);
7264
7265         aconnector->connector_id = link_index;
7266         aconnector->bl_idx = -1;
7267         aconnector->dc_link = link;
7268         aconnector->base.interlace_allowed = false;
7269         aconnector->base.doublescan_allowed = false;
7270         aconnector->base.stereo_allowed = false;
7271         aconnector->base.dpms = DRM_MODE_DPMS_OFF;
7272         aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
7273         aconnector->audio_inst = -1;
7274         aconnector->pack_sdp_v1_3 = false;
7275         aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE;
7276         memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info));
7277         mutex_init(&aconnector->hpd_lock);
7278         mutex_init(&aconnector->handle_mst_msg_ready);
7279
7280         /*
7281          * configure support HPD hot plug connector_>polled default value is 0
7282          * which means HPD hot plug not supported
7283          */
7284         switch (connector_type) {
7285         case DRM_MODE_CONNECTOR_HDMIA:
7286                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7287                 aconnector->base.ycbcr_420_allowed =
7288                         link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
7289                 break;
7290         case DRM_MODE_CONNECTOR_DisplayPort:
7291                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7292                 link->link_enc = link_enc_cfg_get_link_enc(link);
7293                 ASSERT(link->link_enc);
7294                 if (link->link_enc)
7295                         aconnector->base.ycbcr_420_allowed =
7296                         link->link_enc->features.dp_ycbcr420_supported ? true : false;
7297                 break;
7298         case DRM_MODE_CONNECTOR_DVID:
7299                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7300                 break;
7301         default:
7302                 break;
7303         }
7304
7305         drm_object_attach_property(&aconnector->base.base,
7306                                 dm->ddev->mode_config.scaling_mode_property,
7307                                 DRM_MODE_SCALE_NONE);
7308
7309         drm_object_attach_property(&aconnector->base.base,
7310                                 adev->mode_info.underscan_property,
7311                                 UNDERSCAN_OFF);
7312         drm_object_attach_property(&aconnector->base.base,
7313                                 adev->mode_info.underscan_hborder_property,
7314                                 0);
7315         drm_object_attach_property(&aconnector->base.base,
7316                                 adev->mode_info.underscan_vborder_property,
7317                                 0);
7318
7319         if (!aconnector->mst_root)
7320                 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
7321
7322         aconnector->base.state->max_bpc = 16;
7323         aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
7324
7325         if (connector_type == DRM_MODE_CONNECTOR_eDP &&
7326             (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) {
7327                 drm_object_attach_property(&aconnector->base.base,
7328                                 adev->mode_info.abm_level_property, 0);
7329         }
7330
7331         if (connector_type == DRM_MODE_CONNECTOR_HDMIA) {
7332                 if (!drm_mode_create_hdmi_colorspace_property(&aconnector->base, supported_colorspaces))
7333                         drm_connector_attach_colorspace_property(&aconnector->base);
7334         } else if ((connector_type == DRM_MODE_CONNECTOR_DisplayPort && !aconnector->mst_root) ||
7335                    connector_type == DRM_MODE_CONNECTOR_eDP) {
7336                 if (!drm_mode_create_dp_colorspace_property(&aconnector->base, supported_colorspaces))
7337                         drm_connector_attach_colorspace_property(&aconnector->base);
7338         }
7339
7340         if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
7341             connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
7342             connector_type == DRM_MODE_CONNECTOR_eDP) {
7343                 drm_connector_attach_hdr_output_metadata_property(&aconnector->base);
7344
7345                 if (!aconnector->mst_root)
7346                         drm_connector_attach_vrr_capable_property(&aconnector->base);
7347
7348                 if (adev->dm.hdcp_workqueue)
7349                         drm_connector_attach_content_protection_property(&aconnector->base, true);
7350         }
7351 }
7352
7353 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
7354                               struct i2c_msg *msgs, int num)
7355 {
7356         struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
7357         struct ddc_service *ddc_service = i2c->ddc_service;
7358         struct i2c_command cmd;
7359         int i;
7360         int result = -EIO;
7361
7362         cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
7363
7364         if (!cmd.payloads)
7365                 return result;
7366
7367         cmd.number_of_payloads = num;
7368         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
7369         cmd.speed = 100;
7370
7371         for (i = 0; i < num; i++) {
7372                 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
7373                 cmd.payloads[i].address = msgs[i].addr;
7374                 cmd.payloads[i].length = msgs[i].len;
7375                 cmd.payloads[i].data = msgs[i].buf;
7376         }
7377
7378         if (dc_submit_i2c(
7379                         ddc_service->ctx->dc,
7380                         ddc_service->link->link_index,
7381                         &cmd))
7382                 result = num;
7383
7384         kfree(cmd.payloads);
7385         return result;
7386 }
7387
7388 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
7389 {
7390         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
7391 }
7392
7393 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
7394         .master_xfer = amdgpu_dm_i2c_xfer,
7395         .functionality = amdgpu_dm_i2c_func,
7396 };
7397
7398 static struct amdgpu_i2c_adapter *
7399 create_i2c(struct ddc_service *ddc_service,
7400            int link_index,
7401            int *res)
7402 {
7403         struct amdgpu_device *adev = ddc_service->ctx->driver_context;
7404         struct amdgpu_i2c_adapter *i2c;
7405
7406         i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
7407         if (!i2c)
7408                 return NULL;
7409         i2c->base.owner = THIS_MODULE;
7410         i2c->base.class = I2C_CLASS_DDC;
7411         i2c->base.dev.parent = &adev->pdev->dev;
7412         i2c->base.algo = &amdgpu_dm_i2c_algo;
7413         snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
7414         i2c_set_adapdata(&i2c->base, i2c);
7415         i2c->ddc_service = ddc_service;
7416
7417         return i2c;
7418 }
7419
7420
7421 /*
7422  * Note: this function assumes that dc_link_detect() was called for the
7423  * dc_link which will be represented by this aconnector.
7424  */
7425 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
7426                                     struct amdgpu_dm_connector *aconnector,
7427                                     u32 link_index,
7428                                     struct amdgpu_encoder *aencoder)
7429 {
7430         int res = 0;
7431         int connector_type;
7432         struct dc *dc = dm->dc;
7433         struct dc_link *link = dc_get_link_at_index(dc, link_index);
7434         struct amdgpu_i2c_adapter *i2c;
7435
7436         link->priv = aconnector;
7437
7438
7439         i2c = create_i2c(link->ddc, link->link_index, &res);
7440         if (!i2c) {
7441                 DRM_ERROR("Failed to create i2c adapter data\n");
7442                 return -ENOMEM;
7443         }
7444
7445         aconnector->i2c = i2c;
7446         res = i2c_add_adapter(&i2c->base);
7447
7448         if (res) {
7449                 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
7450                 goto out_free;
7451         }
7452
7453         connector_type = to_drm_connector_type(link->connector_signal);
7454
7455         res = drm_connector_init_with_ddc(
7456                         dm->ddev,
7457                         &aconnector->base,
7458                         &amdgpu_dm_connector_funcs,
7459                         connector_type,
7460                         &i2c->base);
7461
7462         if (res) {
7463                 DRM_ERROR("connector_init failed\n");
7464                 aconnector->connector_id = -1;
7465                 goto out_free;
7466         }
7467
7468         drm_connector_helper_add(
7469                         &aconnector->base,
7470                         &amdgpu_dm_connector_helper_funcs);
7471
7472         amdgpu_dm_connector_init_helper(
7473                 dm,
7474                 aconnector,
7475                 connector_type,
7476                 link,
7477                 link_index);
7478
7479         drm_connector_attach_encoder(
7480                 &aconnector->base, &aencoder->base);
7481
7482         if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
7483                 || connector_type == DRM_MODE_CONNECTOR_eDP)
7484                 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);
7485
7486 out_free:
7487         if (res) {
7488                 kfree(i2c);
7489                 aconnector->i2c = NULL;
7490         }
7491         return res;
7492 }
7493
7494 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
7495 {
7496         switch (adev->mode_info.num_crtc) {
7497         case 1:
7498                 return 0x1;
7499         case 2:
7500                 return 0x3;
7501         case 3:
7502                 return 0x7;
7503         case 4:
7504                 return 0xf;
7505         case 5:
7506                 return 0x1f;
7507         case 6:
7508         default:
7509                 return 0x3f;
7510         }
7511 }
7512
7513 static int amdgpu_dm_encoder_init(struct drm_device *dev,
7514                                   struct amdgpu_encoder *aencoder,
7515                                   uint32_t link_index)
7516 {
7517         struct amdgpu_device *adev = drm_to_adev(dev);
7518
7519         int res = drm_encoder_init(dev,
7520                                    &aencoder->base,
7521                                    &amdgpu_dm_encoder_funcs,
7522                                    DRM_MODE_ENCODER_TMDS,
7523                                    NULL);
7524
7525         aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
7526
7527         if (!res)
7528                 aencoder->encoder_id = link_index;
7529         else
7530                 aencoder->encoder_id = -1;
7531
7532         drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
7533
7534         return res;
7535 }
7536
7537 static void manage_dm_interrupts(struct amdgpu_device *adev,
7538                                  struct amdgpu_crtc *acrtc,
7539                                  bool enable)
7540 {
7541         /*
7542          * We have no guarantee that the frontend index maps to the same
7543          * backend index - some even map to more than one.
7544          *
7545          * TODO: Use a different interrupt or check DC itself for the mapping.
7546          */
7547         int irq_type =
7548                 amdgpu_display_crtc_idx_to_irq_type(
7549                         adev,
7550                         acrtc->crtc_id);
7551
7552         if (enable) {
7553                 drm_crtc_vblank_on(&acrtc->base);
7554                 amdgpu_irq_get(
7555                         adev,
7556                         &adev->pageflip_irq,
7557                         irq_type);
7558 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7559                 amdgpu_irq_get(
7560                         adev,
7561                         &adev->vline0_irq,
7562                         irq_type);
7563 #endif
7564         } else {
7565 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7566                 amdgpu_irq_put(
7567                         adev,
7568                         &adev->vline0_irq,
7569                         irq_type);
7570 #endif
7571                 amdgpu_irq_put(
7572                         adev,
7573                         &adev->pageflip_irq,
7574                         irq_type);
7575                 drm_crtc_vblank_off(&acrtc->base);
7576         }
7577 }
7578
7579 static void dm_update_pflip_irq_state(struct amdgpu_device *adev,
7580                                       struct amdgpu_crtc *acrtc)
7581 {
7582         int irq_type =
7583                 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
7584
7585         /**
7586          * This reads the current state for the IRQ and force reapplies
7587          * the setting to hardware.
7588          */
7589         amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type);
7590 }
7591
7592 static bool
7593 is_scaling_state_different(const struct dm_connector_state *dm_state,
7594                            const struct dm_connector_state *old_dm_state)
7595 {
7596         if (dm_state->scaling != old_dm_state->scaling)
7597                 return true;
7598         if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
7599                 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
7600                         return true;
7601         } else  if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
7602                 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
7603                         return true;
7604         } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
7605                    dm_state->underscan_vborder != old_dm_state->underscan_vborder)
7606                 return true;
7607         return false;
7608 }
7609
7610 static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state,
7611                                             struct drm_crtc_state *old_crtc_state,
7612                                             struct drm_connector_state *new_conn_state,
7613                                             struct drm_connector_state *old_conn_state,
7614                                             const struct drm_connector *connector,
7615                                             struct hdcp_workqueue *hdcp_w)
7616 {
7617         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7618         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
7619
7620         pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
7621                 connector->index, connector->status, connector->dpms);
7622         pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
7623                 old_conn_state->content_protection, new_conn_state->content_protection);
7624
7625         if (old_crtc_state)
7626                 pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7627                 old_crtc_state->enable,
7628                 old_crtc_state->active,
7629                 old_crtc_state->mode_changed,
7630                 old_crtc_state->active_changed,
7631                 old_crtc_state->connectors_changed);
7632
7633         if (new_crtc_state)
7634                 pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7635                 new_crtc_state->enable,
7636                 new_crtc_state->active,
7637                 new_crtc_state->mode_changed,
7638                 new_crtc_state->active_changed,
7639                 new_crtc_state->connectors_changed);
7640
7641         /* hdcp content type change */
7642         if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type &&
7643             new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
7644                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7645                 pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__);
7646                 return true;
7647         }
7648
7649         /* CP is being re enabled, ignore this */
7650         if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
7651             new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7652                 if (new_crtc_state && new_crtc_state->mode_changed) {
7653                         new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7654                         pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__);
7655                         return true;
7656                 }
7657                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
7658                 pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__);
7659                 return false;
7660         }
7661
7662         /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED
7663          *
7664          * Handles:     UNDESIRED -> ENABLED
7665          */
7666         if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
7667             new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
7668                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7669
7670         /* Stream removed and re-enabled
7671          *
7672          * Can sometimes overlap with the HPD case,
7673          * thus set update_hdcp to false to avoid
7674          * setting HDCP multiple times.
7675          *
7676          * Handles:     DESIRED -> DESIRED (Special case)
7677          */
7678         if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) &&
7679                 new_conn_state->crtc && new_conn_state->crtc->enabled &&
7680                 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7681                 dm_con_state->update_hdcp = false;
7682                 pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n",
7683                         __func__);
7684                 return true;
7685         }
7686
7687         /* Hot-plug, headless s3, dpms
7688          *
7689          * Only start HDCP if the display is connected/enabled.
7690          * update_hdcp flag will be set to false until the next
7691          * HPD comes in.
7692          *
7693          * Handles:     DESIRED -> DESIRED (Special case)
7694          */
7695         if (dm_con_state->update_hdcp &&
7696         new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
7697         connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
7698                 dm_con_state->update_hdcp = false;
7699                 pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n",
7700                         __func__);
7701                 return true;
7702         }
7703
7704         if (old_conn_state->content_protection == new_conn_state->content_protection) {
7705                 if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7706                         if (new_crtc_state && new_crtc_state->mode_changed) {
7707                                 pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n",
7708                                         __func__);
7709                                 return true;
7710                         }
7711                         pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n",
7712                                 __func__);
7713                         return false;
7714                 }
7715
7716                 pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__);
7717                 return false;
7718         }
7719
7720         if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) {
7721                 pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n",
7722                         __func__);
7723                 return true;
7724         }
7725
7726         pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__);
7727         return false;
7728 }
7729
7730 static void remove_stream(struct amdgpu_device *adev,
7731                           struct amdgpu_crtc *acrtc,
7732                           struct dc_stream_state *stream)
7733 {
7734         /* this is the update mode case */
7735
7736         acrtc->otg_inst = -1;
7737         acrtc->enabled = false;
7738 }
7739
7740 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
7741 {
7742
7743         assert_spin_locked(&acrtc->base.dev->event_lock);
7744         WARN_ON(acrtc->event);
7745
7746         acrtc->event = acrtc->base.state->event;
7747
7748         /* Set the flip status */
7749         acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
7750
7751         /* Mark this event as consumed */
7752         acrtc->base.state->event = NULL;
7753
7754         DC_LOG_PFLIP("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
7755                      acrtc->crtc_id);
7756 }
7757
7758 static void update_freesync_state_on_stream(
7759         struct amdgpu_display_manager *dm,
7760         struct dm_crtc_state *new_crtc_state,
7761         struct dc_stream_state *new_stream,
7762         struct dc_plane_state *surface,
7763         u32 flip_timestamp_in_us)
7764 {
7765         struct mod_vrr_params vrr_params;
7766         struct dc_info_packet vrr_infopacket = {0};
7767         struct amdgpu_device *adev = dm->adev;
7768         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7769         unsigned long flags;
7770         bool pack_sdp_v1_3 = false;
7771         struct amdgpu_dm_connector *aconn;
7772         enum vrr_packet_type packet_type = PACKET_TYPE_VRR;
7773
7774         if (!new_stream)
7775                 return;
7776
7777         /*
7778          * TODO: Determine why min/max totals and vrefresh can be 0 here.
7779          * For now it's sufficient to just guard against these conditions.
7780          */
7781
7782         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7783                 return;
7784
7785         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7786         vrr_params = acrtc->dm_irq_params.vrr_params;
7787
7788         if (surface) {
7789                 mod_freesync_handle_preflip(
7790                         dm->freesync_module,
7791                         surface,
7792                         new_stream,
7793                         flip_timestamp_in_us,
7794                         &vrr_params);
7795
7796                 if (adev->family < AMDGPU_FAMILY_AI &&
7797                     amdgpu_dm_crtc_vrr_active(new_crtc_state)) {
7798                         mod_freesync_handle_v_update(dm->freesync_module,
7799                                                      new_stream, &vrr_params);
7800
7801                         /* Need to call this before the frame ends. */
7802                         dc_stream_adjust_vmin_vmax(dm->dc,
7803                                                    new_crtc_state->stream,
7804                                                    &vrr_params.adjust);
7805                 }
7806         }
7807
7808         aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context;
7809
7810         if (aconn && (aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST || aconn->vsdb_info.replay_mode)) {
7811                 pack_sdp_v1_3 = aconn->pack_sdp_v1_3;
7812
7813                 if (aconn->vsdb_info.amd_vsdb_version == 1)
7814                         packet_type = PACKET_TYPE_FS_V1;
7815                 else if (aconn->vsdb_info.amd_vsdb_version == 2)
7816                         packet_type = PACKET_TYPE_FS_V2;
7817                 else if (aconn->vsdb_info.amd_vsdb_version == 3)
7818                         packet_type = PACKET_TYPE_FS_V3;
7819
7820                 mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL,
7821                                         &new_stream->adaptive_sync_infopacket);
7822         }
7823
7824         mod_freesync_build_vrr_infopacket(
7825                 dm->freesync_module,
7826                 new_stream,
7827                 &vrr_params,
7828                 packet_type,
7829                 TRANSFER_FUNC_UNKNOWN,
7830                 &vrr_infopacket,
7831                 pack_sdp_v1_3);
7832
7833         new_crtc_state->freesync_vrr_info_changed |=
7834                 (memcmp(&new_crtc_state->vrr_infopacket,
7835                         &vrr_infopacket,
7836                         sizeof(vrr_infopacket)) != 0);
7837
7838         acrtc->dm_irq_params.vrr_params = vrr_params;
7839         new_crtc_state->vrr_infopacket = vrr_infopacket;
7840
7841         new_stream->vrr_infopacket = vrr_infopacket;
7842         new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params);
7843
7844         if (new_crtc_state->freesync_vrr_info_changed)
7845                 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
7846                               new_crtc_state->base.crtc->base.id,
7847                               (int)new_crtc_state->base.vrr_enabled,
7848                               (int)vrr_params.state);
7849
7850         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7851 }
7852
7853 static void update_stream_irq_parameters(
7854         struct amdgpu_display_manager *dm,
7855         struct dm_crtc_state *new_crtc_state)
7856 {
7857         struct dc_stream_state *new_stream = new_crtc_state->stream;
7858         struct mod_vrr_params vrr_params;
7859         struct mod_freesync_config config = new_crtc_state->freesync_config;
7860         struct amdgpu_device *adev = dm->adev;
7861         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7862         unsigned long flags;
7863
7864         if (!new_stream)
7865                 return;
7866
7867         /*
7868          * TODO: Determine why min/max totals and vrefresh can be 0 here.
7869          * For now it's sufficient to just guard against these conditions.
7870          */
7871         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7872                 return;
7873
7874         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7875         vrr_params = acrtc->dm_irq_params.vrr_params;
7876
7877         if (new_crtc_state->vrr_supported &&
7878             config.min_refresh_in_uhz &&
7879             config.max_refresh_in_uhz) {
7880                 /*
7881                  * if freesync compatible mode was set, config.state will be set
7882                  * in atomic check
7883                  */
7884                 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz &&
7885                     (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) ||
7886                      new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) {
7887                         vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz;
7888                         vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz;
7889                         vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz;
7890                         vrr_params.state = VRR_STATE_ACTIVE_FIXED;
7891                 } else {
7892                         config.state = new_crtc_state->base.vrr_enabled ?
7893                                                      VRR_STATE_ACTIVE_VARIABLE :
7894                                                      VRR_STATE_INACTIVE;
7895                 }
7896         } else {
7897                 config.state = VRR_STATE_UNSUPPORTED;
7898         }
7899
7900         mod_freesync_build_vrr_params(dm->freesync_module,
7901                                       new_stream,
7902                                       &config, &vrr_params);
7903
7904         new_crtc_state->freesync_config = config;
7905         /* Copy state for access from DM IRQ handler */
7906         acrtc->dm_irq_params.freesync_config = config;
7907         acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes;
7908         acrtc->dm_irq_params.vrr_params = vrr_params;
7909         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7910 }
7911
7912 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
7913                                             struct dm_crtc_state *new_state)
7914 {
7915         bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state);
7916         bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state);
7917
7918         if (!old_vrr_active && new_vrr_active) {
7919                 /* Transition VRR inactive -> active:
7920                  * While VRR is active, we must not disable vblank irq, as a
7921                  * reenable after disable would compute bogus vblank/pflip
7922                  * timestamps if it likely happened inside display front-porch.
7923                  *
7924                  * We also need vupdate irq for the actual core vblank handling
7925                  * at end of vblank.
7926                  */
7927                 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0);
7928                 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0);
7929                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
7930                                  __func__, new_state->base.crtc->base.id);
7931         } else if (old_vrr_active && !new_vrr_active) {
7932                 /* Transition VRR active -> inactive:
7933                  * Allow vblank irq disable again for fixed refresh rate.
7934                  */
7935                 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0);
7936                 drm_crtc_vblank_put(new_state->base.crtc);
7937                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
7938                                  __func__, new_state->base.crtc->base.id);
7939         }
7940 }
7941
7942 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
7943 {
7944         struct drm_plane *plane;
7945         struct drm_plane_state *old_plane_state;
7946         int i;
7947
7948         /*
7949          * TODO: Make this per-stream so we don't issue redundant updates for
7950          * commits with multiple streams.
7951          */
7952         for_each_old_plane_in_state(state, plane, old_plane_state, i)
7953                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
7954                         amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state);
7955 }
7956
7957 static inline uint32_t get_mem_type(struct drm_framebuffer *fb)
7958 {
7959         struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]);
7960
7961         return abo->tbo.resource ? abo->tbo.resource->mem_type : 0;
7962 }
7963
7964 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
7965                                     struct drm_device *dev,
7966                                     struct amdgpu_display_manager *dm,
7967                                     struct drm_crtc *pcrtc,
7968                                     bool wait_for_vblank)
7969 {
7970         u32 i;
7971         u64 timestamp_ns = ktime_get_ns();
7972         struct drm_plane *plane;
7973         struct drm_plane_state *old_plane_state, *new_plane_state;
7974         struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
7975         struct drm_crtc_state *new_pcrtc_state =
7976                         drm_atomic_get_new_crtc_state(state, pcrtc);
7977         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
7978         struct dm_crtc_state *dm_old_crtc_state =
7979                         to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
7980         int planes_count = 0, vpos, hpos;
7981         unsigned long flags;
7982         u32 target_vblank, last_flip_vblank;
7983         bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state);
7984         bool cursor_update = false;
7985         bool pflip_present = false;
7986         bool dirty_rects_changed = false;
7987         struct {
7988                 struct dc_surface_update surface_updates[MAX_SURFACES];
7989                 struct dc_plane_info plane_infos[MAX_SURFACES];
7990                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
7991                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
7992                 struct dc_stream_update stream_update;
7993         } *bundle;
7994
7995         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
7996
7997         if (!bundle) {
7998                 dm_error("Failed to allocate update bundle\n");
7999                 goto cleanup;
8000         }
8001
8002         /*
8003          * Disable the cursor first if we're disabling all the planes.
8004          * It'll remain on the screen after the planes are re-enabled
8005          * if we don't.
8006          */
8007         if (acrtc_state->active_planes == 0)
8008                 amdgpu_dm_commit_cursors(state);
8009
8010         /* update planes when needed */
8011         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
8012                 struct drm_crtc *crtc = new_plane_state->crtc;
8013                 struct drm_crtc_state *new_crtc_state;
8014                 struct drm_framebuffer *fb = new_plane_state->fb;
8015                 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb;
8016                 bool plane_needs_flip;
8017                 struct dc_plane_state *dc_plane;
8018                 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
8019
8020                 /* Cursor plane is handled after stream updates */
8021                 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
8022                         if ((fb && crtc == pcrtc) ||
8023                             (old_plane_state->fb && old_plane_state->crtc == pcrtc))
8024                                 cursor_update = true;
8025
8026                         continue;
8027                 }
8028
8029                 if (!fb || !crtc || pcrtc != crtc)
8030                         continue;
8031
8032                 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
8033                 if (!new_crtc_state->active)
8034                         continue;
8035
8036                 dc_plane = dm_new_plane_state->dc_state;
8037                 if (!dc_plane)
8038                         continue;
8039
8040                 bundle->surface_updates[planes_count].surface = dc_plane;
8041                 if (new_pcrtc_state->color_mgmt_changed) {
8042                         bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
8043                         bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
8044                         bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;
8045                 }
8046
8047                 amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state,
8048                                      &bundle->scaling_infos[planes_count]);
8049
8050                 bundle->surface_updates[planes_count].scaling_info =
8051                         &bundle->scaling_infos[planes_count];
8052
8053                 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
8054
8055                 pflip_present = pflip_present || plane_needs_flip;
8056
8057                 if (!plane_needs_flip) {
8058                         planes_count += 1;
8059                         continue;
8060                 }
8061
8062                 fill_dc_plane_info_and_addr(
8063                         dm->adev, new_plane_state,
8064                         afb->tiling_flags,
8065                         &bundle->plane_infos[planes_count],
8066                         &bundle->flip_addrs[planes_count].address,
8067                         afb->tmz_surface, false);
8068
8069                 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n",
8070                                  new_plane_state->plane->index,
8071                                  bundle->plane_infos[planes_count].dcc.enable);
8072
8073                 bundle->surface_updates[planes_count].plane_info =
8074                         &bundle->plane_infos[planes_count];
8075
8076                 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8077                         fill_dc_dirty_rects(plane, old_plane_state,
8078                                             new_plane_state, new_crtc_state,
8079                                             &bundle->flip_addrs[planes_count],
8080                                             &dirty_rects_changed);
8081
8082                         /*
8083                          * If the dirty regions changed, PSR-SU need to be disabled temporarily
8084                          * and enabled it again after dirty regions are stable to avoid video glitch.
8085                          * PSR-SU will be enabled in vblank_control_worker() if user pause the video
8086                          * during the PSR-SU was disabled.
8087                          */
8088                         if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8089                             acrtc_attach->dm_irq_params.allow_psr_entry &&
8090 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8091                             !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8092 #endif
8093                             dirty_rects_changed) {
8094                                 mutex_lock(&dm->dc_lock);
8095                                 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns =
8096                                 timestamp_ns;
8097                                 if (acrtc_state->stream->link->psr_settings.psr_allow_active)
8098                                         amdgpu_dm_psr_disable(acrtc_state->stream);
8099                                 mutex_unlock(&dm->dc_lock);
8100                         }
8101                 }
8102
8103                 /*
8104                  * Only allow immediate flips for fast updates that don't
8105                  * change memory domain, FB pitch, DCC state, rotation or
8106                  * mirroring.
8107                  *
8108                  * dm_crtc_helper_atomic_check() only accepts async flips with
8109                  * fast updates.
8110                  */
8111                 if (crtc->state->async_flip &&
8112                     (acrtc_state->update_type != UPDATE_TYPE_FAST ||
8113                      get_mem_type(old_plane_state->fb) != get_mem_type(fb)))
8114                         drm_warn_once(state->dev,
8115                                       "[PLANE:%d:%s] async flip with non-fast update\n",
8116                                       plane->base.id, plane->name);
8117
8118                 bundle->flip_addrs[planes_count].flip_immediate =
8119                         crtc->state->async_flip &&
8120                         acrtc_state->update_type == UPDATE_TYPE_FAST &&
8121                         get_mem_type(old_plane_state->fb) == get_mem_type(fb);
8122
8123                 timestamp_ns = ktime_get_ns();
8124                 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
8125                 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
8126                 bundle->surface_updates[planes_count].surface = dc_plane;
8127
8128                 if (!bundle->surface_updates[planes_count].surface) {
8129                         DRM_ERROR("No surface for CRTC: id=%d\n",
8130                                         acrtc_attach->crtc_id);
8131                         continue;
8132                 }
8133
8134                 if (plane == pcrtc->primary)
8135                         update_freesync_state_on_stream(
8136                                 dm,
8137                                 acrtc_state,
8138                                 acrtc_state->stream,
8139                                 dc_plane,
8140                                 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
8141
8142                 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n",
8143                                  __func__,
8144                                  bundle->flip_addrs[planes_count].address.grph.addr.high_part,
8145                                  bundle->flip_addrs[planes_count].address.grph.addr.low_part);
8146
8147                 planes_count += 1;
8148
8149         }
8150
8151         if (pflip_present) {
8152                 if (!vrr_active) {
8153                         /* Use old throttling in non-vrr fixed refresh rate mode
8154                          * to keep flip scheduling based on target vblank counts
8155                          * working in a backwards compatible way, e.g., for
8156                          * clients using the GLX_OML_sync_control extension or
8157                          * DRI3/Present extension with defined target_msc.
8158                          */
8159                         last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);
8160                 } else {
8161                         /* For variable refresh rate mode only:
8162                          * Get vblank of last completed flip to avoid > 1 vrr
8163                          * flips per video frame by use of throttling, but allow
8164                          * flip programming anywhere in the possibly large
8165                          * variable vrr vblank interval for fine-grained flip
8166                          * timing control and more opportunity to avoid stutter
8167                          * on late submission of flips.
8168                          */
8169                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8170                         last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank;
8171                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8172                 }
8173
8174                 target_vblank = last_flip_vblank + wait_for_vblank;
8175
8176                 /*
8177                  * Wait until we're out of the vertical blank period before the one
8178                  * targeted by the flip
8179                  */
8180                 while ((acrtc_attach->enabled &&
8181                         (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
8182                                                             0, &vpos, &hpos, NULL,
8183                                                             NULL, &pcrtc->hwmode)
8184                          & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
8185                         (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
8186                         (int)(target_vblank -
8187                           amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) {
8188                         usleep_range(1000, 1100);
8189                 }
8190
8191                 /**
8192                  * Prepare the flip event for the pageflip interrupt to handle.
8193                  *
8194                  * This only works in the case where we've already turned on the
8195                  * appropriate hardware blocks (eg. HUBP) so in the transition case
8196                  * from 0 -> n planes we have to skip a hardware generated event
8197                  * and rely on sending it from software.
8198                  */
8199                 if (acrtc_attach->base.state->event &&
8200                     acrtc_state->active_planes > 0) {
8201                         drm_crtc_vblank_get(pcrtc);
8202
8203                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8204
8205                         WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
8206                         prepare_flip_isr(acrtc_attach);
8207
8208                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8209                 }
8210
8211                 if (acrtc_state->stream) {
8212                         if (acrtc_state->freesync_vrr_info_changed)
8213                                 bundle->stream_update.vrr_infopacket =
8214                                         &acrtc_state->stream->vrr_infopacket;
8215                 }
8216         } else if (cursor_update && acrtc_state->active_planes > 0 &&
8217                    acrtc_attach->base.state->event) {
8218                 drm_crtc_vblank_get(pcrtc);
8219
8220                 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8221
8222                 acrtc_attach->event = acrtc_attach->base.state->event;
8223                 acrtc_attach->base.state->event = NULL;
8224
8225                 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8226         }
8227
8228         /* Update the planes if changed or disable if we don't have any. */
8229         if ((planes_count || acrtc_state->active_planes == 0) &&
8230                 acrtc_state->stream) {
8231                 /*
8232                  * If PSR or idle optimizations are enabled then flush out
8233                  * any pending work before hardware programming.
8234                  */
8235                 if (dm->vblank_control_workqueue)
8236                         flush_workqueue(dm->vblank_control_workqueue);
8237
8238                 bundle->stream_update.stream = acrtc_state->stream;
8239                 if (new_pcrtc_state->mode_changed) {
8240                         bundle->stream_update.src = acrtc_state->stream->src;
8241                         bundle->stream_update.dst = acrtc_state->stream->dst;
8242                 }
8243
8244                 if (new_pcrtc_state->color_mgmt_changed) {
8245                         /*
8246                          * TODO: This isn't fully correct since we've actually
8247                          * already modified the stream in place.
8248                          */
8249                         bundle->stream_update.gamut_remap =
8250                                 &acrtc_state->stream->gamut_remap_matrix;
8251                         bundle->stream_update.output_csc_transform =
8252                                 &acrtc_state->stream->csc_color_matrix;
8253                         bundle->stream_update.out_transfer_func =
8254                                 acrtc_state->stream->out_transfer_func;
8255                 }
8256
8257                 acrtc_state->stream->abm_level = acrtc_state->abm_level;
8258                 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
8259                         bundle->stream_update.abm_level = &acrtc_state->abm_level;
8260
8261                 mutex_lock(&dm->dc_lock);
8262                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8263                                 acrtc_state->stream->link->psr_settings.psr_allow_active)
8264                         amdgpu_dm_psr_disable(acrtc_state->stream);
8265                 mutex_unlock(&dm->dc_lock);
8266
8267                 /*
8268                  * If FreeSync state on the stream has changed then we need to
8269                  * re-adjust the min/max bounds now that DC doesn't handle this
8270                  * as part of commit.
8271                  */
8272                 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) {
8273                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8274                         dc_stream_adjust_vmin_vmax(
8275                                 dm->dc, acrtc_state->stream,
8276                                 &acrtc_attach->dm_irq_params.vrr_params.adjust);
8277                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8278                 }
8279                 mutex_lock(&dm->dc_lock);
8280                 update_planes_and_stream_adapter(dm->dc,
8281                                          acrtc_state->update_type,
8282                                          planes_count,
8283                                          acrtc_state->stream,
8284                                          &bundle->stream_update,
8285                                          bundle->surface_updates);
8286
8287                 /**
8288                  * Enable or disable the interrupts on the backend.
8289                  *
8290                  * Most pipes are put into power gating when unused.
8291                  *
8292                  * When power gating is enabled on a pipe we lose the
8293                  * interrupt enablement state when power gating is disabled.
8294                  *
8295                  * So we need to update the IRQ control state in hardware
8296                  * whenever the pipe turns on (since it could be previously
8297                  * power gated) or off (since some pipes can't be power gated
8298                  * on some ASICs).
8299                  */
8300                 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes)
8301                         dm_update_pflip_irq_state(drm_to_adev(dev),
8302                                                   acrtc_attach);
8303
8304                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8305                                 acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
8306                                 !acrtc_state->stream->link->psr_settings.psr_feature_enabled)
8307                         amdgpu_dm_link_setup_psr(acrtc_state->stream);
8308
8309                 /* Decrement skip count when PSR is enabled and we're doing fast updates. */
8310                 if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
8311                     acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8312                         struct amdgpu_dm_connector *aconn =
8313                                 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
8314
8315                         if (aconn->psr_skip_count > 0)
8316                                 aconn->psr_skip_count--;
8317
8318                         /* Allow PSR when skip count is 0. */
8319                         acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count;
8320
8321                         /*
8322                          * If sink supports PSR SU, there is no need to rely on
8323                          * a vblank event disable request to enable PSR. PSR SU
8324                          * can be enabled immediately once OS demonstrates an
8325                          * adequate number of fast atomic commits to notify KMD
8326                          * of update events. See `vblank_control_worker()`.
8327                          */
8328                         if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8329                             acrtc_attach->dm_irq_params.allow_psr_entry &&
8330 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8331                             !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8332 #endif
8333                             !acrtc_state->stream->link->psr_settings.psr_allow_active &&
8334                             (timestamp_ns -
8335                             acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) >
8336                             500000000)
8337                                 amdgpu_dm_psr_enable(acrtc_state->stream);
8338                 } else {
8339                         acrtc_attach->dm_irq_params.allow_psr_entry = false;
8340                 }
8341
8342                 mutex_unlock(&dm->dc_lock);
8343         }
8344
8345         /*
8346          * Update cursor state *after* programming all the planes.
8347          * This avoids redundant programming in the case where we're going
8348          * to be disabling a single plane - those pipes are being disabled.
8349          */
8350         if (acrtc_state->active_planes)
8351                 amdgpu_dm_commit_cursors(state);
8352
8353 cleanup:
8354         kfree(bundle);
8355 }
8356
8357 static void amdgpu_dm_commit_audio(struct drm_device *dev,
8358                                    struct drm_atomic_state *state)
8359 {
8360         struct amdgpu_device *adev = drm_to_adev(dev);
8361         struct amdgpu_dm_connector *aconnector;
8362         struct drm_connector *connector;
8363         struct drm_connector_state *old_con_state, *new_con_state;
8364         struct drm_crtc_state *new_crtc_state;
8365         struct dm_crtc_state *new_dm_crtc_state;
8366         const struct dc_stream_status *status;
8367         int i, inst;
8368
8369         /* Notify device removals. */
8370         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8371                 if (old_con_state->crtc != new_con_state->crtc) {
8372                         /* CRTC changes require notification. */
8373                         goto notify;
8374                 }
8375
8376                 if (!new_con_state->crtc)
8377                         continue;
8378
8379                 new_crtc_state = drm_atomic_get_new_crtc_state(
8380                         state, new_con_state->crtc);
8381
8382                 if (!new_crtc_state)
8383                         continue;
8384
8385                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8386                         continue;
8387
8388 notify:
8389                 aconnector = to_amdgpu_dm_connector(connector);
8390
8391                 mutex_lock(&adev->dm.audio_lock);
8392                 inst = aconnector->audio_inst;
8393                 aconnector->audio_inst = -1;
8394                 mutex_unlock(&adev->dm.audio_lock);
8395
8396                 amdgpu_dm_audio_eld_notify(adev, inst);
8397         }
8398
8399         /* Notify audio device additions. */
8400         for_each_new_connector_in_state(state, connector, new_con_state, i) {
8401                 if (!new_con_state->crtc)
8402                         continue;
8403
8404                 new_crtc_state = drm_atomic_get_new_crtc_state(
8405                         state, new_con_state->crtc);
8406
8407                 if (!new_crtc_state)
8408                         continue;
8409
8410                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8411                         continue;
8412
8413                 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
8414                 if (!new_dm_crtc_state->stream)
8415                         continue;
8416
8417                 status = dc_stream_get_status(new_dm_crtc_state->stream);
8418                 if (!status)
8419                         continue;
8420
8421                 aconnector = to_amdgpu_dm_connector(connector);
8422
8423                 mutex_lock(&adev->dm.audio_lock);
8424                 inst = status->audio_inst;
8425                 aconnector->audio_inst = inst;
8426                 mutex_unlock(&adev->dm.audio_lock);
8427
8428                 amdgpu_dm_audio_eld_notify(adev, inst);
8429         }
8430 }
8431
8432 /*
8433  * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
8434  * @crtc_state: the DRM CRTC state
8435  * @stream_state: the DC stream state.
8436  *
8437  * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
8438  * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
8439  */
8440 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
8441                                                 struct dc_stream_state *stream_state)
8442 {
8443         stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
8444 }
8445
8446 static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,
8447                                         struct dc_state *dc_state)
8448 {
8449         struct drm_device *dev = state->dev;
8450         struct amdgpu_device *adev = drm_to_adev(dev);
8451         struct amdgpu_display_manager *dm = &adev->dm;
8452         struct drm_crtc *crtc;
8453         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8454         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8455         bool mode_set_reset_required = false;
8456         u32 i;
8457
8458         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
8459                                       new_crtc_state, i) {
8460                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8461
8462                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8463
8464                 if (old_crtc_state->active &&
8465                     (!new_crtc_state->active ||
8466                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8467                         manage_dm_interrupts(adev, acrtc, false);
8468                         dc_stream_release(dm_old_crtc_state->stream);
8469                 }
8470         }
8471
8472         drm_atomic_helper_calc_timestamping_constants(state);
8473
8474         /* update changed items */
8475         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8476                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8477
8478                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8479                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8480
8481                 drm_dbg_state(state->dev,
8482                         "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n",
8483                         acrtc->crtc_id,
8484                         new_crtc_state->enable,
8485                         new_crtc_state->active,
8486                         new_crtc_state->planes_changed,
8487                         new_crtc_state->mode_changed,
8488                         new_crtc_state->active_changed,
8489                         new_crtc_state->connectors_changed);
8490
8491                 /* Disable cursor if disabling crtc */
8492                 if (old_crtc_state->active && !new_crtc_state->active) {
8493                         struct dc_cursor_position position;
8494
8495                         memset(&position, 0, sizeof(position));
8496                         mutex_lock(&dm->dc_lock);
8497                         dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position);
8498                         mutex_unlock(&dm->dc_lock);
8499                 }
8500
8501                 /* Copy all transient state flags into dc state */
8502                 if (dm_new_crtc_state->stream) {
8503                         amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
8504                                                             dm_new_crtc_state->stream);
8505                 }
8506
8507                 /* handles headless hotplug case, updating new_state and
8508                  * aconnector as needed
8509                  */
8510
8511                 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
8512
8513                         DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
8514
8515                         if (!dm_new_crtc_state->stream) {
8516                                 /*
8517                                  * this could happen because of issues with
8518                                  * userspace notifications delivery.
8519                                  * In this case userspace tries to set mode on
8520                                  * display which is disconnected in fact.
8521                                  * dc_sink is NULL in this case on aconnector.
8522                                  * We expect reset mode will come soon.
8523                                  *
8524                                  * This can also happen when unplug is done
8525                                  * during resume sequence ended
8526                                  *
8527                                  * In this case, we want to pretend we still
8528                                  * have a sink to keep the pipe running so that
8529                                  * hw state is consistent with the sw state
8530                                  */
8531                                 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
8532                                                 __func__, acrtc->base.base.id);
8533                                 continue;
8534                         }
8535
8536                         if (dm_old_crtc_state->stream)
8537                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8538
8539                         pm_runtime_get_noresume(dev->dev);
8540
8541                         acrtc->enabled = true;
8542                         acrtc->hw_mode = new_crtc_state->mode;
8543                         crtc->hwmode = new_crtc_state->mode;
8544                         mode_set_reset_required = true;
8545                 } else if (modereset_required(new_crtc_state)) {
8546                         DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
8547                         /* i.e. reset mode */
8548                         if (dm_old_crtc_state->stream)
8549                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8550
8551                         mode_set_reset_required = true;
8552                 }
8553         } /* for_each_crtc_in_state() */
8554
8555         /* if there mode set or reset, disable eDP PSR */
8556         if (mode_set_reset_required) {
8557                 if (dm->vblank_control_workqueue)
8558                         flush_workqueue(dm->vblank_control_workqueue);
8559
8560                 amdgpu_dm_psr_disable_all(dm);
8561         }
8562
8563         dm_enable_per_frame_crtc_master_sync(dc_state);
8564         mutex_lock(&dm->dc_lock);
8565         WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
8566
8567         /* Allow idle optimization when vblank count is 0 for display off */
8568         if (dm->active_vblank_irq_count == 0)
8569                 dc_allow_idle_optimizations(dm->dc, true);
8570         mutex_unlock(&dm->dc_lock);
8571
8572         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8573                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8574
8575                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8576
8577                 if (dm_new_crtc_state->stream != NULL) {
8578                         const struct dc_stream_status *status =
8579                                         dc_stream_get_status(dm_new_crtc_state->stream);
8580
8581                         if (!status)
8582                                 status = dc_stream_get_status_from_state(dc_state,
8583                                                                          dm_new_crtc_state->stream);
8584                         if (!status)
8585                                 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
8586                         else
8587                                 acrtc->otg_inst = status->primary_otg_inst;
8588                 }
8589         }
8590 }
8591
8592 /**
8593  * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
8594  * @state: The atomic state to commit
8595  *
8596  * This will tell DC to commit the constructed DC state from atomic_check,
8597  * programming the hardware. Any failures here implies a hardware failure, since
8598  * atomic check should have filtered anything non-kosher.
8599  */
8600 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
8601 {
8602         struct drm_device *dev = state->dev;
8603         struct amdgpu_device *adev = drm_to_adev(dev);
8604         struct amdgpu_display_manager *dm = &adev->dm;
8605         struct dm_atomic_state *dm_state;
8606         struct dc_state *dc_state = NULL;
8607         u32 i, j;
8608         struct drm_crtc *crtc;
8609         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8610         unsigned long flags;
8611         bool wait_for_vblank = true;
8612         struct drm_connector *connector;
8613         struct drm_connector_state *old_con_state, *new_con_state;
8614         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8615         int crtc_disable_count = 0;
8616
8617         trace_amdgpu_dm_atomic_commit_tail_begin(state);
8618
8619         drm_atomic_helper_update_legacy_modeset_state(dev, state);
8620         drm_dp_mst_atomic_wait_for_dependencies(state);
8621
8622         dm_state = dm_atomic_get_new_state(state);
8623         if (dm_state && dm_state->context) {
8624                 dc_state = dm_state->context;
8625                 amdgpu_dm_commit_streams(state, dc_state);
8626         }
8627
8628         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8629                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8630                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8631                 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8632
8633                 if (!adev->dm.hdcp_workqueue)
8634                         continue;
8635
8636                 pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i);
8637
8638                 if (!connector)
8639                         continue;
8640
8641                 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
8642                         connector->index, connector->status, connector->dpms);
8643                 pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
8644                         old_con_state->content_protection, new_con_state->content_protection);
8645
8646                 if (aconnector->dc_sink) {
8647                         if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
8648                                 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) {
8649                                 pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n",
8650                                 aconnector->dc_sink->edid_caps.display_name);
8651                         }
8652                 }
8653
8654                 new_crtc_state = NULL;
8655                 old_crtc_state = NULL;
8656
8657                 if (acrtc) {
8658                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8659                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8660                 }
8661
8662                 if (old_crtc_state)
8663                         pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8664                         old_crtc_state->enable,
8665                         old_crtc_state->active,
8666                         old_crtc_state->mode_changed,
8667                         old_crtc_state->active_changed,
8668                         old_crtc_state->connectors_changed);
8669
8670                 if (new_crtc_state)
8671                         pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8672                         new_crtc_state->enable,
8673                         new_crtc_state->active,
8674                         new_crtc_state->mode_changed,
8675                         new_crtc_state->active_changed,
8676                         new_crtc_state->connectors_changed);
8677         }
8678
8679         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8680                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8681                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8682                 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8683
8684                 if (!adev->dm.hdcp_workqueue)
8685                         continue;
8686
8687                 new_crtc_state = NULL;
8688                 old_crtc_state = NULL;
8689
8690                 if (acrtc) {
8691                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8692                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8693                 }
8694
8695                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8696
8697                 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
8698                     connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
8699                         hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
8700                         new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
8701                         dm_new_con_state->update_hdcp = true;
8702                         continue;
8703                 }
8704
8705                 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state,
8706                                                                                         old_con_state, connector, adev->dm.hdcp_workqueue)) {
8707                         /* when display is unplugged from mst hub, connctor will
8708                          * be destroyed within dm_dp_mst_connector_destroy. connector
8709                          * hdcp perperties, like type, undesired, desired, enabled,
8710                          * will be lost. So, save hdcp properties into hdcp_work within
8711                          * amdgpu_dm_atomic_commit_tail. if the same display is
8712                          * plugged back with same display index, its hdcp properties
8713                          * will be retrieved from hdcp_work within dm_dp_mst_get_modes
8714                          */
8715
8716                         bool enable_encryption = false;
8717
8718                         if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED)
8719                                 enable_encryption = true;
8720
8721                         if (aconnector->dc_link && aconnector->dc_sink &&
8722                                 aconnector->dc_link->type == dc_connection_mst_branch) {
8723                                 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
8724                                 struct hdcp_workqueue *hdcp_w =
8725                                         &hdcp_work[aconnector->dc_link->link_index];
8726
8727                                 hdcp_w->hdcp_content_type[connector->index] =
8728                                         new_con_state->hdcp_content_type;
8729                                 hdcp_w->content_protection[connector->index] =
8730                                         new_con_state->content_protection;
8731                         }
8732
8733                         if (new_crtc_state && new_crtc_state->mode_changed &&
8734                                 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED)
8735                                 enable_encryption = true;
8736
8737                         DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption);
8738
8739                         hdcp_update_display(
8740                                 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
8741                                 new_con_state->hdcp_content_type, enable_encryption);
8742                 }
8743         }
8744
8745         /* Handle connector state changes */
8746         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8747                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8748                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
8749                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8750                 struct dc_surface_update *dummy_updates;
8751                 struct dc_stream_update stream_update;
8752                 struct dc_info_packet hdr_packet;
8753                 struct dc_stream_status *status = NULL;
8754                 bool abm_changed, hdr_changed, scaling_changed;
8755
8756                 memset(&stream_update, 0, sizeof(stream_update));
8757
8758                 if (acrtc) {
8759                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8760                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8761                 }
8762
8763                 /* Skip any modesets/resets */
8764                 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
8765                         continue;
8766
8767                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8768                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8769
8770                 scaling_changed = is_scaling_state_different(dm_new_con_state,
8771                                                              dm_old_con_state);
8772
8773                 abm_changed = dm_new_crtc_state->abm_level !=
8774                               dm_old_crtc_state->abm_level;
8775
8776                 hdr_changed =
8777                         !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state);
8778
8779                 if (!scaling_changed && !abm_changed && !hdr_changed)
8780                         continue;
8781
8782                 stream_update.stream = dm_new_crtc_state->stream;
8783                 if (scaling_changed) {
8784                         update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
8785                                         dm_new_con_state, dm_new_crtc_state->stream);
8786
8787                         stream_update.src = dm_new_crtc_state->stream->src;
8788                         stream_update.dst = dm_new_crtc_state->stream->dst;
8789                 }
8790
8791                 if (abm_changed) {
8792                         dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
8793
8794                         stream_update.abm_level = &dm_new_crtc_state->abm_level;
8795                 }
8796
8797                 if (hdr_changed) {
8798                         fill_hdr_info_packet(new_con_state, &hdr_packet);
8799                         stream_update.hdr_static_metadata = &hdr_packet;
8800                 }
8801
8802                 status = dc_stream_get_status(dm_new_crtc_state->stream);
8803
8804                 if (WARN_ON(!status))
8805                         continue;
8806
8807                 WARN_ON(!status->plane_count);
8808
8809                 /*
8810                  * TODO: DC refuses to perform stream updates without a dc_surface_update.
8811                  * Here we create an empty update on each plane.
8812                  * To fix this, DC should permit updating only stream properties.
8813                  */
8814                 dummy_updates = kzalloc(sizeof(struct dc_surface_update) * MAX_SURFACES, GFP_ATOMIC);
8815                 for (j = 0; j < status->plane_count; j++)
8816                         dummy_updates[j].surface = status->plane_states[0];
8817
8818
8819                 mutex_lock(&dm->dc_lock);
8820                 dc_update_planes_and_stream(dm->dc,
8821                                             dummy_updates,
8822                                             status->plane_count,
8823                                             dm_new_crtc_state->stream,
8824                                             &stream_update);
8825                 mutex_unlock(&dm->dc_lock);
8826                 kfree(dummy_updates);
8827         }
8828
8829         /**
8830          * Enable interrupts for CRTCs that are newly enabled or went through
8831          * a modeset. It was intentionally deferred until after the front end
8832          * state was modified to wait until the OTG was on and so the IRQ
8833          * handlers didn't access stale or invalid state.
8834          */
8835         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8836                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8837 #ifdef CONFIG_DEBUG_FS
8838                 enum amdgpu_dm_pipe_crc_source cur_crc_src;
8839 #endif
8840                 /* Count number of newly disabled CRTCs for dropping PM refs later. */
8841                 if (old_crtc_state->active && !new_crtc_state->active)
8842                         crtc_disable_count++;
8843
8844                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8845                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8846
8847                 /* For freesync config update on crtc state and params for irq */
8848                 update_stream_irq_parameters(dm, dm_new_crtc_state);
8849
8850 #ifdef CONFIG_DEBUG_FS
8851                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8852                 cur_crc_src = acrtc->dm_irq_params.crc_src;
8853                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8854 #endif
8855
8856                 if (new_crtc_state->active &&
8857                     (!old_crtc_state->active ||
8858                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8859                         dc_stream_retain(dm_new_crtc_state->stream);
8860                         acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
8861                         manage_dm_interrupts(adev, acrtc, true);
8862                 }
8863                 /* Handle vrr on->off / off->on transitions */
8864                 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state);
8865
8866 #ifdef CONFIG_DEBUG_FS
8867                 if (new_crtc_state->active &&
8868                     (!old_crtc_state->active ||
8869                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8870                         /**
8871                          * Frontend may have changed so reapply the CRC capture
8872                          * settings for the stream.
8873                          */
8874                         if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
8875 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
8876                                 if (amdgpu_dm_crc_window_is_activated(crtc)) {
8877                                         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8878                                         acrtc->dm_irq_params.window_param.update_win = true;
8879
8880                                         /**
8881                                          * It takes 2 frames for HW to stably generate CRC when
8882                                          * resuming from suspend, so we set skip_frame_cnt 2.
8883                                          */
8884                                         acrtc->dm_irq_params.window_param.skip_frame_cnt = 2;
8885                                         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8886                                 }
8887 #endif
8888                                 if (amdgpu_dm_crtc_configure_crc_source(
8889                                         crtc, dm_new_crtc_state, cur_crc_src))
8890                                         DRM_DEBUG_DRIVER("Failed to configure crc source");
8891                         }
8892                 }
8893 #endif
8894         }
8895
8896         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
8897                 if (new_crtc_state->async_flip)
8898                         wait_for_vblank = false;
8899
8900         /* update planes when needed per crtc*/
8901         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
8902                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8903
8904                 if (dm_new_crtc_state->stream)
8905                         amdgpu_dm_commit_planes(state, dev, dm, crtc, wait_for_vblank);
8906         }
8907
8908         /* Update audio instances for each connector. */
8909         amdgpu_dm_commit_audio(dev, state);
8910
8911         /* restore the backlight level */
8912         for (i = 0; i < dm->num_of_edps; i++) {
8913                 if (dm->backlight_dev[i] &&
8914                     (dm->actual_brightness[i] != dm->brightness[i]))
8915                         amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
8916         }
8917
8918         /*
8919          * send vblank event on all events not handled in flip and
8920          * mark consumed event for drm_atomic_helper_commit_hw_done
8921          */
8922         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8923         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8924
8925                 if (new_crtc_state->event)
8926                         drm_send_event_locked(dev, &new_crtc_state->event->base);
8927
8928                 new_crtc_state->event = NULL;
8929         }
8930         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8931
8932         /* Signal HW programming completion */
8933         drm_atomic_helper_commit_hw_done(state);
8934
8935         if (wait_for_vblank)
8936                 drm_atomic_helper_wait_for_flip_done(dev, state);
8937
8938         drm_atomic_helper_cleanup_planes(dev, state);
8939
8940         /* Don't free the memory if we are hitting this as part of suspend.
8941          * This way we don't free any memory during suspend; see
8942          * amdgpu_bo_free_kernel().  The memory will be freed in the first
8943          * non-suspend modeset or when the driver is torn down.
8944          */
8945         if (!adev->in_suspend) {
8946                 /* return the stolen vga memory back to VRAM */
8947                 if (!adev->mman.keep_stolen_vga_memory)
8948                         amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
8949                 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
8950         }
8951
8952         /*
8953          * Finally, drop a runtime PM reference for each newly disabled CRTC,
8954          * so we can put the GPU into runtime suspend if we're not driving any
8955          * displays anymore
8956          */
8957         for (i = 0; i < crtc_disable_count; i++)
8958                 pm_runtime_put_autosuspend(dev->dev);
8959         pm_runtime_mark_last_busy(dev->dev);
8960 }
8961
8962 static int dm_force_atomic_commit(struct drm_connector *connector)
8963 {
8964         int ret = 0;
8965         struct drm_device *ddev = connector->dev;
8966         struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
8967         struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
8968         struct drm_plane *plane = disconnected_acrtc->base.primary;
8969         struct drm_connector_state *conn_state;
8970         struct drm_crtc_state *crtc_state;
8971         struct drm_plane_state *plane_state;
8972
8973         if (!state)
8974                 return -ENOMEM;
8975
8976         state->acquire_ctx = ddev->mode_config.acquire_ctx;
8977
8978         /* Construct an atomic state to restore previous display setting */
8979
8980         /*
8981          * Attach connectors to drm_atomic_state
8982          */
8983         conn_state = drm_atomic_get_connector_state(state, connector);
8984
8985         ret = PTR_ERR_OR_ZERO(conn_state);
8986         if (ret)
8987                 goto out;
8988
8989         /* Attach crtc to drm_atomic_state*/
8990         crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
8991
8992         ret = PTR_ERR_OR_ZERO(crtc_state);
8993         if (ret)
8994                 goto out;
8995
8996         /* force a restore */
8997         crtc_state->mode_changed = true;
8998
8999         /* Attach plane to drm_atomic_state */
9000         plane_state = drm_atomic_get_plane_state(state, plane);
9001
9002         ret = PTR_ERR_OR_ZERO(plane_state);
9003         if (ret)
9004                 goto out;
9005
9006         /* Call commit internally with the state we just constructed */
9007         ret = drm_atomic_commit(state);
9008
9009 out:
9010         drm_atomic_state_put(state);
9011         if (ret)
9012                 DRM_ERROR("Restoring old state failed with %i\n", ret);
9013
9014         return ret;
9015 }
9016
9017 /*
9018  * This function handles all cases when set mode does not come upon hotplug.
9019  * This includes when a display is unplugged then plugged back into the
9020  * same port and when running without usermode desktop manager supprot
9021  */
9022 void dm_restore_drm_connector_state(struct drm_device *dev,
9023                                     struct drm_connector *connector)
9024 {
9025         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
9026         struct amdgpu_crtc *disconnected_acrtc;
9027         struct dm_crtc_state *acrtc_state;
9028
9029         if (!aconnector->dc_sink || !connector->state || !connector->encoder)
9030                 return;
9031
9032         disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
9033         if (!disconnected_acrtc)
9034                 return;
9035
9036         acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
9037         if (!acrtc_state->stream)
9038                 return;
9039
9040         /*
9041          * If the previous sink is not released and different from the current,
9042          * we deduce we are in a state where we can not rely on usermode call
9043          * to turn on the display, so we do it here
9044          */
9045         if (acrtc_state->stream->sink != aconnector->dc_sink)
9046                 dm_force_atomic_commit(&aconnector->base);
9047 }
9048
9049 /*
9050  * Grabs all modesetting locks to serialize against any blocking commits,
9051  * Waits for completion of all non blocking commits.
9052  */
9053 static int do_aquire_global_lock(struct drm_device *dev,
9054                                  struct drm_atomic_state *state)
9055 {
9056         struct drm_crtc *crtc;
9057         struct drm_crtc_commit *commit;
9058         long ret;
9059
9060         /*
9061          * Adding all modeset locks to aquire_ctx will
9062          * ensure that when the framework release it the
9063          * extra locks we are locking here will get released to
9064          */
9065         ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
9066         if (ret)
9067                 return ret;
9068
9069         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9070                 spin_lock(&crtc->commit_lock);
9071                 commit = list_first_entry_or_null(&crtc->commit_list,
9072                                 struct drm_crtc_commit, commit_entry);
9073                 if (commit)
9074                         drm_crtc_commit_get(commit);
9075                 spin_unlock(&crtc->commit_lock);
9076
9077                 if (!commit)
9078                         continue;
9079
9080                 /*
9081                  * Make sure all pending HW programming completed and
9082                  * page flips done
9083                  */
9084                 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
9085
9086                 if (ret > 0)
9087                         ret = wait_for_completion_interruptible_timeout(
9088                                         &commit->flip_done, 10*HZ);
9089
9090                 if (ret == 0)
9091                         DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done timed out\n",
9092                                   crtc->base.id, crtc->name);
9093
9094                 drm_crtc_commit_put(commit);
9095         }
9096
9097         return ret < 0 ? ret : 0;
9098 }
9099
9100 static void get_freesync_config_for_crtc(
9101         struct dm_crtc_state *new_crtc_state,
9102         struct dm_connector_state *new_con_state)
9103 {
9104         struct mod_freesync_config config = {0};
9105         struct amdgpu_dm_connector *aconnector =
9106                         to_amdgpu_dm_connector(new_con_state->base.connector);
9107         struct drm_display_mode *mode = &new_crtc_state->base.mode;
9108         int vrefresh = drm_mode_vrefresh(mode);
9109         bool fs_vid_mode = false;
9110
9111         new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
9112                                         vrefresh >= aconnector->min_vfreq &&
9113                                         vrefresh <= aconnector->max_vfreq;
9114
9115         if (new_crtc_state->vrr_supported) {
9116                 new_crtc_state->stream->ignore_msa_timing_param = true;
9117                 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
9118
9119                 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000;
9120                 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000;
9121                 config.vsif_supported = true;
9122                 config.btr = true;
9123
9124                 if (fs_vid_mode) {
9125                         config.state = VRR_STATE_ACTIVE_FIXED;
9126                         config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz;
9127                         goto out;
9128                 } else if (new_crtc_state->base.vrr_enabled) {
9129                         config.state = VRR_STATE_ACTIVE_VARIABLE;
9130                 } else {
9131                         config.state = VRR_STATE_INACTIVE;
9132                 }
9133         }
9134 out:
9135         new_crtc_state->freesync_config = config;
9136 }
9137
9138 static void reset_freesync_config_for_crtc(
9139         struct dm_crtc_state *new_crtc_state)
9140 {
9141         new_crtc_state->vrr_supported = false;
9142
9143         memset(&new_crtc_state->vrr_infopacket, 0,
9144                sizeof(new_crtc_state->vrr_infopacket));
9145 }
9146
9147 static bool
9148 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
9149                                  struct drm_crtc_state *new_crtc_state)
9150 {
9151         const struct drm_display_mode *old_mode, *new_mode;
9152
9153         if (!old_crtc_state || !new_crtc_state)
9154                 return false;
9155
9156         old_mode = &old_crtc_state->mode;
9157         new_mode = &new_crtc_state->mode;
9158
9159         if (old_mode->clock       == new_mode->clock &&
9160             old_mode->hdisplay    == new_mode->hdisplay &&
9161             old_mode->vdisplay    == new_mode->vdisplay &&
9162             old_mode->htotal      == new_mode->htotal &&
9163             old_mode->vtotal      != new_mode->vtotal &&
9164             old_mode->hsync_start == new_mode->hsync_start &&
9165             old_mode->vsync_start != new_mode->vsync_start &&
9166             old_mode->hsync_end   == new_mode->hsync_end &&
9167             old_mode->vsync_end   != new_mode->vsync_end &&
9168             old_mode->hskew       == new_mode->hskew &&
9169             old_mode->vscan       == new_mode->vscan &&
9170             (old_mode->vsync_end - old_mode->vsync_start) ==
9171             (new_mode->vsync_end - new_mode->vsync_start))
9172                 return true;
9173
9174         return false;
9175 }
9176
9177 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state)
9178 {
9179         u64 num, den, res;
9180         struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
9181
9182         dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;
9183
9184         num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000;
9185         den = (unsigned long long)new_crtc_state->mode.htotal *
9186               (unsigned long long)new_crtc_state->mode.vtotal;
9187
9188         res = div_u64(num, den);
9189         dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
9190 }
9191
9192 static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
9193                          struct drm_atomic_state *state,
9194                          struct drm_crtc *crtc,
9195                          struct drm_crtc_state *old_crtc_state,
9196                          struct drm_crtc_state *new_crtc_state,
9197                          bool enable,
9198                          bool *lock_and_validation_needed)
9199 {
9200         struct dm_atomic_state *dm_state = NULL;
9201         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9202         struct dc_stream_state *new_stream;
9203         int ret = 0;
9204
9205         /*
9206          * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
9207          * update changed items
9208          */
9209         struct amdgpu_crtc *acrtc = NULL;
9210         struct amdgpu_dm_connector *aconnector = NULL;
9211         struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
9212         struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
9213
9214         new_stream = NULL;
9215
9216         dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9217         dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9218         acrtc = to_amdgpu_crtc(crtc);
9219         aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
9220
9221         /* TODO This hack should go away */
9222         if (aconnector && enable) {
9223                 /* Make sure fake sink is created in plug-in scenario */
9224                 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
9225                                                             &aconnector->base);
9226                 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
9227                                                             &aconnector->base);
9228
9229                 if (IS_ERR(drm_new_conn_state)) {
9230                         ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
9231                         goto fail;
9232                 }
9233
9234                 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
9235                 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
9236
9237                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9238                         goto skip_modeset;
9239
9240                 new_stream = create_validate_stream_for_sink(aconnector,
9241                                                              &new_crtc_state->mode,
9242                                                              dm_new_conn_state,
9243                                                              dm_old_crtc_state->stream);
9244
9245                 /*
9246                  * we can have no stream on ACTION_SET if a display
9247                  * was disconnected during S3, in this case it is not an
9248                  * error, the OS will be updated after detection, and
9249                  * will do the right thing on next atomic commit
9250                  */
9251
9252                 if (!new_stream) {
9253                         DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
9254                                         __func__, acrtc->base.base.id);
9255                         ret = -ENOMEM;
9256                         goto fail;
9257                 }
9258
9259                 /*
9260                  * TODO: Check VSDB bits to decide whether this should
9261                  * be enabled or not.
9262                  */
9263                 new_stream->triggered_crtc_reset.enabled =
9264                         dm->force_timing_sync;
9265
9266                 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9267
9268                 ret = fill_hdr_info_packet(drm_new_conn_state,
9269                                            &new_stream->hdr_static_metadata);
9270                 if (ret)
9271                         goto fail;
9272
9273                 /*
9274                  * If we already removed the old stream from the context
9275                  * (and set the new stream to NULL) then we can't reuse
9276                  * the old stream even if the stream and scaling are unchanged.
9277                  * We'll hit the BUG_ON and black screen.
9278                  *
9279                  * TODO: Refactor this function to allow this check to work
9280                  * in all conditions.
9281                  */
9282                 if (dm_new_crtc_state->stream &&
9283                     is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))
9284                         goto skip_modeset;
9285
9286                 if (dm_new_crtc_state->stream &&
9287                     dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9288                     dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
9289                         new_crtc_state->mode_changed = false;
9290                         DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
9291                                          new_crtc_state->mode_changed);
9292                 }
9293         }
9294
9295         /* mode_changed flag may get updated above, need to check again */
9296         if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9297                 goto skip_modeset;
9298
9299         drm_dbg_state(state->dev,
9300                 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n",
9301                 acrtc->crtc_id,
9302                 new_crtc_state->enable,
9303                 new_crtc_state->active,
9304                 new_crtc_state->planes_changed,
9305                 new_crtc_state->mode_changed,
9306                 new_crtc_state->active_changed,
9307                 new_crtc_state->connectors_changed);
9308
9309         /* Remove stream for any changed/disabled CRTC */
9310         if (!enable) {
9311
9312                 if (!dm_old_crtc_state->stream)
9313                         goto skip_modeset;
9314
9315                 /* Unset freesync video if it was active before */
9316                 if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) {
9317                         dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE;
9318                         dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0;
9319                 }
9320
9321                 /* Now check if we should set freesync video mode */
9322                 if (dm_new_crtc_state->stream &&
9323                     dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9324                     dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream) &&
9325                     is_timing_unchanged_for_freesync(new_crtc_state,
9326                                                      old_crtc_state)) {
9327                         new_crtc_state->mode_changed = false;
9328                         DRM_DEBUG_DRIVER(
9329                                 "Mode change not required for front porch change, setting mode_changed to %d",
9330                                 new_crtc_state->mode_changed);
9331
9332                         set_freesync_fixed_config(dm_new_crtc_state);
9333
9334                         goto skip_modeset;
9335                 } else if (aconnector &&
9336                            is_freesync_video_mode(&new_crtc_state->mode,
9337                                                   aconnector)) {
9338                         struct drm_display_mode *high_mode;
9339
9340                         high_mode = get_highest_refresh_rate_mode(aconnector, false);
9341                         if (!drm_mode_equal(&new_crtc_state->mode, high_mode))
9342                                 set_freesync_fixed_config(dm_new_crtc_state);
9343                 }
9344
9345                 ret = dm_atomic_get_state(state, &dm_state);
9346                 if (ret)
9347                         goto fail;
9348
9349                 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
9350                                 crtc->base.id);
9351
9352                 /* i.e. reset mode */
9353                 if (dc_remove_stream_from_ctx(
9354                                 dm->dc,
9355                                 dm_state->context,
9356                                 dm_old_crtc_state->stream) != DC_OK) {
9357                         ret = -EINVAL;
9358                         goto fail;
9359                 }
9360
9361                 dc_stream_release(dm_old_crtc_state->stream);
9362                 dm_new_crtc_state->stream = NULL;
9363
9364                 reset_freesync_config_for_crtc(dm_new_crtc_state);
9365
9366                 *lock_and_validation_needed = true;
9367
9368         } else {/* Add stream for any updated/enabled CRTC */
9369                 /*
9370                  * Quick fix to prevent NULL pointer on new_stream when
9371                  * added MST connectors not found in existing crtc_state in the chained mode
9372                  * TODO: need to dig out the root cause of that
9373                  */
9374                 if (!aconnector)
9375                         goto skip_modeset;
9376
9377                 if (modereset_required(new_crtc_state))
9378                         goto skip_modeset;
9379
9380                 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream,
9381                                      dm_old_crtc_state->stream)) {
9382
9383                         WARN_ON(dm_new_crtc_state->stream);
9384
9385                         ret = dm_atomic_get_state(state, &dm_state);
9386                         if (ret)
9387                                 goto fail;
9388
9389                         dm_new_crtc_state->stream = new_stream;
9390
9391                         dc_stream_retain(new_stream);
9392
9393                         DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n",
9394                                          crtc->base.id);
9395
9396                         if (dc_add_stream_to_ctx(
9397                                         dm->dc,
9398                                         dm_state->context,
9399                                         dm_new_crtc_state->stream) != DC_OK) {
9400                                 ret = -EINVAL;
9401                                 goto fail;
9402                         }
9403
9404                         *lock_and_validation_needed = true;
9405                 }
9406         }
9407
9408 skip_modeset:
9409         /* Release extra reference */
9410         if (new_stream)
9411                 dc_stream_release(new_stream);
9412
9413         /*
9414          * We want to do dc stream updates that do not require a
9415          * full modeset below.
9416          */
9417         if (!(enable && aconnector && new_crtc_state->active))
9418                 return 0;
9419         /*
9420          * Given above conditions, the dc state cannot be NULL because:
9421          * 1. We're in the process of enabling CRTCs (just been added
9422          *    to the dc context, or already is on the context)
9423          * 2. Has a valid connector attached, and
9424          * 3. Is currently active and enabled.
9425          * => The dc stream state currently exists.
9426          */
9427         BUG_ON(dm_new_crtc_state->stream == NULL);
9428
9429         /* Scaling or underscan settings */
9430         if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) ||
9431                                 drm_atomic_crtc_needs_modeset(new_crtc_state))
9432                 update_stream_scaling_settings(
9433                         &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
9434
9435         /* ABM settings */
9436         dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9437
9438         /*
9439          * Color management settings. We also update color properties
9440          * when a modeset is needed, to ensure it gets reprogrammed.
9441          */
9442         if (dm_new_crtc_state->base.color_mgmt_changed ||
9443             drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9444                 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
9445                 if (ret)
9446                         goto fail;
9447         }
9448
9449         /* Update Freesync settings. */
9450         get_freesync_config_for_crtc(dm_new_crtc_state,
9451                                      dm_new_conn_state);
9452
9453         return ret;
9454
9455 fail:
9456         if (new_stream)
9457                 dc_stream_release(new_stream);
9458         return ret;
9459 }
9460
9461 static bool should_reset_plane(struct drm_atomic_state *state,
9462                                struct drm_plane *plane,
9463                                struct drm_plane_state *old_plane_state,
9464                                struct drm_plane_state *new_plane_state)
9465 {
9466         struct drm_plane *other;
9467         struct drm_plane_state *old_other_state, *new_other_state;
9468         struct drm_crtc_state *new_crtc_state;
9469         int i;
9470
9471         /*
9472          * TODO: Remove this hack once the checks below are sufficient
9473          * enough to determine when we need to reset all the planes on
9474          * the stream.
9475          */
9476         if (state->allow_modeset)
9477                 return true;
9478
9479         /* Exit early if we know that we're adding or removing the plane. */
9480         if (old_plane_state->crtc != new_plane_state->crtc)
9481                 return true;
9482
9483         /* old crtc == new_crtc == NULL, plane not in context. */
9484         if (!new_plane_state->crtc)
9485                 return false;
9486
9487         new_crtc_state =
9488                 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
9489
9490         if (!new_crtc_state)
9491                 return true;
9492
9493         /* CRTC Degamma changes currently require us to recreate planes. */
9494         if (new_crtc_state->color_mgmt_changed)
9495                 return true;
9496
9497         if (drm_atomic_crtc_needs_modeset(new_crtc_state))
9498                 return true;
9499
9500         /*
9501          * If there are any new primary or overlay planes being added or
9502          * removed then the z-order can potentially change. To ensure
9503          * correct z-order and pipe acquisition the current DC architecture
9504          * requires us to remove and recreate all existing planes.
9505          *
9506          * TODO: Come up with a more elegant solution for this.
9507          */
9508         for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
9509                 struct amdgpu_framebuffer *old_afb, *new_afb;
9510
9511                 if (other->type == DRM_PLANE_TYPE_CURSOR)
9512                         continue;
9513
9514                 if (old_other_state->crtc != new_plane_state->crtc &&
9515                     new_other_state->crtc != new_plane_state->crtc)
9516                         continue;
9517
9518                 if (old_other_state->crtc != new_other_state->crtc)
9519                         return true;
9520
9521                 /* Src/dst size and scaling updates. */
9522                 if (old_other_state->src_w != new_other_state->src_w ||
9523                     old_other_state->src_h != new_other_state->src_h ||
9524                     old_other_state->crtc_w != new_other_state->crtc_w ||
9525                     old_other_state->crtc_h != new_other_state->crtc_h)
9526                         return true;
9527
9528                 /* Rotation / mirroring updates. */
9529                 if (old_other_state->rotation != new_other_state->rotation)
9530                         return true;
9531
9532                 /* Blending updates. */
9533                 if (old_other_state->pixel_blend_mode !=
9534                     new_other_state->pixel_blend_mode)
9535                         return true;
9536
9537                 /* Alpha updates. */
9538                 if (old_other_state->alpha != new_other_state->alpha)
9539                         return true;
9540
9541                 /* Colorspace changes. */
9542                 if (old_other_state->color_range != new_other_state->color_range ||
9543                     old_other_state->color_encoding != new_other_state->color_encoding)
9544                         return true;
9545
9546                 /* Framebuffer checks fall at the end. */
9547                 if (!old_other_state->fb || !new_other_state->fb)
9548                         continue;
9549
9550                 /* Pixel format changes can require bandwidth updates. */
9551                 if (old_other_state->fb->format != new_other_state->fb->format)
9552                         return true;
9553
9554                 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb;
9555                 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb;
9556
9557                 /* Tiling and DCC changes also require bandwidth updates. */
9558                 if (old_afb->tiling_flags != new_afb->tiling_flags ||
9559                     old_afb->base.modifier != new_afb->base.modifier)
9560                         return true;
9561         }
9562
9563         return false;
9564 }
9565
9566 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,
9567                               struct drm_plane_state *new_plane_state,
9568                               struct drm_framebuffer *fb)
9569 {
9570         struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev);
9571         struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
9572         unsigned int pitch;
9573         bool linear;
9574
9575         if (fb->width > new_acrtc->max_cursor_width ||
9576             fb->height > new_acrtc->max_cursor_height) {
9577                 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n",
9578                                  new_plane_state->fb->width,
9579                                  new_plane_state->fb->height);
9580                 return -EINVAL;
9581         }
9582         if (new_plane_state->src_w != fb->width << 16 ||
9583             new_plane_state->src_h != fb->height << 16) {
9584                 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9585                 return -EINVAL;
9586         }
9587
9588         /* Pitch in pixels */
9589         pitch = fb->pitches[0] / fb->format->cpp[0];
9590
9591         if (fb->width != pitch) {
9592                 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d",
9593                                  fb->width, pitch);
9594                 return -EINVAL;
9595         }
9596
9597         switch (pitch) {
9598         case 64:
9599         case 128:
9600         case 256:
9601                 /* FB pitch is supported by cursor plane */
9602                 break;
9603         default:
9604                 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch);
9605                 return -EINVAL;
9606         }
9607
9608         /* Core DRM takes care of checking FB modifiers, so we only need to
9609          * check tiling flags when the FB doesn't have a modifier.
9610          */
9611         if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) {
9612                 if (adev->family < AMDGPU_FAMILY_AI) {
9613                         linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &&
9614                                  AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &&
9615                                  AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0;
9616                 } else {
9617                         linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;
9618                 }
9619                 if (!linear) {
9620                         DRM_DEBUG_ATOMIC("Cursor FB not linear");
9621                         return -EINVAL;
9622                 }
9623         }
9624
9625         return 0;
9626 }
9627
9628 static int dm_update_plane_state(struct dc *dc,
9629                                  struct drm_atomic_state *state,
9630                                  struct drm_plane *plane,
9631                                  struct drm_plane_state *old_plane_state,
9632                                  struct drm_plane_state *new_plane_state,
9633                                  bool enable,
9634                                  bool *lock_and_validation_needed,
9635                                  bool *is_top_most_overlay)
9636 {
9637
9638         struct dm_atomic_state *dm_state = NULL;
9639         struct drm_crtc *new_plane_crtc, *old_plane_crtc;
9640         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9641         struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
9642         struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
9643         struct amdgpu_crtc *new_acrtc;
9644         bool needs_reset;
9645         int ret = 0;
9646
9647
9648         new_plane_crtc = new_plane_state->crtc;
9649         old_plane_crtc = old_plane_state->crtc;
9650         dm_new_plane_state = to_dm_plane_state(new_plane_state);
9651         dm_old_plane_state = to_dm_plane_state(old_plane_state);
9652
9653         if (plane->type == DRM_PLANE_TYPE_CURSOR) {
9654                 if (!enable || !new_plane_crtc ||
9655                         drm_atomic_plane_disabling(plane->state, new_plane_state))
9656                         return 0;
9657
9658                 new_acrtc = to_amdgpu_crtc(new_plane_crtc);
9659
9660                 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) {
9661                         DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9662                         return -EINVAL;
9663                 }
9664
9665                 if (new_plane_state->fb) {
9666                         ret = dm_check_cursor_fb(new_acrtc, new_plane_state,
9667                                                  new_plane_state->fb);
9668                         if (ret)
9669                                 return ret;
9670                 }
9671
9672                 return 0;
9673         }
9674
9675         needs_reset = should_reset_plane(state, plane, old_plane_state,
9676                                          new_plane_state);
9677
9678         /* Remove any changed/removed planes */
9679         if (!enable) {
9680                 if (!needs_reset)
9681                         return 0;
9682
9683                 if (!old_plane_crtc)
9684                         return 0;
9685
9686                 old_crtc_state = drm_atomic_get_old_crtc_state(
9687                                 state, old_plane_crtc);
9688                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9689
9690                 if (!dm_old_crtc_state->stream)
9691                         return 0;
9692
9693                 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
9694                                 plane->base.id, old_plane_crtc->base.id);
9695
9696                 ret = dm_atomic_get_state(state, &dm_state);
9697                 if (ret)
9698                         return ret;
9699
9700                 if (!dc_remove_plane_from_context(
9701                                 dc,
9702                                 dm_old_crtc_state->stream,
9703                                 dm_old_plane_state->dc_state,
9704                                 dm_state->context)) {
9705
9706                         return -EINVAL;
9707                 }
9708
9709                 if (dm_old_plane_state->dc_state)
9710                         dc_plane_state_release(dm_old_plane_state->dc_state);
9711
9712                 dm_new_plane_state->dc_state = NULL;
9713
9714                 *lock_and_validation_needed = true;
9715
9716         } else { /* Add new planes */
9717                 struct dc_plane_state *dc_new_plane_state;
9718
9719                 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
9720                         return 0;
9721
9722                 if (!new_plane_crtc)
9723                         return 0;
9724
9725                 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
9726                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9727
9728                 if (!dm_new_crtc_state->stream)
9729                         return 0;
9730
9731                 if (!needs_reset)
9732                         return 0;
9733
9734                 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state);
9735                 if (ret)
9736                         return ret;
9737
9738                 WARN_ON(dm_new_plane_state->dc_state);
9739
9740                 dc_new_plane_state = dc_create_plane_state(dc);
9741                 if (!dc_new_plane_state)
9742                         return -ENOMEM;
9743
9744                 /* Block top most plane from being a video plane */
9745                 if (plane->type == DRM_PLANE_TYPE_OVERLAY) {
9746                         if (is_video_format(new_plane_state->fb->format->format) && *is_top_most_overlay)
9747                                 return -EINVAL;
9748
9749                         *is_top_most_overlay = false;
9750                 }
9751
9752                 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n",
9753                                  plane->base.id, new_plane_crtc->base.id);
9754
9755                 ret = fill_dc_plane_attributes(
9756                         drm_to_adev(new_plane_crtc->dev),
9757                         dc_new_plane_state,
9758                         new_plane_state,
9759                         new_crtc_state);
9760                 if (ret) {
9761                         dc_plane_state_release(dc_new_plane_state);
9762                         return ret;
9763                 }
9764
9765                 ret = dm_atomic_get_state(state, &dm_state);
9766                 if (ret) {
9767                         dc_plane_state_release(dc_new_plane_state);
9768                         return ret;
9769                 }
9770
9771                 /*
9772                  * Any atomic check errors that occur after this will
9773                  * not need a release. The plane state will be attached
9774                  * to the stream, and therefore part of the atomic
9775                  * state. It'll be released when the atomic state is
9776                  * cleaned.
9777                  */
9778                 if (!dc_add_plane_to_context(
9779                                 dc,
9780                                 dm_new_crtc_state->stream,
9781                                 dc_new_plane_state,
9782                                 dm_state->context)) {
9783
9784                         dc_plane_state_release(dc_new_plane_state);
9785                         return -EINVAL;
9786                 }
9787
9788                 dm_new_plane_state->dc_state = dc_new_plane_state;
9789
9790                 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY);
9791
9792                 /* Tell DC to do a full surface update every time there
9793                  * is a plane change. Inefficient, but works for now.
9794                  */
9795                 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
9796
9797                 *lock_and_validation_needed = true;
9798         }
9799
9800
9801         return ret;
9802 }
9803
9804 static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state,
9805                                        int *src_w, int *src_h)
9806 {
9807         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
9808         case DRM_MODE_ROTATE_90:
9809         case DRM_MODE_ROTATE_270:
9810                 *src_w = plane_state->src_h >> 16;
9811                 *src_h = plane_state->src_w >> 16;
9812                 break;
9813         case DRM_MODE_ROTATE_0:
9814         case DRM_MODE_ROTATE_180:
9815         default:
9816                 *src_w = plane_state->src_w >> 16;
9817                 *src_h = plane_state->src_h >> 16;
9818                 break;
9819         }
9820 }
9821
9822 static int dm_check_crtc_cursor(struct drm_atomic_state *state,
9823                                 struct drm_crtc *crtc,
9824                                 struct drm_crtc_state *new_crtc_state)
9825 {
9826         struct drm_plane *cursor = crtc->cursor, *underlying;
9827         struct drm_plane_state *new_cursor_state, *new_underlying_state;
9828         int i;
9829         int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h;
9830         int cursor_src_w, cursor_src_h;
9831         int underlying_src_w, underlying_src_h;
9832
9833         /* On DCE and DCN there is no dedicated hardware cursor plane. We get a
9834          * cursor per pipe but it's going to inherit the scaling and
9835          * positioning from the underlying pipe. Check the cursor plane's
9836          * blending properties match the underlying planes'.
9837          */
9838
9839         new_cursor_state = drm_atomic_get_new_plane_state(state, cursor);
9840         if (!new_cursor_state || !new_cursor_state->fb)
9841                 return 0;
9842
9843         dm_get_oriented_plane_size(new_cursor_state, &cursor_src_w, &cursor_src_h);
9844         cursor_scale_w = new_cursor_state->crtc_w * 1000 / cursor_src_w;
9845         cursor_scale_h = new_cursor_state->crtc_h * 1000 / cursor_src_h;
9846
9847         for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) {
9848                 /* Narrow down to non-cursor planes on the same CRTC as the cursor */
9849                 if (new_underlying_state->crtc != crtc || underlying == crtc->cursor)
9850                         continue;
9851
9852                 /* Ignore disabled planes */
9853                 if (!new_underlying_state->fb)
9854                         continue;
9855
9856                 dm_get_oriented_plane_size(new_underlying_state,
9857                                            &underlying_src_w, &underlying_src_h);
9858                 underlying_scale_w = new_underlying_state->crtc_w * 1000 / underlying_src_w;
9859                 underlying_scale_h = new_underlying_state->crtc_h * 1000 / underlying_src_h;
9860
9861                 if (cursor_scale_w != underlying_scale_w ||
9862                     cursor_scale_h != underlying_scale_h) {
9863                         drm_dbg_atomic(crtc->dev,
9864                                        "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n",
9865                                        cursor->base.id, cursor->name, underlying->base.id, underlying->name);
9866                         return -EINVAL;
9867                 }
9868
9869                 /* If this plane covers the whole CRTC, no need to check planes underneath */
9870                 if (new_underlying_state->crtc_x <= 0 &&
9871                     new_underlying_state->crtc_y <= 0 &&
9872                     new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay &&
9873                     new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay)
9874                         break;
9875         }
9876
9877         return 0;
9878 }
9879
9880 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
9881 {
9882         struct drm_connector *connector;
9883         struct drm_connector_state *conn_state, *old_conn_state;
9884         struct amdgpu_dm_connector *aconnector = NULL;
9885         int i;
9886
9887         for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) {
9888                 if (!conn_state->crtc)
9889                         conn_state = old_conn_state;
9890
9891                 if (conn_state->crtc != crtc)
9892                         continue;
9893
9894                 aconnector = to_amdgpu_dm_connector(connector);
9895                 if (!aconnector->mst_output_port || !aconnector->mst_root)
9896                         aconnector = NULL;
9897                 else
9898                         break;
9899         }
9900
9901         if (!aconnector)
9902                 return 0;
9903
9904         return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr);
9905 }
9906
9907 /**
9908  * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
9909  *
9910  * @dev: The DRM device
9911  * @state: The atomic state to commit
9912  *
9913  * Validate that the given atomic state is programmable by DC into hardware.
9914  * This involves constructing a &struct dc_state reflecting the new hardware
9915  * state we wish to commit, then querying DC to see if it is programmable. It's
9916  * important not to modify the existing DC state. Otherwise, atomic_check
9917  * may unexpectedly commit hardware changes.
9918  *
9919  * When validating the DC state, it's important that the right locks are
9920  * acquired. For full updates case which removes/adds/updates streams on one
9921  * CRTC while flipping on another CRTC, acquiring global lock will guarantee
9922  * that any such full update commit will wait for completion of any outstanding
9923  * flip using DRMs synchronization events.
9924  *
9925  * Note that DM adds the affected connectors for all CRTCs in state, when that
9926  * might not seem necessary. This is because DC stream creation requires the
9927  * DC sink, which is tied to the DRM connector state. Cleaning this up should
9928  * be possible but non-trivial - a possible TODO item.
9929  *
9930  * Return: -Error code if validation failed.
9931  */
9932 static int amdgpu_dm_atomic_check(struct drm_device *dev,
9933                                   struct drm_atomic_state *state)
9934 {
9935         struct amdgpu_device *adev = drm_to_adev(dev);
9936         struct dm_atomic_state *dm_state = NULL;
9937         struct dc *dc = adev->dm.dc;
9938         struct drm_connector *connector;
9939         struct drm_connector_state *old_con_state, *new_con_state;
9940         struct drm_crtc *crtc;
9941         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9942         struct drm_plane *plane;
9943         struct drm_plane_state *old_plane_state, *new_plane_state;
9944         enum dc_status status;
9945         int ret, i;
9946         bool lock_and_validation_needed = false;
9947         bool is_top_most_overlay = true;
9948         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9949         struct drm_dp_mst_topology_mgr *mgr;
9950         struct drm_dp_mst_topology_state *mst_state;
9951         struct dsc_mst_fairness_vars vars[MAX_PIPES];
9952
9953         trace_amdgpu_dm_atomic_check_begin(state);
9954
9955         ret = drm_atomic_helper_check_modeset(dev, state);
9956         if (ret) {
9957                 DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n");
9958                 goto fail;
9959         }
9960
9961         /* Check connector changes */
9962         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9963                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
9964                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9965
9966                 /* Skip connectors that are disabled or part of modeset already. */
9967                 if (!new_con_state->crtc)
9968                         continue;
9969
9970                 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc);
9971                 if (IS_ERR(new_crtc_state)) {
9972                         DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n");
9973                         ret = PTR_ERR(new_crtc_state);
9974                         goto fail;
9975                 }
9976
9977                 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level ||
9978                     dm_old_con_state->scaling != dm_new_con_state->scaling)
9979                         new_crtc_state->connectors_changed = true;
9980         }
9981
9982         if (dc_resource_is_dsc_encoding_supported(dc)) {
9983                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9984                         if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9985                                 ret = add_affected_mst_dsc_crtcs(state, crtc);
9986                                 if (ret) {
9987                                         DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n");
9988                                         goto fail;
9989                                 }
9990                         }
9991                 }
9992         }
9993         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9994                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9995
9996                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
9997                     !new_crtc_state->color_mgmt_changed &&
9998                     old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled &&
9999                         dm_old_crtc_state->dsc_force_changed == false)
10000                         continue;
10001
10002                 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state);
10003                 if (ret) {
10004                         DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n");
10005                         goto fail;
10006                 }
10007
10008                 if (!new_crtc_state->enable)
10009                         continue;
10010
10011                 ret = drm_atomic_add_affected_connectors(state, crtc);
10012                 if (ret) {
10013                         DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n");
10014                         goto fail;
10015                 }
10016
10017                 ret = drm_atomic_add_affected_planes(state, crtc);
10018                 if (ret) {
10019                         DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n");
10020                         goto fail;
10021                 }
10022
10023                 if (dm_old_crtc_state->dsc_force_changed)
10024                         new_crtc_state->mode_changed = true;
10025         }
10026
10027         /*
10028          * Add all primary and overlay planes on the CRTC to the state
10029          * whenever a plane is enabled to maintain correct z-ordering
10030          * and to enable fast surface updates.
10031          */
10032         drm_for_each_crtc(crtc, dev) {
10033                 bool modified = false;
10034
10035                 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
10036                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
10037                                 continue;
10038
10039                         if (new_plane_state->crtc == crtc ||
10040                             old_plane_state->crtc == crtc) {
10041                                 modified = true;
10042                                 break;
10043                         }
10044                 }
10045
10046                 if (!modified)
10047                         continue;
10048
10049                 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
10050                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
10051                                 continue;
10052
10053                         new_plane_state =
10054                                 drm_atomic_get_plane_state(state, plane);
10055
10056                         if (IS_ERR(new_plane_state)) {
10057                                 ret = PTR_ERR(new_plane_state);
10058                                 DRM_DEBUG_DRIVER("new_plane_state is BAD\n");
10059                                 goto fail;
10060                         }
10061                 }
10062         }
10063
10064         /*
10065          * DC consults the zpos (layer_index in DC terminology) to determine the
10066          * hw plane on which to enable the hw cursor (see
10067          * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in
10068          * atomic state, so call drm helper to normalize zpos.
10069          */
10070         ret = drm_atomic_normalize_zpos(dev, state);
10071         if (ret) {
10072                 drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n");
10073                 goto fail;
10074         }
10075
10076         /* Remove exiting planes if they are modified */
10077         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10078                 if (old_plane_state->fb && new_plane_state->fb &&
10079                     get_mem_type(old_plane_state->fb) !=
10080                     get_mem_type(new_plane_state->fb))
10081                         lock_and_validation_needed = true;
10082
10083                 ret = dm_update_plane_state(dc, state, plane,
10084                                             old_plane_state,
10085                                             new_plane_state,
10086                                             false,
10087                                             &lock_and_validation_needed,
10088                                             &is_top_most_overlay);
10089                 if (ret) {
10090                         DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10091                         goto fail;
10092                 }
10093         }
10094
10095         /* Disable all crtcs which require disable */
10096         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10097                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10098                                            old_crtc_state,
10099                                            new_crtc_state,
10100                                            false,
10101                                            &lock_and_validation_needed);
10102                 if (ret) {
10103                         DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n");
10104                         goto fail;
10105                 }
10106         }
10107
10108         /* Enable all crtcs which require enable */
10109         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10110                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10111                                            old_crtc_state,
10112                                            new_crtc_state,
10113                                            true,
10114                                            &lock_and_validation_needed);
10115                 if (ret) {
10116                         DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n");
10117                         goto fail;
10118                 }
10119         }
10120
10121         /* Add new/modified planes */
10122         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10123                 ret = dm_update_plane_state(dc, state, plane,
10124                                             old_plane_state,
10125                                             new_plane_state,
10126                                             true,
10127                                             &lock_and_validation_needed,
10128                                             &is_top_most_overlay);
10129                 if (ret) {
10130                         DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10131                         goto fail;
10132                 }
10133         }
10134
10135         if (dc_resource_is_dsc_encoding_supported(dc)) {
10136                 ret = pre_validate_dsc(state, &dm_state, vars);
10137                 if (ret != 0)
10138                         goto fail;
10139         }
10140
10141         /* Run this here since we want to validate the streams we created */
10142         ret = drm_atomic_helper_check_planes(dev, state);
10143         if (ret) {
10144                 DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n");
10145                 goto fail;
10146         }
10147
10148         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10149                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
10150                 if (dm_new_crtc_state->mpo_requested)
10151                         DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc);
10152         }
10153
10154         /* Check cursor planes scaling */
10155         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10156                 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state);
10157                 if (ret) {
10158                         DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n");
10159                         goto fail;
10160                 }
10161         }
10162
10163         if (state->legacy_cursor_update) {
10164                 /*
10165                  * This is a fast cursor update coming from the plane update
10166                  * helper, check if it can be done asynchronously for better
10167                  * performance.
10168                  */
10169                 state->async_update =
10170                         !drm_atomic_helper_async_check(dev, state);
10171
10172                 /*
10173                  * Skip the remaining global validation if this is an async
10174                  * update. Cursor updates can be done without affecting
10175                  * state or bandwidth calcs and this avoids the performance
10176                  * penalty of locking the private state object and
10177                  * allocating a new dc_state.
10178                  */
10179                 if (state->async_update)
10180                         return 0;
10181         }
10182
10183         /* Check scaling and underscan changes*/
10184         /* TODO Removed scaling changes validation due to inability to commit
10185          * new stream into context w\o causing full reset. Need to
10186          * decide how to handle.
10187          */
10188         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
10189                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
10190                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10191                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
10192
10193                 /* Skip any modesets/resets */
10194                 if (!acrtc || drm_atomic_crtc_needs_modeset(
10195                                 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
10196                         continue;
10197
10198                 /* Skip any thing not scale or underscan changes */
10199                 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
10200                         continue;
10201
10202                 lock_and_validation_needed = true;
10203         }
10204
10205         /* set the slot info for each mst_state based on the link encoding format */
10206         for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
10207                 struct amdgpu_dm_connector *aconnector;
10208                 struct drm_connector *connector;
10209                 struct drm_connector_list_iter iter;
10210                 u8 link_coding_cap;
10211
10212                 drm_connector_list_iter_begin(dev, &iter);
10213                 drm_for_each_connector_iter(connector, &iter) {
10214                         if (connector->index == mst_state->mgr->conn_base_id) {
10215                                 aconnector = to_amdgpu_dm_connector(connector);
10216                                 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link);
10217                                 drm_dp_mst_update_slots(mst_state, link_coding_cap);
10218
10219                                 break;
10220                         }
10221                 }
10222                 drm_connector_list_iter_end(&iter);
10223         }
10224
10225         /**
10226          * Streams and planes are reset when there are changes that affect
10227          * bandwidth. Anything that affects bandwidth needs to go through
10228          * DC global validation to ensure that the configuration can be applied
10229          * to hardware.
10230          *
10231          * We have to currently stall out here in atomic_check for outstanding
10232          * commits to finish in this case because our IRQ handlers reference
10233          * DRM state directly - we can end up disabling interrupts too early
10234          * if we don't.
10235          *
10236          * TODO: Remove this stall and drop DM state private objects.
10237          */
10238         if (lock_and_validation_needed) {
10239                 ret = dm_atomic_get_state(state, &dm_state);
10240                 if (ret) {
10241                         DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n");
10242                         goto fail;
10243                 }
10244
10245                 ret = do_aquire_global_lock(dev, state);
10246                 if (ret) {
10247                         DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n");
10248                         goto fail;
10249                 }
10250
10251                 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars);
10252                 if (ret) {
10253                         DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n");
10254                         ret = -EINVAL;
10255                         goto fail;
10256                 }
10257
10258                 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars);
10259                 if (ret) {
10260                         DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n");
10261                         goto fail;
10262                 }
10263
10264                 /*
10265                  * Perform validation of MST topology in the state:
10266                  * We need to perform MST atomic check before calling
10267                  * dc_validate_global_state(), or there is a chance
10268                  * to get stuck in an infinite loop and hang eventually.
10269                  */
10270                 ret = drm_dp_mst_atomic_check(state);
10271                 if (ret) {
10272                         DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n");
10273                         goto fail;
10274                 }
10275                 status = dc_validate_global_state(dc, dm_state->context, true);
10276                 if (status != DC_OK) {
10277                         DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)",
10278                                        dc_status_to_str(status), status);
10279                         ret = -EINVAL;
10280                         goto fail;
10281                 }
10282         } else {
10283                 /*
10284                  * The commit is a fast update. Fast updates shouldn't change
10285                  * the DC context, affect global validation, and can have their
10286                  * commit work done in parallel with other commits not touching
10287                  * the same resource. If we have a new DC context as part of
10288                  * the DM atomic state from validation we need to free it and
10289                  * retain the existing one instead.
10290                  *
10291                  * Furthermore, since the DM atomic state only contains the DC
10292                  * context and can safely be annulled, we can free the state
10293                  * and clear the associated private object now to free
10294                  * some memory and avoid a possible use-after-free later.
10295                  */
10296
10297                 for (i = 0; i < state->num_private_objs; i++) {
10298                         struct drm_private_obj *obj = state->private_objs[i].ptr;
10299
10300                         if (obj->funcs == adev->dm.atomic_obj.funcs) {
10301                                 int j = state->num_private_objs-1;
10302
10303                                 dm_atomic_destroy_state(obj,
10304                                                 state->private_objs[i].state);
10305
10306                                 /* If i is not at the end of the array then the
10307                                  * last element needs to be moved to where i was
10308                                  * before the array can safely be truncated.
10309                                  */
10310                                 if (i != j)
10311                                         state->private_objs[i] =
10312                                                 state->private_objs[j];
10313
10314                                 state->private_objs[j].ptr = NULL;
10315                                 state->private_objs[j].state = NULL;
10316                                 state->private_objs[j].old_state = NULL;
10317                                 state->private_objs[j].new_state = NULL;
10318
10319                                 state->num_private_objs = j;
10320                                 break;
10321                         }
10322                 }
10323         }
10324
10325         /* Store the overall update type for use later in atomic check. */
10326         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10327                 struct dm_crtc_state *dm_new_crtc_state =
10328                         to_dm_crtc_state(new_crtc_state);
10329
10330                 /*
10331                  * Only allow async flips for fast updates that don't change
10332                  * the FB pitch, the DCC state, rotation, etc.
10333                  */
10334                 if (new_crtc_state->async_flip && lock_and_validation_needed) {
10335                         drm_dbg_atomic(crtc->dev,
10336                                        "[CRTC:%d:%s] async flips are only supported for fast updates\n",
10337                                        crtc->base.id, crtc->name);
10338                         ret = -EINVAL;
10339                         goto fail;
10340                 }
10341
10342                 dm_new_crtc_state->update_type = lock_and_validation_needed ?
10343                         UPDATE_TYPE_FULL : UPDATE_TYPE_FAST;
10344         }
10345
10346         /* Must be success */
10347         WARN_ON(ret);
10348
10349         trace_amdgpu_dm_atomic_check_finish(state, ret);
10350
10351         return ret;
10352
10353 fail:
10354         if (ret == -EDEADLK)
10355                 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
10356         else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
10357                 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
10358         else
10359                 DRM_DEBUG_DRIVER("Atomic check failed with err: %d\n", ret);
10360
10361         trace_amdgpu_dm_atomic_check_finish(state, ret);
10362
10363         return ret;
10364 }
10365
10366 static bool is_dp_capable_without_timing_msa(struct dc *dc,
10367                                              struct amdgpu_dm_connector *amdgpu_dm_connector)
10368 {
10369         u8 dpcd_data;
10370         bool capable = false;
10371
10372         if (amdgpu_dm_connector->dc_link &&
10373                 dm_helpers_dp_read_dpcd(
10374                                 NULL,
10375                                 amdgpu_dm_connector->dc_link,
10376                                 DP_DOWN_STREAM_PORT_COUNT,
10377                                 &dpcd_data,
10378                                 sizeof(dpcd_data))) {
10379                 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
10380         }
10381
10382         return capable;
10383 }
10384
10385 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,
10386                 unsigned int offset,
10387                 unsigned int total_length,
10388                 u8 *data,
10389                 unsigned int length,
10390                 struct amdgpu_hdmi_vsdb_info *vsdb)
10391 {
10392         bool res;
10393         union dmub_rb_cmd cmd;
10394         struct dmub_cmd_send_edid_cea *input;
10395         struct dmub_cmd_edid_cea_output *output;
10396
10397         if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES)
10398                 return false;
10399
10400         memset(&cmd, 0, sizeof(cmd));
10401
10402         input = &cmd.edid_cea.data.input;
10403
10404         cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA;
10405         cmd.edid_cea.header.sub_type = 0;
10406         cmd.edid_cea.header.payload_bytes =
10407                 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header);
10408         input->offset = offset;
10409         input->length = length;
10410         input->cea_total_length = total_length;
10411         memcpy(input->payload, data, length);
10412
10413         res = dm_execute_dmub_cmd(dm->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY);
10414         if (!res) {
10415                 DRM_ERROR("EDID CEA parser failed\n");
10416                 return false;
10417         }
10418
10419         output = &cmd.edid_cea.data.output;
10420
10421         if (output->type == DMUB_CMD__EDID_CEA_ACK) {
10422                 if (!output->ack.success) {
10423                         DRM_ERROR("EDID CEA ack failed at offset %d\n",
10424                                         output->ack.offset);
10425                 }
10426         } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) {
10427                 if (!output->amd_vsdb.vsdb_found)
10428                         return false;
10429
10430                 vsdb->freesync_supported = output->amd_vsdb.freesync_supported;
10431                 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version;
10432                 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate;
10433                 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate;
10434         } else {
10435                 DRM_WARN("Unknown EDID CEA parser results\n");
10436                 return false;
10437         }
10438
10439         return true;
10440 }
10441
10442 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm,
10443                 u8 *edid_ext, int len,
10444                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10445 {
10446         int i;
10447
10448         /* send extension block to DMCU for parsing */
10449         for (i = 0; i < len; i += 8) {
10450                 bool res;
10451                 int offset;
10452
10453                 /* send 8 bytes a time */
10454                 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8))
10455                         return false;
10456
10457                 if (i+8 == len) {
10458                         /* EDID block sent completed, expect result */
10459                         int version, min_rate, max_rate;
10460
10461                         res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate);
10462                         if (res) {
10463                                 /* amd vsdb found */
10464                                 vsdb_info->freesync_supported = 1;
10465                                 vsdb_info->amd_vsdb_version = version;
10466                                 vsdb_info->min_refresh_rate_hz = min_rate;
10467                                 vsdb_info->max_refresh_rate_hz = max_rate;
10468                                 return true;
10469                         }
10470                         /* not amd vsdb */
10471                         return false;
10472                 }
10473
10474                 /* check for ack*/
10475                 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset);
10476                 if (!res)
10477                         return false;
10478         }
10479
10480         return false;
10481 }
10482
10483 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm,
10484                 u8 *edid_ext, int len,
10485                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10486 {
10487         int i;
10488
10489         /* send extension block to DMCU for parsing */
10490         for (i = 0; i < len; i += 8) {
10491                 /* send 8 bytes a time */
10492                 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info))
10493                         return false;
10494         }
10495
10496         return vsdb_info->freesync_supported;
10497 }
10498
10499 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
10500                 u8 *edid_ext, int len,
10501                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10502 {
10503         struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
10504         bool ret;
10505
10506         mutex_lock(&adev->dm.dc_lock);
10507         if (adev->dm.dmub_srv)
10508                 ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info);
10509         else
10510                 ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info);
10511         mutex_unlock(&adev->dm.dc_lock);
10512         return ret;
10513 }
10514
10515 static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector,
10516                           struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
10517 {
10518         u8 *edid_ext = NULL;
10519         int i;
10520         int j = 0;
10521
10522         if (edid == NULL || edid->extensions == 0)
10523                 return -ENODEV;
10524
10525         /* Find DisplayID extension */
10526         for (i = 0; i < edid->extensions; i++) {
10527                 edid_ext = (void *)(edid + (i + 1));
10528                 if (edid_ext[0] == DISPLAYID_EXT)
10529                         break;
10530         }
10531
10532         while (j < EDID_LENGTH) {
10533                 struct amd_vsdb_block *amd_vsdb = (struct amd_vsdb_block *)&edid_ext[j];
10534                 unsigned int ieeeId = (amd_vsdb->ieee_id[2] << 16) | (amd_vsdb->ieee_id[1] << 8) | (amd_vsdb->ieee_id[0]);
10535
10536                 if (ieeeId == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID &&
10537                                 amd_vsdb->version == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3) {
10538                         vsdb_info->replay_mode = (amd_vsdb->feature_caps & AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE) ? true : false;
10539                         vsdb_info->amd_vsdb_version = HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3;
10540                         DRM_DEBUG_KMS("Panel supports Replay Mode: %d\n", vsdb_info->replay_mode);
10541
10542                         return true;
10543                 }
10544                 j++;
10545         }
10546
10547         return false;
10548 }
10549
10550 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
10551                 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
10552 {
10553         u8 *edid_ext = NULL;
10554         int i;
10555         bool valid_vsdb_found = false;
10556
10557         /*----- drm_find_cea_extension() -----*/
10558         /* No EDID or EDID extensions */
10559         if (edid == NULL || edid->extensions == 0)
10560                 return -ENODEV;
10561
10562         /* Find CEA extension */
10563         for (i = 0; i < edid->extensions; i++) {
10564                 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1);
10565                 if (edid_ext[0] == CEA_EXT)
10566                         break;
10567         }
10568
10569         if (i == edid->extensions)
10570                 return -ENODEV;
10571
10572         /*----- cea_db_offsets() -----*/
10573         if (edid_ext[0] != CEA_EXT)
10574                 return -ENODEV;
10575
10576         valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info);
10577
10578         return valid_vsdb_found ? i : -ENODEV;
10579 }
10580
10581 /**
10582  * amdgpu_dm_update_freesync_caps - Update Freesync capabilities
10583  *
10584  * @connector: Connector to query.
10585  * @edid: EDID from monitor
10586  *
10587  * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep
10588  * track of some of the display information in the internal data struct used by
10589  * amdgpu_dm. This function checks which type of connector we need to set the
10590  * FreeSync parameters.
10591  */
10592 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
10593                                     struct edid *edid)
10594 {
10595         int i = 0;
10596         struct detailed_timing *timing;
10597         struct detailed_non_pixel *data;
10598         struct detailed_data_monitor_range *range;
10599         struct amdgpu_dm_connector *amdgpu_dm_connector =
10600                         to_amdgpu_dm_connector(connector);
10601         struct dm_connector_state *dm_con_state = NULL;
10602         struct dc_sink *sink;
10603
10604         struct drm_device *dev = connector->dev;
10605         struct amdgpu_device *adev = drm_to_adev(dev);
10606         struct amdgpu_hdmi_vsdb_info vsdb_info = {0};
10607         bool freesync_capable = false;
10608         enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE;
10609
10610         if (!connector->state) {
10611                 DRM_ERROR("%s - Connector has no state", __func__);
10612                 goto update;
10613         }
10614
10615         sink = amdgpu_dm_connector->dc_sink ?
10616                 amdgpu_dm_connector->dc_sink :
10617                 amdgpu_dm_connector->dc_em_sink;
10618
10619         if (!edid || !sink) {
10620                 dm_con_state = to_dm_connector_state(connector->state);
10621
10622                 amdgpu_dm_connector->min_vfreq = 0;
10623                 amdgpu_dm_connector->max_vfreq = 0;
10624                 amdgpu_dm_connector->pixel_clock_mhz = 0;
10625                 connector->display_info.monitor_range.min_vfreq = 0;
10626                 connector->display_info.monitor_range.max_vfreq = 0;
10627                 freesync_capable = false;
10628
10629                 goto update;
10630         }
10631
10632         dm_con_state = to_dm_connector_state(connector->state);
10633
10634         if (!adev->dm.freesync_module)
10635                 goto update;
10636
10637         if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
10638                 || sink->sink_signal == SIGNAL_TYPE_EDP) {
10639                 bool edid_check_required = false;
10640
10641                 if (edid) {
10642                         edid_check_required = is_dp_capable_without_timing_msa(
10643                                                 adev->dm.dc,
10644                                                 amdgpu_dm_connector);
10645                 }
10646
10647                 if (edid_check_required == true && (edid->version > 1 ||
10648                    (edid->version == 1 && edid->revision > 1))) {
10649                         for (i = 0; i < 4; i++) {
10650
10651                                 timing  = &edid->detailed_timings[i];
10652                                 data    = &timing->data.other_data;
10653                                 range   = &data->data.range;
10654                                 /*
10655                                  * Check if monitor has continuous frequency mode
10656                                  */
10657                                 if (data->type != EDID_DETAIL_MONITOR_RANGE)
10658                                         continue;
10659                                 /*
10660                                  * Check for flag range limits only. If flag == 1 then
10661                                  * no additional timing information provided.
10662                                  * Default GTF, GTF Secondary curve and CVT are not
10663                                  * supported
10664                                  */
10665                                 if (range->flags != 1)
10666                                         continue;
10667
10668                                 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
10669                                 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
10670                                 amdgpu_dm_connector->pixel_clock_mhz =
10671                                         range->pixel_clock_mhz * 10;
10672
10673                                 connector->display_info.monitor_range.min_vfreq = range->min_vfreq;
10674                                 connector->display_info.monitor_range.max_vfreq = range->max_vfreq;
10675
10676                                 break;
10677                         }
10678
10679                         if (amdgpu_dm_connector->max_vfreq -
10680                             amdgpu_dm_connector->min_vfreq > 10) {
10681
10682                                 freesync_capable = true;
10683                         }
10684                 }
10685                 parse_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10686
10687                 if (vsdb_info.replay_mode) {
10688                         amdgpu_dm_connector->vsdb_info.replay_mode = vsdb_info.replay_mode;
10689                         amdgpu_dm_connector->vsdb_info.amd_vsdb_version = vsdb_info.amd_vsdb_version;
10690                         amdgpu_dm_connector->as_type = ADAPTIVE_SYNC_TYPE_EDP;
10691                 }
10692
10693         } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
10694                 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10695                 if (i >= 0 && vsdb_info.freesync_supported) {
10696                         timing  = &edid->detailed_timings[i];
10697                         data    = &timing->data.other_data;
10698
10699                         amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10700                         amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10701                         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10702                                 freesync_capable = true;
10703
10704                         connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10705                         connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10706                 }
10707         }
10708
10709         as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link);
10710
10711         if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {
10712                 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10713                 if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) {
10714
10715                         amdgpu_dm_connector->pack_sdp_v1_3 = true;
10716                         amdgpu_dm_connector->as_type = as_type;
10717                         amdgpu_dm_connector->vsdb_info = vsdb_info;
10718
10719                         amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10720                         amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10721                         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10722                                 freesync_capable = true;
10723
10724                         connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10725                         connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10726                 }
10727         }
10728
10729 update:
10730         if (dm_con_state)
10731                 dm_con_state->freesync_capable = freesync_capable;
10732
10733         if (connector->vrr_capable_property)
10734                 drm_connector_set_vrr_capable_property(connector,
10735                                                        freesync_capable);
10736 }
10737
10738 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
10739 {
10740         struct amdgpu_device *adev = drm_to_adev(dev);
10741         struct dc *dc = adev->dm.dc;
10742         int i;
10743
10744         mutex_lock(&adev->dm.dc_lock);
10745         if (dc->current_state) {
10746                 for (i = 0; i < dc->current_state->stream_count; ++i)
10747                         dc->current_state->streams[i]
10748                                 ->triggered_crtc_reset.enabled =
10749                                 adev->dm.force_timing_sync;
10750
10751                 dm_enable_per_frame_crtc_master_sync(dc->current_state);
10752                 dc_trigger_sync(dc, dc->current_state);
10753         }
10754         mutex_unlock(&adev->dm.dc_lock);
10755 }
10756
10757 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
10758                        u32 value, const char *func_name)
10759 {
10760 #ifdef DM_CHECK_ADDR_0
10761         if (address == 0) {
10762                 DC_ERR("invalid register write. address = 0");
10763                 return;
10764         }
10765 #endif
10766         cgs_write_register(ctx->cgs_device, address, value);
10767         trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
10768 }
10769
10770 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
10771                           const char *func_name)
10772 {
10773         u32 value;
10774 #ifdef DM_CHECK_ADDR_0
10775         if (address == 0) {
10776                 DC_ERR("invalid register read; address = 0\n");
10777                 return 0;
10778         }
10779 #endif
10780
10781         if (ctx->dmub_srv &&
10782             ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
10783             !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
10784                 ASSERT(false);
10785                 return 0;
10786         }
10787
10788         value = cgs_read_register(ctx->cgs_device, address);
10789
10790         trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
10791
10792         return value;
10793 }
10794
10795 int amdgpu_dm_process_dmub_aux_transfer_sync(
10796                 struct dc_context *ctx,
10797                 unsigned int link_index,
10798                 struct aux_payload *payload,
10799                 enum aux_return_code_type *operation_result)
10800 {
10801         struct amdgpu_device *adev = ctx->driver_context;
10802         struct dmub_notification *p_notify = adev->dm.dmub_notify;
10803         int ret = -1;
10804
10805         mutex_lock(&adev->dm.dpia_aux_lock);
10806         if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) {
10807                 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE;
10808                 goto out;
10809         }
10810
10811         if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10812                 DRM_ERROR("wait_for_completion_timeout timeout!");
10813                 *operation_result = AUX_RET_ERROR_TIMEOUT;
10814                 goto out;
10815         }
10816
10817         if (p_notify->result != AUX_RET_SUCCESS) {
10818                 /*
10819                  * Transient states before tunneling is enabled could
10820                  * lead to this error. We can ignore this for now.
10821                  */
10822                 if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) {
10823                         DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n",
10824                                         payload->address, payload->length,
10825                                         p_notify->result);
10826                 }
10827                 *operation_result = AUX_RET_ERROR_INVALID_REPLY;
10828                 goto out;
10829         }
10830
10831
10832         payload->reply[0] = adev->dm.dmub_notify->aux_reply.command;
10833         if (!payload->write && p_notify->aux_reply.length &&
10834                         (payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) {
10835
10836                 if (payload->length != p_notify->aux_reply.length) {
10837                         DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n",
10838                                 p_notify->aux_reply.length,
10839                                         payload->address, payload->length);
10840                         *operation_result = AUX_RET_ERROR_INVALID_REPLY;
10841                         goto out;
10842                 }
10843
10844                 memcpy(payload->data, p_notify->aux_reply.data,
10845                                 p_notify->aux_reply.length);
10846         }
10847
10848         /* success */
10849         ret = p_notify->aux_reply.length;
10850         *operation_result = p_notify->result;
10851 out:
10852         reinit_completion(&adev->dm.dmub_aux_transfer_done);
10853         mutex_unlock(&adev->dm.dpia_aux_lock);
10854         return ret;
10855 }
10856
10857 int amdgpu_dm_process_dmub_set_config_sync(
10858                 struct dc_context *ctx,
10859                 unsigned int link_index,
10860                 struct set_config_cmd_payload *payload,
10861                 enum set_config_status *operation_result)
10862 {
10863         struct amdgpu_device *adev = ctx->driver_context;
10864         bool is_cmd_complete;
10865         int ret;
10866
10867         mutex_lock(&adev->dm.dpia_aux_lock);
10868         is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc,
10869                         link_index, payload, adev->dm.dmub_notify);
10870
10871         if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10872                 ret = 0;
10873                 *operation_result = adev->dm.dmub_notify->sc_status;
10874         } else {
10875                 DRM_ERROR("wait_for_completion_timeout timeout!");
10876                 ret = -1;
10877                 *operation_result = SET_CONFIG_UNKNOWN_ERROR;
10878         }
10879
10880         if (!is_cmd_complete)
10881                 reinit_completion(&adev->dm.dmub_aux_transfer_done);
10882         mutex_unlock(&adev->dm.dpia_aux_lock);
10883         return ret;
10884 }
10885
10886 /*
10887  * Check whether seamless boot is supported.
10888  *
10889  * So far we only support seamless boot on CHIP_VANGOGH.
10890  * If everything goes well, we may consider expanding
10891  * seamless boot to other ASICs.
10892  */
10893 bool check_seamless_boot_capability(struct amdgpu_device *adev)
10894 {
10895         switch (adev->ip_versions[DCE_HWIP][0]) {
10896         case IP_VERSION(3, 0, 1):
10897                 if (!adev->mman.keep_stolen_vga_memory)
10898                         return true;
10899                 break;
10900         default:
10901                 break;
10902         }
10903
10904         return false;
10905 }
10906
10907 bool dm_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
10908 {
10909         return dc_dmub_srv_cmd_run(ctx->dmub_srv, cmd, wait_type);
10910 }
10911
10912 bool dm_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
10913 {
10914         return dc_dmub_srv_cmd_run_list(ctx->dmub_srv, count, cmd, wait_type);
10915 }