drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 /* The caprices of the preprocessor require that this be declared right here */
  27 #define CREATE_TRACE_POINTS
  28
  29 #include "dm_services_types.h"
  30 #include "dc.h"
  31 #include "link_enc_cfg.h"
  32 #include "dc/inc/core_types.h"
  33 #include "dal_asic_id.h"
  34 #include "dmub/dmub_srv.h"
  35 #include "dc/inc/hw/dmcu.h"
  36 #include "dc/inc/hw/abm.h"
  37 #include "dc/dc_dmub_srv.h"
  38 #include "dc/dc_edid_parser.h"
  39 #include "dc/dc_stat.h"
  40 #include "amdgpu_dm_trace.h"
  41 #include "dpcd_defs.h"
  42 #include "link/protocols/link_dpcd.h"
  43 #include "link_service_types.h"
  44 #include "link/protocols/link_dp_capability.h"
  45 #include "link/protocols/link_ddc.h"
  46
  47 #include "vid.h"
  48 #include "amdgpu.h"
  49 #include "amdgpu_display.h"
  50 #include "amdgpu_ucode.h"
  51 #include "atom.h"
  52 #include "amdgpu_dm.h"
  53 #include "amdgpu_dm_plane.h"
  54 #include "amdgpu_dm_crtc.h"
  55 #include "amdgpu_dm_hdcp.h"
  56 #include <drm/display/drm_hdcp_helper.h>
  57 #include "amdgpu_pm.h"
  58 #include "amdgpu_atombios.h"
  59
  60 #include "amd_shared.h"
  61 #include "amdgpu_dm_irq.h"
  62 #include "dm_helpers.h"
  63 #include "amdgpu_dm_mst_types.h"
  64 #if defined(CONFIG_DEBUG_FS)
  65 #include "amdgpu_dm_debugfs.h"
  66 #endif
  67 #include "amdgpu_dm_psr.h"
  68
  69 #include "ivsrcid/ivsrcid_vislands30.h"
  70
  71 #include <linux/backlight.h>
  72 #include <linux/module.h>
  73 #include <linux/moduleparam.h>
  74 #include <linux/types.h>
  75 #include <linux/pm_runtime.h>
  76 #include <linux/pci.h>
  77 #include <linux/firmware.h>
  78 #include <linux/component.h>
  79 #include <linux/dmi.h>
  80
  81 #include <drm/display/drm_dp_mst_helper.h>
  82 #include <drm/display/drm_hdmi_helper.h>
  83 #include <drm/drm_atomic.h>
  84 #include <drm/drm_atomic_uapi.h>
  85 #include <drm/drm_atomic_helper.h>
  86 #include <drm/drm_blend.h>
  87 #include <drm/drm_fourcc.h>
  88 #include <drm/drm_edid.h>
  89 #include <drm/drm_vblank.h>
  90 #include <drm/drm_audio_component.h>
  91 #include <drm/drm_gem_atomic_helper.h>
  92 #include <drm/drm_plane_helper.h>
  93
  94 #include <acpi/video.h>
  95
  96 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
  97
  98 #include "dcn/dcn_1_0_offset.h"
  99 #include "dcn/dcn_1_0_sh_mask.h"
 100 #include "soc15_hw_ip.h"
 101 #include "soc15_common.h"
 102 #include "vega10_ip_offset.h"
 103
 104 #include "gc/gc_11_0_0_offset.h"
 105 #include "gc/gc_11_0_0_sh_mask.h"
 106
 107 #include "modules/inc/mod_freesync.h"
 108 #include "modules/power/power_helpers.h"
 109
 110 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
 111 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
 112 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"
 113 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
 114 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
 115 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
 116 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
 117 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
 118 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
 119 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
 120 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"
 121 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
 122 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin"
 123 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);
 124 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin"
 125 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);
 126 #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin"
 127 MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB);
 128 #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin"
 129 MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB);
 130 #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin"
 131 MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB);
 132
 133 #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin"
 134 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB);
 135 #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin"
 136 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB);
 137
 138 #define FIRMWARE_RAVEN_DMCU             "amdgpu/raven_dmcu.bin"
 139 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
 140
 141 #define FIRMWARE_NAVI12_DMCU            "amdgpu/navi12_dmcu.bin"
 142 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);
 143
 144 /* Number of bytes in PSP header for firmware. */
 145 #define PSP_HEADER_BYTES 0x100
 146
 147 /* Number of bytes in PSP footer for firmware. */
 148 #define PSP_FOOTER_BYTES 0x100
 149
 150 /**
 151  * DOC: overview
 152  *
 153  * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
 154  * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM
 155  * requests into DC requests, and DC responses into DRM responses.
 156  *
 157  * The root control structure is &struct amdgpu_display_manager.
 158  */
 159
 160 /* basic init/fini API */
 161 static int amdgpu_dm_init(struct amdgpu_device *adev);
 162 static void amdgpu_dm_fini(struct amdgpu_device *adev);
 163 static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector);
 164
 165 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)
 166 {
 167         switch (link->dpcd_caps.dongle_type) {
 168         case DISPLAY_DONGLE_NONE:
 169                 return DRM_MODE_SUBCONNECTOR_Native;
 170         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
 171                 return DRM_MODE_SUBCONNECTOR_VGA;
 172         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
 173         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 174                 return DRM_MODE_SUBCONNECTOR_DVID;
 175         case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
 176         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 177                 return DRM_MODE_SUBCONNECTOR_HDMIA;
 178         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 179         default:
 180                 return DRM_MODE_SUBCONNECTOR_Unknown;
 181         }
 182 }
 183
 184 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector)
 185 {
 186         struct dc_link *link = aconnector->dc_link;
 187         struct drm_connector *connector = &aconnector->base;
 188         enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
 189
 190         if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
 191                 return;
 192
 193         if (aconnector->dc_sink)
 194                 subconnector = get_subconnector_type(link);
 195
 196         drm_object_property_set_value(&connector->base,
 197                         connector->dev->mode_config.dp_subconnector_property,
 198                         subconnector);
 199 }
 200
 201 /*
 202  * initializes drm_device display related structures, based on the information
 203  * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
 204  * drm_encoder, drm_mode_config
 205  *
 206  * Returns 0 on success
 207  */
 208 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
 209 /* removes and deallocates the drm structures, created by the above function */
 210 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
 211
 212 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
 213                                     struct amdgpu_dm_connector *amdgpu_dm_connector,
 214                                     u32 link_index,
 215                                     struct amdgpu_encoder *amdgpu_encoder);
 216 static int amdgpu_dm_encoder_init(struct drm_device *dev,
 217                                   struct amdgpu_encoder *aencoder,
 218                                   uint32_t link_index);
 219
 220 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
 221
 222 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
 223
 224 static int amdgpu_dm_atomic_check(struct drm_device *dev,
 225                                   struct drm_atomic_state *state);
 226
 227 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector);
 228 static void handle_hpd_rx_irq(void *param);
 229
 230 static bool
 231 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
 232                                  struct drm_crtc_state *new_crtc_state);
 233 /*
 234  * dm_vblank_get_counter
 235  *
 236  * @brief
 237  * Get counter for number of vertical blanks
 238  *
 239  * @param
 240  * struct amdgpu_device *adev - [in] desired amdgpu device
 241  * int disp_idx - [in] which CRTC to get the counter from
 242  *
 243  * @return
 244  * Counter for vertical blanks
 245  */
 246 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 247 {
 248         if (crtc >= adev->mode_info.num_crtc)
 249                 return 0;
 250         else {
 251                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 252
 253                 if (acrtc->dm_irq_params.stream == NULL) {
 254                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 255                                   crtc);
 256                         return 0;
 257                 }
 258
 259                 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);
 260         }
 261 }
 262
 263 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 264                                   u32 *vbl, u32 *position)
 265 {
 266         u32 v_blank_start, v_blank_end, h_position, v_position;
 267
 268         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 269                 return -EINVAL;
 270         else {
 271                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 272
 273                 if (acrtc->dm_irq_params.stream ==  NULL) {
 274                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 275                                   crtc);
 276                         return 0;
 277                 }
 278
 279                 /*
 280                  * TODO rework base driver to use values directly.
 281                  * for now parse it back into reg-format
 282                  */
 283                 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream,
 284                                          &v_blank_start,
 285                                          &v_blank_end,
 286                                          &h_position,
 287                                          &v_position);
 288
 289                 *position = v_position | (h_position << 16);
 290                 *vbl = v_blank_start | (v_blank_end << 16);
 291         }
 292
 293         return 0;
 294 }
 295
 296 static bool dm_is_idle(void *handle)
 297 {
 298         /* XXX todo */
 299         return true;
 300 }
 301
 302 static int dm_wait_for_idle(void *handle)
 303 {
 304         /* XXX todo */
 305         return 0;
 306 }
 307
 308 static bool dm_check_soft_reset(void *handle)
 309 {
 310         return false;
 311 }
 312
 313 static int dm_soft_reset(void *handle)
 314 {
 315         /* XXX todo */
 316         return 0;
 317 }
 318
 319 static struct amdgpu_crtc *
 320 get_crtc_by_otg_inst(struct amdgpu_device *adev,
 321                      int otg_inst)
 322 {
 323         struct drm_device *dev = adev_to_drm(adev);
 324         struct drm_crtc *crtc;
 325         struct amdgpu_crtc *amdgpu_crtc;
 326
 327         if (WARN_ON(otg_inst == -1))
 328                 return adev->mode_info.crtcs[0];
 329
 330         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 331                 amdgpu_crtc = to_amdgpu_crtc(crtc);
 332
 333                 if (amdgpu_crtc->otg_inst == otg_inst)
 334                         return amdgpu_crtc;
 335         }
 336
 337         return NULL;
 338 }
 339
 340 static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,
 341                                               struct dm_crtc_state *new_state)
 342 {
 343         if (new_state->freesync_config.state ==  VRR_STATE_ACTIVE_FIXED)
 344                 return true;
 345         else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state))
 346                 return true;
 347         else
 348                 return false;
 349 }
 350
 351 static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update,
 352                                         int planes_count)
 353 {
 354         int i, j;
 355
 356         for (i = 0, j = planes_count - 1; i < j; i++, j--)
 357                 swap(array_of_surface_update[i], array_of_surface_update[j]);
 358 }
 359
 360 /**
 361  * update_planes_and_stream_adapter() - Send planes to be updated in DC
 362  *
 363  * DC has a generic way to update planes and stream via
 364  * dc_update_planes_and_stream function; however, DM might need some
 365  * adjustments and preparation before calling it. This function is a wrapper
 366  * for the dc_update_planes_and_stream that does any required configuration
 367  * before passing control to DC.
 368  */
 369 static inline bool update_planes_and_stream_adapter(struct dc *dc,
 370                                                     int update_type,
 371                                                     int planes_count,
 372                                                     struct dc_stream_state *stream,
 373                                                     struct dc_stream_update *stream_update,
 374                                                     struct dc_surface_update *array_of_surface_update)
 375 {
 376         reverse_planes_order(array_of_surface_update, planes_count);
 377
 378         /*
 379          * Previous frame finished and HW is ready for optimization.
 380          */
 381         if (update_type == UPDATE_TYPE_FAST)
 382                 dc_post_update_surfaces_to_stream(dc);
 383
 384         return dc_update_planes_and_stream(dc,
 385                                            array_of_surface_update,
 386                                            planes_count,
 387                                            stream,
 388                                            stream_update);
 389 }
 390
 391 /**
 392  * dm_pflip_high_irq() - Handle pageflip interrupt
 393  * @interrupt_params: ignored
 394  *
 395  * Handles the pageflip interrupt by notifying all interested parties
 396  * that the pageflip has been completed.
 397  */
 398 static void dm_pflip_high_irq(void *interrupt_params)
 399 {
 400         struct amdgpu_crtc *amdgpu_crtc;
 401         struct common_irq_params *irq_params = interrupt_params;
 402         struct amdgpu_device *adev = irq_params->adev;
 403         unsigned long flags;
 404         struct drm_pending_vblank_event *e;
 405         u32 vpos, hpos, v_blank_start, v_blank_end;
 406         bool vrr_active;
 407
 408         amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
 409
 410         /* IRQ could occur when in initial stage */
 411         /* TODO work and BO cleanup */
 412         if (amdgpu_crtc == NULL) {
 413                 DC_LOG_PFLIP("CRTC is null, returning.\n");
 414                 return;
 415         }
 416
 417         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 418
 419         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
 420                 DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
 421                                                  amdgpu_crtc->pflip_status,
 422                                                  AMDGPU_FLIP_SUBMITTED,
 423                                                  amdgpu_crtc->crtc_id,
 424                                                  amdgpu_crtc);
 425                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 426                 return;
 427         }
 428
 429         /* page flip completed. */
 430         e = amdgpu_crtc->event;
 431         amdgpu_crtc->event = NULL;
 432
 433         WARN_ON(!e);
 434
 435         vrr_active = amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc);
 436
 437         /* Fixed refresh rate, or VRR scanout position outside front-porch? */
 438         if (!vrr_active ||
 439             !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start,
 440                                       &v_blank_end, &hpos, &vpos) ||
 441             (vpos < v_blank_start)) {
 442                 /* Update to correct count and vblank timestamp if racing with
 443                  * vblank irq. This also updates to the correct vblank timestamp
 444                  * even in VRR mode, as scanout is past the front-porch atm.
 445                  */
 446                 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
 447
 448                 /* Wake up userspace by sending the pageflip event with proper
 449                  * count and timestamp of vblank of flip completion.
 450                  */
 451                 if (e) {
 452                         drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
 453
 454                         /* Event sent, so done with vblank for this flip */
 455                         drm_crtc_vblank_put(&amdgpu_crtc->base);
 456                 }
 457         } else if (e) {
 458                 /* VRR active and inside front-porch: vblank count and
 459                  * timestamp for pageflip event will only be up to date after
 460                  * drm_crtc_handle_vblank() has been executed from late vblank
 461                  * irq handler after start of back-porch (vline 0). We queue the
 462                  * pageflip event for send-out by drm_crtc_handle_vblank() with
 463                  * updated timestamp and count, once it runs after us.
 464                  *
 465                  * We need to open-code this instead of using the helper
 466                  * drm_crtc_arm_vblank_event(), as that helper would
 467                  * call drm_crtc_accurate_vblank_count(), which we must
 468                  * not call in VRR mode while we are in front-porch!
 469                  */
 470
 471                 /* sequence will be replaced by real count during send-out. */
 472                 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
 473                 e->pipe = amdgpu_crtc->crtc_id;
 474
 475                 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list);
 476                 e = NULL;
 477         }
 478
 479         /* Keep track of vblank of this flip for flip throttling. We use the
 480          * cooked hw counter, as that one incremented at start of this vblank
 481          * of pageflip completion, so last_flip_vblank is the forbidden count
 482          * for queueing new pageflips if vsync + VRR is enabled.
 483          */
 484         amdgpu_crtc->dm_irq_params.last_flip_vblank =
 485                 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base);
 486
 487         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
 488         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 489
 490         DC_LOG_PFLIP("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
 491                      amdgpu_crtc->crtc_id, amdgpu_crtc,
 492                      vrr_active, (int) !e);
 493 }
 494
 495 static void dm_vupdate_high_irq(void *interrupt_params)
 496 {
 497         struct common_irq_params *irq_params = interrupt_params;
 498         struct amdgpu_device *adev = irq_params->adev;
 499         struct amdgpu_crtc *acrtc;
 500         struct drm_device *drm_dev;
 501         struct drm_vblank_crtc *vblank;
 502         ktime_t frame_duration_ns, previous_timestamp;
 503         unsigned long flags;
 504         int vrr_active;
 505
 506         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
 507
 508         if (acrtc) {
 509                 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
 510                 drm_dev = acrtc->base.dev;
 511                 vblank = &drm_dev->vblank[acrtc->base.index];
 512                 previous_timestamp = atomic64_read(&irq_params->previous_timestamp);
 513                 frame_duration_ns = vblank->time - previous_timestamp;
 514
 515                 if (frame_duration_ns > 0) {
 516                         trace_amdgpu_refresh_rate_track(acrtc->base.index,
 517                                                 frame_duration_ns,
 518                                                 ktime_divns(NSEC_PER_SEC, frame_duration_ns));
 519                         atomic64_set(&irq_params->previous_timestamp, vblank->time);
 520                 }
 521
 522                 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d\n",
 523                               acrtc->crtc_id,
 524                               vrr_active);
 525
 526                 /* Core vblank handling is done here after end of front-porch in
 527                  * vrr mode, as vblank timestamping will give valid results
 528                  * while now done after front-porch. This will also deliver
 529                  * page-flip completion events that have been queued to us
 530                  * if a pageflip happened inside front-porch.
 531                  */
 532                 if (vrr_active) {
 533                         amdgpu_dm_crtc_handle_vblank(acrtc);
 534
 535                         /* BTR processing for pre-DCE12 ASICs */
 536                         if (acrtc->dm_irq_params.stream &&
 537                             adev->family < AMDGPU_FAMILY_AI) {
 538                                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 539                                 mod_freesync_handle_v_update(
 540                                     adev->dm.freesync_module,
 541                                     acrtc->dm_irq_params.stream,
 542                                     &acrtc->dm_irq_params.vrr_params);
 543
 544                                 dc_stream_adjust_vmin_vmax(
 545                                     adev->dm.dc,
 546                                     acrtc->dm_irq_params.stream,
 547                                     &acrtc->dm_irq_params.vrr_params.adjust);
 548                                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 549                         }
 550                 }
 551         }
 552 }
 553
 554 /**
 555  * dm_crtc_high_irq() - Handles CRTC interrupt
 556  * @interrupt_params: used for determining the CRTC instance
 557  *
 558  * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
 559  * event handler.
 560  */
 561 static void dm_crtc_high_irq(void *interrupt_params)
 562 {
 563         struct common_irq_params *irq_params = interrupt_params;
 564         struct amdgpu_device *adev = irq_params->adev;
 565         struct amdgpu_crtc *acrtc;
 566         unsigned long flags;
 567         int vrr_active;
 568
 569         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
 570         if (!acrtc)
 571                 return;
 572
 573         vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
 574
 575         DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,
 576                       vrr_active, acrtc->dm_irq_params.active_planes);
 577
 578         /**
 579          * Core vblank handling at start of front-porch is only possible
 580          * in non-vrr mode, as only there vblank timestamping will give
 581          * valid results while done in front-porch. Otherwise defer it
 582          * to dm_vupdate_high_irq after end of front-porch.
 583          */
 584         if (!vrr_active)
 585                 amdgpu_dm_crtc_handle_vblank(acrtc);
 586
 587         /**
 588          * Following stuff must happen at start of vblank, for crc
 589          * computation and below-the-range btr support in vrr mode.
 590          */
 591         amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
 592
 593         /* BTR updates need to happen before VUPDATE on Vega and above. */
 594         if (adev->family < AMDGPU_FAMILY_AI)
 595                 return;
 596
 597         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 598
 599         if (acrtc->dm_irq_params.stream &&
 600             acrtc->dm_irq_params.vrr_params.supported &&
 601             acrtc->dm_irq_params.freesync_config.state ==
 602                     VRR_STATE_ACTIVE_VARIABLE) {
 603                 mod_freesync_handle_v_update(adev->dm.freesync_module,
 604                                              acrtc->dm_irq_params.stream,
 605                                              &acrtc->dm_irq_params.vrr_params);
 606
 607                 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,
 608                                            &acrtc->dm_irq_params.vrr_params.adjust);
 609         }
 610
 611         /*
 612          * If there aren't any active_planes then DCH HUBP may be clock-gated.
 613          * In that case, pageflip completion interrupts won't fire and pageflip
 614          * completion events won't get delivered. Prevent this by sending
 615          * pending pageflip events from here if a flip is still pending.
 616          *
 617          * If any planes are enabled, use dm_pflip_high_irq() instead, to
 618          * avoid race conditions between flip programming and completion,
 619          * which could cause too early flip completion events.
 620          */
 621         if (adev->family >= AMDGPU_FAMILY_RV &&
 622             acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
 623             acrtc->dm_irq_params.active_planes == 0) {
 624                 if (acrtc->event) {
 625                         drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
 626                         acrtc->event = NULL;
 627                         drm_crtc_vblank_put(&acrtc->base);
 628                 }
 629                 acrtc->pflip_status = AMDGPU_FLIP_NONE;
 630         }
 631
 632         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 633 }
 634
 635 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
 636 /**
 637  * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for
 638  * DCN generation ASICs
 639  * @interrupt_params: interrupt parameters
 640  *
 641  * Used to set crc window/read out crc value at vertical line 0 position
 642  */
 643 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)
 644 {
 645         struct common_irq_params *irq_params = interrupt_params;
 646         struct amdgpu_device *adev = irq_params->adev;
 647         struct amdgpu_crtc *acrtc;
 648
 649         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0);
 650
 651         if (!acrtc)
 652                 return;
 653
 654         amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base);
 655 }
 656 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */
 657
 658 /**
 659  * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command.
 660  * @adev: amdgpu_device pointer
 661  * @notify: dmub notification structure
 662  *
 663  * Dmub AUX or SET_CONFIG command completion processing callback
 664  * Copies dmub notification to DM which is to be read by AUX command.
 665  * issuing thread and also signals the event to wake up the thread.
 666  */
 667 static void dmub_aux_setconfig_callback(struct amdgpu_device *adev,
 668                                         struct dmub_notification *notify)
 669 {
 670         if (adev->dm.dmub_notify)
 671                 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification));
 672         if (notify->type == DMUB_NOTIFICATION_AUX_REPLY)
 673                 complete(&adev->dm.dmub_aux_transfer_done);
 674 }
 675
 676 /**
 677  * dmub_hpd_callback - DMUB HPD interrupt processing callback.
 678  * @adev: amdgpu_device pointer
 679  * @notify: dmub notification structure
 680  *
 681  * Dmub Hpd interrupt processing callback. Gets displayindex through the
 682  * ink index and calls helper to do the processing.
 683  */
 684 static void dmub_hpd_callback(struct amdgpu_device *adev,
 685                               struct dmub_notification *notify)
 686 {
 687         struct amdgpu_dm_connector *aconnector;
 688         struct amdgpu_dm_connector *hpd_aconnector = NULL;
 689         struct drm_connector *connector;
 690         struct drm_connector_list_iter iter;
 691         struct dc_link *link;
 692         u8 link_index = 0;
 693         struct drm_device *dev;
 694
 695         if (adev == NULL)
 696                 return;
 697
 698         if (notify == NULL) {
 699                 DRM_ERROR("DMUB HPD callback notification was NULL");
 700                 return;
 701         }
 702
 703         if (notify->link_index > adev->dm.dc->link_count) {
 704                 DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index);
 705                 return;
 706         }
 707
 708         link_index = notify->link_index;
 709         link = adev->dm.dc->links[link_index];
 710         dev = adev->dm.ddev;
 711
 712         drm_connector_list_iter_begin(dev, &iter);
 713         drm_for_each_connector_iter(connector, &iter) {
 714                 aconnector = to_amdgpu_dm_connector(connector);
 715                 if (link && aconnector->dc_link == link) {
 716                         if (notify->type == DMUB_NOTIFICATION_HPD)
 717                                 DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index);
 718                         else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
 719                                 DRM_INFO("DMUB HPD IRQ callback: link_index=%u\n", link_index);
 720                         else
 721                                 DRM_WARN("DMUB Unknown HPD callback type %d, link_index=%u\n",
 722                                                 notify->type, link_index);
 723
 724                         hpd_aconnector = aconnector;
 725                         break;
 726                 }
 727         }
 728         drm_connector_list_iter_end(&iter);
 729
 730         if (hpd_aconnector) {
 731                 if (notify->type == DMUB_NOTIFICATION_HPD)
 732                         handle_hpd_irq_helper(hpd_aconnector);
 733                 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
 734                         handle_hpd_rx_irq(hpd_aconnector);
 735         }
 736 }
 737
 738 /**
 739  * register_dmub_notify_callback - Sets callback for DMUB notify
 740  * @adev: amdgpu_device pointer
 741  * @type: Type of dmub notification
 742  * @callback: Dmub interrupt callback function
 743  * @dmub_int_thread_offload: offload indicator
 744  *
 745  * API to register a dmub callback handler for a dmub notification
 746  * Also sets indicator whether callback processing to be offloaded.
 747  * to dmub interrupt handling thread
 748  * Return: true if successfully registered, false if there is existing registration
 749  */
 750 static bool register_dmub_notify_callback(struct amdgpu_device *adev,
 751                                           enum dmub_notification_type type,
 752                                           dmub_notify_interrupt_callback_t callback,
 753                                           bool dmub_int_thread_offload)
 754 {
 755         if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) {
 756                 adev->dm.dmub_callback[type] = callback;
 757                 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload;
 758         } else
 759                 return false;
 760
 761         return true;
 762 }
 763
 764 static void dm_handle_hpd_work(struct work_struct *work)
 765 {
 766         struct dmub_hpd_work *dmub_hpd_wrk;
 767
 768         dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work);
 769
 770         if (!dmub_hpd_wrk->dmub_notify) {
 771                 DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL");
 772                 return;
 773         }
 774
 775         if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) {
 776                 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev,
 777                 dmub_hpd_wrk->dmub_notify);
 778         }
 779
 780         kfree(dmub_hpd_wrk->dmub_notify);
 781         kfree(dmub_hpd_wrk);
 782
 783 }
 784
 785 #define DMUB_TRACE_MAX_READ 64
 786 /**
 787  * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt
 788  * @interrupt_params: used for determining the Outbox instance
 789  *
 790  * Handles the Outbox Interrupt
 791  * event handler.
 792  */
 793 static void dm_dmub_outbox1_low_irq(void *interrupt_params)
 794 {
 795         struct dmub_notification notify;
 796         struct common_irq_params *irq_params = interrupt_params;
 797         struct amdgpu_device *adev = irq_params->adev;
 798         struct amdgpu_display_manager *dm = &adev->dm;
 799         struct dmcub_trace_buf_entry entry = { 0 };
 800         u32 count = 0;
 801         struct dmub_hpd_work *dmub_hpd_wrk;
 802         struct dc_link *plink = NULL;
 803
 804         if (dc_enable_dmub_notifications(adev->dm.dc) &&
 805                 irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) {
 806
 807                 do {
 808                         dc_stat_get_dmub_notification(adev->dm.dc, &notify);
 809                         if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) {
 810                                 DRM_ERROR("DM: notify type %d invalid!", notify.type);
 811                                 continue;
 812                         }
 813                         if (!dm->dmub_callback[notify.type]) {
 814                                 DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type);
 815                                 continue;
 816                         }
 817                         if (dm->dmub_thread_offload[notify.type] == true) {
 818                                 dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC);
 819                                 if (!dmub_hpd_wrk) {
 820                                         DRM_ERROR("Failed to allocate dmub_hpd_wrk");
 821                                         return;
 822                                 }
 823                                 dmub_hpd_wrk->dmub_notify = kmemdup(&notify, sizeof(struct dmub_notification),
 824                                                                     GFP_ATOMIC);
 825                                 if (!dmub_hpd_wrk->dmub_notify) {
 826                                         kfree(dmub_hpd_wrk);
 827                                         DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify");
 828                                         return;
 829                                 }
 830                                 INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work);
 831                                 dmub_hpd_wrk->adev = adev;
 832                                 if (notify.type == DMUB_NOTIFICATION_HPD) {
 833                                         plink = adev->dm.dc->links[notify.link_index];
 834                                         if (plink) {
 835                                                 plink->hpd_status =
 836                                                         notify.hpd_status == DP_HPD_PLUG;
 837                                         }
 838                                 }
 839                                 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work);
 840                         } else {
 841                                 dm->dmub_callback[notify.type](adev, &notify);
 842                         }
 843                 } while (notify.pending_notification);
 844         }
 845
 846
 847         do {
 848                 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {
 849                         trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,
 850                                                         entry.param0, entry.param1);
 851
 852                         DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",
 853                                  entry.trace_code, entry.tick_count, entry.param0, entry.param1);
 854                 } else
 855                         break;
 856
 857                 count++;
 858
 859         } while (count <= DMUB_TRACE_MAX_READ);
 860
 861         if (count > DMUB_TRACE_MAX_READ)
 862                 DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ");
 863 }
 864
 865 static int dm_set_clockgating_state(void *handle,
 866                   enum amd_clockgating_state state)
 867 {
 868         return 0;
 869 }
 870
 871 static int dm_set_powergating_state(void *handle,
 872                   enum amd_powergating_state state)
 873 {
 874         return 0;
 875 }
 876
 877 /* Prototypes of private functions */
 878 static int dm_early_init(void* handle);
 879
 880 /* Allocate memory for FBC compressed data  */
 881 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
 882 {
 883         struct drm_device *dev = connector->dev;
 884         struct amdgpu_device *adev = drm_to_adev(dev);
 885         struct dm_compressor_info *compressor = &adev->dm.compressor;
 886         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
 887         struct drm_display_mode *mode;
 888         unsigned long max_size = 0;
 889
 890         if (adev->dm.dc->fbc_compressor == NULL)
 891                 return;
 892
 893         if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
 894                 return;
 895
 896         if (compressor->bo_ptr)
 897                 return;
 898
 899
 900         list_for_each_entry(mode, &connector->modes, head) {
 901                 if (max_size < mode->htotal * mode->vtotal)
 902                         max_size = mode->htotal * mode->vtotal;
 903         }
 904
 905         if (max_size) {
 906                 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
 907                             AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
 908                             &compressor->gpu_addr, &compressor->cpu_addr);
 909
 910                 if (r)
 911                         DRM_ERROR("DM: Failed to initialize FBC\n");
 912                 else {
 913                         adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
 914                         DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
 915                 }
 916
 917         }
 918
 919 }
 920
 921 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
 922                                           int pipe, bool *enabled,
 923                                           unsigned char *buf, int max_bytes)
 924 {
 925         struct drm_device *dev = dev_get_drvdata(kdev);
 926         struct amdgpu_device *adev = drm_to_adev(dev);
 927         struct drm_connector *connector;
 928         struct drm_connector_list_iter conn_iter;
 929         struct amdgpu_dm_connector *aconnector;
 930         int ret = 0;
 931
 932         *enabled = false;
 933
 934         mutex_lock(&adev->dm.audio_lock);
 935
 936         drm_connector_list_iter_begin(dev, &conn_iter);
 937         drm_for_each_connector_iter(connector, &conn_iter) {
 938                 aconnector = to_amdgpu_dm_connector(connector);
 939                 if (aconnector->audio_inst != port)
 940                         continue;
 941
 942                 *enabled = true;
 943                 ret = drm_eld_size(connector->eld);
 944                 memcpy(buf, connector->eld, min(max_bytes, ret));
 945
 946                 break;
 947         }
 948         drm_connector_list_iter_end(&conn_iter);
 949
 950         mutex_unlock(&adev->dm.audio_lock);
 951
 952         DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
 953
 954         return ret;
 955 }
 956
 957 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
 958         .get_eld = amdgpu_dm_audio_component_get_eld,
 959 };
 960
 961 static int amdgpu_dm_audio_component_bind(struct device *kdev,
 962                                        struct device *hda_kdev, void *data)
 963 {
 964         struct drm_device *dev = dev_get_drvdata(kdev);
 965         struct amdgpu_device *adev = drm_to_adev(dev);
 966         struct drm_audio_component *acomp = data;
 967
 968         acomp->ops = &amdgpu_dm_audio_component_ops;
 969         acomp->dev = kdev;
 970         adev->dm.audio_component = acomp;
 971
 972         return 0;
 973 }
 974
 975 static void amdgpu_dm_audio_component_unbind(struct device *kdev,
 976                                           struct device *hda_kdev, void *data)
 977 {
 978         struct drm_device *dev = dev_get_drvdata(kdev);
 979         struct amdgpu_device *adev = drm_to_adev(dev);
 980         struct drm_audio_component *acomp = data;
 981
 982         acomp->ops = NULL;
 983         acomp->dev = NULL;
 984         adev->dm.audio_component = NULL;
 985 }
 986
 987 static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
 988         .bind   = amdgpu_dm_audio_component_bind,
 989         .unbind = amdgpu_dm_audio_component_unbind,
 990 };
 991
 992 static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
 993 {
 994         int i, ret;
 995
 996         if (!amdgpu_audio)
 997                 return 0;
 998
 999         adev->mode_info.audio.enabled = true;
1000
1001         adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
1002
1003         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1004                 adev->mode_info.audio.pin[i].channels = -1;
1005                 adev->mode_info.audio.pin[i].rate = -1;
1006                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1007                 adev->mode_info.audio.pin[i].status_bits = 0;
1008                 adev->mode_info.audio.pin[i].category_code = 0;
1009                 adev->mode_info.audio.pin[i].connected = false;
1010                 adev->mode_info.audio.pin[i].id =
1011                         adev->dm.dc->res_pool->audios[i]->inst;
1012                 adev->mode_info.audio.pin[i].offset = 0;
1013         }
1014
1015         ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1016         if (ret < 0)
1017                 return ret;
1018
1019         adev->dm.audio_registered = true;
1020
1021         return 0;
1022 }
1023
1024 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
1025 {
1026         if (!amdgpu_audio)
1027                 return;
1028
1029         if (!adev->mode_info.audio.enabled)
1030                 return;
1031
1032         if (adev->dm.audio_registered) {
1033                 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1034                 adev->dm.audio_registered = false;
1035         }
1036
1037         /* TODO: Disable audio? */
1038
1039         adev->mode_info.audio.enabled = false;
1040 }
1041
1042 static  void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
1043 {
1044         struct drm_audio_component *acomp = adev->dm.audio_component;
1045
1046         if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
1047                 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
1048
1049                 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
1050                                                  pin, -1);
1051         }
1052 }
1053
1054 static int dm_dmub_hw_init(struct amdgpu_device *adev)
1055 {
1056         const struct dmcub_firmware_header_v1_0 *hdr;
1057         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1058         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
1059         const struct firmware *dmub_fw = adev->dm.dmub_fw;
1060         struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
1061         struct abm *abm = adev->dm.dc->res_pool->abm;
1062         struct dmub_srv_hw_params hw_params;
1063         enum dmub_status status;
1064         const unsigned char *fw_inst_const, *fw_bss_data;
1065         u32 i, fw_inst_const_size, fw_bss_data_size;
1066         bool has_hw_support;
1067
1068         if (!dmub_srv)
1069                 /* DMUB isn't supported on the ASIC. */
1070                 return 0;
1071
1072         if (!fb_info) {
1073                 DRM_ERROR("No framebuffer info for DMUB service.\n");
1074                 return -EINVAL;
1075         }
1076
1077         if (!dmub_fw) {
1078                 /* Firmware required for DMUB support. */
1079                 DRM_ERROR("No firmware provided for DMUB.\n");
1080                 return -EINVAL;
1081         }
1082
1083         status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
1084         if (status != DMUB_STATUS_OK) {
1085                 DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
1086                 return -EINVAL;
1087         }
1088
1089         if (!has_hw_support) {
1090                 DRM_INFO("DMUB unsupported on ASIC\n");
1091                 return 0;
1092         }
1093
1094         /* Reset DMCUB if it was previously running - before we overwrite its memory. */
1095         status = dmub_srv_hw_reset(dmub_srv);
1096         if (status != DMUB_STATUS_OK)
1097                 DRM_WARN("Error resetting DMUB HW: %d\n", status);
1098
1099         hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
1100
1101         fw_inst_const = dmub_fw->data +
1102                         le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1103                         PSP_HEADER_BYTES;
1104
1105         fw_bss_data = dmub_fw->data +
1106                       le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1107                       le32_to_cpu(hdr->inst_const_bytes);
1108
1109         /* Copy firmware and bios info into FB memory. */
1110         fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
1111                              PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
1112
1113         fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
1114
1115         /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP,
1116          * amdgpu_ucode_init_single_fw will load dmub firmware
1117          * fw_inst_const part to cw0; otherwise, the firmware back door load
1118          * will be done by dm_dmub_hw_init
1119          */
1120         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1121                 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
1122                                 fw_inst_const_size);
1123         }
1124
1125         if (fw_bss_data_size)
1126                 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr,
1127                        fw_bss_data, fw_bss_data_size);
1128
1129         /* Copy firmware bios info into FB memory. */
1130         memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,
1131                adev->bios_size);
1132
1133         /* Reset regions that need to be reset. */
1134         memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,
1135         fb_info->fb[DMUB_WINDOW_4_MAILBOX].size);
1136
1137         memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,
1138                fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size);
1139
1140         memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,
1141                fb_info->fb[DMUB_WINDOW_6_FW_STATE].size);
1142
1143         /* Initialize hardware. */
1144         memset(&hw_params, 0, sizeof(hw_params));
1145         hw_params.fb_base = adev->gmc.fb_start;
1146         hw_params.fb_offset = adev->vm_manager.vram_base_offset;
1147
1148         /* backdoor load firmware and trigger dmub running */
1149         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
1150                 hw_params.load_inst_const = true;
1151
1152         if (dmcu)
1153                 hw_params.psp_version = dmcu->psp_version;
1154
1155         for (i = 0; i < fb_info->num_fb; ++i)
1156                 hw_params.fb[i] = &fb_info->fb[i];
1157
1158         switch (adev->ip_versions[DCE_HWIP][0]) {
1159         case IP_VERSION(3, 1, 3):
1160         case IP_VERSION(3, 1, 4):
1161                 hw_params.dpia_supported = true;
1162                 hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia;
1163                 break;
1164         default:
1165                 break;
1166         }
1167
1168         status = dmub_srv_hw_init(dmub_srv, &hw_params);
1169         if (status != DMUB_STATUS_OK) {
1170                 DRM_ERROR("Error initializing DMUB HW: %d\n", status);
1171                 return -EINVAL;
1172         }
1173
1174         /* Wait for firmware load to finish. */
1175         status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1176         if (status != DMUB_STATUS_OK)
1177                 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1178
1179         /* Init DMCU and ABM if available. */
1180         if (dmcu && abm) {
1181                 dmcu->funcs->dmcu_init(dmcu);
1182                 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
1183         }
1184
1185         if (!adev->dm.dc->ctx->dmub_srv)
1186                 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
1187         if (!adev->dm.dc->ctx->dmub_srv) {
1188                 DRM_ERROR("Couldn't allocate DC DMUB server!\n");
1189                 return -ENOMEM;
1190         }
1191
1192         DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
1193                  adev->dm.dmcub_fw_version);
1194
1195         return 0;
1196 }
1197
1198 static void dm_dmub_hw_resume(struct amdgpu_device *adev)
1199 {
1200         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1201         enum dmub_status status;
1202         bool init;
1203
1204         if (!dmub_srv) {
1205                 /* DMUB isn't supported on the ASIC. */
1206                 return;
1207         }
1208
1209         status = dmub_srv_is_hw_init(dmub_srv, &init);
1210         if (status != DMUB_STATUS_OK)
1211                 DRM_WARN("DMUB hardware init check failed: %d\n", status);
1212
1213         if (status == DMUB_STATUS_OK && init) {
1214                 /* Wait for firmware load to finish. */
1215                 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1216                 if (status != DMUB_STATUS_OK)
1217                         DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1218         } else {
1219                 /* Perform the full hardware initialization. */
1220                 dm_dmub_hw_init(adev);
1221         }
1222 }
1223
1224 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
1225 {
1226         u64 pt_base;
1227         u32 logical_addr_low;
1228         u32 logical_addr_high;
1229         u32 agp_base, agp_bot, agp_top;
1230         PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;
1231
1232         memset(pa_config, 0, sizeof(*pa_config));
1233
1234         agp_base = 0;
1235         agp_bot = adev->gmc.agp_start >> 24;
1236         agp_top = adev->gmc.agp_end >> 24;
1237
1238         /* AGP aperture is disabled */
1239         if (agp_bot == agp_top) {
1240                 logical_addr_low = adev->gmc.fb_start >> 18;
1241                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1242                         /*
1243                          * Raven2 has a HW issue that it is unable to use the vram which
1244                          * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1245                          * workaround that increase system aperture high address (add 1)
1246                          * to get rid of the VM fault and hardware hang.
1247                          */
1248                         logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1;
1249                 else
1250                         logical_addr_high = adev->gmc.fb_end >> 18;
1251         } else {
1252                 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
1253                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1254                         /*
1255                          * Raven2 has a HW issue that it is unable to use the vram which
1256                          * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1257                          * workaround that increase system aperture high address (add 1)
1258                          * to get rid of the VM fault and hardware hang.
1259                          */
1260                         logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
1261                 else
1262                         logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
1263         }
1264
1265         pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
1266
1267         page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF;
1268         page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12);
1269         page_table_end.high_part = (u32)(adev->gmc.gart_end >> 44) & 0xF;
1270         page_table_end.low_part = (u32)(adev->gmc.gart_end >> 12);
1271         page_table_base.high_part = upper_32_bits(pt_base) & 0xF;
1272         page_table_base.low_part = lower_32_bits(pt_base);
1273
1274         pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
1275         pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18;
1276
1277         pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24 ;
1278         pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24;
1279         pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24;
1280
1281         pa_config->system_aperture.fb_base = adev->gmc.fb_start;
1282         pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset;
1283         pa_config->system_aperture.fb_top = adev->gmc.fb_end;
1284
1285         pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12;
1286         pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12;
1287         pa_config->gart_config.page_table_base_addr = page_table_base.quad_part;
1288
1289         pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support;
1290
1291 }
1292
1293 static void force_connector_state(
1294         struct amdgpu_dm_connector *aconnector,
1295         enum drm_connector_force force_state)
1296 {
1297         struct drm_connector *connector = &aconnector->base;
1298
1299         mutex_lock(&connector->dev->mode_config.mutex);
1300         aconnector->base.force = force_state;
1301         mutex_unlock(&connector->dev->mode_config.mutex);
1302
1303         mutex_lock(&aconnector->hpd_lock);
1304         drm_kms_helper_connector_hotplug_event(connector);
1305         mutex_unlock(&aconnector->hpd_lock);
1306 }
1307
1308 static void dm_handle_hpd_rx_offload_work(struct work_struct *work)
1309 {
1310         struct hpd_rx_irq_offload_work *offload_work;
1311         struct amdgpu_dm_connector *aconnector;
1312         struct dc_link *dc_link;
1313         struct amdgpu_device *adev;
1314         enum dc_connection_type new_connection_type = dc_connection_none;
1315         unsigned long flags;
1316         union test_response test_response;
1317
1318         memset(&test_response, 0, sizeof(test_response));
1319
1320         offload_work = container_of(work, struct hpd_rx_irq_offload_work, work);
1321         aconnector = offload_work->offload_wq->aconnector;
1322
1323         if (!aconnector) {
1324                 DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work");
1325                 goto skip;
1326         }
1327
1328         adev = drm_to_adev(aconnector->base.dev);
1329         dc_link = aconnector->dc_link;
1330
1331         mutex_lock(&aconnector->hpd_lock);
1332         if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
1333                 DRM_ERROR("KMS: Failed to detect connector\n");
1334         mutex_unlock(&aconnector->hpd_lock);
1335
1336         if (new_connection_type == dc_connection_none)
1337                 goto skip;
1338
1339         if (amdgpu_in_reset(adev))
1340                 goto skip;
1341
1342         mutex_lock(&adev->dm.dc_lock);
1343         if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
1344                 dc_link_dp_handle_automated_test(dc_link);
1345
1346                 if (aconnector->timing_changed) {
1347                         /* force connector disconnect and reconnect */
1348                         force_connector_state(aconnector, DRM_FORCE_OFF);
1349                         msleep(100);
1350                         force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED);
1351                 }
1352
1353                 test_response.bits.ACK = 1;
1354
1355                 core_link_write_dpcd(
1356                 dc_link,
1357                 DP_TEST_RESPONSE,
1358                 &test_response.raw,
1359                 sizeof(test_response));
1360         }
1361         else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) &&
1362                         dc_link_check_link_loss_status(dc_link, &offload_work->data) &&
1363                         dc_link_dp_allow_hpd_rx_irq(dc_link)) {
1364                 /* offload_work->data is from handle_hpd_rx_irq->
1365                  * schedule_hpd_rx_offload_work.this is defer handle
1366                  * for hpd short pulse. upon here, link status may be
1367                  * changed, need get latest link status from dpcd
1368                  * registers. if link status is good, skip run link
1369                  * training again.
1370                  */
1371                 union hpd_irq_data irq_data;
1372
1373                 memset(&irq_data, 0, sizeof(irq_data));
1374
1375                 /* before dc_link_dp_handle_link_loss, allow new link lost handle
1376                  * request be added to work queue if link lost at end of dc_link_
1377                  * dp_handle_link_loss
1378                  */
1379                 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1380                 offload_work->offload_wq->is_handling_link_loss = false;
1381                 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1382
1383                 if ((dc_link_dp_read_hpd_rx_irq_data(dc_link, &irq_data) == DC_OK) &&
1384                         dc_link_check_link_loss_status(dc_link, &irq_data))
1385                         dc_link_dp_handle_link_loss(dc_link);
1386         }
1387         mutex_unlock(&adev->dm.dc_lock);
1388
1389 skip:
1390         kfree(offload_work);
1391
1392 }
1393
1394 static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc)
1395 {
1396         int max_caps = dc->caps.max_links;
1397         int i = 0;
1398         struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL;
1399
1400         hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL);
1401
1402         if (!hpd_rx_offload_wq)
1403                 return NULL;
1404
1405
1406         for (i = 0; i < max_caps; i++) {
1407                 hpd_rx_offload_wq[i].wq =
1408                                     create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq");
1409
1410                 if (hpd_rx_offload_wq[i].wq == NULL) {
1411                         DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!");
1412                         goto out_err;
1413                 }
1414
1415                 spin_lock_init(&hpd_rx_offload_wq[i].offload_lock);
1416         }
1417
1418         return hpd_rx_offload_wq;
1419
1420 out_err:
1421         for (i = 0; i < max_caps; i++) {
1422                 if (hpd_rx_offload_wq[i].wq)
1423                         destroy_workqueue(hpd_rx_offload_wq[i].wq);
1424         }
1425         kfree(hpd_rx_offload_wq);
1426         return NULL;
1427 }
1428
1429 struct amdgpu_stutter_quirk {
1430         u16 chip_vendor;
1431         u16 chip_device;
1432         u16 subsys_vendor;
1433         u16 subsys_device;
1434         u8 revision;
1435 };
1436
1437 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = {
1438         /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */
1439         { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },
1440         { 0, 0, 0, 0, 0 },
1441 };
1442
1443 static bool dm_should_disable_stutter(struct pci_dev *pdev)
1444 {
1445         const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list;
1446
1447         while (p && p->chip_device != 0) {
1448                 if (pdev->vendor == p->chip_vendor &&
1449                     pdev->device == p->chip_device &&
1450                     pdev->subsystem_vendor == p->subsys_vendor &&
1451                     pdev->subsystem_device == p->subsys_device &&
1452                     pdev->revision == p->revision) {
1453                         return true;
1454                 }
1455                 ++p;
1456         }
1457         return false;
1458 }
1459
1460 static const struct dmi_system_id hpd_disconnect_quirk_table[] = {
1461         {
1462                 .matches = {
1463                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1464                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"),
1465                 },
1466         },
1467         {
1468                 .matches = {
1469                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1470                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"),
1471                 },
1472         },
1473         {
1474                 .matches = {
1475                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1476                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"),
1477                 },
1478         },
1479         {
1480                 .matches = {
1481                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1482                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"),
1483                 },
1484         },
1485         {
1486                 .matches = {
1487                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1488                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"),
1489                 },
1490         },
1491         {
1492                 .matches = {
1493                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1494                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"),
1495                 },
1496         },
1497         {
1498                 .matches = {
1499                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1500                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"),
1501                 },
1502         },
1503         {
1504                 .matches = {
1505                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1506                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"),
1507                 },
1508         },
1509         {
1510                 .matches = {
1511                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1512                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"),
1513                 },
1514         },
1515         {}
1516         /* TODO: refactor this from a fixed table to a dynamic option */
1517 };
1518
1519 static void retrieve_dmi_info(struct amdgpu_display_manager *dm)
1520 {
1521         const struct dmi_system_id *dmi_id;
1522
1523         dm->aux_hpd_discon_quirk = false;
1524
1525         dmi_id = dmi_first_match(hpd_disconnect_quirk_table);
1526         if (dmi_id) {
1527                 dm->aux_hpd_discon_quirk = true;
1528                 DRM_INFO("aux_hpd_discon_quirk attached\n");
1529         }
1530 }
1531
1532 static int amdgpu_dm_init(struct amdgpu_device *adev)
1533 {
1534         struct dc_init_data init_data;
1535         struct dc_callback_init init_params;
1536         int r;
1537
1538         adev->dm.ddev = adev_to_drm(adev);
1539         adev->dm.adev = adev;
1540
1541         /* Zero all the fields */
1542         memset(&init_data, 0, sizeof(init_data));
1543         memset(&init_params, 0, sizeof(init_params));
1544
1545         mutex_init(&adev->dm.dpia_aux_lock);
1546         mutex_init(&adev->dm.dc_lock);
1547         mutex_init(&adev->dm.audio_lock);
1548
1549         if(amdgpu_dm_irq_init(adev)) {
1550                 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
1551                 goto error;
1552         }
1553
1554         init_data.asic_id.chip_family = adev->family;
1555
1556         init_data.asic_id.pci_revision_id = adev->pdev->revision;
1557         init_data.asic_id.hw_internal_rev = adev->external_rev_id;
1558         init_data.asic_id.chip_id = adev->pdev->device;
1559
1560         init_data.asic_id.vram_width = adev->gmc.vram_width;
1561         /* TODO: initialize init_data.asic_id.vram_type here!!!! */
1562         init_data.asic_id.atombios_base_address =
1563                 adev->mode_info.atom_context->bios;
1564
1565         init_data.driver = adev;
1566
1567         adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
1568
1569         if (!adev->dm.cgs_device) {
1570                 DRM_ERROR("amdgpu: failed to create cgs device.\n");
1571                 goto error;
1572         }
1573
1574         init_data.cgs_device = adev->dm.cgs_device;
1575
1576         init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
1577
1578         switch (adev->ip_versions[DCE_HWIP][0]) {
1579         case IP_VERSION(2, 1, 0):
1580                 switch (adev->dm.dmcub_fw_version) {
1581                 case 0: /* development */
1582                 case 0x1: /* linux-firmware.git hash 6d9f399 */
1583                 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */
1584                         init_data.flags.disable_dmcu = false;
1585                         break;
1586                 default:
1587                         init_data.flags.disable_dmcu = true;
1588                 }
1589                 break;
1590         case IP_VERSION(2, 0, 3):
1591                 init_data.flags.disable_dmcu = true;
1592                 break;
1593         default:
1594                 break;
1595         }
1596
1597         switch (adev->asic_type) {
1598         case CHIP_CARRIZO:
1599         case CHIP_STONEY:
1600                 init_data.flags.gpu_vm_support = true;
1601                 break;
1602         default:
1603                 switch (adev->ip_versions[DCE_HWIP][0]) {
1604                 case IP_VERSION(1, 0, 0):
1605                 case IP_VERSION(1, 0, 1):
1606                         /* enable S/G on PCO and RV2 */
1607                         if ((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
1608                             (adev->apu_flags & AMD_APU_IS_PICASSO))
1609                                 init_data.flags.gpu_vm_support = true;
1610                         break;
1611                 case IP_VERSION(2, 1, 0):
1612                 case IP_VERSION(3, 0, 1):
1613                 case IP_VERSION(3, 1, 2):
1614                 case IP_VERSION(3, 1, 3):
1615                 case IP_VERSION(3, 1, 4):
1616                 case IP_VERSION(3, 1, 5):
1617                 case IP_VERSION(3, 1, 6):
1618                         init_data.flags.gpu_vm_support = true;
1619                         break;
1620                 default:
1621                         break;
1622                 }
1623                 break;
1624         }
1625         if (init_data.flags.gpu_vm_support &&
1626             (amdgpu_sg_display == 0))
1627                 init_data.flags.gpu_vm_support = false;
1628
1629         if (init_data.flags.gpu_vm_support)
1630                 adev->mode_info.gpu_vm_support = true;
1631
1632         if (amdgpu_dc_feature_mask & DC_FBC_MASK)
1633                 init_data.flags.fbc_support = true;
1634
1635         if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
1636                 init_data.flags.multi_mon_pp_mclk_switch = true;
1637
1638         if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
1639                 init_data.flags.disable_fractional_pwm = true;
1640
1641         if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING)
1642                 init_data.flags.edp_no_power_sequencing = true;
1643
1644         if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A)
1645                 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true;
1646         if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)
1647                 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;
1648
1649         /* Disable SubVP + DRR config by default */
1650         init_data.flags.disable_subvp_drr = true;
1651         if (amdgpu_dc_feature_mask & DC_ENABLE_SUBVP_DRR)
1652                 init_data.flags.disable_subvp_drr = false;
1653
1654         init_data.flags.seamless_boot_edp_requested = false;
1655
1656         if (check_seamless_boot_capability(adev)) {
1657                 init_data.flags.seamless_boot_edp_requested = true;
1658                 init_data.flags.allow_seamless_boot_optimization = true;
1659                 DRM_INFO("Seamless boot condition check passed\n");
1660         }
1661
1662         init_data.flags.enable_mipi_converter_optimization = true;
1663
1664         init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];
1665         init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];
1666
1667         INIT_LIST_HEAD(&adev->dm.da_list);
1668
1669         retrieve_dmi_info(&adev->dm);
1670
1671         /* Display Core create. */
1672         adev->dm.dc = dc_create(&init_data);
1673
1674         if (adev->dm.dc) {
1675                 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
1676         } else {
1677                 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
1678                 goto error;
1679         }
1680
1681         if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
1682                 adev->dm.dc->debug.force_single_disp_pipe_split = false;
1683                 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
1684         }
1685
1686         if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
1687                 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
1688         if (dm_should_disable_stutter(adev->pdev))
1689                 adev->dm.dc->debug.disable_stutter = true;
1690
1691         if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
1692                 adev->dm.dc->debug.disable_stutter = true;
1693
1694         if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) {
1695                 adev->dm.dc->debug.disable_dsc = true;
1696         }
1697
1698         if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
1699                 adev->dm.dc->debug.disable_clock_gate = true;
1700
1701         if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH)
1702                 adev->dm.dc->debug.force_subvp_mclk_switch = true;
1703
1704         adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm;
1705
1706         /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */
1707         adev->dm.dc->debug.ignore_cable_id = true;
1708
1709         /* TODO: There is a new drm mst change where the freedom of
1710          * vc_next_start_slot update is revoked/moved into drm, instead of in
1711          * driver. This forces us to make sure to get vc_next_start_slot updated
1712          * in drm function each time without considering if mst_state is active
1713          * or not. Otherwise, next time hotplug will give wrong start_slot
1714          * number. We are implementing a temporary solution to even notify drm
1715          * mst deallocation when link is no longer of MST type when uncommitting
1716          * the stream so we will have more time to work on a proper solution.
1717          * Ideally when dm_helpers_dp_mst_stop_top_mgr message is triggered, we
1718          * should notify drm to do a complete "reset" of its states and stop
1719          * calling further drm mst functions when link is no longer of an MST
1720          * type. This could happen when we unplug an MST hubs/displays. When
1721          * uncommit stream comes later after unplug, we should just reset
1722          * hardware states only.
1723          */
1724         adev->dm.dc->debug.temp_mst_deallocation_sequence = true;
1725
1726         if (adev->dm.dc->caps.dp_hdmi21_pcon_support)
1727                 DRM_INFO("DP-HDMI FRL PCON supported\n");
1728
1729         r = dm_dmub_hw_init(adev);
1730         if (r) {
1731                 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
1732                 goto error;
1733         }
1734
1735         dc_hardware_init(adev->dm.dc);
1736
1737         adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc);
1738         if (!adev->dm.hpd_rx_offload_wq) {
1739                 DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n");
1740                 goto error;
1741         }
1742
1743         if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) {
1744                 struct dc_phy_addr_space_config pa_config;
1745
1746                 mmhub_read_system_context(adev, &pa_config);
1747
1748                 // Call the DC init_memory func
1749                 dc_setup_system_context(adev->dm.dc, &pa_config);
1750         }
1751
1752         adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
1753         if (!adev->dm.freesync_module) {
1754                 DRM_ERROR(
1755                 "amdgpu: failed to initialize freesync_module.\n");
1756         } else
1757                 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
1758                                 adev->dm.freesync_module);
1759
1760         amdgpu_dm_init_color_mod();
1761
1762         if (adev->dm.dc->caps.max_links > 0) {
1763                 adev->dm.vblank_control_workqueue =
1764                         create_singlethread_workqueue("dm_vblank_control_workqueue");
1765                 if (!adev->dm.vblank_control_workqueue)
1766                         DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n");
1767         }
1768
1769         if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
1770                 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
1771
1772                 if (!adev->dm.hdcp_workqueue)
1773                         DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
1774                 else
1775                         DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
1776
1777                 dc_init_callbacks(adev->dm.dc, &init_params);
1778         }
1779 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1780         adev->dm.secure_display_ctxs = amdgpu_dm_crtc_secure_display_create_contexts(adev);
1781         if (!adev->dm.secure_display_ctxs) {
1782                 DRM_ERROR("amdgpu: failed to initialize secure_display_ctxs.\n");
1783         }
1784 #endif
1785         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
1786                 init_completion(&adev->dm.dmub_aux_transfer_done);
1787                 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL);
1788                 if (!adev->dm.dmub_notify) {
1789                         DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify");
1790                         goto error;
1791                 }
1792
1793                 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq");
1794                 if (!adev->dm.delayed_hpd_wq) {
1795                         DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n");
1796                         goto error;
1797                 }
1798
1799                 amdgpu_dm_outbox_init(adev);
1800                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY,
1801                         dmub_aux_setconfig_callback, false)) {
1802                         DRM_ERROR("amdgpu: fail to register dmub aux callback");
1803                         goto error;
1804                 }
1805                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true)) {
1806                         DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1807                         goto error;
1808                 }
1809                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true)) {
1810                         DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1811                         goto error;
1812                 }
1813         }
1814
1815         /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive.
1816          * It is expected that DMUB will resend any pending notifications at this point, for
1817          * example HPD from DPIA.
1818          */
1819         if (dc_is_dmub_outbox_supported(adev->dm.dc))
1820                 dc_enable_dmub_outbox(adev->dm.dc);
1821
1822         if (amdgpu_dm_initialize_drm_device(adev)) {
1823                 DRM_ERROR(
1824                 "amdgpu: failed to initialize sw for display support.\n");
1825                 goto error;
1826         }
1827
1828         /* create fake encoders for MST */
1829         dm_dp_create_fake_mst_encoders(adev);
1830
1831         /* TODO: Add_display_info? */
1832
1833         /* TODO use dynamic cursor width */
1834         adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
1835         adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
1836
1837         if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
1838                 DRM_ERROR(
1839                 "amdgpu: failed to initialize sw for display support.\n");
1840                 goto error;
1841         }
1842
1843
1844         DRM_DEBUG_DRIVER("KMS initialized.\n");
1845
1846         return 0;
1847 error:
1848         amdgpu_dm_fini(adev);
1849
1850         return -EINVAL;
1851 }
1852
1853 static int amdgpu_dm_early_fini(void *handle)
1854 {
1855         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1856
1857         amdgpu_dm_audio_fini(adev);
1858
1859         return 0;
1860 }
1861
1862 static void amdgpu_dm_fini(struct amdgpu_device *adev)
1863 {
1864         int i;
1865
1866         if (adev->dm.vblank_control_workqueue) {
1867                 destroy_workqueue(adev->dm.vblank_control_workqueue);
1868                 adev->dm.vblank_control_workqueue = NULL;
1869         }
1870
1871         amdgpu_dm_destroy_drm_device(&adev->dm);
1872
1873 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1874         if (adev->dm.secure_display_ctxs) {
1875                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1876                         if (adev->dm.secure_display_ctxs[i].crtc) {
1877                                 flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work);
1878                                 flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work);
1879                         }
1880                 }
1881                 kfree(adev->dm.secure_display_ctxs);
1882                 adev->dm.secure_display_ctxs = NULL;
1883         }
1884 #endif
1885         if (adev->dm.hdcp_workqueue) {
1886                 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue);
1887                 adev->dm.hdcp_workqueue = NULL;
1888         }
1889
1890         if (adev->dm.dc)
1891                 dc_deinit_callbacks(adev->dm.dc);
1892
1893         if (adev->dm.dc)
1894                 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
1895
1896         if (dc_enable_dmub_notifications(adev->dm.dc)) {
1897                 kfree(adev->dm.dmub_notify);
1898                 adev->dm.dmub_notify = NULL;
1899                 destroy_workqueue(adev->dm.delayed_hpd_wq);
1900                 adev->dm.delayed_hpd_wq = NULL;
1901         }
1902
1903         if (adev->dm.dmub_bo)
1904                 amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
1905                                       &adev->dm.dmub_bo_gpu_addr,
1906                                       &adev->dm.dmub_bo_cpu_addr);
1907
1908         if (adev->dm.hpd_rx_offload_wq) {
1909                 for (i = 0; i < adev->dm.dc->caps.max_links; i++) {
1910                         if (adev->dm.hpd_rx_offload_wq[i].wq) {
1911                                 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq);
1912                                 adev->dm.hpd_rx_offload_wq[i].wq = NULL;
1913                         }
1914                 }
1915
1916                 kfree(adev->dm.hpd_rx_offload_wq);
1917                 adev->dm.hpd_rx_offload_wq = NULL;
1918         }
1919
1920         /* DC Destroy TODO: Replace destroy DAL */
1921         if (adev->dm.dc)
1922                 dc_destroy(&adev->dm.dc);
1923         /*
1924          * TODO: pageflip, vlank interrupt
1925          *
1926          * amdgpu_dm_irq_fini(adev);
1927          */
1928
1929         if (adev->dm.cgs_device) {
1930                 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
1931                 adev->dm.cgs_device = NULL;
1932         }
1933         if (adev->dm.freesync_module) {
1934                 mod_freesync_destroy(adev->dm.freesync_module);
1935                 adev->dm.freesync_module = NULL;
1936         }
1937
1938         mutex_destroy(&adev->dm.audio_lock);
1939         mutex_destroy(&adev->dm.dc_lock);
1940         mutex_destroy(&adev->dm.dpia_aux_lock);
1941
1942         return;
1943 }
1944
1945 static int load_dmcu_fw(struct amdgpu_device *adev)
1946 {
1947         const char *fw_name_dmcu = NULL;
1948         int r;
1949         const struct dmcu_firmware_header_v1_0 *hdr;
1950
1951         switch(adev->asic_type) {
1952 #if defined(CONFIG_DRM_AMD_DC_SI)
1953         case CHIP_TAHITI:
1954         case CHIP_PITCAIRN:
1955         case CHIP_VERDE:
1956         case CHIP_OLAND:
1957 #endif
1958         case CHIP_BONAIRE:
1959         case CHIP_HAWAII:
1960         case CHIP_KAVERI:
1961         case CHIP_KABINI:
1962         case CHIP_MULLINS:
1963         case CHIP_TONGA:
1964         case CHIP_FIJI:
1965         case CHIP_CARRIZO:
1966         case CHIP_STONEY:
1967         case CHIP_POLARIS11:
1968         case CHIP_POLARIS10:
1969         case CHIP_POLARIS12:
1970         case CHIP_VEGAM:
1971         case CHIP_VEGA10:
1972         case CHIP_VEGA12:
1973         case CHIP_VEGA20:
1974                 return 0;
1975         case CHIP_NAVI12:
1976                 fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
1977                 break;
1978         case CHIP_RAVEN:
1979                 if (ASICREV_IS_PICASSO(adev->external_rev_id))
1980                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1981                 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
1982                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1983                 else
1984                         return 0;
1985                 break;
1986         default:
1987                 switch (adev->ip_versions[DCE_HWIP][0]) {
1988                 case IP_VERSION(2, 0, 2):
1989                 case IP_VERSION(2, 0, 3):
1990                 case IP_VERSION(2, 0, 0):
1991                 case IP_VERSION(2, 1, 0):
1992                 case IP_VERSION(3, 0, 0):
1993                 case IP_VERSION(3, 0, 2):
1994                 case IP_VERSION(3, 0, 3):
1995                 case IP_VERSION(3, 0, 1):
1996                 case IP_VERSION(3, 1, 2):
1997                 case IP_VERSION(3, 1, 3):
1998                 case IP_VERSION(3, 1, 4):
1999                 case IP_VERSION(3, 1, 5):
2000                 case IP_VERSION(3, 1, 6):
2001                 case IP_VERSION(3, 2, 0):
2002                 case IP_VERSION(3, 2, 1):
2003                         return 0;
2004                 default:
2005                         break;
2006                 }
2007                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2008                 return -EINVAL;
2009         }
2010
2011         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2012                 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
2013                 return 0;
2014         }
2015
2016         r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, fw_name_dmcu);
2017         if (r == -ENODEV) {
2018                 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
2019                 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
2020                 adev->dm.fw_dmcu = NULL;
2021                 return 0;
2022         }
2023         if (r) {
2024                 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
2025                         fw_name_dmcu);
2026                 amdgpu_ucode_release(&adev->dm.fw_dmcu);
2027                 return r;
2028         }
2029
2030         hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
2031         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
2032         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
2033         adev->firmware.fw_size +=
2034                 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2035
2036         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
2037         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
2038         adev->firmware.fw_size +=
2039                 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2040
2041         adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
2042
2043         DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
2044
2045         return 0;
2046 }
2047
2048 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
2049 {
2050         struct amdgpu_device *adev = ctx;
2051
2052         return dm_read_reg(adev->dm.dc->ctx, address);
2053 }
2054
2055 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
2056                                      uint32_t value)
2057 {
2058         struct amdgpu_device *adev = ctx;
2059
2060         return dm_write_reg(adev->dm.dc->ctx, address, value);
2061 }
2062
2063 static int dm_dmub_sw_init(struct amdgpu_device *adev)
2064 {
2065         struct dmub_srv_create_params create_params;
2066         struct dmub_srv_region_params region_params;
2067         struct dmub_srv_region_info region_info;
2068         struct dmub_srv_fb_params fb_params;
2069         struct dmub_srv_fb_info *fb_info;
2070         struct dmub_srv *dmub_srv;
2071         const struct dmcub_firmware_header_v1_0 *hdr;
2072         enum dmub_asic dmub_asic;
2073         enum dmub_status status;
2074         int r;
2075
2076         switch (adev->ip_versions[DCE_HWIP][0]) {
2077         case IP_VERSION(2, 1, 0):
2078                 dmub_asic = DMUB_ASIC_DCN21;
2079                 break;
2080         case IP_VERSION(3, 0, 0):
2081                 dmub_asic = DMUB_ASIC_DCN30;
2082                 break;
2083         case IP_VERSION(3, 0, 1):
2084                 dmub_asic = DMUB_ASIC_DCN301;
2085                 break;
2086         case IP_VERSION(3, 0, 2):
2087                 dmub_asic = DMUB_ASIC_DCN302;
2088                 break;
2089         case IP_VERSION(3, 0, 3):
2090                 dmub_asic = DMUB_ASIC_DCN303;
2091                 break;
2092         case IP_VERSION(3, 1, 2):
2093         case IP_VERSION(3, 1, 3):
2094                 dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31;
2095                 break;
2096         case IP_VERSION(3, 1, 4):
2097                 dmub_asic = DMUB_ASIC_DCN314;
2098                 break;
2099         case IP_VERSION(3, 1, 5):
2100                 dmub_asic = DMUB_ASIC_DCN315;
2101                 break;
2102         case IP_VERSION(3, 1, 6):
2103                 dmub_asic = DMUB_ASIC_DCN316;
2104                 break;
2105         case IP_VERSION(3, 2, 0):
2106                 dmub_asic = DMUB_ASIC_DCN32;
2107                 break;
2108         case IP_VERSION(3, 2, 1):
2109                 dmub_asic = DMUB_ASIC_DCN321;
2110                 break;
2111         default:
2112                 /* ASIC doesn't support DMUB. */
2113                 return 0;
2114         }
2115
2116         hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
2117         adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
2118
2119         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2120                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
2121                         AMDGPU_UCODE_ID_DMCUB;
2122                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw =
2123                         adev->dm.dmub_fw;
2124                 adev->firmware.fw_size +=
2125                         ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
2126
2127                 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
2128                          adev->dm.dmcub_fw_version);
2129         }
2130
2131
2132         adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
2133         dmub_srv = adev->dm.dmub_srv;
2134
2135         if (!dmub_srv) {
2136                 DRM_ERROR("Failed to allocate DMUB service!\n");
2137                 return -ENOMEM;
2138         }
2139
2140         memset(&create_params, 0, sizeof(create_params));
2141         create_params.user_ctx = adev;
2142         create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
2143         create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
2144         create_params.asic = dmub_asic;
2145
2146         /* Create the DMUB service. */
2147         status = dmub_srv_create(dmub_srv, &create_params);
2148         if (status != DMUB_STATUS_OK) {
2149                 DRM_ERROR("Error creating DMUB service: %d\n", status);
2150                 return -EINVAL;
2151         }
2152
2153         /* Calculate the size of all the regions for the DMUB service. */
2154         memset(&region_params, 0, sizeof(region_params));
2155
2156         region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
2157                                         PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
2158         region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
2159         region_params.vbios_size = adev->bios_size;
2160         region_params.fw_bss_data = region_params.bss_data_size ?
2161                 adev->dm.dmub_fw->data +
2162                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2163                 le32_to_cpu(hdr->inst_const_bytes) : NULL;
2164         region_params.fw_inst_const =
2165                 adev->dm.dmub_fw->data +
2166                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2167                 PSP_HEADER_BYTES;
2168
2169         status = dmub_srv_calc_region_info(dmub_srv, &region_params,
2170                                            &region_info);
2171
2172         if (status != DMUB_STATUS_OK) {
2173                 DRM_ERROR("Error calculating DMUB region info: %d\n", status);
2174                 return -EINVAL;
2175         }
2176
2177         /*
2178          * Allocate a framebuffer based on the total size of all the regions.
2179          * TODO: Move this into GART.
2180          */
2181         r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
2182                                     AMDGPU_GEM_DOMAIN_VRAM |
2183                                     AMDGPU_GEM_DOMAIN_GTT,
2184                                     &adev->dm.dmub_bo,
2185                                     &adev->dm.dmub_bo_gpu_addr,
2186                                     &adev->dm.dmub_bo_cpu_addr);
2187         if (r)
2188                 return r;
2189
2190         /* Rebase the regions on the framebuffer address. */
2191         memset(&fb_params, 0, sizeof(fb_params));
2192         fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr;
2193         fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr;
2194         fb_params.region_info = &region_info;
2195
2196         adev->dm.dmub_fb_info =
2197                 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);
2198         fb_info = adev->dm.dmub_fb_info;
2199
2200         if (!fb_info) {
2201                 DRM_ERROR(
2202                         "Failed to allocate framebuffer info for DMUB service!\n");
2203                 return -ENOMEM;
2204         }
2205
2206         status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info);
2207         if (status != DMUB_STATUS_OK) {
2208                 DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
2209                 return -EINVAL;
2210         }
2211
2212         return 0;
2213 }
2214
2215 static int dm_sw_init(void *handle)
2216 {
2217         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2218         int r;
2219
2220         r = dm_dmub_sw_init(adev);
2221         if (r)
2222                 return r;
2223
2224         return load_dmcu_fw(adev);
2225 }
2226
2227 static int dm_sw_fini(void *handle)
2228 {
2229         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2230
2231         kfree(adev->dm.dmub_fb_info);
2232         adev->dm.dmub_fb_info = NULL;
2233
2234         if (adev->dm.dmub_srv) {
2235                 dmub_srv_destroy(adev->dm.dmub_srv);
2236                 adev->dm.dmub_srv = NULL;
2237         }
2238
2239         amdgpu_ucode_release(&adev->dm.dmub_fw);
2240         amdgpu_ucode_release(&adev->dm.fw_dmcu);
2241
2242         return 0;
2243 }
2244
2245 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
2246 {
2247         struct amdgpu_dm_connector *aconnector;
2248         struct drm_connector *connector;
2249         struct drm_connector_list_iter iter;
2250         int ret = 0;
2251
2252         drm_connector_list_iter_begin(dev, &iter);
2253         drm_for_each_connector_iter(connector, &iter) {
2254                 aconnector = to_amdgpu_dm_connector(connector);
2255                 if (aconnector->dc_link->type == dc_connection_mst_branch &&
2256                     aconnector->mst_mgr.aux) {
2257                         DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
2258                                          aconnector,
2259                                          aconnector->base.base.id);
2260
2261                         ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
2262                         if (ret < 0) {
2263                                 DRM_ERROR("DM_MST: Failed to start MST\n");
2264                                 aconnector->dc_link->type =
2265                                         dc_connection_single;
2266                                 ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2267                                                                      aconnector->dc_link);
2268                                 break;
2269                         }
2270                 }
2271         }
2272         drm_connector_list_iter_end(&iter);
2273
2274         return ret;
2275 }
2276
2277 static int dm_late_init(void *handle)
2278 {
2279         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2280
2281         struct dmcu_iram_parameters params;
2282         unsigned int linear_lut[16];
2283         int i;
2284         struct dmcu *dmcu = NULL;
2285
2286         dmcu = adev->dm.dc->res_pool->dmcu;
2287
2288         for (i = 0; i < 16; i++)
2289                 linear_lut[i] = 0xFFFF * i / 15;
2290
2291         params.set = 0;
2292         params.backlight_ramping_override = false;
2293         params.backlight_ramping_start = 0xCCCC;
2294         params.backlight_ramping_reduction = 0xCCCCCCCC;
2295         params.backlight_lut_array_size = 16;
2296         params.backlight_lut_array = linear_lut;
2297
2298         /* Min backlight level after ABM reduction,  Don't allow below 1%
2299          * 0xFFFF x 0.01 = 0x28F
2300          */
2301         params.min_abm_backlight = 0x28F;
2302         /* In the case where abm is implemented on dmcub,
2303          * dmcu object will be null.
2304          * ABM 2.4 and up are implemented on dmcub.
2305          */
2306         if (dmcu) {
2307                 if (!dmcu_load_iram(dmcu, params))
2308                         return -EINVAL;
2309         } else if (adev->dm.dc->ctx->dmub_srv) {
2310                 struct dc_link *edp_links[MAX_NUM_EDP];
2311                 int edp_num;
2312
2313                 dc_get_edp_links(adev->dm.dc, edp_links, &edp_num);
2314                 for (i = 0; i < edp_num; i++) {
2315                         if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i))
2316                                 return -EINVAL;
2317                 }
2318         }
2319
2320         return detect_mst_link_for_all_connectors(adev_to_drm(adev));
2321 }
2322
2323 static void s3_handle_mst(struct drm_device *dev, bool suspend)
2324 {
2325         struct amdgpu_dm_connector *aconnector;
2326         struct drm_connector *connector;
2327         struct drm_connector_list_iter iter;
2328         struct drm_dp_mst_topology_mgr *mgr;
2329         int ret;
2330         bool need_hotplug = false;
2331
2332         drm_connector_list_iter_begin(dev, &iter);
2333         drm_for_each_connector_iter(connector, &iter) {
2334                 aconnector = to_amdgpu_dm_connector(connector);
2335                 if (aconnector->dc_link->type != dc_connection_mst_branch ||
2336                     aconnector->mst_root)
2337                         continue;
2338
2339                 mgr = &aconnector->mst_mgr;
2340
2341                 if (suspend) {
2342                         drm_dp_mst_topology_mgr_suspend(mgr);
2343                 } else {
2344                         /* if extended timeout is supported in hardware,
2345                          * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
2346                          * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
2347                          */
2348                         try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
2349                         if (!dp_is_lttpr_present(aconnector->dc_link))
2350                                 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
2351
2352                         ret = drm_dp_mst_topology_mgr_resume(mgr, true);
2353                         if (ret < 0) {
2354                                 dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2355                                         aconnector->dc_link);
2356                                 need_hotplug = true;
2357                         }
2358                 }
2359         }
2360         drm_connector_list_iter_end(&iter);
2361
2362         if (need_hotplug)
2363                 drm_kms_helper_hotplug_event(dev);
2364 }
2365
2366 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
2367 {
2368         int ret = 0;
2369
2370         /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
2371          * on window driver dc implementation.
2372          * For Navi1x, clock settings of dcn watermarks are fixed. the settings
2373          * should be passed to smu during boot up and resume from s3.
2374          * boot up: dc calculate dcn watermark clock settings within dc_create,
2375          * dcn20_resource_construct
2376          * then call pplib functions below to pass the settings to smu:
2377          * smu_set_watermarks_for_clock_ranges
2378          * smu_set_watermarks_table
2379          * navi10_set_watermarks_table
2380          * smu_write_watermarks_table
2381          *
2382          * For Renoir, clock settings of dcn watermark are also fixed values.
2383          * dc has implemented different flow for window driver:
2384          * dc_hardware_init / dc_set_power_state
2385          * dcn10_init_hw
2386          * notify_wm_ranges
2387          * set_wm_ranges
2388          * -- Linux
2389          * smu_set_watermarks_for_clock_ranges
2390          * renoir_set_watermarks_table
2391          * smu_write_watermarks_table
2392          *
2393          * For Linux,
2394          * dc_hardware_init -> amdgpu_dm_init
2395          * dc_set_power_state --> dm_resume
2396          *
2397          * therefore, this function apply to navi10/12/14 but not Renoir
2398          * *
2399          */
2400         switch (adev->ip_versions[DCE_HWIP][0]) {
2401         case IP_VERSION(2, 0, 2):
2402         case IP_VERSION(2, 0, 0):
2403                 break;
2404         default:
2405                 return 0;
2406         }
2407
2408         ret = amdgpu_dpm_write_watermarks_table(adev);
2409         if (ret) {
2410                 DRM_ERROR("Failed to update WMTABLE!\n");
2411                 return ret;
2412         }
2413
2414         return 0;
2415 }
2416
2417 /**
2418  * dm_hw_init() - Initialize DC device
2419  * @handle: The base driver device containing the amdgpu_dm device.
2420  *
2421  * Initialize the &struct amdgpu_display_manager device. This involves calling
2422  * the initializers of each DM component, then populating the struct with them.
2423  *
2424  * Although the function implies hardware initialization, both hardware and
2425  * software are initialized here. Splitting them out to their relevant init
2426  * hooks is a future TODO item.
2427  *
2428  * Some notable things that are initialized here:
2429  *
2430  * - Display Core, both software and hardware
2431  * - DC modules that we need (freesync and color management)
2432  * - DRM software states
2433  * - Interrupt sources and handlers
2434  * - Vblank support
2435  * - Debug FS entries, if enabled
2436  */
2437 static int dm_hw_init(void *handle)
2438 {
2439         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2440         /* Create DAL display manager */
2441         amdgpu_dm_init(adev);
2442         amdgpu_dm_hpd_init(adev);
2443
2444         return 0;
2445 }
2446
2447 /**
2448  * dm_hw_fini() - Teardown DC device
2449  * @handle: The base driver device containing the amdgpu_dm device.
2450  *
2451  * Teardown components within &struct amdgpu_display_manager that require
2452  * cleanup. This involves cleaning up the DRM device, DC, and any modules that
2453  * were loaded. Also flush IRQ workqueues and disable them.
2454  */
2455 static int dm_hw_fini(void *handle)
2456 {
2457         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2458
2459         amdgpu_dm_hpd_fini(adev);
2460
2461         amdgpu_dm_irq_fini(adev);
2462         amdgpu_dm_fini(adev);
2463         return 0;
2464 }
2465
2466
2467 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
2468                                  struct dc_state *state, bool enable)
2469 {
2470         enum dc_irq_source irq_source;
2471         struct amdgpu_crtc *acrtc;
2472         int rc = -EBUSY;
2473         int i = 0;
2474
2475         for (i = 0; i < state->stream_count; i++) {
2476                 acrtc = get_crtc_by_otg_inst(
2477                                 adev, state->stream_status[i].primary_otg_inst);
2478
2479                 if (acrtc && state->stream_status[i].plane_count != 0) {
2480                         irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst;
2481                         rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
2482                         if (rc)
2483                                 DRM_WARN("Failed to %s pflip interrupts\n",
2484                                          enable ? "enable" : "disable");
2485
2486                         if (enable) {
2487                                 if (amdgpu_dm_crtc_vrr_active(to_dm_crtc_state(acrtc->base.state)))
2488                                         rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, true);
2489                         } else
2490                                 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, false);
2491
2492                         if (rc)
2493                                 DRM_WARN("Failed to %sable vupdate interrupt\n", enable ? "en" : "dis");
2494
2495                         irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
2496                         /* During gpu-reset we disable and then enable vblank irq, so
2497                          * don't use amdgpu_irq_get/put() to avoid refcount change.
2498                          */
2499                         if (!dc_interrupt_set(adev->dm.dc, irq_source, enable))
2500                                 DRM_WARN("Failed to %sable vblank interrupt\n", enable ? "en" : "dis");
2501                 }
2502         }
2503
2504 }
2505
2506 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
2507 {
2508         struct dc_state *context = NULL;
2509         enum dc_status res = DC_ERROR_UNEXPECTED;
2510         int i;
2511         struct dc_stream_state *del_streams[MAX_PIPES];
2512         int del_streams_count = 0;
2513
2514         memset(del_streams, 0, sizeof(del_streams));
2515
2516         context = dc_create_state(dc);
2517         if (context == NULL)
2518                 goto context_alloc_fail;
2519
2520         dc_resource_state_copy_construct_current(dc, context);
2521
2522         /* First remove from context all streams */
2523         for (i = 0; i < context->stream_count; i++) {
2524                 struct dc_stream_state *stream = context->streams[i];
2525
2526                 del_streams[del_streams_count++] = stream;
2527         }
2528
2529         /* Remove all planes for removed streams and then remove the streams */
2530         for (i = 0; i < del_streams_count; i++) {
2531                 if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) {
2532                         res = DC_FAIL_DETACH_SURFACES;
2533                         goto fail;
2534                 }
2535
2536                 res = dc_remove_stream_from_ctx(dc, context, del_streams[i]);
2537                 if (res != DC_OK)
2538                         goto fail;
2539         }
2540
2541         res = dc_commit_streams(dc, context->streams, context->stream_count);
2542
2543 fail:
2544         dc_release_state(context);
2545
2546 context_alloc_fail:
2547         return res;
2548 }
2549
2550 static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm)
2551 {
2552         int i;
2553
2554         if (dm->hpd_rx_offload_wq) {
2555                 for (i = 0; i < dm->dc->caps.max_links; i++)
2556                         flush_workqueue(dm->hpd_rx_offload_wq[i].wq);
2557         }
2558 }
2559
2560 static int dm_suspend(void *handle)
2561 {
2562         struct amdgpu_device *adev = handle;
2563         struct amdgpu_display_manager *dm = &adev->dm;
2564         int ret = 0;
2565
2566         if (amdgpu_in_reset(adev)) {
2567                 mutex_lock(&dm->dc_lock);
2568
2569                 dc_allow_idle_optimizations(adev->dm.dc, false);
2570
2571                 dm->cached_dc_state = dc_copy_state(dm->dc->current_state);
2572
2573                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
2574
2575                 amdgpu_dm_commit_zero_streams(dm->dc);
2576
2577                 amdgpu_dm_irq_suspend(adev);
2578
2579                 hpd_rx_irq_work_suspend(dm);
2580
2581                 return ret;
2582         }
2583
2584         WARN_ON(adev->dm.cached_state);
2585         adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));
2586
2587         s3_handle_mst(adev_to_drm(adev), true);
2588
2589         amdgpu_dm_irq_suspend(adev);
2590
2591         hpd_rx_irq_work_suspend(dm);
2592
2593         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
2594
2595         return 0;
2596 }
2597
2598 struct amdgpu_dm_connector *
2599 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
2600                                              struct drm_crtc *crtc)
2601 {
2602         u32 i;
2603         struct drm_connector_state *new_con_state;
2604         struct drm_connector *connector;
2605         struct drm_crtc *crtc_from_state;
2606
2607         for_each_new_connector_in_state(state, connector, new_con_state, i) {
2608                 crtc_from_state = new_con_state->crtc;
2609
2610                 if (crtc_from_state == crtc)
2611                         return to_amdgpu_dm_connector(connector);
2612         }
2613
2614         return NULL;
2615 }
2616
2617 static void emulated_link_detect(struct dc_link *link)
2618 {
2619         struct dc_sink_init_data sink_init_data = { 0 };
2620         struct display_sink_capability sink_caps = { 0 };
2621         enum dc_edid_status edid_status;
2622         struct dc_context *dc_ctx = link->ctx;
2623         struct dc_sink *sink = NULL;
2624         struct dc_sink *prev_sink = NULL;
2625
2626         link->type = dc_connection_none;
2627         prev_sink = link->local_sink;
2628
2629         if (prev_sink)
2630                 dc_sink_release(prev_sink);
2631
2632         switch (link->connector_signal) {
2633         case SIGNAL_TYPE_HDMI_TYPE_A: {
2634                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2635                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
2636                 break;
2637         }
2638
2639         case SIGNAL_TYPE_DVI_SINGLE_LINK: {
2640                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2641                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
2642                 break;
2643         }
2644
2645         case SIGNAL_TYPE_DVI_DUAL_LINK: {
2646                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2647                 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
2648                 break;
2649         }
2650
2651         case SIGNAL_TYPE_LVDS: {
2652                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2653                 sink_caps.signal = SIGNAL_TYPE_LVDS;
2654                 break;
2655         }
2656
2657         case SIGNAL_TYPE_EDP: {
2658                 sink_caps.transaction_type =
2659                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2660                 sink_caps.signal = SIGNAL_TYPE_EDP;
2661                 break;
2662         }
2663
2664         case SIGNAL_TYPE_DISPLAY_PORT: {
2665                 sink_caps.transaction_type =
2666                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2667                 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
2668                 break;
2669         }
2670
2671         default:
2672                 DC_ERROR("Invalid connector type! signal:%d\n",
2673                         link->connector_signal);
2674                 return;
2675         }
2676
2677         sink_init_data.link = link;
2678         sink_init_data.sink_signal = sink_caps.signal;
2679
2680         sink = dc_sink_create(&sink_init_data);
2681         if (!sink) {
2682                 DC_ERROR("Failed to create sink!\n");
2683                 return;
2684         }
2685
2686         /* dc_sink_create returns a new reference */
2687         link->local_sink = sink;
2688
2689         edid_status = dm_helpers_read_local_edid(
2690                         link->ctx,
2691                         link,
2692                         sink);
2693
2694         if (edid_status != EDID_OK)
2695                 DC_ERROR("Failed to read EDID");
2696
2697 }
2698
2699 static void dm_gpureset_commit_state(struct dc_state *dc_state,
2700                                      struct amdgpu_display_manager *dm)
2701 {
2702         struct {
2703                 struct dc_surface_update surface_updates[MAX_SURFACES];
2704                 struct dc_plane_info plane_infos[MAX_SURFACES];
2705                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
2706                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
2707                 struct dc_stream_update stream_update;
2708         } * bundle;
2709         int k, m;
2710
2711         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
2712
2713         if (!bundle) {
2714                 dm_error("Failed to allocate update bundle\n");
2715                 goto cleanup;
2716         }
2717
2718         for (k = 0; k < dc_state->stream_count; k++) {
2719                 bundle->stream_update.stream = dc_state->streams[k];
2720
2721                 for (m = 0; m < dc_state->stream_status->plane_count; m++) {
2722                         bundle->surface_updates[m].surface =
2723                                 dc_state->stream_status->plane_states[m];
2724                         bundle->surface_updates[m].surface->force_full_update =
2725                                 true;
2726                 }
2727
2728                 update_planes_and_stream_adapter(dm->dc,
2729                                          UPDATE_TYPE_FULL,
2730                                          dc_state->stream_status->plane_count,
2731                                          dc_state->streams[k],
2732                                          &bundle->stream_update,
2733                                          bundle->surface_updates);
2734         }
2735
2736 cleanup:
2737         kfree(bundle);
2738
2739         return;
2740 }
2741
2742 static int dm_resume(void *handle)
2743 {
2744         struct amdgpu_device *adev = handle;
2745         struct drm_device *ddev = adev_to_drm(adev);
2746         struct amdgpu_display_manager *dm = &adev->dm;
2747         struct amdgpu_dm_connector *aconnector;
2748         struct drm_connector *connector;
2749         struct drm_connector_list_iter iter;
2750         struct drm_crtc *crtc;
2751         struct drm_crtc_state *new_crtc_state;
2752         struct dm_crtc_state *dm_new_crtc_state;
2753         struct drm_plane *plane;
2754         struct drm_plane_state *new_plane_state;
2755         struct dm_plane_state *dm_new_plane_state;
2756         struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
2757         enum dc_connection_type new_connection_type = dc_connection_none;
2758         struct dc_state *dc_state;
2759         int i, r, j;
2760
2761         if (amdgpu_in_reset(adev)) {
2762                 dc_state = dm->cached_dc_state;
2763
2764                 /*
2765                  * The dc->current_state is backed up into dm->cached_dc_state
2766                  * before we commit 0 streams.
2767                  *
2768                  * DC will clear link encoder assignments on the real state
2769                  * but the changes won't propagate over to the copy we made
2770                  * before the 0 streams commit.
2771                  *
2772                  * DC expects that link encoder assignments are *not* valid
2773                  * when committing a state, so as a workaround we can copy
2774                  * off of the current state.
2775                  *
2776                  * We lose the previous assignments, but we had already
2777                  * commit 0 streams anyway.
2778                  */
2779                 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state);
2780
2781                 r = dm_dmub_hw_init(adev);
2782                 if (r)
2783                         DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
2784
2785                 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2786                 dc_resume(dm->dc);
2787
2788                 amdgpu_dm_irq_resume_early(adev);
2789
2790                 for (i = 0; i < dc_state->stream_count; i++) {
2791                         dc_state->streams[i]->mode_changed = true;
2792                         for (j = 0; j < dc_state->stream_status[i].plane_count; j++) {
2793                                 dc_state->stream_status[i].plane_states[j]->update_flags.raw
2794                                         = 0xffffffff;
2795                         }
2796                 }
2797
2798                 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2799                         amdgpu_dm_outbox_init(adev);
2800                         dc_enable_dmub_outbox(adev->dm.dc);
2801                 }
2802
2803                 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
2804
2805                 dm_gpureset_commit_state(dm->cached_dc_state, dm);
2806
2807                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true);
2808
2809                 dc_release_state(dm->cached_dc_state);
2810                 dm->cached_dc_state = NULL;
2811
2812                 amdgpu_dm_irq_resume_late(adev);
2813
2814                 mutex_unlock(&dm->dc_lock);
2815
2816                 return 0;
2817         }
2818         /* Recreate dc_state - DC invalidates it when setting power state to S3. */
2819         dc_release_state(dm_state->context);
2820         dm_state->context = dc_create_state(dm->dc);
2821         /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
2822         dc_resource_state_construct(dm->dc, dm_state->context);
2823
2824         /* Before powering on DC we need to re-initialize DMUB. */
2825         dm_dmub_hw_resume(adev);
2826
2827         /* Re-enable outbox interrupts for DPIA. */
2828         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2829                 amdgpu_dm_outbox_init(adev);
2830                 dc_enable_dmub_outbox(adev->dm.dc);
2831         }
2832
2833         /* power on hardware */
2834         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2835
2836         /* program HPD filter */
2837         dc_resume(dm->dc);
2838
2839         /*
2840          * early enable HPD Rx IRQ, should be done before set mode as short
2841          * pulse interrupts are used for MST
2842          */
2843         amdgpu_dm_irq_resume_early(adev);
2844
2845         /* On resume we need to rewrite the MSTM control bits to enable MST*/
2846         s3_handle_mst(ddev, false);
2847
2848         /* Do detection*/
2849         drm_connector_list_iter_begin(ddev, &iter);
2850         drm_for_each_connector_iter(connector, &iter) {
2851                 aconnector = to_amdgpu_dm_connector(connector);
2852
2853                 if (!aconnector->dc_link)
2854                         continue;
2855
2856                 /*
2857                  * this is the case when traversing through already created
2858                  * MST connectors, should be skipped
2859                  */
2860                 if (aconnector && aconnector->mst_root)
2861                         continue;
2862
2863                 mutex_lock(&aconnector->hpd_lock);
2864                 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
2865                         DRM_ERROR("KMS: Failed to detect connector\n");
2866
2867                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2868                         emulated_link_detect(aconnector->dc_link);
2869                 } else {
2870                         mutex_lock(&dm->dc_lock);
2871                         dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
2872                         mutex_unlock(&dm->dc_lock);
2873                 }
2874
2875                 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
2876                         aconnector->fake_enable = false;
2877
2878                 if (aconnector->dc_sink)
2879                         dc_sink_release(aconnector->dc_sink);
2880                 aconnector->dc_sink = NULL;
2881                 amdgpu_dm_update_connector_after_detect(aconnector);
2882                 mutex_unlock(&aconnector->hpd_lock);
2883         }
2884         drm_connector_list_iter_end(&iter);
2885
2886         /* Force mode set in atomic commit */
2887         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
2888                 new_crtc_state->active_changed = true;
2889
2890         /*
2891          * atomic_check is expected to create the dc states. We need to release
2892          * them here, since they were duplicated as part of the suspend
2893          * procedure.
2894          */
2895         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
2896                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
2897                 if (dm_new_crtc_state->stream) {
2898                         WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
2899                         dc_stream_release(dm_new_crtc_state->stream);
2900                         dm_new_crtc_state->stream = NULL;
2901                 }
2902         }
2903
2904         for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
2905                 dm_new_plane_state = to_dm_plane_state(new_plane_state);
2906                 if (dm_new_plane_state->dc_state) {
2907                         WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
2908                         dc_plane_state_release(dm_new_plane_state->dc_state);
2909                         dm_new_plane_state->dc_state = NULL;
2910                 }
2911         }
2912
2913         drm_atomic_helper_resume(ddev, dm->cached_state);
2914
2915         dm->cached_state = NULL;
2916
2917         amdgpu_dm_irq_resume_late(adev);
2918
2919         amdgpu_dm_smu_write_watermarks_table(adev);
2920
2921         return 0;
2922 }
2923
2924 /**
2925  * DOC: DM Lifecycle
2926  *
2927  * DM (and consequently DC) is registered in the amdgpu base driver as a IP
2928  * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
2929  * the base driver's device list to be initialized and torn down accordingly.
2930  *
2931  * The functions to do so are provided as hooks in &struct amd_ip_funcs.
2932  */
2933
2934 static const struct amd_ip_funcs amdgpu_dm_funcs = {
2935         .name = "dm",
2936         .early_init = dm_early_init,
2937         .late_init = dm_late_init,
2938         .sw_init = dm_sw_init,
2939         .sw_fini = dm_sw_fini,
2940         .early_fini = amdgpu_dm_early_fini,
2941         .hw_init = dm_hw_init,
2942         .hw_fini = dm_hw_fini,
2943         .suspend = dm_suspend,
2944         .resume = dm_resume,
2945         .is_idle = dm_is_idle,
2946         .wait_for_idle = dm_wait_for_idle,
2947         .check_soft_reset = dm_check_soft_reset,
2948         .soft_reset = dm_soft_reset,
2949         .set_clockgating_state = dm_set_clockgating_state,
2950         .set_powergating_state = dm_set_powergating_state,
2951 };
2952
2953 const struct amdgpu_ip_block_version dm_ip_block =
2954 {
2955         .type = AMD_IP_BLOCK_TYPE_DCE,
2956         .major = 1,
2957         .minor = 0,
2958         .rev = 0,
2959         .funcs = &amdgpu_dm_funcs,
2960 };
2961
2962
2963 /**
2964  * DOC: atomic
2965  *
2966  * *WIP*
2967  */
2968
2969 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
2970         .fb_create = amdgpu_display_user_framebuffer_create,
2971         .get_format_info = amdgpu_dm_plane_get_format_info,
2972         .atomic_check = amdgpu_dm_atomic_check,
2973         .atomic_commit = drm_atomic_helper_commit,
2974 };
2975
2976 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
2977         .atomic_commit_tail = amdgpu_dm_atomic_commit_tail,
2978         .atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
2979 };
2980
2981 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
2982 {
2983         struct amdgpu_dm_backlight_caps *caps;
2984         struct drm_connector *conn_base;
2985         struct amdgpu_device *adev;
2986         struct drm_luminance_range_info *luminance_range;
2987
2988         if (aconnector->bl_idx == -1 ||
2989             aconnector->dc_link->connector_signal != SIGNAL_TYPE_EDP)
2990                 return;
2991
2992         conn_base = &aconnector->base;
2993         adev = drm_to_adev(conn_base->dev);
2994
2995         caps = &adev->dm.backlight_caps[aconnector->bl_idx];
2996         caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
2997         caps->aux_support = false;
2998
2999         if (caps->ext_caps->bits.oled == 1 /*||
3000             caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
3001             caps->ext_caps->bits.hdr_aux_backlight_control == 1*/)
3002                 caps->aux_support = true;
3003
3004         if (amdgpu_backlight == 0)
3005                 caps->aux_support = false;
3006         else if (amdgpu_backlight == 1)
3007                 caps->aux_support = true;
3008
3009         luminance_range = &conn_base->display_info.luminance_range;
3010
3011         if (luminance_range->max_luminance) {
3012                 caps->aux_min_input_signal = luminance_range->min_luminance;
3013                 caps->aux_max_input_signal = luminance_range->max_luminance;
3014         } else {
3015                 caps->aux_min_input_signal = 0;
3016                 caps->aux_max_input_signal = 512;
3017         }
3018 }
3019
3020 void amdgpu_dm_update_connector_after_detect(
3021                 struct amdgpu_dm_connector *aconnector)
3022 {
3023         struct drm_connector *connector = &aconnector->base;
3024         struct drm_device *dev = connector->dev;
3025         struct dc_sink *sink;
3026
3027         /* MST handled by drm_mst framework */
3028         if (aconnector->mst_mgr.mst_state == true)
3029                 return;
3030
3031         sink = aconnector->dc_link->local_sink;
3032         if (sink)
3033                 dc_sink_retain(sink);
3034
3035         /*
3036          * Edid mgmt connector gets first update only in mode_valid hook and then
3037          * the connector sink is set to either fake or physical sink depends on link status.
3038          * Skip if already done during boot.
3039          */
3040         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
3041                         && aconnector->dc_em_sink) {
3042
3043                 /*
3044                  * For S3 resume with headless use eml_sink to fake stream
3045                  * because on resume connector->sink is set to NULL
3046                  */
3047                 mutex_lock(&dev->mode_config.mutex);
3048
3049                 if (sink) {
3050                         if (aconnector->dc_sink) {
3051                                 amdgpu_dm_update_freesync_caps(connector, NULL);
3052                                 /*
3053                                  * retain and release below are used to
3054                                  * bump up refcount for sink because the link doesn't point
3055                                  * to it anymore after disconnect, so on next crtc to connector
3056                                  * reshuffle by UMD we will get into unwanted dc_sink release
3057                                  */
3058                                 dc_sink_release(aconnector->dc_sink);
3059                         }
3060                         aconnector->dc_sink = sink;
3061                         dc_sink_retain(aconnector->dc_sink);
3062                         amdgpu_dm_update_freesync_caps(connector,
3063                                         aconnector->edid);
3064                 } else {
3065                         amdgpu_dm_update_freesync_caps(connector, NULL);
3066                         if (!aconnector->dc_sink) {
3067                                 aconnector->dc_sink = aconnector->dc_em_sink;
3068                                 dc_sink_retain(aconnector->dc_sink);
3069                         }
3070                 }
3071
3072                 mutex_unlock(&dev->mode_config.mutex);
3073
3074                 if (sink)
3075                         dc_sink_release(sink);
3076                 return;
3077         }
3078
3079         /*
3080          * TODO: temporary guard to look for proper fix
3081          * if this sink is MST sink, we should not do anything
3082          */
3083         if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3084                 dc_sink_release(sink);
3085                 return;
3086         }
3087
3088         if (aconnector->dc_sink == sink) {
3089                 /*
3090                  * We got a DP short pulse (Link Loss, DP CTS, etc...).
3091                  * Do nothing!!
3092                  */
3093                 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
3094                                 aconnector->connector_id);
3095                 if (sink)
3096                         dc_sink_release(sink);
3097                 return;
3098         }
3099
3100         DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
3101                 aconnector->connector_id, aconnector->dc_sink, sink);
3102
3103         mutex_lock(&dev->mode_config.mutex);
3104
3105         /*
3106          * 1. Update status of the drm connector
3107          * 2. Send an event and let userspace tell us what to do
3108          */
3109         if (sink) {
3110                 /*
3111                  * TODO: check if we still need the S3 mode update workaround.
3112                  * If yes, put it here.
3113                  */
3114                 if (aconnector->dc_sink) {
3115                         amdgpu_dm_update_freesync_caps(connector, NULL);
3116                         dc_sink_release(aconnector->dc_sink);
3117                 }
3118
3119                 aconnector->dc_sink = sink;
3120                 dc_sink_retain(aconnector->dc_sink);
3121                 if (sink->dc_edid.length == 0) {
3122                         aconnector->edid = NULL;
3123                         if (aconnector->dc_link->aux_mode) {
3124                                 drm_dp_cec_unset_edid(
3125                                         &aconnector->dm_dp_aux.aux);
3126                         }
3127                 } else {
3128                         aconnector->edid =
3129                                 (struct edid *)sink->dc_edid.raw_edid;
3130
3131                         if (aconnector->dc_link->aux_mode)
3132                                 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
3133                                                     aconnector->edid);
3134                 }
3135
3136                 if (!aconnector->timing_requested) {
3137                         aconnector->timing_requested =
3138                                 kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL);
3139                         if (!aconnector->timing_requested)
3140                                 dm_error("failed to create aconnector->requested_timing\n");
3141                 }
3142
3143                 drm_connector_update_edid_property(connector, aconnector->edid);
3144                 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
3145                 update_connector_ext_caps(aconnector);
3146         } else {
3147                 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
3148                 amdgpu_dm_update_freesync_caps(connector, NULL);
3149                 drm_connector_update_edid_property(connector, NULL);
3150                 aconnector->num_modes = 0;
3151                 dc_sink_release(aconnector->dc_sink);
3152                 aconnector->dc_sink = NULL;
3153                 aconnector->edid = NULL;
3154                 kfree(aconnector->timing_requested);
3155                 aconnector->timing_requested = NULL;
3156                 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
3157                 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
3158                         connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
3159         }
3160
3161         mutex_unlock(&dev->mode_config.mutex);
3162
3163         update_subconnector_property(aconnector);
3164
3165         if (sink)
3166                 dc_sink_release(sink);
3167 }
3168
3169 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)
3170 {
3171         struct drm_connector *connector = &aconnector->base;
3172         struct drm_device *dev = connector->dev;
3173         enum dc_connection_type new_connection_type = dc_connection_none;
3174         struct amdgpu_device *adev = drm_to_adev(dev);
3175         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
3176         bool ret = false;
3177
3178         if (adev->dm.disable_hpd_irq)
3179                 return;
3180
3181         /*
3182          * In case of failure or MST no need to update connector status or notify the OS
3183          * since (for MST case) MST does this in its own context.
3184          */
3185         mutex_lock(&aconnector->hpd_lock);
3186
3187         if (adev->dm.hdcp_workqueue) {
3188                 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
3189                 dm_con_state->update_hdcp = true;
3190         }
3191         if (aconnector->fake_enable)
3192                 aconnector->fake_enable = false;
3193
3194         aconnector->timing_changed = false;
3195
3196         if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
3197                 DRM_ERROR("KMS: Failed to detect connector\n");
3198
3199         if (aconnector->base.force && new_connection_type == dc_connection_none) {
3200                 emulated_link_detect(aconnector->dc_link);
3201
3202                 drm_modeset_lock_all(dev);
3203                 dm_restore_drm_connector_state(dev, connector);
3204                 drm_modeset_unlock_all(dev);
3205
3206                 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3207                         drm_kms_helper_connector_hotplug_event(connector);
3208         } else {
3209                 mutex_lock(&adev->dm.dc_lock);
3210                 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3211                 mutex_unlock(&adev->dm.dc_lock);
3212                 if (ret) {
3213                         amdgpu_dm_update_connector_after_detect(aconnector);
3214
3215                         drm_modeset_lock_all(dev);
3216                         dm_restore_drm_connector_state(dev, connector);
3217                         drm_modeset_unlock_all(dev);
3218
3219                         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3220                                 drm_kms_helper_connector_hotplug_event(connector);
3221                 }
3222         }
3223         mutex_unlock(&aconnector->hpd_lock);
3224
3225 }
3226
3227 static void handle_hpd_irq(void *param)
3228 {
3229         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3230
3231         handle_hpd_irq_helper(aconnector);
3232
3233 }
3234
3235 static void dm_handle_mst_sideband_msg(struct amdgpu_dm_connector *aconnector)
3236 {
3237         u8 esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
3238         u8 dret;
3239         bool new_irq_handled = false;
3240         int dpcd_addr;
3241         int dpcd_bytes_to_read;
3242
3243         const int max_process_count = 30;
3244         int process_count = 0;
3245
3246         const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
3247
3248         if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
3249                 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
3250                 /* DPCD 0x200 - 0x201 for downstream IRQ */
3251                 dpcd_addr = DP_SINK_COUNT;
3252         } else {
3253                 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
3254                 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
3255                 dpcd_addr = DP_SINK_COUNT_ESI;
3256         }
3257
3258         dret = drm_dp_dpcd_read(
3259                 &aconnector->dm_dp_aux.aux,
3260                 dpcd_addr,
3261                 esi,
3262                 dpcd_bytes_to_read);
3263
3264         while (dret == dpcd_bytes_to_read &&
3265                 process_count < max_process_count) {
3266                 u8 retry;
3267                 dret = 0;
3268
3269                 process_count++;
3270
3271                 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3272                 /* handle HPD short pulse irq */
3273                 if (aconnector->mst_mgr.mst_state)
3274                         drm_dp_mst_hpd_irq(
3275                                 &aconnector->mst_mgr,
3276                                 esi,
3277                                 &new_irq_handled);
3278
3279                 if (new_irq_handled) {
3280                         /* ACK at DPCD to notify down stream */
3281                         const int ack_dpcd_bytes_to_write =
3282                                 dpcd_bytes_to_read - 1;
3283
3284                         for (retry = 0; retry < 3; retry++) {
3285                                 u8 wret;
3286
3287                                 wret = drm_dp_dpcd_write(
3288                                         &aconnector->dm_dp_aux.aux,
3289                                         dpcd_addr + 1,
3290                                         &esi[1],
3291                                         ack_dpcd_bytes_to_write);
3292                                 if (wret == ack_dpcd_bytes_to_write)
3293                                         break;
3294                         }
3295
3296                         /* check if there is new irq to be handled */
3297                         dret = drm_dp_dpcd_read(
3298                                 &aconnector->dm_dp_aux.aux,
3299                                 dpcd_addr,
3300                                 esi,
3301                                 dpcd_bytes_to_read);
3302
3303                         new_irq_handled = false;
3304                 } else {
3305                         break;
3306                 }
3307         }
3308
3309         if (process_count == max_process_count)
3310                 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
3311 }
3312
3313 static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq,
3314                                                         union hpd_irq_data hpd_irq_data)
3315 {
3316         struct hpd_rx_irq_offload_work *offload_work =
3317                                 kzalloc(sizeof(*offload_work), GFP_KERNEL);
3318
3319         if (!offload_work) {
3320                 DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n");
3321                 return;
3322         }
3323
3324         INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work);
3325         offload_work->data = hpd_irq_data;
3326         offload_work->offload_wq = offload_wq;
3327
3328         queue_work(offload_wq->wq, &offload_work->work);
3329         DRM_DEBUG_KMS("queue work to handle hpd_rx offload work");
3330 }
3331
3332 static void handle_hpd_rx_irq(void *param)
3333 {
3334         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3335         struct drm_connector *connector = &aconnector->base;
3336         struct drm_device *dev = connector->dev;
3337         struct dc_link *dc_link = aconnector->dc_link;
3338         bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
3339         bool result = false;
3340         enum dc_connection_type new_connection_type = dc_connection_none;
3341         struct amdgpu_device *adev = drm_to_adev(dev);
3342         union hpd_irq_data hpd_irq_data;
3343         bool link_loss = false;
3344         bool has_left_work = false;
3345         int idx = dc_link->link_index;
3346         struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx];
3347
3348         memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
3349
3350         if (adev->dm.disable_hpd_irq)
3351                 return;
3352
3353         /*
3354          * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
3355          * conflict, after implement i2c helper, this mutex should be
3356          * retired.
3357          */
3358         mutex_lock(&aconnector->hpd_lock);
3359
3360         result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data,
3361                                                 &link_loss, true, &has_left_work);
3362
3363         if (!has_left_work)
3364                 goto out;
3365
3366         if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3367                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3368                 goto out;
3369         }
3370
3371         if (dc_link_dp_allow_hpd_rx_irq(dc_link)) {
3372                 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
3373                         hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
3374                         dm_handle_mst_sideband_msg(aconnector);
3375                         goto out;
3376                 }
3377
3378                 if (link_loss) {
3379                         bool skip = false;
3380
3381                         spin_lock(&offload_wq->offload_lock);
3382                         skip = offload_wq->is_handling_link_loss;
3383
3384                         if (!skip)
3385                                 offload_wq->is_handling_link_loss = true;
3386
3387                         spin_unlock(&offload_wq->offload_lock);
3388
3389                         if (!skip)
3390                                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3391
3392                         goto out;
3393                 }
3394         }
3395
3396 out:
3397         if (result && !is_mst_root_connector) {
3398                 /* Downstream Port status changed. */
3399                 if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
3400                         DRM_ERROR("KMS: Failed to detect connector\n");
3401
3402                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3403                         emulated_link_detect(dc_link);
3404
3405                         if (aconnector->fake_enable)
3406                                 aconnector->fake_enable = false;
3407
3408                         amdgpu_dm_update_connector_after_detect(aconnector);
3409
3410
3411                         drm_modeset_lock_all(dev);
3412                         dm_restore_drm_connector_state(dev, connector);
3413                         drm_modeset_unlock_all(dev);
3414
3415                         drm_kms_helper_connector_hotplug_event(connector);
3416                 } else {
3417                         bool ret = false;
3418
3419                         mutex_lock(&adev->dm.dc_lock);
3420                         ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX);
3421                         mutex_unlock(&adev->dm.dc_lock);
3422
3423                         if (ret) {
3424                                 if (aconnector->fake_enable)
3425                                         aconnector->fake_enable = false;
3426
3427                                 amdgpu_dm_update_connector_after_detect(aconnector);
3428
3429                                 drm_modeset_lock_all(dev);
3430                                 dm_restore_drm_connector_state(dev, connector);
3431                                 drm_modeset_unlock_all(dev);
3432
3433                                 drm_kms_helper_connector_hotplug_event(connector);
3434                         }
3435                 }
3436         }
3437         if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
3438                 if (adev->dm.hdcp_workqueue)
3439                         hdcp_handle_cpirq(adev->dm.hdcp_workqueue,  aconnector->base.index);
3440         }
3441
3442         if (dc_link->type != dc_connection_mst_branch)
3443                 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
3444
3445         mutex_unlock(&aconnector->hpd_lock);
3446 }
3447
3448 static void register_hpd_handlers(struct amdgpu_device *adev)
3449 {
3450         struct drm_device *dev = adev_to_drm(adev);
3451         struct drm_connector *connector;
3452         struct amdgpu_dm_connector *aconnector;
3453         const struct dc_link *dc_link;
3454         struct dc_interrupt_params int_params = {0};
3455
3456         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3457         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3458
3459         list_for_each_entry(connector,
3460                         &dev->mode_config.connector_list, head) {
3461
3462                 aconnector = to_amdgpu_dm_connector(connector);
3463                 dc_link = aconnector->dc_link;
3464
3465                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
3466                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3467                         int_params.irq_source = dc_link->irq_source_hpd;
3468
3469                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
3470                                         handle_hpd_irq,
3471                                         (void *) aconnector);
3472                 }
3473
3474                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
3475
3476                         /* Also register for DP short pulse (hpd_rx). */
3477                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3478                         int_params.irq_source = dc_link->irq_source_hpd_rx;
3479
3480                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
3481                                         handle_hpd_rx_irq,
3482                                         (void *) aconnector);
3483
3484                         if (adev->dm.hpd_rx_offload_wq)
3485                                 adev->dm.hpd_rx_offload_wq[dc_link->link_index].aconnector =
3486                                         aconnector;
3487                 }
3488         }
3489 }
3490
3491 #if defined(CONFIG_DRM_AMD_DC_SI)
3492 /* Register IRQ sources and initialize IRQ callbacks */
3493 static int dce60_register_irq_handlers(struct amdgpu_device *adev)
3494 {
3495         struct dc *dc = adev->dm.dc;
3496         struct common_irq_params *c_irq_params;
3497         struct dc_interrupt_params int_params = {0};
3498         int r;
3499         int i;
3500         unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3501
3502         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3503         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3504
3505         /*
3506          * Actions of amdgpu_irq_add_id():
3507          * 1. Register a set() function with base driver.
3508          *    Base driver will call set() function to enable/disable an
3509          *    interrupt in DC hardware.
3510          * 2. Register amdgpu_dm_irq_handler().
3511          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3512          *    coming from DC hardware.
3513          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3514          *    for acknowledging and handling. */
3515
3516         /* Use VBLANK interrupt */
3517         for (i = 0; i < adev->mode_info.num_crtc; i++) {
3518                 r = amdgpu_irq_add_id(adev, client_id, i+1 , &adev->crtc_irq);
3519                 if (r) {
3520                         DRM_ERROR("Failed to add crtc irq id!\n");
3521                         return r;
3522                 }
3523
3524                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3525                 int_params.irq_source =
3526                         dc_interrupt_to_irq_source(dc, i+1 , 0);
3527
3528                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3529
3530                 c_irq_params->adev = adev;
3531                 c_irq_params->irq_src = int_params.irq_source;
3532
3533                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3534                                 dm_crtc_high_irq, c_irq_params);
3535         }
3536
3537         /* Use GRPH_PFLIP interrupt */
3538         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3539                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3540                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3541                 if (r) {
3542                         DRM_ERROR("Failed to add page flip irq id!\n");
3543                         return r;
3544                 }
3545
3546                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3547                 int_params.irq_source =
3548                         dc_interrupt_to_irq_source(dc, i, 0);
3549
3550                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3551
3552                 c_irq_params->adev = adev;
3553                 c_irq_params->irq_src = int_params.irq_source;
3554
3555                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3556                                 dm_pflip_high_irq, c_irq_params);
3557
3558         }
3559
3560         /* HPD */
3561         r = amdgpu_irq_add_id(adev, client_id,
3562                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3563         if (r) {
3564                 DRM_ERROR("Failed to add hpd irq id!\n");
3565                 return r;
3566         }
3567
3568         register_hpd_handlers(adev);
3569
3570         return 0;
3571 }
3572 #endif
3573
3574 /* Register IRQ sources and initialize IRQ callbacks */
3575 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
3576 {
3577         struct dc *dc = adev->dm.dc;
3578         struct common_irq_params *c_irq_params;
3579         struct dc_interrupt_params int_params = {0};
3580         int r;
3581         int i;
3582         unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3583
3584         if (adev->family >= AMDGPU_FAMILY_AI)
3585                 client_id = SOC15_IH_CLIENTID_DCE;
3586
3587         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3588         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3589
3590         /*
3591          * Actions of amdgpu_irq_add_id():
3592          * 1. Register a set() function with base driver.
3593          *    Base driver will call set() function to enable/disable an
3594          *    interrupt in DC hardware.
3595          * 2. Register amdgpu_dm_irq_handler().
3596          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3597          *    coming from DC hardware.
3598          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3599          *    for acknowledging and handling. */
3600
3601         /* Use VBLANK interrupt */
3602         for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
3603                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
3604                 if (r) {
3605                         DRM_ERROR("Failed to add crtc irq id!\n");
3606                         return r;
3607                 }
3608
3609                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3610                 int_params.irq_source =
3611                         dc_interrupt_to_irq_source(dc, i, 0);
3612
3613                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3614
3615                 c_irq_params->adev = adev;
3616                 c_irq_params->irq_src = int_params.irq_source;
3617
3618                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3619                                 dm_crtc_high_irq, c_irq_params);
3620         }
3621
3622         /* Use VUPDATE interrupt */
3623         for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
3624                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
3625                 if (r) {
3626                         DRM_ERROR("Failed to add vupdate irq id!\n");
3627                         return r;
3628                 }
3629
3630                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3631                 int_params.irq_source =
3632                         dc_interrupt_to_irq_source(dc, i, 0);
3633
3634                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3635
3636                 c_irq_params->adev = adev;
3637                 c_irq_params->irq_src = int_params.irq_source;
3638
3639                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3640                                 dm_vupdate_high_irq, c_irq_params);
3641         }
3642
3643         /* Use GRPH_PFLIP interrupt */
3644         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3645                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3646                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3647                 if (r) {
3648                         DRM_ERROR("Failed to add page flip irq id!\n");
3649                         return r;
3650                 }
3651
3652                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3653                 int_params.irq_source =
3654                         dc_interrupt_to_irq_source(dc, i, 0);
3655
3656                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3657
3658                 c_irq_params->adev = adev;
3659                 c_irq_params->irq_src = int_params.irq_source;
3660
3661                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3662                                 dm_pflip_high_irq, c_irq_params);
3663
3664         }
3665
3666         /* HPD */
3667         r = amdgpu_irq_add_id(adev, client_id,
3668                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3669         if (r) {
3670                 DRM_ERROR("Failed to add hpd irq id!\n");
3671                 return r;
3672         }
3673
3674         register_hpd_handlers(adev);
3675
3676         return 0;
3677 }
3678
3679 /* Register IRQ sources and initialize IRQ callbacks */
3680 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
3681 {
3682         struct dc *dc = adev->dm.dc;
3683         struct common_irq_params *c_irq_params;
3684         struct dc_interrupt_params int_params = {0};
3685         int r;
3686         int i;
3687 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3688         static const unsigned int vrtl_int_srcid[] = {
3689                 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL,
3690                 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL,
3691                 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL,
3692                 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL,
3693                 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL,
3694                 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL
3695         };
3696 #endif
3697
3698         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3699         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3700
3701         /*
3702          * Actions of amdgpu_irq_add_id():
3703          * 1. Register a set() function with base driver.
3704          *    Base driver will call set() function to enable/disable an
3705          *    interrupt in DC hardware.
3706          * 2. Register amdgpu_dm_irq_handler().
3707          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3708          *    coming from DC hardware.
3709          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3710          *    for acknowledging and handling.
3711          */
3712
3713         /* Use VSTARTUP interrupt */
3714         for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
3715                         i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
3716                         i++) {
3717                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
3718
3719                 if (r) {
3720                         DRM_ERROR("Failed to add crtc irq id!\n");
3721                         return r;
3722                 }
3723
3724                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3725                 int_params.irq_source =
3726                         dc_interrupt_to_irq_source(dc, i, 0);
3727
3728                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3729
3730                 c_irq_params->adev = adev;
3731                 c_irq_params->irq_src = int_params.irq_source;
3732
3733                 amdgpu_dm_irq_register_interrupt(
3734                         adev, &int_params, dm_crtc_high_irq, c_irq_params);
3735         }
3736
3737         /* Use otg vertical line interrupt */
3738 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3739         for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) {
3740                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE,
3741                                 vrtl_int_srcid[i], &adev->vline0_irq);
3742
3743                 if (r) {
3744                         DRM_ERROR("Failed to add vline0 irq id!\n");
3745                         return r;
3746                 }
3747
3748                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3749                 int_params.irq_source =
3750                         dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0);
3751
3752                 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) {
3753                         DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]);
3754                         break;
3755                 }
3756
3757                 c_irq_params = &adev->dm.vline0_params[int_params.irq_source
3758                                         - DC_IRQ_SOURCE_DC1_VLINE0];
3759
3760                 c_irq_params->adev = adev;
3761                 c_irq_params->irq_src = int_params.irq_source;
3762
3763                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3764                                 dm_dcn_vertical_interrupt0_high_irq, c_irq_params);
3765         }
3766 #endif
3767
3768         /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
3769          * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
3770          * to trigger at end of each vblank, regardless of state of the lock,
3771          * matching DCE behaviour.
3772          */
3773         for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
3774              i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
3775              i++) {
3776                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
3777
3778                 if (r) {
3779                         DRM_ERROR("Failed to add vupdate irq id!\n");
3780                         return r;
3781                 }
3782
3783                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3784                 int_params.irq_source =
3785                         dc_interrupt_to_irq_source(dc, i, 0);
3786
3787                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3788
3789                 c_irq_params->adev = adev;
3790                 c_irq_params->irq_src = int_params.irq_source;
3791
3792                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3793                                 dm_vupdate_high_irq, c_irq_params);
3794         }
3795
3796         /* Use GRPH_PFLIP interrupt */
3797         for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
3798                         i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1;
3799                         i++) {
3800                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
3801                 if (r) {
3802                         DRM_ERROR("Failed to add page flip irq id!\n");
3803                         return r;
3804                 }
3805
3806                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3807                 int_params.irq_source =
3808                         dc_interrupt_to_irq_source(dc, i, 0);
3809
3810                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3811
3812                 c_irq_params->adev = adev;
3813                 c_irq_params->irq_src = int_params.irq_source;
3814
3815                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3816                                 dm_pflip_high_irq, c_irq_params);
3817
3818         }
3819
3820         /* HPD */
3821         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
3822                         &adev->hpd_irq);
3823         if (r) {
3824                 DRM_ERROR("Failed to add hpd irq id!\n");
3825                 return r;
3826         }
3827
3828         register_hpd_handlers(adev);
3829
3830         return 0;
3831 }
3832 /* Register Outbox IRQ sources and initialize IRQ callbacks */
3833 static int register_outbox_irq_handlers(struct amdgpu_device *adev)
3834 {
3835         struct dc *dc = adev->dm.dc;
3836         struct common_irq_params *c_irq_params;
3837         struct dc_interrupt_params int_params = {0};
3838         int r, i;
3839
3840         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3841         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3842
3843         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT,
3844                         &adev->dmub_outbox_irq);
3845         if (r) {
3846                 DRM_ERROR("Failed to add outbox irq id!\n");
3847                 return r;
3848         }
3849
3850         if (dc->ctx->dmub_srv) {
3851                 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT;
3852                 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3853                 int_params.irq_source =
3854                 dc_interrupt_to_irq_source(dc, i, 0);
3855
3856                 c_irq_params = &adev->dm.dmub_outbox_params[0];
3857
3858                 c_irq_params->adev = adev;
3859                 c_irq_params->irq_src = int_params.irq_source;
3860
3861                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3862                                 dm_dmub_outbox1_low_irq, c_irq_params);
3863         }
3864
3865         return 0;
3866 }
3867
3868 /*
3869  * Acquires the lock for the atomic state object and returns
3870  * the new atomic state.
3871  *
3872  * This should only be called during atomic check.
3873  */
3874 int dm_atomic_get_state(struct drm_atomic_state *state,
3875                         struct dm_atomic_state **dm_state)
3876 {
3877         struct drm_device *dev = state->dev;
3878         struct amdgpu_device *adev = drm_to_adev(dev);
3879         struct amdgpu_display_manager *dm = &adev->dm;
3880         struct drm_private_state *priv_state;
3881
3882         if (*dm_state)
3883                 return 0;
3884
3885         priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
3886         if (IS_ERR(priv_state))
3887                 return PTR_ERR(priv_state);
3888
3889         *dm_state = to_dm_atomic_state(priv_state);
3890
3891         return 0;
3892 }
3893
3894 static struct dm_atomic_state *
3895 dm_atomic_get_new_state(struct drm_atomic_state *state)
3896 {
3897         struct drm_device *dev = state->dev;
3898         struct amdgpu_device *adev = drm_to_adev(dev);
3899         struct amdgpu_display_manager *dm = &adev->dm;
3900         struct drm_private_obj *obj;
3901         struct drm_private_state *new_obj_state;
3902         int i;
3903
3904         for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
3905                 if (obj->funcs == dm->atomic_obj.funcs)
3906                         return to_dm_atomic_state(new_obj_state);
3907         }
3908
3909         return NULL;
3910 }
3911
3912 static struct drm_private_state *
3913 dm_atomic_duplicate_state(struct drm_private_obj *obj)
3914 {
3915         struct dm_atomic_state *old_state, *new_state;
3916
3917         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
3918         if (!new_state)
3919                 return NULL;
3920
3921         __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
3922
3923         old_state = to_dm_atomic_state(obj->state);
3924
3925         if (old_state && old_state->context)
3926                 new_state->context = dc_copy_state(old_state->context);
3927
3928         if (!new_state->context) {
3929                 kfree(new_state);
3930                 return NULL;
3931         }
3932
3933         return &new_state->base;
3934 }
3935
3936 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
3937                                     struct drm_private_state *state)
3938 {
3939         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
3940
3941         if (dm_state && dm_state->context)
3942                 dc_release_state(dm_state->context);
3943
3944         kfree(dm_state);
3945 }
3946
3947 static struct drm_private_state_funcs dm_atomic_state_funcs = {
3948         .atomic_duplicate_state = dm_atomic_duplicate_state,
3949         .atomic_destroy_state = dm_atomic_destroy_state,
3950 };
3951
3952 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
3953 {
3954         struct dm_atomic_state *state;
3955         int r;
3956
3957         adev->mode_info.mode_config_initialized = true;
3958
3959         adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
3960         adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
3961
3962         adev_to_drm(adev)->mode_config.max_width = 16384;
3963         adev_to_drm(adev)->mode_config.max_height = 16384;
3964
3965         adev_to_drm(adev)->mode_config.preferred_depth = 24;
3966         if (adev->asic_type == CHIP_HAWAII)
3967                 /* disable prefer shadow for now due to hibernation issues */
3968                 adev_to_drm(adev)->mode_config.prefer_shadow = 0;
3969         else
3970                 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
3971         /* indicates support for immediate flip */
3972         adev_to_drm(adev)->mode_config.async_page_flip = true;
3973
3974         state = kzalloc(sizeof(*state), GFP_KERNEL);
3975         if (!state)
3976                 return -ENOMEM;
3977
3978         state->context = dc_create_state(adev->dm.dc);
3979         if (!state->context) {
3980                 kfree(state);
3981                 return -ENOMEM;
3982         }
3983
3984         dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
3985
3986         drm_atomic_private_obj_init(adev_to_drm(adev),
3987                                     &adev->dm.atomic_obj,
3988                                     &state->base,
3989                                     &dm_atomic_state_funcs);
3990
3991         r = amdgpu_display_modeset_create_props(adev);
3992         if (r) {
3993                 dc_release_state(state->context);
3994                 kfree(state);
3995                 return r;
3996         }
3997
3998         r = amdgpu_dm_audio_init(adev);
3999         if (r) {
4000                 dc_release_state(state->context);
4001                 kfree(state);
4002                 return r;
4003         }
4004
4005         return 0;
4006 }
4007
4008 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
4009 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
4010 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
4011
4012 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
4013                                             int bl_idx)
4014 {
4015 #if defined(CONFIG_ACPI)
4016         struct amdgpu_dm_backlight_caps caps;
4017
4018         memset(&caps, 0, sizeof(caps));
4019
4020         if (dm->backlight_caps[bl_idx].caps_valid)
4021                 return;
4022
4023         amdgpu_acpi_get_backlight_caps(&caps);
4024         if (caps.caps_valid) {
4025                 dm->backlight_caps[bl_idx].caps_valid = true;
4026                 if (caps.aux_support)
4027                         return;
4028                 dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal;
4029                 dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal;
4030         } else {
4031                 dm->backlight_caps[bl_idx].min_input_signal =
4032                                 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4033                 dm->backlight_caps[bl_idx].max_input_signal =
4034                                 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4035         }
4036 #else
4037         if (dm->backlight_caps[bl_idx].aux_support)
4038                 return;
4039
4040         dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4041         dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4042 #endif
4043 }
4044
4045 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
4046                                 unsigned *min, unsigned *max)
4047 {
4048         if (!caps)
4049                 return 0;
4050
4051         if (caps->aux_support) {
4052                 // Firmware limits are in nits, DC API wants millinits.
4053                 *max = 1000 * caps->aux_max_input_signal;
4054                 *min = 1000 * caps->aux_min_input_signal;
4055         } else {
4056                 // Firmware limits are 8-bit, PWM control is 16-bit.
4057                 *max = 0x101 * caps->max_input_signal;
4058                 *min = 0x101 * caps->min_input_signal;
4059         }
4060         return 1;
4061 }
4062
4063 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
4064                                         uint32_t brightness)
4065 {
4066         unsigned min, max;
4067
4068         if (!get_brightness_range(caps, &min, &max))
4069                 return brightness;
4070
4071         // Rescale 0..255 to min..max
4072         return min + DIV_ROUND_CLOSEST((max - min) * brightness,
4073                                        AMDGPU_MAX_BL_LEVEL);
4074 }
4075
4076 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
4077                                       uint32_t brightness)
4078 {
4079         unsigned min, max;
4080
4081         if (!get_brightness_range(caps, &min, &max))
4082                 return brightness;
4083
4084         if (brightness < min)
4085                 return 0;
4086         // Rescale min..max to 0..255
4087         return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),
4088                                  max - min);
4089 }
4090
4091 static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
4092                                          int bl_idx,
4093                                          u32 user_brightness)
4094 {
4095         struct amdgpu_dm_backlight_caps caps;
4096         struct dc_link *link;
4097         u32 brightness;
4098         bool rc;
4099
4100         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4101         caps = dm->backlight_caps[bl_idx];
4102
4103         dm->brightness[bl_idx] = user_brightness;
4104         /* update scratch register */
4105         if (bl_idx == 0)
4106                 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]);
4107         brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]);
4108         link = (struct dc_link *)dm->backlight_link[bl_idx];
4109
4110         /* Change brightness based on AUX property */
4111         if (caps.aux_support) {
4112                 rc = dc_link_set_backlight_level_nits(link, true, brightness,
4113                                                       AUX_BL_DEFAULT_TRANSITION_TIME_MS);
4114                 if (!rc)
4115                         DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx);
4116         } else {
4117                 rc = dc_link_set_backlight_level(link, brightness, 0);
4118                 if (!rc)
4119                         DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx);
4120         }
4121
4122         if (rc)
4123                 dm->actual_brightness[bl_idx] = user_brightness;
4124 }
4125
4126 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
4127 {
4128         struct amdgpu_display_manager *dm = bl_get_data(bd);
4129         int i;
4130
4131         for (i = 0; i < dm->num_of_edps; i++) {
4132                 if (bd == dm->backlight_dev[i])
4133                         break;
4134         }
4135         if (i >= AMDGPU_DM_MAX_NUM_EDP)
4136                 i = 0;
4137         amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness);
4138
4139         return 0;
4140 }
4141
4142 static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm,
4143                                          int bl_idx)
4144 {
4145         struct amdgpu_dm_backlight_caps caps;
4146         struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx];
4147
4148         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4149         caps = dm->backlight_caps[bl_idx];
4150
4151         if (caps.aux_support) {
4152                 u32 avg, peak;
4153                 bool rc;
4154
4155                 rc = dc_link_get_backlight_level_nits(link, &avg, &peak);
4156                 if (!rc)
4157                         return dm->brightness[bl_idx];
4158                 return convert_brightness_to_user(&caps, avg);
4159         } else {
4160                 int ret = dc_link_get_backlight_level(link);
4161
4162                 if (ret == DC_ERROR_UNEXPECTED)
4163                         return dm->brightness[bl_idx];
4164                 return convert_brightness_to_user(&caps, ret);
4165         }
4166 }
4167
4168 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
4169 {
4170         struct amdgpu_display_manager *dm = bl_get_data(bd);
4171         int i;
4172
4173         for (i = 0; i < dm->num_of_edps; i++) {
4174                 if (bd == dm->backlight_dev[i])
4175                         break;
4176         }
4177         if (i >= AMDGPU_DM_MAX_NUM_EDP)
4178                 i = 0;
4179         return amdgpu_dm_backlight_get_level(dm, i);
4180 }
4181
4182 static const struct backlight_ops amdgpu_dm_backlight_ops = {
4183         .options = BL_CORE_SUSPENDRESUME,
4184         .get_brightness = amdgpu_dm_backlight_get_brightness,
4185         .update_status  = amdgpu_dm_backlight_update_status,
4186 };
4187
4188 static void
4189 amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector)
4190 {
4191         struct drm_device *drm = aconnector->base.dev;
4192         struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm;
4193         struct backlight_properties props = { 0 };
4194         char bl_name[16];
4195
4196         if (aconnector->bl_idx == -1)
4197                 return;
4198
4199         if (!acpi_video_backlight_use_native()) {
4200                 drm_info(drm, "Skipping amdgpu DM backlight registration\n");
4201                 /* Try registering an ACPI video backlight device instead. */
4202                 acpi_video_register_backlight();
4203                 return;
4204         }
4205
4206         props.max_brightness = AMDGPU_MAX_BL_LEVEL;
4207         props.brightness = AMDGPU_MAX_BL_LEVEL;
4208         props.type = BACKLIGHT_RAW;
4209
4210         snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
4211                  drm->primary->index + aconnector->bl_idx);
4212
4213         dm->backlight_dev[aconnector->bl_idx] =
4214                 backlight_device_register(bl_name, aconnector->base.kdev, dm,
4215                                           &amdgpu_dm_backlight_ops, &props);
4216
4217         if (IS_ERR(dm->backlight_dev[aconnector->bl_idx])) {
4218                 DRM_ERROR("DM: Backlight registration failed!\n");
4219                 dm->backlight_dev[aconnector->bl_idx] = NULL;
4220         } else
4221                 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4222 }
4223
4224 static int initialize_plane(struct amdgpu_display_manager *dm,
4225                             struct amdgpu_mode_info *mode_info, int plane_id,
4226                             enum drm_plane_type plane_type,
4227                             const struct dc_plane_cap *plane_cap)
4228 {
4229         struct drm_plane *plane;
4230         unsigned long possible_crtcs;
4231         int ret = 0;
4232
4233         plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
4234         if (!plane) {
4235                 DRM_ERROR("KMS: Failed to allocate plane\n");
4236                 return -ENOMEM;
4237         }
4238         plane->type = plane_type;
4239
4240         /*
4241          * HACK: IGT tests expect that the primary plane for a CRTC
4242          * can only have one possible CRTC. Only expose support for
4243          * any CRTC if they're not going to be used as a primary plane
4244          * for a CRTC - like overlay or underlay planes.
4245          */
4246         possible_crtcs = 1 << plane_id;
4247         if (plane_id >= dm->dc->caps.max_streams)
4248                 possible_crtcs = 0xff;
4249
4250         ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
4251
4252         if (ret) {
4253                 DRM_ERROR("KMS: Failed to initialize plane\n");
4254                 kfree(plane);
4255                 return ret;
4256         }
4257
4258         if (mode_info)
4259                 mode_info->planes[plane_id] = plane;
4260
4261         return ret;
4262 }
4263
4264
4265 static void setup_backlight_device(struct amdgpu_display_manager *dm,
4266                                    struct amdgpu_dm_connector *aconnector)
4267 {
4268         struct dc_link *link = aconnector->dc_link;
4269         int bl_idx = dm->num_of_edps;
4270
4271         if (!(link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) ||
4272             link->type == dc_connection_none)
4273                 return;
4274
4275         if (dm->num_of_edps >= AMDGPU_DM_MAX_NUM_EDP) {
4276                 drm_warn(adev_to_drm(dm->adev), "Too much eDP connections, skipping backlight setup for additional eDPs\n");
4277                 return;
4278         }
4279
4280         aconnector->bl_idx = bl_idx;
4281
4282         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4283         dm->brightness[bl_idx] = AMDGPU_MAX_BL_LEVEL;
4284         dm->backlight_link[bl_idx] = link;
4285         dm->num_of_edps++;
4286
4287         update_connector_ext_caps(aconnector);
4288 }
4289
4290 static void amdgpu_set_panel_orientation(struct drm_connector *connector);
4291
4292 /*
4293  * In this architecture, the association
4294  * connector -> encoder -> crtc
4295  * id not really requried. The crtc and connector will hold the
4296  * display_index as an abstraction to use with DAL component
4297  *
4298  * Returns 0 on success
4299  */
4300 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4301 {
4302         struct amdgpu_display_manager *dm = &adev->dm;
4303         s32 i;
4304         struct amdgpu_dm_connector *aconnector = NULL;
4305         struct amdgpu_encoder *aencoder = NULL;
4306         struct amdgpu_mode_info *mode_info = &adev->mode_info;
4307         u32 link_cnt;
4308         s32 primary_planes;
4309         enum dc_connection_type new_connection_type = dc_connection_none;
4310         const struct dc_plane_cap *plane;
4311         bool psr_feature_enabled = false;
4312         int max_overlay = dm->dc->caps.max_slave_planes;
4313
4314         dm->display_indexes_num = dm->dc->caps.max_streams;
4315         /* Update the actual used number of crtc */
4316         adev->mode_info.num_crtc = adev->dm.display_indexes_num;
4317
4318         amdgpu_dm_set_irq_funcs(adev);
4319
4320         link_cnt = dm->dc->caps.max_links;
4321         if (amdgpu_dm_mode_config_init(dm->adev)) {
4322                 DRM_ERROR("DM: Failed to initialize mode config\n");
4323                 return -EINVAL;
4324         }
4325
4326         /* There is one primary plane per CRTC */
4327         primary_planes = dm->dc->caps.max_streams;
4328         ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
4329
4330         /*
4331          * Initialize primary planes, implicit planes for legacy IOCTLS.
4332          * Order is reversed to match iteration order in atomic check.
4333          */
4334         for (i = (primary_planes - 1); i >= 0; i--) {
4335                 plane = &dm->dc->caps.planes[i];
4336
4337                 if (initialize_plane(dm, mode_info, i,
4338                                      DRM_PLANE_TYPE_PRIMARY, plane)) {
4339                         DRM_ERROR("KMS: Failed to initialize primary plane\n");
4340                         goto fail;
4341                 }
4342         }
4343
4344         /*
4345          * Initialize overlay planes, index starting after primary planes.
4346          * These planes have a higher DRM index than the primary planes since
4347          * they should be considered as having a higher z-order.
4348          * Order is reversed to match iteration order in atomic check.
4349          *
4350          * Only support DCN for now, and only expose one so we don't encourage
4351          * userspace to use up all the pipes.
4352          */
4353         for (i = 0; i < dm->dc->caps.max_planes; ++i) {
4354                 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
4355
4356                 /* Do not create overlay if MPO disabled */
4357                 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO)
4358                         break;
4359
4360                 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
4361                         continue;
4362
4363                 if (!plane->pixel_format_support.argb8888)
4364                         continue;
4365
4366                 if (max_overlay-- == 0)
4367                         break;
4368
4369                 if (initialize_plane(dm, NULL, primary_planes + i,
4370                                      DRM_PLANE_TYPE_OVERLAY, plane)) {
4371                         DRM_ERROR("KMS: Failed to initialize overlay plane\n");
4372                         goto fail;
4373                 }
4374         }
4375
4376         for (i = 0; i < dm->dc->caps.max_streams; i++)
4377                 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
4378                         DRM_ERROR("KMS: Failed to initialize crtc\n");
4379                         goto fail;
4380                 }
4381
4382         /* Use Outbox interrupt */
4383         switch (adev->ip_versions[DCE_HWIP][0]) {
4384         case IP_VERSION(3, 0, 0):
4385         case IP_VERSION(3, 1, 2):
4386         case IP_VERSION(3, 1, 3):
4387         case IP_VERSION(3, 1, 4):
4388         case IP_VERSION(3, 1, 5):
4389         case IP_VERSION(3, 1, 6):
4390         case IP_VERSION(3, 2, 0):
4391         case IP_VERSION(3, 2, 1):
4392         case IP_VERSION(2, 1, 0):
4393                 if (register_outbox_irq_handlers(dm->adev)) {
4394                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4395                         goto fail;
4396                 }
4397                 break;
4398         default:
4399                 DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",
4400                               adev->ip_versions[DCE_HWIP][0]);
4401         }
4402
4403         /* Determine whether to enable PSR support by default. */
4404         if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) {
4405                 switch (adev->ip_versions[DCE_HWIP][0]) {
4406                 case IP_VERSION(3, 1, 2):
4407                 case IP_VERSION(3, 1, 3):
4408                 case IP_VERSION(3, 1, 4):
4409                 case IP_VERSION(3, 1, 5):
4410                 case IP_VERSION(3, 1, 6):
4411                 case IP_VERSION(3, 2, 0):
4412                 case IP_VERSION(3, 2, 1):
4413                         psr_feature_enabled = true;
4414                         break;
4415                 default:
4416                         psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK;
4417                         break;
4418                 }
4419         }
4420
4421         /* loops over all connectors on the board */
4422         for (i = 0; i < link_cnt; i++) {
4423                 struct dc_link *link = NULL;
4424
4425                 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
4426                         DRM_ERROR(
4427                                 "KMS: Cannot support more than %d display indexes\n",
4428                                         AMDGPU_DM_MAX_DISPLAY_INDEX);
4429                         continue;
4430                 }
4431
4432                 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
4433                 if (!aconnector)
4434                         goto fail;
4435
4436                 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
4437                 if (!aencoder)
4438                         goto fail;
4439
4440                 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
4441                         DRM_ERROR("KMS: Failed to initialize encoder\n");
4442                         goto fail;
4443                 }
4444
4445                 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
4446                         DRM_ERROR("KMS: Failed to initialize connector\n");
4447                         goto fail;
4448                 }
4449
4450                 link = dc_get_link_at_index(dm->dc, i);
4451
4452                 if (!dc_link_detect_connection_type(link, &new_connection_type))
4453                         DRM_ERROR("KMS: Failed to detect connector\n");
4454
4455                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
4456                         emulated_link_detect(link);
4457                         amdgpu_dm_update_connector_after_detect(aconnector);
4458                 } else {
4459                         bool ret = false;
4460
4461                         mutex_lock(&dm->dc_lock);
4462                         ret = dc_link_detect(link, DETECT_REASON_BOOT);
4463                         mutex_unlock(&dm->dc_lock);
4464
4465                         if (ret) {
4466                                 amdgpu_dm_update_connector_after_detect(aconnector);
4467                                 setup_backlight_device(dm, aconnector);
4468
4469                                 if (psr_feature_enabled)
4470                                         amdgpu_dm_set_psr_caps(link);
4471
4472                                 /* TODO: Fix vblank control helpers to delay PSR entry to allow this when
4473                                  * PSR is also supported.
4474                                  */
4475                                 if (link->psr_settings.psr_feature_enabled)
4476                                         adev_to_drm(adev)->vblank_disable_immediate = false;
4477                         }
4478                 }
4479                 amdgpu_set_panel_orientation(&aconnector->base);
4480         }
4481
4482         /* Software is initialized. Now we can register interrupt handlers. */
4483         switch (adev->asic_type) {
4484 #if defined(CONFIG_DRM_AMD_DC_SI)
4485         case CHIP_TAHITI:
4486         case CHIP_PITCAIRN:
4487         case CHIP_VERDE:
4488         case CHIP_OLAND:
4489                 if (dce60_register_irq_handlers(dm->adev)) {
4490                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4491                         goto fail;
4492                 }
4493                 break;
4494 #endif
4495         case CHIP_BONAIRE:
4496         case CHIP_HAWAII:
4497         case CHIP_KAVERI:
4498         case CHIP_KABINI:
4499         case CHIP_MULLINS:
4500         case CHIP_TONGA:
4501         case CHIP_FIJI:
4502         case CHIP_CARRIZO:
4503         case CHIP_STONEY:
4504         case CHIP_POLARIS11:
4505         case CHIP_POLARIS10:
4506         case CHIP_POLARIS12:
4507         case CHIP_VEGAM:
4508         case CHIP_VEGA10:
4509         case CHIP_VEGA12:
4510         case CHIP_VEGA20:
4511                 if (dce110_register_irq_handlers(dm->adev)) {
4512                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4513                         goto fail;
4514                 }
4515                 break;
4516         default:
4517                 switch (adev->ip_versions[DCE_HWIP][0]) {
4518                 case IP_VERSION(1, 0, 0):
4519                 case IP_VERSION(1, 0, 1):
4520                 case IP_VERSION(2, 0, 2):
4521                 case IP_VERSION(2, 0, 3):
4522                 case IP_VERSION(2, 0, 0):
4523                 case IP_VERSION(2, 1, 0):
4524                 case IP_VERSION(3, 0, 0):
4525                 case IP_VERSION(3, 0, 2):
4526                 case IP_VERSION(3, 0, 3):
4527                 case IP_VERSION(3, 0, 1):
4528                 case IP_VERSION(3, 1, 2):
4529                 case IP_VERSION(3, 1, 3):
4530                 case IP_VERSION(3, 1, 4):
4531                 case IP_VERSION(3, 1, 5):
4532                 case IP_VERSION(3, 1, 6):
4533                 case IP_VERSION(3, 2, 0):
4534                 case IP_VERSION(3, 2, 1):
4535                         if (dcn10_register_irq_handlers(dm->adev)) {
4536                                 DRM_ERROR("DM: Failed to initialize IRQ\n");
4537                                 goto fail;
4538                         }
4539                         break;
4540                 default:
4541                         DRM_ERROR("Unsupported DCE IP versions: 0x%X\n",
4542                                         adev->ip_versions[DCE_HWIP][0]);
4543                         goto fail;
4544                 }
4545                 break;
4546         }
4547
4548         return 0;
4549 fail:
4550         kfree(aencoder);
4551         kfree(aconnector);
4552
4553         return -EINVAL;
4554 }
4555
4556 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4557 {
4558         drm_atomic_private_obj_fini(&dm->atomic_obj);
4559         return;
4560 }
4561
4562 /******************************************************************************
4563  * amdgpu_display_funcs functions
4564  *****************************************************************************/
4565
4566 /*
4567  * dm_bandwidth_update - program display watermarks
4568  *
4569  * @adev: amdgpu_device pointer
4570  *
4571  * Calculate and program the display watermarks and line buffer allocation.
4572  */
4573 static void dm_bandwidth_update(struct amdgpu_device *adev)
4574 {
4575         /* TODO: implement later */
4576 }
4577
4578 static const struct amdgpu_display_funcs dm_display_funcs = {
4579         .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
4580         .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
4581         .backlight_set_level = NULL, /* never called for DC */
4582         .backlight_get_level = NULL, /* never called for DC */
4583         .hpd_sense = NULL,/* called unconditionally */
4584         .hpd_set_polarity = NULL, /* called unconditionally */
4585         .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4586         .page_flip_get_scanoutpos =
4587                 dm_crtc_get_scanoutpos,/* called unconditionally */
4588         .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
4589         .add_connector = NULL, /* VBIOS parsing. DAL does it. */
4590 };
4591
4592 #if defined(CONFIG_DEBUG_KERNEL_DC)
4593
4594 static ssize_t s3_debug_store(struct device *device,
4595                               struct device_attribute *attr,
4596                               const char *buf,
4597                               size_t count)
4598 {
4599         int ret;
4600         int s3_state;
4601         struct drm_device *drm_dev = dev_get_drvdata(device);
4602         struct amdgpu_device *adev = drm_to_adev(drm_dev);
4603
4604         ret = kstrtoint(buf, 0, &s3_state);
4605
4606         if (ret == 0) {
4607                 if (s3_state) {
4608                         dm_resume(adev);
4609                         drm_kms_helper_hotplug_event(adev_to_drm(adev));
4610                 } else
4611                         dm_suspend(adev);
4612         }
4613
4614         return ret == 0 ? count : 0;
4615 }
4616
4617 DEVICE_ATTR_WO(s3_debug);
4618
4619 #endif
4620
4621 static int dm_init_microcode(struct amdgpu_device *adev)
4622 {
4623         char *fw_name_dmub;
4624         int r;
4625
4626         switch (adev->ip_versions[DCE_HWIP][0]) {
4627         case IP_VERSION(2, 1, 0):
4628                 fw_name_dmub = FIRMWARE_RENOIR_DMUB;
4629                 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
4630                         fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
4631                 break;
4632         case IP_VERSION(3, 0, 0):
4633                 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
4634                         fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
4635                 else
4636                         fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
4637                 break;
4638         case IP_VERSION(3, 0, 1):
4639                 fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
4640                 break;
4641         case IP_VERSION(3, 0, 2):
4642                 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
4643                 break;
4644         case IP_VERSION(3, 0, 3):
4645                 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;
4646                 break;
4647         case IP_VERSION(3, 1, 2):
4648         case IP_VERSION(3, 1, 3):
4649                 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
4650                 break;
4651         case IP_VERSION(3, 1, 4):
4652                 fw_name_dmub = FIRMWARE_DCN_314_DMUB;
4653                 break;
4654         case IP_VERSION(3, 1, 5):
4655                 fw_name_dmub = FIRMWARE_DCN_315_DMUB;
4656                 break;
4657         case IP_VERSION(3, 1, 6):
4658                 fw_name_dmub = FIRMWARE_DCN316_DMUB;
4659                 break;
4660         case IP_VERSION(3, 2, 0):
4661                 fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB;
4662                 break;
4663         case IP_VERSION(3, 2, 1):
4664                 fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB;
4665                 break;
4666         default:
4667                 /* ASIC doesn't support DMUB. */
4668                 return 0;
4669         }
4670         r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, fw_name_dmub);
4671         if (r)
4672                 DRM_ERROR("DMUB firmware loading failed: %d\n", r);
4673         return r;
4674 }
4675
4676 static int dm_early_init(void *handle)
4677 {
4678         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4679         struct amdgpu_mode_info *mode_info = &adev->mode_info;
4680         struct atom_context *ctx = mode_info->atom_context;
4681         int index = GetIndexIntoMasterTable(DATA, Object_Header);
4682         u16 data_offset;
4683
4684         /* if there is no object header, skip DM */
4685         if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
4686                 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
4687                 dev_info(adev->dev, "No object header, skipping DM\n");
4688                 return -ENOENT;
4689         }
4690
4691         switch (adev->asic_type) {
4692 #if defined(CONFIG_DRM_AMD_DC_SI)
4693         case CHIP_TAHITI:
4694         case CHIP_PITCAIRN:
4695         case CHIP_VERDE:
4696                 adev->mode_info.num_crtc = 6;
4697                 adev->mode_info.num_hpd = 6;
4698                 adev->mode_info.num_dig = 6;
4699                 break;
4700         case CHIP_OLAND:
4701                 adev->mode_info.num_crtc = 2;
4702                 adev->mode_info.num_hpd = 2;
4703                 adev->mode_info.num_dig = 2;
4704                 break;
4705 #endif
4706         case CHIP_BONAIRE:
4707         case CHIP_HAWAII:
4708                 adev->mode_info.num_crtc = 6;
4709                 adev->mode_info.num_hpd = 6;
4710                 adev->mode_info.num_dig = 6;
4711                 break;
4712         case CHIP_KAVERI:
4713                 adev->mode_info.num_crtc = 4;
4714                 adev->mode_info.num_hpd = 6;
4715                 adev->mode_info.num_dig = 7;
4716                 break;
4717         case CHIP_KABINI:
4718         case CHIP_MULLINS:
4719                 adev->mode_info.num_crtc = 2;
4720                 adev->mode_info.num_hpd = 6;
4721                 adev->mode_info.num_dig = 6;
4722                 break;
4723         case CHIP_FIJI:
4724         case CHIP_TONGA:
4725                 adev->mode_info.num_crtc = 6;
4726                 adev->mode_info.num_hpd = 6;
4727                 adev->mode_info.num_dig = 7;
4728                 break;
4729         case CHIP_CARRIZO:
4730                 adev->mode_info.num_crtc = 3;
4731                 adev->mode_info.num_hpd = 6;
4732                 adev->mode_info.num_dig = 9;
4733                 break;
4734         case CHIP_STONEY:
4735                 adev->mode_info.num_crtc = 2;
4736                 adev->mode_info.num_hpd = 6;
4737                 adev->mode_info.num_dig = 9;
4738                 break;
4739         case CHIP_POLARIS11:
4740         case CHIP_POLARIS12:
4741                 adev->mode_info.num_crtc = 5;
4742                 adev->mode_info.num_hpd = 5;
4743                 adev->mode_info.num_dig = 5;
4744                 break;
4745         case CHIP_POLARIS10:
4746         case CHIP_VEGAM:
4747                 adev->mode_info.num_crtc = 6;
4748                 adev->mode_info.num_hpd = 6;
4749                 adev->mode_info.num_dig = 6;
4750                 break;
4751         case CHIP_VEGA10:
4752         case CHIP_VEGA12:
4753         case CHIP_VEGA20:
4754                 adev->mode_info.num_crtc = 6;
4755                 adev->mode_info.num_hpd = 6;
4756                 adev->mode_info.num_dig = 6;
4757                 break;
4758         default:
4759
4760                 switch (adev->ip_versions[DCE_HWIP][0]) {
4761                 case IP_VERSION(2, 0, 2):
4762                 case IP_VERSION(3, 0, 0):
4763                         adev->mode_info.num_crtc = 6;
4764                         adev->mode_info.num_hpd = 6;
4765                         adev->mode_info.num_dig = 6;
4766                         break;
4767                 case IP_VERSION(2, 0, 0):
4768                 case IP_VERSION(3, 0, 2):
4769                         adev->mode_info.num_crtc = 5;
4770                         adev->mode_info.num_hpd = 5;
4771                         adev->mode_info.num_dig = 5;
4772                         break;
4773                 case IP_VERSION(2, 0, 3):
4774                 case IP_VERSION(3, 0, 3):
4775                         adev->mode_info.num_crtc = 2;
4776                         adev->mode_info.num_hpd = 2;
4777                         adev->mode_info.num_dig = 2;
4778                         break;
4779                 case IP_VERSION(1, 0, 0):
4780                 case IP_VERSION(1, 0, 1):
4781                 case IP_VERSION(3, 0, 1):
4782                 case IP_VERSION(2, 1, 0):
4783                 case IP_VERSION(3, 1, 2):
4784                 case IP_VERSION(3, 1, 3):
4785                 case IP_VERSION(3, 1, 4):
4786                 case IP_VERSION(3, 1, 5):
4787                 case IP_VERSION(3, 1, 6):
4788                 case IP_VERSION(3, 2, 0):
4789                 case IP_VERSION(3, 2, 1):
4790                         adev->mode_info.num_crtc = 4;
4791                         adev->mode_info.num_hpd = 4;
4792                         adev->mode_info.num_dig = 4;
4793                         break;
4794                 default:
4795                         DRM_ERROR("Unsupported DCE IP versions: 0x%x\n",
4796                                         adev->ip_versions[DCE_HWIP][0]);
4797                         return -EINVAL;
4798                 }
4799                 break;
4800         }
4801
4802         if (adev->mode_info.funcs == NULL)
4803                 adev->mode_info.funcs = &dm_display_funcs;
4804
4805         /*
4806          * Note: Do NOT change adev->audio_endpt_rreg and
4807          * adev->audio_endpt_wreg because they are initialised in
4808          * amdgpu_device_init()
4809          */
4810 #if defined(CONFIG_DEBUG_KERNEL_DC)
4811         device_create_file(
4812                 adev_to_drm(adev)->dev,
4813                 &dev_attr_s3_debug);
4814 #endif
4815         adev->dc_enabled = true;
4816
4817         return dm_init_microcode(adev);
4818 }
4819
4820 static bool modereset_required(struct drm_crtc_state *crtc_state)
4821 {
4822         return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
4823 }
4824
4825 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
4826 {
4827         drm_encoder_cleanup(encoder);
4828         kfree(encoder);
4829 }
4830
4831 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
4832         .destroy = amdgpu_dm_encoder_destroy,
4833 };
4834
4835 static int
4836 fill_plane_color_attributes(const struct drm_plane_state *plane_state,
4837                             const enum surface_pixel_format format,
4838                             enum dc_color_space *color_space)
4839 {
4840         bool full_range;
4841
4842         *color_space = COLOR_SPACE_SRGB;
4843
4844         /* DRM color properties only affect non-RGB formats. */
4845         if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
4846                 return 0;
4847
4848         full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
4849
4850         switch (plane_state->color_encoding) {
4851         case DRM_COLOR_YCBCR_BT601:
4852                 if (full_range)
4853                         *color_space = COLOR_SPACE_YCBCR601;
4854                 else
4855                         *color_space = COLOR_SPACE_YCBCR601_LIMITED;
4856                 break;
4857
4858         case DRM_COLOR_YCBCR_BT709:
4859                 if (full_range)
4860                         *color_space = COLOR_SPACE_YCBCR709;
4861                 else
4862                         *color_space = COLOR_SPACE_YCBCR709_LIMITED;
4863                 break;
4864
4865         case DRM_COLOR_YCBCR_BT2020:
4866                 if (full_range)
4867                         *color_space = COLOR_SPACE_2020_YCBCR;
4868                 else
4869                         return -EINVAL;
4870                 break;
4871
4872         default:
4873                 return -EINVAL;
4874         }
4875
4876         return 0;
4877 }
4878
4879 static int
4880 fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
4881                             const struct drm_plane_state *plane_state,
4882                             const u64 tiling_flags,
4883                             struct dc_plane_info *plane_info,
4884                             struct dc_plane_address *address,
4885                             bool tmz_surface,
4886                             bool force_disable_dcc)
4887 {
4888         const struct drm_framebuffer *fb = plane_state->fb;
4889         const struct amdgpu_framebuffer *afb =
4890                 to_amdgpu_framebuffer(plane_state->fb);
4891         int ret;
4892
4893         memset(plane_info, 0, sizeof(*plane_info));
4894
4895         switch (fb->format->format) {
4896         case DRM_FORMAT_C8:
4897                 plane_info->format =
4898                         SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
4899                 break;
4900         case DRM_FORMAT_RGB565:
4901                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
4902                 break;
4903         case DRM_FORMAT_XRGB8888:
4904         case DRM_FORMAT_ARGB8888:
4905                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
4906                 break;
4907         case DRM_FORMAT_XRGB2101010:
4908         case DRM_FORMAT_ARGB2101010:
4909                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
4910                 break;
4911         case DRM_FORMAT_XBGR2101010:
4912         case DRM_FORMAT_ABGR2101010:
4913                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
4914                 break;
4915         case DRM_FORMAT_XBGR8888:
4916         case DRM_FORMAT_ABGR8888:
4917                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
4918                 break;
4919         case DRM_FORMAT_NV21:
4920                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
4921                 break;
4922         case DRM_FORMAT_NV12:
4923                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
4924                 break;
4925         case DRM_FORMAT_P010:
4926                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb;
4927                 break;
4928         case DRM_FORMAT_XRGB16161616F:
4929         case DRM_FORMAT_ARGB16161616F:
4930                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F;
4931                 break;
4932         case DRM_FORMAT_XBGR16161616F:
4933         case DRM_FORMAT_ABGR16161616F:
4934                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;
4935                 break;
4936         case DRM_FORMAT_XRGB16161616:
4937         case DRM_FORMAT_ARGB16161616:
4938                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616;
4939                 break;
4940         case DRM_FORMAT_XBGR16161616:
4941         case DRM_FORMAT_ABGR16161616:
4942                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616;
4943                 break;
4944         default:
4945                 DRM_ERROR(
4946                         "Unsupported screen format %p4cc\n",
4947                         &fb->format->format);
4948                 return -EINVAL;
4949         }
4950
4951         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
4952         case DRM_MODE_ROTATE_0:
4953                 plane_info->rotation = ROTATION_ANGLE_0;
4954                 break;
4955         case DRM_MODE_ROTATE_90:
4956                 plane_info->rotation = ROTATION_ANGLE_90;
4957                 break;
4958         case DRM_MODE_ROTATE_180:
4959                 plane_info->rotation = ROTATION_ANGLE_180;
4960                 break;
4961         case DRM_MODE_ROTATE_270:
4962                 plane_info->rotation = ROTATION_ANGLE_270;
4963                 break;
4964         default:
4965                 plane_info->rotation = ROTATION_ANGLE_0;
4966                 break;
4967         }
4968
4969
4970         plane_info->visible = true;
4971         plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
4972
4973         plane_info->layer_index = plane_state->normalized_zpos;
4974
4975         ret = fill_plane_color_attributes(plane_state, plane_info->format,
4976                                           &plane_info->color_space);
4977         if (ret)
4978                 return ret;
4979
4980         ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format,
4981                                            plane_info->rotation, tiling_flags,
4982                                            &plane_info->tiling_info,
4983                                            &plane_info->plane_size,
4984                                            &plane_info->dcc, address,
4985                                            tmz_surface, force_disable_dcc);
4986         if (ret)
4987                 return ret;
4988
4989         amdgpu_dm_plane_fill_blending_from_plane_state(
4990                 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha,
4991                 &plane_info->global_alpha, &plane_info->global_alpha_value);
4992
4993         return 0;
4994 }
4995
4996 static int fill_dc_plane_attributes(struct amdgpu_device *adev,
4997                                     struct dc_plane_state *dc_plane_state,
4998                                     struct drm_plane_state *plane_state,
4999                                     struct drm_crtc_state *crtc_state)
5000 {
5001         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5002         struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb;
5003         struct dc_scaling_info scaling_info;
5004         struct dc_plane_info plane_info;
5005         int ret;
5006         bool force_disable_dcc = false;
5007
5008         ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info);
5009         if (ret)
5010                 return ret;
5011
5012         dc_plane_state->src_rect = scaling_info.src_rect;
5013         dc_plane_state->dst_rect = scaling_info.dst_rect;
5014         dc_plane_state->clip_rect = scaling_info.clip_rect;
5015         dc_plane_state->scaling_quality = scaling_info.scaling_quality;
5016
5017         force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
5018         ret = fill_dc_plane_info_and_addr(adev, plane_state,
5019                                           afb->tiling_flags,
5020                                           &plane_info,
5021                                           &dc_plane_state->address,
5022                                           afb->tmz_surface,
5023                                           force_disable_dcc);
5024         if (ret)
5025                 return ret;
5026
5027         dc_plane_state->format = plane_info.format;
5028         dc_plane_state->color_space = plane_info.color_space;
5029         dc_plane_state->format = plane_info.format;
5030         dc_plane_state->plane_size = plane_info.plane_size;
5031         dc_plane_state->rotation = plane_info.rotation;
5032         dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
5033         dc_plane_state->stereo_format = plane_info.stereo_format;
5034         dc_plane_state->tiling_info = plane_info.tiling_info;
5035         dc_plane_state->visible = plane_info.visible;
5036         dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
5037         dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha;
5038         dc_plane_state->global_alpha = plane_info.global_alpha;
5039         dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
5040         dc_plane_state->dcc = plane_info.dcc;
5041         dc_plane_state->layer_index = plane_info.layer_index;
5042         dc_plane_state->flip_int_enabled = true;
5043
5044         /*
5045          * Always set input transfer function, since plane state is refreshed
5046          * every time.
5047          */
5048         ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
5049         if (ret)
5050                 return ret;
5051
5052         return 0;
5053 }
5054
5055 static inline void fill_dc_dirty_rect(struct drm_plane *plane,
5056                                       struct rect *dirty_rect, int32_t x,
5057                                       s32 y, s32 width, s32 height,
5058                                       int *i, bool ffu)
5059 {
5060         if (*i > DC_MAX_DIRTY_RECTS)
5061                 return;
5062
5063         if (*i == DC_MAX_DIRTY_RECTS)
5064                 goto out;
5065
5066         dirty_rect->x = x;
5067         dirty_rect->y = y;
5068         dirty_rect->width = width;
5069         dirty_rect->height = height;
5070
5071         if (ffu)
5072                 drm_dbg(plane->dev,
5073                         "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n",
5074                         plane->base.id, width, height);
5075         else
5076                 drm_dbg(plane->dev,
5077                         "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)",
5078                         plane->base.id, x, y, width, height);
5079
5080 out:
5081         (*i)++;
5082 }
5083
5084 /**
5085  * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates
5086  *
5087  * @plane: DRM plane containing dirty regions that need to be flushed to the eDP
5088  *         remote fb
5089  * @old_plane_state: Old state of @plane
5090  * @new_plane_state: New state of @plane
5091  * @crtc_state: New state of CRTC connected to the @plane
5092  * @flip_addrs: DC flip tracking struct, which also tracts dirty rects
5093  * @dirty_regions_changed: dirty regions changed
5094  *
5095  * For PSR SU, DC informs the DMUB uController of dirty rectangle regions
5096  * (referred to as "damage clips" in DRM nomenclature) that require updating on
5097  * the eDP remote buffer. The responsibility of specifying the dirty regions is
5098  * amdgpu_dm's.
5099  *
5100  * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the
5101  * plane with regions that require flushing to the eDP remote buffer. In
5102  * addition, certain use cases - such as cursor and multi-plane overlay (MPO) -
5103  * implicitly provide damage clips without any client support via the plane
5104  * bounds.
5105  */
5106 static void fill_dc_dirty_rects(struct drm_plane *plane,
5107                                 struct drm_plane_state *old_plane_state,
5108                                 struct drm_plane_state *new_plane_state,
5109                                 struct drm_crtc_state *crtc_state,
5110                                 struct dc_flip_addrs *flip_addrs,
5111                                 bool *dirty_regions_changed)
5112 {
5113         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5114         struct rect *dirty_rects = flip_addrs->dirty_rects;
5115         u32 num_clips;
5116         struct drm_mode_rect *clips;
5117         bool bb_changed;
5118         bool fb_changed;
5119         u32 i = 0;
5120         *dirty_regions_changed = false;
5121
5122         /*
5123          * Cursor plane has it's own dirty rect update interface. See
5124          * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data
5125          */
5126         if (plane->type == DRM_PLANE_TYPE_CURSOR)
5127                 return;
5128
5129         num_clips = drm_plane_get_damage_clips_count(new_plane_state);
5130         clips = drm_plane_get_damage_clips(new_plane_state);
5131
5132         if (!dm_crtc_state->mpo_requested) {
5133                 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS)
5134                         goto ffu;
5135
5136                 for (; flip_addrs->dirty_rect_count < num_clips; clips++)
5137                         fill_dc_dirty_rect(new_plane_state->plane,
5138                                            &dirty_rects[flip_addrs->dirty_rect_count],
5139                                            clips->x1, clips->y1,
5140                                            clips->x2 - clips->x1, clips->y2 - clips->y1,
5141                                            &flip_addrs->dirty_rect_count,
5142                                            false);
5143                 return;
5144         }
5145
5146         /*
5147          * MPO is requested. Add entire plane bounding box to dirty rects if
5148          * flipped to or damaged.
5149          *
5150          * If plane is moved or resized, also add old bounding box to dirty
5151          * rects.
5152          */
5153         fb_changed = old_plane_state->fb->base.id !=
5154                      new_plane_state->fb->base.id;
5155         bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x ||
5156                       old_plane_state->crtc_y != new_plane_state->crtc_y ||
5157                       old_plane_state->crtc_w != new_plane_state->crtc_w ||
5158                       old_plane_state->crtc_h != new_plane_state->crtc_h);
5159
5160         drm_dbg(plane->dev,
5161                 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n",
5162                 new_plane_state->plane->base.id,
5163                 bb_changed, fb_changed, num_clips);
5164
5165         *dirty_regions_changed = bb_changed;
5166
5167         if (bb_changed) {
5168                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5169                                    new_plane_state->crtc_x,
5170                                    new_plane_state->crtc_y,
5171                                    new_plane_state->crtc_w,
5172                                    new_plane_state->crtc_h, &i, false);
5173
5174                 /* Add old plane bounding-box if plane is moved or resized */
5175                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5176                                    old_plane_state->crtc_x,
5177                                    old_plane_state->crtc_y,
5178                                    old_plane_state->crtc_w,
5179                                    old_plane_state->crtc_h, &i, false);
5180         }
5181
5182         if (num_clips) {
5183                 for (; i < num_clips; clips++)
5184                         fill_dc_dirty_rect(new_plane_state->plane,
5185                                            &dirty_rects[i], clips->x1,
5186                                            clips->y1, clips->x2 - clips->x1,
5187                                            clips->y2 - clips->y1, &i, false);
5188         } else if (fb_changed && !bb_changed) {
5189                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5190                                    new_plane_state->crtc_x,
5191                                    new_plane_state->crtc_y,
5192                                    new_plane_state->crtc_w,
5193                                    new_plane_state->crtc_h, &i, false);
5194         }
5195
5196         if (i > DC_MAX_DIRTY_RECTS)
5197                 goto ffu;
5198
5199         flip_addrs->dirty_rect_count = i;
5200         return;
5201
5202 ffu:
5203         fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0,
5204                            dm_crtc_state->base.mode.crtc_hdisplay,
5205                            dm_crtc_state->base.mode.crtc_vdisplay,
5206                            &flip_addrs->dirty_rect_count, true);
5207 }
5208
5209 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
5210                                            const struct dm_connector_state *dm_state,
5211                                            struct dc_stream_state *stream)
5212 {
5213         enum amdgpu_rmx_type rmx_type;
5214
5215         struct rect src = { 0 }; /* viewport in composition space*/
5216         struct rect dst = { 0 }; /* stream addressable area */
5217
5218         /* no mode. nothing to be done */
5219         if (!mode)
5220                 return;
5221
5222         /* Full screen scaling by default */
5223         src.width = mode->hdisplay;
5224         src.height = mode->vdisplay;
5225         dst.width = stream->timing.h_addressable;
5226         dst.height = stream->timing.v_addressable;
5227
5228         if (dm_state) {
5229                 rmx_type = dm_state->scaling;
5230                 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
5231                         if (src.width * dst.height <
5232                                         src.height * dst.width) {
5233                                 /* height needs less upscaling/more downscaling */
5234                                 dst.width = src.width *
5235                                                 dst.height / src.height;
5236                         } else {
5237                                 /* width needs less upscaling/more downscaling */
5238                                 dst.height = src.height *
5239                                                 dst.width / src.width;
5240                         }
5241                 } else if (rmx_type == RMX_CENTER) {
5242                         dst = src;
5243                 }
5244
5245                 dst.x = (stream->timing.h_addressable - dst.width) / 2;
5246                 dst.y = (stream->timing.v_addressable - dst.height) / 2;
5247
5248                 if (dm_state->underscan_enable) {
5249                         dst.x += dm_state->underscan_hborder / 2;
5250                         dst.y += dm_state->underscan_vborder / 2;
5251                         dst.width -= dm_state->underscan_hborder;
5252                         dst.height -= dm_state->underscan_vborder;
5253                 }
5254         }
5255
5256         stream->src = src;
5257         stream->dst = dst;
5258
5259         DRM_DEBUG_KMS("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",
5260                       dst.x, dst.y, dst.width, dst.height);
5261
5262 }
5263
5264 static enum dc_color_depth
5265 convert_color_depth_from_display_info(const struct drm_connector *connector,
5266                                       bool is_y420, int requested_bpc)
5267 {
5268         u8 bpc;
5269
5270         if (is_y420) {
5271                 bpc = 8;
5272
5273                 /* Cap display bpc based on HDMI 2.0 HF-VSDB */
5274                 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)
5275                         bpc = 16;
5276                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
5277                         bpc = 12;
5278                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
5279                         bpc = 10;
5280         } else {
5281                 bpc = (uint8_t)connector->display_info.bpc;
5282                 /* Assume 8 bpc by default if no bpc is specified. */
5283                 bpc = bpc ? bpc : 8;
5284         }
5285
5286         if (requested_bpc > 0) {
5287                 /*
5288                  * Cap display bpc based on the user requested value.
5289                  *
5290                  * The value for state->max_bpc may not correctly updated
5291                  * depending on when the connector gets added to the state
5292                  * or if this was called outside of atomic check, so it
5293                  * can't be used directly.
5294                  */
5295                 bpc = min_t(u8, bpc, requested_bpc);
5296
5297                 /* Round down to the nearest even number. */
5298                 bpc = bpc - (bpc & 1);
5299         }
5300
5301         switch (bpc) {
5302         case 0:
5303                 /*
5304                  * Temporary Work around, DRM doesn't parse color depth for
5305                  * EDID revision before 1.4
5306                  * TODO: Fix edid parsing
5307                  */
5308                 return COLOR_DEPTH_888;
5309         case 6:
5310                 return COLOR_DEPTH_666;
5311         case 8:
5312                 return COLOR_DEPTH_888;
5313         case 10:
5314                 return COLOR_DEPTH_101010;
5315         case 12:
5316                 return COLOR_DEPTH_121212;
5317         case 14:
5318                 return COLOR_DEPTH_141414;
5319         case 16:
5320                 return COLOR_DEPTH_161616;
5321         default:
5322                 return COLOR_DEPTH_UNDEFINED;
5323         }
5324 }
5325
5326 static enum dc_aspect_ratio
5327 get_aspect_ratio(const struct drm_display_mode *mode_in)
5328 {
5329         /* 1-1 mapping, since both enums follow the HDMI spec. */
5330         return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
5331 }
5332
5333 static enum dc_color_space
5334 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
5335 {
5336         enum dc_color_space color_space = COLOR_SPACE_SRGB;
5337
5338         switch (dc_crtc_timing->pixel_encoding) {
5339         case PIXEL_ENCODING_YCBCR422:
5340         case PIXEL_ENCODING_YCBCR444:
5341         case PIXEL_ENCODING_YCBCR420:
5342         {
5343                 /*
5344                  * 27030khz is the separation point between HDTV and SDTV
5345                  * according to HDMI spec, we use YCbCr709 and YCbCr601
5346                  * respectively
5347                  */
5348                 if (dc_crtc_timing->pix_clk_100hz > 270300) {
5349                         if (dc_crtc_timing->flags.Y_ONLY)
5350                                 color_space =
5351                                         COLOR_SPACE_YCBCR709_LIMITED;
5352                         else
5353                                 color_space = COLOR_SPACE_YCBCR709;
5354                 } else {
5355                         if (dc_crtc_timing->flags.Y_ONLY)
5356                                 color_space =
5357                                         COLOR_SPACE_YCBCR601_LIMITED;
5358                         else
5359                                 color_space = COLOR_SPACE_YCBCR601;
5360                 }
5361
5362         }
5363         break;
5364         case PIXEL_ENCODING_RGB:
5365                 color_space = COLOR_SPACE_SRGB;
5366                 break;
5367
5368         default:
5369                 WARN_ON(1);
5370                 break;
5371         }
5372
5373         return color_space;
5374 }
5375
5376 static bool adjust_colour_depth_from_display_info(
5377         struct dc_crtc_timing *timing_out,
5378         const struct drm_display_info *info)
5379 {
5380         enum dc_color_depth depth = timing_out->display_color_depth;
5381         int normalized_clk;
5382         do {
5383                 normalized_clk = timing_out->pix_clk_100hz / 10;
5384                 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
5385                 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
5386                         normalized_clk /= 2;
5387                 /* Adjusting pix clock following on HDMI spec based on colour depth */
5388                 switch (depth) {
5389                 case COLOR_DEPTH_888:
5390                         break;
5391                 case COLOR_DEPTH_101010:
5392                         normalized_clk = (normalized_clk * 30) / 24;
5393                         break;
5394                 case COLOR_DEPTH_121212:
5395                         normalized_clk = (normalized_clk * 36) / 24;
5396                         break;
5397                 case COLOR_DEPTH_161616:
5398                         normalized_clk = (normalized_clk * 48) / 24;
5399                         break;
5400                 default:
5401                         /* The above depths are the only ones valid for HDMI. */
5402                         return false;
5403                 }
5404                 if (normalized_clk <= info->max_tmds_clock) {
5405                         timing_out->display_color_depth = depth;
5406                         return true;
5407                 }
5408         } while (--depth > COLOR_DEPTH_666);
5409         return false;
5410 }
5411
5412 static void fill_stream_properties_from_drm_display_mode(
5413         struct dc_stream_state *stream,
5414         const struct drm_display_mode *mode_in,
5415         const struct drm_connector *connector,
5416         const struct drm_connector_state *connector_state,
5417         const struct dc_stream_state *old_stream,
5418         int requested_bpc)
5419 {
5420         struct dc_crtc_timing *timing_out = &stream->timing;
5421         const struct drm_display_info *info = &connector->display_info;
5422         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5423         struct hdmi_vendor_infoframe hv_frame;
5424         struct hdmi_avi_infoframe avi_frame;
5425
5426         memset(&hv_frame, 0, sizeof(hv_frame));
5427         memset(&avi_frame, 0, sizeof(avi_frame));
5428
5429         timing_out->h_border_left = 0;
5430         timing_out->h_border_right = 0;
5431         timing_out->v_border_top = 0;
5432         timing_out->v_border_bottom = 0;
5433         /* TODO: un-hardcode */
5434         if (drm_mode_is_420_only(info, mode_in)
5435                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5436                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5437         else if (drm_mode_is_420_also(info, mode_in)
5438                         && aconnector->force_yuv420_output)
5439                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5440         else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444)
5441                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5442                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
5443         else
5444                 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
5445
5446         timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
5447         timing_out->display_color_depth = convert_color_depth_from_display_info(
5448                 connector,
5449                 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420),
5450                 requested_bpc);
5451         timing_out->scan_type = SCANNING_TYPE_NODATA;
5452         timing_out->hdmi_vic = 0;
5453
5454         if (old_stream) {
5455                 timing_out->vic = old_stream->timing.vic;
5456                 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
5457                 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
5458         } else {
5459                 timing_out->vic = drm_match_cea_mode(mode_in);
5460                 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
5461                         timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
5462                 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
5463                         timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
5464         }
5465
5466         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5467                 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
5468                 timing_out->vic = avi_frame.video_code;
5469                 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
5470                 timing_out->hdmi_vic = hv_frame.vic;
5471         }
5472
5473         if (is_freesync_video_mode(mode_in, aconnector)) {
5474                 timing_out->h_addressable = mode_in->hdisplay;
5475                 timing_out->h_total = mode_in->htotal;
5476                 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start;
5477                 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay;
5478                 timing_out->v_total = mode_in->vtotal;
5479                 timing_out->v_addressable = mode_in->vdisplay;
5480                 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay;
5481                 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start;
5482                 timing_out->pix_clk_100hz = mode_in->clock * 10;
5483         } else {
5484                 timing_out->h_addressable = mode_in->crtc_hdisplay;
5485                 timing_out->h_total = mode_in->crtc_htotal;
5486                 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
5487                 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
5488                 timing_out->v_total = mode_in->crtc_vtotal;
5489                 timing_out->v_addressable = mode_in->crtc_vdisplay;
5490                 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
5491                 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
5492                 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
5493         }
5494
5495         timing_out->aspect_ratio = get_aspect_ratio(mode_in);
5496
5497         stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
5498         stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
5499         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5500                 if (!adjust_colour_depth_from_display_info(timing_out, info) &&
5501                     drm_mode_is_420_also(info, mode_in) &&
5502                     timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
5503                         timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5504                         adjust_colour_depth_from_display_info(timing_out, info);
5505                 }
5506         }
5507
5508         stream->output_color_space = get_output_color_space(timing_out);
5509 }
5510
5511 static void fill_audio_info(struct audio_info *audio_info,
5512                             const struct drm_connector *drm_connector,
5513                             const struct dc_sink *dc_sink)
5514 {
5515         int i = 0;
5516         int cea_revision = 0;
5517         const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
5518
5519         audio_info->manufacture_id = edid_caps->manufacturer_id;
5520         audio_info->product_id = edid_caps->product_id;
5521
5522         cea_revision = drm_connector->display_info.cea_rev;
5523
5524         strscpy(audio_info->display_name,
5525                 edid_caps->display_name,
5526                 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
5527
5528         if (cea_revision >= 3) {
5529                 audio_info->mode_count = edid_caps->audio_mode_count;
5530
5531                 for (i = 0; i < audio_info->mode_count; ++i) {
5532                         audio_info->modes[i].format_code =
5533                                         (enum audio_format_code)
5534                                         (edid_caps->audio_modes[i].format_code);
5535                         audio_info->modes[i].channel_count =
5536                                         edid_caps->audio_modes[i].channel_count;
5537                         audio_info->modes[i].sample_rates.all =
5538                                         edid_caps->audio_modes[i].sample_rate;
5539                         audio_info->modes[i].sample_size =
5540                                         edid_caps->audio_modes[i].sample_size;
5541                 }
5542         }
5543
5544         audio_info->flags.all = edid_caps->speaker_flags;
5545
5546         /* TODO: We only check for the progressive mode, check for interlace mode too */
5547         if (drm_connector->latency_present[0]) {
5548                 audio_info->video_latency = drm_connector->video_latency[0];
5549                 audio_info->audio_latency = drm_connector->audio_latency[0];
5550         }
5551
5552         /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
5553
5554 }
5555
5556 static void
5557 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
5558                                       struct drm_display_mode *dst_mode)
5559 {
5560         dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
5561         dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
5562         dst_mode->crtc_clock = src_mode->crtc_clock;
5563         dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
5564         dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
5565         dst_mode->crtc_hsync_start =  src_mode->crtc_hsync_start;
5566         dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
5567         dst_mode->crtc_htotal = src_mode->crtc_htotal;
5568         dst_mode->crtc_hskew = src_mode->crtc_hskew;
5569         dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
5570         dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
5571         dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
5572         dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
5573         dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
5574 }
5575
5576 static void
5577 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
5578                                         const struct drm_display_mode *native_mode,
5579                                         bool scale_enabled)
5580 {
5581         if (scale_enabled) {
5582                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5583         } else if (native_mode->clock == drm_mode->clock &&
5584                         native_mode->htotal == drm_mode->htotal &&
5585                         native_mode->vtotal == drm_mode->vtotal) {
5586                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5587         } else {
5588                 /* no scaling nor amdgpu inserted, no need to patch */
5589         }
5590 }
5591
5592 static struct dc_sink *
5593 create_fake_sink(struct amdgpu_dm_connector *aconnector)
5594 {
5595         struct dc_sink_init_data sink_init_data = { 0 };
5596         struct dc_sink *sink = NULL;
5597         sink_init_data.link = aconnector->dc_link;
5598         sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
5599
5600         sink = dc_sink_create(&sink_init_data);
5601         if (!sink) {
5602                 DRM_ERROR("Failed to create sink!\n");
5603                 return NULL;
5604         }
5605         sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
5606
5607         return sink;
5608 }
5609
5610 static void set_multisync_trigger_params(
5611                 struct dc_stream_state *stream)
5612 {
5613         struct dc_stream_state *master = NULL;
5614
5615         if (stream->triggered_crtc_reset.enabled) {
5616                 master = stream->triggered_crtc_reset.event_source;
5617                 stream->triggered_crtc_reset.event =
5618                         master->timing.flags.VSYNC_POSITIVE_POLARITY ?
5619                         CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING;
5620                 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL;
5621         }
5622 }
5623
5624 static void set_master_stream(struct dc_stream_state *stream_set[],
5625                               int stream_count)
5626 {
5627         int j, highest_rfr = 0, master_stream = 0;
5628
5629         for (j = 0;  j < stream_count; j++) {
5630                 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
5631                         int refresh_rate = 0;
5632
5633                         refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
5634                                 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
5635                         if (refresh_rate > highest_rfr) {
5636                                 highest_rfr = refresh_rate;
5637                                 master_stream = j;
5638                         }
5639                 }
5640         }
5641         for (j = 0;  j < stream_count; j++) {
5642                 if (stream_set[j])
5643                         stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
5644         }
5645 }
5646
5647 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
5648 {
5649         int i = 0;
5650         struct dc_stream_state *stream;
5651
5652         if (context->stream_count < 2)
5653                 return;
5654         for (i = 0; i < context->stream_count ; i++) {
5655                 if (!context->streams[i])
5656                         continue;
5657                 /*
5658                  * TODO: add a function to read AMD VSDB bits and set
5659                  * crtc_sync_master.multi_sync_enabled flag
5660                  * For now it's set to false
5661                  */
5662         }
5663
5664         set_master_stream(context->streams, context->stream_count);
5665
5666         for (i = 0; i < context->stream_count ; i++) {
5667                 stream = context->streams[i];
5668
5669                 if (!stream)
5670                         continue;
5671
5672                 set_multisync_trigger_params(stream);
5673         }
5674 }
5675
5676 /**
5677  * DOC: FreeSync Video
5678  *
5679  * When a userspace application wants to play a video, the content follows a
5680  * standard format definition that usually specifies the FPS for that format.
5681  * The below list illustrates some video format and the expected FPS,
5682  * respectively:
5683  *
5684  * - TV/NTSC (23.976 FPS)
5685  * - Cinema (24 FPS)
5686  * - TV/PAL (25 FPS)
5687  * - TV/NTSC (29.97 FPS)
5688  * - TV/NTSC (30 FPS)
5689  * - Cinema HFR (48 FPS)
5690  * - TV/PAL (50 FPS)
5691  * - Commonly used (60 FPS)
5692  * - Multiples of 24 (48,72,96 FPS)
5693  *
5694  * The list of standards video format is not huge and can be added to the
5695  * connector modeset list beforehand. With that, userspace can leverage
5696  * FreeSync to extends the front porch in order to attain the target refresh
5697  * rate. Such a switch will happen seamlessly, without screen blanking or
5698  * reprogramming of the output in any other way. If the userspace requests a
5699  * modesetting change compatible with FreeSync modes that only differ in the
5700  * refresh rate, DC will skip the full update and avoid blink during the
5701  * transition. For example, the video player can change the modesetting from
5702  * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without
5703  * causing any display blink. This same concept can be applied to a mode
5704  * setting change.
5705  */
5706 static struct drm_display_mode *
5707 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
5708                 bool use_probed_modes)
5709 {
5710         struct drm_display_mode *m, *m_pref = NULL;
5711         u16 current_refresh, highest_refresh;
5712         struct list_head *list_head = use_probed_modes ?
5713                 &aconnector->base.probed_modes :
5714                 &aconnector->base.modes;
5715
5716         if (aconnector->freesync_vid_base.clock != 0)
5717                 return &aconnector->freesync_vid_base;
5718
5719         /* Find the preferred mode */
5720         list_for_each_entry (m, list_head, head) {
5721                 if (m->type & DRM_MODE_TYPE_PREFERRED) {
5722                         m_pref = m;
5723                         break;
5724                 }
5725         }
5726
5727         if (!m_pref) {
5728                 /* Probably an EDID with no preferred mode. Fallback to first entry */
5729                 m_pref = list_first_entry_or_null(
5730                                 &aconnector->base.modes, struct drm_display_mode, head);
5731                 if (!m_pref) {
5732                         DRM_DEBUG_DRIVER("No preferred mode found in EDID\n");
5733                         return NULL;
5734                 }
5735         }
5736
5737         highest_refresh = drm_mode_vrefresh(m_pref);
5738
5739         /*
5740          * Find the mode with highest refresh rate with same resolution.
5741          * For some monitors, preferred mode is not the mode with highest
5742          * supported refresh rate.
5743          */
5744         list_for_each_entry (m, list_head, head) {
5745                 current_refresh  = drm_mode_vrefresh(m);
5746
5747                 if (m->hdisplay == m_pref->hdisplay &&
5748                     m->vdisplay == m_pref->vdisplay &&
5749                     highest_refresh < current_refresh) {
5750                         highest_refresh = current_refresh;
5751                         m_pref = m;
5752                 }
5753         }
5754
5755         drm_mode_copy(&aconnector->freesync_vid_base, m_pref);
5756         return m_pref;
5757 }
5758
5759 static bool is_freesync_video_mode(const struct drm_display_mode *mode,
5760                 struct amdgpu_dm_connector *aconnector)
5761 {
5762         struct drm_display_mode *high_mode;
5763         int timing_diff;
5764
5765         high_mode = get_highest_refresh_rate_mode(aconnector, false);
5766         if (!high_mode || !mode)
5767                 return false;
5768
5769         timing_diff = high_mode->vtotal - mode->vtotal;
5770
5771         if (high_mode->clock == 0 || high_mode->clock != mode->clock ||
5772             high_mode->hdisplay != mode->hdisplay ||
5773             high_mode->vdisplay != mode->vdisplay ||
5774             high_mode->hsync_start != mode->hsync_start ||
5775             high_mode->hsync_end != mode->hsync_end ||
5776             high_mode->htotal != mode->htotal ||
5777             high_mode->hskew != mode->hskew ||
5778             high_mode->vscan != mode->vscan ||
5779             high_mode->vsync_start - mode->vsync_start != timing_diff ||
5780             high_mode->vsync_end - mode->vsync_end != timing_diff)
5781                 return false;
5782         else
5783                 return true;
5784 }
5785
5786 static void update_dsc_caps(struct amdgpu_dm_connector *aconnector,
5787                             struct dc_sink *sink, struct dc_stream_state *stream,
5788                             struct dsc_dec_dpcd_caps *dsc_caps)
5789 {
5790         stream->timing.flags.DSC = 0;
5791         dsc_caps->is_dsc_supported = false;
5792
5793         if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
5794             sink->sink_signal == SIGNAL_TYPE_EDP)) {
5795                 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE ||
5796                         sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
5797                         dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
5798                                 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
5799                                 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
5800                                 dsc_caps);
5801         }
5802 }
5803
5804
5805 static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
5806                                     struct dc_sink *sink, struct dc_stream_state *stream,
5807                                     struct dsc_dec_dpcd_caps *dsc_caps,
5808                                     uint32_t max_dsc_target_bpp_limit_override)
5809 {
5810         const struct dc_link_settings *verified_link_cap = NULL;
5811         u32 link_bw_in_kbps;
5812         u32 edp_min_bpp_x16, edp_max_bpp_x16;
5813         struct dc *dc = sink->ctx->dc;
5814         struct dc_dsc_bw_range bw_range = {0};
5815         struct dc_dsc_config dsc_cfg = {0};
5816         struct dc_dsc_config_options dsc_options = {0};
5817
5818         dc_dsc_get_default_config_option(dc, &dsc_options);
5819         dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5820
5821         verified_link_cap = dc_link_get_link_cap(stream->link);
5822         link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap);
5823         edp_min_bpp_x16 = 8 * 16;
5824         edp_max_bpp_x16 = 8 * 16;
5825
5826         if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel)
5827                 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel;
5828
5829         if (edp_max_bpp_x16 < edp_min_bpp_x16)
5830                 edp_min_bpp_x16 = edp_max_bpp_x16;
5831
5832         if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0],
5833                                 dc->debug.dsc_min_slice_height_override,
5834                                 edp_min_bpp_x16, edp_max_bpp_x16,
5835                                 dsc_caps,
5836                                 &stream->timing,
5837                                 &bw_range)) {
5838
5839                 if (bw_range.max_kbps < link_bw_in_kbps) {
5840                         if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5841                                         dsc_caps,
5842                                         &dsc_options,
5843                                         0,
5844                                         &stream->timing,
5845                                         &dsc_cfg)) {
5846                                 stream->timing.dsc_cfg = dsc_cfg;
5847                                 stream->timing.flags.DSC = 1;
5848                                 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16;
5849                         }
5850                         return;
5851                 }
5852         }
5853
5854         if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5855                                 dsc_caps,
5856                                 &dsc_options,
5857                                 link_bw_in_kbps,
5858                                 &stream->timing,
5859                                 &dsc_cfg)) {
5860                 stream->timing.dsc_cfg = dsc_cfg;
5861                 stream->timing.flags.DSC = 1;
5862         }
5863 }
5864
5865
5866 static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
5867                                         struct dc_sink *sink, struct dc_stream_state *stream,
5868                                         struct dsc_dec_dpcd_caps *dsc_caps)
5869 {
5870         struct drm_connector *drm_connector = &aconnector->base;
5871         u32 link_bandwidth_kbps;
5872         struct dc *dc = sink->ctx->dc;
5873         u32 max_supported_bw_in_kbps, timing_bw_in_kbps;
5874         u32 dsc_max_supported_bw_in_kbps;
5875         u32 max_dsc_target_bpp_limit_override =
5876                 drm_connector->display_info.max_dsc_bpp;
5877         struct dc_dsc_config_options dsc_options = {0};
5878
5879         dc_dsc_get_default_config_option(dc, &dsc_options);
5880         dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5881
5882         link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
5883                                                         dc_link_get_link_cap(aconnector->dc_link));
5884
5885         /* Set DSC policy according to dsc_clock_en */
5886         dc_dsc_policy_set_enable_dsc_when_not_needed(
5887                 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);
5888
5889         if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP &&
5890             !aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&
5891             dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
5892
5893                 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);
5894
5895         } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
5896                 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
5897                         if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5898                                                 dsc_caps,
5899                                                 &dsc_options,
5900                                                 link_bandwidth_kbps,
5901                                                 &stream->timing,
5902                                                 &stream->timing.dsc_cfg)) {
5903                                 stream->timing.flags.DSC = 1;
5904                                 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name);
5905                         }
5906                 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
5907                         timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
5908                         max_supported_bw_in_kbps = link_bandwidth_kbps;
5909                         dsc_max_supported_bw_in_kbps = link_bandwidth_kbps;
5910
5911                         if (timing_bw_in_kbps > max_supported_bw_in_kbps &&
5912                                         max_supported_bw_in_kbps > 0 &&
5913                                         dsc_max_supported_bw_in_kbps > 0)
5914                                 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5915                                                 dsc_caps,
5916                                                 &dsc_options,
5917                                                 dsc_max_supported_bw_in_kbps,
5918                                                 &stream->timing,
5919                                                 &stream->timing.dsc_cfg)) {
5920                                         stream->timing.flags.DSC = 1;
5921                                         DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n",
5922                                                                          __func__, drm_connector->name);
5923                                 }
5924                 }
5925         }
5926
5927         /* Overwrite the stream flag if DSC is enabled through debugfs */
5928         if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
5929                 stream->timing.flags.DSC = 1;
5930
5931         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
5932                 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
5933
5934         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
5935                 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
5936
5937         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
5938                 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
5939 }
5940
5941 static struct dc_stream_state *
5942 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
5943                        const struct drm_display_mode *drm_mode,
5944                        const struct dm_connector_state *dm_state,
5945                        const struct dc_stream_state *old_stream,
5946                        int requested_bpc)
5947 {
5948         struct drm_display_mode *preferred_mode = NULL;
5949         struct drm_connector *drm_connector;
5950         const struct drm_connector_state *con_state =
5951                 dm_state ? &dm_state->base : NULL;
5952         struct dc_stream_state *stream = NULL;
5953         struct drm_display_mode mode;
5954         struct drm_display_mode saved_mode;
5955         struct drm_display_mode *freesync_mode = NULL;
5956         bool native_mode_found = false;
5957         bool recalculate_timing = false;
5958         bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
5959         int mode_refresh;
5960         int preferred_refresh = 0;
5961         enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN;
5962         struct dsc_dec_dpcd_caps dsc_caps;
5963
5964         struct dc_sink *sink = NULL;
5965
5966         drm_mode_init(&mode, drm_mode);
5967         memset(&saved_mode, 0, sizeof(saved_mode));
5968
5969         if (aconnector == NULL) {
5970                 DRM_ERROR("aconnector is NULL!\n");
5971                 return stream;
5972         }
5973
5974         drm_connector = &aconnector->base;
5975
5976         if (!aconnector->dc_sink) {
5977                 sink = create_fake_sink(aconnector);
5978                 if (!sink)
5979                         return stream;
5980         } else {
5981                 sink = aconnector->dc_sink;
5982                 dc_sink_retain(sink);
5983         }
5984
5985         stream = dc_create_stream_for_sink(sink);
5986
5987         if (stream == NULL) {
5988                 DRM_ERROR("Failed to create stream for sink!\n");
5989                 goto finish;
5990         }
5991
5992         stream->dm_stream_context = aconnector;
5993
5994         stream->timing.flags.LTE_340MCSC_SCRAMBLE =
5995                 drm_connector->display_info.hdmi.scdc.scrambling.low_rates;
5996
5997         list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
5998                 /* Search for preferred mode */
5999                 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
6000                         native_mode_found = true;
6001                         break;
6002                 }
6003         }
6004         if (!native_mode_found)
6005                 preferred_mode = list_first_entry_or_null(
6006                                 &aconnector->base.modes,
6007                                 struct drm_display_mode,
6008                                 head);
6009
6010         mode_refresh = drm_mode_vrefresh(&mode);
6011
6012         if (preferred_mode == NULL) {
6013                 /*
6014                  * This may not be an error, the use case is when we have no
6015                  * usermode calls to reset and set mode upon hotplug. In this
6016                  * case, we call set mode ourselves to restore the previous mode
6017                  * and the modelist may not be filled in in time.
6018                  */
6019                 DRM_DEBUG_DRIVER("No preferred mode found\n");
6020         } else {
6021                 recalculate_timing = amdgpu_freesync_vid_mode &&
6022                                  is_freesync_video_mode(&mode, aconnector);
6023                 if (recalculate_timing) {
6024                         freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
6025                         drm_mode_copy(&saved_mode, &mode);
6026                         drm_mode_copy(&mode, freesync_mode);
6027                 } else {
6028                         decide_crtc_timing_for_drm_display_mode(
6029                                         &mode, preferred_mode, scale);
6030
6031                         preferred_refresh = drm_mode_vrefresh(preferred_mode);
6032                 }
6033         }
6034
6035         if (recalculate_timing)
6036                 drm_mode_set_crtcinfo(&saved_mode, 0);
6037         else if (!dm_state)
6038                 drm_mode_set_crtcinfo(&mode, 0);
6039
6040         /*
6041         * If scaling is enabled and refresh rate didn't change
6042         * we copy the vic and polarities of the old timings
6043         */
6044         if (!scale || mode_refresh != preferred_refresh)
6045                 fill_stream_properties_from_drm_display_mode(
6046                         stream, &mode, &aconnector->base, con_state, NULL,
6047                         requested_bpc);
6048         else
6049                 fill_stream_properties_from_drm_display_mode(
6050                         stream, &mode, &aconnector->base, con_state, old_stream,
6051                         requested_bpc);
6052
6053         if (aconnector->timing_changed) {
6054                 DC_LOG_DEBUG("%s: overriding timing for automated test, bpc %d, changing to %d\n",
6055                                 __func__,
6056                                 stream->timing.display_color_depth,
6057                                 aconnector->timing_requested->display_color_depth);
6058                 stream->timing = *aconnector->timing_requested;
6059         }
6060
6061         /* SST DSC determination policy */
6062         update_dsc_caps(aconnector, sink, stream, &dsc_caps);
6063         if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported)
6064                 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps);
6065
6066         update_stream_scaling_settings(&mode, dm_state, stream);
6067
6068         fill_audio_info(
6069                 &stream->audio_info,
6070                 drm_connector,
6071                 sink);
6072
6073         update_stream_signal(stream, sink);
6074
6075         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
6076                 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);
6077
6078         if (stream->link->psr_settings.psr_feature_enabled) {
6079                 //
6080                 // should decide stream support vsc sdp colorimetry capability
6081                 // before building vsc info packet
6082                 //
6083                 stream->use_vsc_sdp_for_colorimetry = false;
6084                 if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
6085                         stream->use_vsc_sdp_for_colorimetry =
6086                                 aconnector->dc_sink->is_vsc_sdp_colorimetry_supported;
6087                 } else {
6088                         if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
6089                                 stream->use_vsc_sdp_for_colorimetry = true;
6090                 }
6091                 if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22)
6092                         tf = TRANSFER_FUNC_GAMMA_22;
6093                 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);
6094                 aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
6095
6096         }
6097 finish:
6098         dc_sink_release(sink);
6099
6100         return stream;
6101 }
6102
6103 static enum drm_connector_status
6104 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
6105 {
6106         bool connected;
6107         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6108
6109         /*
6110          * Notes:
6111          * 1. This interface is NOT called in context of HPD irq.
6112          * 2. This interface *is called* in context of user-mode ioctl. Which
6113          * makes it a bad place for *any* MST-related activity.
6114          */
6115
6116         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
6117             !aconnector->fake_enable)
6118                 connected = (aconnector->dc_sink != NULL);
6119         else
6120                 connected = (aconnector->base.force == DRM_FORCE_ON ||
6121                                 aconnector->base.force == DRM_FORCE_ON_DIGITAL);
6122
6123         update_subconnector_property(aconnector);
6124
6125         return (connected ? connector_status_connected :
6126                         connector_status_disconnected);
6127 }
6128
6129 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
6130                                             struct drm_connector_state *connector_state,
6131                                             struct drm_property *property,
6132                                             uint64_t val)
6133 {
6134         struct drm_device *dev = connector->dev;
6135         struct amdgpu_device *adev = drm_to_adev(dev);
6136         struct dm_connector_state *dm_old_state =
6137                 to_dm_connector_state(connector->state);
6138         struct dm_connector_state *dm_new_state =
6139                 to_dm_connector_state(connector_state);
6140
6141         int ret = -EINVAL;
6142
6143         if (property == dev->mode_config.scaling_mode_property) {
6144                 enum amdgpu_rmx_type rmx_type;
6145
6146                 switch (val) {
6147                 case DRM_MODE_SCALE_CENTER:
6148                         rmx_type = RMX_CENTER;
6149                         break;
6150                 case DRM_MODE_SCALE_ASPECT:
6151                         rmx_type = RMX_ASPECT;
6152                         break;
6153                 case DRM_MODE_SCALE_FULLSCREEN:
6154                         rmx_type = RMX_FULL;
6155                         break;
6156                 case DRM_MODE_SCALE_NONE:
6157                 default:
6158                         rmx_type = RMX_OFF;
6159                         break;
6160                 }
6161
6162                 if (dm_old_state->scaling == rmx_type)
6163                         return 0;
6164
6165                 dm_new_state->scaling = rmx_type;
6166                 ret = 0;
6167         } else if (property == adev->mode_info.underscan_hborder_property) {
6168                 dm_new_state->underscan_hborder = val;
6169                 ret = 0;
6170         } else if (property == adev->mode_info.underscan_vborder_property) {
6171                 dm_new_state->underscan_vborder = val;
6172                 ret = 0;
6173         } else if (property == adev->mode_info.underscan_property) {
6174                 dm_new_state->underscan_enable = val;
6175                 ret = 0;
6176         } else if (property == adev->mode_info.abm_level_property) {
6177                 dm_new_state->abm_level = val;
6178                 ret = 0;
6179         }
6180
6181         return ret;
6182 }
6183
6184 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
6185                                             const struct drm_connector_state *state,
6186                                             struct drm_property *property,
6187                                             uint64_t *val)
6188 {
6189         struct drm_device *dev = connector->dev;
6190         struct amdgpu_device *adev = drm_to_adev(dev);
6191         struct dm_connector_state *dm_state =
6192                 to_dm_connector_state(state);
6193         int ret = -EINVAL;
6194
6195         if (property == dev->mode_config.scaling_mode_property) {
6196                 switch (dm_state->scaling) {
6197                 case RMX_CENTER:
6198                         *val = DRM_MODE_SCALE_CENTER;
6199                         break;
6200                 case RMX_ASPECT:
6201                         *val = DRM_MODE_SCALE_ASPECT;
6202                         break;
6203                 case RMX_FULL:
6204                         *val = DRM_MODE_SCALE_FULLSCREEN;
6205                         break;
6206                 case RMX_OFF:
6207                 default:
6208                         *val = DRM_MODE_SCALE_NONE;
6209                         break;
6210                 }
6211                 ret = 0;
6212         } else if (property == adev->mode_info.underscan_hborder_property) {
6213                 *val = dm_state->underscan_hborder;
6214                 ret = 0;
6215         } else if (property == adev->mode_info.underscan_vborder_property) {
6216                 *val = dm_state->underscan_vborder;
6217                 ret = 0;
6218         } else if (property == adev->mode_info.underscan_property) {
6219                 *val = dm_state->underscan_enable;
6220                 ret = 0;
6221         } else if (property == adev->mode_info.abm_level_property) {
6222                 *val = dm_state->abm_level;
6223                 ret = 0;
6224         }
6225
6226         return ret;
6227 }
6228
6229 static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
6230 {
6231         struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
6232
6233         drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
6234 }
6235
6236 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
6237 {
6238         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6239         struct amdgpu_device *adev = drm_to_adev(connector->dev);
6240         struct amdgpu_display_manager *dm = &adev->dm;
6241
6242         /*
6243          * Call only if mst_mgr was initialized before since it's not done
6244          * for all connector types.
6245          */
6246         if (aconnector->mst_mgr.dev)
6247                 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);
6248
6249         if (aconnector->bl_idx != -1) {
6250                 backlight_device_unregister(dm->backlight_dev[aconnector->bl_idx]);
6251                 dm->backlight_dev[aconnector->bl_idx] = NULL;
6252         }
6253
6254         if (aconnector->dc_em_sink)
6255                 dc_sink_release(aconnector->dc_em_sink);
6256         aconnector->dc_em_sink = NULL;
6257         if (aconnector->dc_sink)
6258                 dc_sink_release(aconnector->dc_sink);
6259         aconnector->dc_sink = NULL;
6260
6261         drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
6262         drm_connector_unregister(connector);
6263         drm_connector_cleanup(connector);
6264         if (aconnector->i2c) {
6265                 i2c_del_adapter(&aconnector->i2c->base);
6266                 kfree(aconnector->i2c);
6267         }
6268         kfree(aconnector->dm_dp_aux.aux.name);
6269
6270         kfree(connector);
6271 }
6272
6273 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
6274 {
6275         struct dm_connector_state *state =
6276                 to_dm_connector_state(connector->state);
6277
6278         if (connector->state)
6279                 __drm_atomic_helper_connector_destroy_state(connector->state);
6280
6281         kfree(state);
6282
6283         state = kzalloc(sizeof(*state), GFP_KERNEL);
6284
6285         if (state) {
6286                 state->scaling = RMX_OFF;
6287                 state->underscan_enable = false;
6288                 state->underscan_hborder = 0;
6289                 state->underscan_vborder = 0;
6290                 state->base.max_requested_bpc = 8;
6291                 state->vcpi_slots = 0;
6292                 state->pbn = 0;
6293
6294                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
6295                         state->abm_level = amdgpu_dm_abm_level;
6296
6297                 __drm_atomic_helper_connector_reset(connector, &state->base);
6298         }
6299 }
6300
6301 struct drm_connector_state *
6302 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
6303 {
6304         struct dm_connector_state *state =
6305                 to_dm_connector_state(connector->state);
6306
6307         struct dm_connector_state *new_state =
6308                         kmemdup(state, sizeof(*state), GFP_KERNEL);
6309
6310         if (!new_state)
6311                 return NULL;
6312
6313         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
6314
6315         new_state->freesync_capable = state->freesync_capable;
6316         new_state->abm_level = state->abm_level;
6317         new_state->scaling = state->scaling;
6318         new_state->underscan_enable = state->underscan_enable;
6319         new_state->underscan_hborder = state->underscan_hborder;
6320         new_state->underscan_vborder = state->underscan_vborder;
6321         new_state->vcpi_slots = state->vcpi_slots;
6322         new_state->pbn = state->pbn;
6323         return &new_state->base;
6324 }
6325
6326 static int
6327 amdgpu_dm_connector_late_register(struct drm_connector *connector)
6328 {
6329         struct amdgpu_dm_connector *amdgpu_dm_connector =
6330                 to_amdgpu_dm_connector(connector);
6331         int r;
6332
6333         amdgpu_dm_register_backlight_device(amdgpu_dm_connector);
6334
6335         if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
6336             (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
6337                 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
6338                 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
6339                 if (r)
6340                         return r;
6341         }
6342
6343 #if defined(CONFIG_DEBUG_FS)
6344         connector_debugfs_init(amdgpu_dm_connector);
6345 #endif
6346
6347         return 0;
6348 }
6349
6350 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
6351         .reset = amdgpu_dm_connector_funcs_reset,
6352         .detect = amdgpu_dm_connector_detect,
6353         .fill_modes = drm_helper_probe_single_connector_modes,
6354         .destroy = amdgpu_dm_connector_destroy,
6355         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
6356         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6357         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
6358         .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
6359         .late_register = amdgpu_dm_connector_late_register,
6360         .early_unregister = amdgpu_dm_connector_unregister
6361 };
6362
6363 static int get_modes(struct drm_connector *connector)
6364 {
6365         return amdgpu_dm_connector_get_modes(connector);
6366 }
6367
6368 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
6369 {
6370         struct dc_sink_init_data init_params = {
6371                         .link = aconnector->dc_link,
6372                         .sink_signal = SIGNAL_TYPE_VIRTUAL
6373         };
6374         struct edid *edid;
6375
6376         if (!aconnector->base.edid_blob_ptr) {
6377                 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
6378                                 aconnector->base.name);
6379
6380                 aconnector->base.force = DRM_FORCE_OFF;
6381                 return;
6382         }
6383
6384         edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
6385
6386         aconnector->edid = edid;
6387
6388         aconnector->dc_em_sink = dc_link_add_remote_sink(
6389                 aconnector->dc_link,
6390                 (uint8_t *)edid,
6391                 (edid->extensions + 1) * EDID_LENGTH,
6392                 &init_params);
6393
6394         if (aconnector->base.force == DRM_FORCE_ON) {
6395                 aconnector->dc_sink = aconnector->dc_link->local_sink ?
6396                 aconnector->dc_link->local_sink :
6397                 aconnector->dc_em_sink;
6398                 dc_sink_retain(aconnector->dc_sink);
6399         }
6400 }
6401
6402 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
6403 {
6404         struct dc_link *link = (struct dc_link *)aconnector->dc_link;
6405
6406         /*
6407          * In case of headless boot with force on for DP managed connector
6408          * Those settings have to be != 0 to get initial modeset
6409          */
6410         if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
6411                 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
6412                 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
6413         }
6414
6415         create_eml_sink(aconnector);
6416 }
6417
6418 static enum dc_status dm_validate_stream_and_context(struct dc *dc,
6419                                                 struct dc_stream_state *stream)
6420 {
6421         enum dc_status dc_result = DC_ERROR_UNEXPECTED;
6422         struct dc_plane_state *dc_plane_state = NULL;
6423         struct dc_state *dc_state = NULL;
6424
6425         if (!stream)
6426                 goto cleanup;
6427
6428         dc_plane_state = dc_create_plane_state(dc);
6429         if (!dc_plane_state)
6430                 goto cleanup;
6431
6432         dc_state = dc_create_state(dc);
6433         if (!dc_state)
6434                 goto cleanup;
6435
6436         /* populate stream to plane */
6437         dc_plane_state->src_rect.height  = stream->src.height;
6438         dc_plane_state->src_rect.width   = stream->src.width;
6439         dc_plane_state->dst_rect.height  = stream->src.height;
6440         dc_plane_state->dst_rect.width   = stream->src.width;
6441         dc_plane_state->clip_rect.height = stream->src.height;
6442         dc_plane_state->clip_rect.width  = stream->src.width;
6443         dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256;
6444         dc_plane_state->plane_size.surface_size.height = stream->src.height;
6445         dc_plane_state->plane_size.surface_size.width  = stream->src.width;
6446         dc_plane_state->plane_size.chroma_size.height  = stream->src.height;
6447         dc_plane_state->plane_size.chroma_size.width   = stream->src.width;
6448         dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
6449         dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN;
6450         dc_plane_state->rotation = ROTATION_ANGLE_0;
6451         dc_plane_state->is_tiling_rotated = false;
6452         dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL;
6453
6454         dc_result = dc_validate_stream(dc, stream);
6455         if (dc_result == DC_OK)
6456                 dc_result = dc_validate_plane(dc, dc_plane_state);
6457
6458         if (dc_result == DC_OK)
6459                 dc_result = dc_add_stream_to_ctx(dc, dc_state, stream);
6460
6461         if (dc_result == DC_OK && !dc_add_plane_to_context(
6462                                                 dc,
6463                                                 stream,
6464                                                 dc_plane_state,
6465                                                 dc_state))
6466                 dc_result = DC_FAIL_ATTACH_SURFACES;
6467
6468         if (dc_result == DC_OK)
6469                 dc_result = dc_validate_global_state(dc, dc_state, true);
6470
6471 cleanup:
6472         if (dc_state)
6473                 dc_release_state(dc_state);
6474
6475         if (dc_plane_state)
6476                 dc_plane_state_release(dc_plane_state);
6477
6478         return dc_result;
6479 }
6480
6481 struct dc_stream_state *
6482 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6483                                 const struct drm_display_mode *drm_mode,
6484                                 const struct dm_connector_state *dm_state,
6485                                 const struct dc_stream_state *old_stream)
6486 {
6487         struct drm_connector *connector = &aconnector->base;
6488         struct amdgpu_device *adev = drm_to_adev(connector->dev);
6489         struct dc_stream_state *stream;
6490         const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL;
6491         int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8;
6492         enum dc_status dc_result = DC_OK;
6493
6494         do {
6495                 stream = create_stream_for_sink(aconnector, drm_mode,
6496                                                 dm_state, old_stream,
6497                                                 requested_bpc);
6498                 if (stream == NULL) {
6499                         DRM_ERROR("Failed to create stream for sink!\n");
6500                         break;
6501                 }
6502
6503                 dc_result = dc_validate_stream(adev->dm.dc, stream);
6504                 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
6505                         dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream);
6506
6507                 if (dc_result == DC_OK)
6508                         dc_result = dm_validate_stream_and_context(adev->dm.dc, stream);
6509
6510                 if (dc_result != DC_OK) {
6511                         DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",
6512                                       drm_mode->hdisplay,
6513                                       drm_mode->vdisplay,
6514                                       drm_mode->clock,
6515                                       dc_result,
6516                                       dc_status_to_str(dc_result));
6517
6518                         dc_stream_release(stream);
6519                         stream = NULL;
6520                         requested_bpc -= 2; /* lower bpc to retry validation */
6521                 }
6522
6523         } while (stream == NULL && requested_bpc >= 6);
6524
6525         if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) {
6526                 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n");
6527
6528                 aconnector->force_yuv420_output = true;
6529                 stream = create_validate_stream_for_sink(aconnector, drm_mode,
6530                                                 dm_state, old_stream);
6531                 aconnector->force_yuv420_output = false;
6532         }
6533
6534         return stream;
6535 }
6536
6537 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
6538                                    struct drm_display_mode *mode)
6539 {
6540         int result = MODE_ERROR;
6541         struct dc_sink *dc_sink;
6542         /* TODO: Unhardcode stream count */
6543         struct dc_stream_state *stream;
6544         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6545
6546         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
6547                         (mode->flags & DRM_MODE_FLAG_DBLSCAN))
6548                 return result;
6549
6550         /*
6551          * Only run this the first time mode_valid is called to initilialize
6552          * EDID mgmt
6553          */
6554         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
6555                 !aconnector->dc_em_sink)
6556                 handle_edid_mgmt(aconnector);
6557
6558         dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
6559
6560         if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL &&
6561                                 aconnector->base.force != DRM_FORCE_ON) {
6562                 DRM_ERROR("dc_sink is NULL!\n");
6563                 goto fail;
6564         }
6565
6566         stream = create_validate_stream_for_sink(aconnector, mode, NULL, NULL);
6567         if (stream) {
6568                 dc_stream_release(stream);
6569                 result = MODE_OK;
6570         }
6571
6572 fail:
6573         /* TODO: error handling*/
6574         return result;
6575 }
6576
6577 static int fill_hdr_info_packet(const struct drm_connector_state *state,
6578                                 struct dc_info_packet *out)
6579 {
6580         struct hdmi_drm_infoframe frame;
6581         unsigned char buf[30]; /* 26 + 4 */
6582         ssize_t len;
6583         int ret, i;
6584
6585         memset(out, 0, sizeof(*out));
6586
6587         if (!state->hdr_output_metadata)
6588                 return 0;
6589
6590         ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
6591         if (ret)
6592                 return ret;
6593
6594         len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
6595         if (len < 0)
6596                 return (int)len;
6597
6598         /* Static metadata is a fixed 26 bytes + 4 byte header. */
6599         if (len != 30)
6600                 return -EINVAL;
6601
6602         /* Prepare the infopacket for DC. */
6603         switch (state->connector->connector_type) {
6604         case DRM_MODE_CONNECTOR_HDMIA:
6605                 out->hb0 = 0x87; /* type */
6606                 out->hb1 = 0x01; /* version */
6607                 out->hb2 = 0x1A; /* length */
6608                 out->sb[0] = buf[3]; /* checksum */
6609                 i = 1;
6610                 break;
6611
6612         case DRM_MODE_CONNECTOR_DisplayPort:
6613         case DRM_MODE_CONNECTOR_eDP:
6614                 out->hb0 = 0x00; /* sdp id, zero */
6615                 out->hb1 = 0x87; /* type */
6616                 out->hb2 = 0x1D; /* payload len - 1 */
6617                 out->hb3 = (0x13 << 2); /* sdp version */
6618                 out->sb[0] = 0x01; /* version */
6619                 out->sb[1] = 0x1A; /* length */
6620                 i = 2;
6621                 break;
6622
6623         default:
6624                 return -EINVAL;
6625         }
6626
6627         memcpy(&out->sb[i], &buf[4], 26);
6628         out->valid = true;
6629
6630         print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
6631                        sizeof(out->sb), false);
6632
6633         return 0;
6634 }
6635
6636 static int
6637 amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
6638                                  struct drm_atomic_state *state)
6639 {
6640         struct drm_connector_state *new_con_state =
6641                 drm_atomic_get_new_connector_state(state, conn);
6642         struct drm_connector_state *old_con_state =
6643                 drm_atomic_get_old_connector_state(state, conn);
6644         struct drm_crtc *crtc = new_con_state->crtc;
6645         struct drm_crtc_state *new_crtc_state;
6646         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn);
6647         int ret;
6648
6649         trace_amdgpu_dm_connector_atomic_check(new_con_state);
6650
6651         if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
6652                 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr);
6653                 if (ret < 0)
6654                         return ret;
6655         }
6656
6657         if (!crtc)
6658                 return 0;
6659
6660         if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) {
6661                 struct dc_info_packet hdr_infopacket;
6662
6663                 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
6664                 if (ret)
6665                         return ret;
6666
6667                 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6668                 if (IS_ERR(new_crtc_state))
6669                         return PTR_ERR(new_crtc_state);
6670
6671                 /*
6672                  * DC considers the stream backends changed if the
6673                  * static metadata changes. Forcing the modeset also
6674                  * gives a simple way for userspace to switch from
6675                  * 8bpc to 10bpc when setting the metadata to enter
6676                  * or exit HDR.
6677                  *
6678                  * Changing the static metadata after it's been
6679                  * set is permissible, however. So only force a
6680                  * modeset if we're entering or exiting HDR.
6681                  */
6682                 new_crtc_state->mode_changed =
6683                         !old_con_state->hdr_output_metadata ||
6684                         !new_con_state->hdr_output_metadata;
6685         }
6686
6687         return 0;
6688 }
6689
6690 static const struct drm_connector_helper_funcs
6691 amdgpu_dm_connector_helper_funcs = {
6692         /*
6693          * If hotplugging a second bigger display in FB Con mode, bigger resolution
6694          * modes will be filtered by drm_mode_validate_size(), and those modes
6695          * are missing after user start lightdm. So we need to renew modes list.
6696          * in get_modes call back, not just return the modes count
6697          */
6698         .get_modes = get_modes,
6699         .mode_valid = amdgpu_dm_connector_mode_valid,
6700         .atomic_check = amdgpu_dm_connector_atomic_check,
6701 };
6702
6703 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
6704 {
6705
6706 }
6707
6708 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth)
6709 {
6710         switch (display_color_depth) {
6711         case COLOR_DEPTH_666:
6712                 return 6;
6713         case COLOR_DEPTH_888:
6714                 return 8;
6715         case COLOR_DEPTH_101010:
6716                 return 10;
6717         case COLOR_DEPTH_121212:
6718                 return 12;
6719         case COLOR_DEPTH_141414:
6720                 return 14;
6721         case COLOR_DEPTH_161616:
6722                 return 16;
6723         default:
6724                 break;
6725         }
6726         return 0;
6727 }
6728
6729 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
6730                                           struct drm_crtc_state *crtc_state,
6731                                           struct drm_connector_state *conn_state)
6732 {
6733         struct drm_atomic_state *state = crtc_state->state;
6734         struct drm_connector *connector = conn_state->connector;
6735         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6736         struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state);
6737         const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
6738         struct drm_dp_mst_topology_mgr *mst_mgr;
6739         struct drm_dp_mst_port *mst_port;
6740         struct drm_dp_mst_topology_state *mst_state;
6741         enum dc_color_depth color_depth;
6742         int clock, bpp = 0;
6743         bool is_y420 = false;
6744
6745         if (!aconnector->mst_output_port)
6746                 return 0;
6747
6748         mst_port = aconnector->mst_output_port;
6749         mst_mgr = &aconnector->mst_root->mst_mgr;
6750
6751         if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
6752                 return 0;
6753
6754         mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr);
6755         if (IS_ERR(mst_state))
6756                 return PTR_ERR(mst_state);
6757
6758         if (!mst_state->pbn_div)
6759                 mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link);
6760
6761         if (!state->duplicated) {
6762                 int max_bpc = conn_state->max_requested_bpc;
6763                 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
6764                           aconnector->force_yuv420_output;
6765                 color_depth = convert_color_depth_from_display_info(connector,
6766                                                                     is_y420,
6767                                                                     max_bpc);
6768                 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
6769                 clock = adjusted_mode->clock;
6770                 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
6771         }
6772
6773         dm_new_connector_state->vcpi_slots =
6774                 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port,
6775                                               dm_new_connector_state->pbn);
6776         if (dm_new_connector_state->vcpi_slots < 0) {
6777                 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
6778                 return dm_new_connector_state->vcpi_slots;
6779         }
6780         return 0;
6781 }
6782
6783 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
6784         .disable = dm_encoder_helper_disable,
6785         .atomic_check = dm_encoder_helper_atomic_check
6786 };
6787
6788 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
6789                                             struct dc_state *dc_state,
6790                                             struct dsc_mst_fairness_vars *vars)
6791 {
6792         struct dc_stream_state *stream = NULL;
6793         struct drm_connector *connector;
6794         struct drm_connector_state *new_con_state;
6795         struct amdgpu_dm_connector *aconnector;
6796         struct dm_connector_state *dm_conn_state;
6797         int i, j, ret;
6798         int vcpi, pbn_div, pbn, slot_num = 0;
6799
6800         for_each_new_connector_in_state(state, connector, new_con_state, i) {
6801
6802                 aconnector = to_amdgpu_dm_connector(connector);
6803
6804                 if (!aconnector->mst_output_port)
6805                         continue;
6806
6807                 if (!new_con_state || !new_con_state->crtc)
6808                         continue;
6809
6810                 dm_conn_state = to_dm_connector_state(new_con_state);
6811
6812                 for (j = 0; j < dc_state->stream_count; j++) {
6813                         stream = dc_state->streams[j];
6814                         if (!stream)
6815                                 continue;
6816
6817                         if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector)
6818                                 break;
6819
6820                         stream = NULL;
6821                 }
6822
6823                 if (!stream)
6824                         continue;
6825
6826                 pbn_div = dm_mst_get_pbn_divider(stream->link);
6827                 /* pbn is calculated by compute_mst_dsc_configs_for_state*/
6828                 for (j = 0; j < dc_state->stream_count; j++) {
6829                         if (vars[j].aconnector == aconnector) {
6830                                 pbn = vars[j].pbn;
6831                                 break;
6832                         }
6833                 }
6834
6835                 if (j == dc_state->stream_count)
6836                         continue;
6837
6838                 slot_num = DIV_ROUND_UP(pbn, pbn_div);
6839
6840                 if (stream->timing.flags.DSC != 1) {
6841                         dm_conn_state->pbn = pbn;
6842                         dm_conn_state->vcpi_slots = slot_num;
6843
6844                         ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port,
6845                                                            dm_conn_state->pbn, false);
6846                         if (ret < 0)
6847                                 return ret;
6848
6849                         continue;
6850                 }
6851
6852                 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true);
6853                 if (vcpi < 0)
6854                         return vcpi;
6855
6856                 dm_conn_state->pbn = pbn;
6857                 dm_conn_state->vcpi_slots = vcpi;
6858         }
6859         return 0;
6860 }
6861
6862 static int to_drm_connector_type(enum signal_type st)
6863 {
6864         switch (st) {
6865         case SIGNAL_TYPE_HDMI_TYPE_A:
6866                 return DRM_MODE_CONNECTOR_HDMIA;
6867         case SIGNAL_TYPE_EDP:
6868                 return DRM_MODE_CONNECTOR_eDP;
6869         case SIGNAL_TYPE_LVDS:
6870                 return DRM_MODE_CONNECTOR_LVDS;
6871         case SIGNAL_TYPE_RGB:
6872                 return DRM_MODE_CONNECTOR_VGA;
6873         case SIGNAL_TYPE_DISPLAY_PORT:
6874         case SIGNAL_TYPE_DISPLAY_PORT_MST:
6875                 return DRM_MODE_CONNECTOR_DisplayPort;
6876         case SIGNAL_TYPE_DVI_DUAL_LINK:
6877         case SIGNAL_TYPE_DVI_SINGLE_LINK:
6878                 return DRM_MODE_CONNECTOR_DVID;
6879         case SIGNAL_TYPE_VIRTUAL:
6880                 return DRM_MODE_CONNECTOR_VIRTUAL;
6881
6882         default:
6883                 return DRM_MODE_CONNECTOR_Unknown;
6884         }
6885 }
6886
6887 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
6888 {
6889         struct drm_encoder *encoder;
6890
6891         /* There is only one encoder per connector */
6892         drm_connector_for_each_possible_encoder(connector, encoder)
6893                 return encoder;
6894
6895         return NULL;
6896 }
6897
6898 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
6899 {
6900         struct drm_encoder *encoder;
6901         struct amdgpu_encoder *amdgpu_encoder;
6902
6903         encoder = amdgpu_dm_connector_to_encoder(connector);
6904
6905         if (encoder == NULL)
6906                 return;
6907
6908         amdgpu_encoder = to_amdgpu_encoder(encoder);
6909
6910         amdgpu_encoder->native_mode.clock = 0;
6911
6912         if (!list_empty(&connector->probed_modes)) {
6913                 struct drm_display_mode *preferred_mode = NULL;
6914
6915                 list_for_each_entry(preferred_mode,
6916                                     &connector->probed_modes,
6917                                     head) {
6918                         if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
6919                                 amdgpu_encoder->native_mode = *preferred_mode;
6920
6921                         break;
6922                 }
6923
6924         }
6925 }
6926
6927 static struct drm_display_mode *
6928 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
6929                              char *name,
6930                              int hdisplay, int vdisplay)
6931 {
6932         struct drm_device *dev = encoder->dev;
6933         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
6934         struct drm_display_mode *mode = NULL;
6935         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
6936
6937         mode = drm_mode_duplicate(dev, native_mode);
6938
6939         if (mode == NULL)
6940                 return NULL;
6941
6942         mode->hdisplay = hdisplay;
6943         mode->vdisplay = vdisplay;
6944         mode->type &= ~DRM_MODE_TYPE_PREFERRED;
6945         strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
6946
6947         return mode;
6948
6949 }
6950
6951 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
6952                                                  struct drm_connector *connector)
6953 {
6954         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
6955         struct drm_display_mode *mode = NULL;
6956         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
6957         struct amdgpu_dm_connector *amdgpu_dm_connector =
6958                                 to_amdgpu_dm_connector(connector);
6959         int i;
6960         int n;
6961         struct mode_size {
6962                 char name[DRM_DISPLAY_MODE_LEN];
6963                 int w;
6964                 int h;
6965         } common_modes[] = {
6966                 {  "640x480",  640,  480},
6967                 {  "800x600",  800,  600},
6968                 { "1024x768", 1024,  768},
6969                 { "1280x720", 1280,  720},
6970                 { "1280x800", 1280,  800},
6971                 {"1280x1024", 1280, 1024},
6972                 { "1440x900", 1440,  900},
6973                 {"1680x1050", 1680, 1050},
6974                 {"1600x1200", 1600, 1200},
6975                 {"1920x1080", 1920, 1080},
6976                 {"1920x1200", 1920, 1200}
6977         };
6978
6979         n = ARRAY_SIZE(common_modes);
6980
6981         for (i = 0; i < n; i++) {
6982                 struct drm_display_mode *curmode = NULL;
6983                 bool mode_existed = false;
6984
6985                 if (common_modes[i].w > native_mode->hdisplay ||
6986                     common_modes[i].h > native_mode->vdisplay ||
6987                    (common_modes[i].w == native_mode->hdisplay &&
6988                     common_modes[i].h == native_mode->vdisplay))
6989                         continue;
6990
6991                 list_for_each_entry(curmode, &connector->probed_modes, head) {
6992                         if (common_modes[i].w == curmode->hdisplay &&
6993                             common_modes[i].h == curmode->vdisplay) {
6994                                 mode_existed = true;
6995                                 break;
6996                         }
6997                 }
6998
6999                 if (mode_existed)
7000                         continue;
7001
7002                 mode = amdgpu_dm_create_common_mode(encoder,
7003                                 common_modes[i].name, common_modes[i].w,
7004                                 common_modes[i].h);
7005                 if (!mode)
7006                         continue;
7007
7008                 drm_mode_probed_add(connector, mode);
7009                 amdgpu_dm_connector->num_modes++;
7010         }
7011 }
7012
7013 static void amdgpu_set_panel_orientation(struct drm_connector *connector)
7014 {
7015         struct drm_encoder *encoder;
7016         struct amdgpu_encoder *amdgpu_encoder;
7017         const struct drm_display_mode *native_mode;
7018
7019         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
7020             connector->connector_type != DRM_MODE_CONNECTOR_LVDS)
7021                 return;
7022
7023         mutex_lock(&connector->dev->mode_config.mutex);
7024         amdgpu_dm_connector_get_modes(connector);
7025         mutex_unlock(&connector->dev->mode_config.mutex);
7026
7027         encoder = amdgpu_dm_connector_to_encoder(connector);
7028         if (!encoder)
7029                 return;
7030
7031         amdgpu_encoder = to_amdgpu_encoder(encoder);
7032
7033         native_mode = &amdgpu_encoder->native_mode;
7034         if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0)
7035                 return;
7036
7037         drm_connector_set_panel_orientation_with_quirk(connector,
7038                                                        DRM_MODE_PANEL_ORIENTATION_UNKNOWN,
7039                                                        native_mode->hdisplay,
7040                                                        native_mode->vdisplay);
7041 }
7042
7043 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
7044                                               struct edid *edid)
7045 {
7046         struct amdgpu_dm_connector *amdgpu_dm_connector =
7047                         to_amdgpu_dm_connector(connector);
7048
7049         if (edid) {
7050                 /* empty probed_modes */
7051                 INIT_LIST_HEAD(&connector->probed_modes);
7052                 amdgpu_dm_connector->num_modes =
7053                                 drm_add_edid_modes(connector, edid);
7054
7055                 /* sorting the probed modes before calling function
7056                  * amdgpu_dm_get_native_mode() since EDID can have
7057                  * more than one preferred mode. The modes that are
7058                  * later in the probed mode list could be of higher
7059                  * and preferred resolution. For example, 3840x2160
7060                  * resolution in base EDID preferred timing and 4096x2160
7061                  * preferred resolution in DID extension block later.
7062                  */
7063                 drm_mode_sort(&connector->probed_modes);
7064                 amdgpu_dm_get_native_mode(connector);
7065
7066                 /* Freesync capabilities are reset by calling
7067                  * drm_add_edid_modes() and need to be
7068                  * restored here.
7069                  */
7070                 amdgpu_dm_update_freesync_caps(connector, edid);
7071         } else {
7072                 amdgpu_dm_connector->num_modes = 0;
7073         }
7074 }
7075
7076 static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector,
7077                               struct drm_display_mode *mode)
7078 {
7079         struct drm_display_mode *m;
7080
7081         list_for_each_entry (m, &aconnector->base.probed_modes, head) {
7082                 if (drm_mode_equal(m, mode))
7083                         return true;
7084         }
7085
7086         return false;
7087 }
7088
7089 static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)
7090 {
7091         const struct drm_display_mode *m;
7092         struct drm_display_mode *new_mode;
7093         uint i;
7094         u32 new_modes_count = 0;
7095
7096         /* Standard FPS values
7097          *
7098          * 23.976       - TV/NTSC
7099          * 24           - Cinema
7100          * 25           - TV/PAL
7101          * 29.97        - TV/NTSC
7102          * 30           - TV/NTSC
7103          * 48           - Cinema HFR
7104          * 50           - TV/PAL
7105          * 60           - Commonly used
7106          * 48,72,96,120 - Multiples of 24
7107          */
7108         static const u32 common_rates[] = {
7109                 23976, 24000, 25000, 29970, 30000,
7110                 48000, 50000, 60000, 72000, 96000, 120000
7111         };
7112
7113         /*
7114          * Find mode with highest refresh rate with the same resolution
7115          * as the preferred mode. Some monitors report a preferred mode
7116          * with lower resolution than the highest refresh rate supported.
7117          */
7118
7119         m = get_highest_refresh_rate_mode(aconnector, true);
7120         if (!m)
7121                 return 0;
7122
7123         for (i = 0; i < ARRAY_SIZE(common_rates); i++) {
7124                 u64 target_vtotal, target_vtotal_diff;
7125                 u64 num, den;
7126
7127                 if (drm_mode_vrefresh(m) * 1000 < common_rates[i])
7128                         continue;
7129
7130                 if (common_rates[i] < aconnector->min_vfreq * 1000 ||
7131                     common_rates[i] > aconnector->max_vfreq * 1000)
7132                         continue;
7133
7134                 num = (unsigned long long)m->clock * 1000 * 1000;
7135                 den = common_rates[i] * (unsigned long long)m->htotal;
7136                 target_vtotal = div_u64(num, den);
7137                 target_vtotal_diff = target_vtotal - m->vtotal;
7138
7139                 /* Check for illegal modes */
7140                 if (m->vsync_start + target_vtotal_diff < m->vdisplay ||
7141                     m->vsync_end + target_vtotal_diff < m->vsync_start ||
7142                     m->vtotal + target_vtotal_diff < m->vsync_end)
7143                         continue;
7144
7145                 new_mode = drm_mode_duplicate(aconnector->base.dev, m);
7146                 if (!new_mode)
7147                         goto out;
7148
7149                 new_mode->vtotal += (u16)target_vtotal_diff;
7150                 new_mode->vsync_start += (u16)target_vtotal_diff;
7151                 new_mode->vsync_end += (u16)target_vtotal_diff;
7152                 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7153                 new_mode->type |= DRM_MODE_TYPE_DRIVER;
7154
7155                 if (!is_duplicate_mode(aconnector, new_mode)) {
7156                         drm_mode_probed_add(&aconnector->base, new_mode);
7157                         new_modes_count += 1;
7158                 } else
7159                         drm_mode_destroy(aconnector->base.dev, new_mode);
7160         }
7161  out:
7162         return new_modes_count;
7163 }
7164
7165 static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector,
7166                                                    struct edid *edid)
7167 {
7168         struct amdgpu_dm_connector *amdgpu_dm_connector =
7169                 to_amdgpu_dm_connector(connector);
7170
7171         if (!(amdgpu_freesync_vid_mode && edid))
7172                 return;
7173
7174         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
7175                 amdgpu_dm_connector->num_modes +=
7176                         add_fs_modes(amdgpu_dm_connector);
7177 }
7178
7179 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
7180 {
7181         struct amdgpu_dm_connector *amdgpu_dm_connector =
7182                         to_amdgpu_dm_connector(connector);
7183         struct drm_encoder *encoder;
7184         struct edid *edid = amdgpu_dm_connector->edid;
7185         struct dc_link_settings *verified_link_cap =
7186                         &amdgpu_dm_connector->dc_link->verified_link_cap;
7187         const struct dc *dc = amdgpu_dm_connector->dc_link->dc;
7188
7189         encoder = amdgpu_dm_connector_to_encoder(connector);
7190
7191         if (!drm_edid_is_valid(edid)) {
7192                 amdgpu_dm_connector->num_modes =
7193                                 drm_add_modes_noedid(connector, 640, 480);
7194                 if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING)
7195                         amdgpu_dm_connector->num_modes +=
7196                                 drm_add_modes_noedid(connector, 1920, 1080);
7197         } else {
7198                 amdgpu_dm_connector_ddc_get_modes(connector, edid);
7199                 amdgpu_dm_connector_add_common_modes(encoder, connector);
7200                 amdgpu_dm_connector_add_freesync_modes(connector, edid);
7201         }
7202         amdgpu_dm_fbc_init(connector);
7203
7204         return amdgpu_dm_connector->num_modes;
7205 }
7206
7207 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
7208                                      struct amdgpu_dm_connector *aconnector,
7209                                      int connector_type,
7210                                      struct dc_link *link,
7211                                      int link_index)
7212 {
7213         struct amdgpu_device *adev = drm_to_adev(dm->ddev);
7214
7215         /*
7216          * Some of the properties below require access to state, like bpc.
7217          * Allocate some default initial connector state with our reset helper.
7218          */
7219         if (aconnector->base.funcs->reset)
7220                 aconnector->base.funcs->reset(&aconnector->base);
7221
7222         aconnector->connector_id = link_index;
7223         aconnector->bl_idx = -1;
7224         aconnector->dc_link = link;
7225         aconnector->base.interlace_allowed = false;
7226         aconnector->base.doublescan_allowed = false;
7227         aconnector->base.stereo_allowed = false;
7228         aconnector->base.dpms = DRM_MODE_DPMS_OFF;
7229         aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
7230         aconnector->audio_inst = -1;
7231         aconnector->pack_sdp_v1_3 = false;
7232         aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE;
7233         memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info));
7234         mutex_init(&aconnector->hpd_lock);
7235
7236         /*
7237          * configure support HPD hot plug connector_>polled default value is 0
7238          * which means HPD hot plug not supported
7239          */
7240         switch (connector_type) {
7241         case DRM_MODE_CONNECTOR_HDMIA:
7242                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7243                 aconnector->base.ycbcr_420_allowed =
7244                         link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
7245                 break;
7246         case DRM_MODE_CONNECTOR_DisplayPort:
7247                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7248                 link->link_enc = link_enc_cfg_get_link_enc(link);
7249                 ASSERT(link->link_enc);
7250                 if (link->link_enc)
7251                         aconnector->base.ycbcr_420_allowed =
7252                         link->link_enc->features.dp_ycbcr420_supported ? true : false;
7253                 break;
7254         case DRM_MODE_CONNECTOR_DVID:
7255                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7256                 break;
7257         default:
7258                 break;
7259         }
7260
7261         drm_object_attach_property(&aconnector->base.base,
7262                                 dm->ddev->mode_config.scaling_mode_property,
7263                                 DRM_MODE_SCALE_NONE);
7264
7265         drm_object_attach_property(&aconnector->base.base,
7266                                 adev->mode_info.underscan_property,
7267                                 UNDERSCAN_OFF);
7268         drm_object_attach_property(&aconnector->base.base,
7269                                 adev->mode_info.underscan_hborder_property,
7270                                 0);
7271         drm_object_attach_property(&aconnector->base.base,
7272                                 adev->mode_info.underscan_vborder_property,
7273                                 0);
7274
7275         if (!aconnector->mst_root)
7276                 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
7277
7278         aconnector->base.state->max_bpc = 16;
7279         aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
7280
7281         if (connector_type == DRM_MODE_CONNECTOR_eDP &&
7282             (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) {
7283                 drm_object_attach_property(&aconnector->base.base,
7284                                 adev->mode_info.abm_level_property, 0);
7285         }
7286
7287         if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
7288             connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
7289             connector_type == DRM_MODE_CONNECTOR_eDP) {
7290                 drm_connector_attach_hdr_output_metadata_property(&aconnector->base);
7291
7292                 if (!aconnector->mst_root)
7293                         drm_connector_attach_vrr_capable_property(&aconnector->base);
7294
7295                 if (adev->dm.hdcp_workqueue)
7296                         drm_connector_attach_content_protection_property(&aconnector->base, true);
7297         }
7298 }
7299
7300 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
7301                               struct i2c_msg *msgs, int num)
7302 {
7303         struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
7304         struct ddc_service *ddc_service = i2c->ddc_service;
7305         struct i2c_command cmd;
7306         int i;
7307         int result = -EIO;
7308
7309         cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
7310
7311         if (!cmd.payloads)
7312                 return result;
7313
7314         cmd.number_of_payloads = num;
7315         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
7316         cmd.speed = 100;
7317
7318         for (i = 0; i < num; i++) {
7319                 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
7320                 cmd.payloads[i].address = msgs[i].addr;
7321                 cmd.payloads[i].length = msgs[i].len;
7322                 cmd.payloads[i].data = msgs[i].buf;
7323         }
7324
7325         if (dc_submit_i2c(
7326                         ddc_service->ctx->dc,
7327                         ddc_service->link->link_index,
7328                         &cmd))
7329                 result = num;
7330
7331         kfree(cmd.payloads);
7332         return result;
7333 }
7334
7335 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
7336 {
7337         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
7338 }
7339
7340 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
7341         .master_xfer = amdgpu_dm_i2c_xfer,
7342         .functionality = amdgpu_dm_i2c_func,
7343 };
7344
7345 static struct amdgpu_i2c_adapter *
7346 create_i2c(struct ddc_service *ddc_service,
7347            int link_index,
7348            int *res)
7349 {
7350         struct amdgpu_device *adev = ddc_service->ctx->driver_context;
7351         struct amdgpu_i2c_adapter *i2c;
7352
7353         i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
7354         if (!i2c)
7355                 return NULL;
7356         i2c->base.owner = THIS_MODULE;
7357         i2c->base.class = I2C_CLASS_DDC;
7358         i2c->base.dev.parent = &adev->pdev->dev;
7359         i2c->base.algo = &amdgpu_dm_i2c_algo;
7360         snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
7361         i2c_set_adapdata(&i2c->base, i2c);
7362         i2c->ddc_service = ddc_service;
7363
7364         return i2c;
7365 }
7366
7367
7368 /*
7369  * Note: this function assumes that dc_link_detect() was called for the
7370  * dc_link which will be represented by this aconnector.
7371  */
7372 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
7373                                     struct amdgpu_dm_connector *aconnector,
7374                                     u32 link_index,
7375                                     struct amdgpu_encoder *aencoder)
7376 {
7377         int res = 0;
7378         int connector_type;
7379         struct dc *dc = dm->dc;
7380         struct dc_link *link = dc_get_link_at_index(dc, link_index);
7381         struct amdgpu_i2c_adapter *i2c;
7382
7383         link->priv = aconnector;
7384
7385         DRM_DEBUG_DRIVER("%s()\n", __func__);
7386
7387         i2c = create_i2c(link->ddc, link->link_index, &res);
7388         if (!i2c) {
7389                 DRM_ERROR("Failed to create i2c adapter data\n");
7390                 return -ENOMEM;
7391         }
7392
7393         aconnector->i2c = i2c;
7394         res = i2c_add_adapter(&i2c->base);
7395
7396         if (res) {
7397                 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
7398                 goto out_free;
7399         }
7400
7401         connector_type = to_drm_connector_type(link->connector_signal);
7402
7403         res = drm_connector_init_with_ddc(
7404                         dm->ddev,
7405                         &aconnector->base,
7406                         &amdgpu_dm_connector_funcs,
7407                         connector_type,
7408                         &i2c->base);
7409
7410         if (res) {
7411                 DRM_ERROR("connector_init failed\n");
7412                 aconnector->connector_id = -1;
7413                 goto out_free;
7414         }
7415
7416         drm_connector_helper_add(
7417                         &aconnector->base,
7418                         &amdgpu_dm_connector_helper_funcs);
7419
7420         amdgpu_dm_connector_init_helper(
7421                 dm,
7422                 aconnector,
7423                 connector_type,
7424                 link,
7425                 link_index);
7426
7427         drm_connector_attach_encoder(
7428                 &aconnector->base, &aencoder->base);
7429
7430         if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
7431                 || connector_type == DRM_MODE_CONNECTOR_eDP)
7432                 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);
7433
7434 out_free:
7435         if (res) {
7436                 kfree(i2c);
7437                 aconnector->i2c = NULL;
7438         }
7439         return res;
7440 }
7441
7442 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
7443 {
7444         switch (adev->mode_info.num_crtc) {
7445         case 1:
7446                 return 0x1;
7447         case 2:
7448                 return 0x3;
7449         case 3:
7450                 return 0x7;
7451         case 4:
7452                 return 0xf;
7453         case 5:
7454                 return 0x1f;
7455         case 6:
7456         default:
7457                 return 0x3f;
7458         }
7459 }
7460
7461 static int amdgpu_dm_encoder_init(struct drm_device *dev,
7462                                   struct amdgpu_encoder *aencoder,
7463                                   uint32_t link_index)
7464 {
7465         struct amdgpu_device *adev = drm_to_adev(dev);
7466
7467         int res = drm_encoder_init(dev,
7468                                    &aencoder->base,
7469                                    &amdgpu_dm_encoder_funcs,
7470                                    DRM_MODE_ENCODER_TMDS,
7471                                    NULL);
7472
7473         aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
7474
7475         if (!res)
7476                 aencoder->encoder_id = link_index;
7477         else
7478                 aencoder->encoder_id = -1;
7479
7480         drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
7481
7482         return res;
7483 }
7484
7485 static void manage_dm_interrupts(struct amdgpu_device *adev,
7486                                  struct amdgpu_crtc *acrtc,
7487                                  bool enable)
7488 {
7489         /*
7490          * We have no guarantee that the frontend index maps to the same
7491          * backend index - some even map to more than one.
7492          *
7493          * TODO: Use a different interrupt or check DC itself for the mapping.
7494          */
7495         int irq_type =
7496                 amdgpu_display_crtc_idx_to_irq_type(
7497                         adev,
7498                         acrtc->crtc_id);
7499
7500         if (enable) {
7501                 drm_crtc_vblank_on(&acrtc->base);
7502                 amdgpu_irq_get(
7503                         adev,
7504                         &adev->pageflip_irq,
7505                         irq_type);
7506 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7507                 amdgpu_irq_get(
7508                         adev,
7509                         &adev->vline0_irq,
7510                         irq_type);
7511 #endif
7512         } else {
7513 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7514                 amdgpu_irq_put(
7515                         adev,
7516                         &adev->vline0_irq,
7517                         irq_type);
7518 #endif
7519                 amdgpu_irq_put(
7520                         adev,
7521                         &adev->pageflip_irq,
7522                         irq_type);
7523                 drm_crtc_vblank_off(&acrtc->base);
7524         }
7525 }
7526
7527 static void dm_update_pflip_irq_state(struct amdgpu_device *adev,
7528                                       struct amdgpu_crtc *acrtc)
7529 {
7530         int irq_type =
7531                 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
7532
7533         /**
7534          * This reads the current state for the IRQ and force reapplies
7535          * the setting to hardware.
7536          */
7537         amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type);
7538 }
7539
7540 static bool
7541 is_scaling_state_different(const struct dm_connector_state *dm_state,
7542                            const struct dm_connector_state *old_dm_state)
7543 {
7544         if (dm_state->scaling != old_dm_state->scaling)
7545                 return true;
7546         if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
7547                 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
7548                         return true;
7549         } else  if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
7550                 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
7551                         return true;
7552         } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
7553                    dm_state->underscan_vborder != old_dm_state->underscan_vborder)
7554                 return true;
7555         return false;
7556 }
7557
7558 static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state,
7559                                             struct drm_crtc_state *old_crtc_state,
7560                                             struct drm_connector_state *new_conn_state,
7561                                             struct drm_connector_state *old_conn_state,
7562                                             const struct drm_connector *connector,
7563                                             struct hdcp_workqueue *hdcp_w)
7564 {
7565         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7566         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
7567
7568         pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
7569                 connector->index, connector->status, connector->dpms);
7570         pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
7571                 old_conn_state->content_protection, new_conn_state->content_protection);
7572
7573         if (old_crtc_state)
7574                 pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7575                 old_crtc_state->enable,
7576                 old_crtc_state->active,
7577                 old_crtc_state->mode_changed,
7578                 old_crtc_state->active_changed,
7579                 old_crtc_state->connectors_changed);
7580
7581         if (new_crtc_state)
7582                 pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7583                 new_crtc_state->enable,
7584                 new_crtc_state->active,
7585                 new_crtc_state->mode_changed,
7586                 new_crtc_state->active_changed,
7587                 new_crtc_state->connectors_changed);
7588
7589         /* hdcp content type change */
7590         if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type &&
7591             new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
7592                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7593                 pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__);
7594                 return true;
7595         }
7596
7597         /* CP is being re enabled, ignore this */
7598         if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
7599             new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7600                 if (new_crtc_state && new_crtc_state->mode_changed) {
7601                         new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7602                         pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__);
7603                         return true;
7604                 }
7605                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
7606                 pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__);
7607                 return false;
7608         }
7609
7610         /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED
7611          *
7612          * Handles:     UNDESIRED -> ENABLED
7613          */
7614         if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
7615             new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
7616                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7617
7618         /* Stream removed and re-enabled
7619          *
7620          * Can sometimes overlap with the HPD case,
7621          * thus set update_hdcp to false to avoid
7622          * setting HDCP multiple times.
7623          *
7624          * Handles:     DESIRED -> DESIRED (Special case)
7625          */
7626         if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) &&
7627                 new_conn_state->crtc && new_conn_state->crtc->enabled &&
7628                 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7629                 dm_con_state->update_hdcp = false;
7630                 pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n",
7631                         __func__);
7632                 return true;
7633         }
7634
7635         /* Hot-plug, headless s3, dpms
7636          *
7637          * Only start HDCP if the display is connected/enabled.
7638          * update_hdcp flag will be set to false until the next
7639          * HPD comes in.
7640          *
7641          * Handles:     DESIRED -> DESIRED (Special case)
7642          */
7643         if (dm_con_state->update_hdcp &&
7644         new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
7645         connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
7646                 dm_con_state->update_hdcp = false;
7647                 pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n",
7648                         __func__);
7649                 return true;
7650         }
7651
7652         if (old_conn_state->content_protection == new_conn_state->content_protection) {
7653                 if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7654                         if (new_crtc_state && new_crtc_state->mode_changed) {
7655                                 pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n",
7656                                         __func__);
7657                                 return true;
7658                         }
7659                         pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n",
7660                                 __func__);
7661                         return false;
7662                 }
7663
7664                 pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__);
7665                 return false;
7666         }
7667
7668         if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) {
7669                 pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n",
7670                         __func__);
7671                 return true;
7672         }
7673
7674         pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__);
7675         return false;
7676 }
7677
7678 static void remove_stream(struct amdgpu_device *adev,
7679                           struct amdgpu_crtc *acrtc,
7680                           struct dc_stream_state *stream)
7681 {
7682         /* this is the update mode case */
7683
7684         acrtc->otg_inst = -1;
7685         acrtc->enabled = false;
7686 }
7687
7688 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
7689 {
7690
7691         assert_spin_locked(&acrtc->base.dev->event_lock);
7692         WARN_ON(acrtc->event);
7693
7694         acrtc->event = acrtc->base.state->event;
7695
7696         /* Set the flip status */
7697         acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
7698
7699         /* Mark this event as consumed */
7700         acrtc->base.state->event = NULL;
7701
7702         DC_LOG_PFLIP("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
7703                      acrtc->crtc_id);
7704 }
7705
7706 static void update_freesync_state_on_stream(
7707         struct amdgpu_display_manager *dm,
7708         struct dm_crtc_state *new_crtc_state,
7709         struct dc_stream_state *new_stream,
7710         struct dc_plane_state *surface,
7711         u32 flip_timestamp_in_us)
7712 {
7713         struct mod_vrr_params vrr_params;
7714         struct dc_info_packet vrr_infopacket = {0};
7715         struct amdgpu_device *adev = dm->adev;
7716         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7717         unsigned long flags;
7718         bool pack_sdp_v1_3 = false;
7719         struct amdgpu_dm_connector *aconn;
7720         enum vrr_packet_type packet_type = PACKET_TYPE_VRR;
7721
7722         if (!new_stream)
7723                 return;
7724
7725         /*
7726          * TODO: Determine why min/max totals and vrefresh can be 0 here.
7727          * For now it's sufficient to just guard against these conditions.
7728          */
7729
7730         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7731                 return;
7732
7733         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7734         vrr_params = acrtc->dm_irq_params.vrr_params;
7735
7736         if (surface) {
7737                 mod_freesync_handle_preflip(
7738                         dm->freesync_module,
7739                         surface,
7740                         new_stream,
7741                         flip_timestamp_in_us,
7742                         &vrr_params);
7743
7744                 if (adev->family < AMDGPU_FAMILY_AI &&
7745                     amdgpu_dm_crtc_vrr_active(new_crtc_state)) {
7746                         mod_freesync_handle_v_update(dm->freesync_module,
7747                                                      new_stream, &vrr_params);
7748
7749                         /* Need to call this before the frame ends. */
7750                         dc_stream_adjust_vmin_vmax(dm->dc,
7751                                                    new_crtc_state->stream,
7752                                                    &vrr_params.adjust);
7753                 }
7754         }
7755
7756         aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context;
7757
7758         if (aconn && aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {
7759                 pack_sdp_v1_3 = aconn->pack_sdp_v1_3;
7760
7761                 if (aconn->vsdb_info.amd_vsdb_version == 1)
7762                         packet_type = PACKET_TYPE_FS_V1;
7763                 else if (aconn->vsdb_info.amd_vsdb_version == 2)
7764                         packet_type = PACKET_TYPE_FS_V2;
7765                 else if (aconn->vsdb_info.amd_vsdb_version == 3)
7766                         packet_type = PACKET_TYPE_FS_V3;
7767
7768                 mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL,
7769                                         &new_stream->adaptive_sync_infopacket);
7770         }
7771
7772         mod_freesync_build_vrr_infopacket(
7773                 dm->freesync_module,
7774                 new_stream,
7775                 &vrr_params,
7776                 packet_type,
7777                 TRANSFER_FUNC_UNKNOWN,
7778                 &vrr_infopacket,
7779                 pack_sdp_v1_3);
7780
7781         new_crtc_state->freesync_vrr_info_changed |=
7782                 (memcmp(&new_crtc_state->vrr_infopacket,
7783                         &vrr_infopacket,
7784                         sizeof(vrr_infopacket)) != 0);
7785
7786         acrtc->dm_irq_params.vrr_params = vrr_params;
7787         new_crtc_state->vrr_infopacket = vrr_infopacket;
7788
7789         new_stream->vrr_infopacket = vrr_infopacket;
7790         new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params);
7791
7792         if (new_crtc_state->freesync_vrr_info_changed)
7793                 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
7794                               new_crtc_state->base.crtc->base.id,
7795                               (int)new_crtc_state->base.vrr_enabled,
7796                               (int)vrr_params.state);
7797
7798         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7799 }
7800
7801 static void update_stream_irq_parameters(
7802         struct amdgpu_display_manager *dm,
7803         struct dm_crtc_state *new_crtc_state)
7804 {
7805         struct dc_stream_state *new_stream = new_crtc_state->stream;
7806         struct mod_vrr_params vrr_params;
7807         struct mod_freesync_config config = new_crtc_state->freesync_config;
7808         struct amdgpu_device *adev = dm->adev;
7809         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7810         unsigned long flags;
7811
7812         if (!new_stream)
7813                 return;
7814
7815         /*
7816          * TODO: Determine why min/max totals and vrefresh can be 0 here.
7817          * For now it's sufficient to just guard against these conditions.
7818          */
7819         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7820                 return;
7821
7822         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7823         vrr_params = acrtc->dm_irq_params.vrr_params;
7824
7825         if (new_crtc_state->vrr_supported &&
7826             config.min_refresh_in_uhz &&
7827             config.max_refresh_in_uhz) {
7828                 /*
7829                  * if freesync compatible mode was set, config.state will be set
7830                  * in atomic check
7831                  */
7832                 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz &&
7833                     (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) ||
7834                      new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) {
7835                         vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz;
7836                         vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz;
7837                         vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz;
7838                         vrr_params.state = VRR_STATE_ACTIVE_FIXED;
7839                 } else {
7840                         config.state = new_crtc_state->base.vrr_enabled ?
7841                                                      VRR_STATE_ACTIVE_VARIABLE :
7842                                                      VRR_STATE_INACTIVE;
7843                 }
7844         } else {
7845                 config.state = VRR_STATE_UNSUPPORTED;
7846         }
7847
7848         mod_freesync_build_vrr_params(dm->freesync_module,
7849                                       new_stream,
7850                                       &config, &vrr_params);
7851
7852         new_crtc_state->freesync_config = config;
7853         /* Copy state for access from DM IRQ handler */
7854         acrtc->dm_irq_params.freesync_config = config;
7855         acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes;
7856         acrtc->dm_irq_params.vrr_params = vrr_params;
7857         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7858 }
7859
7860 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
7861                                             struct dm_crtc_state *new_state)
7862 {
7863         bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state);
7864         bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state);
7865
7866         if (!old_vrr_active && new_vrr_active) {
7867                 /* Transition VRR inactive -> active:
7868                  * While VRR is active, we must not disable vblank irq, as a
7869                  * reenable after disable would compute bogus vblank/pflip
7870                  * timestamps if it likely happened inside display front-porch.
7871                  *
7872                  * We also need vupdate irq for the actual core vblank handling
7873                  * at end of vblank.
7874                  */
7875                 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0);
7876                 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0);
7877                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
7878                                  __func__, new_state->base.crtc->base.id);
7879         } else if (old_vrr_active && !new_vrr_active) {
7880                 /* Transition VRR active -> inactive:
7881                  * Allow vblank irq disable again for fixed refresh rate.
7882                  */
7883                 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0);
7884                 drm_crtc_vblank_put(new_state->base.crtc);
7885                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
7886                                  __func__, new_state->base.crtc->base.id);
7887         }
7888 }
7889
7890 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
7891 {
7892         struct drm_plane *plane;
7893         struct drm_plane_state *old_plane_state;
7894         int i;
7895
7896         /*
7897          * TODO: Make this per-stream so we don't issue redundant updates for
7898          * commits with multiple streams.
7899          */
7900         for_each_old_plane_in_state(state, plane, old_plane_state, i)
7901                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
7902                         amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state);
7903 }
7904
7905 static inline uint32_t get_mem_type(struct drm_framebuffer *fb)
7906 {
7907         struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]);
7908
7909         return abo->tbo.resource ? abo->tbo.resource->mem_type : 0;
7910 }
7911
7912 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
7913                                     struct dc_state *dc_state,
7914                                     struct drm_device *dev,
7915                                     struct amdgpu_display_manager *dm,
7916                                     struct drm_crtc *pcrtc,
7917                                     bool wait_for_vblank)
7918 {
7919         u32 i;
7920         u64 timestamp_ns = ktime_get_ns();
7921         struct drm_plane *plane;
7922         struct drm_plane_state *old_plane_state, *new_plane_state;
7923         struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
7924         struct drm_crtc_state *new_pcrtc_state =
7925                         drm_atomic_get_new_crtc_state(state, pcrtc);
7926         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
7927         struct dm_crtc_state *dm_old_crtc_state =
7928                         to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
7929         int planes_count = 0, vpos, hpos;
7930         unsigned long flags;
7931         u32 target_vblank, last_flip_vblank;
7932         bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state);
7933         bool cursor_update = false;
7934         bool pflip_present = false;
7935         bool dirty_rects_changed = false;
7936         struct {
7937                 struct dc_surface_update surface_updates[MAX_SURFACES];
7938                 struct dc_plane_info plane_infos[MAX_SURFACES];
7939                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
7940                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
7941                 struct dc_stream_update stream_update;
7942         } *bundle;
7943
7944         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
7945
7946         if (!bundle) {
7947                 dm_error("Failed to allocate update bundle\n");
7948                 goto cleanup;
7949         }
7950
7951         /*
7952          * Disable the cursor first if we're disabling all the planes.
7953          * It'll remain on the screen after the planes are re-enabled
7954          * if we don't.
7955          */
7956         if (acrtc_state->active_planes == 0)
7957                 amdgpu_dm_commit_cursors(state);
7958
7959         /* update planes when needed */
7960         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
7961                 struct drm_crtc *crtc = new_plane_state->crtc;
7962                 struct drm_crtc_state *new_crtc_state;
7963                 struct drm_framebuffer *fb = new_plane_state->fb;
7964                 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb;
7965                 bool plane_needs_flip;
7966                 struct dc_plane_state *dc_plane;
7967                 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
7968
7969                 /* Cursor plane is handled after stream updates */
7970                 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
7971                         if ((fb && crtc == pcrtc) ||
7972                             (old_plane_state->fb && old_plane_state->crtc == pcrtc))
7973                                 cursor_update = true;
7974
7975                         continue;
7976                 }
7977
7978                 if (!fb || !crtc || pcrtc != crtc)
7979                         continue;
7980
7981                 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
7982                 if (!new_crtc_state->active)
7983                         continue;
7984
7985                 dc_plane = dm_new_plane_state->dc_state;
7986                 if (!dc_plane)
7987                         continue;
7988
7989                 bundle->surface_updates[planes_count].surface = dc_plane;
7990                 if (new_pcrtc_state->color_mgmt_changed) {
7991                         bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
7992                         bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
7993                         bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;
7994                 }
7995
7996                 amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state,
7997                                      &bundle->scaling_infos[planes_count]);
7998
7999                 bundle->surface_updates[planes_count].scaling_info =
8000                         &bundle->scaling_infos[planes_count];
8001
8002                 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
8003
8004                 pflip_present = pflip_present || plane_needs_flip;
8005
8006                 if (!plane_needs_flip) {
8007                         planes_count += 1;
8008                         continue;
8009                 }
8010
8011                 fill_dc_plane_info_and_addr(
8012                         dm->adev, new_plane_state,
8013                         afb->tiling_flags,
8014                         &bundle->plane_infos[planes_count],
8015                         &bundle->flip_addrs[planes_count].address,
8016                         afb->tmz_surface, false);
8017
8018                 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n",
8019                                  new_plane_state->plane->index,
8020                                  bundle->plane_infos[planes_count].dcc.enable);
8021
8022                 bundle->surface_updates[planes_count].plane_info =
8023                         &bundle->plane_infos[planes_count];
8024
8025                 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8026                         fill_dc_dirty_rects(plane, old_plane_state,
8027                                             new_plane_state, new_crtc_state,
8028                                             &bundle->flip_addrs[planes_count],
8029                                             &dirty_rects_changed);
8030
8031                         /*
8032                          * If the dirty regions changed, PSR-SU need to be disabled temporarily
8033                          * and enabled it again after dirty regions are stable to avoid video glitch.
8034                          * PSR-SU will be enabled in vblank_control_worker() if user pause the video
8035                          * during the PSR-SU was disabled.
8036                          */
8037                         if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8038                             acrtc_attach->dm_irq_params.allow_psr_entry &&
8039 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8040                             !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8041 #endif
8042                             dirty_rects_changed) {
8043                                 mutex_lock(&dm->dc_lock);
8044                                 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns =
8045                                 timestamp_ns;
8046                                 if (acrtc_state->stream->link->psr_settings.psr_allow_active)
8047                                         amdgpu_dm_psr_disable(acrtc_state->stream);
8048                                 mutex_unlock(&dm->dc_lock);
8049                         }
8050                 }
8051
8052                 /*
8053                  * Only allow immediate flips for fast updates that don't
8054                  * change memory domain, FB pitch, DCC state, rotation or
8055                  * mirroring.
8056                  */
8057                 bundle->flip_addrs[planes_count].flip_immediate =
8058                         crtc->state->async_flip &&
8059                         acrtc_state->update_type == UPDATE_TYPE_FAST &&
8060                         get_mem_type(old_plane_state->fb) == get_mem_type(fb);
8061
8062                 timestamp_ns = ktime_get_ns();
8063                 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
8064                 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
8065                 bundle->surface_updates[planes_count].surface = dc_plane;
8066
8067                 if (!bundle->surface_updates[planes_count].surface) {
8068                         DRM_ERROR("No surface for CRTC: id=%d\n",
8069                                         acrtc_attach->crtc_id);
8070                         continue;
8071                 }
8072
8073                 if (plane == pcrtc->primary)
8074                         update_freesync_state_on_stream(
8075                                 dm,
8076                                 acrtc_state,
8077                                 acrtc_state->stream,
8078                                 dc_plane,
8079                                 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
8080
8081                 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n",
8082                                  __func__,
8083                                  bundle->flip_addrs[planes_count].address.grph.addr.high_part,
8084                                  bundle->flip_addrs[planes_count].address.grph.addr.low_part);
8085
8086                 planes_count += 1;
8087
8088         }
8089
8090         if (pflip_present) {
8091                 if (!vrr_active) {
8092                         /* Use old throttling in non-vrr fixed refresh rate mode
8093                          * to keep flip scheduling based on target vblank counts
8094                          * working in a backwards compatible way, e.g., for
8095                          * clients using the GLX_OML_sync_control extension or
8096                          * DRI3/Present extension with defined target_msc.
8097                          */
8098                         last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);
8099                 }
8100                 else {
8101                         /* For variable refresh rate mode only:
8102                          * Get vblank of last completed flip to avoid > 1 vrr
8103                          * flips per video frame by use of throttling, but allow
8104                          * flip programming anywhere in the possibly large
8105                          * variable vrr vblank interval for fine-grained flip
8106                          * timing control and more opportunity to avoid stutter
8107                          * on late submission of flips.
8108                          */
8109                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8110                         last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank;
8111                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8112                 }
8113
8114                 target_vblank = last_flip_vblank + wait_for_vblank;
8115
8116                 /*
8117                  * Wait until we're out of the vertical blank period before the one
8118                  * targeted by the flip
8119                  */
8120                 while ((acrtc_attach->enabled &&
8121                         (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
8122                                                             0, &vpos, &hpos, NULL,
8123                                                             NULL, &pcrtc->hwmode)
8124                          & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
8125                         (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
8126                         (int)(target_vblank -
8127                           amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) {
8128                         usleep_range(1000, 1100);
8129                 }
8130
8131                 /**
8132                  * Prepare the flip event for the pageflip interrupt to handle.
8133                  *
8134                  * This only works in the case where we've already turned on the
8135                  * appropriate hardware blocks (eg. HUBP) so in the transition case
8136                  * from 0 -> n planes we have to skip a hardware generated event
8137                  * and rely on sending it from software.
8138                  */
8139                 if (acrtc_attach->base.state->event &&
8140                     acrtc_state->active_planes > 0) {
8141                         drm_crtc_vblank_get(pcrtc);
8142
8143                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8144
8145                         WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
8146                         prepare_flip_isr(acrtc_attach);
8147
8148                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8149                 }
8150
8151                 if (acrtc_state->stream) {
8152                         if (acrtc_state->freesync_vrr_info_changed)
8153                                 bundle->stream_update.vrr_infopacket =
8154                                         &acrtc_state->stream->vrr_infopacket;
8155                 }
8156         } else if (cursor_update && acrtc_state->active_planes > 0 &&
8157                    acrtc_attach->base.state->event) {
8158                 drm_crtc_vblank_get(pcrtc);
8159
8160                 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8161
8162                 acrtc_attach->event = acrtc_attach->base.state->event;
8163                 acrtc_attach->base.state->event = NULL;
8164
8165                 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8166         }
8167
8168         /* Update the planes if changed or disable if we don't have any. */
8169         if ((planes_count || acrtc_state->active_planes == 0) &&
8170                 acrtc_state->stream) {
8171                 /*
8172                  * If PSR or idle optimizations are enabled then flush out
8173                  * any pending work before hardware programming.
8174                  */
8175                 if (dm->vblank_control_workqueue)
8176                         flush_workqueue(dm->vblank_control_workqueue);
8177
8178                 bundle->stream_update.stream = acrtc_state->stream;
8179                 if (new_pcrtc_state->mode_changed) {
8180                         bundle->stream_update.src = acrtc_state->stream->src;
8181                         bundle->stream_update.dst = acrtc_state->stream->dst;
8182                 }
8183
8184                 if (new_pcrtc_state->color_mgmt_changed) {
8185                         /*
8186                          * TODO: This isn't fully correct since we've actually
8187                          * already modified the stream in place.
8188                          */
8189                         bundle->stream_update.gamut_remap =
8190                                 &acrtc_state->stream->gamut_remap_matrix;
8191                         bundle->stream_update.output_csc_transform =
8192                                 &acrtc_state->stream->csc_color_matrix;
8193                         bundle->stream_update.out_transfer_func =
8194                                 acrtc_state->stream->out_transfer_func;
8195                 }
8196
8197                 acrtc_state->stream->abm_level = acrtc_state->abm_level;
8198                 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
8199                         bundle->stream_update.abm_level = &acrtc_state->abm_level;
8200
8201                 /*
8202                  * If FreeSync state on the stream has changed then we need to
8203                  * re-adjust the min/max bounds now that DC doesn't handle this
8204                  * as part of commit.
8205                  */
8206                 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) {
8207                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8208                         dc_stream_adjust_vmin_vmax(
8209                                 dm->dc, acrtc_state->stream,
8210                                 &acrtc_attach->dm_irq_params.vrr_params.adjust);
8211                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8212                 }
8213                 mutex_lock(&dm->dc_lock);
8214                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8215                                 acrtc_state->stream->link->psr_settings.psr_allow_active)
8216                         amdgpu_dm_psr_disable(acrtc_state->stream);
8217
8218                 update_planes_and_stream_adapter(dm->dc,
8219                                          acrtc_state->update_type,
8220                                          planes_count,
8221                                          acrtc_state->stream,
8222                                          &bundle->stream_update,
8223                                          bundle->surface_updates);
8224
8225                 /**
8226                  * Enable or disable the interrupts on the backend.
8227                  *
8228                  * Most pipes are put into power gating when unused.
8229                  *
8230                  * When power gating is enabled on a pipe we lose the
8231                  * interrupt enablement state when power gating is disabled.
8232                  *
8233                  * So we need to update the IRQ control state in hardware
8234                  * whenever the pipe turns on (since it could be previously
8235                  * power gated) or off (since some pipes can't be power gated
8236                  * on some ASICs).
8237                  */
8238                 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes)
8239                         dm_update_pflip_irq_state(drm_to_adev(dev),
8240                                                   acrtc_attach);
8241
8242                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8243                                 acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
8244                                 !acrtc_state->stream->link->psr_settings.psr_feature_enabled)
8245                         amdgpu_dm_link_setup_psr(acrtc_state->stream);
8246
8247                 /* Decrement skip count when PSR is enabled and we're doing fast updates. */
8248                 if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
8249                     acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8250                         struct amdgpu_dm_connector *aconn =
8251                                 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
8252
8253                         if (aconn->psr_skip_count > 0)
8254                                 aconn->psr_skip_count--;
8255
8256                         /* Allow PSR when skip count is 0. */
8257                         acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count;
8258
8259                         /*
8260                          * If sink supports PSR SU, there is no need to rely on
8261                          * a vblank event disable request to enable PSR. PSR SU
8262                          * can be enabled immediately once OS demonstrates an
8263                          * adequate number of fast atomic commits to notify KMD
8264                          * of update events. See `vblank_control_worker()`.
8265                          */
8266                         if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8267                             acrtc_attach->dm_irq_params.allow_psr_entry &&
8268 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8269                             !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8270 #endif
8271                             !acrtc_state->stream->link->psr_settings.psr_allow_active &&
8272                             (timestamp_ns -
8273                             acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) >
8274                             500000000)
8275                                 amdgpu_dm_psr_enable(acrtc_state->stream);
8276                 } else {
8277                         acrtc_attach->dm_irq_params.allow_psr_entry = false;
8278                 }
8279
8280                 mutex_unlock(&dm->dc_lock);
8281         }
8282
8283         /*
8284          * Update cursor state *after* programming all the planes.
8285          * This avoids redundant programming in the case where we're going
8286          * to be disabling a single plane - those pipes are being disabled.
8287          */
8288         if (acrtc_state->active_planes)
8289                 amdgpu_dm_commit_cursors(state);
8290
8291 cleanup:
8292         kfree(bundle);
8293 }
8294
8295 static void amdgpu_dm_commit_audio(struct drm_device *dev,
8296                                    struct drm_atomic_state *state)
8297 {
8298         struct amdgpu_device *adev = drm_to_adev(dev);
8299         struct amdgpu_dm_connector *aconnector;
8300         struct drm_connector *connector;
8301         struct drm_connector_state *old_con_state, *new_con_state;
8302         struct drm_crtc_state *new_crtc_state;
8303         struct dm_crtc_state *new_dm_crtc_state;
8304         const struct dc_stream_status *status;
8305         int i, inst;
8306
8307         /* Notify device removals. */
8308         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8309                 if (old_con_state->crtc != new_con_state->crtc) {
8310                         /* CRTC changes require notification. */
8311                         goto notify;
8312                 }
8313
8314                 if (!new_con_state->crtc)
8315                         continue;
8316
8317                 new_crtc_state = drm_atomic_get_new_crtc_state(
8318                         state, new_con_state->crtc);
8319
8320                 if (!new_crtc_state)
8321                         continue;
8322
8323                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8324                         continue;
8325
8326 notify:
8327                 aconnector = to_amdgpu_dm_connector(connector);
8328
8329                 mutex_lock(&adev->dm.audio_lock);
8330                 inst = aconnector->audio_inst;
8331                 aconnector->audio_inst = -1;
8332                 mutex_unlock(&adev->dm.audio_lock);
8333
8334                 amdgpu_dm_audio_eld_notify(adev, inst);
8335         }
8336
8337         /* Notify audio device additions. */
8338         for_each_new_connector_in_state(state, connector, new_con_state, i) {
8339                 if (!new_con_state->crtc)
8340                         continue;
8341
8342                 new_crtc_state = drm_atomic_get_new_crtc_state(
8343                         state, new_con_state->crtc);
8344
8345                 if (!new_crtc_state)
8346                         continue;
8347
8348                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8349                         continue;
8350
8351                 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
8352                 if (!new_dm_crtc_state->stream)
8353                         continue;
8354
8355                 status = dc_stream_get_status(new_dm_crtc_state->stream);
8356                 if (!status)
8357                         continue;
8358
8359                 aconnector = to_amdgpu_dm_connector(connector);
8360
8361                 mutex_lock(&adev->dm.audio_lock);
8362                 inst = status->audio_inst;
8363                 aconnector->audio_inst = inst;
8364                 mutex_unlock(&adev->dm.audio_lock);
8365
8366                 amdgpu_dm_audio_eld_notify(adev, inst);
8367         }
8368 }
8369
8370 /*
8371  * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
8372  * @crtc_state: the DRM CRTC state
8373  * @stream_state: the DC stream state.
8374  *
8375  * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
8376  * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
8377  */
8378 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
8379                                                 struct dc_stream_state *stream_state)
8380 {
8381         stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
8382 }
8383
8384 /**
8385  * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
8386  * @state: The atomic state to commit
8387  *
8388  * This will tell DC to commit the constructed DC state from atomic_check,
8389  * programming the hardware. Any failures here implies a hardware failure, since
8390  * atomic check should have filtered anything non-kosher.
8391  */
8392 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
8393 {
8394         struct drm_device *dev = state->dev;
8395         struct amdgpu_device *adev = drm_to_adev(dev);
8396         struct amdgpu_display_manager *dm = &adev->dm;
8397         struct dm_atomic_state *dm_state;
8398         struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
8399         u32 i, j;
8400         struct drm_crtc *crtc;
8401         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8402         unsigned long flags;
8403         bool wait_for_vblank = true;
8404         struct drm_connector *connector;
8405         struct drm_connector_state *old_con_state, *new_con_state;
8406         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8407         int crtc_disable_count = 0;
8408         bool mode_set_reset_required = false;
8409         int r;
8410
8411         trace_amdgpu_dm_atomic_commit_tail_begin(state);
8412
8413         r = drm_atomic_helper_wait_for_fences(dev, state, false);
8414         if (unlikely(r))
8415                 DRM_ERROR("Waiting for fences timed out!");
8416
8417         drm_atomic_helper_update_legacy_modeset_state(dev, state);
8418         drm_dp_mst_atomic_wait_for_dependencies(state);
8419
8420         dm_state = dm_atomic_get_new_state(state);
8421         if (dm_state && dm_state->context) {
8422                 dc_state = dm_state->context;
8423         } else {
8424                 /* No state changes, retain current state. */
8425                 dc_state_temp = dc_create_state(dm->dc);
8426                 ASSERT(dc_state_temp);
8427                 dc_state = dc_state_temp;
8428                 dc_resource_state_copy_construct_current(dm->dc, dc_state);
8429         }
8430
8431         for_each_oldnew_crtc_in_state (state, crtc, old_crtc_state,
8432                                        new_crtc_state, i) {
8433                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8434
8435                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8436
8437                 if (old_crtc_state->active &&
8438                     (!new_crtc_state->active ||
8439                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8440                         manage_dm_interrupts(adev, acrtc, false);
8441                         dc_stream_release(dm_old_crtc_state->stream);
8442                 }
8443         }
8444
8445         drm_atomic_helper_calc_timestamping_constants(state);
8446
8447         /* update changed items */
8448         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8449                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8450
8451                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8452                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8453
8454                 drm_dbg_state(state->dev,
8455                         "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
8456                         "planes_changed:%d, mode_changed:%d,active_changed:%d,"
8457                         "connectors_changed:%d\n",
8458                         acrtc->crtc_id,
8459                         new_crtc_state->enable,
8460                         new_crtc_state->active,
8461                         new_crtc_state->planes_changed,
8462                         new_crtc_state->mode_changed,
8463                         new_crtc_state->active_changed,
8464                         new_crtc_state->connectors_changed);
8465
8466                 /* Disable cursor if disabling crtc */
8467                 if (old_crtc_state->active && !new_crtc_state->active) {
8468                         struct dc_cursor_position position;
8469
8470                         memset(&position, 0, sizeof(position));
8471                         mutex_lock(&dm->dc_lock);
8472                         dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position);
8473                         mutex_unlock(&dm->dc_lock);
8474                 }
8475
8476                 /* Copy all transient state flags into dc state */
8477                 if (dm_new_crtc_state->stream) {
8478                         amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
8479                                                             dm_new_crtc_state->stream);
8480                 }
8481
8482                 /* handles headless hotplug case, updating new_state and
8483                  * aconnector as needed
8484                  */
8485
8486                 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
8487
8488                         DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
8489
8490                         if (!dm_new_crtc_state->stream) {
8491                                 /*
8492                                  * this could happen because of issues with
8493                                  * userspace notifications delivery.
8494                                  * In this case userspace tries to set mode on
8495                                  * display which is disconnected in fact.
8496                                  * dc_sink is NULL in this case on aconnector.
8497                                  * We expect reset mode will come soon.
8498                                  *
8499                                  * This can also happen when unplug is done
8500                                  * during resume sequence ended
8501                                  *
8502                                  * In this case, we want to pretend we still
8503                                  * have a sink to keep the pipe running so that
8504                                  * hw state is consistent with the sw state
8505                                  */
8506                                 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
8507                                                 __func__, acrtc->base.base.id);
8508                                 continue;
8509                         }
8510
8511                         if (dm_old_crtc_state->stream)
8512                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8513
8514                         pm_runtime_get_noresume(dev->dev);
8515
8516                         acrtc->enabled = true;
8517                         acrtc->hw_mode = new_crtc_state->mode;
8518                         crtc->hwmode = new_crtc_state->mode;
8519                         mode_set_reset_required = true;
8520                 } else if (modereset_required(new_crtc_state)) {
8521                         DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
8522                         /* i.e. reset mode */
8523                         if (dm_old_crtc_state->stream)
8524                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8525
8526                         mode_set_reset_required = true;
8527                 }
8528         } /* for_each_crtc_in_state() */
8529
8530         if (dc_state) {
8531                 /* if there mode set or reset, disable eDP PSR */
8532                 if (mode_set_reset_required) {
8533                         if (dm->vblank_control_workqueue)
8534                                 flush_workqueue(dm->vblank_control_workqueue);
8535
8536                         amdgpu_dm_psr_disable_all(dm);
8537                 }
8538
8539                 dm_enable_per_frame_crtc_master_sync(dc_state);
8540                 mutex_lock(&dm->dc_lock);
8541                 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
8542
8543                 /* Allow idle optimization when vblank count is 0 for display off */
8544                 if (dm->active_vblank_irq_count == 0)
8545                         dc_allow_idle_optimizations(dm->dc, true);
8546                 mutex_unlock(&dm->dc_lock);
8547         }
8548
8549         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8550                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8551
8552                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8553
8554                 if (dm_new_crtc_state->stream != NULL) {
8555                         const struct dc_stream_status *status =
8556                                         dc_stream_get_status(dm_new_crtc_state->stream);
8557
8558                         if (!status)
8559                                 status = dc_stream_get_status_from_state(dc_state,
8560                                                                          dm_new_crtc_state->stream);
8561                         if (!status)
8562                                 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
8563                         else
8564                                 acrtc->otg_inst = status->primary_otg_inst;
8565                 }
8566         }
8567         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8568                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8569                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8570                 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8571
8572                 if (!adev->dm.hdcp_workqueue)
8573                         continue;
8574
8575                 pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i);
8576
8577                 if (!connector)
8578                         continue;
8579
8580                 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
8581                         connector->index, connector->status, connector->dpms);
8582                 pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
8583                         old_con_state->content_protection, new_con_state->content_protection);
8584
8585                 if (aconnector->dc_sink) {
8586                         if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
8587                                 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) {
8588                                 pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n",
8589                                 aconnector->dc_sink->edid_caps.display_name);
8590                         }
8591                 }
8592
8593                 new_crtc_state = NULL;
8594                 old_crtc_state = NULL;
8595
8596                 if (acrtc) {
8597                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8598                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8599                 }
8600
8601                 if (old_crtc_state)
8602                         pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8603                         old_crtc_state->enable,
8604                         old_crtc_state->active,
8605                         old_crtc_state->mode_changed,
8606                         old_crtc_state->active_changed,
8607                         old_crtc_state->connectors_changed);
8608
8609                 if (new_crtc_state)
8610                         pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8611                         new_crtc_state->enable,
8612                         new_crtc_state->active,
8613                         new_crtc_state->mode_changed,
8614                         new_crtc_state->active_changed,
8615                         new_crtc_state->connectors_changed);
8616         }
8617
8618         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8619                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8620                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8621                 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8622
8623                 if (!adev->dm.hdcp_workqueue)
8624                         continue;
8625
8626                 new_crtc_state = NULL;
8627                 old_crtc_state = NULL;
8628
8629                 if (acrtc) {
8630                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8631                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8632                 }
8633
8634                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8635
8636                 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
8637                     connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
8638                         hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
8639                         new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
8640                         dm_new_con_state->update_hdcp = true;
8641                         continue;
8642                 }
8643
8644                 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state,
8645                                                                                         old_con_state, connector, adev->dm.hdcp_workqueue)) {
8646                         /* when display is unplugged from mst hub, connctor will
8647                          * be destroyed within dm_dp_mst_connector_destroy. connector
8648                          * hdcp perperties, like type, undesired, desired, enabled,
8649                          * will be lost. So, save hdcp properties into hdcp_work within
8650                          * amdgpu_dm_atomic_commit_tail. if the same display is
8651                          * plugged back with same display index, its hdcp properties
8652                          * will be retrieved from hdcp_work within dm_dp_mst_get_modes
8653                          */
8654
8655                         bool enable_encryption = false;
8656
8657                         if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED)
8658                                 enable_encryption = true;
8659
8660                         if (aconnector->dc_link && aconnector->dc_sink &&
8661                                 aconnector->dc_link->type == dc_connection_mst_branch) {
8662                                 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
8663                                 struct hdcp_workqueue *hdcp_w =
8664                                         &hdcp_work[aconnector->dc_link->link_index];
8665
8666                                 hdcp_w->hdcp_content_type[connector->index] =
8667                                         new_con_state->hdcp_content_type;
8668                                 hdcp_w->content_protection[connector->index] =
8669                                         new_con_state->content_protection;
8670                         }
8671
8672                         if (new_crtc_state && new_crtc_state->mode_changed &&
8673                                 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED)
8674                                 enable_encryption = true;
8675
8676                         DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption);
8677
8678                         hdcp_update_display(
8679                                 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
8680                                 new_con_state->hdcp_content_type, enable_encryption);
8681                 }
8682         }
8683
8684         /* Handle connector state changes */
8685         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8686                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8687                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
8688                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8689                 struct dc_surface_update dummy_updates[MAX_SURFACES];
8690                 struct dc_stream_update stream_update;
8691                 struct dc_info_packet hdr_packet;
8692                 struct dc_stream_status *status = NULL;
8693                 bool abm_changed, hdr_changed, scaling_changed;
8694
8695                 memset(&dummy_updates, 0, sizeof(dummy_updates));
8696                 memset(&stream_update, 0, sizeof(stream_update));
8697
8698                 if (acrtc) {
8699                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8700                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8701                 }
8702
8703                 /* Skip any modesets/resets */
8704                 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
8705                         continue;
8706
8707                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8708                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8709
8710                 scaling_changed = is_scaling_state_different(dm_new_con_state,
8711                                                              dm_old_con_state);
8712
8713                 abm_changed = dm_new_crtc_state->abm_level !=
8714                               dm_old_crtc_state->abm_level;
8715
8716                 hdr_changed =
8717                         !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state);
8718
8719                 if (!scaling_changed && !abm_changed && !hdr_changed)
8720                         continue;
8721
8722                 stream_update.stream = dm_new_crtc_state->stream;
8723                 if (scaling_changed) {
8724                         update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
8725                                         dm_new_con_state, dm_new_crtc_state->stream);
8726
8727                         stream_update.src = dm_new_crtc_state->stream->src;
8728                         stream_update.dst = dm_new_crtc_state->stream->dst;
8729                 }
8730
8731                 if (abm_changed) {
8732                         dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
8733
8734                         stream_update.abm_level = &dm_new_crtc_state->abm_level;
8735                 }
8736
8737                 if (hdr_changed) {
8738                         fill_hdr_info_packet(new_con_state, &hdr_packet);
8739                         stream_update.hdr_static_metadata = &hdr_packet;
8740                 }
8741
8742                 status = dc_stream_get_status(dm_new_crtc_state->stream);
8743
8744                 if (WARN_ON(!status))
8745                         continue;
8746
8747                 WARN_ON(!status->plane_count);
8748
8749                 /*
8750                  * TODO: DC refuses to perform stream updates without a dc_surface_update.
8751                  * Here we create an empty update on each plane.
8752                  * To fix this, DC should permit updating only stream properties.
8753                  */
8754                 for (j = 0; j < status->plane_count; j++)
8755                         dummy_updates[j].surface = status->plane_states[0];
8756
8757
8758                 mutex_lock(&dm->dc_lock);
8759                 dc_update_planes_and_stream(dm->dc,
8760                                             dummy_updates,
8761                                             status->plane_count,
8762                                             dm_new_crtc_state->stream,
8763                                             &stream_update);
8764                 mutex_unlock(&dm->dc_lock);
8765         }
8766
8767         /**
8768          * Enable interrupts for CRTCs that are newly enabled or went through
8769          * a modeset. It was intentionally deferred until after the front end
8770          * state was modified to wait until the OTG was on and so the IRQ
8771          * handlers didn't access stale or invalid state.
8772          */
8773         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8774                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8775 #ifdef CONFIG_DEBUG_FS
8776                 enum amdgpu_dm_pipe_crc_source cur_crc_src;
8777 #endif
8778                 /* Count number of newly disabled CRTCs for dropping PM refs later. */
8779                 if (old_crtc_state->active && !new_crtc_state->active)
8780                         crtc_disable_count++;
8781
8782                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8783                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8784
8785                 /* For freesync config update on crtc state and params for irq */
8786                 update_stream_irq_parameters(dm, dm_new_crtc_state);
8787
8788 #ifdef CONFIG_DEBUG_FS
8789                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8790                 cur_crc_src = acrtc->dm_irq_params.crc_src;
8791                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8792 #endif
8793
8794                 if (new_crtc_state->active &&
8795                     (!old_crtc_state->active ||
8796                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8797                         dc_stream_retain(dm_new_crtc_state->stream);
8798                         acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
8799                         manage_dm_interrupts(adev, acrtc, true);
8800                 }
8801                 /* Handle vrr on->off / off->on transitions */
8802                 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state);
8803
8804 #ifdef CONFIG_DEBUG_FS
8805                 if (new_crtc_state->active &&
8806                     (!old_crtc_state->active ||
8807                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8808                         /**
8809                          * Frontend may have changed so reapply the CRC capture
8810                          * settings for the stream.
8811                          */
8812                         if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
8813 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
8814                                 if (amdgpu_dm_crc_window_is_activated(crtc)) {
8815                                         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8816                                         acrtc->dm_irq_params.window_param.update_win = true;
8817
8818                                         /**
8819                                          * It takes 2 frames for HW to stably generate CRC when
8820                                          * resuming from suspend, so we set skip_frame_cnt 2.
8821                                          */
8822                                         acrtc->dm_irq_params.window_param.skip_frame_cnt = 2;
8823                                         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8824                                 }
8825 #endif
8826                                 if (amdgpu_dm_crtc_configure_crc_source(
8827                                         crtc, dm_new_crtc_state, cur_crc_src))
8828                                         DRM_DEBUG_DRIVER("Failed to configure crc source");
8829                         }
8830                 }
8831 #endif
8832         }
8833
8834         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
8835                 if (new_crtc_state->async_flip)
8836                         wait_for_vblank = false;
8837
8838         /* update planes when needed per crtc*/
8839         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
8840                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8841
8842                 if (dm_new_crtc_state->stream)
8843                         amdgpu_dm_commit_planes(state, dc_state, dev,
8844                                                 dm, crtc, wait_for_vblank);
8845         }
8846
8847         /* Update audio instances for each connector. */
8848         amdgpu_dm_commit_audio(dev, state);
8849
8850         /* restore the backlight level */
8851         for (i = 0; i < dm->num_of_edps; i++) {
8852                 if (dm->backlight_dev[i] &&
8853                     (dm->actual_brightness[i] != dm->brightness[i]))
8854                         amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
8855         }
8856
8857         /*
8858          * send vblank event on all events not handled in flip and
8859          * mark consumed event for drm_atomic_helper_commit_hw_done
8860          */
8861         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8862         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8863
8864                 if (new_crtc_state->event)
8865                         drm_send_event_locked(dev, &new_crtc_state->event->base);
8866
8867                 new_crtc_state->event = NULL;
8868         }
8869         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8870
8871         /* Signal HW programming completion */
8872         drm_atomic_helper_commit_hw_done(state);
8873
8874         if (wait_for_vblank)
8875                 drm_atomic_helper_wait_for_flip_done(dev, state);
8876
8877         drm_atomic_helper_cleanup_planes(dev, state);
8878
8879         /* return the stolen vga memory back to VRAM */
8880         if (!adev->mman.keep_stolen_vga_memory)
8881                 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
8882         amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
8883
8884         /*
8885          * Finally, drop a runtime PM reference for each newly disabled CRTC,
8886          * so we can put the GPU into runtime suspend if we're not driving any
8887          * displays anymore
8888          */
8889         for (i = 0; i < crtc_disable_count; i++)
8890                 pm_runtime_put_autosuspend(dev->dev);
8891         pm_runtime_mark_last_busy(dev->dev);
8892
8893         if (dc_state_temp)
8894                 dc_release_state(dc_state_temp);
8895 }
8896
8897 static int dm_force_atomic_commit(struct drm_connector *connector)
8898 {
8899         int ret = 0;
8900         struct drm_device *ddev = connector->dev;
8901         struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
8902         struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
8903         struct drm_plane *plane = disconnected_acrtc->base.primary;
8904         struct drm_connector_state *conn_state;
8905         struct drm_crtc_state *crtc_state;
8906         struct drm_plane_state *plane_state;
8907
8908         if (!state)
8909                 return -ENOMEM;
8910
8911         state->acquire_ctx = ddev->mode_config.acquire_ctx;
8912
8913         /* Construct an atomic state to restore previous display setting */
8914
8915         /*
8916          * Attach connectors to drm_atomic_state
8917          */
8918         conn_state = drm_atomic_get_connector_state(state, connector);
8919
8920         ret = PTR_ERR_OR_ZERO(conn_state);
8921         if (ret)
8922                 goto out;
8923
8924         /* Attach crtc to drm_atomic_state*/
8925         crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
8926
8927         ret = PTR_ERR_OR_ZERO(crtc_state);
8928         if (ret)
8929                 goto out;
8930
8931         /* force a restore */
8932         crtc_state->mode_changed = true;
8933
8934         /* Attach plane to drm_atomic_state */
8935         plane_state = drm_atomic_get_plane_state(state, plane);
8936
8937         ret = PTR_ERR_OR_ZERO(plane_state);
8938         if (ret)
8939                 goto out;
8940
8941         /* Call commit internally with the state we just constructed */
8942         ret = drm_atomic_commit(state);
8943
8944 out:
8945         drm_atomic_state_put(state);
8946         if (ret)
8947                 DRM_ERROR("Restoring old state failed with %i\n", ret);
8948
8949         return ret;
8950 }
8951
8952 /*
8953  * This function handles all cases when set mode does not come upon hotplug.
8954  * This includes when a display is unplugged then plugged back into the
8955  * same port and when running without usermode desktop manager supprot
8956  */
8957 void dm_restore_drm_connector_state(struct drm_device *dev,
8958                                     struct drm_connector *connector)
8959 {
8960         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8961         struct amdgpu_crtc *disconnected_acrtc;
8962         struct dm_crtc_state *acrtc_state;
8963
8964         if (!aconnector->dc_sink || !connector->state || !connector->encoder)
8965                 return;
8966
8967         disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
8968         if (!disconnected_acrtc)
8969                 return;
8970
8971         acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
8972         if (!acrtc_state->stream)
8973                 return;
8974
8975         /*
8976          * If the previous sink is not released and different from the current,
8977          * we deduce we are in a state where we can not rely on usermode call
8978          * to turn on the display, so we do it here
8979          */
8980         if (acrtc_state->stream->sink != aconnector->dc_sink)
8981                 dm_force_atomic_commit(&aconnector->base);
8982 }
8983
8984 /*
8985  * Grabs all modesetting locks to serialize against any blocking commits,
8986  * Waits for completion of all non blocking commits.
8987  */
8988 static int do_aquire_global_lock(struct drm_device *dev,
8989                                  struct drm_atomic_state *state)
8990 {
8991         struct drm_crtc *crtc;
8992         struct drm_crtc_commit *commit;
8993         long ret;
8994
8995         /*
8996          * Adding all modeset locks to aquire_ctx will
8997          * ensure that when the framework release it the
8998          * extra locks we are locking here will get released to
8999          */
9000         ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
9001         if (ret)
9002                 return ret;
9003
9004         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9005                 spin_lock(&crtc->commit_lock);
9006                 commit = list_first_entry_or_null(&crtc->commit_list,
9007                                 struct drm_crtc_commit, commit_entry);
9008                 if (commit)
9009                         drm_crtc_commit_get(commit);
9010                 spin_unlock(&crtc->commit_lock);
9011
9012                 if (!commit)
9013                         continue;
9014
9015                 /*
9016                  * Make sure all pending HW programming completed and
9017                  * page flips done
9018                  */
9019                 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
9020
9021                 if (ret > 0)
9022                         ret = wait_for_completion_interruptible_timeout(
9023                                         &commit->flip_done, 10*HZ);
9024
9025                 if (ret == 0)
9026                         DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
9027                                   "timed out\n", crtc->base.id, crtc->name);
9028
9029                 drm_crtc_commit_put(commit);
9030         }
9031
9032         return ret < 0 ? ret : 0;
9033 }
9034
9035 static void get_freesync_config_for_crtc(
9036         struct dm_crtc_state *new_crtc_state,
9037         struct dm_connector_state *new_con_state)
9038 {
9039         struct mod_freesync_config config = {0};
9040         struct amdgpu_dm_connector *aconnector =
9041                         to_amdgpu_dm_connector(new_con_state->base.connector);
9042         struct drm_display_mode *mode = &new_crtc_state->base.mode;
9043         int vrefresh = drm_mode_vrefresh(mode);
9044         bool fs_vid_mode = false;
9045
9046         new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
9047                                         vrefresh >= aconnector->min_vfreq &&
9048                                         vrefresh <= aconnector->max_vfreq;
9049
9050         if (new_crtc_state->vrr_supported) {
9051                 new_crtc_state->stream->ignore_msa_timing_param = true;
9052                 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
9053
9054                 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000;
9055                 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000;
9056                 config.vsif_supported = true;
9057                 config.btr = true;
9058
9059                 if (fs_vid_mode) {
9060                         config.state = VRR_STATE_ACTIVE_FIXED;
9061                         config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz;
9062                         goto out;
9063                 } else if (new_crtc_state->base.vrr_enabled) {
9064                         config.state = VRR_STATE_ACTIVE_VARIABLE;
9065                 } else {
9066                         config.state = VRR_STATE_INACTIVE;
9067                 }
9068         }
9069 out:
9070         new_crtc_state->freesync_config = config;
9071 }
9072
9073 static void reset_freesync_config_for_crtc(
9074         struct dm_crtc_state *new_crtc_state)
9075 {
9076         new_crtc_state->vrr_supported = false;
9077
9078         memset(&new_crtc_state->vrr_infopacket, 0,
9079                sizeof(new_crtc_state->vrr_infopacket));
9080 }
9081
9082 static bool
9083 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
9084                                  struct drm_crtc_state *new_crtc_state)
9085 {
9086         const struct drm_display_mode *old_mode, *new_mode;
9087
9088         if (!old_crtc_state || !new_crtc_state)
9089                 return false;
9090
9091         old_mode = &old_crtc_state->mode;
9092         new_mode = &new_crtc_state->mode;
9093
9094         if (old_mode->clock       == new_mode->clock &&
9095             old_mode->hdisplay    == new_mode->hdisplay &&
9096             old_mode->vdisplay    == new_mode->vdisplay &&
9097             old_mode->htotal      == new_mode->htotal &&
9098             old_mode->vtotal      != new_mode->vtotal &&
9099             old_mode->hsync_start == new_mode->hsync_start &&
9100             old_mode->vsync_start != new_mode->vsync_start &&
9101             old_mode->hsync_end   == new_mode->hsync_end &&
9102             old_mode->vsync_end   != new_mode->vsync_end &&
9103             old_mode->hskew       == new_mode->hskew &&
9104             old_mode->vscan       == new_mode->vscan &&
9105             (old_mode->vsync_end - old_mode->vsync_start) ==
9106             (new_mode->vsync_end - new_mode->vsync_start))
9107                 return true;
9108
9109         return false;
9110 }
9111
9112 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) {
9113         u64 num, den, res;
9114         struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
9115
9116         dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;
9117
9118         num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000;
9119         den = (unsigned long long)new_crtc_state->mode.htotal *
9120               (unsigned long long)new_crtc_state->mode.vtotal;
9121
9122         res = div_u64(num, den);
9123         dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
9124 }
9125
9126 static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
9127                          struct drm_atomic_state *state,
9128                          struct drm_crtc *crtc,
9129                          struct drm_crtc_state *old_crtc_state,
9130                          struct drm_crtc_state *new_crtc_state,
9131                          bool enable,
9132                          bool *lock_and_validation_needed)
9133 {
9134         struct dm_atomic_state *dm_state = NULL;
9135         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9136         struct dc_stream_state *new_stream;
9137         int ret = 0;
9138
9139         /*
9140          * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
9141          * update changed items
9142          */
9143         struct amdgpu_crtc *acrtc = NULL;
9144         struct amdgpu_dm_connector *aconnector = NULL;
9145         struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
9146         struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
9147
9148         new_stream = NULL;
9149
9150         dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9151         dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9152         acrtc = to_amdgpu_crtc(crtc);
9153         aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
9154
9155         /* TODO This hack should go away */
9156         if (aconnector && enable) {
9157                 /* Make sure fake sink is created in plug-in scenario */
9158                 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
9159                                                             &aconnector->base);
9160                 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
9161                                                             &aconnector->base);
9162
9163                 if (IS_ERR(drm_new_conn_state)) {
9164                         ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
9165                         goto fail;
9166                 }
9167
9168                 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
9169                 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
9170
9171                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9172                         goto skip_modeset;
9173
9174                 new_stream = create_validate_stream_for_sink(aconnector,
9175                                                              &new_crtc_state->mode,
9176                                                              dm_new_conn_state,
9177                                                              dm_old_crtc_state->stream);
9178
9179                 /*
9180                  * we can have no stream on ACTION_SET if a display
9181                  * was disconnected during S3, in this case it is not an
9182                  * error, the OS will be updated after detection, and
9183                  * will do the right thing on next atomic commit
9184                  */
9185
9186                 if (!new_stream) {
9187                         DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
9188                                         __func__, acrtc->base.base.id);
9189                         ret = -ENOMEM;
9190                         goto fail;
9191                 }
9192
9193                 /*
9194                  * TODO: Check VSDB bits to decide whether this should
9195                  * be enabled or not.
9196                  */
9197                 new_stream->triggered_crtc_reset.enabled =
9198                         dm->force_timing_sync;
9199
9200                 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9201
9202                 ret = fill_hdr_info_packet(drm_new_conn_state,
9203                                            &new_stream->hdr_static_metadata);
9204                 if (ret)
9205                         goto fail;
9206
9207                 /*
9208                  * If we already removed the old stream from the context
9209                  * (and set the new stream to NULL) then we can't reuse
9210                  * the old stream even if the stream and scaling are unchanged.
9211                  * We'll hit the BUG_ON and black screen.
9212                  *
9213                  * TODO: Refactor this function to allow this check to work
9214                  * in all conditions.
9215                  */
9216                 if (amdgpu_freesync_vid_mode &&
9217                     dm_new_crtc_state->stream &&
9218                     is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))
9219                         goto skip_modeset;
9220
9221                 if (dm_new_crtc_state->stream &&
9222                     dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9223                     dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
9224                         new_crtc_state->mode_changed = false;
9225                         DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
9226                                          new_crtc_state->mode_changed);
9227                 }
9228         }
9229
9230         /* mode_changed flag may get updated above, need to check again */
9231         if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9232                 goto skip_modeset;
9233
9234         drm_dbg_state(state->dev,
9235                 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
9236                 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
9237                 "connectors_changed:%d\n",
9238                 acrtc->crtc_id,
9239                 new_crtc_state->enable,
9240                 new_crtc_state->active,
9241                 new_crtc_state->planes_changed,
9242                 new_crtc_state->mode_changed,
9243                 new_crtc_state->active_changed,
9244                 new_crtc_state->connectors_changed);
9245
9246         /* Remove stream for any changed/disabled CRTC */
9247         if (!enable) {
9248
9249                 if (!dm_old_crtc_state->stream)
9250                         goto skip_modeset;
9251
9252                 /* Unset freesync video if it was active before */
9253                 if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) {
9254                         dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE;
9255                         dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0;
9256                 }
9257
9258                 /* Now check if we should set freesync video mode */
9259                 if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream &&
9260                     is_timing_unchanged_for_freesync(new_crtc_state,
9261                                                      old_crtc_state)) {
9262                         new_crtc_state->mode_changed = false;
9263                         DRM_DEBUG_DRIVER(
9264                                 "Mode change not required for front porch change, "
9265                                 "setting mode_changed to %d",
9266                                 new_crtc_state->mode_changed);
9267
9268                         set_freesync_fixed_config(dm_new_crtc_state);
9269
9270                         goto skip_modeset;
9271                 } else if (amdgpu_freesync_vid_mode && aconnector &&
9272                            is_freesync_video_mode(&new_crtc_state->mode,
9273                                                   aconnector)) {
9274                         struct drm_display_mode *high_mode;
9275
9276                         high_mode = get_highest_refresh_rate_mode(aconnector, false);
9277                         if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) {
9278                                 set_freesync_fixed_config(dm_new_crtc_state);
9279                         }
9280                 }
9281
9282                 ret = dm_atomic_get_state(state, &dm_state);
9283                 if (ret)
9284                         goto fail;
9285
9286                 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
9287                                 crtc->base.id);
9288
9289                 /* i.e. reset mode */
9290                 if (dc_remove_stream_from_ctx(
9291                                 dm->dc,
9292                                 dm_state->context,
9293                                 dm_old_crtc_state->stream) != DC_OK) {
9294                         ret = -EINVAL;
9295                         goto fail;
9296                 }
9297
9298                 dc_stream_release(dm_old_crtc_state->stream);
9299                 dm_new_crtc_state->stream = NULL;
9300
9301                 reset_freesync_config_for_crtc(dm_new_crtc_state);
9302
9303                 *lock_and_validation_needed = true;
9304
9305         } else {/* Add stream for any updated/enabled CRTC */
9306                 /*
9307                  * Quick fix to prevent NULL pointer on new_stream when
9308                  * added MST connectors not found in existing crtc_state in the chained mode
9309                  * TODO: need to dig out the root cause of that
9310                  */
9311                 if (!aconnector)
9312                         goto skip_modeset;
9313
9314                 if (modereset_required(new_crtc_state))
9315                         goto skip_modeset;
9316
9317                 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream,
9318                                      dm_old_crtc_state->stream)) {
9319
9320                         WARN_ON(dm_new_crtc_state->stream);
9321
9322                         ret = dm_atomic_get_state(state, &dm_state);
9323                         if (ret)
9324                                 goto fail;
9325
9326                         dm_new_crtc_state->stream = new_stream;
9327
9328                         dc_stream_retain(new_stream);
9329
9330                         DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n",
9331                                          crtc->base.id);
9332
9333                         if (dc_add_stream_to_ctx(
9334                                         dm->dc,
9335                                         dm_state->context,
9336                                         dm_new_crtc_state->stream) != DC_OK) {
9337                                 ret = -EINVAL;
9338                                 goto fail;
9339                         }
9340
9341                         *lock_and_validation_needed = true;
9342                 }
9343         }
9344
9345 skip_modeset:
9346         /* Release extra reference */
9347         if (new_stream)
9348                 dc_stream_release(new_stream);
9349
9350         /*
9351          * We want to do dc stream updates that do not require a
9352          * full modeset below.
9353          */
9354         if (!(enable && aconnector && new_crtc_state->active))
9355                 return 0;
9356         /*
9357          * Given above conditions, the dc state cannot be NULL because:
9358          * 1. We're in the process of enabling CRTCs (just been added
9359          *    to the dc context, or already is on the context)
9360          * 2. Has a valid connector attached, and
9361          * 3. Is currently active and enabled.
9362          * => The dc stream state currently exists.
9363          */
9364         BUG_ON(dm_new_crtc_state->stream == NULL);
9365
9366         /* Scaling or underscan settings */
9367         if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) ||
9368                                 drm_atomic_crtc_needs_modeset(new_crtc_state))
9369                 update_stream_scaling_settings(
9370                         &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
9371
9372         /* ABM settings */
9373         dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9374
9375         /*
9376          * Color management settings. We also update color properties
9377          * when a modeset is needed, to ensure it gets reprogrammed.
9378          */
9379         if (dm_new_crtc_state->base.color_mgmt_changed ||
9380             drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9381                 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
9382                 if (ret)
9383                         goto fail;
9384         }
9385
9386         /* Update Freesync settings. */
9387         get_freesync_config_for_crtc(dm_new_crtc_state,
9388                                      dm_new_conn_state);
9389
9390         return ret;
9391
9392 fail:
9393         if (new_stream)
9394                 dc_stream_release(new_stream);
9395         return ret;
9396 }
9397
9398 static bool should_reset_plane(struct drm_atomic_state *state,
9399                                struct drm_plane *plane,
9400                                struct drm_plane_state *old_plane_state,
9401                                struct drm_plane_state *new_plane_state)
9402 {
9403         struct drm_plane *other;
9404         struct drm_plane_state *old_other_state, *new_other_state;
9405         struct drm_crtc_state *new_crtc_state;
9406         int i;
9407
9408         /*
9409          * TODO: Remove this hack once the checks below are sufficient
9410          * enough to determine when we need to reset all the planes on
9411          * the stream.
9412          */
9413         if (state->allow_modeset)
9414                 return true;
9415
9416         /* Exit early if we know that we're adding or removing the plane. */
9417         if (old_plane_state->crtc != new_plane_state->crtc)
9418                 return true;
9419
9420         /* old crtc == new_crtc == NULL, plane not in context. */
9421         if (!new_plane_state->crtc)
9422                 return false;
9423
9424         new_crtc_state =
9425                 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
9426
9427         if (!new_crtc_state)
9428                 return true;
9429
9430         /* CRTC Degamma changes currently require us to recreate planes. */
9431         if (new_crtc_state->color_mgmt_changed)
9432                 return true;
9433
9434         if (drm_atomic_crtc_needs_modeset(new_crtc_state))
9435                 return true;
9436
9437         /*
9438          * If there are any new primary or overlay planes being added or
9439          * removed then the z-order can potentially change. To ensure
9440          * correct z-order and pipe acquisition the current DC architecture
9441          * requires us to remove and recreate all existing planes.
9442          *
9443          * TODO: Come up with a more elegant solution for this.
9444          */
9445         for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
9446                 struct amdgpu_framebuffer *old_afb, *new_afb;
9447                 if (other->type == DRM_PLANE_TYPE_CURSOR)
9448                         continue;
9449
9450                 if (old_other_state->crtc != new_plane_state->crtc &&
9451                     new_other_state->crtc != new_plane_state->crtc)
9452                         continue;
9453
9454                 if (old_other_state->crtc != new_other_state->crtc)
9455                         return true;
9456
9457                 /* Src/dst size and scaling updates. */
9458                 if (old_other_state->src_w != new_other_state->src_w ||
9459                     old_other_state->src_h != new_other_state->src_h ||
9460                     old_other_state->crtc_w != new_other_state->crtc_w ||
9461                     old_other_state->crtc_h != new_other_state->crtc_h)
9462                         return true;
9463
9464                 /* Rotation / mirroring updates. */
9465                 if (old_other_state->rotation != new_other_state->rotation)
9466                         return true;
9467
9468                 /* Blending updates. */
9469                 if (old_other_state->pixel_blend_mode !=
9470                     new_other_state->pixel_blend_mode)
9471                         return true;
9472
9473                 /* Alpha updates. */
9474                 if (old_other_state->alpha != new_other_state->alpha)
9475                         return true;
9476
9477                 /* Colorspace changes. */
9478                 if (old_other_state->color_range != new_other_state->color_range ||
9479                     old_other_state->color_encoding != new_other_state->color_encoding)
9480                         return true;
9481
9482                 /* Framebuffer checks fall at the end. */
9483                 if (!old_other_state->fb || !new_other_state->fb)
9484                         continue;
9485
9486                 /* Pixel format changes can require bandwidth updates. */
9487                 if (old_other_state->fb->format != new_other_state->fb->format)
9488                         return true;
9489
9490                 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb;
9491                 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb;
9492
9493                 /* Tiling and DCC changes also require bandwidth updates. */
9494                 if (old_afb->tiling_flags != new_afb->tiling_flags ||
9495                     old_afb->base.modifier != new_afb->base.modifier)
9496                         return true;
9497         }
9498
9499         return false;
9500 }
9501
9502 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,
9503                               struct drm_plane_state *new_plane_state,
9504                               struct drm_framebuffer *fb)
9505 {
9506         struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev);
9507         struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
9508         unsigned int pitch;
9509         bool linear;
9510
9511         if (fb->width > new_acrtc->max_cursor_width ||
9512             fb->height > new_acrtc->max_cursor_height) {
9513                 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n",
9514                                  new_plane_state->fb->width,
9515                                  new_plane_state->fb->height);
9516                 return -EINVAL;
9517         }
9518         if (new_plane_state->src_w != fb->width << 16 ||
9519             new_plane_state->src_h != fb->height << 16) {
9520                 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9521                 return -EINVAL;
9522         }
9523
9524         /* Pitch in pixels */
9525         pitch = fb->pitches[0] / fb->format->cpp[0];
9526
9527         if (fb->width != pitch) {
9528                 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d",
9529                                  fb->width, pitch);
9530                 return -EINVAL;
9531         }
9532
9533         switch (pitch) {
9534         case 64:
9535         case 128:
9536         case 256:
9537                 /* FB pitch is supported by cursor plane */
9538                 break;
9539         default:
9540                 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch);
9541                 return -EINVAL;
9542         }
9543
9544         /* Core DRM takes care of checking FB modifiers, so we only need to
9545          * check tiling flags when the FB doesn't have a modifier. */
9546         if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) {
9547                 if (adev->family < AMDGPU_FAMILY_AI) {
9548                         linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &&
9549                                  AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &&
9550                                  AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0;
9551                 } else {
9552                         linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;
9553                 }
9554                 if (!linear) {
9555                         DRM_DEBUG_ATOMIC("Cursor FB not linear");
9556                         return -EINVAL;
9557                 }
9558         }
9559
9560         return 0;
9561 }
9562
9563 static int dm_update_plane_state(struct dc *dc,
9564                                  struct drm_atomic_state *state,
9565                                  struct drm_plane *plane,
9566                                  struct drm_plane_state *old_plane_state,
9567                                  struct drm_plane_state *new_plane_state,
9568                                  bool enable,
9569                                  bool *lock_and_validation_needed,
9570                                  bool *is_top_most_overlay)
9571 {
9572
9573         struct dm_atomic_state *dm_state = NULL;
9574         struct drm_crtc *new_plane_crtc, *old_plane_crtc;
9575         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9576         struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
9577         struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
9578         struct amdgpu_crtc *new_acrtc;
9579         bool needs_reset;
9580         int ret = 0;
9581
9582
9583         new_plane_crtc = new_plane_state->crtc;
9584         old_plane_crtc = old_plane_state->crtc;
9585         dm_new_plane_state = to_dm_plane_state(new_plane_state);
9586         dm_old_plane_state = to_dm_plane_state(old_plane_state);
9587
9588         if (plane->type == DRM_PLANE_TYPE_CURSOR) {
9589                 if (!enable || !new_plane_crtc ||
9590                         drm_atomic_plane_disabling(plane->state, new_plane_state))
9591                         return 0;
9592
9593                 new_acrtc = to_amdgpu_crtc(new_plane_crtc);
9594
9595                 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) {
9596                         DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9597                         return -EINVAL;
9598                 }
9599
9600                 if (new_plane_state->fb) {
9601                         ret = dm_check_cursor_fb(new_acrtc, new_plane_state,
9602                                                  new_plane_state->fb);
9603                         if (ret)
9604                                 return ret;
9605                 }
9606
9607                 return 0;
9608         }
9609
9610         needs_reset = should_reset_plane(state, plane, old_plane_state,
9611                                          new_plane_state);
9612
9613         /* Remove any changed/removed planes */
9614         if (!enable) {
9615                 if (!needs_reset)
9616                         return 0;
9617
9618                 if (!old_plane_crtc)
9619                         return 0;
9620
9621                 old_crtc_state = drm_atomic_get_old_crtc_state(
9622                                 state, old_plane_crtc);
9623                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9624
9625                 if (!dm_old_crtc_state->stream)
9626                         return 0;
9627
9628                 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
9629                                 plane->base.id, old_plane_crtc->base.id);
9630
9631                 ret = dm_atomic_get_state(state, &dm_state);
9632                 if (ret)
9633                         return ret;
9634
9635                 if (!dc_remove_plane_from_context(
9636                                 dc,
9637                                 dm_old_crtc_state->stream,
9638                                 dm_old_plane_state->dc_state,
9639                                 dm_state->context)) {
9640
9641                         return -EINVAL;
9642                 }
9643
9644                 if (dm_old_plane_state->dc_state)
9645                         dc_plane_state_release(dm_old_plane_state->dc_state);
9646
9647                 dm_new_plane_state->dc_state = NULL;
9648
9649                 *lock_and_validation_needed = true;
9650
9651         } else { /* Add new planes */
9652                 struct dc_plane_state *dc_new_plane_state;
9653
9654                 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
9655                         return 0;
9656
9657                 if (!new_plane_crtc)
9658                         return 0;
9659
9660                 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
9661                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9662
9663                 if (!dm_new_crtc_state->stream)
9664                         return 0;
9665
9666                 if (!needs_reset)
9667                         return 0;
9668
9669                 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state);
9670                 if (ret)
9671                         return ret;
9672
9673                 WARN_ON(dm_new_plane_state->dc_state);
9674
9675                 dc_new_plane_state = dc_create_plane_state(dc);
9676                 if (!dc_new_plane_state)
9677                         return -ENOMEM;
9678
9679                 /* Block top most plane from being a video plane */
9680                 if (plane->type == DRM_PLANE_TYPE_OVERLAY) {
9681                         if (is_video_format(new_plane_state->fb->format->format) && *is_top_most_overlay)
9682                                 return -EINVAL;
9683                         else
9684                                 *is_top_most_overlay = false;
9685                 }
9686
9687                 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n",
9688                                  plane->base.id, new_plane_crtc->base.id);
9689
9690                 ret = fill_dc_plane_attributes(
9691                         drm_to_adev(new_plane_crtc->dev),
9692                         dc_new_plane_state,
9693                         new_plane_state,
9694                         new_crtc_state);
9695                 if (ret) {
9696                         dc_plane_state_release(dc_new_plane_state);
9697                         return ret;
9698                 }
9699
9700                 ret = dm_atomic_get_state(state, &dm_state);
9701                 if (ret) {
9702                         dc_plane_state_release(dc_new_plane_state);
9703                         return ret;
9704                 }
9705
9706                 /*
9707                  * Any atomic check errors that occur after this will
9708                  * not need a release. The plane state will be attached
9709                  * to the stream, and therefore part of the atomic
9710                  * state. It'll be released when the atomic state is
9711                  * cleaned.
9712                  */
9713                 if (!dc_add_plane_to_context(
9714                                 dc,
9715                                 dm_new_crtc_state->stream,
9716                                 dc_new_plane_state,
9717                                 dm_state->context)) {
9718
9719                         dc_plane_state_release(dc_new_plane_state);
9720                         return -EINVAL;
9721                 }
9722
9723                 dm_new_plane_state->dc_state = dc_new_plane_state;
9724
9725                 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY);
9726
9727                 /* Tell DC to do a full surface update every time there
9728                  * is a plane change. Inefficient, but works for now.
9729                  */
9730                 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
9731
9732                 *lock_and_validation_needed = true;
9733         }
9734
9735
9736         return ret;
9737 }
9738
9739 static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state,
9740                                        int *src_w, int *src_h)
9741 {
9742         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
9743         case DRM_MODE_ROTATE_90:
9744         case DRM_MODE_ROTATE_270:
9745                 *src_w = plane_state->src_h >> 16;
9746                 *src_h = plane_state->src_w >> 16;
9747                 break;
9748         case DRM_MODE_ROTATE_0:
9749         case DRM_MODE_ROTATE_180:
9750         default:
9751                 *src_w = plane_state->src_w >> 16;
9752                 *src_h = plane_state->src_h >> 16;
9753                 break;
9754         }
9755 }
9756
9757 static int dm_check_crtc_cursor(struct drm_atomic_state *state,
9758                                 struct drm_crtc *crtc,
9759                                 struct drm_crtc_state *new_crtc_state)
9760 {
9761         struct drm_plane *cursor = crtc->cursor, *underlying;
9762         struct drm_plane_state *new_cursor_state, *new_underlying_state;
9763         int i;
9764         int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h;
9765         int cursor_src_w, cursor_src_h;
9766         int underlying_src_w, underlying_src_h;
9767
9768         /* On DCE and DCN there is no dedicated hardware cursor plane. We get a
9769          * cursor per pipe but it's going to inherit the scaling and
9770          * positioning from the underlying pipe. Check the cursor plane's
9771          * blending properties match the underlying planes'. */
9772
9773         new_cursor_state = drm_atomic_get_new_plane_state(state, cursor);
9774         if (!new_cursor_state || !new_cursor_state->fb) {
9775                 return 0;
9776         }
9777
9778         dm_get_oriented_plane_size(new_cursor_state, &cursor_src_w, &cursor_src_h);
9779         cursor_scale_w = new_cursor_state->crtc_w * 1000 / cursor_src_w;
9780         cursor_scale_h = new_cursor_state->crtc_h * 1000 / cursor_src_h;
9781
9782         for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) {
9783                 /* Narrow down to non-cursor planes on the same CRTC as the cursor */
9784                 if (new_underlying_state->crtc != crtc || underlying == crtc->cursor)
9785                         continue;
9786
9787                 /* Ignore disabled planes */
9788                 if (!new_underlying_state->fb)
9789                         continue;
9790
9791                 dm_get_oriented_plane_size(new_underlying_state,
9792                                            &underlying_src_w, &underlying_src_h);
9793                 underlying_scale_w = new_underlying_state->crtc_w * 1000 / underlying_src_w;
9794                 underlying_scale_h = new_underlying_state->crtc_h * 1000 / underlying_src_h;
9795
9796                 if (cursor_scale_w != underlying_scale_w ||
9797                     cursor_scale_h != underlying_scale_h) {
9798                         drm_dbg_atomic(crtc->dev,
9799                                        "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n",
9800                                        cursor->base.id, cursor->name, underlying->base.id, underlying->name);
9801                         return -EINVAL;
9802                 }
9803
9804                 /* If this plane covers the whole CRTC, no need to check planes underneath */
9805                 if (new_underlying_state->crtc_x <= 0 &&
9806                     new_underlying_state->crtc_y <= 0 &&
9807                     new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay &&
9808                     new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay)
9809                         break;
9810         }
9811
9812         return 0;
9813 }
9814
9815 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
9816 {
9817         struct drm_connector *connector;
9818         struct drm_connector_state *conn_state, *old_conn_state;
9819         struct amdgpu_dm_connector *aconnector = NULL;
9820         int i;
9821         for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) {
9822                 if (!conn_state->crtc)
9823                         conn_state = old_conn_state;
9824
9825                 if (conn_state->crtc != crtc)
9826                         continue;
9827
9828                 aconnector = to_amdgpu_dm_connector(connector);
9829                 if (!aconnector->mst_output_port || !aconnector->mst_root)
9830                         aconnector = NULL;
9831                 else
9832                         break;
9833         }
9834
9835         if (!aconnector)
9836                 return 0;
9837
9838         return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr);
9839 }
9840
9841 /**
9842  * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
9843  *
9844  * @dev: The DRM device
9845  * @state: The atomic state to commit
9846  *
9847  * Validate that the given atomic state is programmable by DC into hardware.
9848  * This involves constructing a &struct dc_state reflecting the new hardware
9849  * state we wish to commit, then querying DC to see if it is programmable. It's
9850  * important not to modify the existing DC state. Otherwise, atomic_check
9851  * may unexpectedly commit hardware changes.
9852  *
9853  * When validating the DC state, it's important that the right locks are
9854  * acquired. For full updates case which removes/adds/updates streams on one
9855  * CRTC while flipping on another CRTC, acquiring global lock will guarantee
9856  * that any such full update commit will wait for completion of any outstanding
9857  * flip using DRMs synchronization events.
9858  *
9859  * Note that DM adds the affected connectors for all CRTCs in state, when that
9860  * might not seem necessary. This is because DC stream creation requires the
9861  * DC sink, which is tied to the DRM connector state. Cleaning this up should
9862  * be possible but non-trivial - a possible TODO item.
9863  *
9864  * Return: -Error code if validation failed.
9865  */
9866 static int amdgpu_dm_atomic_check(struct drm_device *dev,
9867                                   struct drm_atomic_state *state)
9868 {
9869         struct amdgpu_device *adev = drm_to_adev(dev);
9870         struct dm_atomic_state *dm_state = NULL;
9871         struct dc *dc = adev->dm.dc;
9872         struct drm_connector *connector;
9873         struct drm_connector_state *old_con_state, *new_con_state;
9874         struct drm_crtc *crtc;
9875         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9876         struct drm_plane *plane;
9877         struct drm_plane_state *old_plane_state, *new_plane_state;
9878         enum dc_status status;
9879         int ret, i;
9880         bool lock_and_validation_needed = false;
9881         bool is_top_most_overlay = true;
9882         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9883         struct drm_dp_mst_topology_mgr *mgr;
9884         struct drm_dp_mst_topology_state *mst_state;
9885         struct dsc_mst_fairness_vars vars[MAX_PIPES];
9886
9887         trace_amdgpu_dm_atomic_check_begin(state);
9888
9889         ret = drm_atomic_helper_check_modeset(dev, state);
9890         if (ret) {
9891                 DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n");
9892                 goto fail;
9893         }
9894
9895         /* Check connector changes */
9896         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9897                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
9898                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9899
9900                 /* Skip connectors that are disabled or part of modeset already. */
9901                 if (!new_con_state->crtc)
9902                         continue;
9903
9904                 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc);
9905                 if (IS_ERR(new_crtc_state)) {
9906                         DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n");
9907                         ret = PTR_ERR(new_crtc_state);
9908                         goto fail;
9909                 }
9910
9911                 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level ||
9912                     dm_old_con_state->scaling != dm_new_con_state->scaling)
9913                         new_crtc_state->connectors_changed = true;
9914         }
9915
9916         if (dc_resource_is_dsc_encoding_supported(dc)) {
9917                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9918                         if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9919                                 ret = add_affected_mst_dsc_crtcs(state, crtc);
9920                                 if (ret) {
9921                                         DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n");
9922                                         goto fail;
9923                                 }
9924                         }
9925                 }
9926         }
9927         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9928                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9929
9930                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
9931                     !new_crtc_state->color_mgmt_changed &&
9932                     old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled &&
9933                         dm_old_crtc_state->dsc_force_changed == false)
9934                         continue;
9935
9936                 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state);
9937                 if (ret) {
9938                         DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n");
9939                         goto fail;
9940                 }
9941
9942                 if (!new_crtc_state->enable)
9943                         continue;
9944
9945                 ret = drm_atomic_add_affected_connectors(state, crtc);
9946                 if (ret) {
9947                         DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n");
9948                         goto fail;
9949                 }
9950
9951                 ret = drm_atomic_add_affected_planes(state, crtc);
9952                 if (ret) {
9953                         DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n");
9954                         goto fail;
9955                 }
9956
9957                 if (dm_old_crtc_state->dsc_force_changed)
9958                         new_crtc_state->mode_changed = true;
9959         }
9960
9961         /*
9962          * Add all primary and overlay planes on the CRTC to the state
9963          * whenever a plane is enabled to maintain correct z-ordering
9964          * and to enable fast surface updates.
9965          */
9966         drm_for_each_crtc(crtc, dev) {
9967                 bool modified = false;
9968
9969                 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
9970                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
9971                                 continue;
9972
9973                         if (new_plane_state->crtc == crtc ||
9974                             old_plane_state->crtc == crtc) {
9975                                 modified = true;
9976                                 break;
9977                         }
9978                 }
9979
9980                 if (!modified)
9981                         continue;
9982
9983                 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
9984                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
9985                                 continue;
9986
9987                         new_plane_state =
9988                                 drm_atomic_get_plane_state(state, plane);
9989
9990                         if (IS_ERR(new_plane_state)) {
9991                                 ret = PTR_ERR(new_plane_state);
9992                                 DRM_DEBUG_DRIVER("new_plane_state is BAD\n");
9993                                 goto fail;
9994                         }
9995                 }
9996         }
9997
9998         /*
9999          * DC consults the zpos (layer_index in DC terminology) to determine the
10000          * hw plane on which to enable the hw cursor (see
10001          * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in
10002          * atomic state, so call drm helper to normalize zpos.
10003          */
10004         ret = drm_atomic_normalize_zpos(dev, state);
10005         if (ret) {
10006                 drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n");
10007                 goto fail;
10008         }
10009
10010         /* Remove exiting planes if they are modified */
10011         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10012                 ret = dm_update_plane_state(dc, state, plane,
10013                                             old_plane_state,
10014                                             new_plane_state,
10015                                             false,
10016                                             &lock_and_validation_needed,
10017                                             &is_top_most_overlay);
10018                 if (ret) {
10019                         DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10020                         goto fail;
10021                 }
10022         }
10023
10024         /* Disable all crtcs which require disable */
10025         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10026                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10027                                            old_crtc_state,
10028                                            new_crtc_state,
10029                                            false,
10030                                            &lock_and_validation_needed);
10031                 if (ret) {
10032                         DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n");
10033                         goto fail;
10034                 }
10035         }
10036
10037         /* Enable all crtcs which require enable */
10038         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10039                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10040                                            old_crtc_state,
10041                                            new_crtc_state,
10042                                            true,
10043                                            &lock_and_validation_needed);
10044                 if (ret) {
10045                         DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n");
10046                         goto fail;
10047                 }
10048         }
10049
10050         /* Add new/modified planes */
10051         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10052                 ret = dm_update_plane_state(dc, state, plane,
10053                                             old_plane_state,
10054                                             new_plane_state,
10055                                             true,
10056                                             &lock_and_validation_needed,
10057                                             &is_top_most_overlay);
10058                 if (ret) {
10059                         DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10060                         goto fail;
10061                 }
10062         }
10063
10064         if (dc_resource_is_dsc_encoding_supported(dc)) {
10065                 ret = pre_validate_dsc(state, &dm_state, vars);
10066                 if (ret != 0)
10067                         goto fail;
10068         }
10069
10070         /* Run this here since we want to validate the streams we created */
10071         ret = drm_atomic_helper_check_planes(dev, state);
10072         if (ret) {
10073                 DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n");
10074                 goto fail;
10075         }
10076
10077         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10078                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
10079                 if (dm_new_crtc_state->mpo_requested)
10080                         DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc);
10081         }
10082
10083         /* Check cursor planes scaling */
10084         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10085                 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state);
10086                 if (ret) {
10087                         DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n");
10088                         goto fail;
10089                 }
10090         }
10091
10092         if (state->legacy_cursor_update) {
10093                 /*
10094                  * This is a fast cursor update coming from the plane update
10095                  * helper, check if it can be done asynchronously for better
10096                  * performance.
10097                  */
10098                 state->async_update =
10099                         !drm_atomic_helper_async_check(dev, state);
10100
10101                 /*
10102                  * Skip the remaining global validation if this is an async
10103                  * update. Cursor updates can be done without affecting
10104                  * state or bandwidth calcs and this avoids the performance
10105                  * penalty of locking the private state object and
10106                  * allocating a new dc_state.
10107                  */
10108                 if (state->async_update)
10109                         return 0;
10110         }
10111
10112         /* Check scaling and underscan changes*/
10113         /* TODO Removed scaling changes validation due to inability to commit
10114          * new stream into context w\o causing full reset. Need to
10115          * decide how to handle.
10116          */
10117         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
10118                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
10119                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10120                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
10121
10122                 /* Skip any modesets/resets */
10123                 if (!acrtc || drm_atomic_crtc_needs_modeset(
10124                                 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
10125                         continue;
10126
10127                 /* Skip any thing not scale or underscan changes */
10128                 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
10129                         continue;
10130
10131                 lock_and_validation_needed = true;
10132         }
10133
10134         /* set the slot info for each mst_state based on the link encoding format */
10135         for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
10136                 struct amdgpu_dm_connector *aconnector;
10137                 struct drm_connector *connector;
10138                 struct drm_connector_list_iter iter;
10139                 u8 link_coding_cap;
10140
10141                 drm_connector_list_iter_begin(dev, &iter);
10142                 drm_for_each_connector_iter(connector, &iter) {
10143                         if (connector->index == mst_state->mgr->conn_base_id) {
10144                                 aconnector = to_amdgpu_dm_connector(connector);
10145                                 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link);
10146                                 drm_dp_mst_update_slots(mst_state, link_coding_cap);
10147
10148                                 break;
10149                         }
10150                 }
10151                 drm_connector_list_iter_end(&iter);
10152         }
10153
10154         /**
10155          * Streams and planes are reset when there are changes that affect
10156          * bandwidth. Anything that affects bandwidth needs to go through
10157          * DC global validation to ensure that the configuration can be applied
10158          * to hardware.
10159          *
10160          * We have to currently stall out here in atomic_check for outstanding
10161          * commits to finish in this case because our IRQ handlers reference
10162          * DRM state directly - we can end up disabling interrupts too early
10163          * if we don't.
10164          *
10165          * TODO: Remove this stall and drop DM state private objects.
10166          */
10167         if (lock_and_validation_needed) {
10168                 ret = dm_atomic_get_state(state, &dm_state);
10169                 if (ret) {
10170                         DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n");
10171                         goto fail;
10172                 }
10173
10174                 ret = do_aquire_global_lock(dev, state);
10175                 if (ret) {
10176                         DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n");
10177                         goto fail;
10178                 }
10179
10180                 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars);
10181                 if (ret) {
10182                         DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n");
10183                         ret = -EINVAL;
10184                         goto fail;
10185                 }
10186
10187                 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars);
10188                 if (ret) {
10189                         DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n");
10190                         goto fail;
10191                 }
10192
10193                 /*
10194                  * Perform validation of MST topology in the state:
10195                  * We need to perform MST atomic check before calling
10196                  * dc_validate_global_state(), or there is a chance
10197                  * to get stuck in an infinite loop and hang eventually.
10198                  */
10199                 ret = drm_dp_mst_atomic_check(state);
10200                 if (ret) {
10201                         DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n");
10202                         goto fail;
10203                 }
10204                 status = dc_validate_global_state(dc, dm_state->context, true);
10205                 if (status != DC_OK) {
10206                         DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)",
10207                                        dc_status_to_str(status), status);
10208                         ret = -EINVAL;
10209                         goto fail;
10210                 }
10211         } else {
10212                 /*
10213                  * The commit is a fast update. Fast updates shouldn't change
10214                  * the DC context, affect global validation, and can have their
10215                  * commit work done in parallel with other commits not touching
10216                  * the same resource. If we have a new DC context as part of
10217                  * the DM atomic state from validation we need to free it and
10218                  * retain the existing one instead.
10219                  *
10220                  * Furthermore, since the DM atomic state only contains the DC
10221                  * context and can safely be annulled, we can free the state
10222                  * and clear the associated private object now to free
10223                  * some memory and avoid a possible use-after-free later.
10224                  */
10225
10226                 for (i = 0; i < state->num_private_objs; i++) {
10227                         struct drm_private_obj *obj = state->private_objs[i].ptr;
10228
10229                         if (obj->funcs == adev->dm.atomic_obj.funcs) {
10230                                 int j = state->num_private_objs-1;
10231
10232                                 dm_atomic_destroy_state(obj,
10233                                                 state->private_objs[i].state);
10234
10235                                 /* If i is not at the end of the array then the
10236                                  * last element needs to be moved to where i was
10237                                  * before the array can safely be truncated.
10238                                  */
10239                                 if (i != j)
10240                                         state->private_objs[i] =
10241                                                 state->private_objs[j];
10242
10243                                 state->private_objs[j].ptr = NULL;
10244                                 state->private_objs[j].state = NULL;
10245                                 state->private_objs[j].old_state = NULL;
10246                                 state->private_objs[j].new_state = NULL;
10247
10248                                 state->num_private_objs = j;
10249                                 break;
10250                         }
10251                 }
10252         }
10253
10254         /* Store the overall update type for use later in atomic check. */
10255         for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
10256                 struct dm_crtc_state *dm_new_crtc_state =
10257                         to_dm_crtc_state(new_crtc_state);
10258
10259                 dm_new_crtc_state->update_type = lock_and_validation_needed ?
10260                                                          UPDATE_TYPE_FULL :
10261                                                          UPDATE_TYPE_FAST;
10262         }
10263
10264         /* Must be success */
10265         WARN_ON(ret);
10266
10267         trace_amdgpu_dm_atomic_check_finish(state, ret);
10268
10269         return ret;
10270
10271 fail:
10272         if (ret == -EDEADLK)
10273                 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
10274         else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
10275                 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
10276         else
10277                 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
10278
10279         trace_amdgpu_dm_atomic_check_finish(state, ret);
10280
10281         return ret;
10282 }
10283
10284 static bool is_dp_capable_without_timing_msa(struct dc *dc,
10285                                              struct amdgpu_dm_connector *amdgpu_dm_connector)
10286 {
10287         u8 dpcd_data;
10288         bool capable = false;
10289
10290         if (amdgpu_dm_connector->dc_link &&
10291                 dm_helpers_dp_read_dpcd(
10292                                 NULL,
10293                                 amdgpu_dm_connector->dc_link,
10294                                 DP_DOWN_STREAM_PORT_COUNT,
10295                                 &dpcd_data,
10296                                 sizeof(dpcd_data))) {
10297                 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
10298         }
10299
10300         return capable;
10301 }
10302
10303 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,
10304                 unsigned int offset,
10305                 unsigned int total_length,
10306                 u8 *data,
10307                 unsigned int length,
10308                 struct amdgpu_hdmi_vsdb_info *vsdb)
10309 {
10310         bool res;
10311         union dmub_rb_cmd cmd;
10312         struct dmub_cmd_send_edid_cea *input;
10313         struct dmub_cmd_edid_cea_output *output;
10314
10315         if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES)
10316                 return false;
10317
10318         memset(&cmd, 0, sizeof(cmd));
10319
10320         input = &cmd.edid_cea.data.input;
10321
10322         cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA;
10323         cmd.edid_cea.header.sub_type = 0;
10324         cmd.edid_cea.header.payload_bytes =
10325                 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header);
10326         input->offset = offset;
10327         input->length = length;
10328         input->cea_total_length = total_length;
10329         memcpy(input->payload, data, length);
10330
10331         res = dc_dmub_srv_cmd_with_reply_data(dm->dc->ctx->dmub_srv, &cmd);
10332         if (!res) {
10333                 DRM_ERROR("EDID CEA parser failed\n");
10334                 return false;
10335         }
10336
10337         output = &cmd.edid_cea.data.output;
10338
10339         if (output->type == DMUB_CMD__EDID_CEA_ACK) {
10340                 if (!output->ack.success) {
10341                         DRM_ERROR("EDID CEA ack failed at offset %d\n",
10342                                         output->ack.offset);
10343                 }
10344         } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) {
10345                 if (!output->amd_vsdb.vsdb_found)
10346                         return false;
10347
10348                 vsdb->freesync_supported = output->amd_vsdb.freesync_supported;
10349                 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version;
10350                 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate;
10351                 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate;
10352         } else {
10353                 DRM_WARN("Unknown EDID CEA parser results\n");
10354                 return false;
10355         }
10356
10357         return true;
10358 }
10359
10360 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm,
10361                 u8 *edid_ext, int len,
10362                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10363 {
10364         int i;
10365
10366         /* send extension block to DMCU for parsing */
10367         for (i = 0; i < len; i += 8) {
10368                 bool res;
10369                 int offset;
10370
10371                 /* send 8 bytes a time */
10372                 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8))
10373                         return false;
10374
10375                 if (i+8 == len) {
10376                         /* EDID block sent completed, expect result */
10377                         int version, min_rate, max_rate;
10378
10379                         res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate);
10380                         if (res) {
10381                                 /* amd vsdb found */
10382                                 vsdb_info->freesync_supported = 1;
10383                                 vsdb_info->amd_vsdb_version = version;
10384                                 vsdb_info->min_refresh_rate_hz = min_rate;
10385                                 vsdb_info->max_refresh_rate_hz = max_rate;
10386                                 return true;
10387                         }
10388                         /* not amd vsdb */
10389                         return false;
10390                 }
10391
10392                 /* check for ack*/
10393                 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset);
10394                 if (!res)
10395                         return false;
10396         }
10397
10398         return false;
10399 }
10400
10401 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm,
10402                 u8 *edid_ext, int len,
10403                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10404 {
10405         int i;
10406
10407         /* send extension block to DMCU for parsing */
10408         for (i = 0; i < len; i += 8) {
10409                 /* send 8 bytes a time */
10410                 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info))
10411                         return false;
10412         }
10413
10414         return vsdb_info->freesync_supported;
10415 }
10416
10417 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
10418                 u8 *edid_ext, int len,
10419                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10420 {
10421         struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
10422         bool ret;
10423
10424         mutex_lock(&adev->dm.dc_lock);
10425         if (adev->dm.dmub_srv)
10426                 ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info);
10427         else
10428                 ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info);
10429         mutex_unlock(&adev->dm.dc_lock);
10430         return ret;
10431 }
10432
10433 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
10434                 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
10435 {
10436         u8 *edid_ext = NULL;
10437         int i;
10438         bool valid_vsdb_found = false;
10439
10440         /*----- drm_find_cea_extension() -----*/
10441         /* No EDID or EDID extensions */
10442         if (edid == NULL || edid->extensions == 0)
10443                 return -ENODEV;
10444
10445         /* Find CEA extension */
10446         for (i = 0; i < edid->extensions; i++) {
10447                 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1);
10448                 if (edid_ext[0] == CEA_EXT)
10449                         break;
10450         }
10451
10452         if (i == edid->extensions)
10453                 return -ENODEV;
10454
10455         /*----- cea_db_offsets() -----*/
10456         if (edid_ext[0] != CEA_EXT)
10457                 return -ENODEV;
10458
10459         valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info);
10460
10461         return valid_vsdb_found ? i : -ENODEV;
10462 }
10463
10464 /**
10465  * amdgpu_dm_update_freesync_caps - Update Freesync capabilities
10466  *
10467  * @connector: Connector to query.
10468  * @edid: EDID from monitor
10469  *
10470  * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep
10471  * track of some of the display information in the internal data struct used by
10472  * amdgpu_dm. This function checks which type of connector we need to set the
10473  * FreeSync parameters.
10474  */
10475 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
10476                                     struct edid *edid)
10477 {
10478         int i = 0;
10479         struct detailed_timing *timing;
10480         struct detailed_non_pixel *data;
10481         struct detailed_data_monitor_range *range;
10482         struct amdgpu_dm_connector *amdgpu_dm_connector =
10483                         to_amdgpu_dm_connector(connector);
10484         struct dm_connector_state *dm_con_state = NULL;
10485         struct dc_sink *sink;
10486
10487         struct drm_device *dev = connector->dev;
10488         struct amdgpu_device *adev = drm_to_adev(dev);
10489         struct amdgpu_hdmi_vsdb_info vsdb_info = {0};
10490         bool freesync_capable = false;
10491         enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE;
10492
10493         if (!connector->state) {
10494                 DRM_ERROR("%s - Connector has no state", __func__);
10495                 goto update;
10496         }
10497
10498         sink = amdgpu_dm_connector->dc_sink ?
10499                 amdgpu_dm_connector->dc_sink :
10500                 amdgpu_dm_connector->dc_em_sink;
10501
10502         if (!edid || !sink) {
10503                 dm_con_state = to_dm_connector_state(connector->state);
10504
10505                 amdgpu_dm_connector->min_vfreq = 0;
10506                 amdgpu_dm_connector->max_vfreq = 0;
10507                 amdgpu_dm_connector->pixel_clock_mhz = 0;
10508                 connector->display_info.monitor_range.min_vfreq = 0;
10509                 connector->display_info.monitor_range.max_vfreq = 0;
10510                 freesync_capable = false;
10511
10512                 goto update;
10513         }
10514
10515         dm_con_state = to_dm_connector_state(connector->state);
10516
10517         if (!adev->dm.freesync_module)
10518                 goto update;
10519
10520         if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
10521                 || sink->sink_signal == SIGNAL_TYPE_EDP) {
10522                 bool edid_check_required = false;
10523
10524                 if (edid) {
10525                         edid_check_required = is_dp_capable_without_timing_msa(
10526                                                 adev->dm.dc,
10527                                                 amdgpu_dm_connector);
10528                 }
10529
10530                 if (edid_check_required == true && (edid->version > 1 ||
10531                    (edid->version == 1 && edid->revision > 1))) {
10532                         for (i = 0; i < 4; i++) {
10533
10534                                 timing  = &edid->detailed_timings[i];
10535                                 data    = &timing->data.other_data;
10536                                 range   = &data->data.range;
10537                                 /*
10538                                  * Check if monitor has continuous frequency mode
10539                                  */
10540                                 if (data->type != EDID_DETAIL_MONITOR_RANGE)
10541                                         continue;
10542                                 /*
10543                                  * Check for flag range limits only. If flag == 1 then
10544                                  * no additional timing information provided.
10545                                  * Default GTF, GTF Secondary curve and CVT are not
10546                                  * supported
10547                                  */
10548                                 if (range->flags != 1)
10549                                         continue;
10550
10551                                 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
10552                                 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
10553                                 amdgpu_dm_connector->pixel_clock_mhz =
10554                                         range->pixel_clock_mhz * 10;
10555
10556                                 connector->display_info.monitor_range.min_vfreq = range->min_vfreq;
10557                                 connector->display_info.monitor_range.max_vfreq = range->max_vfreq;
10558
10559                                 break;
10560                         }
10561
10562                         if (amdgpu_dm_connector->max_vfreq -
10563                             amdgpu_dm_connector->min_vfreq > 10) {
10564
10565                                 freesync_capable = true;
10566                         }
10567                 }
10568         } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
10569                 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10570                 if (i >= 0 && vsdb_info.freesync_supported) {
10571                         timing  = &edid->detailed_timings[i];
10572                         data    = &timing->data.other_data;
10573
10574                         amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10575                         amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10576                         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10577                                 freesync_capable = true;
10578
10579                         connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10580                         connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10581                 }
10582         }
10583
10584         as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link);
10585
10586         if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {
10587                 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10588                 if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) {
10589
10590                         amdgpu_dm_connector->pack_sdp_v1_3 = true;
10591                         amdgpu_dm_connector->as_type = as_type;
10592                         amdgpu_dm_connector->vsdb_info = vsdb_info;
10593
10594                         amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10595                         amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10596                         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10597                                 freesync_capable = true;
10598
10599                         connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10600                         connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10601                 }
10602         }
10603
10604 update:
10605         if (dm_con_state)
10606                 dm_con_state->freesync_capable = freesync_capable;
10607
10608         if (connector->vrr_capable_property)
10609                 drm_connector_set_vrr_capable_property(connector,
10610                                                        freesync_capable);
10611 }
10612
10613 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
10614 {
10615         struct amdgpu_device *adev = drm_to_adev(dev);
10616         struct dc *dc = adev->dm.dc;
10617         int i;
10618
10619         mutex_lock(&adev->dm.dc_lock);
10620         if (dc->current_state) {
10621                 for (i = 0; i < dc->current_state->stream_count; ++i)
10622                         dc->current_state->streams[i]
10623                                 ->triggered_crtc_reset.enabled =
10624                                 adev->dm.force_timing_sync;
10625
10626                 dm_enable_per_frame_crtc_master_sync(dc->current_state);
10627                 dc_trigger_sync(dc, dc->current_state);
10628         }
10629         mutex_unlock(&adev->dm.dc_lock);
10630 }
10631
10632 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
10633                        u32 value, const char *func_name)
10634 {
10635 #ifdef DM_CHECK_ADDR_0
10636         if (address == 0) {
10637                 DC_ERR("invalid register write. address = 0");
10638                 return;
10639         }
10640 #endif
10641         cgs_write_register(ctx->cgs_device, address, value);
10642         trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
10643 }
10644
10645 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
10646                           const char *func_name)
10647 {
10648         u32 value;
10649 #ifdef DM_CHECK_ADDR_0
10650         if (address == 0) {
10651                 DC_ERR("invalid register read; address = 0\n");
10652                 return 0;
10653         }
10654 #endif
10655
10656         if (ctx->dmub_srv &&
10657             ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
10658             !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
10659                 ASSERT(false);
10660                 return 0;
10661         }
10662
10663         value = cgs_read_register(ctx->cgs_device, address);
10664
10665         trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
10666
10667         return value;
10668 }
10669
10670 int amdgpu_dm_process_dmub_aux_transfer_sync(
10671                 struct dc_context *ctx,
10672                 unsigned int link_index,
10673                 struct aux_payload *payload,
10674                 enum aux_return_code_type *operation_result)
10675 {
10676         struct amdgpu_device *adev = ctx->driver_context;
10677         struct dmub_notification *p_notify = adev->dm.dmub_notify;
10678         int ret = -1;
10679
10680         mutex_lock(&adev->dm.dpia_aux_lock);
10681         if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) {
10682                 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE;
10683                 goto out;
10684         }
10685
10686         if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10687                 DRM_ERROR("wait_for_completion_timeout timeout!");
10688                 *operation_result = AUX_RET_ERROR_TIMEOUT;
10689                 goto out;
10690         }
10691
10692         if (p_notify->result != AUX_RET_SUCCESS) {
10693                 /*
10694                  * Transient states before tunneling is enabled could
10695                  * lead to this error. We can ignore this for now.
10696                  */
10697                 if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) {
10698                         DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n",
10699                                         payload->address, payload->length,
10700                                         p_notify->result);
10701                 }
10702                 *operation_result = AUX_RET_ERROR_INVALID_REPLY;
10703                 goto out;
10704         }
10705
10706
10707         payload->reply[0] = adev->dm.dmub_notify->aux_reply.command;
10708         if (!payload->write && p_notify->aux_reply.length &&
10709                         (payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) {
10710
10711                 if (payload->length != p_notify->aux_reply.length) {
10712                         DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n",
10713                                 p_notify->aux_reply.length,
10714                                         payload->address, payload->length);
10715                         *operation_result = AUX_RET_ERROR_INVALID_REPLY;
10716                         goto out;
10717                 }
10718
10719                 memcpy(payload->data, p_notify->aux_reply.data,
10720                                 p_notify->aux_reply.length);
10721         }
10722
10723         /* success */
10724         ret = p_notify->aux_reply.length;
10725         *operation_result = p_notify->result;
10726 out:
10727         reinit_completion(&adev->dm.dmub_aux_transfer_done);
10728         mutex_unlock(&adev->dm.dpia_aux_lock);
10729         return ret;
10730 }
10731
10732 int amdgpu_dm_process_dmub_set_config_sync(
10733                 struct dc_context *ctx,
10734                 unsigned int link_index,
10735                 struct set_config_cmd_payload *payload,
10736                 enum set_config_status *operation_result)
10737 {
10738         struct amdgpu_device *adev = ctx->driver_context;
10739         bool is_cmd_complete;
10740         int ret;
10741
10742         mutex_lock(&adev->dm.dpia_aux_lock);
10743         is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc,
10744                         link_index, payload, adev->dm.dmub_notify);
10745
10746         if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10747                 ret = 0;
10748                 *operation_result = adev->dm.dmub_notify->sc_status;
10749         } else {
10750                 DRM_ERROR("wait_for_completion_timeout timeout!");
10751                 ret = -1;
10752                 *operation_result = SET_CONFIG_UNKNOWN_ERROR;
10753         }
10754
10755         if (!is_cmd_complete)
10756                 reinit_completion(&adev->dm.dmub_aux_transfer_done);
10757         mutex_unlock(&adev->dm.dpia_aux_lock);
10758         return ret;
10759 }
10760
10761 /*
10762  * Check whether seamless boot is supported.
10763  *
10764  * So far we only support seamless boot on CHIP_VANGOGH.
10765  * If everything goes well, we may consider expanding
10766  * seamless boot to other ASICs.
10767  */
10768 bool check_seamless_boot_capability(struct amdgpu_device *adev)
10769 {
10770         switch (adev->ip_versions[DCE_HWIP][0]) {
10771         case IP_VERSION(3, 0, 1):
10772                 if (!adev->mman.keep_stolen_vga_memory)
10773                         return true;
10774                 break;
10775         default:
10776                 break;
10777         }
10778
10779         return false;
10780 }