drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 /* The caprices of the preprocessor require that this be declared right here */
  27 #define CREATE_TRACE_POINTS
  28
  29 #include "dm_services_types.h"
  30 #include "dc.h"
  31 #include "link_enc_cfg.h"
  32 #include "dc/inc/core_types.h"
  33 #include "dal_asic_id.h"
  34 #include "dmub/dmub_srv.h"
  35 #include "dc/inc/hw/dmcu.h"
  36 #include "dc/inc/hw/abm.h"
  37 #include "dc/dc_dmub_srv.h"
  38 #include "dc/dc_edid_parser.h"
  39 #include "dc/dc_stat.h"
  40 #include "amdgpu_dm_trace.h"
  41 #include "dpcd_defs.h"
  42 #include "link/protocols/link_dpcd.h"
  43 #include "link_service_types.h"
  44 #include "link/protocols/link_dp_capability.h"
  45 #include "link/protocols/link_ddc.h"
  46
  47 #include "vid.h"
  48 #include "amdgpu.h"
  49 #include "amdgpu_display.h"
  50 #include "amdgpu_ucode.h"
  51 #include "atom.h"
  52 #include "amdgpu_dm.h"
  53 #include "amdgpu_dm_plane.h"
  54 #include "amdgpu_dm_crtc.h"
  55 #include "amdgpu_dm_hdcp.h"
  56 #include <drm/display/drm_hdcp_helper.h>
  57 #include "amdgpu_pm.h"
  58 #include "amdgpu_atombios.h"
  59
  60 #include "amd_shared.h"
  61 #include "amdgpu_dm_irq.h"
  62 #include "dm_helpers.h"
  63 #include "amdgpu_dm_mst_types.h"
  64 #if defined(CONFIG_DEBUG_FS)
  65 #include "amdgpu_dm_debugfs.h"
  66 #endif
  67 #include "amdgpu_dm_psr.h"
  68 #include "amdgpu_dm_replay.h"
  69
  70 #include "ivsrcid/ivsrcid_vislands30.h"
  71
  72 #include <linux/backlight.h>
  73 #include <linux/module.h>
  74 #include <linux/moduleparam.h>
  75 #include <linux/types.h>
  76 #include <linux/pm_runtime.h>
  77 #include <linux/pci.h>
  78 #include <linux/firmware.h>
  79 #include <linux/component.h>
  80 #include <linux/dmi.h>
  81
  82 #include <drm/display/drm_dp_mst_helper.h>
  83 #include <drm/display/drm_hdmi_helper.h>
  84 #include <drm/drm_atomic.h>
  85 #include <drm/drm_atomic_uapi.h>
  86 #include <drm/drm_atomic_helper.h>
  87 #include <drm/drm_blend.h>
  88 #include <drm/drm_fourcc.h>
  89 #include <drm/drm_edid.h>
  90 #include <drm/drm_vblank.h>
  91 #include <drm/drm_audio_component.h>
  92 #include <drm/drm_gem_atomic_helper.h>
  93 #include <drm/drm_plane_helper.h>
  94
  95 #include <acpi/video.h>
  96
  97 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
  98
  99 #include "dcn/dcn_1_0_offset.h"
 100 #include "dcn/dcn_1_0_sh_mask.h"
 101 #include "soc15_hw_ip.h"
 102 #include "soc15_common.h"
 103 #include "vega10_ip_offset.h"
 104
 105 #include "gc/gc_11_0_0_offset.h"
 106 #include "gc/gc_11_0_0_sh_mask.h"
 107
 108 #include "modules/inc/mod_freesync.h"
 109 #include "modules/power/power_helpers.h"
 110
 111 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
 112 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
 113 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"
 114 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
 115 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
 116 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
 117 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
 118 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
 119 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
 120 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
 121 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"
 122 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
 123 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin"
 124 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);
 125 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin"
 126 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);
 127 #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin"
 128 MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB);
 129 #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin"
 130 MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB);
 131 #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin"
 132 MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB);
 133
 134 #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin"
 135 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB);
 136 #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin"
 137 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB);
 138
 139 #define FIRMWARE_RAVEN_DMCU             "amdgpu/raven_dmcu.bin"
 140 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
 141
 142 #define FIRMWARE_NAVI12_DMCU            "amdgpu/navi12_dmcu.bin"
 143 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);
 144
 145 /* Number of bytes in PSP header for firmware. */
 146 #define PSP_HEADER_BYTES 0x100
 147
 148 /* Number of bytes in PSP footer for firmware. */
 149 #define PSP_FOOTER_BYTES 0x100
 150
 151 /**
 152  * DOC: overview
 153  *
 154  * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
 155  * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM
 156  * requests into DC requests, and DC responses into DRM responses.
 157  *
 158  * The root control structure is &struct amdgpu_display_manager.
 159  */
 160
 161 /* basic init/fini API */
 162 static int amdgpu_dm_init(struct amdgpu_device *adev);
 163 static void amdgpu_dm_fini(struct amdgpu_device *adev);
 164 static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector);
 165
 166 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)
 167 {
 168         switch (link->dpcd_caps.dongle_type) {
 169         case DISPLAY_DONGLE_NONE:
 170                 return DRM_MODE_SUBCONNECTOR_Native;
 171         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
 172                 return DRM_MODE_SUBCONNECTOR_VGA;
 173         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
 174         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 175                 return DRM_MODE_SUBCONNECTOR_DVID;
 176         case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
 177         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 178                 return DRM_MODE_SUBCONNECTOR_HDMIA;
 179         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 180         default:
 181                 return DRM_MODE_SUBCONNECTOR_Unknown;
 182         }
 183 }
 184
 185 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector)
 186 {
 187         struct dc_link *link = aconnector->dc_link;
 188         struct drm_connector *connector = &aconnector->base;
 189         enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
 190
 191         if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
 192                 return;
 193
 194         if (aconnector->dc_sink)
 195                 subconnector = get_subconnector_type(link);
 196
 197         drm_object_property_set_value(&connector->base,
 198                         connector->dev->mode_config.dp_subconnector_property,
 199                         subconnector);
 200 }
 201
 202 /*
 203  * initializes drm_device display related structures, based on the information
 204  * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
 205  * drm_encoder, drm_mode_config
 206  *
 207  * Returns 0 on success
 208  */
 209 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
 210 /* removes and deallocates the drm structures, created by the above function */
 211 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
 212
 213 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
 214                                     struct amdgpu_dm_connector *amdgpu_dm_connector,
 215                                     u32 link_index,
 216                                     struct amdgpu_encoder *amdgpu_encoder);
 217 static int amdgpu_dm_encoder_init(struct drm_device *dev,
 218                                   struct amdgpu_encoder *aencoder,
 219                                   uint32_t link_index);
 220
 221 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
 222
 223 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
 224
 225 static int amdgpu_dm_atomic_check(struct drm_device *dev,
 226                                   struct drm_atomic_state *state);
 227
 228 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector);
 229 static void handle_hpd_rx_irq(void *param);
 230
 231 static bool
 232 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
 233                                  struct drm_crtc_state *new_crtc_state);
 234 /*
 235  * dm_vblank_get_counter
 236  *
 237  * @brief
 238  * Get counter for number of vertical blanks
 239  *
 240  * @param
 241  * struct amdgpu_device *adev - [in] desired amdgpu device
 242  * int disp_idx - [in] which CRTC to get the counter from
 243  *
 244  * @return
 245  * Counter for vertical blanks
 246  */
 247 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 248 {
 249         struct amdgpu_crtc *acrtc = NULL;
 250
 251         if (crtc >= adev->mode_info.num_crtc)
 252                 return 0;
 253
 254         acrtc = adev->mode_info.crtcs[crtc];
 255
 256         if (!acrtc->dm_irq_params.stream) {
 257                 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 258                           crtc);
 259                 return 0;
 260         }
 261
 262         return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);
 263 }
 264
 265 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 266                                   u32 *vbl, u32 *position)
 267 {
 268         u32 v_blank_start, v_blank_end, h_position, v_position;
 269         struct amdgpu_crtc *acrtc = NULL;
 270
 271         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 272                 return -EINVAL;
 273
 274         acrtc = adev->mode_info.crtcs[crtc];
 275
 276         if (!acrtc->dm_irq_params.stream) {
 277                 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 278                           crtc);
 279                 return 0;
 280         }
 281
 282         /*
 283          * TODO rework base driver to use values directly.
 284          * for now parse it back into reg-format
 285          */
 286         dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream,
 287                                  &v_blank_start,
 288                                  &v_blank_end,
 289                                  &h_position,
 290                                  &v_position);
 291
 292         *position = v_position | (h_position << 16);
 293         *vbl = v_blank_start | (v_blank_end << 16);
 294
 295         return 0;
 296 }
 297
 298 static bool dm_is_idle(void *handle)
 299 {
 300         /* XXX todo */
 301         return true;
 302 }
 303
 304 static int dm_wait_for_idle(void *handle)
 305 {
 306         /* XXX todo */
 307         return 0;
 308 }
 309
 310 static bool dm_check_soft_reset(void *handle)
 311 {
 312         return false;
 313 }
 314
 315 static int dm_soft_reset(void *handle)
 316 {
 317         /* XXX todo */
 318         return 0;
 319 }
 320
 321 static struct amdgpu_crtc *
 322 get_crtc_by_otg_inst(struct amdgpu_device *adev,
 323                      int otg_inst)
 324 {
 325         struct drm_device *dev = adev_to_drm(adev);
 326         struct drm_crtc *crtc;
 327         struct amdgpu_crtc *amdgpu_crtc;
 328
 329         if (WARN_ON(otg_inst == -1))
 330                 return adev->mode_info.crtcs[0];
 331
 332         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 333                 amdgpu_crtc = to_amdgpu_crtc(crtc);
 334
 335                 if (amdgpu_crtc->otg_inst == otg_inst)
 336                         return amdgpu_crtc;
 337         }
 338
 339         return NULL;
 340 }
 341
 342 static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,
 343                                               struct dm_crtc_state *new_state)
 344 {
 345         if (new_state->freesync_config.state ==  VRR_STATE_ACTIVE_FIXED)
 346                 return true;
 347         else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state))
 348                 return true;
 349         else
 350                 return false;
 351 }
 352
 353 static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update,
 354                                         int planes_count)
 355 {
 356         int i, j;
 357
 358         for (i = 0, j = planes_count - 1; i < j; i++, j--)
 359                 swap(array_of_surface_update[i], array_of_surface_update[j]);
 360 }
 361
 362 /**
 363  * update_planes_and_stream_adapter() - Send planes to be updated in DC
 364  *
 365  * DC has a generic way to update planes and stream via
 366  * dc_update_planes_and_stream function; however, DM might need some
 367  * adjustments and preparation before calling it. This function is a wrapper
 368  * for the dc_update_planes_and_stream that does any required configuration
 369  * before passing control to DC.
 370  *
 371  * @dc: Display Core control structure
 372  * @update_type: specify whether it is FULL/MEDIUM/FAST update
 373  * @planes_count: planes count to update
 374  * @stream: stream state
 375  * @stream_update: stream update
 376  * @array_of_surface_update: dc surface update pointer
 377  *
 378  */
 379 static inline bool update_planes_and_stream_adapter(struct dc *dc,
 380                                                     int update_type,
 381                                                     int planes_count,
 382                                                     struct dc_stream_state *stream,
 383                                                     struct dc_stream_update *stream_update,
 384                                                     struct dc_surface_update *array_of_surface_update)
 385 {
 386         reverse_planes_order(array_of_surface_update, planes_count);
 387
 388         /*
 389          * Previous frame finished and HW is ready for optimization.
 390          */
 391         if (update_type == UPDATE_TYPE_FAST)
 392                 dc_post_update_surfaces_to_stream(dc);
 393
 394         return dc_update_planes_and_stream(dc,
 395                                            array_of_surface_update,
 396                                            planes_count,
 397                                            stream,
 398                                            stream_update);
 399 }
 400
 401 /**
 402  * dm_pflip_high_irq() - Handle pageflip interrupt
 403  * @interrupt_params: ignored
 404  *
 405  * Handles the pageflip interrupt by notifying all interested parties
 406  * that the pageflip has been completed.
 407  */
 408 static void dm_pflip_high_irq(void *interrupt_params)
 409 {
 410         struct amdgpu_crtc *amdgpu_crtc;
 411         struct common_irq_params *irq_params = interrupt_params;
 412         struct amdgpu_device *adev = irq_params->adev;
 413         unsigned long flags;
 414         struct drm_pending_vblank_event *e;
 415         u32 vpos, hpos, v_blank_start, v_blank_end;
 416         bool vrr_active;
 417
 418         amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
 419
 420         /* IRQ could occur when in initial stage */
 421         /* TODO work and BO cleanup */
 422         if (amdgpu_crtc == NULL) {
 423                 DC_LOG_PFLIP("CRTC is null, returning.\n");
 424                 return;
 425         }
 426
 427         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 428
 429         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
 430                 DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p]\n",
 431                              amdgpu_crtc->pflip_status,
 432                              AMDGPU_FLIP_SUBMITTED,
 433                              amdgpu_crtc->crtc_id,
 434                              amdgpu_crtc);
 435                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 436                 return;
 437         }
 438
 439         /* page flip completed. */
 440         e = amdgpu_crtc->event;
 441         amdgpu_crtc->event = NULL;
 442
 443         WARN_ON(!e);
 444
 445         vrr_active = amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc);
 446
 447         /* Fixed refresh rate, or VRR scanout position outside front-porch? */
 448         if (!vrr_active ||
 449             !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start,
 450                                       &v_blank_end, &hpos, &vpos) ||
 451             (vpos < v_blank_start)) {
 452                 /* Update to correct count and vblank timestamp if racing with
 453                  * vblank irq. This also updates to the correct vblank timestamp
 454                  * even in VRR mode, as scanout is past the front-porch atm.
 455                  */
 456                 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
 457
 458                 /* Wake up userspace by sending the pageflip event with proper
 459                  * count and timestamp of vblank of flip completion.
 460                  */
 461                 if (e) {
 462                         drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
 463
 464                         /* Event sent, so done with vblank for this flip */
 465                         drm_crtc_vblank_put(&amdgpu_crtc->base);
 466                 }
 467         } else if (e) {
 468                 /* VRR active and inside front-porch: vblank count and
 469                  * timestamp for pageflip event will only be up to date after
 470                  * drm_crtc_handle_vblank() has been executed from late vblank
 471                  * irq handler after start of back-porch (vline 0). We queue the
 472                  * pageflip event for send-out by drm_crtc_handle_vblank() with
 473                  * updated timestamp and count, once it runs after us.
 474                  *
 475                  * We need to open-code this instead of using the helper
 476                  * drm_crtc_arm_vblank_event(), as that helper would
 477                  * call drm_crtc_accurate_vblank_count(), which we must
 478                  * not call in VRR mode while we are in front-porch!
 479                  */
 480
 481                 /* sequence will be replaced by real count during send-out. */
 482                 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
 483                 e->pipe = amdgpu_crtc->crtc_id;
 484
 485                 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list);
 486                 e = NULL;
 487         }
 488
 489         /* Keep track of vblank of this flip for flip throttling. We use the
 490          * cooked hw counter, as that one incremented at start of this vblank
 491          * of pageflip completion, so last_flip_vblank is the forbidden count
 492          * for queueing new pageflips if vsync + VRR is enabled.
 493          */
 494         amdgpu_crtc->dm_irq_params.last_flip_vblank =
 495                 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base);
 496
 497         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
 498         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 499
 500         DC_LOG_PFLIP("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
 501                      amdgpu_crtc->crtc_id, amdgpu_crtc,
 502                      vrr_active, (int) !e);
 503 }
 504
 505 static void dm_vupdate_high_irq(void *interrupt_params)
 506 {
 507         struct common_irq_params *irq_params = interrupt_params;
 508         struct amdgpu_device *adev = irq_params->adev;
 509         struct amdgpu_crtc *acrtc;
 510         struct drm_device *drm_dev;
 511         struct drm_vblank_crtc *vblank;
 512         ktime_t frame_duration_ns, previous_timestamp;
 513         unsigned long flags;
 514         int vrr_active;
 515
 516         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
 517
 518         if (acrtc) {
 519                 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
 520                 drm_dev = acrtc->base.dev;
 521                 vblank = &drm_dev->vblank[acrtc->base.index];
 522                 previous_timestamp = atomic64_read(&irq_params->previous_timestamp);
 523                 frame_duration_ns = vblank->time - previous_timestamp;
 524
 525                 if (frame_duration_ns > 0) {
 526                         trace_amdgpu_refresh_rate_track(acrtc->base.index,
 527                                                 frame_duration_ns,
 528                                                 ktime_divns(NSEC_PER_SEC, frame_duration_ns));
 529                         atomic64_set(&irq_params->previous_timestamp, vblank->time);
 530                 }
 531
 532                 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d\n",
 533                               acrtc->crtc_id,
 534                               vrr_active);
 535
 536                 /* Core vblank handling is done here after end of front-porch in
 537                  * vrr mode, as vblank timestamping will give valid results
 538                  * while now done after front-porch. This will also deliver
 539                  * page-flip completion events that have been queued to us
 540                  * if a pageflip happened inside front-porch.
 541                  */
 542                 if (vrr_active) {
 543                         amdgpu_dm_crtc_handle_vblank(acrtc);
 544
 545                         /* BTR processing for pre-DCE12 ASICs */
 546                         if (acrtc->dm_irq_params.stream &&
 547                             adev->family < AMDGPU_FAMILY_AI) {
 548                                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 549                                 mod_freesync_handle_v_update(
 550                                     adev->dm.freesync_module,
 551                                     acrtc->dm_irq_params.stream,
 552                                     &acrtc->dm_irq_params.vrr_params);
 553
 554                                 dc_stream_adjust_vmin_vmax(
 555                                     adev->dm.dc,
 556                                     acrtc->dm_irq_params.stream,
 557                                     &acrtc->dm_irq_params.vrr_params.adjust);
 558                                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 559                         }
 560                 }
 561         }
 562 }
 563
 564 /**
 565  * dm_crtc_high_irq() - Handles CRTC interrupt
 566  * @interrupt_params: used for determining the CRTC instance
 567  *
 568  * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
 569  * event handler.
 570  */
 571 static void dm_crtc_high_irq(void *interrupt_params)
 572 {
 573         struct common_irq_params *irq_params = interrupt_params;
 574         struct amdgpu_device *adev = irq_params->adev;
 575         struct amdgpu_crtc *acrtc;
 576         unsigned long flags;
 577         int vrr_active;
 578
 579         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
 580         if (!acrtc)
 581                 return;
 582
 583         vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
 584
 585         DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,
 586                       vrr_active, acrtc->dm_irq_params.active_planes);
 587
 588         /**
 589          * Core vblank handling at start of front-porch is only possible
 590          * in non-vrr mode, as only there vblank timestamping will give
 591          * valid results while done in front-porch. Otherwise defer it
 592          * to dm_vupdate_high_irq after end of front-porch.
 593          */
 594         if (!vrr_active)
 595                 amdgpu_dm_crtc_handle_vblank(acrtc);
 596
 597         /**
 598          * Following stuff must happen at start of vblank, for crc
 599          * computation and below-the-range btr support in vrr mode.
 600          */
 601         amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
 602
 603         /* BTR updates need to happen before VUPDATE on Vega and above. */
 604         if (adev->family < AMDGPU_FAMILY_AI)
 605                 return;
 606
 607         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 608
 609         if (acrtc->dm_irq_params.stream &&
 610             acrtc->dm_irq_params.vrr_params.supported &&
 611             acrtc->dm_irq_params.freesync_config.state ==
 612                     VRR_STATE_ACTIVE_VARIABLE) {
 613                 mod_freesync_handle_v_update(adev->dm.freesync_module,
 614                                              acrtc->dm_irq_params.stream,
 615                                              &acrtc->dm_irq_params.vrr_params);
 616
 617                 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,
 618                                            &acrtc->dm_irq_params.vrr_params.adjust);
 619         }
 620
 621         /*
 622          * If there aren't any active_planes then DCH HUBP may be clock-gated.
 623          * In that case, pageflip completion interrupts won't fire and pageflip
 624          * completion events won't get delivered. Prevent this by sending
 625          * pending pageflip events from here if a flip is still pending.
 626          *
 627          * If any planes are enabled, use dm_pflip_high_irq() instead, to
 628          * avoid race conditions between flip programming and completion,
 629          * which could cause too early flip completion events.
 630          */
 631         if (adev->family >= AMDGPU_FAMILY_RV &&
 632             acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
 633             acrtc->dm_irq_params.active_planes == 0) {
 634                 if (acrtc->event) {
 635                         drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
 636                         acrtc->event = NULL;
 637                         drm_crtc_vblank_put(&acrtc->base);
 638                 }
 639                 acrtc->pflip_status = AMDGPU_FLIP_NONE;
 640         }
 641
 642         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 643 }
 644
 645 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
 646 /**
 647  * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for
 648  * DCN generation ASICs
 649  * @interrupt_params: interrupt parameters
 650  *
 651  * Used to set crc window/read out crc value at vertical line 0 position
 652  */
 653 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)
 654 {
 655         struct common_irq_params *irq_params = interrupt_params;
 656         struct amdgpu_device *adev = irq_params->adev;
 657         struct amdgpu_crtc *acrtc;
 658
 659         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0);
 660
 661         if (!acrtc)
 662                 return;
 663
 664         amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base);
 665 }
 666 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */
 667
 668 /**
 669  * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command.
 670  * @adev: amdgpu_device pointer
 671  * @notify: dmub notification structure
 672  *
 673  * Dmub AUX or SET_CONFIG command completion processing callback
 674  * Copies dmub notification to DM which is to be read by AUX command.
 675  * issuing thread and also signals the event to wake up the thread.
 676  */
 677 static void dmub_aux_setconfig_callback(struct amdgpu_device *adev,
 678                                         struct dmub_notification *notify)
 679 {
 680         if (adev->dm.dmub_notify)
 681                 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification));
 682         if (notify->type == DMUB_NOTIFICATION_AUX_REPLY)
 683                 complete(&adev->dm.dmub_aux_transfer_done);
 684 }
 685
 686 /**
 687  * dmub_hpd_callback - DMUB HPD interrupt processing callback.
 688  * @adev: amdgpu_device pointer
 689  * @notify: dmub notification structure
 690  *
 691  * Dmub Hpd interrupt processing callback. Gets displayindex through the
 692  * ink index and calls helper to do the processing.
 693  */
 694 static void dmub_hpd_callback(struct amdgpu_device *adev,
 695                               struct dmub_notification *notify)
 696 {
 697         struct amdgpu_dm_connector *aconnector;
 698         struct amdgpu_dm_connector *hpd_aconnector = NULL;
 699         struct drm_connector *connector;
 700         struct drm_connector_list_iter iter;
 701         struct dc_link *link;
 702         u8 link_index = 0;
 703         struct drm_device *dev;
 704
 705         if (adev == NULL)
 706                 return;
 707
 708         if (notify == NULL) {
 709                 DRM_ERROR("DMUB HPD callback notification was NULL");
 710                 return;
 711         }
 712
 713         if (notify->link_index > adev->dm.dc->link_count) {
 714                 DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index);
 715                 return;
 716         }
 717
 718         link_index = notify->link_index;
 719         link = adev->dm.dc->links[link_index];
 720         dev = adev->dm.ddev;
 721
 722         drm_connector_list_iter_begin(dev, &iter);
 723         drm_for_each_connector_iter(connector, &iter) {
 724                 aconnector = to_amdgpu_dm_connector(connector);
 725                 if (link && aconnector->dc_link == link) {
 726                         if (notify->type == DMUB_NOTIFICATION_HPD)
 727                                 DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index);
 728                         else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
 729                                 DRM_INFO("DMUB HPD IRQ callback: link_index=%u\n", link_index);
 730                         else
 731                                 DRM_WARN("DMUB Unknown HPD callback type %d, link_index=%u\n",
 732                                                 notify->type, link_index);
 733
 734                         hpd_aconnector = aconnector;
 735                         break;
 736                 }
 737         }
 738         drm_connector_list_iter_end(&iter);
 739
 740         if (hpd_aconnector) {
 741                 if (notify->type == DMUB_NOTIFICATION_HPD)
 742                         handle_hpd_irq_helper(hpd_aconnector);
 743                 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
 744                         handle_hpd_rx_irq(hpd_aconnector);
 745         }
 746 }
 747
 748 /**
 749  * register_dmub_notify_callback - Sets callback for DMUB notify
 750  * @adev: amdgpu_device pointer
 751  * @type: Type of dmub notification
 752  * @callback: Dmub interrupt callback function
 753  * @dmub_int_thread_offload: offload indicator
 754  *
 755  * API to register a dmub callback handler for a dmub notification
 756  * Also sets indicator whether callback processing to be offloaded.
 757  * to dmub interrupt handling thread
 758  * Return: true if successfully registered, false if there is existing registration
 759  */
 760 static bool register_dmub_notify_callback(struct amdgpu_device *adev,
 761                                           enum dmub_notification_type type,
 762                                           dmub_notify_interrupt_callback_t callback,
 763                                           bool dmub_int_thread_offload)
 764 {
 765         if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) {
 766                 adev->dm.dmub_callback[type] = callback;
 767                 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload;
 768         } else
 769                 return false;
 770
 771         return true;
 772 }
 773
 774 static void dm_handle_hpd_work(struct work_struct *work)
 775 {
 776         struct dmub_hpd_work *dmub_hpd_wrk;
 777
 778         dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work);
 779
 780         if (!dmub_hpd_wrk->dmub_notify) {
 781                 DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL");
 782                 return;
 783         }
 784
 785         if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) {
 786                 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev,
 787                 dmub_hpd_wrk->dmub_notify);
 788         }
 789
 790         kfree(dmub_hpd_wrk->dmub_notify);
 791         kfree(dmub_hpd_wrk);
 792
 793 }
 794
 795 #define DMUB_TRACE_MAX_READ 64
 796 /**
 797  * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt
 798  * @interrupt_params: used for determining the Outbox instance
 799  *
 800  * Handles the Outbox Interrupt
 801  * event handler.
 802  */
 803 static void dm_dmub_outbox1_low_irq(void *interrupt_params)
 804 {
 805         struct dmub_notification notify;
 806         struct common_irq_params *irq_params = interrupt_params;
 807         struct amdgpu_device *adev = irq_params->adev;
 808         struct amdgpu_display_manager *dm = &adev->dm;
 809         struct dmcub_trace_buf_entry entry = { 0 };
 810         u32 count = 0;
 811         struct dmub_hpd_work *dmub_hpd_wrk;
 812         struct dc_link *plink = NULL;
 813
 814         if (dc_enable_dmub_notifications(adev->dm.dc) &&
 815                 irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) {
 816
 817                 do {
 818                         dc_stat_get_dmub_notification(adev->dm.dc, &notify);
 819                         if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) {
 820                                 DRM_ERROR("DM: notify type %d invalid!", notify.type);
 821                                 continue;
 822                         }
 823                         if (!dm->dmub_callback[notify.type]) {
 824                                 DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type);
 825                                 continue;
 826                         }
 827                         if (dm->dmub_thread_offload[notify.type] == true) {
 828                                 dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC);
 829                                 if (!dmub_hpd_wrk) {
 830                                         DRM_ERROR("Failed to allocate dmub_hpd_wrk");
 831                                         return;
 832                                 }
 833                                 dmub_hpd_wrk->dmub_notify = kmemdup(&notify, sizeof(struct dmub_notification),
 834                                                                     GFP_ATOMIC);
 835                                 if (!dmub_hpd_wrk->dmub_notify) {
 836                                         kfree(dmub_hpd_wrk);
 837                                         DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify");
 838                                         return;
 839                                 }
 840                                 INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work);
 841                                 dmub_hpd_wrk->adev = adev;
 842                                 if (notify.type == DMUB_NOTIFICATION_HPD) {
 843                                         plink = adev->dm.dc->links[notify.link_index];
 844                                         if (plink) {
 845                                                 plink->hpd_status =
 846                                                         notify.hpd_status == DP_HPD_PLUG;
 847                                         }
 848                                 }
 849                                 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work);
 850                         } else {
 851                                 dm->dmub_callback[notify.type](adev, &notify);
 852                         }
 853                 } while (notify.pending_notification);
 854         }
 855
 856
 857         do {
 858                 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {
 859                         trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,
 860                                                         entry.param0, entry.param1);
 861
 862                         DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",
 863                                  entry.trace_code, entry.tick_count, entry.param0, entry.param1);
 864                 } else
 865                         break;
 866
 867                 count++;
 868
 869         } while (count <= DMUB_TRACE_MAX_READ);
 870
 871         if (count > DMUB_TRACE_MAX_READ)
 872                 DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ");
 873 }
 874
 875 static int dm_set_clockgating_state(void *handle,
 876                   enum amd_clockgating_state state)
 877 {
 878         return 0;
 879 }
 880
 881 static int dm_set_powergating_state(void *handle,
 882                   enum amd_powergating_state state)
 883 {
 884         return 0;
 885 }
 886
 887 /* Prototypes of private functions */
 888 static int dm_early_init(void *handle);
 889
 890 /* Allocate memory for FBC compressed data  */
 891 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
 892 {
 893         struct drm_device *dev = connector->dev;
 894         struct amdgpu_device *adev = drm_to_adev(dev);
 895         struct dm_compressor_info *compressor = &adev->dm.compressor;
 896         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
 897         struct drm_display_mode *mode;
 898         unsigned long max_size = 0;
 899
 900         if (adev->dm.dc->fbc_compressor == NULL)
 901                 return;
 902
 903         if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
 904                 return;
 905
 906         if (compressor->bo_ptr)
 907                 return;
 908
 909
 910         list_for_each_entry(mode, &connector->modes, head) {
 911                 if (max_size < mode->htotal * mode->vtotal)
 912                         max_size = mode->htotal * mode->vtotal;
 913         }
 914
 915         if (max_size) {
 916                 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
 917                             AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
 918                             &compressor->gpu_addr, &compressor->cpu_addr);
 919
 920                 if (r)
 921                         DRM_ERROR("DM: Failed to initialize FBC\n");
 922                 else {
 923                         adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
 924                         DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
 925                 }
 926
 927         }
 928
 929 }
 930
 931 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
 932                                           int pipe, bool *enabled,
 933                                           unsigned char *buf, int max_bytes)
 934 {
 935         struct drm_device *dev = dev_get_drvdata(kdev);
 936         struct amdgpu_device *adev = drm_to_adev(dev);
 937         struct drm_connector *connector;
 938         struct drm_connector_list_iter conn_iter;
 939         struct amdgpu_dm_connector *aconnector;
 940         int ret = 0;
 941
 942         *enabled = false;
 943
 944         mutex_lock(&adev->dm.audio_lock);
 945
 946         drm_connector_list_iter_begin(dev, &conn_iter);
 947         drm_for_each_connector_iter(connector, &conn_iter) {
 948                 aconnector = to_amdgpu_dm_connector(connector);
 949                 if (aconnector->audio_inst != port)
 950                         continue;
 951
 952                 *enabled = true;
 953                 ret = drm_eld_size(connector->eld);
 954                 memcpy(buf, connector->eld, min(max_bytes, ret));
 955
 956                 break;
 957         }
 958         drm_connector_list_iter_end(&conn_iter);
 959
 960         mutex_unlock(&adev->dm.audio_lock);
 961
 962         DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
 963
 964         return ret;
 965 }
 966
 967 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
 968         .get_eld = amdgpu_dm_audio_component_get_eld,
 969 };
 970
 971 static int amdgpu_dm_audio_component_bind(struct device *kdev,
 972                                        struct device *hda_kdev, void *data)
 973 {
 974         struct drm_device *dev = dev_get_drvdata(kdev);
 975         struct amdgpu_device *adev = drm_to_adev(dev);
 976         struct drm_audio_component *acomp = data;
 977
 978         acomp->ops = &amdgpu_dm_audio_component_ops;
 979         acomp->dev = kdev;
 980         adev->dm.audio_component = acomp;
 981
 982         return 0;
 983 }
 984
 985 static void amdgpu_dm_audio_component_unbind(struct device *kdev,
 986                                           struct device *hda_kdev, void *data)
 987 {
 988         struct drm_device *dev = dev_get_drvdata(kdev);
 989         struct amdgpu_device *adev = drm_to_adev(dev);
 990         struct drm_audio_component *acomp = data;
 991
 992         acomp->ops = NULL;
 993         acomp->dev = NULL;
 994         adev->dm.audio_component = NULL;
 995 }
 996
 997 static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
 998         .bind   = amdgpu_dm_audio_component_bind,
 999         .unbind = amdgpu_dm_audio_component_unbind,
1000 };
1001
1002 static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
1003 {
1004         int i, ret;
1005
1006         if (!amdgpu_audio)
1007                 return 0;
1008
1009         adev->mode_info.audio.enabled = true;
1010
1011         adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
1012
1013         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1014                 adev->mode_info.audio.pin[i].channels = -1;
1015                 adev->mode_info.audio.pin[i].rate = -1;
1016                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1017                 adev->mode_info.audio.pin[i].status_bits = 0;
1018                 adev->mode_info.audio.pin[i].category_code = 0;
1019                 adev->mode_info.audio.pin[i].connected = false;
1020                 adev->mode_info.audio.pin[i].id =
1021                         adev->dm.dc->res_pool->audios[i]->inst;
1022                 adev->mode_info.audio.pin[i].offset = 0;
1023         }
1024
1025         ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1026         if (ret < 0)
1027                 return ret;
1028
1029         adev->dm.audio_registered = true;
1030
1031         return 0;
1032 }
1033
1034 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
1035 {
1036         if (!amdgpu_audio)
1037                 return;
1038
1039         if (!adev->mode_info.audio.enabled)
1040                 return;
1041
1042         if (adev->dm.audio_registered) {
1043                 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1044                 adev->dm.audio_registered = false;
1045         }
1046
1047         /* TODO: Disable audio? */
1048
1049         adev->mode_info.audio.enabled = false;
1050 }
1051
1052 static  void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
1053 {
1054         struct drm_audio_component *acomp = adev->dm.audio_component;
1055
1056         if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
1057                 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
1058
1059                 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
1060                                                  pin, -1);
1061         }
1062 }
1063
1064 static int dm_dmub_hw_init(struct amdgpu_device *adev)
1065 {
1066         const struct dmcub_firmware_header_v1_0 *hdr;
1067         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1068         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
1069         const struct firmware *dmub_fw = adev->dm.dmub_fw;
1070         struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
1071         struct abm *abm = adev->dm.dc->res_pool->abm;
1072         struct dmub_srv_hw_params hw_params;
1073         enum dmub_status status;
1074         const unsigned char *fw_inst_const, *fw_bss_data;
1075         u32 i, fw_inst_const_size, fw_bss_data_size;
1076         bool has_hw_support;
1077
1078         if (!dmub_srv)
1079                 /* DMUB isn't supported on the ASIC. */
1080                 return 0;
1081
1082         if (!fb_info) {
1083                 DRM_ERROR("No framebuffer info for DMUB service.\n");
1084                 return -EINVAL;
1085         }
1086
1087         if (!dmub_fw) {
1088                 /* Firmware required for DMUB support. */
1089                 DRM_ERROR("No firmware provided for DMUB.\n");
1090                 return -EINVAL;
1091         }
1092
1093         status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
1094         if (status != DMUB_STATUS_OK) {
1095                 DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
1096                 return -EINVAL;
1097         }
1098
1099         if (!has_hw_support) {
1100                 DRM_INFO("DMUB unsupported on ASIC\n");
1101                 return 0;
1102         }
1103
1104         /* Reset DMCUB if it was previously running - before we overwrite its memory. */
1105         status = dmub_srv_hw_reset(dmub_srv);
1106         if (status != DMUB_STATUS_OK)
1107                 DRM_WARN("Error resetting DMUB HW: %d\n", status);
1108
1109         hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
1110
1111         fw_inst_const = dmub_fw->data +
1112                         le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1113                         PSP_HEADER_BYTES;
1114
1115         fw_bss_data = dmub_fw->data +
1116                       le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1117                       le32_to_cpu(hdr->inst_const_bytes);
1118
1119         /* Copy firmware and bios info into FB memory. */
1120         fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
1121                              PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
1122
1123         fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
1124
1125         /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP,
1126          * amdgpu_ucode_init_single_fw will load dmub firmware
1127          * fw_inst_const part to cw0; otherwise, the firmware back door load
1128          * will be done by dm_dmub_hw_init
1129          */
1130         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1131                 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
1132                                 fw_inst_const_size);
1133         }
1134
1135         if (fw_bss_data_size)
1136                 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr,
1137                        fw_bss_data, fw_bss_data_size);
1138
1139         /* Copy firmware bios info into FB memory. */
1140         memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,
1141                adev->bios_size);
1142
1143         /* Reset regions that need to be reset. */
1144         memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,
1145         fb_info->fb[DMUB_WINDOW_4_MAILBOX].size);
1146
1147         memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,
1148                fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size);
1149
1150         memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,
1151                fb_info->fb[DMUB_WINDOW_6_FW_STATE].size);
1152
1153         /* Initialize hardware. */
1154         memset(&hw_params, 0, sizeof(hw_params));
1155         hw_params.fb_base = adev->gmc.fb_start;
1156         hw_params.fb_offset = adev->vm_manager.vram_base_offset;
1157
1158         /* backdoor load firmware and trigger dmub running */
1159         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
1160                 hw_params.load_inst_const = true;
1161
1162         if (dmcu)
1163                 hw_params.psp_version = dmcu->psp_version;
1164
1165         for (i = 0; i < fb_info->num_fb; ++i)
1166                 hw_params.fb[i] = &fb_info->fb[i];
1167
1168         switch (adev->ip_versions[DCE_HWIP][0]) {
1169         case IP_VERSION(3, 1, 3):
1170         case IP_VERSION(3, 1, 4):
1171                 hw_params.dpia_supported = true;
1172                 hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia;
1173                 break;
1174         default:
1175                 break;
1176         }
1177
1178         status = dmub_srv_hw_init(dmub_srv, &hw_params);
1179         if (status != DMUB_STATUS_OK) {
1180                 DRM_ERROR("Error initializing DMUB HW: %d\n", status);
1181                 return -EINVAL;
1182         }
1183
1184         /* Wait for firmware load to finish. */
1185         status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1186         if (status != DMUB_STATUS_OK)
1187                 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1188
1189         /* Init DMCU and ABM if available. */
1190         if (dmcu && abm) {
1191                 dmcu->funcs->dmcu_init(dmcu);
1192                 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
1193         }
1194
1195         if (!adev->dm.dc->ctx->dmub_srv)
1196                 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
1197         if (!adev->dm.dc->ctx->dmub_srv) {
1198                 DRM_ERROR("Couldn't allocate DC DMUB server!\n");
1199                 return -ENOMEM;
1200         }
1201
1202         DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
1203                  adev->dm.dmcub_fw_version);
1204
1205         return 0;
1206 }
1207
1208 static void dm_dmub_hw_resume(struct amdgpu_device *adev)
1209 {
1210         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1211         enum dmub_status status;
1212         bool init;
1213
1214         if (!dmub_srv) {
1215                 /* DMUB isn't supported on the ASIC. */
1216                 return;
1217         }
1218
1219         status = dmub_srv_is_hw_init(dmub_srv, &init);
1220         if (status != DMUB_STATUS_OK)
1221                 DRM_WARN("DMUB hardware init check failed: %d\n", status);
1222
1223         if (status == DMUB_STATUS_OK && init) {
1224                 /* Wait for firmware load to finish. */
1225                 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1226                 if (status != DMUB_STATUS_OK)
1227                         DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1228         } else {
1229                 /* Perform the full hardware initialization. */
1230                 dm_dmub_hw_init(adev);
1231         }
1232 }
1233
1234 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
1235 {
1236         u64 pt_base;
1237         u32 logical_addr_low;
1238         u32 logical_addr_high;
1239         u32 agp_base, agp_bot, agp_top;
1240         PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;
1241
1242         memset(pa_config, 0, sizeof(*pa_config));
1243
1244         agp_base = 0;
1245         agp_bot = adev->gmc.agp_start >> 24;
1246         agp_top = adev->gmc.agp_end >> 24;
1247
1248         /* AGP aperture is disabled */
1249         if (agp_bot == agp_top) {
1250                 logical_addr_low = adev->gmc.fb_start >> 18;
1251                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1252                         /*
1253                          * Raven2 has a HW issue that it is unable to use the vram which
1254                          * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1255                          * workaround that increase system aperture high address (add 1)
1256                          * to get rid of the VM fault and hardware hang.
1257                          */
1258                         logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1;
1259                 else
1260                         logical_addr_high = adev->gmc.fb_end >> 18;
1261         } else {
1262                 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
1263                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1264                         /*
1265                          * Raven2 has a HW issue that it is unable to use the vram which
1266                          * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1267                          * workaround that increase system aperture high address (add 1)
1268                          * to get rid of the VM fault and hardware hang.
1269                          */
1270                         logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
1271                 else
1272                         logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
1273         }
1274
1275         pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
1276
1277         page_table_start.high_part = upper_32_bits(adev->gmc.gart_start >>
1278                                                    AMDGPU_GPU_PAGE_SHIFT);
1279         page_table_start.low_part = lower_32_bits(adev->gmc.gart_start >>
1280                                                   AMDGPU_GPU_PAGE_SHIFT);
1281         page_table_end.high_part = upper_32_bits(adev->gmc.gart_end >>
1282                                                  AMDGPU_GPU_PAGE_SHIFT);
1283         page_table_end.low_part = lower_32_bits(adev->gmc.gart_end >>
1284                                                 AMDGPU_GPU_PAGE_SHIFT);
1285         page_table_base.high_part = upper_32_bits(pt_base);
1286         page_table_base.low_part = lower_32_bits(pt_base);
1287
1288         pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
1289         pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18;
1290
1291         pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24;
1292         pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24;
1293         pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24;
1294
1295         pa_config->system_aperture.fb_base = adev->gmc.fb_start;
1296         pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset;
1297         pa_config->system_aperture.fb_top = adev->gmc.fb_end;
1298
1299         pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12;
1300         pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12;
1301         pa_config->gart_config.page_table_base_addr = page_table_base.quad_part;
1302
1303         pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support;
1304
1305 }
1306
1307 static void force_connector_state(
1308         struct amdgpu_dm_connector *aconnector,
1309         enum drm_connector_force force_state)
1310 {
1311         struct drm_connector *connector = &aconnector->base;
1312
1313         mutex_lock(&connector->dev->mode_config.mutex);
1314         aconnector->base.force = force_state;
1315         mutex_unlock(&connector->dev->mode_config.mutex);
1316
1317         mutex_lock(&aconnector->hpd_lock);
1318         drm_kms_helper_connector_hotplug_event(connector);
1319         mutex_unlock(&aconnector->hpd_lock);
1320 }
1321
1322 static void dm_handle_hpd_rx_offload_work(struct work_struct *work)
1323 {
1324         struct hpd_rx_irq_offload_work *offload_work;
1325         struct amdgpu_dm_connector *aconnector;
1326         struct dc_link *dc_link;
1327         struct amdgpu_device *adev;
1328         enum dc_connection_type new_connection_type = dc_connection_none;
1329         unsigned long flags;
1330         union test_response test_response;
1331
1332         memset(&test_response, 0, sizeof(test_response));
1333
1334         offload_work = container_of(work, struct hpd_rx_irq_offload_work, work);
1335         aconnector = offload_work->offload_wq->aconnector;
1336
1337         if (!aconnector) {
1338                 DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work");
1339                 goto skip;
1340         }
1341
1342         adev = drm_to_adev(aconnector->base.dev);
1343         dc_link = aconnector->dc_link;
1344
1345         mutex_lock(&aconnector->hpd_lock);
1346         if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
1347                 DRM_ERROR("KMS: Failed to detect connector\n");
1348         mutex_unlock(&aconnector->hpd_lock);
1349
1350         if (new_connection_type == dc_connection_none)
1351                 goto skip;
1352
1353         if (amdgpu_in_reset(adev))
1354                 goto skip;
1355
1356         if (offload_work->data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
1357                 offload_work->data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
1358                 dm_handle_mst_sideband_msg_ready_event(&aconnector->mst_mgr, DOWN_OR_UP_MSG_RDY_EVENT);
1359                 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1360                 offload_work->offload_wq->is_handling_mst_msg_rdy_event = false;
1361                 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1362                 goto skip;
1363         }
1364
1365         mutex_lock(&adev->dm.dc_lock);
1366         if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
1367                 dc_link_dp_handle_automated_test(dc_link);
1368
1369                 if (aconnector->timing_changed) {
1370                         /* force connector disconnect and reconnect */
1371                         force_connector_state(aconnector, DRM_FORCE_OFF);
1372                         msleep(100);
1373                         force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED);
1374                 }
1375
1376                 test_response.bits.ACK = 1;
1377
1378                 core_link_write_dpcd(
1379                 dc_link,
1380                 DP_TEST_RESPONSE,
1381                 &test_response.raw,
1382                 sizeof(test_response));
1383         } else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) &&
1384                         dc_link_check_link_loss_status(dc_link, &offload_work->data) &&
1385                         dc_link_dp_allow_hpd_rx_irq(dc_link)) {
1386                 /* offload_work->data is from handle_hpd_rx_irq->
1387                  * schedule_hpd_rx_offload_work.this is defer handle
1388                  * for hpd short pulse. upon here, link status may be
1389                  * changed, need get latest link status from dpcd
1390                  * registers. if link status is good, skip run link
1391                  * training again.
1392                  */
1393                 union hpd_irq_data irq_data;
1394
1395                 memset(&irq_data, 0, sizeof(irq_data));
1396
1397                 /* before dc_link_dp_handle_link_loss, allow new link lost handle
1398                  * request be added to work queue if link lost at end of dc_link_
1399                  * dp_handle_link_loss
1400                  */
1401                 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1402                 offload_work->offload_wq->is_handling_link_loss = false;
1403                 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1404
1405                 if ((dc_link_dp_read_hpd_rx_irq_data(dc_link, &irq_data) == DC_OK) &&
1406                         dc_link_check_link_loss_status(dc_link, &irq_data))
1407                         dc_link_dp_handle_link_loss(dc_link);
1408         }
1409         mutex_unlock(&adev->dm.dc_lock);
1410
1411 skip:
1412         kfree(offload_work);
1413
1414 }
1415
1416 static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc)
1417 {
1418         int max_caps = dc->caps.max_links;
1419         int i = 0;
1420         struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL;
1421
1422         hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL);
1423
1424         if (!hpd_rx_offload_wq)
1425                 return NULL;
1426
1427
1428         for (i = 0; i < max_caps; i++) {
1429                 hpd_rx_offload_wq[i].wq =
1430                                     create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq");
1431
1432                 if (hpd_rx_offload_wq[i].wq == NULL) {
1433                         DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!");
1434                         goto out_err;
1435                 }
1436
1437                 spin_lock_init(&hpd_rx_offload_wq[i].offload_lock);
1438         }
1439
1440         return hpd_rx_offload_wq;
1441
1442 out_err:
1443         for (i = 0; i < max_caps; i++) {
1444                 if (hpd_rx_offload_wq[i].wq)
1445                         destroy_workqueue(hpd_rx_offload_wq[i].wq);
1446         }
1447         kfree(hpd_rx_offload_wq);
1448         return NULL;
1449 }
1450
1451 struct amdgpu_stutter_quirk {
1452         u16 chip_vendor;
1453         u16 chip_device;
1454         u16 subsys_vendor;
1455         u16 subsys_device;
1456         u8 revision;
1457 };
1458
1459 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = {
1460         /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */
1461         { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },
1462         { 0, 0, 0, 0, 0 },
1463 };
1464
1465 static bool dm_should_disable_stutter(struct pci_dev *pdev)
1466 {
1467         const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list;
1468
1469         while (p && p->chip_device != 0) {
1470                 if (pdev->vendor == p->chip_vendor &&
1471                     pdev->device == p->chip_device &&
1472                     pdev->subsystem_vendor == p->subsys_vendor &&
1473                     pdev->subsystem_device == p->subsys_device &&
1474                     pdev->revision == p->revision) {
1475                         return true;
1476                 }
1477                 ++p;
1478         }
1479         return false;
1480 }
1481
1482 static const struct dmi_system_id hpd_disconnect_quirk_table[] = {
1483         {
1484                 .matches = {
1485                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1486                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"),
1487                 },
1488         },
1489         {
1490                 .matches = {
1491                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1492                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"),
1493                 },
1494         },
1495         {
1496                 .matches = {
1497                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1498                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"),
1499                 },
1500         },
1501         {
1502                 .matches = {
1503                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1504                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"),
1505                 },
1506         },
1507         {
1508                 .matches = {
1509                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1510                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"),
1511                 },
1512         },
1513         {
1514                 .matches = {
1515                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1516                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"),
1517                 },
1518         },
1519         {
1520                 .matches = {
1521                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1522                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"),
1523                 },
1524         },
1525         {
1526                 .matches = {
1527                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1528                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"),
1529                 },
1530         },
1531         {
1532                 .matches = {
1533                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1534                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"),
1535                 },
1536         },
1537         {}
1538         /* TODO: refactor this from a fixed table to a dynamic option */
1539 };
1540
1541 static void retrieve_dmi_info(struct amdgpu_display_manager *dm)
1542 {
1543         const struct dmi_system_id *dmi_id;
1544
1545         dm->aux_hpd_discon_quirk = false;
1546
1547         dmi_id = dmi_first_match(hpd_disconnect_quirk_table);
1548         if (dmi_id) {
1549                 dm->aux_hpd_discon_quirk = true;
1550                 DRM_INFO("aux_hpd_discon_quirk attached\n");
1551         }
1552 }
1553
1554 static int amdgpu_dm_init(struct amdgpu_device *adev)
1555 {
1556         struct dc_init_data init_data;
1557         struct dc_callback_init init_params;
1558         int r;
1559
1560         adev->dm.ddev = adev_to_drm(adev);
1561         adev->dm.adev = adev;
1562
1563         /* Zero all the fields */
1564         memset(&init_data, 0, sizeof(init_data));
1565         memset(&init_params, 0, sizeof(init_params));
1566
1567         mutex_init(&adev->dm.dpia_aux_lock);
1568         mutex_init(&adev->dm.dc_lock);
1569         mutex_init(&adev->dm.audio_lock);
1570
1571         if (amdgpu_dm_irq_init(adev)) {
1572                 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
1573                 goto error;
1574         }
1575
1576         init_data.asic_id.chip_family = adev->family;
1577
1578         init_data.asic_id.pci_revision_id = adev->pdev->revision;
1579         init_data.asic_id.hw_internal_rev = adev->external_rev_id;
1580         init_data.asic_id.chip_id = adev->pdev->device;
1581
1582         init_data.asic_id.vram_width = adev->gmc.vram_width;
1583         /* TODO: initialize init_data.asic_id.vram_type here!!!! */
1584         init_data.asic_id.atombios_base_address =
1585                 adev->mode_info.atom_context->bios;
1586
1587         init_data.driver = adev;
1588
1589         adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
1590
1591         if (!adev->dm.cgs_device) {
1592                 DRM_ERROR("amdgpu: failed to create cgs device.\n");
1593                 goto error;
1594         }
1595
1596         init_data.cgs_device = adev->dm.cgs_device;
1597
1598         init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
1599
1600         switch (adev->ip_versions[DCE_HWIP][0]) {
1601         case IP_VERSION(2, 1, 0):
1602                 switch (adev->dm.dmcub_fw_version) {
1603                 case 0: /* development */
1604                 case 0x1: /* linux-firmware.git hash 6d9f399 */
1605                 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */
1606                         init_data.flags.disable_dmcu = false;
1607                         break;
1608                 default:
1609                         init_data.flags.disable_dmcu = true;
1610                 }
1611                 break;
1612         case IP_VERSION(2, 0, 3):
1613                 init_data.flags.disable_dmcu = true;
1614                 break;
1615         default:
1616                 break;
1617         }
1618
1619         switch (adev->asic_type) {
1620         case CHIP_CARRIZO:
1621         case CHIP_STONEY:
1622                 init_data.flags.gpu_vm_support = true;
1623                 break;
1624         default:
1625                 switch (adev->ip_versions[DCE_HWIP][0]) {
1626                 case IP_VERSION(1, 0, 0):
1627                 case IP_VERSION(1, 0, 1):
1628                         /* enable S/G on PCO and RV2 */
1629                         if ((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
1630                             (adev->apu_flags & AMD_APU_IS_PICASSO))
1631                                 init_data.flags.gpu_vm_support = true;
1632                         break;
1633                 case IP_VERSION(2, 1, 0):
1634                 case IP_VERSION(3, 0, 1):
1635                 case IP_VERSION(3, 1, 2):
1636                 case IP_VERSION(3, 1, 3):
1637                 case IP_VERSION(3, 1, 4):
1638                 case IP_VERSION(3, 1, 5):
1639                 case IP_VERSION(3, 1, 6):
1640                         init_data.flags.gpu_vm_support = true;
1641                         break;
1642                 default:
1643                         break;
1644                 }
1645                 break;
1646         }
1647         if (init_data.flags.gpu_vm_support &&
1648             (amdgpu_sg_display == 0))
1649                 init_data.flags.gpu_vm_support = false;
1650
1651         if (init_data.flags.gpu_vm_support)
1652                 adev->mode_info.gpu_vm_support = true;
1653
1654         if (amdgpu_dc_feature_mask & DC_FBC_MASK)
1655                 init_data.flags.fbc_support = true;
1656
1657         if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
1658                 init_data.flags.multi_mon_pp_mclk_switch = true;
1659
1660         if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
1661                 init_data.flags.disable_fractional_pwm = true;
1662
1663         if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING)
1664                 init_data.flags.edp_no_power_sequencing = true;
1665
1666         if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A)
1667                 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true;
1668         if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)
1669                 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;
1670
1671         init_data.flags.seamless_boot_edp_requested = false;
1672
1673         if (check_seamless_boot_capability(adev)) {
1674                 init_data.flags.seamless_boot_edp_requested = true;
1675                 init_data.flags.allow_seamless_boot_optimization = true;
1676                 DRM_INFO("Seamless boot condition check passed\n");
1677         }
1678
1679         init_data.flags.enable_mipi_converter_optimization = true;
1680
1681         init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];
1682         init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];
1683
1684         INIT_LIST_HEAD(&adev->dm.da_list);
1685
1686         retrieve_dmi_info(&adev->dm);
1687
1688         /* Display Core create. */
1689         adev->dm.dc = dc_create(&init_data);
1690
1691         if (adev->dm.dc) {
1692                 DRM_INFO("Display Core v%s initialized on %s\n", DC_VER,
1693                          dce_version_to_string(adev->dm.dc->ctx->dce_version));
1694         } else {
1695                 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
1696                 goto error;
1697         }
1698
1699         if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
1700                 adev->dm.dc->debug.force_single_disp_pipe_split = false;
1701                 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
1702         }
1703
1704         if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
1705                 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
1706         if (dm_should_disable_stutter(adev->pdev))
1707                 adev->dm.dc->debug.disable_stutter = true;
1708
1709         if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
1710                 adev->dm.dc->debug.disable_stutter = true;
1711
1712         if (amdgpu_dc_debug_mask & DC_DISABLE_DSC)
1713                 adev->dm.dc->debug.disable_dsc = true;
1714
1715         if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
1716                 adev->dm.dc->debug.disable_clock_gate = true;
1717
1718         if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH)
1719                 adev->dm.dc->debug.force_subvp_mclk_switch = true;
1720
1721         adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm;
1722
1723         /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */
1724         adev->dm.dc->debug.ignore_cable_id = true;
1725
1726         /* TODO: There is a new drm mst change where the freedom of
1727          * vc_next_start_slot update is revoked/moved into drm, instead of in
1728          * driver. This forces us to make sure to get vc_next_start_slot updated
1729          * in drm function each time without considering if mst_state is active
1730          * or not. Otherwise, next time hotplug will give wrong start_slot
1731          * number. We are implementing a temporary solution to even notify drm
1732          * mst deallocation when link is no longer of MST type when uncommitting
1733          * the stream so we will have more time to work on a proper solution.
1734          * Ideally when dm_helpers_dp_mst_stop_top_mgr message is triggered, we
1735          * should notify drm to do a complete "reset" of its states and stop
1736          * calling further drm mst functions when link is no longer of an MST
1737          * type. This could happen when we unplug an MST hubs/displays. When
1738          * uncommit stream comes later after unplug, we should just reset
1739          * hardware states only.
1740          */
1741         adev->dm.dc->debug.temp_mst_deallocation_sequence = true;
1742
1743         if (adev->dm.dc->caps.dp_hdmi21_pcon_support)
1744                 DRM_INFO("DP-HDMI FRL PCON supported\n");
1745
1746         r = dm_dmub_hw_init(adev);
1747         if (r) {
1748                 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
1749                 goto error;
1750         }
1751
1752         dc_hardware_init(adev->dm.dc);
1753
1754         adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc);
1755         if (!adev->dm.hpd_rx_offload_wq) {
1756                 DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n");
1757                 goto error;
1758         }
1759
1760         if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) {
1761                 struct dc_phy_addr_space_config pa_config;
1762
1763                 mmhub_read_system_context(adev, &pa_config);
1764
1765                 // Call the DC init_memory func
1766                 dc_setup_system_context(adev->dm.dc, &pa_config);
1767         }
1768
1769         adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
1770         if (!adev->dm.freesync_module) {
1771                 DRM_ERROR(
1772                 "amdgpu: failed to initialize freesync_module.\n");
1773         } else
1774                 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
1775                                 adev->dm.freesync_module);
1776
1777         amdgpu_dm_init_color_mod();
1778
1779         if (adev->dm.dc->caps.max_links > 0) {
1780                 adev->dm.vblank_control_workqueue =
1781                         create_singlethread_workqueue("dm_vblank_control_workqueue");
1782                 if (!adev->dm.vblank_control_workqueue)
1783                         DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n");
1784         }
1785
1786         if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
1787                 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
1788
1789                 if (!adev->dm.hdcp_workqueue)
1790                         DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
1791                 else
1792                         DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
1793
1794                 dc_init_callbacks(adev->dm.dc, &init_params);
1795         }
1796         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
1797                 init_completion(&adev->dm.dmub_aux_transfer_done);
1798                 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL);
1799                 if (!adev->dm.dmub_notify) {
1800                         DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify");
1801                         goto error;
1802                 }
1803
1804                 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq");
1805                 if (!adev->dm.delayed_hpd_wq) {
1806                         DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n");
1807                         goto error;
1808                 }
1809
1810                 amdgpu_dm_outbox_init(adev);
1811                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY,
1812                         dmub_aux_setconfig_callback, false)) {
1813                         DRM_ERROR("amdgpu: fail to register dmub aux callback");
1814                         goto error;
1815                 }
1816                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true)) {
1817                         DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1818                         goto error;
1819                 }
1820                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true)) {
1821                         DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1822                         goto error;
1823                 }
1824         }
1825
1826         /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive.
1827          * It is expected that DMUB will resend any pending notifications at this point, for
1828          * example HPD from DPIA.
1829          */
1830         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
1831                 dc_enable_dmub_outbox(adev->dm.dc);
1832
1833                 /* DPIA trace goes to dmesg logs only if outbox is enabled */
1834                 if (amdgpu_dc_debug_mask & DC_ENABLE_DPIA_TRACE)
1835                         dc_dmub_srv_enable_dpia_trace(adev->dm.dc);
1836         }
1837
1838         if (amdgpu_dm_initialize_drm_device(adev)) {
1839                 DRM_ERROR(
1840                 "amdgpu: failed to initialize sw for display support.\n");
1841                 goto error;
1842         }
1843
1844         /* create fake encoders for MST */
1845         dm_dp_create_fake_mst_encoders(adev);
1846
1847         /* TODO: Add_display_info? */
1848
1849         /* TODO use dynamic cursor width */
1850         adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
1851         adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
1852
1853         if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
1854                 DRM_ERROR(
1855                 "amdgpu: failed to initialize sw for display support.\n");
1856                 goto error;
1857         }
1858
1859 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1860         adev->dm.secure_display_ctxs = amdgpu_dm_crtc_secure_display_create_contexts(adev);
1861         if (!adev->dm.secure_display_ctxs)
1862                 DRM_ERROR("amdgpu: failed to initialize secure display contexts.\n");
1863 #endif
1864
1865         DRM_DEBUG_DRIVER("KMS initialized.\n");
1866
1867         return 0;
1868 error:
1869         amdgpu_dm_fini(adev);
1870
1871         return -EINVAL;
1872 }
1873
1874 static int amdgpu_dm_early_fini(void *handle)
1875 {
1876         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1877
1878         amdgpu_dm_audio_fini(adev);
1879
1880         return 0;
1881 }
1882
1883 static void amdgpu_dm_fini(struct amdgpu_device *adev)
1884 {
1885         int i;
1886
1887         if (adev->dm.vblank_control_workqueue) {
1888                 destroy_workqueue(adev->dm.vblank_control_workqueue);
1889                 adev->dm.vblank_control_workqueue = NULL;
1890         }
1891
1892         amdgpu_dm_destroy_drm_device(&adev->dm);
1893
1894 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1895         if (adev->dm.secure_display_ctxs) {
1896                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1897                         if (adev->dm.secure_display_ctxs[i].crtc) {
1898                                 flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work);
1899                                 flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work);
1900                         }
1901                 }
1902                 kfree(adev->dm.secure_display_ctxs);
1903                 adev->dm.secure_display_ctxs = NULL;
1904         }
1905 #endif
1906         if (adev->dm.hdcp_workqueue) {
1907                 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue);
1908                 adev->dm.hdcp_workqueue = NULL;
1909         }
1910
1911         if (adev->dm.dc)
1912                 dc_deinit_callbacks(adev->dm.dc);
1913
1914         if (adev->dm.dc)
1915                 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
1916
1917         if (dc_enable_dmub_notifications(adev->dm.dc)) {
1918                 kfree(adev->dm.dmub_notify);
1919                 adev->dm.dmub_notify = NULL;
1920                 destroy_workqueue(adev->dm.delayed_hpd_wq);
1921                 adev->dm.delayed_hpd_wq = NULL;
1922         }
1923
1924         if (adev->dm.dmub_bo)
1925                 amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
1926                                       &adev->dm.dmub_bo_gpu_addr,
1927                                       &adev->dm.dmub_bo_cpu_addr);
1928
1929         if (adev->dm.hpd_rx_offload_wq) {
1930                 for (i = 0; i < adev->dm.dc->caps.max_links; i++) {
1931                         if (adev->dm.hpd_rx_offload_wq[i].wq) {
1932                                 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq);
1933                                 adev->dm.hpd_rx_offload_wq[i].wq = NULL;
1934                         }
1935                 }
1936
1937                 kfree(adev->dm.hpd_rx_offload_wq);
1938                 adev->dm.hpd_rx_offload_wq = NULL;
1939         }
1940
1941         /* DC Destroy TODO: Replace destroy DAL */
1942         if (adev->dm.dc)
1943                 dc_destroy(&adev->dm.dc);
1944         /*
1945          * TODO: pageflip, vlank interrupt
1946          *
1947          * amdgpu_dm_irq_fini(adev);
1948          */
1949
1950         if (adev->dm.cgs_device) {
1951                 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
1952                 adev->dm.cgs_device = NULL;
1953         }
1954         if (adev->dm.freesync_module) {
1955                 mod_freesync_destroy(adev->dm.freesync_module);
1956                 adev->dm.freesync_module = NULL;
1957         }
1958
1959         mutex_destroy(&adev->dm.audio_lock);
1960         mutex_destroy(&adev->dm.dc_lock);
1961         mutex_destroy(&adev->dm.dpia_aux_lock);
1962 }
1963
1964 static int load_dmcu_fw(struct amdgpu_device *adev)
1965 {
1966         const char *fw_name_dmcu = NULL;
1967         int r;
1968         const struct dmcu_firmware_header_v1_0 *hdr;
1969
1970         switch (adev->asic_type) {
1971 #if defined(CONFIG_DRM_AMD_DC_SI)
1972         case CHIP_TAHITI:
1973         case CHIP_PITCAIRN:
1974         case CHIP_VERDE:
1975         case CHIP_OLAND:
1976 #endif
1977         case CHIP_BONAIRE:
1978         case CHIP_HAWAII:
1979         case CHIP_KAVERI:
1980         case CHIP_KABINI:
1981         case CHIP_MULLINS:
1982         case CHIP_TONGA:
1983         case CHIP_FIJI:
1984         case CHIP_CARRIZO:
1985         case CHIP_STONEY:
1986         case CHIP_POLARIS11:
1987         case CHIP_POLARIS10:
1988         case CHIP_POLARIS12:
1989         case CHIP_VEGAM:
1990         case CHIP_VEGA10:
1991         case CHIP_VEGA12:
1992         case CHIP_VEGA20:
1993                 return 0;
1994         case CHIP_NAVI12:
1995                 fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
1996                 break;
1997         case CHIP_RAVEN:
1998                 if (ASICREV_IS_PICASSO(adev->external_rev_id))
1999                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
2000                 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
2001                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
2002                 else
2003                         return 0;
2004                 break;
2005         default:
2006                 switch (adev->ip_versions[DCE_HWIP][0]) {
2007                 case IP_VERSION(2, 0, 2):
2008                 case IP_VERSION(2, 0, 3):
2009                 case IP_VERSION(2, 0, 0):
2010                 case IP_VERSION(2, 1, 0):
2011                 case IP_VERSION(3, 0, 0):
2012                 case IP_VERSION(3, 0, 2):
2013                 case IP_VERSION(3, 0, 3):
2014                 case IP_VERSION(3, 0, 1):
2015                 case IP_VERSION(3, 1, 2):
2016                 case IP_VERSION(3, 1, 3):
2017                 case IP_VERSION(3, 1, 4):
2018                 case IP_VERSION(3, 1, 5):
2019                 case IP_VERSION(3, 1, 6):
2020                 case IP_VERSION(3, 2, 0):
2021                 case IP_VERSION(3, 2, 1):
2022                         return 0;
2023                 default:
2024                         break;
2025                 }
2026                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2027                 return -EINVAL;
2028         }
2029
2030         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2031                 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
2032                 return 0;
2033         }
2034
2035         r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, fw_name_dmcu);
2036         if (r == -ENODEV) {
2037                 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
2038                 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
2039                 adev->dm.fw_dmcu = NULL;
2040                 return 0;
2041         }
2042         if (r) {
2043                 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
2044                         fw_name_dmcu);
2045                 amdgpu_ucode_release(&adev->dm.fw_dmcu);
2046                 return r;
2047         }
2048
2049         hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
2050         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
2051         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
2052         adev->firmware.fw_size +=
2053                 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2054
2055         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
2056         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
2057         adev->firmware.fw_size +=
2058                 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2059
2060         adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
2061
2062         DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
2063
2064         return 0;
2065 }
2066
2067 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
2068 {
2069         struct amdgpu_device *adev = ctx;
2070
2071         return dm_read_reg(adev->dm.dc->ctx, address);
2072 }
2073
2074 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
2075                                      uint32_t value)
2076 {
2077         struct amdgpu_device *adev = ctx;
2078
2079         return dm_write_reg(adev->dm.dc->ctx, address, value);
2080 }
2081
2082 static int dm_dmub_sw_init(struct amdgpu_device *adev)
2083 {
2084         struct dmub_srv_create_params create_params;
2085         struct dmub_srv_region_params region_params;
2086         struct dmub_srv_region_info region_info;
2087         struct dmub_srv_fb_params fb_params;
2088         struct dmub_srv_fb_info *fb_info;
2089         struct dmub_srv *dmub_srv;
2090         const struct dmcub_firmware_header_v1_0 *hdr;
2091         enum dmub_asic dmub_asic;
2092         enum dmub_status status;
2093         int r;
2094
2095         switch (adev->ip_versions[DCE_HWIP][0]) {
2096         case IP_VERSION(2, 1, 0):
2097                 dmub_asic = DMUB_ASIC_DCN21;
2098                 break;
2099         case IP_VERSION(3, 0, 0):
2100                 dmub_asic = DMUB_ASIC_DCN30;
2101                 break;
2102         case IP_VERSION(3, 0, 1):
2103                 dmub_asic = DMUB_ASIC_DCN301;
2104                 break;
2105         case IP_VERSION(3, 0, 2):
2106                 dmub_asic = DMUB_ASIC_DCN302;
2107                 break;
2108         case IP_VERSION(3, 0, 3):
2109                 dmub_asic = DMUB_ASIC_DCN303;
2110                 break;
2111         case IP_VERSION(3, 1, 2):
2112         case IP_VERSION(3, 1, 3):
2113                 dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31;
2114                 break;
2115         case IP_VERSION(3, 1, 4):
2116                 dmub_asic = DMUB_ASIC_DCN314;
2117                 break;
2118         case IP_VERSION(3, 1, 5):
2119                 dmub_asic = DMUB_ASIC_DCN315;
2120                 break;
2121         case IP_VERSION(3, 1, 6):
2122                 dmub_asic = DMUB_ASIC_DCN316;
2123                 break;
2124         case IP_VERSION(3, 2, 0):
2125                 dmub_asic = DMUB_ASIC_DCN32;
2126                 break;
2127         case IP_VERSION(3, 2, 1):
2128                 dmub_asic = DMUB_ASIC_DCN321;
2129                 break;
2130         default:
2131                 /* ASIC doesn't support DMUB. */
2132                 return 0;
2133         }
2134
2135         hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
2136         adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
2137
2138         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2139                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
2140                         AMDGPU_UCODE_ID_DMCUB;
2141                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw =
2142                         adev->dm.dmub_fw;
2143                 adev->firmware.fw_size +=
2144                         ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
2145
2146                 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
2147                          adev->dm.dmcub_fw_version);
2148         }
2149
2150
2151         adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
2152         dmub_srv = adev->dm.dmub_srv;
2153
2154         if (!dmub_srv) {
2155                 DRM_ERROR("Failed to allocate DMUB service!\n");
2156                 return -ENOMEM;
2157         }
2158
2159         memset(&create_params, 0, sizeof(create_params));
2160         create_params.user_ctx = adev;
2161         create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
2162         create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
2163         create_params.asic = dmub_asic;
2164
2165         /* Create the DMUB service. */
2166         status = dmub_srv_create(dmub_srv, &create_params);
2167         if (status != DMUB_STATUS_OK) {
2168                 DRM_ERROR("Error creating DMUB service: %d\n", status);
2169                 return -EINVAL;
2170         }
2171
2172         /* Calculate the size of all the regions for the DMUB service. */
2173         memset(&region_params, 0, sizeof(region_params));
2174
2175         region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
2176                                         PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
2177         region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
2178         region_params.vbios_size = adev->bios_size;
2179         region_params.fw_bss_data = region_params.bss_data_size ?
2180                 adev->dm.dmub_fw->data +
2181                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2182                 le32_to_cpu(hdr->inst_const_bytes) : NULL;
2183         region_params.fw_inst_const =
2184                 adev->dm.dmub_fw->data +
2185                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2186                 PSP_HEADER_BYTES;
2187
2188         status = dmub_srv_calc_region_info(dmub_srv, &region_params,
2189                                            &region_info);
2190
2191         if (status != DMUB_STATUS_OK) {
2192                 DRM_ERROR("Error calculating DMUB region info: %d\n", status);
2193                 return -EINVAL;
2194         }
2195
2196         /*
2197          * Allocate a framebuffer based on the total size of all the regions.
2198          * TODO: Move this into GART.
2199          */
2200         r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
2201                                     AMDGPU_GEM_DOMAIN_VRAM |
2202                                     AMDGPU_GEM_DOMAIN_GTT,
2203                                     &adev->dm.dmub_bo,
2204                                     &adev->dm.dmub_bo_gpu_addr,
2205                                     &adev->dm.dmub_bo_cpu_addr);
2206         if (r)
2207                 return r;
2208
2209         /* Rebase the regions on the framebuffer address. */
2210         memset(&fb_params, 0, sizeof(fb_params));
2211         fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr;
2212         fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr;
2213         fb_params.region_info = &region_info;
2214
2215         adev->dm.dmub_fb_info =
2216                 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);
2217         fb_info = adev->dm.dmub_fb_info;
2218
2219         if (!fb_info) {
2220                 DRM_ERROR(
2221                         "Failed to allocate framebuffer info for DMUB service!\n");
2222                 return -ENOMEM;
2223         }
2224
2225         status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info);
2226         if (status != DMUB_STATUS_OK) {
2227                 DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
2228                 return -EINVAL;
2229         }
2230
2231         return 0;
2232 }
2233
2234 static int dm_sw_init(void *handle)
2235 {
2236         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2237         int r;
2238
2239         r = dm_dmub_sw_init(adev);
2240         if (r)
2241                 return r;
2242
2243         return load_dmcu_fw(adev);
2244 }
2245
2246 static int dm_sw_fini(void *handle)
2247 {
2248         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2249
2250         kfree(adev->dm.dmub_fb_info);
2251         adev->dm.dmub_fb_info = NULL;
2252
2253         if (adev->dm.dmub_srv) {
2254                 dmub_srv_destroy(adev->dm.dmub_srv);
2255                 adev->dm.dmub_srv = NULL;
2256         }
2257
2258         amdgpu_ucode_release(&adev->dm.dmub_fw);
2259         amdgpu_ucode_release(&adev->dm.fw_dmcu);
2260
2261         return 0;
2262 }
2263
2264 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
2265 {
2266         struct amdgpu_dm_connector *aconnector;
2267         struct drm_connector *connector;
2268         struct drm_connector_list_iter iter;
2269         int ret = 0;
2270
2271         drm_connector_list_iter_begin(dev, &iter);
2272         drm_for_each_connector_iter(connector, &iter) {
2273                 aconnector = to_amdgpu_dm_connector(connector);
2274                 if (aconnector->dc_link->type == dc_connection_mst_branch &&
2275                     aconnector->mst_mgr.aux) {
2276                         DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
2277                                          aconnector,
2278                                          aconnector->base.base.id);
2279
2280                         ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
2281                         if (ret < 0) {
2282                                 DRM_ERROR("DM_MST: Failed to start MST\n");
2283                                 aconnector->dc_link->type =
2284                                         dc_connection_single;
2285                                 ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2286                                                                      aconnector->dc_link);
2287                                 break;
2288                         }
2289                 }
2290         }
2291         drm_connector_list_iter_end(&iter);
2292
2293         return ret;
2294 }
2295
2296 static int dm_late_init(void *handle)
2297 {
2298         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2299
2300         struct dmcu_iram_parameters params;
2301         unsigned int linear_lut[16];
2302         int i;
2303         struct dmcu *dmcu = NULL;
2304
2305         dmcu = adev->dm.dc->res_pool->dmcu;
2306
2307         for (i = 0; i < 16; i++)
2308                 linear_lut[i] = 0xFFFF * i / 15;
2309
2310         params.set = 0;
2311         params.backlight_ramping_override = false;
2312         params.backlight_ramping_start = 0xCCCC;
2313         params.backlight_ramping_reduction = 0xCCCCCCCC;
2314         params.backlight_lut_array_size = 16;
2315         params.backlight_lut_array = linear_lut;
2316
2317         /* Min backlight level after ABM reduction,  Don't allow below 1%
2318          * 0xFFFF x 0.01 = 0x28F
2319          */
2320         params.min_abm_backlight = 0x28F;
2321         /* In the case where abm is implemented on dmcub,
2322          * dmcu object will be null.
2323          * ABM 2.4 and up are implemented on dmcub.
2324          */
2325         if (dmcu) {
2326                 if (!dmcu_load_iram(dmcu, params))
2327                         return -EINVAL;
2328         } else if (adev->dm.dc->ctx->dmub_srv) {
2329                 struct dc_link *edp_links[MAX_NUM_EDP];
2330                 int edp_num;
2331
2332                 dc_get_edp_links(adev->dm.dc, edp_links, &edp_num);
2333                 for (i = 0; i < edp_num; i++) {
2334                         if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i))
2335                                 return -EINVAL;
2336                 }
2337         }
2338
2339         return detect_mst_link_for_all_connectors(adev_to_drm(adev));
2340 }
2341
2342 static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr)
2343 {
2344         int ret;
2345         u8 guid[16];
2346         u64 tmp64;
2347
2348         mutex_lock(&mgr->lock);
2349         if (!mgr->mst_primary)
2350                 goto out_fail;
2351
2352         if (drm_dp_read_dpcd_caps(mgr->aux, mgr->dpcd) < 0) {
2353                 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n");
2354                 goto out_fail;
2355         }
2356
2357         ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
2358                                  DP_MST_EN |
2359                                  DP_UP_REQ_EN |
2360                                  DP_UPSTREAM_IS_SRC);
2361         if (ret < 0) {
2362                 drm_dbg_kms(mgr->dev, "mst write failed - undocked during suspend?\n");
2363                 goto out_fail;
2364         }
2365
2366         /* Some hubs forget their guids after they resume */
2367         ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, guid, 16);
2368         if (ret != 16) {
2369                 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n");
2370                 goto out_fail;
2371         }
2372
2373         if (memchr_inv(guid, 0, 16) == NULL) {
2374                 tmp64 = get_jiffies_64();
2375                 memcpy(&guid[0], &tmp64, sizeof(u64));
2376                 memcpy(&guid[8], &tmp64, sizeof(u64));
2377
2378                 ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, guid, 16);
2379
2380                 if (ret != 16) {
2381                         drm_dbg_kms(mgr->dev, "check mstb guid failed - undocked during suspend?\n");
2382                         goto out_fail;
2383                 }
2384         }
2385
2386         memcpy(mgr->mst_primary->guid, guid, 16);
2387
2388 out_fail:
2389         mutex_unlock(&mgr->lock);
2390 }
2391
2392 static void s3_handle_mst(struct drm_device *dev, bool suspend)
2393 {
2394         struct amdgpu_dm_connector *aconnector;
2395         struct drm_connector *connector;
2396         struct drm_connector_list_iter iter;
2397         struct drm_dp_mst_topology_mgr *mgr;
2398
2399         drm_connector_list_iter_begin(dev, &iter);
2400         drm_for_each_connector_iter(connector, &iter) {
2401                 aconnector = to_amdgpu_dm_connector(connector);
2402                 if (aconnector->dc_link->type != dc_connection_mst_branch ||
2403                     aconnector->mst_root)
2404                         continue;
2405
2406                 mgr = &aconnector->mst_mgr;
2407
2408                 if (suspend) {
2409                         drm_dp_mst_topology_mgr_suspend(mgr);
2410                 } else {
2411                         /* if extended timeout is supported in hardware,
2412                          * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
2413                          * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
2414                          */
2415                         try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
2416                         if (!dp_is_lttpr_present(aconnector->dc_link))
2417                                 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
2418
2419                         /* TODO: move resume_mst_branch_status() into drm mst resume again
2420                          * once topology probing work is pulled out from mst resume into mst
2421                          * resume 2nd step. mst resume 2nd step should be called after old
2422                          * state getting restored (i.e. drm_atomic_helper_resume()).
2423                          */
2424                         resume_mst_branch_status(mgr);
2425                 }
2426         }
2427         drm_connector_list_iter_end(&iter);
2428 }
2429
2430 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
2431 {
2432         int ret = 0;
2433
2434         /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
2435          * on window driver dc implementation.
2436          * For Navi1x, clock settings of dcn watermarks are fixed. the settings
2437          * should be passed to smu during boot up and resume from s3.
2438          * boot up: dc calculate dcn watermark clock settings within dc_create,
2439          * dcn20_resource_construct
2440          * then call pplib functions below to pass the settings to smu:
2441          * smu_set_watermarks_for_clock_ranges
2442          * smu_set_watermarks_table
2443          * navi10_set_watermarks_table
2444          * smu_write_watermarks_table
2445          *
2446          * For Renoir, clock settings of dcn watermark are also fixed values.
2447          * dc has implemented different flow for window driver:
2448          * dc_hardware_init / dc_set_power_state
2449          * dcn10_init_hw
2450          * notify_wm_ranges
2451          * set_wm_ranges
2452          * -- Linux
2453          * smu_set_watermarks_for_clock_ranges
2454          * renoir_set_watermarks_table
2455          * smu_write_watermarks_table
2456          *
2457          * For Linux,
2458          * dc_hardware_init -> amdgpu_dm_init
2459          * dc_set_power_state --> dm_resume
2460          *
2461          * therefore, this function apply to navi10/12/14 but not Renoir
2462          * *
2463          */
2464         switch (adev->ip_versions[DCE_HWIP][0]) {
2465         case IP_VERSION(2, 0, 2):
2466         case IP_VERSION(2, 0, 0):
2467                 break;
2468         default:
2469                 return 0;
2470         }
2471
2472         ret = amdgpu_dpm_write_watermarks_table(adev);
2473         if (ret) {
2474                 DRM_ERROR("Failed to update WMTABLE!\n");
2475                 return ret;
2476         }
2477
2478         return 0;
2479 }
2480
2481 /**
2482  * dm_hw_init() - Initialize DC device
2483  * @handle: The base driver device containing the amdgpu_dm device.
2484  *
2485  * Initialize the &struct amdgpu_display_manager device. This involves calling
2486  * the initializers of each DM component, then populating the struct with them.
2487  *
2488  * Although the function implies hardware initialization, both hardware and
2489  * software are initialized here. Splitting them out to their relevant init
2490  * hooks is a future TODO item.
2491  *
2492  * Some notable things that are initialized here:
2493  *
2494  * - Display Core, both software and hardware
2495  * - DC modules that we need (freesync and color management)
2496  * - DRM software states
2497  * - Interrupt sources and handlers
2498  * - Vblank support
2499  * - Debug FS entries, if enabled
2500  */
2501 static int dm_hw_init(void *handle)
2502 {
2503         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2504         /* Create DAL display manager */
2505         amdgpu_dm_init(adev);
2506         amdgpu_dm_hpd_init(adev);
2507
2508         return 0;
2509 }
2510
2511 /**
2512  * dm_hw_fini() - Teardown DC device
2513  * @handle: The base driver device containing the amdgpu_dm device.
2514  *
2515  * Teardown components within &struct amdgpu_display_manager that require
2516  * cleanup. This involves cleaning up the DRM device, DC, and any modules that
2517  * were loaded. Also flush IRQ workqueues and disable them.
2518  */
2519 static int dm_hw_fini(void *handle)
2520 {
2521         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2522
2523         amdgpu_dm_hpd_fini(adev);
2524
2525         amdgpu_dm_irq_fini(adev);
2526         amdgpu_dm_fini(adev);
2527         return 0;
2528 }
2529
2530
2531 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
2532                                  struct dc_state *state, bool enable)
2533 {
2534         enum dc_irq_source irq_source;
2535         struct amdgpu_crtc *acrtc;
2536         int rc = -EBUSY;
2537         int i = 0;
2538
2539         for (i = 0; i < state->stream_count; i++) {
2540                 acrtc = get_crtc_by_otg_inst(
2541                                 adev, state->stream_status[i].primary_otg_inst);
2542
2543                 if (acrtc && state->stream_status[i].plane_count != 0) {
2544                         irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst;
2545                         rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
2546                         if (rc)
2547                                 DRM_WARN("Failed to %s pflip interrupts\n",
2548                                          enable ? "enable" : "disable");
2549
2550                         if (enable) {
2551                                 if (amdgpu_dm_crtc_vrr_active(to_dm_crtc_state(acrtc->base.state)))
2552                                         rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, true);
2553                         } else
2554                                 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, false);
2555
2556                         if (rc)
2557                                 DRM_WARN("Failed to %sable vupdate interrupt\n", enable ? "en" : "dis");
2558
2559                         irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
2560                         /* During gpu-reset we disable and then enable vblank irq, so
2561                          * don't use amdgpu_irq_get/put() to avoid refcount change.
2562                          */
2563                         if (!dc_interrupt_set(adev->dm.dc, irq_source, enable))
2564                                 DRM_WARN("Failed to %sable vblank interrupt\n", enable ? "en" : "dis");
2565                 }
2566         }
2567
2568 }
2569
2570 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
2571 {
2572         struct dc_state *context = NULL;
2573         enum dc_status res = DC_ERROR_UNEXPECTED;
2574         int i;
2575         struct dc_stream_state *del_streams[MAX_PIPES];
2576         int del_streams_count = 0;
2577
2578         memset(del_streams, 0, sizeof(del_streams));
2579
2580         context = dc_create_state(dc);
2581         if (context == NULL)
2582                 goto context_alloc_fail;
2583
2584         dc_resource_state_copy_construct_current(dc, context);
2585
2586         /* First remove from context all streams */
2587         for (i = 0; i < context->stream_count; i++) {
2588                 struct dc_stream_state *stream = context->streams[i];
2589
2590                 del_streams[del_streams_count++] = stream;
2591         }
2592
2593         /* Remove all planes for removed streams and then remove the streams */
2594         for (i = 0; i < del_streams_count; i++) {
2595                 if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) {
2596                         res = DC_FAIL_DETACH_SURFACES;
2597                         goto fail;
2598                 }
2599
2600                 res = dc_remove_stream_from_ctx(dc, context, del_streams[i]);
2601                 if (res != DC_OK)
2602                         goto fail;
2603         }
2604
2605         res = dc_commit_streams(dc, context->streams, context->stream_count);
2606
2607 fail:
2608         dc_release_state(context);
2609
2610 context_alloc_fail:
2611         return res;
2612 }
2613
2614 static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm)
2615 {
2616         int i;
2617
2618         if (dm->hpd_rx_offload_wq) {
2619                 for (i = 0; i < dm->dc->caps.max_links; i++)
2620                         flush_workqueue(dm->hpd_rx_offload_wq[i].wq);
2621         }
2622 }
2623
2624 static int dm_suspend(void *handle)
2625 {
2626         struct amdgpu_device *adev = handle;
2627         struct amdgpu_display_manager *dm = &adev->dm;
2628         int ret = 0;
2629
2630         if (amdgpu_in_reset(adev)) {
2631                 mutex_lock(&dm->dc_lock);
2632
2633                 dc_allow_idle_optimizations(adev->dm.dc, false);
2634
2635                 dm->cached_dc_state = dc_copy_state(dm->dc->current_state);
2636
2637                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
2638
2639                 amdgpu_dm_commit_zero_streams(dm->dc);
2640
2641                 amdgpu_dm_irq_suspend(adev);
2642
2643                 hpd_rx_irq_work_suspend(dm);
2644
2645                 return ret;
2646         }
2647
2648         WARN_ON(adev->dm.cached_state);
2649         adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));
2650
2651         s3_handle_mst(adev_to_drm(adev), true);
2652
2653         amdgpu_dm_irq_suspend(adev);
2654
2655         hpd_rx_irq_work_suspend(dm);
2656
2657         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
2658
2659         return 0;
2660 }
2661
2662 struct amdgpu_dm_connector *
2663 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
2664                                              struct drm_crtc *crtc)
2665 {
2666         u32 i;
2667         struct drm_connector_state *new_con_state;
2668         struct drm_connector *connector;
2669         struct drm_crtc *crtc_from_state;
2670
2671         for_each_new_connector_in_state(state, connector, new_con_state, i) {
2672                 crtc_from_state = new_con_state->crtc;
2673
2674                 if (crtc_from_state == crtc)
2675                         return to_amdgpu_dm_connector(connector);
2676         }
2677
2678         return NULL;
2679 }
2680
2681 static void emulated_link_detect(struct dc_link *link)
2682 {
2683         struct dc_sink_init_data sink_init_data = { 0 };
2684         struct display_sink_capability sink_caps = { 0 };
2685         enum dc_edid_status edid_status;
2686         struct dc_context *dc_ctx = link->ctx;
2687         struct dc_sink *sink = NULL;
2688         struct dc_sink *prev_sink = NULL;
2689
2690         link->type = dc_connection_none;
2691         prev_sink = link->local_sink;
2692
2693         if (prev_sink)
2694                 dc_sink_release(prev_sink);
2695
2696         switch (link->connector_signal) {
2697         case SIGNAL_TYPE_HDMI_TYPE_A: {
2698                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2699                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
2700                 break;
2701         }
2702
2703         case SIGNAL_TYPE_DVI_SINGLE_LINK: {
2704                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2705                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
2706                 break;
2707         }
2708
2709         case SIGNAL_TYPE_DVI_DUAL_LINK: {
2710                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2711                 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
2712                 break;
2713         }
2714
2715         case SIGNAL_TYPE_LVDS: {
2716                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2717                 sink_caps.signal = SIGNAL_TYPE_LVDS;
2718                 break;
2719         }
2720
2721         case SIGNAL_TYPE_EDP: {
2722                 sink_caps.transaction_type =
2723                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2724                 sink_caps.signal = SIGNAL_TYPE_EDP;
2725                 break;
2726         }
2727
2728         case SIGNAL_TYPE_DISPLAY_PORT: {
2729                 sink_caps.transaction_type =
2730                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2731                 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
2732                 break;
2733         }
2734
2735         default:
2736                 DC_ERROR("Invalid connector type! signal:%d\n",
2737                         link->connector_signal);
2738                 return;
2739         }
2740
2741         sink_init_data.link = link;
2742         sink_init_data.sink_signal = sink_caps.signal;
2743
2744         sink = dc_sink_create(&sink_init_data);
2745         if (!sink) {
2746                 DC_ERROR("Failed to create sink!\n");
2747                 return;
2748         }
2749
2750         /* dc_sink_create returns a new reference */
2751         link->local_sink = sink;
2752
2753         edid_status = dm_helpers_read_local_edid(
2754                         link->ctx,
2755                         link,
2756                         sink);
2757
2758         if (edid_status != EDID_OK)
2759                 DC_ERROR("Failed to read EDID");
2760
2761 }
2762
2763 static void dm_gpureset_commit_state(struct dc_state *dc_state,
2764                                      struct amdgpu_display_manager *dm)
2765 {
2766         struct {
2767                 struct dc_surface_update surface_updates[MAX_SURFACES];
2768                 struct dc_plane_info plane_infos[MAX_SURFACES];
2769                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
2770                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
2771                 struct dc_stream_update stream_update;
2772         } *bundle;
2773         int k, m;
2774
2775         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
2776
2777         if (!bundle) {
2778                 dm_error("Failed to allocate update bundle\n");
2779                 goto cleanup;
2780         }
2781
2782         for (k = 0; k < dc_state->stream_count; k++) {
2783                 bundle->stream_update.stream = dc_state->streams[k];
2784
2785                 for (m = 0; m < dc_state->stream_status->plane_count; m++) {
2786                         bundle->surface_updates[m].surface =
2787                                 dc_state->stream_status->plane_states[m];
2788                         bundle->surface_updates[m].surface->force_full_update =
2789                                 true;
2790                 }
2791
2792                 update_planes_and_stream_adapter(dm->dc,
2793                                          UPDATE_TYPE_FULL,
2794                                          dc_state->stream_status->plane_count,
2795                                          dc_state->streams[k],
2796                                          &bundle->stream_update,
2797                                          bundle->surface_updates);
2798         }
2799
2800 cleanup:
2801         kfree(bundle);
2802 }
2803
2804 static int dm_resume(void *handle)
2805 {
2806         struct amdgpu_device *adev = handle;
2807         struct drm_device *ddev = adev_to_drm(adev);
2808         struct amdgpu_display_manager *dm = &adev->dm;
2809         struct amdgpu_dm_connector *aconnector;
2810         struct drm_connector *connector;
2811         struct drm_connector_list_iter iter;
2812         struct drm_crtc *crtc;
2813         struct drm_crtc_state *new_crtc_state;
2814         struct dm_crtc_state *dm_new_crtc_state;
2815         struct drm_plane *plane;
2816         struct drm_plane_state *new_plane_state;
2817         struct dm_plane_state *dm_new_plane_state;
2818         struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
2819         enum dc_connection_type new_connection_type = dc_connection_none;
2820         struct dc_state *dc_state;
2821         int i, r, j, ret;
2822         bool need_hotplug = false;
2823
2824         if (amdgpu_in_reset(adev)) {
2825                 dc_state = dm->cached_dc_state;
2826
2827                 /*
2828                  * The dc->current_state is backed up into dm->cached_dc_state
2829                  * before we commit 0 streams.
2830                  *
2831                  * DC will clear link encoder assignments on the real state
2832                  * but the changes won't propagate over to the copy we made
2833                  * before the 0 streams commit.
2834                  *
2835                  * DC expects that link encoder assignments are *not* valid
2836                  * when committing a state, so as a workaround we can copy
2837                  * off of the current state.
2838                  *
2839                  * We lose the previous assignments, but we had already
2840                  * commit 0 streams anyway.
2841                  */
2842                 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state);
2843
2844                 r = dm_dmub_hw_init(adev);
2845                 if (r)
2846                         DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
2847
2848                 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2849                 dc_resume(dm->dc);
2850
2851                 amdgpu_dm_irq_resume_early(adev);
2852
2853                 for (i = 0; i < dc_state->stream_count; i++) {
2854                         dc_state->streams[i]->mode_changed = true;
2855                         for (j = 0; j < dc_state->stream_status[i].plane_count; j++) {
2856                                 dc_state->stream_status[i].plane_states[j]->update_flags.raw
2857                                         = 0xffffffff;
2858                         }
2859                 }
2860
2861                 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2862                         amdgpu_dm_outbox_init(adev);
2863                         dc_enable_dmub_outbox(adev->dm.dc);
2864                 }
2865
2866                 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
2867
2868                 dm_gpureset_commit_state(dm->cached_dc_state, dm);
2869
2870                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true);
2871
2872                 dc_release_state(dm->cached_dc_state);
2873                 dm->cached_dc_state = NULL;
2874
2875                 amdgpu_dm_irq_resume_late(adev);
2876
2877                 mutex_unlock(&dm->dc_lock);
2878
2879                 return 0;
2880         }
2881         /* Recreate dc_state - DC invalidates it when setting power state to S3. */
2882         dc_release_state(dm_state->context);
2883         dm_state->context = dc_create_state(dm->dc);
2884         /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
2885         dc_resource_state_construct(dm->dc, dm_state->context);
2886
2887         /* Before powering on DC we need to re-initialize DMUB. */
2888         dm_dmub_hw_resume(adev);
2889
2890         /* Re-enable outbox interrupts for DPIA. */
2891         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2892                 amdgpu_dm_outbox_init(adev);
2893                 dc_enable_dmub_outbox(adev->dm.dc);
2894         }
2895
2896         /* power on hardware */
2897         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2898
2899         /* program HPD filter */
2900         dc_resume(dm->dc);
2901
2902         /*
2903          * early enable HPD Rx IRQ, should be done before set mode as short
2904          * pulse interrupts are used for MST
2905          */
2906         amdgpu_dm_irq_resume_early(adev);
2907
2908         /* On resume we need to rewrite the MSTM control bits to enable MST*/
2909         s3_handle_mst(ddev, false);
2910
2911         /* Do detection*/
2912         drm_connector_list_iter_begin(ddev, &iter);
2913         drm_for_each_connector_iter(connector, &iter) {
2914                 aconnector = to_amdgpu_dm_connector(connector);
2915
2916                 if (!aconnector->dc_link)
2917                         continue;
2918
2919                 /*
2920                  * this is the case when traversing through already created end sink
2921                  * MST connectors, should be skipped
2922                  */
2923                 if (aconnector && aconnector->mst_root)
2924                         continue;
2925
2926                 mutex_lock(&aconnector->hpd_lock);
2927                 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
2928                         DRM_ERROR("KMS: Failed to detect connector\n");
2929
2930                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2931                         emulated_link_detect(aconnector->dc_link);
2932                 } else {
2933                         mutex_lock(&dm->dc_lock);
2934                         dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
2935                         mutex_unlock(&dm->dc_lock);
2936                 }
2937
2938                 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
2939                         aconnector->fake_enable = false;
2940
2941                 if (aconnector->dc_sink)
2942                         dc_sink_release(aconnector->dc_sink);
2943                 aconnector->dc_sink = NULL;
2944                 amdgpu_dm_update_connector_after_detect(aconnector);
2945                 mutex_unlock(&aconnector->hpd_lock);
2946         }
2947         drm_connector_list_iter_end(&iter);
2948
2949         /* Force mode set in atomic commit */
2950         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
2951                 new_crtc_state->active_changed = true;
2952
2953         /*
2954          * atomic_check is expected to create the dc states. We need to release
2955          * them here, since they were duplicated as part of the suspend
2956          * procedure.
2957          */
2958         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
2959                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
2960                 if (dm_new_crtc_state->stream) {
2961                         WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
2962                         dc_stream_release(dm_new_crtc_state->stream);
2963                         dm_new_crtc_state->stream = NULL;
2964                 }
2965         }
2966
2967         for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
2968                 dm_new_plane_state = to_dm_plane_state(new_plane_state);
2969                 if (dm_new_plane_state->dc_state) {
2970                         WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
2971                         dc_plane_state_release(dm_new_plane_state->dc_state);
2972                         dm_new_plane_state->dc_state = NULL;
2973                 }
2974         }
2975
2976         drm_atomic_helper_resume(ddev, dm->cached_state);
2977
2978         dm->cached_state = NULL;
2979
2980         /* Do mst topology probing after resuming cached state*/
2981         drm_connector_list_iter_begin(ddev, &iter);
2982         drm_for_each_connector_iter(connector, &iter) {
2983                 aconnector = to_amdgpu_dm_connector(connector);
2984                 if (aconnector->dc_link->type != dc_connection_mst_branch ||
2985                     aconnector->mst_root)
2986                         continue;
2987
2988                 ret = drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr, true);
2989
2990                 if (ret < 0) {
2991                         dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2992                                         aconnector->dc_link);
2993                         need_hotplug = true;
2994                 }
2995         }
2996         drm_connector_list_iter_end(&iter);
2997
2998         if (need_hotplug)
2999                 drm_kms_helper_hotplug_event(ddev);
3000
3001         amdgpu_dm_irq_resume_late(adev);
3002
3003         amdgpu_dm_smu_write_watermarks_table(adev);
3004
3005         return 0;
3006 }
3007
3008 /**
3009  * DOC: DM Lifecycle
3010  *
3011  * DM (and consequently DC) is registered in the amdgpu base driver as a IP
3012  * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
3013  * the base driver's device list to be initialized and torn down accordingly.
3014  *
3015  * The functions to do so are provided as hooks in &struct amd_ip_funcs.
3016  */
3017
3018 static const struct amd_ip_funcs amdgpu_dm_funcs = {
3019         .name = "dm",
3020         .early_init = dm_early_init,
3021         .late_init = dm_late_init,
3022         .sw_init = dm_sw_init,
3023         .sw_fini = dm_sw_fini,
3024         .early_fini = amdgpu_dm_early_fini,
3025         .hw_init = dm_hw_init,
3026         .hw_fini = dm_hw_fini,
3027         .suspend = dm_suspend,
3028         .resume = dm_resume,
3029         .is_idle = dm_is_idle,
3030         .wait_for_idle = dm_wait_for_idle,
3031         .check_soft_reset = dm_check_soft_reset,
3032         .soft_reset = dm_soft_reset,
3033         .set_clockgating_state = dm_set_clockgating_state,
3034         .set_powergating_state = dm_set_powergating_state,
3035 };
3036
3037 const struct amdgpu_ip_block_version dm_ip_block = {
3038         .type = AMD_IP_BLOCK_TYPE_DCE,
3039         .major = 1,
3040         .minor = 0,
3041         .rev = 0,
3042         .funcs = &amdgpu_dm_funcs,
3043 };
3044
3045
3046 /**
3047  * DOC: atomic
3048  *
3049  * *WIP*
3050  */
3051
3052 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
3053         .fb_create = amdgpu_display_user_framebuffer_create,
3054         .get_format_info = amdgpu_dm_plane_get_format_info,
3055         .atomic_check = amdgpu_dm_atomic_check,
3056         .atomic_commit = drm_atomic_helper_commit,
3057 };
3058
3059 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
3060         .atomic_commit_tail = amdgpu_dm_atomic_commit_tail,
3061         .atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
3062 };
3063
3064 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
3065 {
3066         struct amdgpu_dm_backlight_caps *caps;
3067         struct drm_connector *conn_base;
3068         struct amdgpu_device *adev;
3069         struct drm_luminance_range_info *luminance_range;
3070
3071         if (aconnector->bl_idx == -1 ||
3072             aconnector->dc_link->connector_signal != SIGNAL_TYPE_EDP)
3073                 return;
3074
3075         conn_base = &aconnector->base;
3076         adev = drm_to_adev(conn_base->dev);
3077
3078         caps = &adev->dm.backlight_caps[aconnector->bl_idx];
3079         caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
3080         caps->aux_support = false;
3081
3082         if (caps->ext_caps->bits.oled == 1
3083             /*
3084              * ||
3085              * caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
3086              * caps->ext_caps->bits.hdr_aux_backlight_control == 1
3087              */)
3088                 caps->aux_support = true;
3089
3090         if (amdgpu_backlight == 0)
3091                 caps->aux_support = false;
3092         else if (amdgpu_backlight == 1)
3093                 caps->aux_support = true;
3094
3095         luminance_range = &conn_base->display_info.luminance_range;
3096
3097         if (luminance_range->max_luminance) {
3098                 caps->aux_min_input_signal = luminance_range->min_luminance;
3099                 caps->aux_max_input_signal = luminance_range->max_luminance;
3100         } else {
3101                 caps->aux_min_input_signal = 0;
3102                 caps->aux_max_input_signal = 512;
3103         }
3104 }
3105
3106 void amdgpu_dm_update_connector_after_detect(
3107                 struct amdgpu_dm_connector *aconnector)
3108 {
3109         struct drm_connector *connector = &aconnector->base;
3110         struct drm_device *dev = connector->dev;
3111         struct dc_sink *sink;
3112
3113         /* MST handled by drm_mst framework */
3114         if (aconnector->mst_mgr.mst_state == true)
3115                 return;
3116
3117         sink = aconnector->dc_link->local_sink;
3118         if (sink)
3119                 dc_sink_retain(sink);
3120
3121         /*
3122          * Edid mgmt connector gets first update only in mode_valid hook and then
3123          * the connector sink is set to either fake or physical sink depends on link status.
3124          * Skip if already done during boot.
3125          */
3126         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
3127                         && aconnector->dc_em_sink) {
3128
3129                 /*
3130                  * For S3 resume with headless use eml_sink to fake stream
3131                  * because on resume connector->sink is set to NULL
3132                  */
3133                 mutex_lock(&dev->mode_config.mutex);
3134
3135                 if (sink) {
3136                         if (aconnector->dc_sink) {
3137                                 amdgpu_dm_update_freesync_caps(connector, NULL);
3138                                 /*
3139                                  * retain and release below are used to
3140                                  * bump up refcount for sink because the link doesn't point
3141                                  * to it anymore after disconnect, so on next crtc to connector
3142                                  * reshuffle by UMD we will get into unwanted dc_sink release
3143                                  */
3144                                 dc_sink_release(aconnector->dc_sink);
3145                         }
3146                         aconnector->dc_sink = sink;
3147                         dc_sink_retain(aconnector->dc_sink);
3148                         amdgpu_dm_update_freesync_caps(connector,
3149                                         aconnector->edid);
3150                 } else {
3151                         amdgpu_dm_update_freesync_caps(connector, NULL);
3152                         if (!aconnector->dc_sink) {
3153                                 aconnector->dc_sink = aconnector->dc_em_sink;
3154                                 dc_sink_retain(aconnector->dc_sink);
3155                         }
3156                 }
3157
3158                 mutex_unlock(&dev->mode_config.mutex);
3159
3160                 if (sink)
3161                         dc_sink_release(sink);
3162                 return;
3163         }
3164
3165         /*
3166          * TODO: temporary guard to look for proper fix
3167          * if this sink is MST sink, we should not do anything
3168          */
3169         if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3170                 dc_sink_release(sink);
3171                 return;
3172         }
3173
3174         if (aconnector->dc_sink == sink) {
3175                 /*
3176                  * We got a DP short pulse (Link Loss, DP CTS, etc...).
3177                  * Do nothing!!
3178                  */
3179                 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
3180                                 aconnector->connector_id);
3181                 if (sink)
3182                         dc_sink_release(sink);
3183                 return;
3184         }
3185
3186         DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
3187                 aconnector->connector_id, aconnector->dc_sink, sink);
3188
3189         mutex_lock(&dev->mode_config.mutex);
3190
3191         /*
3192          * 1. Update status of the drm connector
3193          * 2. Send an event and let userspace tell us what to do
3194          */
3195         if (sink) {
3196                 /*
3197                  * TODO: check if we still need the S3 mode update workaround.
3198                  * If yes, put it here.
3199                  */
3200                 if (aconnector->dc_sink) {
3201                         amdgpu_dm_update_freesync_caps(connector, NULL);
3202                         dc_sink_release(aconnector->dc_sink);
3203                 }
3204
3205                 aconnector->dc_sink = sink;
3206                 dc_sink_retain(aconnector->dc_sink);
3207                 if (sink->dc_edid.length == 0) {
3208                         aconnector->edid = NULL;
3209                         if (aconnector->dc_link->aux_mode) {
3210                                 drm_dp_cec_unset_edid(
3211                                         &aconnector->dm_dp_aux.aux);
3212                         }
3213                 } else {
3214                         aconnector->edid =
3215                                 (struct edid *)sink->dc_edid.raw_edid;
3216
3217                         if (aconnector->dc_link->aux_mode)
3218                                 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
3219                                                     aconnector->edid);
3220                 }
3221
3222                 if (!aconnector->timing_requested) {
3223                         aconnector->timing_requested =
3224                                 kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL);
3225                         if (!aconnector->timing_requested)
3226                                 dm_error("failed to create aconnector->requested_timing\n");
3227                 }
3228
3229                 drm_connector_update_edid_property(connector, aconnector->edid);
3230                 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
3231                 update_connector_ext_caps(aconnector);
3232         } else {
3233                 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
3234                 amdgpu_dm_update_freesync_caps(connector, NULL);
3235                 drm_connector_update_edid_property(connector, NULL);
3236                 aconnector->num_modes = 0;
3237                 dc_sink_release(aconnector->dc_sink);
3238                 aconnector->dc_sink = NULL;
3239                 aconnector->edid = NULL;
3240                 kfree(aconnector->timing_requested);
3241                 aconnector->timing_requested = NULL;
3242                 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
3243                 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
3244                         connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
3245         }
3246
3247         mutex_unlock(&dev->mode_config.mutex);
3248
3249         update_subconnector_property(aconnector);
3250
3251         if (sink)
3252                 dc_sink_release(sink);
3253 }
3254
3255 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)
3256 {
3257         struct drm_connector *connector = &aconnector->base;
3258         struct drm_device *dev = connector->dev;
3259         enum dc_connection_type new_connection_type = dc_connection_none;
3260         struct amdgpu_device *adev = drm_to_adev(dev);
3261         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
3262         bool ret = false;
3263
3264         if (adev->dm.disable_hpd_irq)
3265                 return;
3266
3267         /*
3268          * In case of failure or MST no need to update connector status or notify the OS
3269          * since (for MST case) MST does this in its own context.
3270          */
3271         mutex_lock(&aconnector->hpd_lock);
3272
3273         if (adev->dm.hdcp_workqueue) {
3274                 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
3275                 dm_con_state->update_hdcp = true;
3276         }
3277         if (aconnector->fake_enable)
3278                 aconnector->fake_enable = false;
3279
3280         aconnector->timing_changed = false;
3281
3282         if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
3283                 DRM_ERROR("KMS: Failed to detect connector\n");
3284
3285         if (aconnector->base.force && new_connection_type == dc_connection_none) {
3286                 emulated_link_detect(aconnector->dc_link);
3287
3288                 drm_modeset_lock_all(dev);
3289                 dm_restore_drm_connector_state(dev, connector);
3290                 drm_modeset_unlock_all(dev);
3291
3292                 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3293                         drm_kms_helper_connector_hotplug_event(connector);
3294         } else {
3295                 mutex_lock(&adev->dm.dc_lock);
3296                 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3297                 mutex_unlock(&adev->dm.dc_lock);
3298                 if (ret) {
3299                         amdgpu_dm_update_connector_after_detect(aconnector);
3300
3301                         drm_modeset_lock_all(dev);
3302                         dm_restore_drm_connector_state(dev, connector);
3303                         drm_modeset_unlock_all(dev);
3304
3305                         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3306                                 drm_kms_helper_connector_hotplug_event(connector);
3307                 }
3308         }
3309         mutex_unlock(&aconnector->hpd_lock);
3310
3311 }
3312
3313 static void handle_hpd_irq(void *param)
3314 {
3315         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3316
3317         handle_hpd_irq_helper(aconnector);
3318
3319 }
3320
3321 static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq,
3322                                                         union hpd_irq_data hpd_irq_data)
3323 {
3324         struct hpd_rx_irq_offload_work *offload_work =
3325                                 kzalloc(sizeof(*offload_work), GFP_KERNEL);
3326
3327         if (!offload_work) {
3328                 DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n");
3329                 return;
3330         }
3331
3332         INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work);
3333         offload_work->data = hpd_irq_data;
3334         offload_work->offload_wq = offload_wq;
3335
3336         queue_work(offload_wq->wq, &offload_work->work);
3337         DRM_DEBUG_KMS("queue work to handle hpd_rx offload work");
3338 }
3339
3340 static void handle_hpd_rx_irq(void *param)
3341 {
3342         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3343         struct drm_connector *connector = &aconnector->base;
3344         struct drm_device *dev = connector->dev;
3345         struct dc_link *dc_link = aconnector->dc_link;
3346         bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
3347         bool result = false;
3348         enum dc_connection_type new_connection_type = dc_connection_none;
3349         struct amdgpu_device *adev = drm_to_adev(dev);
3350         union hpd_irq_data hpd_irq_data;
3351         bool link_loss = false;
3352         bool has_left_work = false;
3353         int idx = dc_link->link_index;
3354         struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx];
3355
3356         memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
3357
3358         if (adev->dm.disable_hpd_irq)
3359                 return;
3360
3361         /*
3362          * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
3363          * conflict, after implement i2c helper, this mutex should be
3364          * retired.
3365          */
3366         mutex_lock(&aconnector->hpd_lock);
3367
3368         result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data,
3369                                                 &link_loss, true, &has_left_work);
3370
3371         if (!has_left_work)
3372                 goto out;
3373
3374         if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3375                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3376                 goto out;
3377         }
3378
3379         if (dc_link_dp_allow_hpd_rx_irq(dc_link)) {
3380                 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
3381                         hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
3382                         bool skip = false;
3383
3384                         /*
3385                          * DOWN_REP_MSG_RDY is also handled by polling method
3386                          * mgr->cbs->poll_hpd_irq()
3387                          */
3388                         spin_lock(&offload_wq->offload_lock);
3389                         skip = offload_wq->is_handling_mst_msg_rdy_event;
3390
3391                         if (!skip)
3392                                 offload_wq->is_handling_mst_msg_rdy_event = true;
3393
3394                         spin_unlock(&offload_wq->offload_lock);
3395
3396                         if (!skip)
3397                                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3398
3399                         goto out;
3400                 }
3401
3402                 if (link_loss) {
3403                         bool skip = false;
3404
3405                         spin_lock(&offload_wq->offload_lock);
3406                         skip = offload_wq->is_handling_link_loss;
3407
3408                         if (!skip)
3409                                 offload_wq->is_handling_link_loss = true;
3410
3411                         spin_unlock(&offload_wq->offload_lock);
3412
3413                         if (!skip)
3414                                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3415
3416                         goto out;
3417                 }
3418         }
3419
3420 out:
3421         if (result && !is_mst_root_connector) {
3422                 /* Downstream Port status changed. */
3423                 if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
3424                         DRM_ERROR("KMS: Failed to detect connector\n");
3425
3426                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3427                         emulated_link_detect(dc_link);
3428
3429                         if (aconnector->fake_enable)
3430                                 aconnector->fake_enable = false;
3431
3432                         amdgpu_dm_update_connector_after_detect(aconnector);
3433
3434
3435                         drm_modeset_lock_all(dev);
3436                         dm_restore_drm_connector_state(dev, connector);
3437                         drm_modeset_unlock_all(dev);
3438
3439                         drm_kms_helper_connector_hotplug_event(connector);
3440                 } else {
3441                         bool ret = false;
3442
3443                         mutex_lock(&adev->dm.dc_lock);
3444                         ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX);
3445                         mutex_unlock(&adev->dm.dc_lock);
3446
3447                         if (ret) {
3448                                 if (aconnector->fake_enable)
3449                                         aconnector->fake_enable = false;
3450
3451                                 amdgpu_dm_update_connector_after_detect(aconnector);
3452
3453                                 drm_modeset_lock_all(dev);
3454                                 dm_restore_drm_connector_state(dev, connector);
3455                                 drm_modeset_unlock_all(dev);
3456
3457                                 drm_kms_helper_connector_hotplug_event(connector);
3458                         }
3459                 }
3460         }
3461         if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
3462                 if (adev->dm.hdcp_workqueue)
3463                         hdcp_handle_cpirq(adev->dm.hdcp_workqueue,  aconnector->base.index);
3464         }
3465
3466         if (dc_link->type != dc_connection_mst_branch)
3467                 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
3468
3469         mutex_unlock(&aconnector->hpd_lock);
3470 }
3471
3472 static void register_hpd_handlers(struct amdgpu_device *adev)
3473 {
3474         struct drm_device *dev = adev_to_drm(adev);
3475         struct drm_connector *connector;
3476         struct amdgpu_dm_connector *aconnector;
3477         const struct dc_link *dc_link;
3478         struct dc_interrupt_params int_params = {0};
3479
3480         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3481         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3482
3483         list_for_each_entry(connector,
3484                         &dev->mode_config.connector_list, head) {
3485
3486                 aconnector = to_amdgpu_dm_connector(connector);
3487                 dc_link = aconnector->dc_link;
3488
3489                 if (dc_link->irq_source_hpd != DC_IRQ_SOURCE_INVALID) {
3490                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3491                         int_params.irq_source = dc_link->irq_source_hpd;
3492
3493                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
3494                                         handle_hpd_irq,
3495                                         (void *) aconnector);
3496                 }
3497
3498                 if (dc_link->irq_source_hpd_rx != DC_IRQ_SOURCE_INVALID) {
3499
3500                         /* Also register for DP short pulse (hpd_rx). */
3501                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3502                         int_params.irq_source = dc_link->irq_source_hpd_rx;
3503
3504                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
3505                                         handle_hpd_rx_irq,
3506                                         (void *) aconnector);
3507                 }
3508
3509                 if (adev->dm.hpd_rx_offload_wq)
3510                         adev->dm.hpd_rx_offload_wq[connector->index].aconnector =
3511                                 aconnector;
3512         }
3513 }
3514
3515 #if defined(CONFIG_DRM_AMD_DC_SI)
3516 /* Register IRQ sources and initialize IRQ callbacks */
3517 static int dce60_register_irq_handlers(struct amdgpu_device *adev)
3518 {
3519         struct dc *dc = adev->dm.dc;
3520         struct common_irq_params *c_irq_params;
3521         struct dc_interrupt_params int_params = {0};
3522         int r;
3523         int i;
3524         unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3525
3526         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3527         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3528
3529         /*
3530          * Actions of amdgpu_irq_add_id():
3531          * 1. Register a set() function with base driver.
3532          *    Base driver will call set() function to enable/disable an
3533          *    interrupt in DC hardware.
3534          * 2. Register amdgpu_dm_irq_handler().
3535          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3536          *    coming from DC hardware.
3537          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3538          *    for acknowledging and handling.
3539          */
3540
3541         /* Use VBLANK interrupt */
3542         for (i = 0; i < adev->mode_info.num_crtc; i++) {
3543                 r = amdgpu_irq_add_id(adev, client_id, i + 1, &adev->crtc_irq);
3544                 if (r) {
3545                         DRM_ERROR("Failed to add crtc irq id!\n");
3546                         return r;
3547                 }
3548
3549                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3550                 int_params.irq_source =
3551                         dc_interrupt_to_irq_source(dc, i + 1, 0);
3552
3553                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3554
3555                 c_irq_params->adev = adev;
3556                 c_irq_params->irq_src = int_params.irq_source;
3557
3558                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3559                                 dm_crtc_high_irq, c_irq_params);
3560         }
3561
3562         /* Use GRPH_PFLIP interrupt */
3563         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3564                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3565                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3566                 if (r) {
3567                         DRM_ERROR("Failed to add page flip irq id!\n");
3568                         return r;
3569                 }
3570
3571                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3572                 int_params.irq_source =
3573                         dc_interrupt_to_irq_source(dc, i, 0);
3574
3575                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3576
3577                 c_irq_params->adev = adev;
3578                 c_irq_params->irq_src = int_params.irq_source;
3579
3580                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3581                                 dm_pflip_high_irq, c_irq_params);
3582
3583         }
3584
3585         /* HPD */
3586         r = amdgpu_irq_add_id(adev, client_id,
3587                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3588         if (r) {
3589                 DRM_ERROR("Failed to add hpd irq id!\n");
3590                 return r;
3591         }
3592
3593         register_hpd_handlers(adev);
3594
3595         return 0;
3596 }
3597 #endif
3598
3599 /* Register IRQ sources and initialize IRQ callbacks */
3600 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
3601 {
3602         struct dc *dc = adev->dm.dc;
3603         struct common_irq_params *c_irq_params;
3604         struct dc_interrupt_params int_params = {0};
3605         int r;
3606         int i;
3607         unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3608
3609         if (adev->family >= AMDGPU_FAMILY_AI)
3610                 client_id = SOC15_IH_CLIENTID_DCE;
3611
3612         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3613         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3614
3615         /*
3616          * Actions of amdgpu_irq_add_id():
3617          * 1. Register a set() function with base driver.
3618          *    Base driver will call set() function to enable/disable an
3619          *    interrupt in DC hardware.
3620          * 2. Register amdgpu_dm_irq_handler().
3621          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3622          *    coming from DC hardware.
3623          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3624          *    for acknowledging and handling.
3625          */
3626
3627         /* Use VBLANK interrupt */
3628         for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
3629                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
3630                 if (r) {
3631                         DRM_ERROR("Failed to add crtc irq id!\n");
3632                         return r;
3633                 }
3634
3635                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3636                 int_params.irq_source =
3637                         dc_interrupt_to_irq_source(dc, i, 0);
3638
3639                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3640
3641                 c_irq_params->adev = adev;
3642                 c_irq_params->irq_src = int_params.irq_source;
3643
3644                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3645                                 dm_crtc_high_irq, c_irq_params);
3646         }
3647
3648         /* Use VUPDATE interrupt */
3649         for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
3650                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
3651                 if (r) {
3652                         DRM_ERROR("Failed to add vupdate irq id!\n");
3653                         return r;
3654                 }
3655
3656                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3657                 int_params.irq_source =
3658                         dc_interrupt_to_irq_source(dc, i, 0);
3659
3660                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3661
3662                 c_irq_params->adev = adev;
3663                 c_irq_params->irq_src = int_params.irq_source;
3664
3665                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3666                                 dm_vupdate_high_irq, c_irq_params);
3667         }
3668
3669         /* Use GRPH_PFLIP interrupt */
3670         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3671                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3672                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3673                 if (r) {
3674                         DRM_ERROR("Failed to add page flip irq id!\n");
3675                         return r;
3676                 }
3677
3678                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3679                 int_params.irq_source =
3680                         dc_interrupt_to_irq_source(dc, i, 0);
3681
3682                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3683
3684                 c_irq_params->adev = adev;
3685                 c_irq_params->irq_src = int_params.irq_source;
3686
3687                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3688                                 dm_pflip_high_irq, c_irq_params);
3689
3690         }
3691
3692         /* HPD */
3693         r = amdgpu_irq_add_id(adev, client_id,
3694                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3695         if (r) {
3696                 DRM_ERROR("Failed to add hpd irq id!\n");
3697                 return r;
3698         }
3699
3700         register_hpd_handlers(adev);
3701
3702         return 0;
3703 }
3704
3705 /* Register IRQ sources and initialize IRQ callbacks */
3706 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
3707 {
3708         struct dc *dc = adev->dm.dc;
3709         struct common_irq_params *c_irq_params;
3710         struct dc_interrupt_params int_params = {0};
3711         int r;
3712         int i;
3713 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3714         static const unsigned int vrtl_int_srcid[] = {
3715                 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL,
3716                 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL,
3717                 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL,
3718                 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL,
3719                 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL,
3720                 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL
3721         };
3722 #endif
3723
3724         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3725         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3726
3727         /*
3728          * Actions of amdgpu_irq_add_id():
3729          * 1. Register a set() function with base driver.
3730          *    Base driver will call set() function to enable/disable an
3731          *    interrupt in DC hardware.
3732          * 2. Register amdgpu_dm_irq_handler().
3733          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3734          *    coming from DC hardware.
3735          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3736          *    for acknowledging and handling.
3737          */
3738
3739         /* Use VSTARTUP interrupt */
3740         for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
3741                         i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
3742                         i++) {
3743                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
3744
3745                 if (r) {
3746                         DRM_ERROR("Failed to add crtc irq id!\n");
3747                         return r;
3748                 }
3749
3750                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3751                 int_params.irq_source =
3752                         dc_interrupt_to_irq_source(dc, i, 0);
3753
3754                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3755
3756                 c_irq_params->adev = adev;
3757                 c_irq_params->irq_src = int_params.irq_source;
3758
3759                 amdgpu_dm_irq_register_interrupt(
3760                         adev, &int_params, dm_crtc_high_irq, c_irq_params);
3761         }
3762
3763         /* Use otg vertical line interrupt */
3764 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3765         for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) {
3766                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE,
3767                                 vrtl_int_srcid[i], &adev->vline0_irq);
3768
3769                 if (r) {
3770                         DRM_ERROR("Failed to add vline0 irq id!\n");
3771                         return r;
3772                 }
3773
3774                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3775                 int_params.irq_source =
3776                         dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0);
3777
3778                 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) {
3779                         DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]);
3780                         break;
3781                 }
3782
3783                 c_irq_params = &adev->dm.vline0_params[int_params.irq_source
3784                                         - DC_IRQ_SOURCE_DC1_VLINE0];
3785
3786                 c_irq_params->adev = adev;
3787                 c_irq_params->irq_src = int_params.irq_source;
3788
3789                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3790                                 dm_dcn_vertical_interrupt0_high_irq, c_irq_params);
3791         }
3792 #endif
3793
3794         /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
3795          * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
3796          * to trigger at end of each vblank, regardless of state of the lock,
3797          * matching DCE behaviour.
3798          */
3799         for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
3800              i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
3801              i++) {
3802                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
3803
3804                 if (r) {
3805                         DRM_ERROR("Failed to add vupdate irq id!\n");
3806                         return r;
3807                 }
3808
3809                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3810                 int_params.irq_source =
3811                         dc_interrupt_to_irq_source(dc, i, 0);
3812
3813                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3814
3815                 c_irq_params->adev = adev;
3816                 c_irq_params->irq_src = int_params.irq_source;
3817
3818                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3819                                 dm_vupdate_high_irq, c_irq_params);
3820         }
3821
3822         /* Use GRPH_PFLIP interrupt */
3823         for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
3824                         i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1;
3825                         i++) {
3826                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
3827                 if (r) {
3828                         DRM_ERROR("Failed to add page flip irq id!\n");
3829                         return r;
3830                 }
3831
3832                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3833                 int_params.irq_source =
3834                         dc_interrupt_to_irq_source(dc, i, 0);
3835
3836                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3837
3838                 c_irq_params->adev = adev;
3839                 c_irq_params->irq_src = int_params.irq_source;
3840
3841                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3842                                 dm_pflip_high_irq, c_irq_params);
3843
3844         }
3845
3846         /* HPD */
3847         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
3848                         &adev->hpd_irq);
3849         if (r) {
3850                 DRM_ERROR("Failed to add hpd irq id!\n");
3851                 return r;
3852         }
3853
3854         register_hpd_handlers(adev);
3855
3856         return 0;
3857 }
3858 /* Register Outbox IRQ sources and initialize IRQ callbacks */
3859 static int register_outbox_irq_handlers(struct amdgpu_device *adev)
3860 {
3861         struct dc *dc = adev->dm.dc;
3862         struct common_irq_params *c_irq_params;
3863         struct dc_interrupt_params int_params = {0};
3864         int r, i;
3865
3866         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3867         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3868
3869         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT,
3870                         &adev->dmub_outbox_irq);
3871         if (r) {
3872                 DRM_ERROR("Failed to add outbox irq id!\n");
3873                 return r;
3874         }
3875
3876         if (dc->ctx->dmub_srv) {
3877                 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT;
3878                 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3879                 int_params.irq_source =
3880                 dc_interrupt_to_irq_source(dc, i, 0);
3881
3882                 c_irq_params = &adev->dm.dmub_outbox_params[0];
3883
3884                 c_irq_params->adev = adev;
3885                 c_irq_params->irq_src = int_params.irq_source;
3886
3887                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3888                                 dm_dmub_outbox1_low_irq, c_irq_params);
3889         }
3890
3891         return 0;
3892 }
3893
3894 /*
3895  * Acquires the lock for the atomic state object and returns
3896  * the new atomic state.
3897  *
3898  * This should only be called during atomic check.
3899  */
3900 int dm_atomic_get_state(struct drm_atomic_state *state,
3901                         struct dm_atomic_state **dm_state)
3902 {
3903         struct drm_device *dev = state->dev;
3904         struct amdgpu_device *adev = drm_to_adev(dev);
3905         struct amdgpu_display_manager *dm = &adev->dm;
3906         struct drm_private_state *priv_state;
3907
3908         if (*dm_state)
3909                 return 0;
3910
3911         priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
3912         if (IS_ERR(priv_state))
3913                 return PTR_ERR(priv_state);
3914
3915         *dm_state = to_dm_atomic_state(priv_state);
3916
3917         return 0;
3918 }
3919
3920 static struct dm_atomic_state *
3921 dm_atomic_get_new_state(struct drm_atomic_state *state)
3922 {
3923         struct drm_device *dev = state->dev;
3924         struct amdgpu_device *adev = drm_to_adev(dev);
3925         struct amdgpu_display_manager *dm = &adev->dm;
3926         struct drm_private_obj *obj;
3927         struct drm_private_state *new_obj_state;
3928         int i;
3929
3930         for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
3931                 if (obj->funcs == dm->atomic_obj.funcs)
3932                         return to_dm_atomic_state(new_obj_state);
3933         }
3934
3935         return NULL;
3936 }
3937
3938 static struct drm_private_state *
3939 dm_atomic_duplicate_state(struct drm_private_obj *obj)
3940 {
3941         struct dm_atomic_state *old_state, *new_state;
3942
3943         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
3944         if (!new_state)
3945                 return NULL;
3946
3947         __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
3948
3949         old_state = to_dm_atomic_state(obj->state);
3950
3951         if (old_state && old_state->context)
3952                 new_state->context = dc_copy_state(old_state->context);
3953
3954         if (!new_state->context) {
3955                 kfree(new_state);
3956                 return NULL;
3957         }
3958
3959         return &new_state->base;
3960 }
3961
3962 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
3963                                     struct drm_private_state *state)
3964 {
3965         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
3966
3967         if (dm_state && dm_state->context)
3968                 dc_release_state(dm_state->context);
3969
3970         kfree(dm_state);
3971 }
3972
3973 static struct drm_private_state_funcs dm_atomic_state_funcs = {
3974         .atomic_duplicate_state = dm_atomic_duplicate_state,
3975         .atomic_destroy_state = dm_atomic_destroy_state,
3976 };
3977
3978 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
3979 {
3980         struct dm_atomic_state *state;
3981         int r;
3982
3983         adev->mode_info.mode_config_initialized = true;
3984
3985         adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
3986         adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
3987
3988         adev_to_drm(adev)->mode_config.max_width = 16384;
3989         adev_to_drm(adev)->mode_config.max_height = 16384;
3990
3991         adev_to_drm(adev)->mode_config.preferred_depth = 24;
3992         if (adev->asic_type == CHIP_HAWAII)
3993                 /* disable prefer shadow for now due to hibernation issues */
3994                 adev_to_drm(adev)->mode_config.prefer_shadow = 0;
3995         else
3996                 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
3997         /* indicates support for immediate flip */
3998         adev_to_drm(adev)->mode_config.async_page_flip = true;
3999
4000         state = kzalloc(sizeof(*state), GFP_KERNEL);
4001         if (!state)
4002                 return -ENOMEM;
4003
4004         state->context = dc_create_state(adev->dm.dc);
4005         if (!state->context) {
4006                 kfree(state);
4007                 return -ENOMEM;
4008         }
4009
4010         dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
4011
4012         drm_atomic_private_obj_init(adev_to_drm(adev),
4013                                     &adev->dm.atomic_obj,
4014                                     &state->base,
4015                                     &dm_atomic_state_funcs);
4016
4017         r = amdgpu_display_modeset_create_props(adev);
4018         if (r) {
4019                 dc_release_state(state->context);
4020                 kfree(state);
4021                 return r;
4022         }
4023
4024         r = amdgpu_dm_audio_init(adev);
4025         if (r) {
4026                 dc_release_state(state->context);
4027                 kfree(state);
4028                 return r;
4029         }
4030
4031         return 0;
4032 }
4033
4034 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
4035 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
4036 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
4037
4038 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
4039                                             int bl_idx)
4040 {
4041 #if defined(CONFIG_ACPI)
4042         struct amdgpu_dm_backlight_caps caps;
4043
4044         memset(&caps, 0, sizeof(caps));
4045
4046         if (dm->backlight_caps[bl_idx].caps_valid)
4047                 return;
4048
4049         amdgpu_acpi_get_backlight_caps(&caps);
4050         if (caps.caps_valid) {
4051                 dm->backlight_caps[bl_idx].caps_valid = true;
4052                 if (caps.aux_support)
4053                         return;
4054                 dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal;
4055                 dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal;
4056         } else {
4057                 dm->backlight_caps[bl_idx].min_input_signal =
4058                                 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4059                 dm->backlight_caps[bl_idx].max_input_signal =
4060                                 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4061         }
4062 #else
4063         if (dm->backlight_caps[bl_idx].aux_support)
4064                 return;
4065
4066         dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4067         dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4068 #endif
4069 }
4070
4071 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
4072                                 unsigned int *min, unsigned int *max)
4073 {
4074         if (!caps)
4075                 return 0;
4076
4077         if (caps->aux_support) {
4078                 // Firmware limits are in nits, DC API wants millinits.
4079                 *max = 1000 * caps->aux_max_input_signal;
4080                 *min = 1000 * caps->aux_min_input_signal;
4081         } else {
4082                 // Firmware limits are 8-bit, PWM control is 16-bit.
4083                 *max = 0x101 * caps->max_input_signal;
4084                 *min = 0x101 * caps->min_input_signal;
4085         }
4086         return 1;
4087 }
4088
4089 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
4090                                         uint32_t brightness)
4091 {
4092         unsigned int min, max;
4093
4094         if (!get_brightness_range(caps, &min, &max))
4095                 return brightness;
4096
4097         // Rescale 0..255 to min..max
4098         return min + DIV_ROUND_CLOSEST((max - min) * brightness,
4099                                        AMDGPU_MAX_BL_LEVEL);
4100 }
4101
4102 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
4103                                       uint32_t brightness)
4104 {
4105         unsigned int min, max;
4106
4107         if (!get_brightness_range(caps, &min, &max))
4108                 return brightness;
4109
4110         if (brightness < min)
4111                 return 0;
4112         // Rescale min..max to 0..255
4113         return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),
4114                                  max - min);
4115 }
4116
4117 static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
4118                                          int bl_idx,
4119                                          u32 user_brightness)
4120 {
4121         struct amdgpu_dm_backlight_caps caps;
4122         struct dc_link *link;
4123         u32 brightness;
4124         bool rc;
4125
4126         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4127         caps = dm->backlight_caps[bl_idx];
4128
4129         dm->brightness[bl_idx] = user_brightness;
4130         /* update scratch register */
4131         if (bl_idx == 0)
4132                 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]);
4133         brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]);
4134         link = (struct dc_link *)dm->backlight_link[bl_idx];
4135
4136         /* Change brightness based on AUX property */
4137         if (caps.aux_support) {
4138                 rc = dc_link_set_backlight_level_nits(link, true, brightness,
4139                                                       AUX_BL_DEFAULT_TRANSITION_TIME_MS);
4140                 if (!rc)
4141                         DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx);
4142         } else {
4143                 rc = dc_link_set_backlight_level(link, brightness, 0);
4144                 if (!rc)
4145                         DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx);
4146         }
4147
4148         if (rc)
4149                 dm->actual_brightness[bl_idx] = user_brightness;
4150 }
4151
4152 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
4153 {
4154         struct amdgpu_display_manager *dm = bl_get_data(bd);
4155         int i;
4156
4157         for (i = 0; i < dm->num_of_edps; i++) {
4158                 if (bd == dm->backlight_dev[i])
4159                         break;
4160         }
4161         if (i >= AMDGPU_DM_MAX_NUM_EDP)
4162                 i = 0;
4163         amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness);
4164
4165         return 0;
4166 }
4167
4168 static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm,
4169                                          int bl_idx)
4170 {
4171         int ret;
4172         struct amdgpu_dm_backlight_caps caps;
4173         struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx];
4174
4175         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4176         caps = dm->backlight_caps[bl_idx];
4177
4178         if (caps.aux_support) {
4179                 u32 avg, peak;
4180                 bool rc;
4181
4182                 rc = dc_link_get_backlight_level_nits(link, &avg, &peak);
4183                 if (!rc)
4184                         return dm->brightness[bl_idx];
4185                 return convert_brightness_to_user(&caps, avg);
4186         }
4187
4188         ret = dc_link_get_backlight_level(link);
4189
4190         if (ret == DC_ERROR_UNEXPECTED)
4191                 return dm->brightness[bl_idx];
4192
4193         return convert_brightness_to_user(&caps, ret);
4194 }
4195
4196 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
4197 {
4198         struct amdgpu_display_manager *dm = bl_get_data(bd);
4199         int i;
4200
4201         for (i = 0; i < dm->num_of_edps; i++) {
4202                 if (bd == dm->backlight_dev[i])
4203                         break;
4204         }
4205         if (i >= AMDGPU_DM_MAX_NUM_EDP)
4206                 i = 0;
4207         return amdgpu_dm_backlight_get_level(dm, i);
4208 }
4209
4210 static const struct backlight_ops amdgpu_dm_backlight_ops = {
4211         .options = BL_CORE_SUSPENDRESUME,
4212         .get_brightness = amdgpu_dm_backlight_get_brightness,
4213         .update_status  = amdgpu_dm_backlight_update_status,
4214 };
4215
4216 static void
4217 amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector)
4218 {
4219         struct drm_device *drm = aconnector->base.dev;
4220         struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm;
4221         struct backlight_properties props = { 0 };
4222         char bl_name[16];
4223
4224         if (aconnector->bl_idx == -1)
4225                 return;
4226
4227         if (!acpi_video_backlight_use_native()) {
4228                 drm_info(drm, "Skipping amdgpu DM backlight registration\n");
4229                 /* Try registering an ACPI video backlight device instead. */
4230                 acpi_video_register_backlight();
4231                 return;
4232         }
4233
4234         props.max_brightness = AMDGPU_MAX_BL_LEVEL;
4235         props.brightness = AMDGPU_MAX_BL_LEVEL;
4236         props.type = BACKLIGHT_RAW;
4237
4238         snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
4239                  drm->primary->index + aconnector->bl_idx);
4240
4241         dm->backlight_dev[aconnector->bl_idx] =
4242                 backlight_device_register(bl_name, aconnector->base.kdev, dm,
4243                                           &amdgpu_dm_backlight_ops, &props);
4244
4245         if (IS_ERR(dm->backlight_dev[aconnector->bl_idx])) {
4246                 DRM_ERROR("DM: Backlight registration failed!\n");
4247                 dm->backlight_dev[aconnector->bl_idx] = NULL;
4248         } else
4249                 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4250 }
4251
4252 static int initialize_plane(struct amdgpu_display_manager *dm,
4253                             struct amdgpu_mode_info *mode_info, int plane_id,
4254                             enum drm_plane_type plane_type,
4255                             const struct dc_plane_cap *plane_cap)
4256 {
4257         struct drm_plane *plane;
4258         unsigned long possible_crtcs;
4259         int ret = 0;
4260
4261         plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
4262         if (!plane) {
4263                 DRM_ERROR("KMS: Failed to allocate plane\n");
4264                 return -ENOMEM;
4265         }
4266         plane->type = plane_type;
4267
4268         /*
4269          * HACK: IGT tests expect that the primary plane for a CRTC
4270          * can only have one possible CRTC. Only expose support for
4271          * any CRTC if they're not going to be used as a primary plane
4272          * for a CRTC - like overlay or underlay planes.
4273          */
4274         possible_crtcs = 1 << plane_id;
4275         if (plane_id >= dm->dc->caps.max_streams)
4276                 possible_crtcs = 0xff;
4277
4278         ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
4279
4280         if (ret) {
4281                 DRM_ERROR("KMS: Failed to initialize plane\n");
4282                 kfree(plane);
4283                 return ret;
4284         }
4285
4286         if (mode_info)
4287                 mode_info->planes[plane_id] = plane;
4288
4289         return ret;
4290 }
4291
4292
4293 static void setup_backlight_device(struct amdgpu_display_manager *dm,
4294                                    struct amdgpu_dm_connector *aconnector)
4295 {
4296         struct dc_link *link = aconnector->dc_link;
4297         int bl_idx = dm->num_of_edps;
4298
4299         if (!(link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) ||
4300             link->type == dc_connection_none)
4301                 return;
4302
4303         if (dm->num_of_edps >= AMDGPU_DM_MAX_NUM_EDP) {
4304                 drm_warn(adev_to_drm(dm->adev), "Too much eDP connections, skipping backlight setup for additional eDPs\n");
4305                 return;
4306         }
4307
4308         aconnector->bl_idx = bl_idx;
4309
4310         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4311         dm->brightness[bl_idx] = AMDGPU_MAX_BL_LEVEL;
4312         dm->backlight_link[bl_idx] = link;
4313         dm->num_of_edps++;
4314
4315         update_connector_ext_caps(aconnector);
4316 }
4317
4318 static void amdgpu_set_panel_orientation(struct drm_connector *connector);
4319
4320 /*
4321  * In this architecture, the association
4322  * connector -> encoder -> crtc
4323  * id not really requried. The crtc and connector will hold the
4324  * display_index as an abstraction to use with DAL component
4325  *
4326  * Returns 0 on success
4327  */
4328 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4329 {
4330         struct amdgpu_display_manager *dm = &adev->dm;
4331         s32 i;
4332         struct amdgpu_dm_connector *aconnector = NULL;
4333         struct amdgpu_encoder *aencoder = NULL;
4334         struct amdgpu_mode_info *mode_info = &adev->mode_info;
4335         u32 link_cnt;
4336         s32 primary_planes;
4337         enum dc_connection_type new_connection_type = dc_connection_none;
4338         const struct dc_plane_cap *plane;
4339         bool psr_feature_enabled = false;
4340         bool replay_feature_enabled = false;
4341         int max_overlay = dm->dc->caps.max_slave_planes;
4342
4343         dm->display_indexes_num = dm->dc->caps.max_streams;
4344         /* Update the actual used number of crtc */
4345         adev->mode_info.num_crtc = adev->dm.display_indexes_num;
4346
4347         amdgpu_dm_set_irq_funcs(adev);
4348
4349         link_cnt = dm->dc->caps.max_links;
4350         if (amdgpu_dm_mode_config_init(dm->adev)) {
4351                 DRM_ERROR("DM: Failed to initialize mode config\n");
4352                 return -EINVAL;
4353         }
4354
4355         /* There is one primary plane per CRTC */
4356         primary_planes = dm->dc->caps.max_streams;
4357         ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
4358
4359         /*
4360          * Initialize primary planes, implicit planes for legacy IOCTLS.
4361          * Order is reversed to match iteration order in atomic check.
4362          */
4363         for (i = (primary_planes - 1); i >= 0; i--) {
4364                 plane = &dm->dc->caps.planes[i];
4365
4366                 if (initialize_plane(dm, mode_info, i,
4367                                      DRM_PLANE_TYPE_PRIMARY, plane)) {
4368                         DRM_ERROR("KMS: Failed to initialize primary plane\n");
4369                         goto fail;
4370                 }
4371         }
4372
4373         /*
4374          * Initialize overlay planes, index starting after primary planes.
4375          * These planes have a higher DRM index than the primary planes since
4376          * they should be considered as having a higher z-order.
4377          * Order is reversed to match iteration order in atomic check.
4378          *
4379          * Only support DCN for now, and only expose one so we don't encourage
4380          * userspace to use up all the pipes.
4381          */
4382         for (i = 0; i < dm->dc->caps.max_planes; ++i) {
4383                 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
4384
4385                 /* Do not create overlay if MPO disabled */
4386                 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO)
4387                         break;
4388
4389                 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
4390                         continue;
4391
4392                 if (!plane->pixel_format_support.argb8888)
4393                         continue;
4394
4395                 if (max_overlay-- == 0)
4396                         break;
4397
4398                 if (initialize_plane(dm, NULL, primary_planes + i,
4399                                      DRM_PLANE_TYPE_OVERLAY, plane)) {
4400                         DRM_ERROR("KMS: Failed to initialize overlay plane\n");
4401                         goto fail;
4402                 }
4403         }
4404
4405         for (i = 0; i < dm->dc->caps.max_streams; i++)
4406                 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
4407                         DRM_ERROR("KMS: Failed to initialize crtc\n");
4408                         goto fail;
4409                 }
4410
4411         /* Use Outbox interrupt */
4412         switch (adev->ip_versions[DCE_HWIP][0]) {
4413         case IP_VERSION(3, 0, 0):
4414         case IP_VERSION(3, 1, 2):
4415         case IP_VERSION(3, 1, 3):
4416         case IP_VERSION(3, 1, 4):
4417         case IP_VERSION(3, 1, 5):
4418         case IP_VERSION(3, 1, 6):
4419         case IP_VERSION(3, 2, 0):
4420         case IP_VERSION(3, 2, 1):
4421         case IP_VERSION(2, 1, 0):
4422                 if (register_outbox_irq_handlers(dm->adev)) {
4423                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4424                         goto fail;
4425                 }
4426                 break;
4427         default:
4428                 DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",
4429                               adev->ip_versions[DCE_HWIP][0]);
4430         }
4431
4432         /* Determine whether to enable PSR support by default. */
4433         if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) {
4434                 switch (adev->ip_versions[DCE_HWIP][0]) {
4435                 case IP_VERSION(3, 1, 2):
4436                 case IP_VERSION(3, 1, 3):
4437                 case IP_VERSION(3, 1, 4):
4438                 case IP_VERSION(3, 1, 5):
4439                 case IP_VERSION(3, 1, 6):
4440                 case IP_VERSION(3, 2, 0):
4441                 case IP_VERSION(3, 2, 1):
4442                         psr_feature_enabled = true;
4443                         break;
4444                 default:
4445                         psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK;
4446                         break;
4447                 }
4448         }
4449
4450         if (!(amdgpu_dc_debug_mask & DC_DISABLE_REPLAY)) {
4451                 switch (adev->ip_versions[DCE_HWIP][0]) {
4452                 case IP_VERSION(3, 1, 4):
4453                 case IP_VERSION(3, 1, 5):
4454                 case IP_VERSION(3, 1, 6):
4455                 case IP_VERSION(3, 2, 0):
4456                 case IP_VERSION(3, 2, 1):
4457                         replay_feature_enabled = true;
4458                         break;
4459                 default:
4460                         replay_feature_enabled = amdgpu_dc_feature_mask & DC_REPLAY_MASK;
4461                         break;
4462                 }
4463         }
4464         /* loops over all connectors on the board */
4465         for (i = 0; i < link_cnt; i++) {
4466                 struct dc_link *link = NULL;
4467
4468                 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
4469                         DRM_ERROR(
4470                                 "KMS: Cannot support more than %d display indexes\n",
4471                                         AMDGPU_DM_MAX_DISPLAY_INDEX);
4472                         continue;
4473                 }
4474
4475                 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
4476                 if (!aconnector)
4477                         goto fail;
4478
4479                 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
4480                 if (!aencoder)
4481                         goto fail;
4482
4483                 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
4484                         DRM_ERROR("KMS: Failed to initialize encoder\n");
4485                         goto fail;
4486                 }
4487
4488                 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
4489                         DRM_ERROR("KMS: Failed to initialize connector\n");
4490                         goto fail;
4491                 }
4492
4493                 link = dc_get_link_at_index(dm->dc, i);
4494
4495                 if (!dc_link_detect_connection_type(link, &new_connection_type))
4496                         DRM_ERROR("KMS: Failed to detect connector\n");
4497
4498                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
4499                         emulated_link_detect(link);
4500                         amdgpu_dm_update_connector_after_detect(aconnector);
4501                 } else {
4502                         bool ret = false;
4503
4504                         mutex_lock(&dm->dc_lock);
4505                         ret = dc_link_detect(link, DETECT_REASON_BOOT);
4506                         mutex_unlock(&dm->dc_lock);
4507
4508                         if (ret) {
4509                                 amdgpu_dm_update_connector_after_detect(aconnector);
4510                                 setup_backlight_device(dm, aconnector);
4511
4512                                 /*
4513                                  * Disable psr if replay can be enabled
4514                                  */
4515                                 if (replay_feature_enabled && amdgpu_dm_setup_replay(link, aconnector))
4516                                         psr_feature_enabled = false;
4517
4518                                 if (psr_feature_enabled)
4519                                         amdgpu_dm_set_psr_caps(link);
4520
4521                                 /* TODO: Fix vblank control helpers to delay PSR entry to allow this when
4522                                  * PSR is also supported.
4523                                  */
4524                                 if (link->psr_settings.psr_feature_enabled)
4525                                         adev_to_drm(adev)->vblank_disable_immediate = false;
4526                         }
4527                 }
4528                 amdgpu_set_panel_orientation(&aconnector->base);
4529         }
4530
4531         /* Software is initialized. Now we can register interrupt handlers. */
4532         switch (adev->asic_type) {
4533 #if defined(CONFIG_DRM_AMD_DC_SI)
4534         case CHIP_TAHITI:
4535         case CHIP_PITCAIRN:
4536         case CHIP_VERDE:
4537         case CHIP_OLAND:
4538                 if (dce60_register_irq_handlers(dm->adev)) {
4539                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4540                         goto fail;
4541                 }
4542                 break;
4543 #endif
4544         case CHIP_BONAIRE:
4545         case CHIP_HAWAII:
4546         case CHIP_KAVERI:
4547         case CHIP_KABINI:
4548         case CHIP_MULLINS:
4549         case CHIP_TONGA:
4550         case CHIP_FIJI:
4551         case CHIP_CARRIZO:
4552         case CHIP_STONEY:
4553         case CHIP_POLARIS11:
4554         case CHIP_POLARIS10:
4555         case CHIP_POLARIS12:
4556         case CHIP_VEGAM:
4557         case CHIP_VEGA10:
4558         case CHIP_VEGA12:
4559         case CHIP_VEGA20:
4560                 if (dce110_register_irq_handlers(dm->adev)) {
4561                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4562                         goto fail;
4563                 }
4564                 break;
4565         default:
4566                 switch (adev->ip_versions[DCE_HWIP][0]) {
4567                 case IP_VERSION(1, 0, 0):
4568                 case IP_VERSION(1, 0, 1):
4569                 case IP_VERSION(2, 0, 2):
4570                 case IP_VERSION(2, 0, 3):
4571                 case IP_VERSION(2, 0, 0):
4572                 case IP_VERSION(2, 1, 0):
4573                 case IP_VERSION(3, 0, 0):
4574                 case IP_VERSION(3, 0, 2):
4575                 case IP_VERSION(3, 0, 3):
4576                 case IP_VERSION(3, 0, 1):
4577                 case IP_VERSION(3, 1, 2):
4578                 case IP_VERSION(3, 1, 3):
4579                 case IP_VERSION(3, 1, 4):
4580                 case IP_VERSION(3, 1, 5):
4581                 case IP_VERSION(3, 1, 6):
4582                 case IP_VERSION(3, 2, 0):
4583                 case IP_VERSION(3, 2, 1):
4584                         if (dcn10_register_irq_handlers(dm->adev)) {
4585                                 DRM_ERROR("DM: Failed to initialize IRQ\n");
4586                                 goto fail;
4587                         }
4588                         break;
4589                 default:
4590                         DRM_ERROR("Unsupported DCE IP versions: 0x%X\n",
4591                                         adev->ip_versions[DCE_HWIP][0]);
4592                         goto fail;
4593                 }
4594                 break;
4595         }
4596
4597         return 0;
4598 fail:
4599         kfree(aencoder);
4600         kfree(aconnector);
4601
4602         return -EINVAL;
4603 }
4604
4605 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4606 {
4607         drm_atomic_private_obj_fini(&dm->atomic_obj);
4608 }
4609
4610 /******************************************************************************
4611  * amdgpu_display_funcs functions
4612  *****************************************************************************/
4613
4614 /*
4615  * dm_bandwidth_update - program display watermarks
4616  *
4617  * @adev: amdgpu_device pointer
4618  *
4619  * Calculate and program the display watermarks and line buffer allocation.
4620  */
4621 static void dm_bandwidth_update(struct amdgpu_device *adev)
4622 {
4623         /* TODO: implement later */
4624 }
4625
4626 static const struct amdgpu_display_funcs dm_display_funcs = {
4627         .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
4628         .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
4629         .backlight_set_level = NULL, /* never called for DC */
4630         .backlight_get_level = NULL, /* never called for DC */
4631         .hpd_sense = NULL,/* called unconditionally */
4632         .hpd_set_polarity = NULL, /* called unconditionally */
4633         .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4634         .page_flip_get_scanoutpos =
4635                 dm_crtc_get_scanoutpos,/* called unconditionally */
4636         .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
4637         .add_connector = NULL, /* VBIOS parsing. DAL does it. */
4638 };
4639
4640 #if defined(CONFIG_DEBUG_KERNEL_DC)
4641
4642 static ssize_t s3_debug_store(struct device *device,
4643                               struct device_attribute *attr,
4644                               const char *buf,
4645                               size_t count)
4646 {
4647         int ret;
4648         int s3_state;
4649         struct drm_device *drm_dev = dev_get_drvdata(device);
4650         struct amdgpu_device *adev = drm_to_adev(drm_dev);
4651
4652         ret = kstrtoint(buf, 0, &s3_state);
4653
4654         if (ret == 0) {
4655                 if (s3_state) {
4656                         dm_resume(adev);
4657                         drm_kms_helper_hotplug_event(adev_to_drm(adev));
4658                 } else
4659                         dm_suspend(adev);
4660         }
4661
4662         return ret == 0 ? count : 0;
4663 }
4664
4665 DEVICE_ATTR_WO(s3_debug);
4666
4667 #endif
4668
4669 static int dm_init_microcode(struct amdgpu_device *adev)
4670 {
4671         char *fw_name_dmub;
4672         int r;
4673
4674         switch (adev->ip_versions[DCE_HWIP][0]) {
4675         case IP_VERSION(2, 1, 0):
4676                 fw_name_dmub = FIRMWARE_RENOIR_DMUB;
4677                 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
4678                         fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
4679                 break;
4680         case IP_VERSION(3, 0, 0):
4681                 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
4682                         fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
4683                 else
4684                         fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
4685                 break;
4686         case IP_VERSION(3, 0, 1):
4687                 fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
4688                 break;
4689         case IP_VERSION(3, 0, 2):
4690                 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
4691                 break;
4692         case IP_VERSION(3, 0, 3):
4693                 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;
4694                 break;
4695         case IP_VERSION(3, 1, 2):
4696         case IP_VERSION(3, 1, 3):
4697                 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
4698                 break;
4699         case IP_VERSION(3, 1, 4):
4700                 fw_name_dmub = FIRMWARE_DCN_314_DMUB;
4701                 break;
4702         case IP_VERSION(3, 1, 5):
4703                 fw_name_dmub = FIRMWARE_DCN_315_DMUB;
4704                 break;
4705         case IP_VERSION(3, 1, 6):
4706                 fw_name_dmub = FIRMWARE_DCN316_DMUB;
4707                 break;
4708         case IP_VERSION(3, 2, 0):
4709                 fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB;
4710                 break;
4711         case IP_VERSION(3, 2, 1):
4712                 fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB;
4713                 break;
4714         default:
4715                 /* ASIC doesn't support DMUB. */
4716                 return 0;
4717         }
4718         r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, fw_name_dmub);
4719         if (r)
4720                 DRM_ERROR("DMUB firmware loading failed: %d\n", r);
4721         return r;
4722 }
4723
4724 static int dm_early_init(void *handle)
4725 {
4726         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4727         struct amdgpu_mode_info *mode_info = &adev->mode_info;
4728         struct atom_context *ctx = mode_info->atom_context;
4729         int index = GetIndexIntoMasterTable(DATA, Object_Header);
4730         u16 data_offset;
4731
4732         /* if there is no object header, skip DM */
4733         if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
4734                 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
4735                 dev_info(adev->dev, "No object header, skipping DM\n");
4736                 return -ENOENT;
4737         }
4738
4739         switch (adev->asic_type) {
4740 #if defined(CONFIG_DRM_AMD_DC_SI)
4741         case CHIP_TAHITI:
4742         case CHIP_PITCAIRN:
4743         case CHIP_VERDE:
4744                 adev->mode_info.num_crtc = 6;
4745                 adev->mode_info.num_hpd = 6;
4746                 adev->mode_info.num_dig = 6;
4747                 break;
4748         case CHIP_OLAND:
4749                 adev->mode_info.num_crtc = 2;
4750                 adev->mode_info.num_hpd = 2;
4751                 adev->mode_info.num_dig = 2;
4752                 break;
4753 #endif
4754         case CHIP_BONAIRE:
4755         case CHIP_HAWAII:
4756                 adev->mode_info.num_crtc = 6;
4757                 adev->mode_info.num_hpd = 6;
4758                 adev->mode_info.num_dig = 6;
4759                 break;
4760         case CHIP_KAVERI:
4761                 adev->mode_info.num_crtc = 4;
4762                 adev->mode_info.num_hpd = 6;
4763                 adev->mode_info.num_dig = 7;
4764                 break;
4765         case CHIP_KABINI:
4766         case CHIP_MULLINS:
4767                 adev->mode_info.num_crtc = 2;
4768                 adev->mode_info.num_hpd = 6;
4769                 adev->mode_info.num_dig = 6;
4770                 break;
4771         case CHIP_FIJI:
4772         case CHIP_TONGA:
4773                 adev->mode_info.num_crtc = 6;
4774                 adev->mode_info.num_hpd = 6;
4775                 adev->mode_info.num_dig = 7;
4776                 break;
4777         case CHIP_CARRIZO:
4778                 adev->mode_info.num_crtc = 3;
4779                 adev->mode_info.num_hpd = 6;
4780                 adev->mode_info.num_dig = 9;
4781                 break;
4782         case CHIP_STONEY:
4783                 adev->mode_info.num_crtc = 2;
4784                 adev->mode_info.num_hpd = 6;
4785                 adev->mode_info.num_dig = 9;
4786                 break;
4787         case CHIP_POLARIS11:
4788         case CHIP_POLARIS12:
4789                 adev->mode_info.num_crtc = 5;
4790                 adev->mode_info.num_hpd = 5;
4791                 adev->mode_info.num_dig = 5;
4792                 break;
4793         case CHIP_POLARIS10:
4794         case CHIP_VEGAM:
4795                 adev->mode_info.num_crtc = 6;
4796                 adev->mode_info.num_hpd = 6;
4797                 adev->mode_info.num_dig = 6;
4798                 break;
4799         case CHIP_VEGA10:
4800         case CHIP_VEGA12:
4801         case CHIP_VEGA20:
4802                 adev->mode_info.num_crtc = 6;
4803                 adev->mode_info.num_hpd = 6;
4804                 adev->mode_info.num_dig = 6;
4805                 break;
4806         default:
4807
4808                 switch (adev->ip_versions[DCE_HWIP][0]) {
4809                 case IP_VERSION(2, 0, 2):
4810                 case IP_VERSION(3, 0, 0):
4811                         adev->mode_info.num_crtc = 6;
4812                         adev->mode_info.num_hpd = 6;
4813                         adev->mode_info.num_dig = 6;
4814                         break;
4815                 case IP_VERSION(2, 0, 0):
4816                 case IP_VERSION(3, 0, 2):
4817                         adev->mode_info.num_crtc = 5;
4818                         adev->mode_info.num_hpd = 5;
4819                         adev->mode_info.num_dig = 5;
4820                         break;
4821                 case IP_VERSION(2, 0, 3):
4822                 case IP_VERSION(3, 0, 3):
4823                         adev->mode_info.num_crtc = 2;
4824                         adev->mode_info.num_hpd = 2;
4825                         adev->mode_info.num_dig = 2;
4826                         break;
4827                 case IP_VERSION(1, 0, 0):
4828                 case IP_VERSION(1, 0, 1):
4829                 case IP_VERSION(3, 0, 1):
4830                 case IP_VERSION(2, 1, 0):
4831                 case IP_VERSION(3, 1, 2):
4832                 case IP_VERSION(3, 1, 3):
4833                 case IP_VERSION(3, 1, 4):
4834                 case IP_VERSION(3, 1, 5):
4835                 case IP_VERSION(3, 1, 6):
4836                 case IP_VERSION(3, 2, 0):
4837                 case IP_VERSION(3, 2, 1):
4838                         adev->mode_info.num_crtc = 4;
4839                         adev->mode_info.num_hpd = 4;
4840                         adev->mode_info.num_dig = 4;
4841                         break;
4842                 default:
4843                         DRM_ERROR("Unsupported DCE IP versions: 0x%x\n",
4844                                         adev->ip_versions[DCE_HWIP][0]);
4845                         return -EINVAL;
4846                 }
4847                 break;
4848         }
4849
4850         if (adev->mode_info.funcs == NULL)
4851                 adev->mode_info.funcs = &dm_display_funcs;
4852
4853         /*
4854          * Note: Do NOT change adev->audio_endpt_rreg and
4855          * adev->audio_endpt_wreg because they are initialised in
4856          * amdgpu_device_init()
4857          */
4858 #if defined(CONFIG_DEBUG_KERNEL_DC)
4859         device_create_file(
4860                 adev_to_drm(adev)->dev,
4861                 &dev_attr_s3_debug);
4862 #endif
4863         adev->dc_enabled = true;
4864
4865         return dm_init_microcode(adev);
4866 }
4867
4868 static bool modereset_required(struct drm_crtc_state *crtc_state)
4869 {
4870         return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
4871 }
4872
4873 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
4874 {
4875         drm_encoder_cleanup(encoder);
4876         kfree(encoder);
4877 }
4878
4879 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
4880         .destroy = amdgpu_dm_encoder_destroy,
4881 };
4882
4883 static int
4884 fill_plane_color_attributes(const struct drm_plane_state *plane_state,
4885                             const enum surface_pixel_format format,
4886                             enum dc_color_space *color_space)
4887 {
4888         bool full_range;
4889
4890         *color_space = COLOR_SPACE_SRGB;
4891
4892         /* DRM color properties only affect non-RGB formats. */
4893         if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
4894                 return 0;
4895
4896         full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
4897
4898         switch (plane_state->color_encoding) {
4899         case DRM_COLOR_YCBCR_BT601:
4900                 if (full_range)
4901                         *color_space = COLOR_SPACE_YCBCR601;
4902                 else
4903                         *color_space = COLOR_SPACE_YCBCR601_LIMITED;
4904                 break;
4905
4906         case DRM_COLOR_YCBCR_BT709:
4907                 if (full_range)
4908                         *color_space = COLOR_SPACE_YCBCR709;
4909                 else
4910                         *color_space = COLOR_SPACE_YCBCR709_LIMITED;
4911                 break;
4912
4913         case DRM_COLOR_YCBCR_BT2020:
4914                 if (full_range)
4915                         *color_space = COLOR_SPACE_2020_YCBCR;
4916                 else
4917                         return -EINVAL;
4918                 break;
4919
4920         default:
4921                 return -EINVAL;
4922         }
4923
4924         return 0;
4925 }
4926
4927 static int
4928 fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
4929                             const struct drm_plane_state *plane_state,
4930                             const u64 tiling_flags,
4931                             struct dc_plane_info *plane_info,
4932                             struct dc_plane_address *address,
4933                             bool tmz_surface,
4934                             bool force_disable_dcc)
4935 {
4936         const struct drm_framebuffer *fb = plane_state->fb;
4937         const struct amdgpu_framebuffer *afb =
4938                 to_amdgpu_framebuffer(plane_state->fb);
4939         int ret;
4940
4941         memset(plane_info, 0, sizeof(*plane_info));
4942
4943         switch (fb->format->format) {
4944         case DRM_FORMAT_C8:
4945                 plane_info->format =
4946                         SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
4947                 break;
4948         case DRM_FORMAT_RGB565:
4949                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
4950                 break;
4951         case DRM_FORMAT_XRGB8888:
4952         case DRM_FORMAT_ARGB8888:
4953                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
4954                 break;
4955         case DRM_FORMAT_XRGB2101010:
4956         case DRM_FORMAT_ARGB2101010:
4957                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
4958                 break;
4959         case DRM_FORMAT_XBGR2101010:
4960         case DRM_FORMAT_ABGR2101010:
4961                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
4962                 break;
4963         case DRM_FORMAT_XBGR8888:
4964         case DRM_FORMAT_ABGR8888:
4965                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
4966                 break;
4967         case DRM_FORMAT_NV21:
4968                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
4969                 break;
4970         case DRM_FORMAT_NV12:
4971                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
4972                 break;
4973         case DRM_FORMAT_P010:
4974                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb;
4975                 break;
4976         case DRM_FORMAT_XRGB16161616F:
4977         case DRM_FORMAT_ARGB16161616F:
4978                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F;
4979                 break;
4980         case DRM_FORMAT_XBGR16161616F:
4981         case DRM_FORMAT_ABGR16161616F:
4982                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;
4983                 break;
4984         case DRM_FORMAT_XRGB16161616:
4985         case DRM_FORMAT_ARGB16161616:
4986                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616;
4987                 break;
4988         case DRM_FORMAT_XBGR16161616:
4989         case DRM_FORMAT_ABGR16161616:
4990                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616;
4991                 break;
4992         default:
4993                 DRM_ERROR(
4994                         "Unsupported screen format %p4cc\n",
4995                         &fb->format->format);
4996                 return -EINVAL;
4997         }
4998
4999         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
5000         case DRM_MODE_ROTATE_0:
5001                 plane_info->rotation = ROTATION_ANGLE_0;
5002                 break;
5003         case DRM_MODE_ROTATE_90:
5004                 plane_info->rotation = ROTATION_ANGLE_90;
5005                 break;
5006         case DRM_MODE_ROTATE_180:
5007                 plane_info->rotation = ROTATION_ANGLE_180;
5008                 break;
5009         case DRM_MODE_ROTATE_270:
5010                 plane_info->rotation = ROTATION_ANGLE_270;
5011                 break;
5012         default:
5013                 plane_info->rotation = ROTATION_ANGLE_0;
5014                 break;
5015         }
5016
5017
5018         plane_info->visible = true;
5019         plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
5020
5021         plane_info->layer_index = plane_state->normalized_zpos;
5022
5023         ret = fill_plane_color_attributes(plane_state, plane_info->format,
5024                                           &plane_info->color_space);
5025         if (ret)
5026                 return ret;
5027
5028         ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format,
5029                                            plane_info->rotation, tiling_flags,
5030                                            &plane_info->tiling_info,
5031                                            &plane_info->plane_size,
5032                                            &plane_info->dcc, address,
5033                                            tmz_surface, force_disable_dcc);
5034         if (ret)
5035                 return ret;
5036
5037         amdgpu_dm_plane_fill_blending_from_plane_state(
5038                 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha,
5039                 &plane_info->global_alpha, &plane_info->global_alpha_value);
5040
5041         return 0;
5042 }
5043
5044 static int fill_dc_plane_attributes(struct amdgpu_device *adev,
5045                                     struct dc_plane_state *dc_plane_state,
5046                                     struct drm_plane_state *plane_state,
5047                                     struct drm_crtc_state *crtc_state)
5048 {
5049         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5050         struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb;
5051         struct dc_scaling_info scaling_info;
5052         struct dc_plane_info plane_info;
5053         int ret;
5054         bool force_disable_dcc = false;
5055
5056         ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info);
5057         if (ret)
5058                 return ret;
5059
5060         dc_plane_state->src_rect = scaling_info.src_rect;
5061         dc_plane_state->dst_rect = scaling_info.dst_rect;
5062         dc_plane_state->clip_rect = scaling_info.clip_rect;
5063         dc_plane_state->scaling_quality = scaling_info.scaling_quality;
5064
5065         force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
5066         ret = fill_dc_plane_info_and_addr(adev, plane_state,
5067                                           afb->tiling_flags,
5068                                           &plane_info,
5069                                           &dc_plane_state->address,
5070                                           afb->tmz_surface,
5071                                           force_disable_dcc);
5072         if (ret)
5073                 return ret;
5074
5075         dc_plane_state->format = plane_info.format;
5076         dc_plane_state->color_space = plane_info.color_space;
5077         dc_plane_state->format = plane_info.format;
5078         dc_plane_state->plane_size = plane_info.plane_size;
5079         dc_plane_state->rotation = plane_info.rotation;
5080         dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
5081         dc_plane_state->stereo_format = plane_info.stereo_format;
5082         dc_plane_state->tiling_info = plane_info.tiling_info;
5083         dc_plane_state->visible = plane_info.visible;
5084         dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
5085         dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha;
5086         dc_plane_state->global_alpha = plane_info.global_alpha;
5087         dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
5088         dc_plane_state->dcc = plane_info.dcc;
5089         dc_plane_state->layer_index = plane_info.layer_index;
5090         dc_plane_state->flip_int_enabled = true;
5091
5092         /*
5093          * Always set input transfer function, since plane state is refreshed
5094          * every time.
5095          */
5096         ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
5097         if (ret)
5098                 return ret;
5099
5100         return 0;
5101 }
5102
5103 static inline void fill_dc_dirty_rect(struct drm_plane *plane,
5104                                       struct rect *dirty_rect, int32_t x,
5105                                       s32 y, s32 width, s32 height,
5106                                       int *i, bool ffu)
5107 {
5108         WARN_ON(*i >= DC_MAX_DIRTY_RECTS);
5109
5110         dirty_rect->x = x;
5111         dirty_rect->y = y;
5112         dirty_rect->width = width;
5113         dirty_rect->height = height;
5114
5115         if (ffu)
5116                 drm_dbg(plane->dev,
5117                         "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n",
5118                         plane->base.id, width, height);
5119         else
5120                 drm_dbg(plane->dev,
5121                         "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)",
5122                         plane->base.id, x, y, width, height);
5123
5124         (*i)++;
5125 }
5126
5127 /**
5128  * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates
5129  *
5130  * @plane: DRM plane containing dirty regions that need to be flushed to the eDP
5131  *         remote fb
5132  * @old_plane_state: Old state of @plane
5133  * @new_plane_state: New state of @plane
5134  * @crtc_state: New state of CRTC connected to the @plane
5135  * @flip_addrs: DC flip tracking struct, which also tracts dirty rects
5136  * @dirty_regions_changed: dirty regions changed
5137  *
5138  * For PSR SU, DC informs the DMUB uController of dirty rectangle regions
5139  * (referred to as "damage clips" in DRM nomenclature) that require updating on
5140  * the eDP remote buffer. The responsibility of specifying the dirty regions is
5141  * amdgpu_dm's.
5142  *
5143  * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the
5144  * plane with regions that require flushing to the eDP remote buffer. In
5145  * addition, certain use cases - such as cursor and multi-plane overlay (MPO) -
5146  * implicitly provide damage clips without any client support via the plane
5147  * bounds.
5148  */
5149 static void fill_dc_dirty_rects(struct drm_plane *plane,
5150                                 struct drm_plane_state *old_plane_state,
5151                                 struct drm_plane_state *new_plane_state,
5152                                 struct drm_crtc_state *crtc_state,
5153                                 struct dc_flip_addrs *flip_addrs,
5154                                 bool *dirty_regions_changed)
5155 {
5156         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5157         struct rect *dirty_rects = flip_addrs->dirty_rects;
5158         u32 num_clips;
5159         struct drm_mode_rect *clips;
5160         bool bb_changed;
5161         bool fb_changed;
5162         u32 i = 0;
5163         *dirty_regions_changed = false;
5164
5165         /*
5166          * Cursor plane has it's own dirty rect update interface. See
5167          * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data
5168          */
5169         if (plane->type == DRM_PLANE_TYPE_CURSOR)
5170                 return;
5171
5172         num_clips = drm_plane_get_damage_clips_count(new_plane_state);
5173         clips = drm_plane_get_damage_clips(new_plane_state);
5174
5175         if (!dm_crtc_state->mpo_requested) {
5176                 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS)
5177                         goto ffu;
5178
5179                 for (; flip_addrs->dirty_rect_count < num_clips; clips++)
5180                         fill_dc_dirty_rect(new_plane_state->plane,
5181                                            &dirty_rects[flip_addrs->dirty_rect_count],
5182                                            clips->x1, clips->y1,
5183                                            clips->x2 - clips->x1, clips->y2 - clips->y1,
5184                                            &flip_addrs->dirty_rect_count,
5185                                            false);
5186                 return;
5187         }
5188
5189         /*
5190          * MPO is requested. Add entire plane bounding box to dirty rects if
5191          * flipped to or damaged.
5192          *
5193          * If plane is moved or resized, also add old bounding box to dirty
5194          * rects.
5195          */
5196         fb_changed = old_plane_state->fb->base.id !=
5197                      new_plane_state->fb->base.id;
5198         bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x ||
5199                       old_plane_state->crtc_y != new_plane_state->crtc_y ||
5200                       old_plane_state->crtc_w != new_plane_state->crtc_w ||
5201                       old_plane_state->crtc_h != new_plane_state->crtc_h);
5202
5203         drm_dbg(plane->dev,
5204                 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n",
5205                 new_plane_state->plane->base.id,
5206                 bb_changed, fb_changed, num_clips);
5207
5208         *dirty_regions_changed = bb_changed;
5209
5210         if ((num_clips + (bb_changed ? 2 : 0)) > DC_MAX_DIRTY_RECTS)
5211                 goto ffu;
5212
5213         if (bb_changed) {
5214                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5215                                    new_plane_state->crtc_x,
5216                                    new_plane_state->crtc_y,
5217                                    new_plane_state->crtc_w,
5218                                    new_plane_state->crtc_h, &i, false);
5219
5220                 /* Add old plane bounding-box if plane is moved or resized */
5221                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5222                                    old_plane_state->crtc_x,
5223                                    old_plane_state->crtc_y,
5224                                    old_plane_state->crtc_w,
5225                                    old_plane_state->crtc_h, &i, false);
5226         }
5227
5228         if (num_clips) {
5229                 for (; i < num_clips; clips++)
5230                         fill_dc_dirty_rect(new_plane_state->plane,
5231                                            &dirty_rects[i], clips->x1,
5232                                            clips->y1, clips->x2 - clips->x1,
5233                                            clips->y2 - clips->y1, &i, false);
5234         } else if (fb_changed && !bb_changed) {
5235                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5236                                    new_plane_state->crtc_x,
5237                                    new_plane_state->crtc_y,
5238                                    new_plane_state->crtc_w,
5239                                    new_plane_state->crtc_h, &i, false);
5240         }
5241
5242         flip_addrs->dirty_rect_count = i;
5243         return;
5244
5245 ffu:
5246         fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0,
5247                            dm_crtc_state->base.mode.crtc_hdisplay,
5248                            dm_crtc_state->base.mode.crtc_vdisplay,
5249                            &flip_addrs->dirty_rect_count, true);
5250 }
5251
5252 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
5253                                            const struct dm_connector_state *dm_state,
5254                                            struct dc_stream_state *stream)
5255 {
5256         enum amdgpu_rmx_type rmx_type;
5257
5258         struct rect src = { 0 }; /* viewport in composition space*/
5259         struct rect dst = { 0 }; /* stream addressable area */
5260
5261         /* no mode. nothing to be done */
5262         if (!mode)
5263                 return;
5264
5265         /* Full screen scaling by default */
5266         src.width = mode->hdisplay;
5267         src.height = mode->vdisplay;
5268         dst.width = stream->timing.h_addressable;
5269         dst.height = stream->timing.v_addressable;
5270
5271         if (dm_state) {
5272                 rmx_type = dm_state->scaling;
5273                 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
5274                         if (src.width * dst.height <
5275                                         src.height * dst.width) {
5276                                 /* height needs less upscaling/more downscaling */
5277                                 dst.width = src.width *
5278                                                 dst.height / src.height;
5279                         } else {
5280                                 /* width needs less upscaling/more downscaling */
5281                                 dst.height = src.height *
5282                                                 dst.width / src.width;
5283                         }
5284                 } else if (rmx_type == RMX_CENTER) {
5285                         dst = src;
5286                 }
5287
5288                 dst.x = (stream->timing.h_addressable - dst.width) / 2;
5289                 dst.y = (stream->timing.v_addressable - dst.height) / 2;
5290
5291                 if (dm_state->underscan_enable) {
5292                         dst.x += dm_state->underscan_hborder / 2;
5293                         dst.y += dm_state->underscan_vborder / 2;
5294                         dst.width -= dm_state->underscan_hborder;
5295                         dst.height -= dm_state->underscan_vborder;
5296                 }
5297         }
5298
5299         stream->src = src;
5300         stream->dst = dst;
5301
5302         DRM_DEBUG_KMS("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",
5303                       dst.x, dst.y, dst.width, dst.height);
5304
5305 }
5306
5307 static enum dc_color_depth
5308 convert_color_depth_from_display_info(const struct drm_connector *connector,
5309                                       bool is_y420, int requested_bpc)
5310 {
5311         u8 bpc;
5312
5313         if (is_y420) {
5314                 bpc = 8;
5315
5316                 /* Cap display bpc based on HDMI 2.0 HF-VSDB */
5317                 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)
5318                         bpc = 16;
5319                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
5320                         bpc = 12;
5321                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
5322                         bpc = 10;
5323         } else {
5324                 bpc = (uint8_t)connector->display_info.bpc;
5325                 /* Assume 8 bpc by default if no bpc is specified. */
5326                 bpc = bpc ? bpc : 8;
5327         }
5328
5329         if (requested_bpc > 0) {
5330                 /*
5331                  * Cap display bpc based on the user requested value.
5332                  *
5333                  * The value for state->max_bpc may not correctly updated
5334                  * depending on when the connector gets added to the state
5335                  * or if this was called outside of atomic check, so it
5336                  * can't be used directly.
5337                  */
5338                 bpc = min_t(u8, bpc, requested_bpc);
5339
5340                 /* Round down to the nearest even number. */
5341                 bpc = bpc - (bpc & 1);
5342         }
5343
5344         switch (bpc) {
5345         case 0:
5346                 /*
5347                  * Temporary Work around, DRM doesn't parse color depth for
5348                  * EDID revision before 1.4
5349                  * TODO: Fix edid parsing
5350                  */
5351                 return COLOR_DEPTH_888;
5352         case 6:
5353                 return COLOR_DEPTH_666;
5354         case 8:
5355                 return COLOR_DEPTH_888;
5356         case 10:
5357                 return COLOR_DEPTH_101010;
5358         case 12:
5359                 return COLOR_DEPTH_121212;
5360         case 14:
5361                 return COLOR_DEPTH_141414;
5362         case 16:
5363                 return COLOR_DEPTH_161616;
5364         default:
5365                 return COLOR_DEPTH_UNDEFINED;
5366         }
5367 }
5368
5369 static enum dc_aspect_ratio
5370 get_aspect_ratio(const struct drm_display_mode *mode_in)
5371 {
5372         /* 1-1 mapping, since both enums follow the HDMI spec. */
5373         return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
5374 }
5375
5376 static enum dc_color_space
5377 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing,
5378                        const struct drm_connector_state *connector_state)
5379 {
5380         enum dc_color_space color_space = COLOR_SPACE_SRGB;
5381
5382         switch (connector_state->colorspace) {
5383         case DRM_MODE_COLORIMETRY_BT601_YCC:
5384                 if (dc_crtc_timing->flags.Y_ONLY)
5385                         color_space = COLOR_SPACE_YCBCR601_LIMITED;
5386                 else
5387                         color_space = COLOR_SPACE_YCBCR601;
5388                 break;
5389         case DRM_MODE_COLORIMETRY_BT709_YCC:
5390                 if (dc_crtc_timing->flags.Y_ONLY)
5391                         color_space = COLOR_SPACE_YCBCR709_LIMITED;
5392                 else
5393                         color_space = COLOR_SPACE_YCBCR709;
5394                 break;
5395         case DRM_MODE_COLORIMETRY_OPRGB:
5396                 color_space = COLOR_SPACE_ADOBERGB;
5397                 break;
5398         case DRM_MODE_COLORIMETRY_BT2020_RGB:
5399         case DRM_MODE_COLORIMETRY_BT2020_YCC:
5400                 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB)
5401                         color_space = COLOR_SPACE_2020_RGB_FULLRANGE;
5402                 else
5403                         color_space = COLOR_SPACE_2020_YCBCR;
5404                 break;
5405         case DRM_MODE_COLORIMETRY_DEFAULT: // ITU601
5406         default:
5407                 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) {
5408                         color_space = COLOR_SPACE_SRGB;
5409                 /*
5410                  * 27030khz is the separation point between HDTV and SDTV
5411                  * according to HDMI spec, we use YCbCr709 and YCbCr601
5412                  * respectively
5413                  */
5414                 } else if (dc_crtc_timing->pix_clk_100hz > 270300) {
5415                         if (dc_crtc_timing->flags.Y_ONLY)
5416                                 color_space =
5417                                         COLOR_SPACE_YCBCR709_LIMITED;
5418                         else
5419                                 color_space = COLOR_SPACE_YCBCR709;
5420                 } else {
5421                         if (dc_crtc_timing->flags.Y_ONLY)
5422                                 color_space =
5423                                         COLOR_SPACE_YCBCR601_LIMITED;
5424                         else
5425                                 color_space = COLOR_SPACE_YCBCR601;
5426                 }
5427                 break;
5428         }
5429
5430         return color_space;
5431 }
5432
5433 static bool adjust_colour_depth_from_display_info(
5434         struct dc_crtc_timing *timing_out,
5435         const struct drm_display_info *info)
5436 {
5437         enum dc_color_depth depth = timing_out->display_color_depth;
5438         int normalized_clk;
5439
5440         do {
5441                 normalized_clk = timing_out->pix_clk_100hz / 10;
5442                 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
5443                 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
5444                         normalized_clk /= 2;
5445                 /* Adjusting pix clock following on HDMI spec based on colour depth */
5446                 switch (depth) {
5447                 case COLOR_DEPTH_888:
5448                         break;
5449                 case COLOR_DEPTH_101010:
5450                         normalized_clk = (normalized_clk * 30) / 24;
5451                         break;
5452                 case COLOR_DEPTH_121212:
5453                         normalized_clk = (normalized_clk * 36) / 24;
5454                         break;
5455                 case COLOR_DEPTH_161616:
5456                         normalized_clk = (normalized_clk * 48) / 24;
5457                         break;
5458                 default:
5459                         /* The above depths are the only ones valid for HDMI. */
5460                         return false;
5461                 }
5462                 if (normalized_clk <= info->max_tmds_clock) {
5463                         timing_out->display_color_depth = depth;
5464                         return true;
5465                 }
5466         } while (--depth > COLOR_DEPTH_666);
5467         return false;
5468 }
5469
5470 static void fill_stream_properties_from_drm_display_mode(
5471         struct dc_stream_state *stream,
5472         const struct drm_display_mode *mode_in,
5473         const struct drm_connector *connector,
5474         const struct drm_connector_state *connector_state,
5475         const struct dc_stream_state *old_stream,
5476         int requested_bpc)
5477 {
5478         struct dc_crtc_timing *timing_out = &stream->timing;
5479         const struct drm_display_info *info = &connector->display_info;
5480         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5481         struct hdmi_vendor_infoframe hv_frame;
5482         struct hdmi_avi_infoframe avi_frame;
5483
5484         memset(&hv_frame, 0, sizeof(hv_frame));
5485         memset(&avi_frame, 0, sizeof(avi_frame));
5486
5487         timing_out->h_border_left = 0;
5488         timing_out->h_border_right = 0;
5489         timing_out->v_border_top = 0;
5490         timing_out->v_border_bottom = 0;
5491         /* TODO: un-hardcode */
5492         if (drm_mode_is_420_only(info, mode_in)
5493                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5494                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5495         else if (drm_mode_is_420_also(info, mode_in)
5496                         && aconnector->force_yuv420_output)
5497                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5498         else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444)
5499                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5500                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
5501         else
5502                 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
5503
5504         timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
5505         timing_out->display_color_depth = convert_color_depth_from_display_info(
5506                 connector,
5507                 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420),
5508                 requested_bpc);
5509         timing_out->scan_type = SCANNING_TYPE_NODATA;
5510         timing_out->hdmi_vic = 0;
5511
5512         if (old_stream) {
5513                 timing_out->vic = old_stream->timing.vic;
5514                 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
5515                 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
5516         } else {
5517                 timing_out->vic = drm_match_cea_mode(mode_in);
5518                 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
5519                         timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
5520                 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
5521                         timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
5522         }
5523
5524         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5525                 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
5526                 timing_out->vic = avi_frame.video_code;
5527                 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
5528                 timing_out->hdmi_vic = hv_frame.vic;
5529         }
5530
5531         if (is_freesync_video_mode(mode_in, aconnector)) {
5532                 timing_out->h_addressable = mode_in->hdisplay;
5533                 timing_out->h_total = mode_in->htotal;
5534                 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start;
5535                 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay;
5536                 timing_out->v_total = mode_in->vtotal;
5537                 timing_out->v_addressable = mode_in->vdisplay;
5538                 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay;
5539                 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start;
5540                 timing_out->pix_clk_100hz = mode_in->clock * 10;
5541         } else {
5542                 timing_out->h_addressable = mode_in->crtc_hdisplay;
5543                 timing_out->h_total = mode_in->crtc_htotal;
5544                 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
5545                 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
5546                 timing_out->v_total = mode_in->crtc_vtotal;
5547                 timing_out->v_addressable = mode_in->crtc_vdisplay;
5548                 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
5549                 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
5550                 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
5551         }
5552
5553         timing_out->aspect_ratio = get_aspect_ratio(mode_in);
5554
5555         stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
5556         stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
5557         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5558                 if (!adjust_colour_depth_from_display_info(timing_out, info) &&
5559                     drm_mode_is_420_also(info, mode_in) &&
5560                     timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
5561                         timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5562                         adjust_colour_depth_from_display_info(timing_out, info);
5563                 }
5564         }
5565
5566         stream->output_color_space = get_output_color_space(timing_out, connector_state);
5567 }
5568
5569 static void fill_audio_info(struct audio_info *audio_info,
5570                             const struct drm_connector *drm_connector,
5571                             const struct dc_sink *dc_sink)
5572 {
5573         int i = 0;
5574         int cea_revision = 0;
5575         const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
5576
5577         audio_info->manufacture_id = edid_caps->manufacturer_id;
5578         audio_info->product_id = edid_caps->product_id;
5579
5580         cea_revision = drm_connector->display_info.cea_rev;
5581
5582         strscpy(audio_info->display_name,
5583                 edid_caps->display_name,
5584                 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
5585
5586         if (cea_revision >= 3) {
5587                 audio_info->mode_count = edid_caps->audio_mode_count;
5588
5589                 for (i = 0; i < audio_info->mode_count; ++i) {
5590                         audio_info->modes[i].format_code =
5591                                         (enum audio_format_code)
5592                                         (edid_caps->audio_modes[i].format_code);
5593                         audio_info->modes[i].channel_count =
5594                                         edid_caps->audio_modes[i].channel_count;
5595                         audio_info->modes[i].sample_rates.all =
5596                                         edid_caps->audio_modes[i].sample_rate;
5597                         audio_info->modes[i].sample_size =
5598                                         edid_caps->audio_modes[i].sample_size;
5599                 }
5600         }
5601
5602         audio_info->flags.all = edid_caps->speaker_flags;
5603
5604         /* TODO: We only check for the progressive mode, check for interlace mode too */
5605         if (drm_connector->latency_present[0]) {
5606                 audio_info->video_latency = drm_connector->video_latency[0];
5607                 audio_info->audio_latency = drm_connector->audio_latency[0];
5608         }
5609
5610         /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
5611
5612 }
5613
5614 static void
5615 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
5616                                       struct drm_display_mode *dst_mode)
5617 {
5618         dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
5619         dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
5620         dst_mode->crtc_clock = src_mode->crtc_clock;
5621         dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
5622         dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
5623         dst_mode->crtc_hsync_start =  src_mode->crtc_hsync_start;
5624         dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
5625         dst_mode->crtc_htotal = src_mode->crtc_htotal;
5626         dst_mode->crtc_hskew = src_mode->crtc_hskew;
5627         dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
5628         dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
5629         dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
5630         dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
5631         dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
5632 }
5633
5634 static void
5635 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
5636                                         const struct drm_display_mode *native_mode,
5637                                         bool scale_enabled)
5638 {
5639         if (scale_enabled) {
5640                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5641         } else if (native_mode->clock == drm_mode->clock &&
5642                         native_mode->htotal == drm_mode->htotal &&
5643                         native_mode->vtotal == drm_mode->vtotal) {
5644                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5645         } else {
5646                 /* no scaling nor amdgpu inserted, no need to patch */
5647         }
5648 }
5649
5650 static struct dc_sink *
5651 create_fake_sink(struct amdgpu_dm_connector *aconnector)
5652 {
5653         struct dc_sink_init_data sink_init_data = { 0 };
5654         struct dc_sink *sink = NULL;
5655
5656         sink_init_data.link = aconnector->dc_link;
5657         sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
5658
5659         sink = dc_sink_create(&sink_init_data);
5660         if (!sink) {
5661                 DRM_ERROR("Failed to create sink!\n");
5662                 return NULL;
5663         }
5664         sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
5665
5666         return sink;
5667 }
5668
5669 static void set_multisync_trigger_params(
5670                 struct dc_stream_state *stream)
5671 {
5672         struct dc_stream_state *master = NULL;
5673
5674         if (stream->triggered_crtc_reset.enabled) {
5675                 master = stream->triggered_crtc_reset.event_source;
5676                 stream->triggered_crtc_reset.event =
5677                         master->timing.flags.VSYNC_POSITIVE_POLARITY ?
5678                         CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING;
5679                 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL;
5680         }
5681 }
5682
5683 static void set_master_stream(struct dc_stream_state *stream_set[],
5684                               int stream_count)
5685 {
5686         int j, highest_rfr = 0, master_stream = 0;
5687
5688         for (j = 0;  j < stream_count; j++) {
5689                 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
5690                         int refresh_rate = 0;
5691
5692                         refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
5693                                 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
5694                         if (refresh_rate > highest_rfr) {
5695                                 highest_rfr = refresh_rate;
5696                                 master_stream = j;
5697                         }
5698                 }
5699         }
5700         for (j = 0;  j < stream_count; j++) {
5701                 if (stream_set[j])
5702                         stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
5703         }
5704 }
5705
5706 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
5707 {
5708         int i = 0;
5709         struct dc_stream_state *stream;
5710
5711         if (context->stream_count < 2)
5712                 return;
5713         for (i = 0; i < context->stream_count ; i++) {
5714                 if (!context->streams[i])
5715                         continue;
5716                 /*
5717                  * TODO: add a function to read AMD VSDB bits and set
5718                  * crtc_sync_master.multi_sync_enabled flag
5719                  * For now it's set to false
5720                  */
5721         }
5722
5723         set_master_stream(context->streams, context->stream_count);
5724
5725         for (i = 0; i < context->stream_count ; i++) {
5726                 stream = context->streams[i];
5727
5728                 if (!stream)
5729                         continue;
5730
5731                 set_multisync_trigger_params(stream);
5732         }
5733 }
5734
5735 /**
5736  * DOC: FreeSync Video
5737  *
5738  * When a userspace application wants to play a video, the content follows a
5739  * standard format definition that usually specifies the FPS for that format.
5740  * The below list illustrates some video format and the expected FPS,
5741  * respectively:
5742  *
5743  * - TV/NTSC (23.976 FPS)
5744  * - Cinema (24 FPS)
5745  * - TV/PAL (25 FPS)
5746  * - TV/NTSC (29.97 FPS)
5747  * - TV/NTSC (30 FPS)
5748  * - Cinema HFR (48 FPS)
5749  * - TV/PAL (50 FPS)
5750  * - Commonly used (60 FPS)
5751  * - Multiples of 24 (48,72,96 FPS)
5752  *
5753  * The list of standards video format is not huge and can be added to the
5754  * connector modeset list beforehand. With that, userspace can leverage
5755  * FreeSync to extends the front porch in order to attain the target refresh
5756  * rate. Such a switch will happen seamlessly, without screen blanking or
5757  * reprogramming of the output in any other way. If the userspace requests a
5758  * modesetting change compatible with FreeSync modes that only differ in the
5759  * refresh rate, DC will skip the full update and avoid blink during the
5760  * transition. For example, the video player can change the modesetting from
5761  * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without
5762  * causing any display blink. This same concept can be applied to a mode
5763  * setting change.
5764  */
5765 static struct drm_display_mode *
5766 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
5767                 bool use_probed_modes)
5768 {
5769         struct drm_display_mode *m, *m_pref = NULL;
5770         u16 current_refresh, highest_refresh;
5771         struct list_head *list_head = use_probed_modes ?
5772                 &aconnector->base.probed_modes :
5773                 &aconnector->base.modes;
5774
5775         if (aconnector->freesync_vid_base.clock != 0)
5776                 return &aconnector->freesync_vid_base;
5777
5778         /* Find the preferred mode */
5779         list_for_each_entry(m, list_head, head) {
5780                 if (m->type & DRM_MODE_TYPE_PREFERRED) {
5781                         m_pref = m;
5782                         break;
5783                 }
5784         }
5785
5786         if (!m_pref) {
5787                 /* Probably an EDID with no preferred mode. Fallback to first entry */
5788                 m_pref = list_first_entry_or_null(
5789                                 &aconnector->base.modes, struct drm_display_mode, head);
5790                 if (!m_pref) {
5791                         DRM_DEBUG_DRIVER("No preferred mode found in EDID\n");
5792                         return NULL;
5793                 }
5794         }
5795
5796         highest_refresh = drm_mode_vrefresh(m_pref);
5797
5798         /*
5799          * Find the mode with highest refresh rate with same resolution.
5800          * For some monitors, preferred mode is not the mode with highest
5801          * supported refresh rate.
5802          */
5803         list_for_each_entry(m, list_head, head) {
5804                 current_refresh  = drm_mode_vrefresh(m);
5805
5806                 if (m->hdisplay == m_pref->hdisplay &&
5807                     m->vdisplay == m_pref->vdisplay &&
5808                     highest_refresh < current_refresh) {
5809                         highest_refresh = current_refresh;
5810                         m_pref = m;
5811                 }
5812         }
5813
5814         drm_mode_copy(&aconnector->freesync_vid_base, m_pref);
5815         return m_pref;
5816 }
5817
5818 static bool is_freesync_video_mode(const struct drm_display_mode *mode,
5819                 struct amdgpu_dm_connector *aconnector)
5820 {
5821         struct drm_display_mode *high_mode;
5822         int timing_diff;
5823
5824         high_mode = get_highest_refresh_rate_mode(aconnector, false);
5825         if (!high_mode || !mode)
5826                 return false;
5827
5828         timing_diff = high_mode->vtotal - mode->vtotal;
5829
5830         if (high_mode->clock == 0 || high_mode->clock != mode->clock ||
5831             high_mode->hdisplay != mode->hdisplay ||
5832             high_mode->vdisplay != mode->vdisplay ||
5833             high_mode->hsync_start != mode->hsync_start ||
5834             high_mode->hsync_end != mode->hsync_end ||
5835             high_mode->htotal != mode->htotal ||
5836             high_mode->hskew != mode->hskew ||
5837             high_mode->vscan != mode->vscan ||
5838             high_mode->vsync_start - mode->vsync_start != timing_diff ||
5839             high_mode->vsync_end - mode->vsync_end != timing_diff)
5840                 return false;
5841         else
5842                 return true;
5843 }
5844
5845 static void update_dsc_caps(struct amdgpu_dm_connector *aconnector,
5846                             struct dc_sink *sink, struct dc_stream_state *stream,
5847                             struct dsc_dec_dpcd_caps *dsc_caps)
5848 {
5849         stream->timing.flags.DSC = 0;
5850         dsc_caps->is_dsc_supported = false;
5851
5852         if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
5853             sink->sink_signal == SIGNAL_TYPE_EDP)) {
5854                 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE ||
5855                         sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
5856                         dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
5857                                 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
5858                                 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
5859                                 dsc_caps);
5860         }
5861 }
5862
5863
5864 static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
5865                                     struct dc_sink *sink, struct dc_stream_state *stream,
5866                                     struct dsc_dec_dpcd_caps *dsc_caps,
5867                                     uint32_t max_dsc_target_bpp_limit_override)
5868 {
5869         const struct dc_link_settings *verified_link_cap = NULL;
5870         u32 link_bw_in_kbps;
5871         u32 edp_min_bpp_x16, edp_max_bpp_x16;
5872         struct dc *dc = sink->ctx->dc;
5873         struct dc_dsc_bw_range bw_range = {0};
5874         struct dc_dsc_config dsc_cfg = {0};
5875         struct dc_dsc_config_options dsc_options = {0};
5876
5877         dc_dsc_get_default_config_option(dc, &dsc_options);
5878         dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5879
5880         verified_link_cap = dc_link_get_link_cap(stream->link);
5881         link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap);
5882         edp_min_bpp_x16 = 8 * 16;
5883         edp_max_bpp_x16 = 8 * 16;
5884
5885         if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel)
5886                 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel;
5887
5888         if (edp_max_bpp_x16 < edp_min_bpp_x16)
5889                 edp_min_bpp_x16 = edp_max_bpp_x16;
5890
5891         if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0],
5892                                 dc->debug.dsc_min_slice_height_override,
5893                                 edp_min_bpp_x16, edp_max_bpp_x16,
5894                                 dsc_caps,
5895                                 &stream->timing,
5896                                 dc_link_get_highest_encoding_format(aconnector->dc_link),
5897                                 &bw_range)) {
5898
5899                 if (bw_range.max_kbps < link_bw_in_kbps) {
5900                         if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5901                                         dsc_caps,
5902                                         &dsc_options,
5903                                         0,
5904                                         &stream->timing,
5905                                         dc_link_get_highest_encoding_format(aconnector->dc_link),
5906                                         &dsc_cfg)) {
5907                                 stream->timing.dsc_cfg = dsc_cfg;
5908                                 stream->timing.flags.DSC = 1;
5909                                 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16;
5910                         }
5911                         return;
5912                 }
5913         }
5914
5915         if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5916                                 dsc_caps,
5917                                 &dsc_options,
5918                                 link_bw_in_kbps,
5919                                 &stream->timing,
5920                                 dc_link_get_highest_encoding_format(aconnector->dc_link),
5921                                 &dsc_cfg)) {
5922                 stream->timing.dsc_cfg = dsc_cfg;
5923                 stream->timing.flags.DSC = 1;
5924         }
5925 }
5926
5927
5928 static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
5929                                         struct dc_sink *sink, struct dc_stream_state *stream,
5930                                         struct dsc_dec_dpcd_caps *dsc_caps)
5931 {
5932         struct drm_connector *drm_connector = &aconnector->base;
5933         u32 link_bandwidth_kbps;
5934         struct dc *dc = sink->ctx->dc;
5935         u32 max_supported_bw_in_kbps, timing_bw_in_kbps;
5936         u32 dsc_max_supported_bw_in_kbps;
5937         u32 max_dsc_target_bpp_limit_override =
5938                 drm_connector->display_info.max_dsc_bpp;
5939         struct dc_dsc_config_options dsc_options = {0};
5940
5941         dc_dsc_get_default_config_option(dc, &dsc_options);
5942         dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5943
5944         link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
5945                                                         dc_link_get_link_cap(aconnector->dc_link));
5946
5947         /* Set DSC policy according to dsc_clock_en */
5948         dc_dsc_policy_set_enable_dsc_when_not_needed(
5949                 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);
5950
5951         if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP &&
5952             !aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&
5953             dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
5954
5955                 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);
5956
5957         } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
5958                 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
5959                         if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5960                                                 dsc_caps,
5961                                                 &dsc_options,
5962                                                 link_bandwidth_kbps,
5963                                                 &stream->timing,
5964                                                 dc_link_get_highest_encoding_format(aconnector->dc_link),
5965                                                 &stream->timing.dsc_cfg)) {
5966                                 stream->timing.flags.DSC = 1;
5967                                 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name);
5968                         }
5969                 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
5970                         timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing,
5971                                         dc_link_get_highest_encoding_format(aconnector->dc_link));
5972                         max_supported_bw_in_kbps = link_bandwidth_kbps;
5973                         dsc_max_supported_bw_in_kbps = link_bandwidth_kbps;
5974
5975                         if (timing_bw_in_kbps > max_supported_bw_in_kbps &&
5976                                         max_supported_bw_in_kbps > 0 &&
5977                                         dsc_max_supported_bw_in_kbps > 0)
5978                                 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5979                                                 dsc_caps,
5980                                                 &dsc_options,
5981                                                 dsc_max_supported_bw_in_kbps,
5982                                                 &stream->timing,
5983                                                 dc_link_get_highest_encoding_format(aconnector->dc_link),
5984                                                 &stream->timing.dsc_cfg)) {
5985                                         stream->timing.flags.DSC = 1;
5986                                         DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n",
5987                                                                          __func__, drm_connector->name);
5988                                 }
5989                 }
5990         }
5991
5992         /* Overwrite the stream flag if DSC is enabled through debugfs */
5993         if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
5994                 stream->timing.flags.DSC = 1;
5995
5996         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
5997                 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
5998
5999         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
6000                 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
6001
6002         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
6003                 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
6004 }
6005
6006 static struct dc_stream_state *
6007 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6008                        const struct drm_display_mode *drm_mode,
6009                        const struct dm_connector_state *dm_state,
6010                        const struct dc_stream_state *old_stream,
6011                        int requested_bpc)
6012 {
6013         struct drm_display_mode *preferred_mode = NULL;
6014         struct drm_connector *drm_connector;
6015         const struct drm_connector_state *con_state = &dm_state->base;
6016         struct dc_stream_state *stream = NULL;
6017         struct drm_display_mode mode;
6018         struct drm_display_mode saved_mode;
6019         struct drm_display_mode *freesync_mode = NULL;
6020         bool native_mode_found = false;
6021         bool recalculate_timing = false;
6022         bool scale = dm_state->scaling != RMX_OFF;
6023         int mode_refresh;
6024         int preferred_refresh = 0;
6025         enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN;
6026         struct dsc_dec_dpcd_caps dsc_caps;
6027
6028         struct dc_sink *sink = NULL;
6029
6030         drm_mode_init(&mode, drm_mode);
6031         memset(&saved_mode, 0, sizeof(saved_mode));
6032
6033         if (aconnector == NULL) {
6034                 DRM_ERROR("aconnector is NULL!\n");
6035                 return stream;
6036         }
6037
6038         drm_connector = &aconnector->base;
6039
6040         if (!aconnector->dc_sink) {
6041                 sink = create_fake_sink(aconnector);
6042                 if (!sink)
6043                         return stream;
6044         } else {
6045                 sink = aconnector->dc_sink;
6046                 dc_sink_retain(sink);
6047         }
6048
6049         stream = dc_create_stream_for_sink(sink);
6050
6051         if (stream == NULL) {
6052                 DRM_ERROR("Failed to create stream for sink!\n");
6053                 goto finish;
6054         }
6055
6056         stream->dm_stream_context = aconnector;
6057
6058         stream->timing.flags.LTE_340MCSC_SCRAMBLE =
6059                 drm_connector->display_info.hdmi.scdc.scrambling.low_rates;
6060
6061         list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
6062                 /* Search for preferred mode */
6063                 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
6064                         native_mode_found = true;
6065                         break;
6066                 }
6067         }
6068         if (!native_mode_found)
6069                 preferred_mode = list_first_entry_or_null(
6070                                 &aconnector->base.modes,
6071                                 struct drm_display_mode,
6072                                 head);
6073
6074         mode_refresh = drm_mode_vrefresh(&mode);
6075
6076         if (preferred_mode == NULL) {
6077                 /*
6078                  * This may not be an error, the use case is when we have no
6079                  * usermode calls to reset and set mode upon hotplug. In this
6080                  * case, we call set mode ourselves to restore the previous mode
6081                  * and the modelist may not be filled in time.
6082                  */
6083                 DRM_DEBUG_DRIVER("No preferred mode found\n");
6084         } else {
6085                 recalculate_timing = is_freesync_video_mode(&mode, aconnector);
6086                 if (recalculate_timing) {
6087                         freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
6088                         drm_mode_copy(&saved_mode, &mode);
6089                         drm_mode_copy(&mode, freesync_mode);
6090                 } else {
6091                         decide_crtc_timing_for_drm_display_mode(
6092                                         &mode, preferred_mode, scale);
6093
6094                         preferred_refresh = drm_mode_vrefresh(preferred_mode);
6095                 }
6096         }
6097
6098         if (recalculate_timing)
6099                 drm_mode_set_crtcinfo(&saved_mode, 0);
6100
6101         /*
6102          * If scaling is enabled and refresh rate didn't change
6103          * we copy the vic and polarities of the old timings
6104          */
6105         if (!scale || mode_refresh != preferred_refresh)
6106                 fill_stream_properties_from_drm_display_mode(
6107                         stream, &mode, &aconnector->base, con_state, NULL,
6108                         requested_bpc);
6109         else
6110                 fill_stream_properties_from_drm_display_mode(
6111                         stream, &mode, &aconnector->base, con_state, old_stream,
6112                         requested_bpc);
6113
6114         if (aconnector->timing_changed) {
6115                 DC_LOG_DEBUG("%s: overriding timing for automated test, bpc %d, changing to %d\n",
6116                                 __func__,
6117                                 stream->timing.display_color_depth,
6118                                 aconnector->timing_requested->display_color_depth);
6119                 stream->timing = *aconnector->timing_requested;
6120         }
6121
6122         /* SST DSC determination policy */
6123         update_dsc_caps(aconnector, sink, stream, &dsc_caps);
6124         if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported)
6125                 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps);
6126
6127         update_stream_scaling_settings(&mode, dm_state, stream);
6128
6129         fill_audio_info(
6130                 &stream->audio_info,
6131                 drm_connector,
6132                 sink);
6133
6134         update_stream_signal(stream, sink);
6135
6136         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
6137                 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);
6138
6139         if (stream->link->psr_settings.psr_feature_enabled || stream->link->replay_settings.replay_feature_enabled) {
6140                 //
6141                 // should decide stream support vsc sdp colorimetry capability
6142                 // before building vsc info packet
6143                 //
6144                 stream->use_vsc_sdp_for_colorimetry = false;
6145                 if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
6146                         stream->use_vsc_sdp_for_colorimetry =
6147                                 aconnector->dc_sink->is_vsc_sdp_colorimetry_supported;
6148                 } else {
6149                         if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
6150                                 stream->use_vsc_sdp_for_colorimetry = true;
6151                 }
6152                 if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22)
6153                         tf = TRANSFER_FUNC_GAMMA_22;
6154                 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);
6155                 aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
6156
6157         }
6158 finish:
6159         dc_sink_release(sink);
6160
6161         return stream;
6162 }
6163
6164 static enum drm_connector_status
6165 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
6166 {
6167         bool connected;
6168         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6169
6170         /*
6171          * Notes:
6172          * 1. This interface is NOT called in context of HPD irq.
6173          * 2. This interface *is called* in context of user-mode ioctl. Which
6174          * makes it a bad place for *any* MST-related activity.
6175          */
6176
6177         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
6178             !aconnector->fake_enable)
6179                 connected = (aconnector->dc_sink != NULL);
6180         else
6181                 connected = (aconnector->base.force == DRM_FORCE_ON ||
6182                                 aconnector->base.force == DRM_FORCE_ON_DIGITAL);
6183
6184         update_subconnector_property(aconnector);
6185
6186         return (connected ? connector_status_connected :
6187                         connector_status_disconnected);
6188 }
6189
6190 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
6191                                             struct drm_connector_state *connector_state,
6192                                             struct drm_property *property,
6193                                             uint64_t val)
6194 {
6195         struct drm_device *dev = connector->dev;
6196         struct amdgpu_device *adev = drm_to_adev(dev);
6197         struct dm_connector_state *dm_old_state =
6198                 to_dm_connector_state(connector->state);
6199         struct dm_connector_state *dm_new_state =
6200                 to_dm_connector_state(connector_state);
6201
6202         int ret = -EINVAL;
6203
6204         if (property == dev->mode_config.scaling_mode_property) {
6205                 enum amdgpu_rmx_type rmx_type;
6206
6207                 switch (val) {
6208                 case DRM_MODE_SCALE_CENTER:
6209                         rmx_type = RMX_CENTER;
6210                         break;
6211                 case DRM_MODE_SCALE_ASPECT:
6212                         rmx_type = RMX_ASPECT;
6213                         break;
6214                 case DRM_MODE_SCALE_FULLSCREEN:
6215                         rmx_type = RMX_FULL;
6216                         break;
6217                 case DRM_MODE_SCALE_NONE:
6218                 default:
6219                         rmx_type = RMX_OFF;
6220                         break;
6221                 }
6222
6223                 if (dm_old_state->scaling == rmx_type)
6224                         return 0;
6225
6226                 dm_new_state->scaling = rmx_type;
6227                 ret = 0;
6228         } else if (property == adev->mode_info.underscan_hborder_property) {
6229                 dm_new_state->underscan_hborder = val;
6230                 ret = 0;
6231         } else if (property == adev->mode_info.underscan_vborder_property) {
6232                 dm_new_state->underscan_vborder = val;
6233                 ret = 0;
6234         } else if (property == adev->mode_info.underscan_property) {
6235                 dm_new_state->underscan_enable = val;
6236                 ret = 0;
6237         } else if (property == adev->mode_info.abm_level_property) {
6238                 dm_new_state->abm_level = val;
6239                 ret = 0;
6240         }
6241
6242         return ret;
6243 }
6244
6245 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
6246                                             const struct drm_connector_state *state,
6247                                             struct drm_property *property,
6248                                             uint64_t *val)
6249 {
6250         struct drm_device *dev = connector->dev;
6251         struct amdgpu_device *adev = drm_to_adev(dev);
6252         struct dm_connector_state *dm_state =
6253                 to_dm_connector_state(state);
6254         int ret = -EINVAL;
6255
6256         if (property == dev->mode_config.scaling_mode_property) {
6257                 switch (dm_state->scaling) {
6258                 case RMX_CENTER:
6259                         *val = DRM_MODE_SCALE_CENTER;
6260                         break;
6261                 case RMX_ASPECT:
6262                         *val = DRM_MODE_SCALE_ASPECT;
6263                         break;
6264                 case RMX_FULL:
6265                         *val = DRM_MODE_SCALE_FULLSCREEN;
6266                         break;
6267                 case RMX_OFF:
6268                 default:
6269                         *val = DRM_MODE_SCALE_NONE;
6270                         break;
6271                 }
6272                 ret = 0;
6273         } else if (property == adev->mode_info.underscan_hborder_property) {
6274                 *val = dm_state->underscan_hborder;
6275                 ret = 0;
6276         } else if (property == adev->mode_info.underscan_vborder_property) {
6277                 *val = dm_state->underscan_vborder;
6278                 ret = 0;
6279         } else if (property == adev->mode_info.underscan_property) {
6280                 *val = dm_state->underscan_enable;
6281                 ret = 0;
6282         } else if (property == adev->mode_info.abm_level_property) {
6283                 *val = dm_state->abm_level;
6284                 ret = 0;
6285         }
6286
6287         return ret;
6288 }
6289
6290 static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
6291 {
6292         struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
6293
6294         drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
6295 }
6296
6297 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
6298 {
6299         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6300         struct amdgpu_device *adev = drm_to_adev(connector->dev);
6301         struct amdgpu_display_manager *dm = &adev->dm;
6302
6303         /*
6304          * Call only if mst_mgr was initialized before since it's not done
6305          * for all connector types.
6306          */
6307         if (aconnector->mst_mgr.dev)
6308                 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);
6309
6310         if (aconnector->bl_idx != -1) {
6311                 backlight_device_unregister(dm->backlight_dev[aconnector->bl_idx]);
6312                 dm->backlight_dev[aconnector->bl_idx] = NULL;
6313         }
6314
6315         if (aconnector->dc_em_sink)
6316                 dc_sink_release(aconnector->dc_em_sink);
6317         aconnector->dc_em_sink = NULL;
6318         if (aconnector->dc_sink)
6319                 dc_sink_release(aconnector->dc_sink);
6320         aconnector->dc_sink = NULL;
6321
6322         drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
6323         drm_connector_unregister(connector);
6324         drm_connector_cleanup(connector);
6325         if (aconnector->i2c) {
6326                 i2c_del_adapter(&aconnector->i2c->base);
6327                 kfree(aconnector->i2c);
6328         }
6329         kfree(aconnector->dm_dp_aux.aux.name);
6330
6331         kfree(connector);
6332 }
6333
6334 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
6335 {
6336         struct dm_connector_state *state =
6337                 to_dm_connector_state(connector->state);
6338
6339         if (connector->state)
6340                 __drm_atomic_helper_connector_destroy_state(connector->state);
6341
6342         kfree(state);
6343
6344         state = kzalloc(sizeof(*state), GFP_KERNEL);
6345
6346         if (state) {
6347                 state->scaling = RMX_OFF;
6348                 state->underscan_enable = false;
6349                 state->underscan_hborder = 0;
6350                 state->underscan_vborder = 0;
6351                 state->base.max_requested_bpc = 8;
6352                 state->vcpi_slots = 0;
6353                 state->pbn = 0;
6354
6355                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
6356                         state->abm_level = amdgpu_dm_abm_level;
6357
6358                 __drm_atomic_helper_connector_reset(connector, &state->base);
6359         }
6360 }
6361
6362 struct drm_connector_state *
6363 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
6364 {
6365         struct dm_connector_state *state =
6366                 to_dm_connector_state(connector->state);
6367
6368         struct dm_connector_state *new_state =
6369                         kmemdup(state, sizeof(*state), GFP_KERNEL);
6370
6371         if (!new_state)
6372                 return NULL;
6373
6374         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
6375
6376         new_state->freesync_capable = state->freesync_capable;
6377         new_state->abm_level = state->abm_level;
6378         new_state->scaling = state->scaling;
6379         new_state->underscan_enable = state->underscan_enable;
6380         new_state->underscan_hborder = state->underscan_hborder;
6381         new_state->underscan_vborder = state->underscan_vborder;
6382         new_state->vcpi_slots = state->vcpi_slots;
6383         new_state->pbn = state->pbn;
6384         return &new_state->base;
6385 }
6386
6387 static int
6388 amdgpu_dm_connector_late_register(struct drm_connector *connector)
6389 {
6390         struct amdgpu_dm_connector *amdgpu_dm_connector =
6391                 to_amdgpu_dm_connector(connector);
6392         int r;
6393
6394         amdgpu_dm_register_backlight_device(amdgpu_dm_connector);
6395
6396         if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
6397             (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
6398                 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
6399                 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
6400                 if (r)
6401                         return r;
6402         }
6403
6404 #if defined(CONFIG_DEBUG_FS)
6405         connector_debugfs_init(amdgpu_dm_connector);
6406 #endif
6407
6408         return 0;
6409 }
6410
6411 static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector)
6412 {
6413         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6414         struct dc_link *dc_link = aconnector->dc_link;
6415         struct dc_sink *dc_em_sink = aconnector->dc_em_sink;
6416         struct edid *edid;
6417
6418         if (!connector->edid_override)
6419                 return;
6420
6421         drm_edid_override_connector_update(&aconnector->base);
6422         edid = aconnector->base.edid_blob_ptr->data;
6423         aconnector->edid = edid;
6424
6425         /* Update emulated (virtual) sink's EDID */
6426         if (dc_em_sink && dc_link) {
6427                 memset(&dc_em_sink->edid_caps, 0, sizeof(struct dc_edid_caps));
6428                 memmove(dc_em_sink->dc_edid.raw_edid, edid, (edid->extensions + 1) * EDID_LENGTH);
6429                 dm_helpers_parse_edid_caps(
6430                         dc_link,
6431                         &dc_em_sink->dc_edid,
6432                         &dc_em_sink->edid_caps);
6433         }
6434 }
6435
6436 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
6437         .reset = amdgpu_dm_connector_funcs_reset,
6438         .detect = amdgpu_dm_connector_detect,
6439         .fill_modes = drm_helper_probe_single_connector_modes,
6440         .destroy = amdgpu_dm_connector_destroy,
6441         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
6442         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6443         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
6444         .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
6445         .late_register = amdgpu_dm_connector_late_register,
6446         .early_unregister = amdgpu_dm_connector_unregister,
6447         .force = amdgpu_dm_connector_funcs_force
6448 };
6449
6450 static int get_modes(struct drm_connector *connector)
6451 {
6452         return amdgpu_dm_connector_get_modes(connector);
6453 }
6454
6455 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
6456 {
6457         struct dc_sink_init_data init_params = {
6458                         .link = aconnector->dc_link,
6459                         .sink_signal = SIGNAL_TYPE_VIRTUAL
6460         };
6461         struct edid *edid;
6462
6463         if (!aconnector->base.edid_blob_ptr) {
6464                 /* if connector->edid_override valid, pass
6465                  * it to edid_override to edid_blob_ptr
6466                  */
6467
6468                 drm_edid_override_connector_update(&aconnector->base);
6469
6470                 if (!aconnector->base.edid_blob_ptr) {
6471                         DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
6472                                         aconnector->base.name);
6473
6474                         aconnector->base.force = DRM_FORCE_OFF;
6475                         return;
6476                 }
6477         }
6478
6479         edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
6480
6481         aconnector->edid = edid;
6482
6483         aconnector->dc_em_sink = dc_link_add_remote_sink(
6484                 aconnector->dc_link,
6485                 (uint8_t *)edid,
6486                 (edid->extensions + 1) * EDID_LENGTH,
6487                 &init_params);
6488
6489         if (aconnector->base.force == DRM_FORCE_ON) {
6490                 aconnector->dc_sink = aconnector->dc_link->local_sink ?
6491                 aconnector->dc_link->local_sink :
6492                 aconnector->dc_em_sink;
6493                 dc_sink_retain(aconnector->dc_sink);
6494         }
6495 }
6496
6497 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
6498 {
6499         struct dc_link *link = (struct dc_link *)aconnector->dc_link;
6500
6501         /*
6502          * In case of headless boot with force on for DP managed connector
6503          * Those settings have to be != 0 to get initial modeset
6504          */
6505         if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
6506                 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
6507                 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
6508         }
6509
6510         create_eml_sink(aconnector);
6511 }
6512
6513 static enum dc_status dm_validate_stream_and_context(struct dc *dc,
6514                                                 struct dc_stream_state *stream)
6515 {
6516         enum dc_status dc_result = DC_ERROR_UNEXPECTED;
6517         struct dc_plane_state *dc_plane_state = NULL;
6518         struct dc_state *dc_state = NULL;
6519
6520         if (!stream)
6521                 goto cleanup;
6522
6523         dc_plane_state = dc_create_plane_state(dc);
6524         if (!dc_plane_state)
6525                 goto cleanup;
6526
6527         dc_state = dc_create_state(dc);
6528         if (!dc_state)
6529                 goto cleanup;
6530
6531         /* populate stream to plane */
6532         dc_plane_state->src_rect.height  = stream->src.height;
6533         dc_plane_state->src_rect.width   = stream->src.width;
6534         dc_plane_state->dst_rect.height  = stream->src.height;
6535         dc_plane_state->dst_rect.width   = stream->src.width;
6536         dc_plane_state->clip_rect.height = stream->src.height;
6537         dc_plane_state->clip_rect.width  = stream->src.width;
6538         dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256;
6539         dc_plane_state->plane_size.surface_size.height = stream->src.height;
6540         dc_plane_state->plane_size.surface_size.width  = stream->src.width;
6541         dc_plane_state->plane_size.chroma_size.height  = stream->src.height;
6542         dc_plane_state->plane_size.chroma_size.width   = stream->src.width;
6543         dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
6544         dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN;
6545         dc_plane_state->rotation = ROTATION_ANGLE_0;
6546         dc_plane_state->is_tiling_rotated = false;
6547         dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL;
6548
6549         dc_result = dc_validate_stream(dc, stream);
6550         if (dc_result == DC_OK)
6551                 dc_result = dc_validate_plane(dc, dc_plane_state);
6552
6553         if (dc_result == DC_OK)
6554                 dc_result = dc_add_stream_to_ctx(dc, dc_state, stream);
6555
6556         if (dc_result == DC_OK && !dc_add_plane_to_context(
6557                                                 dc,
6558                                                 stream,
6559                                                 dc_plane_state,
6560                                                 dc_state))
6561                 dc_result = DC_FAIL_ATTACH_SURFACES;
6562
6563         if (dc_result == DC_OK)
6564                 dc_result = dc_validate_global_state(dc, dc_state, true);
6565
6566 cleanup:
6567         if (dc_state)
6568                 dc_release_state(dc_state);
6569
6570         if (dc_plane_state)
6571                 dc_plane_state_release(dc_plane_state);
6572
6573         return dc_result;
6574 }
6575
6576 struct dc_stream_state *
6577 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6578                                 const struct drm_display_mode *drm_mode,
6579                                 const struct dm_connector_state *dm_state,
6580                                 const struct dc_stream_state *old_stream)
6581 {
6582         struct drm_connector *connector = &aconnector->base;
6583         struct amdgpu_device *adev = drm_to_adev(connector->dev);
6584         struct dc_stream_state *stream;
6585         const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL;
6586         int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8;
6587         enum dc_status dc_result = DC_OK;
6588
6589         do {
6590                 stream = create_stream_for_sink(aconnector, drm_mode,
6591                                                 dm_state, old_stream,
6592                                                 requested_bpc);
6593                 if (stream == NULL) {
6594                         DRM_ERROR("Failed to create stream for sink!\n");
6595                         break;
6596                 }
6597
6598                 dc_result = dc_validate_stream(adev->dm.dc, stream);
6599                 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
6600                         dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream);
6601
6602                 if (dc_result == DC_OK)
6603                         dc_result = dm_validate_stream_and_context(adev->dm.dc, stream);
6604
6605                 if (dc_result != DC_OK) {
6606                         DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",
6607                                       drm_mode->hdisplay,
6608                                       drm_mode->vdisplay,
6609                                       drm_mode->clock,
6610                                       dc_result,
6611                                       dc_status_to_str(dc_result));
6612
6613                         dc_stream_release(stream);
6614                         stream = NULL;
6615                         requested_bpc -= 2; /* lower bpc to retry validation */
6616                 }
6617
6618         } while (stream == NULL && requested_bpc >= 6);
6619
6620         if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) {
6621                 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n");
6622
6623                 aconnector->force_yuv420_output = true;
6624                 stream = create_validate_stream_for_sink(aconnector, drm_mode,
6625                                                 dm_state, old_stream);
6626                 aconnector->force_yuv420_output = false;
6627         }
6628
6629         return stream;
6630 }
6631
6632 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
6633                                    struct drm_display_mode *mode)
6634 {
6635         int result = MODE_ERROR;
6636         struct dc_sink *dc_sink;
6637         /* TODO: Unhardcode stream count */
6638         struct dc_stream_state *stream;
6639         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6640
6641         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
6642                         (mode->flags & DRM_MODE_FLAG_DBLSCAN))
6643                 return result;
6644
6645         /*
6646          * Only run this the first time mode_valid is called to initilialize
6647          * EDID mgmt
6648          */
6649         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
6650                 !aconnector->dc_em_sink)
6651                 handle_edid_mgmt(aconnector);
6652
6653         dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
6654
6655         if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL &&
6656                                 aconnector->base.force != DRM_FORCE_ON) {
6657                 DRM_ERROR("dc_sink is NULL!\n");
6658                 goto fail;
6659         }
6660
6661         drm_mode_set_crtcinfo(mode, 0);
6662
6663         stream = create_validate_stream_for_sink(aconnector, mode,
6664                                                  to_dm_connector_state(connector->state),
6665                                                  NULL);
6666         if (stream) {
6667                 dc_stream_release(stream);
6668                 result = MODE_OK;
6669         }
6670
6671 fail:
6672         /* TODO: error handling*/
6673         return result;
6674 }
6675
6676 static int fill_hdr_info_packet(const struct drm_connector_state *state,
6677                                 struct dc_info_packet *out)
6678 {
6679         struct hdmi_drm_infoframe frame;
6680         unsigned char buf[30]; /* 26 + 4 */
6681         ssize_t len;
6682         int ret, i;
6683
6684         memset(out, 0, sizeof(*out));
6685
6686         if (!state->hdr_output_metadata)
6687                 return 0;
6688
6689         ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
6690         if (ret)
6691                 return ret;
6692
6693         len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
6694         if (len < 0)
6695                 return (int)len;
6696
6697         /* Static metadata is a fixed 26 bytes + 4 byte header. */
6698         if (len != 30)
6699                 return -EINVAL;
6700
6701         /* Prepare the infopacket for DC. */
6702         switch (state->connector->connector_type) {
6703         case DRM_MODE_CONNECTOR_HDMIA:
6704                 out->hb0 = 0x87; /* type */
6705                 out->hb1 = 0x01; /* version */
6706                 out->hb2 = 0x1A; /* length */
6707                 out->sb[0] = buf[3]; /* checksum */
6708                 i = 1;
6709                 break;
6710
6711         case DRM_MODE_CONNECTOR_DisplayPort:
6712         case DRM_MODE_CONNECTOR_eDP:
6713                 out->hb0 = 0x00; /* sdp id, zero */
6714                 out->hb1 = 0x87; /* type */
6715                 out->hb2 = 0x1D; /* payload len - 1 */
6716                 out->hb3 = (0x13 << 2); /* sdp version */
6717                 out->sb[0] = 0x01; /* version */
6718                 out->sb[1] = 0x1A; /* length */
6719                 i = 2;
6720                 break;
6721
6722         default:
6723                 return -EINVAL;
6724         }
6725
6726         memcpy(&out->sb[i], &buf[4], 26);
6727         out->valid = true;
6728
6729         print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
6730                        sizeof(out->sb), false);
6731
6732         return 0;
6733 }
6734
6735 static int
6736 amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
6737                                  struct drm_atomic_state *state)
6738 {
6739         struct drm_connector_state *new_con_state =
6740                 drm_atomic_get_new_connector_state(state, conn);
6741         struct drm_connector_state *old_con_state =
6742                 drm_atomic_get_old_connector_state(state, conn);
6743         struct drm_crtc *crtc = new_con_state->crtc;
6744         struct drm_crtc_state *new_crtc_state;
6745         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn);
6746         int ret;
6747
6748         trace_amdgpu_dm_connector_atomic_check(new_con_state);
6749
6750         if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
6751                 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr);
6752                 if (ret < 0)
6753                         return ret;
6754         }
6755
6756         if (!crtc)
6757                 return 0;
6758
6759         if (new_con_state->colorspace != old_con_state->colorspace) {
6760                 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6761                 if (IS_ERR(new_crtc_state))
6762                         return PTR_ERR(new_crtc_state);
6763
6764                 new_crtc_state->mode_changed = true;
6765         }
6766
6767         if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) {
6768                 struct dc_info_packet hdr_infopacket;
6769
6770                 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
6771                 if (ret)
6772                         return ret;
6773
6774                 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6775                 if (IS_ERR(new_crtc_state))
6776                         return PTR_ERR(new_crtc_state);
6777
6778                 /*
6779                  * DC considers the stream backends changed if the
6780                  * static metadata changes. Forcing the modeset also
6781                  * gives a simple way for userspace to switch from
6782                  * 8bpc to 10bpc when setting the metadata to enter
6783                  * or exit HDR.
6784                  *
6785                  * Changing the static metadata after it's been
6786                  * set is permissible, however. So only force a
6787                  * modeset if we're entering or exiting HDR.
6788                  */
6789                 new_crtc_state->mode_changed = new_crtc_state->mode_changed ||
6790                         !old_con_state->hdr_output_metadata ||
6791                         !new_con_state->hdr_output_metadata;
6792         }
6793
6794         return 0;
6795 }
6796
6797 static const struct drm_connector_helper_funcs
6798 amdgpu_dm_connector_helper_funcs = {
6799         /*
6800          * If hotplugging a second bigger display in FB Con mode, bigger resolution
6801          * modes will be filtered by drm_mode_validate_size(), and those modes
6802          * are missing after user start lightdm. So we need to renew modes list.
6803          * in get_modes call back, not just return the modes count
6804          */
6805         .get_modes = get_modes,
6806         .mode_valid = amdgpu_dm_connector_mode_valid,
6807         .atomic_check = amdgpu_dm_connector_atomic_check,
6808 };
6809
6810 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
6811 {
6812
6813 }
6814
6815 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth)
6816 {
6817         switch (display_color_depth) {
6818         case COLOR_DEPTH_666:
6819                 return 6;
6820         case COLOR_DEPTH_888:
6821                 return 8;
6822         case COLOR_DEPTH_101010:
6823                 return 10;
6824         case COLOR_DEPTH_121212:
6825                 return 12;
6826         case COLOR_DEPTH_141414:
6827                 return 14;
6828         case COLOR_DEPTH_161616:
6829                 return 16;
6830         default:
6831                 break;
6832         }
6833         return 0;
6834 }
6835
6836 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
6837                                           struct drm_crtc_state *crtc_state,
6838                                           struct drm_connector_state *conn_state)
6839 {
6840         struct drm_atomic_state *state = crtc_state->state;
6841         struct drm_connector *connector = conn_state->connector;
6842         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6843         struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state);
6844         const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
6845         struct drm_dp_mst_topology_mgr *mst_mgr;
6846         struct drm_dp_mst_port *mst_port;
6847         struct drm_dp_mst_topology_state *mst_state;
6848         enum dc_color_depth color_depth;
6849         int clock, bpp = 0;
6850         bool is_y420 = false;
6851
6852         if (!aconnector->mst_output_port)
6853                 return 0;
6854
6855         mst_port = aconnector->mst_output_port;
6856         mst_mgr = &aconnector->mst_root->mst_mgr;
6857
6858         if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
6859                 return 0;
6860
6861         mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr);
6862         if (IS_ERR(mst_state))
6863                 return PTR_ERR(mst_state);
6864
6865         if (!mst_state->pbn_div)
6866                 mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link);
6867
6868         if (!state->duplicated) {
6869                 int max_bpc = conn_state->max_requested_bpc;
6870
6871                 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
6872                           aconnector->force_yuv420_output;
6873                 color_depth = convert_color_depth_from_display_info(connector,
6874                                                                     is_y420,
6875                                                                     max_bpc);
6876                 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
6877                 clock = adjusted_mode->clock;
6878                 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
6879         }
6880
6881         dm_new_connector_state->vcpi_slots =
6882                 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port,
6883                                               dm_new_connector_state->pbn);
6884         if (dm_new_connector_state->vcpi_slots < 0) {
6885                 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
6886                 return dm_new_connector_state->vcpi_slots;
6887         }
6888         return 0;
6889 }
6890
6891 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
6892         .disable = dm_encoder_helper_disable,
6893         .atomic_check = dm_encoder_helper_atomic_check
6894 };
6895
6896 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
6897                                             struct dc_state *dc_state,
6898                                             struct dsc_mst_fairness_vars *vars)
6899 {
6900         struct dc_stream_state *stream = NULL;
6901         struct drm_connector *connector;
6902         struct drm_connector_state *new_con_state;
6903         struct amdgpu_dm_connector *aconnector;
6904         struct dm_connector_state *dm_conn_state;
6905         int i, j, ret;
6906         int vcpi, pbn_div, pbn, slot_num = 0;
6907
6908         for_each_new_connector_in_state(state, connector, new_con_state, i) {
6909
6910                 aconnector = to_amdgpu_dm_connector(connector);
6911
6912                 if (!aconnector->mst_output_port)
6913                         continue;
6914
6915                 if (!new_con_state || !new_con_state->crtc)
6916                         continue;
6917
6918                 dm_conn_state = to_dm_connector_state(new_con_state);
6919
6920                 for (j = 0; j < dc_state->stream_count; j++) {
6921                         stream = dc_state->streams[j];
6922                         if (!stream)
6923                                 continue;
6924
6925                         if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector)
6926                                 break;
6927
6928                         stream = NULL;
6929                 }
6930
6931                 if (!stream)
6932                         continue;
6933
6934                 pbn_div = dm_mst_get_pbn_divider(stream->link);
6935                 /* pbn is calculated by compute_mst_dsc_configs_for_state*/
6936                 for (j = 0; j < dc_state->stream_count; j++) {
6937                         if (vars[j].aconnector == aconnector) {
6938                                 pbn = vars[j].pbn;
6939                                 break;
6940                         }
6941                 }
6942
6943                 if (j == dc_state->stream_count)
6944                         continue;
6945
6946                 slot_num = DIV_ROUND_UP(pbn, pbn_div);
6947
6948                 if (stream->timing.flags.DSC != 1) {
6949                         dm_conn_state->pbn = pbn;
6950                         dm_conn_state->vcpi_slots = slot_num;
6951
6952                         ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port,
6953                                                            dm_conn_state->pbn, false);
6954                         if (ret < 0)
6955                                 return ret;
6956
6957                         continue;
6958                 }
6959
6960                 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true);
6961                 if (vcpi < 0)
6962                         return vcpi;
6963
6964                 dm_conn_state->pbn = pbn;
6965                 dm_conn_state->vcpi_slots = vcpi;
6966         }
6967         return 0;
6968 }
6969
6970 static int to_drm_connector_type(enum signal_type st)
6971 {
6972         switch (st) {
6973         case SIGNAL_TYPE_HDMI_TYPE_A:
6974                 return DRM_MODE_CONNECTOR_HDMIA;
6975         case SIGNAL_TYPE_EDP:
6976                 return DRM_MODE_CONNECTOR_eDP;
6977         case SIGNAL_TYPE_LVDS:
6978                 return DRM_MODE_CONNECTOR_LVDS;
6979         case SIGNAL_TYPE_RGB:
6980                 return DRM_MODE_CONNECTOR_VGA;
6981         case SIGNAL_TYPE_DISPLAY_PORT:
6982         case SIGNAL_TYPE_DISPLAY_PORT_MST:
6983                 return DRM_MODE_CONNECTOR_DisplayPort;
6984         case SIGNAL_TYPE_DVI_DUAL_LINK:
6985         case SIGNAL_TYPE_DVI_SINGLE_LINK:
6986                 return DRM_MODE_CONNECTOR_DVID;
6987         case SIGNAL_TYPE_VIRTUAL:
6988                 return DRM_MODE_CONNECTOR_VIRTUAL;
6989
6990         default:
6991                 return DRM_MODE_CONNECTOR_Unknown;
6992         }
6993 }
6994
6995 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
6996 {
6997         struct drm_encoder *encoder;
6998
6999         /* There is only one encoder per connector */
7000         drm_connector_for_each_possible_encoder(connector, encoder)
7001                 return encoder;
7002
7003         return NULL;
7004 }
7005
7006 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
7007 {
7008         struct drm_encoder *encoder;
7009         struct amdgpu_encoder *amdgpu_encoder;
7010
7011         encoder = amdgpu_dm_connector_to_encoder(connector);
7012
7013         if (encoder == NULL)
7014                 return;
7015
7016         amdgpu_encoder = to_amdgpu_encoder(encoder);
7017
7018         amdgpu_encoder->native_mode.clock = 0;
7019
7020         if (!list_empty(&connector->probed_modes)) {
7021                 struct drm_display_mode *preferred_mode = NULL;
7022
7023                 list_for_each_entry(preferred_mode,
7024                                     &connector->probed_modes,
7025                                     head) {
7026                         if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
7027                                 amdgpu_encoder->native_mode = *preferred_mode;
7028
7029                         break;
7030                 }
7031
7032         }
7033 }
7034
7035 static struct drm_display_mode *
7036 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
7037                              char *name,
7038                              int hdisplay, int vdisplay)
7039 {
7040         struct drm_device *dev = encoder->dev;
7041         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
7042         struct drm_display_mode *mode = NULL;
7043         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
7044
7045         mode = drm_mode_duplicate(dev, native_mode);
7046
7047         if (mode == NULL)
7048                 return NULL;
7049
7050         mode->hdisplay = hdisplay;
7051         mode->vdisplay = vdisplay;
7052         mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7053         strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
7054
7055         return mode;
7056
7057 }
7058
7059 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
7060                                                  struct drm_connector *connector)
7061 {
7062         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
7063         struct drm_display_mode *mode = NULL;
7064         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
7065         struct amdgpu_dm_connector *amdgpu_dm_connector =
7066                                 to_amdgpu_dm_connector(connector);
7067         int i;
7068         int n;
7069         struct mode_size {
7070                 char name[DRM_DISPLAY_MODE_LEN];
7071                 int w;
7072                 int h;
7073         } common_modes[] = {
7074                 {  "640x480",  640,  480},
7075                 {  "800x600",  800,  600},
7076                 { "1024x768", 1024,  768},
7077                 { "1280x720", 1280,  720},
7078                 { "1280x800", 1280,  800},
7079                 {"1280x1024", 1280, 1024},
7080                 { "1440x900", 1440,  900},
7081                 {"1680x1050", 1680, 1050},
7082                 {"1600x1200", 1600, 1200},
7083                 {"1920x1080", 1920, 1080},
7084                 {"1920x1200", 1920, 1200}
7085         };
7086
7087         n = ARRAY_SIZE(common_modes);
7088
7089         for (i = 0; i < n; i++) {
7090                 struct drm_display_mode *curmode = NULL;
7091                 bool mode_existed = false;
7092
7093                 if (common_modes[i].w > native_mode->hdisplay ||
7094                     common_modes[i].h > native_mode->vdisplay ||
7095                    (common_modes[i].w == native_mode->hdisplay &&
7096                     common_modes[i].h == native_mode->vdisplay))
7097                         continue;
7098
7099                 list_for_each_entry(curmode, &connector->probed_modes, head) {
7100                         if (common_modes[i].w == curmode->hdisplay &&
7101                             common_modes[i].h == curmode->vdisplay) {
7102                                 mode_existed = true;
7103                                 break;
7104                         }
7105                 }
7106
7107                 if (mode_existed)
7108                         continue;
7109
7110                 mode = amdgpu_dm_create_common_mode(encoder,
7111                                 common_modes[i].name, common_modes[i].w,
7112                                 common_modes[i].h);
7113                 if (!mode)
7114                         continue;
7115
7116                 drm_mode_probed_add(connector, mode);
7117                 amdgpu_dm_connector->num_modes++;
7118         }
7119 }
7120
7121 static void amdgpu_set_panel_orientation(struct drm_connector *connector)
7122 {
7123         struct drm_encoder *encoder;
7124         struct amdgpu_encoder *amdgpu_encoder;
7125         const struct drm_display_mode *native_mode;
7126
7127         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
7128             connector->connector_type != DRM_MODE_CONNECTOR_LVDS)
7129                 return;
7130
7131         mutex_lock(&connector->dev->mode_config.mutex);
7132         amdgpu_dm_connector_get_modes(connector);
7133         mutex_unlock(&connector->dev->mode_config.mutex);
7134
7135         encoder = amdgpu_dm_connector_to_encoder(connector);
7136         if (!encoder)
7137                 return;
7138
7139         amdgpu_encoder = to_amdgpu_encoder(encoder);
7140
7141         native_mode = &amdgpu_encoder->native_mode;
7142         if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0)
7143                 return;
7144
7145         drm_connector_set_panel_orientation_with_quirk(connector,
7146                                                        DRM_MODE_PANEL_ORIENTATION_UNKNOWN,
7147                                                        native_mode->hdisplay,
7148                                                        native_mode->vdisplay);
7149 }
7150
7151 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
7152                                               struct edid *edid)
7153 {
7154         struct amdgpu_dm_connector *amdgpu_dm_connector =
7155                         to_amdgpu_dm_connector(connector);
7156
7157         if (edid) {
7158                 /* empty probed_modes */
7159                 INIT_LIST_HEAD(&connector->probed_modes);
7160                 amdgpu_dm_connector->num_modes =
7161                                 drm_add_edid_modes(connector, edid);
7162
7163                 /* sorting the probed modes before calling function
7164                  * amdgpu_dm_get_native_mode() since EDID can have
7165                  * more than one preferred mode. The modes that are
7166                  * later in the probed mode list could be of higher
7167                  * and preferred resolution. For example, 3840x2160
7168                  * resolution in base EDID preferred timing and 4096x2160
7169                  * preferred resolution in DID extension block later.
7170                  */
7171                 drm_mode_sort(&connector->probed_modes);
7172                 amdgpu_dm_get_native_mode(connector);
7173
7174                 /* Freesync capabilities are reset by calling
7175                  * drm_add_edid_modes() and need to be
7176                  * restored here.
7177                  */
7178                 amdgpu_dm_update_freesync_caps(connector, edid);
7179         } else {
7180                 amdgpu_dm_connector->num_modes = 0;
7181         }
7182 }
7183
7184 static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector,
7185                               struct drm_display_mode *mode)
7186 {
7187         struct drm_display_mode *m;
7188
7189         list_for_each_entry(m, &aconnector->base.probed_modes, head) {
7190                 if (drm_mode_equal(m, mode))
7191                         return true;
7192         }
7193
7194         return false;
7195 }
7196
7197 static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)
7198 {
7199         const struct drm_display_mode *m;
7200         struct drm_display_mode *new_mode;
7201         uint i;
7202         u32 new_modes_count = 0;
7203
7204         /* Standard FPS values
7205          *
7206          * 23.976       - TV/NTSC
7207          * 24           - Cinema
7208          * 25           - TV/PAL
7209          * 29.97        - TV/NTSC
7210          * 30           - TV/NTSC
7211          * 48           - Cinema HFR
7212          * 50           - TV/PAL
7213          * 60           - Commonly used
7214          * 48,72,96,120 - Multiples of 24
7215          */
7216         static const u32 common_rates[] = {
7217                 23976, 24000, 25000, 29970, 30000,
7218                 48000, 50000, 60000, 72000, 96000, 120000
7219         };
7220
7221         /*
7222          * Find mode with highest refresh rate with the same resolution
7223          * as the preferred mode. Some monitors report a preferred mode
7224          * with lower resolution than the highest refresh rate supported.
7225          */
7226
7227         m = get_highest_refresh_rate_mode(aconnector, true);
7228         if (!m)
7229                 return 0;
7230
7231         for (i = 0; i < ARRAY_SIZE(common_rates); i++) {
7232                 u64 target_vtotal, target_vtotal_diff;
7233                 u64 num, den;
7234
7235                 if (drm_mode_vrefresh(m) * 1000 < common_rates[i])
7236                         continue;
7237
7238                 if (common_rates[i] < aconnector->min_vfreq * 1000 ||
7239                     common_rates[i] > aconnector->max_vfreq * 1000)
7240                         continue;
7241
7242                 num = (unsigned long long)m->clock * 1000 * 1000;
7243                 den = common_rates[i] * (unsigned long long)m->htotal;
7244                 target_vtotal = div_u64(num, den);
7245                 target_vtotal_diff = target_vtotal - m->vtotal;
7246
7247                 /* Check for illegal modes */
7248                 if (m->vsync_start + target_vtotal_diff < m->vdisplay ||
7249                     m->vsync_end + target_vtotal_diff < m->vsync_start ||
7250                     m->vtotal + target_vtotal_diff < m->vsync_end)
7251                         continue;
7252
7253                 new_mode = drm_mode_duplicate(aconnector->base.dev, m);
7254                 if (!new_mode)
7255                         goto out;
7256
7257                 new_mode->vtotal += (u16)target_vtotal_diff;
7258                 new_mode->vsync_start += (u16)target_vtotal_diff;
7259                 new_mode->vsync_end += (u16)target_vtotal_diff;
7260                 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7261                 new_mode->type |= DRM_MODE_TYPE_DRIVER;
7262
7263                 if (!is_duplicate_mode(aconnector, new_mode)) {
7264                         drm_mode_probed_add(&aconnector->base, new_mode);
7265                         new_modes_count += 1;
7266                 } else
7267                         drm_mode_destroy(aconnector->base.dev, new_mode);
7268         }
7269  out:
7270         return new_modes_count;
7271 }
7272
7273 static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector,
7274                                                    struct edid *edid)
7275 {
7276         struct amdgpu_dm_connector *amdgpu_dm_connector =
7277                 to_amdgpu_dm_connector(connector);
7278
7279         if (!edid)
7280                 return;
7281
7282         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
7283                 amdgpu_dm_connector->num_modes +=
7284                         add_fs_modes(amdgpu_dm_connector);
7285 }
7286
7287 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
7288 {
7289         struct amdgpu_dm_connector *amdgpu_dm_connector =
7290                         to_amdgpu_dm_connector(connector);
7291         struct drm_encoder *encoder;
7292         struct edid *edid = amdgpu_dm_connector->edid;
7293         struct dc_link_settings *verified_link_cap =
7294                         &amdgpu_dm_connector->dc_link->verified_link_cap;
7295         const struct dc *dc = amdgpu_dm_connector->dc_link->dc;
7296
7297         encoder = amdgpu_dm_connector_to_encoder(connector);
7298
7299         if (!drm_edid_is_valid(edid)) {
7300                 amdgpu_dm_connector->num_modes =
7301                                 drm_add_modes_noedid(connector, 640, 480);
7302                 if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING)
7303                         amdgpu_dm_connector->num_modes +=
7304                                 drm_add_modes_noedid(connector, 1920, 1080);
7305         } else {
7306                 amdgpu_dm_connector_ddc_get_modes(connector, edid);
7307                 amdgpu_dm_connector_add_common_modes(encoder, connector);
7308                 amdgpu_dm_connector_add_freesync_modes(connector, edid);
7309         }
7310         amdgpu_dm_fbc_init(connector);
7311
7312         return amdgpu_dm_connector->num_modes;
7313 }
7314
7315 static const u32 supported_colorspaces =
7316         BIT(DRM_MODE_COLORIMETRY_BT709_YCC) |
7317         BIT(DRM_MODE_COLORIMETRY_OPRGB) |
7318         BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) |
7319         BIT(DRM_MODE_COLORIMETRY_BT2020_YCC);
7320
7321 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
7322                                      struct amdgpu_dm_connector *aconnector,
7323                                      int connector_type,
7324                                      struct dc_link *link,
7325                                      int link_index)
7326 {
7327         struct amdgpu_device *adev = drm_to_adev(dm->ddev);
7328
7329         /*
7330          * Some of the properties below require access to state, like bpc.
7331          * Allocate some default initial connector state with our reset helper.
7332          */
7333         if (aconnector->base.funcs->reset)
7334                 aconnector->base.funcs->reset(&aconnector->base);
7335
7336         aconnector->connector_id = link_index;
7337         aconnector->bl_idx = -1;
7338         aconnector->dc_link = link;
7339         aconnector->base.interlace_allowed = false;
7340         aconnector->base.doublescan_allowed = false;
7341         aconnector->base.stereo_allowed = false;
7342         aconnector->base.dpms = DRM_MODE_DPMS_OFF;
7343         aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
7344         aconnector->audio_inst = -1;
7345         aconnector->pack_sdp_v1_3 = false;
7346         aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE;
7347         memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info));
7348         mutex_init(&aconnector->hpd_lock);
7349         mutex_init(&aconnector->handle_mst_msg_ready);
7350
7351         /*
7352          * configure support HPD hot plug connector_>polled default value is 0
7353          * which means HPD hot plug not supported
7354          */
7355         switch (connector_type) {
7356         case DRM_MODE_CONNECTOR_HDMIA:
7357                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7358                 aconnector->base.ycbcr_420_allowed =
7359                         link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
7360                 break;
7361         case DRM_MODE_CONNECTOR_DisplayPort:
7362                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7363                 link->link_enc = link_enc_cfg_get_link_enc(link);
7364                 ASSERT(link->link_enc);
7365                 if (link->link_enc)
7366                         aconnector->base.ycbcr_420_allowed =
7367                         link->link_enc->features.dp_ycbcr420_supported ? true : false;
7368                 break;
7369         case DRM_MODE_CONNECTOR_DVID:
7370                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7371                 break;
7372         default:
7373                 break;
7374         }
7375
7376         drm_object_attach_property(&aconnector->base.base,
7377                                 dm->ddev->mode_config.scaling_mode_property,
7378                                 DRM_MODE_SCALE_NONE);
7379
7380         drm_object_attach_property(&aconnector->base.base,
7381                                 adev->mode_info.underscan_property,
7382                                 UNDERSCAN_OFF);
7383         drm_object_attach_property(&aconnector->base.base,
7384                                 adev->mode_info.underscan_hborder_property,
7385                                 0);
7386         drm_object_attach_property(&aconnector->base.base,
7387                                 adev->mode_info.underscan_vborder_property,
7388                                 0);
7389
7390         if (!aconnector->mst_root)
7391                 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
7392
7393         aconnector->base.state->max_bpc = 16;
7394         aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
7395
7396         if (connector_type == DRM_MODE_CONNECTOR_eDP &&
7397             (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) {
7398                 drm_object_attach_property(&aconnector->base.base,
7399                                 adev->mode_info.abm_level_property, 0);
7400         }
7401
7402         if (connector_type == DRM_MODE_CONNECTOR_HDMIA) {
7403                 if (!drm_mode_create_hdmi_colorspace_property(&aconnector->base, supported_colorspaces))
7404                         drm_connector_attach_colorspace_property(&aconnector->base);
7405         } else if ((connector_type == DRM_MODE_CONNECTOR_DisplayPort && !aconnector->mst_root) ||
7406                    connector_type == DRM_MODE_CONNECTOR_eDP) {
7407                 if (!drm_mode_create_dp_colorspace_property(&aconnector->base, supported_colorspaces))
7408                         drm_connector_attach_colorspace_property(&aconnector->base);
7409         }
7410
7411         if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
7412             connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
7413             connector_type == DRM_MODE_CONNECTOR_eDP) {
7414                 drm_connector_attach_hdr_output_metadata_property(&aconnector->base);
7415
7416                 if (!aconnector->mst_root)
7417                         drm_connector_attach_vrr_capable_property(&aconnector->base);
7418
7419                 if (adev->dm.hdcp_workqueue)
7420                         drm_connector_attach_content_protection_property(&aconnector->base, true);
7421         }
7422 }
7423
7424 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
7425                               struct i2c_msg *msgs, int num)
7426 {
7427         struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
7428         struct ddc_service *ddc_service = i2c->ddc_service;
7429         struct i2c_command cmd;
7430         int i;
7431         int result = -EIO;
7432
7433         if (!ddc_service->ddc_pin || !ddc_service->ddc_pin->hw_info.hw_supported)
7434                 return result;
7435
7436         cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
7437
7438         if (!cmd.payloads)
7439                 return result;
7440
7441         cmd.number_of_payloads = num;
7442         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
7443         cmd.speed = 100;
7444
7445         for (i = 0; i < num; i++) {
7446                 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
7447                 cmd.payloads[i].address = msgs[i].addr;
7448                 cmd.payloads[i].length = msgs[i].len;
7449                 cmd.payloads[i].data = msgs[i].buf;
7450         }
7451
7452         if (dc_submit_i2c(
7453                         ddc_service->ctx->dc,
7454                         ddc_service->link->link_index,
7455                         &cmd))
7456                 result = num;
7457
7458         kfree(cmd.payloads);
7459         return result;
7460 }
7461
7462 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
7463 {
7464         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
7465 }
7466
7467 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
7468         .master_xfer = amdgpu_dm_i2c_xfer,
7469         .functionality = amdgpu_dm_i2c_func,
7470 };
7471
7472 static struct amdgpu_i2c_adapter *
7473 create_i2c(struct ddc_service *ddc_service,
7474            int link_index,
7475            int *res)
7476 {
7477         struct amdgpu_device *adev = ddc_service->ctx->driver_context;
7478         struct amdgpu_i2c_adapter *i2c;
7479
7480         i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
7481         if (!i2c)
7482                 return NULL;
7483         i2c->base.owner = THIS_MODULE;
7484         i2c->base.class = I2C_CLASS_DDC;
7485         i2c->base.dev.parent = &adev->pdev->dev;
7486         i2c->base.algo = &amdgpu_dm_i2c_algo;
7487         snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
7488         i2c_set_adapdata(&i2c->base, i2c);
7489         i2c->ddc_service = ddc_service;
7490
7491         return i2c;
7492 }
7493
7494
7495 /*
7496  * Note: this function assumes that dc_link_detect() was called for the
7497  * dc_link which will be represented by this aconnector.
7498  */
7499 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
7500                                     struct amdgpu_dm_connector *aconnector,
7501                                     u32 link_index,
7502                                     struct amdgpu_encoder *aencoder)
7503 {
7504         int res = 0;
7505         int connector_type;
7506         struct dc *dc = dm->dc;
7507         struct dc_link *link = dc_get_link_at_index(dc, link_index);
7508         struct amdgpu_i2c_adapter *i2c;
7509
7510         link->priv = aconnector;
7511
7512
7513         i2c = create_i2c(link->ddc, link->link_index, &res);
7514         if (!i2c) {
7515                 DRM_ERROR("Failed to create i2c adapter data\n");
7516                 return -ENOMEM;
7517         }
7518
7519         aconnector->i2c = i2c;
7520         res = i2c_add_adapter(&i2c->base);
7521
7522         if (res) {
7523                 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
7524                 goto out_free;
7525         }
7526
7527         connector_type = to_drm_connector_type(link->connector_signal);
7528
7529         res = drm_connector_init_with_ddc(
7530                         dm->ddev,
7531                         &aconnector->base,
7532                         &amdgpu_dm_connector_funcs,
7533                         connector_type,
7534                         &i2c->base);
7535
7536         if (res) {
7537                 DRM_ERROR("connector_init failed\n");
7538                 aconnector->connector_id = -1;
7539                 goto out_free;
7540         }
7541
7542         drm_connector_helper_add(
7543                         &aconnector->base,
7544                         &amdgpu_dm_connector_helper_funcs);
7545
7546         amdgpu_dm_connector_init_helper(
7547                 dm,
7548                 aconnector,
7549                 connector_type,
7550                 link,
7551                 link_index);
7552
7553         drm_connector_attach_encoder(
7554                 &aconnector->base, &aencoder->base);
7555
7556         if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
7557                 || connector_type == DRM_MODE_CONNECTOR_eDP)
7558                 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);
7559
7560 out_free:
7561         if (res) {
7562                 kfree(i2c);
7563                 aconnector->i2c = NULL;
7564         }
7565         return res;
7566 }
7567
7568 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
7569 {
7570         switch (adev->mode_info.num_crtc) {
7571         case 1:
7572                 return 0x1;
7573         case 2:
7574                 return 0x3;
7575         case 3:
7576                 return 0x7;
7577         case 4:
7578                 return 0xf;
7579         case 5:
7580                 return 0x1f;
7581         case 6:
7582         default:
7583                 return 0x3f;
7584         }
7585 }
7586
7587 static int amdgpu_dm_encoder_init(struct drm_device *dev,
7588                                   struct amdgpu_encoder *aencoder,
7589                                   uint32_t link_index)
7590 {
7591         struct amdgpu_device *adev = drm_to_adev(dev);
7592
7593         int res = drm_encoder_init(dev,
7594                                    &aencoder->base,
7595                                    &amdgpu_dm_encoder_funcs,
7596                                    DRM_MODE_ENCODER_TMDS,
7597                                    NULL);
7598
7599         aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
7600
7601         if (!res)
7602                 aencoder->encoder_id = link_index;
7603         else
7604                 aencoder->encoder_id = -1;
7605
7606         drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
7607
7608         return res;
7609 }
7610
7611 static void manage_dm_interrupts(struct amdgpu_device *adev,
7612                                  struct amdgpu_crtc *acrtc,
7613                                  bool enable)
7614 {
7615         /*
7616          * We have no guarantee that the frontend index maps to the same
7617          * backend index - some even map to more than one.
7618          *
7619          * TODO: Use a different interrupt or check DC itself for the mapping.
7620          */
7621         int irq_type =
7622                 amdgpu_display_crtc_idx_to_irq_type(
7623                         adev,
7624                         acrtc->crtc_id);
7625
7626         if (enable) {
7627                 drm_crtc_vblank_on(&acrtc->base);
7628                 amdgpu_irq_get(
7629                         adev,
7630                         &adev->pageflip_irq,
7631                         irq_type);
7632 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7633                 amdgpu_irq_get(
7634                         adev,
7635                         &adev->vline0_irq,
7636                         irq_type);
7637 #endif
7638         } else {
7639 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7640                 amdgpu_irq_put(
7641                         adev,
7642                         &adev->vline0_irq,
7643                         irq_type);
7644 #endif
7645                 amdgpu_irq_put(
7646                         adev,
7647                         &adev->pageflip_irq,
7648                         irq_type);
7649                 drm_crtc_vblank_off(&acrtc->base);
7650         }
7651 }
7652
7653 static void dm_update_pflip_irq_state(struct amdgpu_device *adev,
7654                                       struct amdgpu_crtc *acrtc)
7655 {
7656         int irq_type =
7657                 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
7658
7659         /**
7660          * This reads the current state for the IRQ and force reapplies
7661          * the setting to hardware.
7662          */
7663         amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type);
7664 }
7665
7666 static bool
7667 is_scaling_state_different(const struct dm_connector_state *dm_state,
7668                            const struct dm_connector_state *old_dm_state)
7669 {
7670         if (dm_state->scaling != old_dm_state->scaling)
7671                 return true;
7672         if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
7673                 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
7674                         return true;
7675         } else  if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
7676                 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
7677                         return true;
7678         } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
7679                    dm_state->underscan_vborder != old_dm_state->underscan_vborder)
7680                 return true;
7681         return false;
7682 }
7683
7684 static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state,
7685                                             struct drm_crtc_state *old_crtc_state,
7686                                             struct drm_connector_state *new_conn_state,
7687                                             struct drm_connector_state *old_conn_state,
7688                                             const struct drm_connector *connector,
7689                                             struct hdcp_workqueue *hdcp_w)
7690 {
7691         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7692         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
7693
7694         pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
7695                 connector->index, connector->status, connector->dpms);
7696         pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
7697                 old_conn_state->content_protection, new_conn_state->content_protection);
7698
7699         if (old_crtc_state)
7700                 pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7701                 old_crtc_state->enable,
7702                 old_crtc_state->active,
7703                 old_crtc_state->mode_changed,
7704                 old_crtc_state->active_changed,
7705                 old_crtc_state->connectors_changed);
7706
7707         if (new_crtc_state)
7708                 pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7709                 new_crtc_state->enable,
7710                 new_crtc_state->active,
7711                 new_crtc_state->mode_changed,
7712                 new_crtc_state->active_changed,
7713                 new_crtc_state->connectors_changed);
7714
7715         /* hdcp content type change */
7716         if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type &&
7717             new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
7718                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7719                 pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__);
7720                 return true;
7721         }
7722
7723         /* CP is being re enabled, ignore this */
7724         if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
7725             new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7726                 if (new_crtc_state && new_crtc_state->mode_changed) {
7727                         new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7728                         pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__);
7729                         return true;
7730                 }
7731                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
7732                 pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__);
7733                 return false;
7734         }
7735
7736         /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED
7737          *
7738          * Handles:     UNDESIRED -> ENABLED
7739          */
7740         if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
7741             new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
7742                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7743
7744         /* Stream removed and re-enabled
7745          *
7746          * Can sometimes overlap with the HPD case,
7747          * thus set update_hdcp to false to avoid
7748          * setting HDCP multiple times.
7749          *
7750          * Handles:     DESIRED -> DESIRED (Special case)
7751          */
7752         if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) &&
7753                 new_conn_state->crtc && new_conn_state->crtc->enabled &&
7754                 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7755                 dm_con_state->update_hdcp = false;
7756                 pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n",
7757                         __func__);
7758                 return true;
7759         }
7760
7761         /* Hot-plug, headless s3, dpms
7762          *
7763          * Only start HDCP if the display is connected/enabled.
7764          * update_hdcp flag will be set to false until the next
7765          * HPD comes in.
7766          *
7767          * Handles:     DESIRED -> DESIRED (Special case)
7768          */
7769         if (dm_con_state->update_hdcp &&
7770         new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
7771         connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
7772                 dm_con_state->update_hdcp = false;
7773                 pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n",
7774                         __func__);
7775                 return true;
7776         }
7777
7778         if (old_conn_state->content_protection == new_conn_state->content_protection) {
7779                 if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7780                         if (new_crtc_state && new_crtc_state->mode_changed) {
7781                                 pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n",
7782                                         __func__);
7783                                 return true;
7784                         }
7785                         pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n",
7786                                 __func__);
7787                         return false;
7788                 }
7789
7790                 pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__);
7791                 return false;
7792         }
7793
7794         if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) {
7795                 pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n",
7796                         __func__);
7797                 return true;
7798         }
7799
7800         pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__);
7801         return false;
7802 }
7803
7804 static void remove_stream(struct amdgpu_device *adev,
7805                           struct amdgpu_crtc *acrtc,
7806                           struct dc_stream_state *stream)
7807 {
7808         /* this is the update mode case */
7809
7810         acrtc->otg_inst = -1;
7811         acrtc->enabled = false;
7812 }
7813
7814 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
7815 {
7816
7817         assert_spin_locked(&acrtc->base.dev->event_lock);
7818         WARN_ON(acrtc->event);
7819
7820         acrtc->event = acrtc->base.state->event;
7821
7822         /* Set the flip status */
7823         acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
7824
7825         /* Mark this event as consumed */
7826         acrtc->base.state->event = NULL;
7827
7828         DC_LOG_PFLIP("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
7829                      acrtc->crtc_id);
7830 }
7831
7832 static void update_freesync_state_on_stream(
7833         struct amdgpu_display_manager *dm,
7834         struct dm_crtc_state *new_crtc_state,
7835         struct dc_stream_state *new_stream,
7836         struct dc_plane_state *surface,
7837         u32 flip_timestamp_in_us)
7838 {
7839         struct mod_vrr_params vrr_params;
7840         struct dc_info_packet vrr_infopacket = {0};
7841         struct amdgpu_device *adev = dm->adev;
7842         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7843         unsigned long flags;
7844         bool pack_sdp_v1_3 = false;
7845         struct amdgpu_dm_connector *aconn;
7846         enum vrr_packet_type packet_type = PACKET_TYPE_VRR;
7847
7848         if (!new_stream)
7849                 return;
7850
7851         /*
7852          * TODO: Determine why min/max totals and vrefresh can be 0 here.
7853          * For now it's sufficient to just guard against these conditions.
7854          */
7855
7856         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7857                 return;
7858
7859         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7860         vrr_params = acrtc->dm_irq_params.vrr_params;
7861
7862         if (surface) {
7863                 mod_freesync_handle_preflip(
7864                         dm->freesync_module,
7865                         surface,
7866                         new_stream,
7867                         flip_timestamp_in_us,
7868                         &vrr_params);
7869
7870                 if (adev->family < AMDGPU_FAMILY_AI &&
7871                     amdgpu_dm_crtc_vrr_active(new_crtc_state)) {
7872                         mod_freesync_handle_v_update(dm->freesync_module,
7873                                                      new_stream, &vrr_params);
7874
7875                         /* Need to call this before the frame ends. */
7876                         dc_stream_adjust_vmin_vmax(dm->dc,
7877                                                    new_crtc_state->stream,
7878                                                    &vrr_params.adjust);
7879                 }
7880         }
7881
7882         aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context;
7883
7884         if (aconn && (aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST || aconn->vsdb_info.replay_mode)) {
7885                 pack_sdp_v1_3 = aconn->pack_sdp_v1_3;
7886
7887                 if (aconn->vsdb_info.amd_vsdb_version == 1)
7888                         packet_type = PACKET_TYPE_FS_V1;
7889                 else if (aconn->vsdb_info.amd_vsdb_version == 2)
7890                         packet_type = PACKET_TYPE_FS_V2;
7891                 else if (aconn->vsdb_info.amd_vsdb_version == 3)
7892                         packet_type = PACKET_TYPE_FS_V3;
7893
7894                 mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL,
7895                                         &new_stream->adaptive_sync_infopacket);
7896         }
7897
7898         mod_freesync_build_vrr_infopacket(
7899                 dm->freesync_module,
7900                 new_stream,
7901                 &vrr_params,
7902                 packet_type,
7903                 TRANSFER_FUNC_UNKNOWN,
7904                 &vrr_infopacket,
7905                 pack_sdp_v1_3);
7906
7907         new_crtc_state->freesync_vrr_info_changed |=
7908                 (memcmp(&new_crtc_state->vrr_infopacket,
7909                         &vrr_infopacket,
7910                         sizeof(vrr_infopacket)) != 0);
7911
7912         acrtc->dm_irq_params.vrr_params = vrr_params;
7913         new_crtc_state->vrr_infopacket = vrr_infopacket;
7914
7915         new_stream->vrr_infopacket = vrr_infopacket;
7916         new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params);
7917
7918         if (new_crtc_state->freesync_vrr_info_changed)
7919                 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
7920                               new_crtc_state->base.crtc->base.id,
7921                               (int)new_crtc_state->base.vrr_enabled,
7922                               (int)vrr_params.state);
7923
7924         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7925 }
7926
7927 static void update_stream_irq_parameters(
7928         struct amdgpu_display_manager *dm,
7929         struct dm_crtc_state *new_crtc_state)
7930 {
7931         struct dc_stream_state *new_stream = new_crtc_state->stream;
7932         struct mod_vrr_params vrr_params;
7933         struct mod_freesync_config config = new_crtc_state->freesync_config;
7934         struct amdgpu_device *adev = dm->adev;
7935         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7936         unsigned long flags;
7937
7938         if (!new_stream)
7939                 return;
7940
7941         /*
7942          * TODO: Determine why min/max totals and vrefresh can be 0 here.
7943          * For now it's sufficient to just guard against these conditions.
7944          */
7945         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7946                 return;
7947
7948         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7949         vrr_params = acrtc->dm_irq_params.vrr_params;
7950
7951         if (new_crtc_state->vrr_supported &&
7952             config.min_refresh_in_uhz &&
7953             config.max_refresh_in_uhz) {
7954                 /*
7955                  * if freesync compatible mode was set, config.state will be set
7956                  * in atomic check
7957                  */
7958                 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz &&
7959                     (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) ||
7960                      new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) {
7961                         vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz;
7962                         vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz;
7963                         vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz;
7964                         vrr_params.state = VRR_STATE_ACTIVE_FIXED;
7965                 } else {
7966                         config.state = new_crtc_state->base.vrr_enabled ?
7967                                                      VRR_STATE_ACTIVE_VARIABLE :
7968                                                      VRR_STATE_INACTIVE;
7969                 }
7970         } else {
7971                 config.state = VRR_STATE_UNSUPPORTED;
7972         }
7973
7974         mod_freesync_build_vrr_params(dm->freesync_module,
7975                                       new_stream,
7976                                       &config, &vrr_params);
7977
7978         new_crtc_state->freesync_config = config;
7979         /* Copy state for access from DM IRQ handler */
7980         acrtc->dm_irq_params.freesync_config = config;
7981         acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes;
7982         acrtc->dm_irq_params.vrr_params = vrr_params;
7983         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7984 }
7985
7986 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
7987                                             struct dm_crtc_state *new_state)
7988 {
7989         bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state);
7990         bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state);
7991
7992         if (!old_vrr_active && new_vrr_active) {
7993                 /* Transition VRR inactive -> active:
7994                  * While VRR is active, we must not disable vblank irq, as a
7995                  * reenable after disable would compute bogus vblank/pflip
7996                  * timestamps if it likely happened inside display front-porch.
7997                  *
7998                  * We also need vupdate irq for the actual core vblank handling
7999                  * at end of vblank.
8000                  */
8001                 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0);
8002                 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0);
8003                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
8004                                  __func__, new_state->base.crtc->base.id);
8005         } else if (old_vrr_active && !new_vrr_active) {
8006                 /* Transition VRR active -> inactive:
8007                  * Allow vblank irq disable again for fixed refresh rate.
8008                  */
8009                 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0);
8010                 drm_crtc_vblank_put(new_state->base.crtc);
8011                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
8012                                  __func__, new_state->base.crtc->base.id);
8013         }
8014 }
8015
8016 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
8017 {
8018         struct drm_plane *plane;
8019         struct drm_plane_state *old_plane_state;
8020         int i;
8021
8022         /*
8023          * TODO: Make this per-stream so we don't issue redundant updates for
8024          * commits with multiple streams.
8025          */
8026         for_each_old_plane_in_state(state, plane, old_plane_state, i)
8027                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
8028                         amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state);
8029 }
8030
8031 static inline uint32_t get_mem_type(struct drm_framebuffer *fb)
8032 {
8033         struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]);
8034
8035         return abo->tbo.resource ? abo->tbo.resource->mem_type : 0;
8036 }
8037
8038 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
8039                                     struct drm_device *dev,
8040                                     struct amdgpu_display_manager *dm,
8041                                     struct drm_crtc *pcrtc,
8042                                     bool wait_for_vblank)
8043 {
8044         u32 i;
8045         u64 timestamp_ns = ktime_get_ns();
8046         struct drm_plane *plane;
8047         struct drm_plane_state *old_plane_state, *new_plane_state;
8048         struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
8049         struct drm_crtc_state *new_pcrtc_state =
8050                         drm_atomic_get_new_crtc_state(state, pcrtc);
8051         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
8052         struct dm_crtc_state *dm_old_crtc_state =
8053                         to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
8054         int planes_count = 0, vpos, hpos;
8055         unsigned long flags;
8056         u32 target_vblank, last_flip_vblank;
8057         bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state);
8058         bool cursor_update = false;
8059         bool pflip_present = false;
8060         bool dirty_rects_changed = false;
8061         struct {
8062                 struct dc_surface_update surface_updates[MAX_SURFACES];
8063                 struct dc_plane_info plane_infos[MAX_SURFACES];
8064                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
8065                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
8066                 struct dc_stream_update stream_update;
8067         } *bundle;
8068
8069         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
8070
8071         if (!bundle) {
8072                 dm_error("Failed to allocate update bundle\n");
8073                 goto cleanup;
8074         }
8075
8076         /*
8077          * Disable the cursor first if we're disabling all the planes.
8078          * It'll remain on the screen after the planes are re-enabled
8079          * if we don't.
8080          */
8081         if (acrtc_state->active_planes == 0)
8082                 amdgpu_dm_commit_cursors(state);
8083
8084         /* update planes when needed */
8085         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
8086                 struct drm_crtc *crtc = new_plane_state->crtc;
8087                 struct drm_crtc_state *new_crtc_state;
8088                 struct drm_framebuffer *fb = new_plane_state->fb;
8089                 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb;
8090                 bool plane_needs_flip;
8091                 struct dc_plane_state *dc_plane;
8092                 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
8093
8094                 /* Cursor plane is handled after stream updates */
8095                 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
8096                         if ((fb && crtc == pcrtc) ||
8097                             (old_plane_state->fb && old_plane_state->crtc == pcrtc))
8098                                 cursor_update = true;
8099
8100                         continue;
8101                 }
8102
8103                 if (!fb || !crtc || pcrtc != crtc)
8104                         continue;
8105
8106                 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
8107                 if (!new_crtc_state->active)
8108                         continue;
8109
8110                 dc_plane = dm_new_plane_state->dc_state;
8111                 if (!dc_plane)
8112                         continue;
8113
8114                 bundle->surface_updates[planes_count].surface = dc_plane;
8115                 if (new_pcrtc_state->color_mgmt_changed) {
8116                         bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
8117                         bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
8118                         bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;
8119                 }
8120
8121                 amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state,
8122                                      &bundle->scaling_infos[planes_count]);
8123
8124                 bundle->surface_updates[planes_count].scaling_info =
8125                         &bundle->scaling_infos[planes_count];
8126
8127                 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
8128
8129                 pflip_present = pflip_present || plane_needs_flip;
8130
8131                 if (!plane_needs_flip) {
8132                         planes_count += 1;
8133                         continue;
8134                 }
8135
8136                 fill_dc_plane_info_and_addr(
8137                         dm->adev, new_plane_state,
8138                         afb->tiling_flags,
8139                         &bundle->plane_infos[planes_count],
8140                         &bundle->flip_addrs[planes_count].address,
8141                         afb->tmz_surface, false);
8142
8143                 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n",
8144                                  new_plane_state->plane->index,
8145                                  bundle->plane_infos[planes_count].dcc.enable);
8146
8147                 bundle->surface_updates[planes_count].plane_info =
8148                         &bundle->plane_infos[planes_count];
8149
8150                 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled ||
8151                     acrtc_state->stream->link->replay_settings.replay_feature_enabled) {
8152                         fill_dc_dirty_rects(plane, old_plane_state,
8153                                             new_plane_state, new_crtc_state,
8154                                             &bundle->flip_addrs[planes_count],
8155                                             &dirty_rects_changed);
8156
8157                         /*
8158                          * If the dirty regions changed, PSR-SU need to be disabled temporarily
8159                          * and enabled it again after dirty regions are stable to avoid video glitch.
8160                          * PSR-SU will be enabled in vblank_control_worker() if user pause the video
8161                          * during the PSR-SU was disabled.
8162                          */
8163                         if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8164                             acrtc_attach->dm_irq_params.allow_psr_entry &&
8165 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8166                             !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8167 #endif
8168                             dirty_rects_changed) {
8169                                 mutex_lock(&dm->dc_lock);
8170                                 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns =
8171                                 timestamp_ns;
8172                                 if (acrtc_state->stream->link->psr_settings.psr_allow_active)
8173                                         amdgpu_dm_psr_disable(acrtc_state->stream);
8174                                 mutex_unlock(&dm->dc_lock);
8175                         }
8176                 }
8177
8178                 /*
8179                  * Only allow immediate flips for fast updates that don't
8180                  * change memory domain, FB pitch, DCC state, rotation or
8181                  * mirroring.
8182                  *
8183                  * dm_crtc_helper_atomic_check() only accepts async flips with
8184                  * fast updates.
8185                  */
8186                 if (crtc->state->async_flip &&
8187                     (acrtc_state->update_type != UPDATE_TYPE_FAST ||
8188                      get_mem_type(old_plane_state->fb) != get_mem_type(fb)))
8189                         drm_warn_once(state->dev,
8190                                       "[PLANE:%d:%s] async flip with non-fast update\n",
8191                                       plane->base.id, plane->name);
8192
8193                 bundle->flip_addrs[planes_count].flip_immediate =
8194                         crtc->state->async_flip &&
8195                         acrtc_state->update_type == UPDATE_TYPE_FAST &&
8196                         get_mem_type(old_plane_state->fb) == get_mem_type(fb);
8197
8198                 timestamp_ns = ktime_get_ns();
8199                 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
8200                 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
8201                 bundle->surface_updates[planes_count].surface = dc_plane;
8202
8203                 if (!bundle->surface_updates[planes_count].surface) {
8204                         DRM_ERROR("No surface for CRTC: id=%d\n",
8205                                         acrtc_attach->crtc_id);
8206                         continue;
8207                 }
8208
8209                 if (plane == pcrtc->primary)
8210                         update_freesync_state_on_stream(
8211                                 dm,
8212                                 acrtc_state,
8213                                 acrtc_state->stream,
8214                                 dc_plane,
8215                                 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
8216
8217                 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n",
8218                                  __func__,
8219                                  bundle->flip_addrs[planes_count].address.grph.addr.high_part,
8220                                  bundle->flip_addrs[planes_count].address.grph.addr.low_part);
8221
8222                 planes_count += 1;
8223
8224         }
8225
8226         if (pflip_present) {
8227                 if (!vrr_active) {
8228                         /* Use old throttling in non-vrr fixed refresh rate mode
8229                          * to keep flip scheduling based on target vblank counts
8230                          * working in a backwards compatible way, e.g., for
8231                          * clients using the GLX_OML_sync_control extension or
8232                          * DRI3/Present extension with defined target_msc.
8233                          */
8234                         last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);
8235                 } else {
8236                         /* For variable refresh rate mode only:
8237                          * Get vblank of last completed flip to avoid > 1 vrr
8238                          * flips per video frame by use of throttling, but allow
8239                          * flip programming anywhere in the possibly large
8240                          * variable vrr vblank interval for fine-grained flip
8241                          * timing control and more opportunity to avoid stutter
8242                          * on late submission of flips.
8243                          */
8244                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8245                         last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank;
8246                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8247                 }
8248
8249                 target_vblank = last_flip_vblank + wait_for_vblank;
8250
8251                 /*
8252                  * Wait until we're out of the vertical blank period before the one
8253                  * targeted by the flip
8254                  */
8255                 while ((acrtc_attach->enabled &&
8256                         (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
8257                                                             0, &vpos, &hpos, NULL,
8258                                                             NULL, &pcrtc->hwmode)
8259                          & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
8260                         (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
8261                         (int)(target_vblank -
8262                           amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) {
8263                         usleep_range(1000, 1100);
8264                 }
8265
8266                 /**
8267                  * Prepare the flip event for the pageflip interrupt to handle.
8268                  *
8269                  * This only works in the case where we've already turned on the
8270                  * appropriate hardware blocks (eg. HUBP) so in the transition case
8271                  * from 0 -> n planes we have to skip a hardware generated event
8272                  * and rely on sending it from software.
8273                  */
8274                 if (acrtc_attach->base.state->event &&
8275                     acrtc_state->active_planes > 0) {
8276                         drm_crtc_vblank_get(pcrtc);
8277
8278                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8279
8280                         WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
8281                         prepare_flip_isr(acrtc_attach);
8282
8283                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8284                 }
8285
8286                 if (acrtc_state->stream) {
8287                         if (acrtc_state->freesync_vrr_info_changed)
8288                                 bundle->stream_update.vrr_infopacket =
8289                                         &acrtc_state->stream->vrr_infopacket;
8290                 }
8291         } else if (cursor_update && acrtc_state->active_planes > 0 &&
8292                    acrtc_attach->base.state->event) {
8293                 drm_crtc_vblank_get(pcrtc);
8294
8295                 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8296
8297                 acrtc_attach->event = acrtc_attach->base.state->event;
8298                 acrtc_attach->base.state->event = NULL;
8299
8300                 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8301         }
8302
8303         /* Update the planes if changed or disable if we don't have any. */
8304         if ((planes_count || acrtc_state->active_planes == 0) &&
8305                 acrtc_state->stream) {
8306                 /*
8307                  * If PSR or idle optimizations are enabled then flush out
8308                  * any pending work before hardware programming.
8309                  */
8310                 if (dm->vblank_control_workqueue)
8311                         flush_workqueue(dm->vblank_control_workqueue);
8312
8313                 bundle->stream_update.stream = acrtc_state->stream;
8314                 if (new_pcrtc_state->mode_changed) {
8315                         bundle->stream_update.src = acrtc_state->stream->src;
8316                         bundle->stream_update.dst = acrtc_state->stream->dst;
8317                 }
8318
8319                 if (new_pcrtc_state->color_mgmt_changed) {
8320                         /*
8321                          * TODO: This isn't fully correct since we've actually
8322                          * already modified the stream in place.
8323                          */
8324                         bundle->stream_update.gamut_remap =
8325                                 &acrtc_state->stream->gamut_remap_matrix;
8326                         bundle->stream_update.output_csc_transform =
8327                                 &acrtc_state->stream->csc_color_matrix;
8328                         bundle->stream_update.out_transfer_func =
8329                                 acrtc_state->stream->out_transfer_func;
8330                 }
8331
8332                 acrtc_state->stream->abm_level = acrtc_state->abm_level;
8333                 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
8334                         bundle->stream_update.abm_level = &acrtc_state->abm_level;
8335
8336                 mutex_lock(&dm->dc_lock);
8337                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8338                                 acrtc_state->stream->link->psr_settings.psr_allow_active)
8339                         amdgpu_dm_psr_disable(acrtc_state->stream);
8340                 mutex_unlock(&dm->dc_lock);
8341
8342                 /*
8343                  * If FreeSync state on the stream has changed then we need to
8344                  * re-adjust the min/max bounds now that DC doesn't handle this
8345                  * as part of commit.
8346                  */
8347                 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) {
8348                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8349                         dc_stream_adjust_vmin_vmax(
8350                                 dm->dc, acrtc_state->stream,
8351                                 &acrtc_attach->dm_irq_params.vrr_params.adjust);
8352                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8353                 }
8354                 mutex_lock(&dm->dc_lock);
8355                 update_planes_and_stream_adapter(dm->dc,
8356                                          acrtc_state->update_type,
8357                                          planes_count,
8358                                          acrtc_state->stream,
8359                                          &bundle->stream_update,
8360                                          bundle->surface_updates);
8361
8362                 /**
8363                  * Enable or disable the interrupts on the backend.
8364                  *
8365                  * Most pipes are put into power gating when unused.
8366                  *
8367                  * When power gating is enabled on a pipe we lose the
8368                  * interrupt enablement state when power gating is disabled.
8369                  *
8370                  * So we need to update the IRQ control state in hardware
8371                  * whenever the pipe turns on (since it could be previously
8372                  * power gated) or off (since some pipes can't be power gated
8373                  * on some ASICs).
8374                  */
8375                 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes)
8376                         dm_update_pflip_irq_state(drm_to_adev(dev),
8377                                                   acrtc_attach);
8378
8379                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8380                                 acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
8381                                 !acrtc_state->stream->link->psr_settings.psr_feature_enabled)
8382                         amdgpu_dm_link_setup_psr(acrtc_state->stream);
8383
8384                 /* Decrement skip count when PSR is enabled and we're doing fast updates. */
8385                 if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
8386                     acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8387                         struct amdgpu_dm_connector *aconn =
8388                                 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
8389
8390                         if (aconn->psr_skip_count > 0)
8391                                 aconn->psr_skip_count--;
8392
8393                         /* Allow PSR when skip count is 0. */
8394                         acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count;
8395
8396                         /*
8397                          * If sink supports PSR SU, there is no need to rely on
8398                          * a vblank event disable request to enable PSR. PSR SU
8399                          * can be enabled immediately once OS demonstrates an
8400                          * adequate number of fast atomic commits to notify KMD
8401                          * of update events. See `vblank_control_worker()`.
8402                          */
8403                         if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8404                             acrtc_attach->dm_irq_params.allow_psr_entry &&
8405 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8406                             !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8407 #endif
8408                             !acrtc_state->stream->link->psr_settings.psr_allow_active &&
8409                             (timestamp_ns -
8410                             acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) >
8411                             500000000)
8412                                 amdgpu_dm_psr_enable(acrtc_state->stream);
8413                 } else {
8414                         acrtc_attach->dm_irq_params.allow_psr_entry = false;
8415                 }
8416
8417                 mutex_unlock(&dm->dc_lock);
8418         }
8419
8420         /*
8421          * Update cursor state *after* programming all the planes.
8422          * This avoids redundant programming in the case where we're going
8423          * to be disabling a single plane - those pipes are being disabled.
8424          */
8425         if (acrtc_state->active_planes)
8426                 amdgpu_dm_commit_cursors(state);
8427
8428 cleanup:
8429         kfree(bundle);
8430 }
8431
8432 static void amdgpu_dm_commit_audio(struct drm_device *dev,
8433                                    struct drm_atomic_state *state)
8434 {
8435         struct amdgpu_device *adev = drm_to_adev(dev);
8436         struct amdgpu_dm_connector *aconnector;
8437         struct drm_connector *connector;
8438         struct drm_connector_state *old_con_state, *new_con_state;
8439         struct drm_crtc_state *new_crtc_state;
8440         struct dm_crtc_state *new_dm_crtc_state;
8441         const struct dc_stream_status *status;
8442         int i, inst;
8443
8444         /* Notify device removals. */
8445         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8446                 if (old_con_state->crtc != new_con_state->crtc) {
8447                         /* CRTC changes require notification. */
8448                         goto notify;
8449                 }
8450
8451                 if (!new_con_state->crtc)
8452                         continue;
8453
8454                 new_crtc_state = drm_atomic_get_new_crtc_state(
8455                         state, new_con_state->crtc);
8456
8457                 if (!new_crtc_state)
8458                         continue;
8459
8460                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8461                         continue;
8462
8463 notify:
8464                 aconnector = to_amdgpu_dm_connector(connector);
8465
8466                 mutex_lock(&adev->dm.audio_lock);
8467                 inst = aconnector->audio_inst;
8468                 aconnector->audio_inst = -1;
8469                 mutex_unlock(&adev->dm.audio_lock);
8470
8471                 amdgpu_dm_audio_eld_notify(adev, inst);
8472         }
8473
8474         /* Notify audio device additions. */
8475         for_each_new_connector_in_state(state, connector, new_con_state, i) {
8476                 if (!new_con_state->crtc)
8477                         continue;
8478
8479                 new_crtc_state = drm_atomic_get_new_crtc_state(
8480                         state, new_con_state->crtc);
8481
8482                 if (!new_crtc_state)
8483                         continue;
8484
8485                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8486                         continue;
8487
8488                 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
8489                 if (!new_dm_crtc_state->stream)
8490                         continue;
8491
8492                 status = dc_stream_get_status(new_dm_crtc_state->stream);
8493                 if (!status)
8494                         continue;
8495
8496                 aconnector = to_amdgpu_dm_connector(connector);
8497
8498                 mutex_lock(&adev->dm.audio_lock);
8499                 inst = status->audio_inst;
8500                 aconnector->audio_inst = inst;
8501                 mutex_unlock(&adev->dm.audio_lock);
8502
8503                 amdgpu_dm_audio_eld_notify(adev, inst);
8504         }
8505 }
8506
8507 /*
8508  * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
8509  * @crtc_state: the DRM CRTC state
8510  * @stream_state: the DC stream state.
8511  *
8512  * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
8513  * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
8514  */
8515 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
8516                                                 struct dc_stream_state *stream_state)
8517 {
8518         stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
8519 }
8520
8521 static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,
8522                                         struct dc_state *dc_state)
8523 {
8524         struct drm_device *dev = state->dev;
8525         struct amdgpu_device *adev = drm_to_adev(dev);
8526         struct amdgpu_display_manager *dm = &adev->dm;
8527         struct drm_crtc *crtc;
8528         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8529         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8530         bool mode_set_reset_required = false;
8531         u32 i;
8532
8533         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
8534                                       new_crtc_state, i) {
8535                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8536
8537                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8538
8539                 if (old_crtc_state->active &&
8540                     (!new_crtc_state->active ||
8541                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8542                         manage_dm_interrupts(adev, acrtc, false);
8543                         dc_stream_release(dm_old_crtc_state->stream);
8544                 }
8545         }
8546
8547         drm_atomic_helper_calc_timestamping_constants(state);
8548
8549         /* update changed items */
8550         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8551                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8552
8553                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8554                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8555
8556                 drm_dbg_state(state->dev,
8557                         "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n",
8558                         acrtc->crtc_id,
8559                         new_crtc_state->enable,
8560                         new_crtc_state->active,
8561                         new_crtc_state->planes_changed,
8562                         new_crtc_state->mode_changed,
8563                         new_crtc_state->active_changed,
8564                         new_crtc_state->connectors_changed);
8565
8566                 /* Disable cursor if disabling crtc */
8567                 if (old_crtc_state->active && !new_crtc_state->active) {
8568                         struct dc_cursor_position position;
8569
8570                         memset(&position, 0, sizeof(position));
8571                         mutex_lock(&dm->dc_lock);
8572                         dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position);
8573                         mutex_unlock(&dm->dc_lock);
8574                 }
8575
8576                 /* Copy all transient state flags into dc state */
8577                 if (dm_new_crtc_state->stream) {
8578                         amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
8579                                                             dm_new_crtc_state->stream);
8580                 }
8581
8582                 /* handles headless hotplug case, updating new_state and
8583                  * aconnector as needed
8584                  */
8585
8586                 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
8587
8588                         DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
8589
8590                         if (!dm_new_crtc_state->stream) {
8591                                 /*
8592                                  * this could happen because of issues with
8593                                  * userspace notifications delivery.
8594                                  * In this case userspace tries to set mode on
8595                                  * display which is disconnected in fact.
8596                                  * dc_sink is NULL in this case on aconnector.
8597                                  * We expect reset mode will come soon.
8598                                  *
8599                                  * This can also happen when unplug is done
8600                                  * during resume sequence ended
8601                                  *
8602                                  * In this case, we want to pretend we still
8603                                  * have a sink to keep the pipe running so that
8604                                  * hw state is consistent with the sw state
8605                                  */
8606                                 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
8607                                                 __func__, acrtc->base.base.id);
8608                                 continue;
8609                         }
8610
8611                         if (dm_old_crtc_state->stream)
8612                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8613
8614                         pm_runtime_get_noresume(dev->dev);
8615
8616                         acrtc->enabled = true;
8617                         acrtc->hw_mode = new_crtc_state->mode;
8618                         crtc->hwmode = new_crtc_state->mode;
8619                         mode_set_reset_required = true;
8620                 } else if (modereset_required(new_crtc_state)) {
8621                         DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
8622                         /* i.e. reset mode */
8623                         if (dm_old_crtc_state->stream)
8624                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8625
8626                         mode_set_reset_required = true;
8627                 }
8628         } /* for_each_crtc_in_state() */
8629
8630         /* if there mode set or reset, disable eDP PSR */
8631         if (mode_set_reset_required) {
8632                 if (dm->vblank_control_workqueue)
8633                         flush_workqueue(dm->vblank_control_workqueue);
8634
8635                 amdgpu_dm_psr_disable_all(dm);
8636         }
8637
8638         dm_enable_per_frame_crtc_master_sync(dc_state);
8639         mutex_lock(&dm->dc_lock);
8640         WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
8641
8642         /* Allow idle optimization when vblank count is 0 for display off */
8643         if (dm->active_vblank_irq_count == 0)
8644                 dc_allow_idle_optimizations(dm->dc, true);
8645         mutex_unlock(&dm->dc_lock);
8646
8647         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8648                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8649
8650                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8651
8652                 if (dm_new_crtc_state->stream != NULL) {
8653                         const struct dc_stream_status *status =
8654                                         dc_stream_get_status(dm_new_crtc_state->stream);
8655
8656                         if (!status)
8657                                 status = dc_stream_get_status_from_state(dc_state,
8658                                                                          dm_new_crtc_state->stream);
8659                         if (!status)
8660                                 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
8661                         else
8662                                 acrtc->otg_inst = status->primary_otg_inst;
8663                 }
8664         }
8665 }
8666
8667 /**
8668  * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
8669  * @state: The atomic state to commit
8670  *
8671  * This will tell DC to commit the constructed DC state from atomic_check,
8672  * programming the hardware. Any failures here implies a hardware failure, since
8673  * atomic check should have filtered anything non-kosher.
8674  */
8675 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
8676 {
8677         struct drm_device *dev = state->dev;
8678         struct amdgpu_device *adev = drm_to_adev(dev);
8679         struct amdgpu_display_manager *dm = &adev->dm;
8680         struct dm_atomic_state *dm_state;
8681         struct dc_state *dc_state = NULL;
8682         u32 i, j;
8683         struct drm_crtc *crtc;
8684         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8685         unsigned long flags;
8686         bool wait_for_vblank = true;
8687         struct drm_connector *connector;
8688         struct drm_connector_state *old_con_state, *new_con_state;
8689         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8690         int crtc_disable_count = 0;
8691
8692         trace_amdgpu_dm_atomic_commit_tail_begin(state);
8693
8694         drm_atomic_helper_update_legacy_modeset_state(dev, state);
8695         drm_dp_mst_atomic_wait_for_dependencies(state);
8696
8697         dm_state = dm_atomic_get_new_state(state);
8698         if (dm_state && dm_state->context) {
8699                 dc_state = dm_state->context;
8700                 amdgpu_dm_commit_streams(state, dc_state);
8701         }
8702
8703         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8704                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8705                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8706                 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8707
8708                 if (!adev->dm.hdcp_workqueue)
8709                         continue;
8710
8711                 pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i);
8712
8713                 if (!connector)
8714                         continue;
8715
8716                 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
8717                         connector->index, connector->status, connector->dpms);
8718                 pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
8719                         old_con_state->content_protection, new_con_state->content_protection);
8720
8721                 if (aconnector->dc_sink) {
8722                         if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
8723                                 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) {
8724                                 pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n",
8725                                 aconnector->dc_sink->edid_caps.display_name);
8726                         }
8727                 }
8728
8729                 new_crtc_state = NULL;
8730                 old_crtc_state = NULL;
8731
8732                 if (acrtc) {
8733                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8734                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8735                 }
8736
8737                 if (old_crtc_state)
8738                         pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8739                         old_crtc_state->enable,
8740                         old_crtc_state->active,
8741                         old_crtc_state->mode_changed,
8742                         old_crtc_state->active_changed,
8743                         old_crtc_state->connectors_changed);
8744
8745                 if (new_crtc_state)
8746                         pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8747                         new_crtc_state->enable,
8748                         new_crtc_state->active,
8749                         new_crtc_state->mode_changed,
8750                         new_crtc_state->active_changed,
8751                         new_crtc_state->connectors_changed);
8752         }
8753
8754         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8755                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8756                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8757                 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8758
8759                 if (!adev->dm.hdcp_workqueue)
8760                         continue;
8761
8762                 new_crtc_state = NULL;
8763                 old_crtc_state = NULL;
8764
8765                 if (acrtc) {
8766                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8767                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8768                 }
8769
8770                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8771
8772                 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
8773                     connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
8774                         hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
8775                         new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
8776                         dm_new_con_state->update_hdcp = true;
8777                         continue;
8778                 }
8779
8780                 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state,
8781                                                                                         old_con_state, connector, adev->dm.hdcp_workqueue)) {
8782                         /* when display is unplugged from mst hub, connctor will
8783                          * be destroyed within dm_dp_mst_connector_destroy. connector
8784                          * hdcp perperties, like type, undesired, desired, enabled,
8785                          * will be lost. So, save hdcp properties into hdcp_work within
8786                          * amdgpu_dm_atomic_commit_tail. if the same display is
8787                          * plugged back with same display index, its hdcp properties
8788                          * will be retrieved from hdcp_work within dm_dp_mst_get_modes
8789                          */
8790
8791                         bool enable_encryption = false;
8792
8793                         if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED)
8794                                 enable_encryption = true;
8795
8796                         if (aconnector->dc_link && aconnector->dc_sink &&
8797                                 aconnector->dc_link->type == dc_connection_mst_branch) {
8798                                 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
8799                                 struct hdcp_workqueue *hdcp_w =
8800                                         &hdcp_work[aconnector->dc_link->link_index];
8801
8802                                 hdcp_w->hdcp_content_type[connector->index] =
8803                                         new_con_state->hdcp_content_type;
8804                                 hdcp_w->content_protection[connector->index] =
8805                                         new_con_state->content_protection;
8806                         }
8807
8808                         if (new_crtc_state && new_crtc_state->mode_changed &&
8809                                 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED)
8810                                 enable_encryption = true;
8811
8812                         DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption);
8813
8814                         hdcp_update_display(
8815                                 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
8816                                 new_con_state->hdcp_content_type, enable_encryption);
8817                 }
8818         }
8819
8820         /* Handle connector state changes */
8821         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8822                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8823                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
8824                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8825                 struct dc_surface_update *dummy_updates;
8826                 struct dc_stream_update stream_update;
8827                 struct dc_info_packet hdr_packet;
8828                 struct dc_stream_status *status = NULL;
8829                 bool abm_changed, hdr_changed, scaling_changed;
8830
8831                 memset(&stream_update, 0, sizeof(stream_update));
8832
8833                 if (acrtc) {
8834                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8835                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8836                 }
8837
8838                 /* Skip any modesets/resets */
8839                 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
8840                         continue;
8841
8842                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8843                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8844
8845                 scaling_changed = is_scaling_state_different(dm_new_con_state,
8846                                                              dm_old_con_state);
8847
8848                 abm_changed = dm_new_crtc_state->abm_level !=
8849                               dm_old_crtc_state->abm_level;
8850
8851                 hdr_changed =
8852                         !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state);
8853
8854                 if (!scaling_changed && !abm_changed && !hdr_changed)
8855                         continue;
8856
8857                 stream_update.stream = dm_new_crtc_state->stream;
8858                 if (scaling_changed) {
8859                         update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
8860                                         dm_new_con_state, dm_new_crtc_state->stream);
8861
8862                         stream_update.src = dm_new_crtc_state->stream->src;
8863                         stream_update.dst = dm_new_crtc_state->stream->dst;
8864                 }
8865
8866                 if (abm_changed) {
8867                         dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
8868
8869                         stream_update.abm_level = &dm_new_crtc_state->abm_level;
8870                 }
8871
8872                 if (hdr_changed) {
8873                         fill_hdr_info_packet(new_con_state, &hdr_packet);
8874                         stream_update.hdr_static_metadata = &hdr_packet;
8875                 }
8876
8877                 status = dc_stream_get_status(dm_new_crtc_state->stream);
8878
8879                 if (WARN_ON(!status))
8880                         continue;
8881
8882                 WARN_ON(!status->plane_count);
8883
8884                 /*
8885                  * TODO: DC refuses to perform stream updates without a dc_surface_update.
8886                  * Here we create an empty update on each plane.
8887                  * To fix this, DC should permit updating only stream properties.
8888                  */
8889                 dummy_updates = kzalloc(sizeof(struct dc_surface_update) * MAX_SURFACES, GFP_ATOMIC);
8890                 for (j = 0; j < status->plane_count; j++)
8891                         dummy_updates[j].surface = status->plane_states[0];
8892
8893
8894                 mutex_lock(&dm->dc_lock);
8895                 dc_update_planes_and_stream(dm->dc,
8896                                             dummy_updates,
8897                                             status->plane_count,
8898                                             dm_new_crtc_state->stream,
8899                                             &stream_update);
8900                 mutex_unlock(&dm->dc_lock);
8901                 kfree(dummy_updates);
8902         }
8903
8904         /**
8905          * Enable interrupts for CRTCs that are newly enabled or went through
8906          * a modeset. It was intentionally deferred until after the front end
8907          * state was modified to wait until the OTG was on and so the IRQ
8908          * handlers didn't access stale or invalid state.
8909          */
8910         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8911                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8912 #ifdef CONFIG_DEBUG_FS
8913                 enum amdgpu_dm_pipe_crc_source cur_crc_src;
8914 #endif
8915                 /* Count number of newly disabled CRTCs for dropping PM refs later. */
8916                 if (old_crtc_state->active && !new_crtc_state->active)
8917                         crtc_disable_count++;
8918
8919                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8920                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8921
8922                 /* For freesync config update on crtc state and params for irq */
8923                 update_stream_irq_parameters(dm, dm_new_crtc_state);
8924
8925 #ifdef CONFIG_DEBUG_FS
8926                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8927                 cur_crc_src = acrtc->dm_irq_params.crc_src;
8928                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8929 #endif
8930
8931                 if (new_crtc_state->active &&
8932                     (!old_crtc_state->active ||
8933                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8934                         dc_stream_retain(dm_new_crtc_state->stream);
8935                         acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
8936                         manage_dm_interrupts(adev, acrtc, true);
8937                 }
8938                 /* Handle vrr on->off / off->on transitions */
8939                 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state);
8940
8941 #ifdef CONFIG_DEBUG_FS
8942                 if (new_crtc_state->active &&
8943                     (!old_crtc_state->active ||
8944                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8945                         /**
8946                          * Frontend may have changed so reapply the CRC capture
8947                          * settings for the stream.
8948                          */
8949                         if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
8950 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
8951                                 if (amdgpu_dm_crc_window_is_activated(crtc)) {
8952                                         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8953                                         acrtc->dm_irq_params.window_param.update_win = true;
8954
8955                                         /**
8956                                          * It takes 2 frames for HW to stably generate CRC when
8957                                          * resuming from suspend, so we set skip_frame_cnt 2.
8958                                          */
8959                                         acrtc->dm_irq_params.window_param.skip_frame_cnt = 2;
8960                                         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8961                                 }
8962 #endif
8963                                 if (amdgpu_dm_crtc_configure_crc_source(
8964                                         crtc, dm_new_crtc_state, cur_crc_src))
8965                                         DRM_DEBUG_DRIVER("Failed to configure crc source");
8966                         }
8967                 }
8968 #endif
8969         }
8970
8971         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
8972                 if (new_crtc_state->async_flip)
8973                         wait_for_vblank = false;
8974
8975         /* update planes when needed per crtc*/
8976         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
8977                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8978
8979                 if (dm_new_crtc_state->stream)
8980                         amdgpu_dm_commit_planes(state, dev, dm, crtc, wait_for_vblank);
8981         }
8982
8983         /* Update audio instances for each connector. */
8984         amdgpu_dm_commit_audio(dev, state);
8985
8986         /* restore the backlight level */
8987         for (i = 0; i < dm->num_of_edps; i++) {
8988                 if (dm->backlight_dev[i] &&
8989                     (dm->actual_brightness[i] != dm->brightness[i]))
8990                         amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
8991         }
8992
8993         /*
8994          * send vblank event on all events not handled in flip and
8995          * mark consumed event for drm_atomic_helper_commit_hw_done
8996          */
8997         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8998         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8999
9000                 if (new_crtc_state->event)
9001                         drm_send_event_locked(dev, &new_crtc_state->event->base);
9002
9003                 new_crtc_state->event = NULL;
9004         }
9005         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
9006
9007         /* Signal HW programming completion */
9008         drm_atomic_helper_commit_hw_done(state);
9009
9010         if (wait_for_vblank)
9011                 drm_atomic_helper_wait_for_flip_done(dev, state);
9012
9013         drm_atomic_helper_cleanup_planes(dev, state);
9014
9015         /* Don't free the memory if we are hitting this as part of suspend.
9016          * This way we don't free any memory during suspend; see
9017          * amdgpu_bo_free_kernel().  The memory will be freed in the first
9018          * non-suspend modeset or when the driver is torn down.
9019          */
9020         if (!adev->in_suspend) {
9021                 /* return the stolen vga memory back to VRAM */
9022                 if (!adev->mman.keep_stolen_vga_memory)
9023                         amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
9024                 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
9025         }
9026
9027         /*
9028          * Finally, drop a runtime PM reference for each newly disabled CRTC,
9029          * so we can put the GPU into runtime suspend if we're not driving any
9030          * displays anymore
9031          */
9032         for (i = 0; i < crtc_disable_count; i++)
9033                 pm_runtime_put_autosuspend(dev->dev);
9034         pm_runtime_mark_last_busy(dev->dev);
9035 }
9036
9037 static int dm_force_atomic_commit(struct drm_connector *connector)
9038 {
9039         int ret = 0;
9040         struct drm_device *ddev = connector->dev;
9041         struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
9042         struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
9043         struct drm_plane *plane = disconnected_acrtc->base.primary;
9044         struct drm_connector_state *conn_state;
9045         struct drm_crtc_state *crtc_state;
9046         struct drm_plane_state *plane_state;
9047
9048         if (!state)
9049                 return -ENOMEM;
9050
9051         state->acquire_ctx = ddev->mode_config.acquire_ctx;
9052
9053         /* Construct an atomic state to restore previous display setting */
9054
9055         /*
9056          * Attach connectors to drm_atomic_state
9057          */
9058         conn_state = drm_atomic_get_connector_state(state, connector);
9059
9060         ret = PTR_ERR_OR_ZERO(conn_state);
9061         if (ret)
9062                 goto out;
9063
9064         /* Attach crtc to drm_atomic_state*/
9065         crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
9066
9067         ret = PTR_ERR_OR_ZERO(crtc_state);
9068         if (ret)
9069                 goto out;
9070
9071         /* force a restore */
9072         crtc_state->mode_changed = true;
9073
9074         /* Attach plane to drm_atomic_state */
9075         plane_state = drm_atomic_get_plane_state(state, plane);
9076
9077         ret = PTR_ERR_OR_ZERO(plane_state);
9078         if (ret)
9079                 goto out;
9080
9081         /* Call commit internally with the state we just constructed */
9082         ret = drm_atomic_commit(state);
9083
9084 out:
9085         drm_atomic_state_put(state);
9086         if (ret)
9087                 DRM_ERROR("Restoring old state failed with %i\n", ret);
9088
9089         return ret;
9090 }
9091
9092 /*
9093  * This function handles all cases when set mode does not come upon hotplug.
9094  * This includes when a display is unplugged then plugged back into the
9095  * same port and when running without usermode desktop manager supprot
9096  */
9097 void dm_restore_drm_connector_state(struct drm_device *dev,
9098                                     struct drm_connector *connector)
9099 {
9100         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
9101         struct amdgpu_crtc *disconnected_acrtc;
9102         struct dm_crtc_state *acrtc_state;
9103
9104         if (!aconnector->dc_sink || !connector->state || !connector->encoder)
9105                 return;
9106
9107         disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
9108         if (!disconnected_acrtc)
9109                 return;
9110
9111         acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
9112         if (!acrtc_state->stream)
9113                 return;
9114
9115         /*
9116          * If the previous sink is not released and different from the current,
9117          * we deduce we are in a state where we can not rely on usermode call
9118          * to turn on the display, so we do it here
9119          */
9120         if (acrtc_state->stream->sink != aconnector->dc_sink)
9121                 dm_force_atomic_commit(&aconnector->base);
9122 }
9123
9124 /*
9125  * Grabs all modesetting locks to serialize against any blocking commits,
9126  * Waits for completion of all non blocking commits.
9127  */
9128 static int do_aquire_global_lock(struct drm_device *dev,
9129                                  struct drm_atomic_state *state)
9130 {
9131         struct drm_crtc *crtc;
9132         struct drm_crtc_commit *commit;
9133         long ret;
9134
9135         /*
9136          * Adding all modeset locks to aquire_ctx will
9137          * ensure that when the framework release it the
9138          * extra locks we are locking here will get released to
9139          */
9140         ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
9141         if (ret)
9142                 return ret;
9143
9144         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9145                 spin_lock(&crtc->commit_lock);
9146                 commit = list_first_entry_or_null(&crtc->commit_list,
9147                                 struct drm_crtc_commit, commit_entry);
9148                 if (commit)
9149                         drm_crtc_commit_get(commit);
9150                 spin_unlock(&crtc->commit_lock);
9151
9152                 if (!commit)
9153                         continue;
9154
9155                 /*
9156                  * Make sure all pending HW programming completed and
9157                  * page flips done
9158                  */
9159                 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
9160
9161                 if (ret > 0)
9162                         ret = wait_for_completion_interruptible_timeout(
9163                                         &commit->flip_done, 10*HZ);
9164
9165                 if (ret == 0)
9166                         DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done timed out\n",
9167                                   crtc->base.id, crtc->name);
9168
9169                 drm_crtc_commit_put(commit);
9170         }
9171
9172         return ret < 0 ? ret : 0;
9173 }
9174
9175 static void get_freesync_config_for_crtc(
9176         struct dm_crtc_state *new_crtc_state,
9177         struct dm_connector_state *new_con_state)
9178 {
9179         struct mod_freesync_config config = {0};
9180         struct amdgpu_dm_connector *aconnector =
9181                         to_amdgpu_dm_connector(new_con_state->base.connector);
9182         struct drm_display_mode *mode = &new_crtc_state->base.mode;
9183         int vrefresh = drm_mode_vrefresh(mode);
9184         bool fs_vid_mode = false;
9185
9186         new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
9187                                         vrefresh >= aconnector->min_vfreq &&
9188                                         vrefresh <= aconnector->max_vfreq;
9189
9190         if (new_crtc_state->vrr_supported) {
9191                 new_crtc_state->stream->ignore_msa_timing_param = true;
9192                 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
9193
9194                 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000;
9195                 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000;
9196                 config.vsif_supported = true;
9197                 config.btr = true;
9198
9199                 if (fs_vid_mode) {
9200                         config.state = VRR_STATE_ACTIVE_FIXED;
9201                         config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz;
9202                         goto out;
9203                 } else if (new_crtc_state->base.vrr_enabled) {
9204                         config.state = VRR_STATE_ACTIVE_VARIABLE;
9205                 } else {
9206                         config.state = VRR_STATE_INACTIVE;
9207                 }
9208         }
9209 out:
9210         new_crtc_state->freesync_config = config;
9211 }
9212
9213 static void reset_freesync_config_for_crtc(
9214         struct dm_crtc_state *new_crtc_state)
9215 {
9216         new_crtc_state->vrr_supported = false;
9217
9218         memset(&new_crtc_state->vrr_infopacket, 0,
9219                sizeof(new_crtc_state->vrr_infopacket));
9220 }
9221
9222 static bool
9223 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
9224                                  struct drm_crtc_state *new_crtc_state)
9225 {
9226         const struct drm_display_mode *old_mode, *new_mode;
9227
9228         if (!old_crtc_state || !new_crtc_state)
9229                 return false;
9230
9231         old_mode = &old_crtc_state->mode;
9232         new_mode = &new_crtc_state->mode;
9233
9234         if (old_mode->clock       == new_mode->clock &&
9235             old_mode->hdisplay    == new_mode->hdisplay &&
9236             old_mode->vdisplay    == new_mode->vdisplay &&
9237             old_mode->htotal      == new_mode->htotal &&
9238             old_mode->vtotal      != new_mode->vtotal &&
9239             old_mode->hsync_start == new_mode->hsync_start &&
9240             old_mode->vsync_start != new_mode->vsync_start &&
9241             old_mode->hsync_end   == new_mode->hsync_end &&
9242             old_mode->vsync_end   != new_mode->vsync_end &&
9243             old_mode->hskew       == new_mode->hskew &&
9244             old_mode->vscan       == new_mode->vscan &&
9245             (old_mode->vsync_end - old_mode->vsync_start) ==
9246             (new_mode->vsync_end - new_mode->vsync_start))
9247                 return true;
9248
9249         return false;
9250 }
9251
9252 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state)
9253 {
9254         u64 num, den, res;
9255         struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
9256
9257         dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;
9258
9259         num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000;
9260         den = (unsigned long long)new_crtc_state->mode.htotal *
9261               (unsigned long long)new_crtc_state->mode.vtotal;
9262
9263         res = div_u64(num, den);
9264         dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
9265 }
9266
9267 static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
9268                          struct drm_atomic_state *state,
9269                          struct drm_crtc *crtc,
9270                          struct drm_crtc_state *old_crtc_state,
9271                          struct drm_crtc_state *new_crtc_state,
9272                          bool enable,
9273                          bool *lock_and_validation_needed)
9274 {
9275         struct dm_atomic_state *dm_state = NULL;
9276         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9277         struct dc_stream_state *new_stream;
9278         int ret = 0;
9279
9280         /*
9281          * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
9282          * update changed items
9283          */
9284         struct amdgpu_crtc *acrtc = NULL;
9285         struct amdgpu_dm_connector *aconnector = NULL;
9286         struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
9287         struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
9288
9289         new_stream = NULL;
9290
9291         dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9292         dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9293         acrtc = to_amdgpu_crtc(crtc);
9294         aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
9295
9296         /* TODO This hack should go away */
9297         if (aconnector && enable) {
9298                 /* Make sure fake sink is created in plug-in scenario */
9299                 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
9300                                                             &aconnector->base);
9301                 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
9302                                                             &aconnector->base);
9303
9304                 if (IS_ERR(drm_new_conn_state)) {
9305                         ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
9306                         goto fail;
9307                 }
9308
9309                 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
9310                 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
9311
9312                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9313                         goto skip_modeset;
9314
9315                 new_stream = create_validate_stream_for_sink(aconnector,
9316                                                              &new_crtc_state->mode,
9317                                                              dm_new_conn_state,
9318                                                              dm_old_crtc_state->stream);
9319
9320                 /*
9321                  * we can have no stream on ACTION_SET if a display
9322                  * was disconnected during S3, in this case it is not an
9323                  * error, the OS will be updated after detection, and
9324                  * will do the right thing on next atomic commit
9325                  */
9326
9327                 if (!new_stream) {
9328                         DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
9329                                         __func__, acrtc->base.base.id);
9330                         ret = -ENOMEM;
9331                         goto fail;
9332                 }
9333
9334                 /*
9335                  * TODO: Check VSDB bits to decide whether this should
9336                  * be enabled or not.
9337                  */
9338                 new_stream->triggered_crtc_reset.enabled =
9339                         dm->force_timing_sync;
9340
9341                 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9342
9343                 ret = fill_hdr_info_packet(drm_new_conn_state,
9344                                            &new_stream->hdr_static_metadata);
9345                 if (ret)
9346                         goto fail;
9347
9348                 /*
9349                  * If we already removed the old stream from the context
9350                  * (and set the new stream to NULL) then we can't reuse
9351                  * the old stream even if the stream and scaling are unchanged.
9352                  * We'll hit the BUG_ON and black screen.
9353                  *
9354                  * TODO: Refactor this function to allow this check to work
9355                  * in all conditions.
9356                  */
9357                 if (dm_new_crtc_state->stream &&
9358                     is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))
9359                         goto skip_modeset;
9360
9361                 if (dm_new_crtc_state->stream &&
9362                     dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9363                     dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
9364                         new_crtc_state->mode_changed = false;
9365                         DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
9366                                          new_crtc_state->mode_changed);
9367                 }
9368         }
9369
9370         /* mode_changed flag may get updated above, need to check again */
9371         if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9372                 goto skip_modeset;
9373
9374         drm_dbg_state(state->dev,
9375                 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n",
9376                 acrtc->crtc_id,
9377                 new_crtc_state->enable,
9378                 new_crtc_state->active,
9379                 new_crtc_state->planes_changed,
9380                 new_crtc_state->mode_changed,
9381                 new_crtc_state->active_changed,
9382                 new_crtc_state->connectors_changed);
9383
9384         /* Remove stream for any changed/disabled CRTC */
9385         if (!enable) {
9386
9387                 if (!dm_old_crtc_state->stream)
9388                         goto skip_modeset;
9389
9390                 /* Unset freesync video if it was active before */
9391                 if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) {
9392                         dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE;
9393                         dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0;
9394                 }
9395
9396                 /* Now check if we should set freesync video mode */
9397                 if (dm_new_crtc_state->stream &&
9398                     dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9399                     dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream) &&
9400                     is_timing_unchanged_for_freesync(new_crtc_state,
9401                                                      old_crtc_state)) {
9402                         new_crtc_state->mode_changed = false;
9403                         DRM_DEBUG_DRIVER(
9404                                 "Mode change not required for front porch change, setting mode_changed to %d",
9405                                 new_crtc_state->mode_changed);
9406
9407                         set_freesync_fixed_config(dm_new_crtc_state);
9408
9409                         goto skip_modeset;
9410                 } else if (aconnector &&
9411                            is_freesync_video_mode(&new_crtc_state->mode,
9412                                                   aconnector)) {
9413                         struct drm_display_mode *high_mode;
9414
9415                         high_mode = get_highest_refresh_rate_mode(aconnector, false);
9416                         if (!drm_mode_equal(&new_crtc_state->mode, high_mode))
9417                                 set_freesync_fixed_config(dm_new_crtc_state);
9418                 }
9419
9420                 ret = dm_atomic_get_state(state, &dm_state);
9421                 if (ret)
9422                         goto fail;
9423
9424                 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
9425                                 crtc->base.id);
9426
9427                 /* i.e. reset mode */
9428                 if (dc_remove_stream_from_ctx(
9429                                 dm->dc,
9430                                 dm_state->context,
9431                                 dm_old_crtc_state->stream) != DC_OK) {
9432                         ret = -EINVAL;
9433                         goto fail;
9434                 }
9435
9436                 dc_stream_release(dm_old_crtc_state->stream);
9437                 dm_new_crtc_state->stream = NULL;
9438
9439                 reset_freesync_config_for_crtc(dm_new_crtc_state);
9440
9441                 *lock_and_validation_needed = true;
9442
9443         } else {/* Add stream for any updated/enabled CRTC */
9444                 /*
9445                  * Quick fix to prevent NULL pointer on new_stream when
9446                  * added MST connectors not found in existing crtc_state in the chained mode
9447                  * TODO: need to dig out the root cause of that
9448                  */
9449                 if (!aconnector)
9450                         goto skip_modeset;
9451
9452                 if (modereset_required(new_crtc_state))
9453                         goto skip_modeset;
9454
9455                 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream,
9456                                      dm_old_crtc_state->stream)) {
9457
9458                         WARN_ON(dm_new_crtc_state->stream);
9459
9460                         ret = dm_atomic_get_state(state, &dm_state);
9461                         if (ret)
9462                                 goto fail;
9463
9464                         dm_new_crtc_state->stream = new_stream;
9465
9466                         dc_stream_retain(new_stream);
9467
9468                         DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n",
9469                                          crtc->base.id);
9470
9471                         if (dc_add_stream_to_ctx(
9472                                         dm->dc,
9473                                         dm_state->context,
9474                                         dm_new_crtc_state->stream) != DC_OK) {
9475                                 ret = -EINVAL;
9476                                 goto fail;
9477                         }
9478
9479                         *lock_and_validation_needed = true;
9480                 }
9481         }
9482
9483 skip_modeset:
9484         /* Release extra reference */
9485         if (new_stream)
9486                 dc_stream_release(new_stream);
9487
9488         /*
9489          * We want to do dc stream updates that do not require a
9490          * full modeset below.
9491          */
9492         if (!(enable && aconnector && new_crtc_state->active))
9493                 return 0;
9494         /*
9495          * Given above conditions, the dc state cannot be NULL because:
9496          * 1. We're in the process of enabling CRTCs (just been added
9497          *    to the dc context, or already is on the context)
9498          * 2. Has a valid connector attached, and
9499          * 3. Is currently active and enabled.
9500          * => The dc stream state currently exists.
9501          */
9502         BUG_ON(dm_new_crtc_state->stream == NULL);
9503
9504         /* Scaling or underscan settings */
9505         if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) ||
9506                                 drm_atomic_crtc_needs_modeset(new_crtc_state))
9507                 update_stream_scaling_settings(
9508                         &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
9509
9510         /* ABM settings */
9511         dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9512
9513         /*
9514          * Color management settings. We also update color properties
9515          * when a modeset is needed, to ensure it gets reprogrammed.
9516          */
9517         if (dm_new_crtc_state->base.color_mgmt_changed ||
9518             drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9519                 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
9520                 if (ret)
9521                         goto fail;
9522         }
9523
9524         /* Update Freesync settings. */
9525         get_freesync_config_for_crtc(dm_new_crtc_state,
9526                                      dm_new_conn_state);
9527
9528         return ret;
9529
9530 fail:
9531         if (new_stream)
9532                 dc_stream_release(new_stream);
9533         return ret;
9534 }
9535
9536 static bool should_reset_plane(struct drm_atomic_state *state,
9537                                struct drm_plane *plane,
9538                                struct drm_plane_state *old_plane_state,
9539                                struct drm_plane_state *new_plane_state)
9540 {
9541         struct drm_plane *other;
9542         struct drm_plane_state *old_other_state, *new_other_state;
9543         struct drm_crtc_state *new_crtc_state;
9544         int i;
9545
9546         /*
9547          * TODO: Remove this hack once the checks below are sufficient
9548          * enough to determine when we need to reset all the planes on
9549          * the stream.
9550          */
9551         if (state->allow_modeset)
9552                 return true;
9553
9554         /* Exit early if we know that we're adding or removing the plane. */
9555         if (old_plane_state->crtc != new_plane_state->crtc)
9556                 return true;
9557
9558         /* old crtc == new_crtc == NULL, plane not in context. */
9559         if (!new_plane_state->crtc)
9560                 return false;
9561
9562         new_crtc_state =
9563                 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
9564
9565         if (!new_crtc_state)
9566                 return true;
9567
9568         /* CRTC Degamma changes currently require us to recreate planes. */
9569         if (new_crtc_state->color_mgmt_changed)
9570                 return true;
9571
9572         if (drm_atomic_crtc_needs_modeset(new_crtc_state))
9573                 return true;
9574
9575         /*
9576          * If there are any new primary or overlay planes being added or
9577          * removed then the z-order can potentially change. To ensure
9578          * correct z-order and pipe acquisition the current DC architecture
9579          * requires us to remove and recreate all existing planes.
9580          *
9581          * TODO: Come up with a more elegant solution for this.
9582          */
9583         for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
9584                 struct amdgpu_framebuffer *old_afb, *new_afb;
9585
9586                 if (other->type == DRM_PLANE_TYPE_CURSOR)
9587                         continue;
9588
9589                 if (old_other_state->crtc != new_plane_state->crtc &&
9590                     new_other_state->crtc != new_plane_state->crtc)
9591                         continue;
9592
9593                 if (old_other_state->crtc != new_other_state->crtc)
9594                         return true;
9595
9596                 /* Src/dst size and scaling updates. */
9597                 if (old_other_state->src_w != new_other_state->src_w ||
9598                     old_other_state->src_h != new_other_state->src_h ||
9599                     old_other_state->crtc_w != new_other_state->crtc_w ||
9600                     old_other_state->crtc_h != new_other_state->crtc_h)
9601                         return true;
9602
9603                 /* Rotation / mirroring updates. */
9604                 if (old_other_state->rotation != new_other_state->rotation)
9605                         return true;
9606
9607                 /* Blending updates. */
9608                 if (old_other_state->pixel_blend_mode !=
9609                     new_other_state->pixel_blend_mode)
9610                         return true;
9611
9612                 /* Alpha updates. */
9613                 if (old_other_state->alpha != new_other_state->alpha)
9614                         return true;
9615
9616                 /* Colorspace changes. */
9617                 if (old_other_state->color_range != new_other_state->color_range ||
9618                     old_other_state->color_encoding != new_other_state->color_encoding)
9619                         return true;
9620
9621                 /* Framebuffer checks fall at the end. */
9622                 if (!old_other_state->fb || !new_other_state->fb)
9623                         continue;
9624
9625                 /* Pixel format changes can require bandwidth updates. */
9626                 if (old_other_state->fb->format != new_other_state->fb->format)
9627                         return true;
9628
9629                 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb;
9630                 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb;
9631
9632                 /* Tiling and DCC changes also require bandwidth updates. */
9633                 if (old_afb->tiling_flags != new_afb->tiling_flags ||
9634                     old_afb->base.modifier != new_afb->base.modifier)
9635                         return true;
9636         }
9637
9638         return false;
9639 }
9640
9641 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,
9642                               struct drm_plane_state *new_plane_state,
9643                               struct drm_framebuffer *fb)
9644 {
9645         struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev);
9646         struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
9647         unsigned int pitch;
9648         bool linear;
9649
9650         if (fb->width > new_acrtc->max_cursor_width ||
9651             fb->height > new_acrtc->max_cursor_height) {
9652                 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n",
9653                                  new_plane_state->fb->width,
9654                                  new_plane_state->fb->height);
9655                 return -EINVAL;
9656         }
9657         if (new_plane_state->src_w != fb->width << 16 ||
9658             new_plane_state->src_h != fb->height << 16) {
9659                 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9660                 return -EINVAL;
9661         }
9662
9663         /* Pitch in pixels */
9664         pitch = fb->pitches[0] / fb->format->cpp[0];
9665
9666         if (fb->width != pitch) {
9667                 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d",
9668                                  fb->width, pitch);
9669                 return -EINVAL;
9670         }
9671
9672         switch (pitch) {
9673         case 64:
9674         case 128:
9675         case 256:
9676                 /* FB pitch is supported by cursor plane */
9677                 break;
9678         default:
9679                 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch);
9680                 return -EINVAL;
9681         }
9682
9683         /* Core DRM takes care of checking FB modifiers, so we only need to
9684          * check tiling flags when the FB doesn't have a modifier.
9685          */
9686         if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) {
9687                 if (adev->family < AMDGPU_FAMILY_AI) {
9688                         linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &&
9689                                  AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &&
9690                                  AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0;
9691                 } else {
9692                         linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;
9693                 }
9694                 if (!linear) {
9695                         DRM_DEBUG_ATOMIC("Cursor FB not linear");
9696                         return -EINVAL;
9697                 }
9698         }
9699
9700         return 0;
9701 }
9702
9703 static int dm_update_plane_state(struct dc *dc,
9704                                  struct drm_atomic_state *state,
9705                                  struct drm_plane *plane,
9706                                  struct drm_plane_state *old_plane_state,
9707                                  struct drm_plane_state *new_plane_state,
9708                                  bool enable,
9709                                  bool *lock_and_validation_needed,
9710                                  bool *is_top_most_overlay)
9711 {
9712
9713         struct dm_atomic_state *dm_state = NULL;
9714         struct drm_crtc *new_plane_crtc, *old_plane_crtc;
9715         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9716         struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
9717         struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
9718         struct amdgpu_crtc *new_acrtc;
9719         bool needs_reset;
9720         int ret = 0;
9721
9722
9723         new_plane_crtc = new_plane_state->crtc;
9724         old_plane_crtc = old_plane_state->crtc;
9725         dm_new_plane_state = to_dm_plane_state(new_plane_state);
9726         dm_old_plane_state = to_dm_plane_state(old_plane_state);
9727
9728         if (plane->type == DRM_PLANE_TYPE_CURSOR) {
9729                 if (!enable || !new_plane_crtc ||
9730                         drm_atomic_plane_disabling(plane->state, new_plane_state))
9731                         return 0;
9732
9733                 new_acrtc = to_amdgpu_crtc(new_plane_crtc);
9734
9735                 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) {
9736                         DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9737                         return -EINVAL;
9738                 }
9739
9740                 if (new_plane_state->fb) {
9741                         ret = dm_check_cursor_fb(new_acrtc, new_plane_state,
9742                                                  new_plane_state->fb);
9743                         if (ret)
9744                                 return ret;
9745                 }
9746
9747                 return 0;
9748         }
9749
9750         needs_reset = should_reset_plane(state, plane, old_plane_state,
9751                                          new_plane_state);
9752
9753         /* Remove any changed/removed planes */
9754         if (!enable) {
9755                 if (!needs_reset)
9756                         return 0;
9757
9758                 if (!old_plane_crtc)
9759                         return 0;
9760
9761                 old_crtc_state = drm_atomic_get_old_crtc_state(
9762                                 state, old_plane_crtc);
9763                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9764
9765                 if (!dm_old_crtc_state->stream)
9766                         return 0;
9767
9768                 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
9769                                 plane->base.id, old_plane_crtc->base.id);
9770
9771                 ret = dm_atomic_get_state(state, &dm_state);
9772                 if (ret)
9773                         return ret;
9774
9775                 if (!dc_remove_plane_from_context(
9776                                 dc,
9777                                 dm_old_crtc_state->stream,
9778                                 dm_old_plane_state->dc_state,
9779                                 dm_state->context)) {
9780
9781                         return -EINVAL;
9782                 }
9783
9784                 if (dm_old_plane_state->dc_state)
9785                         dc_plane_state_release(dm_old_plane_state->dc_state);
9786
9787                 dm_new_plane_state->dc_state = NULL;
9788
9789                 *lock_and_validation_needed = true;
9790
9791         } else { /* Add new planes */
9792                 struct dc_plane_state *dc_new_plane_state;
9793
9794                 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
9795                         return 0;
9796
9797                 if (!new_plane_crtc)
9798                         return 0;
9799
9800                 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
9801                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9802
9803                 if (!dm_new_crtc_state->stream)
9804                         return 0;
9805
9806                 if (!needs_reset)
9807                         return 0;
9808
9809                 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state);
9810                 if (ret)
9811                         return ret;
9812
9813                 WARN_ON(dm_new_plane_state->dc_state);
9814
9815                 dc_new_plane_state = dc_create_plane_state(dc);
9816                 if (!dc_new_plane_state)
9817                         return -ENOMEM;
9818
9819                 /* Block top most plane from being a video plane */
9820                 if (plane->type == DRM_PLANE_TYPE_OVERLAY) {
9821                         if (is_video_format(new_plane_state->fb->format->format) && *is_top_most_overlay)
9822                                 return -EINVAL;
9823
9824                         *is_top_most_overlay = false;
9825                 }
9826
9827                 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n",
9828                                  plane->base.id, new_plane_crtc->base.id);
9829
9830                 ret = fill_dc_plane_attributes(
9831                         drm_to_adev(new_plane_crtc->dev),
9832                         dc_new_plane_state,
9833                         new_plane_state,
9834                         new_crtc_state);
9835                 if (ret) {
9836                         dc_plane_state_release(dc_new_plane_state);
9837                         return ret;
9838                 }
9839
9840                 ret = dm_atomic_get_state(state, &dm_state);
9841                 if (ret) {
9842                         dc_plane_state_release(dc_new_plane_state);
9843                         return ret;
9844                 }
9845
9846                 /*
9847                  * Any atomic check errors that occur after this will
9848                  * not need a release. The plane state will be attached
9849                  * to the stream, and therefore part of the atomic
9850                  * state. It'll be released when the atomic state is
9851                  * cleaned.
9852                  */
9853                 if (!dc_add_plane_to_context(
9854                                 dc,
9855                                 dm_new_crtc_state->stream,
9856                                 dc_new_plane_state,
9857                                 dm_state->context)) {
9858
9859                         dc_plane_state_release(dc_new_plane_state);
9860                         return -EINVAL;
9861                 }
9862
9863                 dm_new_plane_state->dc_state = dc_new_plane_state;
9864
9865                 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY);
9866
9867                 /* Tell DC to do a full surface update every time there
9868                  * is a plane change. Inefficient, but works for now.
9869                  */
9870                 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
9871
9872                 *lock_and_validation_needed = true;
9873         }
9874
9875
9876         return ret;
9877 }
9878
9879 static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state,
9880                                        int *src_w, int *src_h)
9881 {
9882         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
9883         case DRM_MODE_ROTATE_90:
9884         case DRM_MODE_ROTATE_270:
9885                 *src_w = plane_state->src_h >> 16;
9886                 *src_h = plane_state->src_w >> 16;
9887                 break;
9888         case DRM_MODE_ROTATE_0:
9889         case DRM_MODE_ROTATE_180:
9890         default:
9891                 *src_w = plane_state->src_w >> 16;
9892                 *src_h = plane_state->src_h >> 16;
9893                 break;
9894         }
9895 }
9896
9897 static void
9898 dm_get_plane_scale(struct drm_plane_state *plane_state,
9899                    int *out_plane_scale_w, int *out_plane_scale_h)
9900 {
9901         int plane_src_w, plane_src_h;
9902
9903         dm_get_oriented_plane_size(plane_state, &plane_src_w, &plane_src_h);
9904         *out_plane_scale_w = plane_state->crtc_w * 1000 / plane_src_w;
9905         *out_plane_scale_h = plane_state->crtc_h * 1000 / plane_src_h;
9906 }
9907
9908 static int dm_check_crtc_cursor(struct drm_atomic_state *state,
9909                                 struct drm_crtc *crtc,
9910                                 struct drm_crtc_state *new_crtc_state)
9911 {
9912         struct drm_plane *cursor = crtc->cursor, *plane, *underlying;
9913         struct drm_plane_state *old_plane_state, *new_plane_state;
9914         struct drm_plane_state *new_cursor_state, *new_underlying_state;
9915         int i;
9916         int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h;
9917         bool any_relevant_change = false;
9918
9919         /* On DCE and DCN there is no dedicated hardware cursor plane. We get a
9920          * cursor per pipe but it's going to inherit the scaling and
9921          * positioning from the underlying pipe. Check the cursor plane's
9922          * blending properties match the underlying planes'.
9923          */
9924
9925         /* If no plane was enabled or changed scaling, no need to check again */
9926         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
9927                 int new_scale_w, new_scale_h, old_scale_w, old_scale_h;
9928
9929                 if (!new_plane_state || !new_plane_state->fb || new_plane_state->crtc != crtc)
9930                         continue;
9931
9932                 if (!old_plane_state || !old_plane_state->fb || old_plane_state->crtc != crtc) {
9933                         any_relevant_change = true;
9934                         break;
9935                 }
9936
9937                 if (new_plane_state->fb == old_plane_state->fb &&
9938                     new_plane_state->crtc_w == old_plane_state->crtc_w &&
9939                     new_plane_state->crtc_h == old_plane_state->crtc_h)
9940                         continue;
9941
9942                 dm_get_plane_scale(new_plane_state, &new_scale_w, &new_scale_h);
9943                 dm_get_plane_scale(old_plane_state, &old_scale_w, &old_scale_h);
9944
9945                 if (new_scale_w != old_scale_w || new_scale_h != old_scale_h) {
9946                         any_relevant_change = true;
9947                         break;
9948                 }
9949         }
9950
9951         if (!any_relevant_change)
9952                 return 0;
9953
9954         new_cursor_state = drm_atomic_get_plane_state(state, cursor);
9955         if (IS_ERR(new_cursor_state))
9956                 return PTR_ERR(new_cursor_state);
9957
9958         if (!new_cursor_state->fb)
9959                 return 0;
9960
9961         dm_get_plane_scale(new_cursor_state, &cursor_scale_w, &cursor_scale_h);
9962
9963         /* Need to check all enabled planes, even if this commit doesn't change
9964          * their state
9965          */
9966         i = drm_atomic_add_affected_planes(state, crtc);
9967         if (i)
9968                 return i;
9969
9970         for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) {
9971                 /* Narrow down to non-cursor planes on the same CRTC as the cursor */
9972                 if (new_underlying_state->crtc != crtc || underlying == crtc->cursor)
9973                         continue;
9974
9975                 /* Ignore disabled planes */
9976                 if (!new_underlying_state->fb)
9977                         continue;
9978
9979                 dm_get_plane_scale(new_underlying_state,
9980                                    &underlying_scale_w, &underlying_scale_h);
9981
9982                 if (cursor_scale_w != underlying_scale_w ||
9983                     cursor_scale_h != underlying_scale_h) {
9984                         drm_dbg_atomic(crtc->dev,
9985                                        "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n",
9986                                        cursor->base.id, cursor->name, underlying->base.id, underlying->name);
9987                         return -EINVAL;
9988                 }
9989
9990                 /* If this plane covers the whole CRTC, no need to check planes underneath */
9991                 if (new_underlying_state->crtc_x <= 0 &&
9992                     new_underlying_state->crtc_y <= 0 &&
9993                     new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay &&
9994                     new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay)
9995                         break;
9996         }
9997
9998         return 0;
9999 }
10000
10001 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
10002 {
10003         struct drm_connector *connector;
10004         struct drm_connector_state *conn_state, *old_conn_state;
10005         struct amdgpu_dm_connector *aconnector = NULL;
10006         int i;
10007
10008         for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) {
10009                 if (!conn_state->crtc)
10010                         conn_state = old_conn_state;
10011
10012                 if (conn_state->crtc != crtc)
10013                         continue;
10014
10015                 aconnector = to_amdgpu_dm_connector(connector);
10016                 if (!aconnector->mst_output_port || !aconnector->mst_root)
10017                         aconnector = NULL;
10018                 else
10019                         break;
10020         }
10021
10022         if (!aconnector)
10023                 return 0;
10024
10025         return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr);
10026 }
10027
10028 /**
10029  * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
10030  *
10031  * @dev: The DRM device
10032  * @state: The atomic state to commit
10033  *
10034  * Validate that the given atomic state is programmable by DC into hardware.
10035  * This involves constructing a &struct dc_state reflecting the new hardware
10036  * state we wish to commit, then querying DC to see if it is programmable. It's
10037  * important not to modify the existing DC state. Otherwise, atomic_check
10038  * may unexpectedly commit hardware changes.
10039  *
10040  * When validating the DC state, it's important that the right locks are
10041  * acquired. For full updates case which removes/adds/updates streams on one
10042  * CRTC while flipping on another CRTC, acquiring global lock will guarantee
10043  * that any such full update commit will wait for completion of any outstanding
10044  * flip using DRMs synchronization events.
10045  *
10046  * Note that DM adds the affected connectors for all CRTCs in state, when that
10047  * might not seem necessary. This is because DC stream creation requires the
10048  * DC sink, which is tied to the DRM connector state. Cleaning this up should
10049  * be possible but non-trivial - a possible TODO item.
10050  *
10051  * Return: -Error code if validation failed.
10052  */
10053 static int amdgpu_dm_atomic_check(struct drm_device *dev,
10054                                   struct drm_atomic_state *state)
10055 {
10056         struct amdgpu_device *adev = drm_to_adev(dev);
10057         struct dm_atomic_state *dm_state = NULL;
10058         struct dc *dc = adev->dm.dc;
10059         struct drm_connector *connector;
10060         struct drm_connector_state *old_con_state, *new_con_state;
10061         struct drm_crtc *crtc;
10062         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
10063         struct drm_plane *plane;
10064         struct drm_plane_state *old_plane_state, *new_plane_state;
10065         enum dc_status status;
10066         int ret, i;
10067         bool lock_and_validation_needed = false;
10068         bool is_top_most_overlay = true;
10069         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
10070         struct drm_dp_mst_topology_mgr *mgr;
10071         struct drm_dp_mst_topology_state *mst_state;
10072         struct dsc_mst_fairness_vars vars[MAX_PIPES];
10073
10074         trace_amdgpu_dm_atomic_check_begin(state);
10075
10076         ret = drm_atomic_helper_check_modeset(dev, state);
10077         if (ret) {
10078                 DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n");
10079                 goto fail;
10080         }
10081
10082         /* Check connector changes */
10083         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
10084                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
10085                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10086
10087                 /* Skip connectors that are disabled or part of modeset already. */
10088                 if (!new_con_state->crtc)
10089                         continue;
10090
10091                 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc);
10092                 if (IS_ERR(new_crtc_state)) {
10093                         DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n");
10094                         ret = PTR_ERR(new_crtc_state);
10095                         goto fail;
10096                 }
10097
10098                 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level ||
10099                     dm_old_con_state->scaling != dm_new_con_state->scaling)
10100                         new_crtc_state->connectors_changed = true;
10101         }
10102
10103         if (dc_resource_is_dsc_encoding_supported(dc)) {
10104                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10105                         if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
10106                                 ret = add_affected_mst_dsc_crtcs(state, crtc);
10107                                 if (ret) {
10108                                         DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n");
10109                                         goto fail;
10110                                 }
10111                         }
10112                 }
10113         }
10114         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10115                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
10116
10117                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
10118                     !new_crtc_state->color_mgmt_changed &&
10119                     old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled &&
10120                         dm_old_crtc_state->dsc_force_changed == false)
10121                         continue;
10122
10123                 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state);
10124                 if (ret) {
10125                         DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n");
10126                         goto fail;
10127                 }
10128
10129                 if (!new_crtc_state->enable)
10130                         continue;
10131
10132                 ret = drm_atomic_add_affected_connectors(state, crtc);
10133                 if (ret) {
10134                         DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n");
10135                         goto fail;
10136                 }
10137
10138                 ret = drm_atomic_add_affected_planes(state, crtc);
10139                 if (ret) {
10140                         DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n");
10141                         goto fail;
10142                 }
10143
10144                 if (dm_old_crtc_state->dsc_force_changed)
10145                         new_crtc_state->mode_changed = true;
10146         }
10147
10148         /*
10149          * Add all primary and overlay planes on the CRTC to the state
10150          * whenever a plane is enabled to maintain correct z-ordering
10151          * and to enable fast surface updates.
10152          */
10153         drm_for_each_crtc(crtc, dev) {
10154                 bool modified = false;
10155
10156                 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
10157                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
10158                                 continue;
10159
10160                         if (new_plane_state->crtc == crtc ||
10161                             old_plane_state->crtc == crtc) {
10162                                 modified = true;
10163                                 break;
10164                         }
10165                 }
10166
10167                 if (!modified)
10168                         continue;
10169
10170                 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
10171                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
10172                                 continue;
10173
10174                         new_plane_state =
10175                                 drm_atomic_get_plane_state(state, plane);
10176
10177                         if (IS_ERR(new_plane_state)) {
10178                                 ret = PTR_ERR(new_plane_state);
10179                                 DRM_DEBUG_DRIVER("new_plane_state is BAD\n");
10180                                 goto fail;
10181                         }
10182                 }
10183         }
10184
10185         /*
10186          * DC consults the zpos (layer_index in DC terminology) to determine the
10187          * hw plane on which to enable the hw cursor (see
10188          * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in
10189          * atomic state, so call drm helper to normalize zpos.
10190          */
10191         ret = drm_atomic_normalize_zpos(dev, state);
10192         if (ret) {
10193                 drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n");
10194                 goto fail;
10195         }
10196
10197         /* Remove exiting planes if they are modified */
10198         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10199                 if (old_plane_state->fb && new_plane_state->fb &&
10200                     get_mem_type(old_plane_state->fb) !=
10201                     get_mem_type(new_plane_state->fb))
10202                         lock_and_validation_needed = true;
10203
10204                 ret = dm_update_plane_state(dc, state, plane,
10205                                             old_plane_state,
10206                                             new_plane_state,
10207                                             false,
10208                                             &lock_and_validation_needed,
10209                                             &is_top_most_overlay);
10210                 if (ret) {
10211                         DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10212                         goto fail;
10213                 }
10214         }
10215
10216         /* Disable all crtcs which require disable */
10217         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10218                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10219                                            old_crtc_state,
10220                                            new_crtc_state,
10221                                            false,
10222                                            &lock_and_validation_needed);
10223                 if (ret) {
10224                         DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n");
10225                         goto fail;
10226                 }
10227         }
10228
10229         /* Enable all crtcs which require enable */
10230         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10231                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10232                                            old_crtc_state,
10233                                            new_crtc_state,
10234                                            true,
10235                                            &lock_and_validation_needed);
10236                 if (ret) {
10237                         DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n");
10238                         goto fail;
10239                 }
10240         }
10241
10242         /* Add new/modified planes */
10243         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10244                 ret = dm_update_plane_state(dc, state, plane,
10245                                             old_plane_state,
10246                                             new_plane_state,
10247                                             true,
10248                                             &lock_and_validation_needed,
10249                                             &is_top_most_overlay);
10250                 if (ret) {
10251                         DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10252                         goto fail;
10253                 }
10254         }
10255
10256         if (dc_resource_is_dsc_encoding_supported(dc)) {
10257                 ret = pre_validate_dsc(state, &dm_state, vars);
10258                 if (ret != 0)
10259                         goto fail;
10260         }
10261
10262         /* Run this here since we want to validate the streams we created */
10263         ret = drm_atomic_helper_check_planes(dev, state);
10264         if (ret) {
10265                 DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n");
10266                 goto fail;
10267         }
10268
10269         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10270                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
10271                 if (dm_new_crtc_state->mpo_requested)
10272                         DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc);
10273         }
10274
10275         /* Check cursor planes scaling */
10276         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10277                 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state);
10278                 if (ret) {
10279                         DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n");
10280                         goto fail;
10281                 }
10282         }
10283
10284         if (state->legacy_cursor_update) {
10285                 /*
10286                  * This is a fast cursor update coming from the plane update
10287                  * helper, check if it can be done asynchronously for better
10288                  * performance.
10289                  */
10290                 state->async_update =
10291                         !drm_atomic_helper_async_check(dev, state);
10292
10293                 /*
10294                  * Skip the remaining global validation if this is an async
10295                  * update. Cursor updates can be done without affecting
10296                  * state or bandwidth calcs and this avoids the performance
10297                  * penalty of locking the private state object and
10298                  * allocating a new dc_state.
10299                  */
10300                 if (state->async_update)
10301                         return 0;
10302         }
10303
10304         /* Check scaling and underscan changes*/
10305         /* TODO Removed scaling changes validation due to inability to commit
10306          * new stream into context w\o causing full reset. Need to
10307          * decide how to handle.
10308          */
10309         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
10310                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
10311                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10312                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
10313
10314                 /* Skip any modesets/resets */
10315                 if (!acrtc || drm_atomic_crtc_needs_modeset(
10316                                 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
10317                         continue;
10318
10319                 /* Skip any thing not scale or underscan changes */
10320                 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
10321                         continue;
10322
10323                 lock_and_validation_needed = true;
10324         }
10325
10326         /* set the slot info for each mst_state based on the link encoding format */
10327         for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
10328                 struct amdgpu_dm_connector *aconnector;
10329                 struct drm_connector *connector;
10330                 struct drm_connector_list_iter iter;
10331                 u8 link_coding_cap;
10332
10333                 drm_connector_list_iter_begin(dev, &iter);
10334                 drm_for_each_connector_iter(connector, &iter) {
10335                         if (connector->index == mst_state->mgr->conn_base_id) {
10336                                 aconnector = to_amdgpu_dm_connector(connector);
10337                                 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link);
10338                                 drm_dp_mst_update_slots(mst_state, link_coding_cap);
10339
10340                                 break;
10341                         }
10342                 }
10343                 drm_connector_list_iter_end(&iter);
10344         }
10345
10346         /**
10347          * Streams and planes are reset when there are changes that affect
10348          * bandwidth. Anything that affects bandwidth needs to go through
10349          * DC global validation to ensure that the configuration can be applied
10350          * to hardware.
10351          *
10352          * We have to currently stall out here in atomic_check for outstanding
10353          * commits to finish in this case because our IRQ handlers reference
10354          * DRM state directly - we can end up disabling interrupts too early
10355          * if we don't.
10356          *
10357          * TODO: Remove this stall and drop DM state private objects.
10358          */
10359         if (lock_and_validation_needed) {
10360                 ret = dm_atomic_get_state(state, &dm_state);
10361                 if (ret) {
10362                         DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n");
10363                         goto fail;
10364                 }
10365
10366                 ret = do_aquire_global_lock(dev, state);
10367                 if (ret) {
10368                         DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n");
10369                         goto fail;
10370                 }
10371
10372                 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars);
10373                 if (ret) {
10374                         DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n");
10375                         ret = -EINVAL;
10376                         goto fail;
10377                 }
10378
10379                 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars);
10380                 if (ret) {
10381                         DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n");
10382                         goto fail;
10383                 }
10384
10385                 /*
10386                  * Perform validation of MST topology in the state:
10387                  * We need to perform MST atomic check before calling
10388                  * dc_validate_global_state(), or there is a chance
10389                  * to get stuck in an infinite loop and hang eventually.
10390                  */
10391                 ret = drm_dp_mst_atomic_check(state);
10392                 if (ret) {
10393                         DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n");
10394                         goto fail;
10395                 }
10396                 status = dc_validate_global_state(dc, dm_state->context, true);
10397                 if (status != DC_OK) {
10398                         DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)",
10399                                        dc_status_to_str(status), status);
10400                         ret = -EINVAL;
10401                         goto fail;
10402                 }
10403         } else {
10404                 /*
10405                  * The commit is a fast update. Fast updates shouldn't change
10406                  * the DC context, affect global validation, and can have their
10407                  * commit work done in parallel with other commits not touching
10408                  * the same resource. If we have a new DC context as part of
10409                  * the DM atomic state from validation we need to free it and
10410                  * retain the existing one instead.
10411                  *
10412                  * Furthermore, since the DM atomic state only contains the DC
10413                  * context and can safely be annulled, we can free the state
10414                  * and clear the associated private object now to free
10415                  * some memory and avoid a possible use-after-free later.
10416                  */
10417
10418                 for (i = 0; i < state->num_private_objs; i++) {
10419                         struct drm_private_obj *obj = state->private_objs[i].ptr;
10420
10421                         if (obj->funcs == adev->dm.atomic_obj.funcs) {
10422                                 int j = state->num_private_objs-1;
10423
10424                                 dm_atomic_destroy_state(obj,
10425                                                 state->private_objs[i].state);
10426
10427                                 /* If i is not at the end of the array then the
10428                                  * last element needs to be moved to where i was
10429                                  * before the array can safely be truncated.
10430                                  */
10431                                 if (i != j)
10432                                         state->private_objs[i] =
10433                                                 state->private_objs[j];
10434
10435                                 state->private_objs[j].ptr = NULL;
10436                                 state->private_objs[j].state = NULL;
10437                                 state->private_objs[j].old_state = NULL;
10438                                 state->private_objs[j].new_state = NULL;
10439
10440                                 state->num_private_objs = j;
10441                                 break;
10442                         }
10443                 }
10444         }
10445
10446         /* Store the overall update type for use later in atomic check. */
10447         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10448                 struct dm_crtc_state *dm_new_crtc_state =
10449                         to_dm_crtc_state(new_crtc_state);
10450
10451                 /*
10452                  * Only allow async flips for fast updates that don't change
10453                  * the FB pitch, the DCC state, rotation, etc.
10454                  */
10455                 if (new_crtc_state->async_flip && lock_and_validation_needed) {
10456                         drm_dbg_atomic(crtc->dev,
10457                                        "[CRTC:%d:%s] async flips are only supported for fast updates\n",
10458                                        crtc->base.id, crtc->name);
10459                         ret = -EINVAL;
10460                         goto fail;
10461                 }
10462
10463                 dm_new_crtc_state->update_type = lock_and_validation_needed ?
10464                         UPDATE_TYPE_FULL : UPDATE_TYPE_FAST;
10465         }
10466
10467         /* Must be success */
10468         WARN_ON(ret);
10469
10470         trace_amdgpu_dm_atomic_check_finish(state, ret);
10471
10472         return ret;
10473
10474 fail:
10475         if (ret == -EDEADLK)
10476                 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
10477         else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
10478                 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
10479         else
10480                 DRM_DEBUG_DRIVER("Atomic check failed with err: %d\n", ret);
10481
10482         trace_amdgpu_dm_atomic_check_finish(state, ret);
10483
10484         return ret;
10485 }
10486
10487 static bool is_dp_capable_without_timing_msa(struct dc *dc,
10488                                              struct amdgpu_dm_connector *amdgpu_dm_connector)
10489 {
10490         u8 dpcd_data;
10491         bool capable = false;
10492
10493         if (amdgpu_dm_connector->dc_link &&
10494                 dm_helpers_dp_read_dpcd(
10495                                 NULL,
10496                                 amdgpu_dm_connector->dc_link,
10497                                 DP_DOWN_STREAM_PORT_COUNT,
10498                                 &dpcd_data,
10499                                 sizeof(dpcd_data))) {
10500                 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
10501         }
10502
10503         return capable;
10504 }
10505
10506 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,
10507                 unsigned int offset,
10508                 unsigned int total_length,
10509                 u8 *data,
10510                 unsigned int length,
10511                 struct amdgpu_hdmi_vsdb_info *vsdb)
10512 {
10513         bool res;
10514         union dmub_rb_cmd cmd;
10515         struct dmub_cmd_send_edid_cea *input;
10516         struct dmub_cmd_edid_cea_output *output;
10517
10518         if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES)
10519                 return false;
10520
10521         memset(&cmd, 0, sizeof(cmd));
10522
10523         input = &cmd.edid_cea.data.input;
10524
10525         cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA;
10526         cmd.edid_cea.header.sub_type = 0;
10527         cmd.edid_cea.header.payload_bytes =
10528                 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header);
10529         input->offset = offset;
10530         input->length = length;
10531         input->cea_total_length = total_length;
10532         memcpy(input->payload, data, length);
10533
10534         res = dm_execute_dmub_cmd(dm->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY);
10535         if (!res) {
10536                 DRM_ERROR("EDID CEA parser failed\n");
10537                 return false;
10538         }
10539
10540         output = &cmd.edid_cea.data.output;
10541
10542         if (output->type == DMUB_CMD__EDID_CEA_ACK) {
10543                 if (!output->ack.success) {
10544                         DRM_ERROR("EDID CEA ack failed at offset %d\n",
10545                                         output->ack.offset);
10546                 }
10547         } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) {
10548                 if (!output->amd_vsdb.vsdb_found)
10549                         return false;
10550
10551                 vsdb->freesync_supported = output->amd_vsdb.freesync_supported;
10552                 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version;
10553                 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate;
10554                 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate;
10555         } else {
10556                 DRM_WARN("Unknown EDID CEA parser results\n");
10557                 return false;
10558         }
10559
10560         return true;
10561 }
10562
10563 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm,
10564                 u8 *edid_ext, int len,
10565                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10566 {
10567         int i;
10568
10569         /* send extension block to DMCU for parsing */
10570         for (i = 0; i < len; i += 8) {
10571                 bool res;
10572                 int offset;
10573
10574                 /* send 8 bytes a time */
10575                 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8))
10576                         return false;
10577
10578                 if (i+8 == len) {
10579                         /* EDID block sent completed, expect result */
10580                         int version, min_rate, max_rate;
10581
10582                         res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate);
10583                         if (res) {
10584                                 /* amd vsdb found */
10585                                 vsdb_info->freesync_supported = 1;
10586                                 vsdb_info->amd_vsdb_version = version;
10587                                 vsdb_info->min_refresh_rate_hz = min_rate;
10588                                 vsdb_info->max_refresh_rate_hz = max_rate;
10589                                 return true;
10590                         }
10591                         /* not amd vsdb */
10592                         return false;
10593                 }
10594
10595                 /* check for ack*/
10596                 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset);
10597                 if (!res)
10598                         return false;
10599         }
10600
10601         return false;
10602 }
10603
10604 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm,
10605                 u8 *edid_ext, int len,
10606                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10607 {
10608         int i;
10609
10610         /* send extension block to DMCU for parsing */
10611         for (i = 0; i < len; i += 8) {
10612                 /* send 8 bytes a time */
10613                 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info))
10614                         return false;
10615         }
10616
10617         return vsdb_info->freesync_supported;
10618 }
10619
10620 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
10621                 u8 *edid_ext, int len,
10622                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10623 {
10624         struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
10625         bool ret;
10626
10627         mutex_lock(&adev->dm.dc_lock);
10628         if (adev->dm.dmub_srv)
10629                 ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info);
10630         else
10631                 ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info);
10632         mutex_unlock(&adev->dm.dc_lock);
10633         return ret;
10634 }
10635
10636 static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector,
10637                           struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
10638 {
10639         u8 *edid_ext = NULL;
10640         int i;
10641         int j = 0;
10642
10643         if (edid == NULL || edid->extensions == 0)
10644                 return -ENODEV;
10645
10646         /* Find DisplayID extension */
10647         for (i = 0; i < edid->extensions; i++) {
10648                 edid_ext = (void *)(edid + (i + 1));
10649                 if (edid_ext[0] == DISPLAYID_EXT)
10650                         break;
10651         }
10652
10653         while (j < EDID_LENGTH) {
10654                 struct amd_vsdb_block *amd_vsdb = (struct amd_vsdb_block *)&edid_ext[j];
10655                 unsigned int ieeeId = (amd_vsdb->ieee_id[2] << 16) | (amd_vsdb->ieee_id[1] << 8) | (amd_vsdb->ieee_id[0]);
10656
10657                 if (ieeeId == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID &&
10658                                 amd_vsdb->version == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3) {
10659                         vsdb_info->replay_mode = (amd_vsdb->feature_caps & AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE) ? true : false;
10660                         vsdb_info->amd_vsdb_version = HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3;
10661                         DRM_DEBUG_KMS("Panel supports Replay Mode: %d\n", vsdb_info->replay_mode);
10662
10663                         return true;
10664                 }
10665                 j++;
10666         }
10667
10668         return false;
10669 }
10670
10671 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
10672                 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
10673 {
10674         u8 *edid_ext = NULL;
10675         int i;
10676         bool valid_vsdb_found = false;
10677
10678         /*----- drm_find_cea_extension() -----*/
10679         /* No EDID or EDID extensions */
10680         if (edid == NULL || edid->extensions == 0)
10681                 return -ENODEV;
10682
10683         /* Find CEA extension */
10684         for (i = 0; i < edid->extensions; i++) {
10685                 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1);
10686                 if (edid_ext[0] == CEA_EXT)
10687                         break;
10688         }
10689
10690         if (i == edid->extensions)
10691                 return -ENODEV;
10692
10693         /*----- cea_db_offsets() -----*/
10694         if (edid_ext[0] != CEA_EXT)
10695                 return -ENODEV;
10696
10697         valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info);
10698
10699         return valid_vsdb_found ? i : -ENODEV;
10700 }
10701
10702 /**
10703  * amdgpu_dm_update_freesync_caps - Update Freesync capabilities
10704  *
10705  * @connector: Connector to query.
10706  * @edid: EDID from monitor
10707  *
10708  * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep
10709  * track of some of the display information in the internal data struct used by
10710  * amdgpu_dm. This function checks which type of connector we need to set the
10711  * FreeSync parameters.
10712  */
10713 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
10714                                     struct edid *edid)
10715 {
10716         int i = 0;
10717         struct detailed_timing *timing;
10718         struct detailed_non_pixel *data;
10719         struct detailed_data_monitor_range *range;
10720         struct amdgpu_dm_connector *amdgpu_dm_connector =
10721                         to_amdgpu_dm_connector(connector);
10722         struct dm_connector_state *dm_con_state = NULL;
10723         struct dc_sink *sink;
10724
10725         struct drm_device *dev = connector->dev;
10726         struct amdgpu_device *adev = drm_to_adev(dev);
10727         struct amdgpu_hdmi_vsdb_info vsdb_info = {0};
10728         bool freesync_capable = false;
10729         enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE;
10730
10731         if (!connector->state) {
10732                 DRM_ERROR("%s - Connector has no state", __func__);
10733                 goto update;
10734         }
10735
10736         sink = amdgpu_dm_connector->dc_sink ?
10737                 amdgpu_dm_connector->dc_sink :
10738                 amdgpu_dm_connector->dc_em_sink;
10739
10740         if (!edid || !sink) {
10741                 dm_con_state = to_dm_connector_state(connector->state);
10742
10743                 amdgpu_dm_connector->min_vfreq = 0;
10744                 amdgpu_dm_connector->max_vfreq = 0;
10745                 amdgpu_dm_connector->pixel_clock_mhz = 0;
10746                 connector->display_info.monitor_range.min_vfreq = 0;
10747                 connector->display_info.monitor_range.max_vfreq = 0;
10748                 freesync_capable = false;
10749
10750                 goto update;
10751         }
10752
10753         dm_con_state = to_dm_connector_state(connector->state);
10754
10755         if (!adev->dm.freesync_module)
10756                 goto update;
10757
10758         if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
10759                 || sink->sink_signal == SIGNAL_TYPE_EDP) {
10760                 bool edid_check_required = false;
10761
10762                 if (edid) {
10763                         edid_check_required = is_dp_capable_without_timing_msa(
10764                                                 adev->dm.dc,
10765                                                 amdgpu_dm_connector);
10766                 }
10767
10768                 if (edid_check_required == true && (edid->version > 1 ||
10769                    (edid->version == 1 && edid->revision > 1))) {
10770                         for (i = 0; i < 4; i++) {
10771
10772                                 timing  = &edid->detailed_timings[i];
10773                                 data    = &timing->data.other_data;
10774                                 range   = &data->data.range;
10775                                 /*
10776                                  * Check if monitor has continuous frequency mode
10777                                  */
10778                                 if (data->type != EDID_DETAIL_MONITOR_RANGE)
10779                                         continue;
10780                                 /*
10781                                  * Check for flag range limits only. If flag == 1 then
10782                                  * no additional timing information provided.
10783                                  * Default GTF, GTF Secondary curve and CVT are not
10784                                  * supported
10785                                  */
10786                                 if (range->flags != 1)
10787                                         continue;
10788
10789                                 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
10790                                 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
10791                                 amdgpu_dm_connector->pixel_clock_mhz =
10792                                         range->pixel_clock_mhz * 10;
10793
10794                                 connector->display_info.monitor_range.min_vfreq = range->min_vfreq;
10795                                 connector->display_info.monitor_range.max_vfreq = range->max_vfreq;
10796
10797                                 break;
10798                         }
10799
10800                         if (amdgpu_dm_connector->max_vfreq -
10801                             amdgpu_dm_connector->min_vfreq > 10) {
10802
10803                                 freesync_capable = true;
10804                         }
10805                 }
10806                 parse_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10807
10808                 if (vsdb_info.replay_mode) {
10809                         amdgpu_dm_connector->vsdb_info.replay_mode = vsdb_info.replay_mode;
10810                         amdgpu_dm_connector->vsdb_info.amd_vsdb_version = vsdb_info.amd_vsdb_version;
10811                         amdgpu_dm_connector->as_type = ADAPTIVE_SYNC_TYPE_EDP;
10812                 }
10813
10814         } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
10815                 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10816                 if (i >= 0 && vsdb_info.freesync_supported) {
10817                         timing  = &edid->detailed_timings[i];
10818                         data    = &timing->data.other_data;
10819
10820                         amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10821                         amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10822                         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10823                                 freesync_capable = true;
10824
10825                         connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10826                         connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10827                 }
10828         }
10829
10830         as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link);
10831
10832         if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {
10833                 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10834                 if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) {
10835
10836                         amdgpu_dm_connector->pack_sdp_v1_3 = true;
10837                         amdgpu_dm_connector->as_type = as_type;
10838                         amdgpu_dm_connector->vsdb_info = vsdb_info;
10839
10840                         amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10841                         amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10842                         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10843                                 freesync_capable = true;
10844
10845                         connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10846                         connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10847                 }
10848         }
10849
10850 update:
10851         if (dm_con_state)
10852                 dm_con_state->freesync_capable = freesync_capable;
10853
10854         if (connector->vrr_capable_property)
10855                 drm_connector_set_vrr_capable_property(connector,
10856                                                        freesync_capable);
10857 }
10858
10859 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
10860 {
10861         struct amdgpu_device *adev = drm_to_adev(dev);
10862         struct dc *dc = adev->dm.dc;
10863         int i;
10864
10865         mutex_lock(&adev->dm.dc_lock);
10866         if (dc->current_state) {
10867                 for (i = 0; i < dc->current_state->stream_count; ++i)
10868                         dc->current_state->streams[i]
10869                                 ->triggered_crtc_reset.enabled =
10870                                 adev->dm.force_timing_sync;
10871
10872                 dm_enable_per_frame_crtc_master_sync(dc->current_state);
10873                 dc_trigger_sync(dc, dc->current_state);
10874         }
10875         mutex_unlock(&adev->dm.dc_lock);
10876 }
10877
10878 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
10879                        u32 value, const char *func_name)
10880 {
10881 #ifdef DM_CHECK_ADDR_0
10882         if (address == 0) {
10883                 DC_ERR("invalid register write. address = 0");
10884                 return;
10885         }
10886 #endif
10887         cgs_write_register(ctx->cgs_device, address, value);
10888         trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
10889 }
10890
10891 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
10892                           const char *func_name)
10893 {
10894         u32 value;
10895 #ifdef DM_CHECK_ADDR_0
10896         if (address == 0) {
10897                 DC_ERR("invalid register read; address = 0\n");
10898                 return 0;
10899         }
10900 #endif
10901
10902         if (ctx->dmub_srv &&
10903             ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
10904             !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
10905                 ASSERT(false);
10906                 return 0;
10907         }
10908
10909         value = cgs_read_register(ctx->cgs_device, address);
10910
10911         trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
10912
10913         return value;
10914 }
10915
10916 int amdgpu_dm_process_dmub_aux_transfer_sync(
10917                 struct dc_context *ctx,
10918                 unsigned int link_index,
10919                 struct aux_payload *payload,
10920                 enum aux_return_code_type *operation_result)
10921 {
10922         struct amdgpu_device *adev = ctx->driver_context;
10923         struct dmub_notification *p_notify = adev->dm.dmub_notify;
10924         int ret = -1;
10925
10926         mutex_lock(&adev->dm.dpia_aux_lock);
10927         if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) {
10928                 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE;
10929                 goto out;
10930         }
10931
10932         if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10933                 DRM_ERROR("wait_for_completion_timeout timeout!");
10934                 *operation_result = AUX_RET_ERROR_TIMEOUT;
10935                 goto out;
10936         }
10937
10938         if (p_notify->result != AUX_RET_SUCCESS) {
10939                 /*
10940                  * Transient states before tunneling is enabled could
10941                  * lead to this error. We can ignore this for now.
10942                  */
10943                 if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) {
10944                         DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n",
10945                                         payload->address, payload->length,
10946                                         p_notify->result);
10947                 }
10948                 *operation_result = AUX_RET_ERROR_INVALID_REPLY;
10949                 goto out;
10950         }
10951
10952
10953         payload->reply[0] = adev->dm.dmub_notify->aux_reply.command;
10954         if (!payload->write && p_notify->aux_reply.length &&
10955                         (payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) {
10956
10957                 if (payload->length != p_notify->aux_reply.length) {
10958                         DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n",
10959                                 p_notify->aux_reply.length,
10960                                         payload->address, payload->length);
10961                         *operation_result = AUX_RET_ERROR_INVALID_REPLY;
10962                         goto out;
10963                 }
10964
10965                 memcpy(payload->data, p_notify->aux_reply.data,
10966                                 p_notify->aux_reply.length);
10967         }
10968
10969         /* success */
10970         ret = p_notify->aux_reply.length;
10971         *operation_result = p_notify->result;
10972 out:
10973         reinit_completion(&adev->dm.dmub_aux_transfer_done);
10974         mutex_unlock(&adev->dm.dpia_aux_lock);
10975         return ret;
10976 }
10977
10978 int amdgpu_dm_process_dmub_set_config_sync(
10979                 struct dc_context *ctx,
10980                 unsigned int link_index,
10981                 struct set_config_cmd_payload *payload,
10982                 enum set_config_status *operation_result)
10983 {
10984         struct amdgpu_device *adev = ctx->driver_context;
10985         bool is_cmd_complete;
10986         int ret;
10987
10988         mutex_lock(&adev->dm.dpia_aux_lock);
10989         is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc,
10990                         link_index, payload, adev->dm.dmub_notify);
10991
10992         if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10993                 ret = 0;
10994                 *operation_result = adev->dm.dmub_notify->sc_status;
10995         } else {
10996                 DRM_ERROR("wait_for_completion_timeout timeout!");
10997                 ret = -1;
10998                 *operation_result = SET_CONFIG_UNKNOWN_ERROR;
10999         }
11000
11001         if (!is_cmd_complete)
11002                 reinit_completion(&adev->dm.dmub_aux_transfer_done);
11003         mutex_unlock(&adev->dm.dpia_aux_lock);
11004         return ret;
11005 }
11006
11007 /*
11008  * Check whether seamless boot is supported.
11009  *
11010  * So far we only support seamless boot on CHIP_VANGOGH.
11011  * If everything goes well, we may consider expanding
11012  * seamless boot to other ASICs.
11013  */
11014 bool check_seamless_boot_capability(struct amdgpu_device *adev)
11015 {
11016         switch (adev->ip_versions[DCE_HWIP][0]) {
11017         case IP_VERSION(3, 0, 1):
11018                 if (!adev->mman.keep_stolen_vga_memory)
11019                         return true;
11020                 break;
11021         default:
11022                 break;
11023         }
11024
11025         return false;
11026 }
11027
11028 bool dm_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
11029 {
11030         return dc_dmub_srv_cmd_run(ctx->dmub_srv, cmd, wait_type);
11031 }
11032
11033 bool dm_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
11034 {
11035         return dc_dmub_srv_cmd_run_list(ctx->dmub_srv, count, cmd, wait_type);
11036 }