2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 /* The caprices of the preprocessor require that this be declared right here */
27 #define CREATE_TRACE_POINTS
29 #include "dm_services_types.h"
31 #include "link_enc_cfg.h"
32 #include "dc/inc/core_types.h"
33 #include "dal_asic_id.h"
34 #include "dmub/dmub_srv.h"
35 #include "dc/inc/hw/dmcu.h"
36 #include "dc/inc/hw/abm.h"
37 #include "dc/dc_dmub_srv.h"
38 #include "dc/dc_edid_parser.h"
39 #include "dc/dc_stat.h"
40 #include "amdgpu_dm_trace.h"
41 #include "dpcd_defs.h"
42 #include "link/protocols/link_dpcd.h"
43 #include "link_service_types.h"
44 #include "link/protocols/link_dp_capability.h"
45 #include "link/protocols/link_ddc.h"
49 #include "amdgpu_display.h"
50 #include "amdgpu_ucode.h"
52 #include "amdgpu_dm.h"
53 #include "amdgpu_dm_plane.h"
54 #include "amdgpu_dm_crtc.h"
55 #include "amdgpu_dm_hdcp.h"
56 #include <drm/display/drm_hdcp_helper.h>
57 #include "amdgpu_pm.h"
58 #include "amdgpu_atombios.h"
60 #include "amd_shared.h"
61 #include "amdgpu_dm_irq.h"
62 #include "dm_helpers.h"
63 #include "amdgpu_dm_mst_types.h"
64 #if defined(CONFIG_DEBUG_FS)
65 #include "amdgpu_dm_debugfs.h"
67 #include "amdgpu_dm_psr.h"
68 #include "amdgpu_dm_replay.h"
70 #include "ivsrcid/ivsrcid_vislands30.h"
72 #include <linux/backlight.h>
73 #include <linux/module.h>
74 #include <linux/moduleparam.h>
75 #include <linux/types.h>
76 #include <linux/pm_runtime.h>
77 #include <linux/pci.h>
78 #include <linux/firmware.h>
79 #include <linux/component.h>
80 #include <linux/dmi.h>
82 #include <drm/display/drm_dp_mst_helper.h>
83 #include <drm/display/drm_hdmi_helper.h>
84 #include <drm/drm_atomic.h>
85 #include <drm/drm_atomic_uapi.h>
86 #include <drm/drm_atomic_helper.h>
87 #include <drm/drm_blend.h>
88 #include <drm/drm_fourcc.h>
89 #include <drm/drm_edid.h>
90 #include <drm/drm_vblank.h>
91 #include <drm/drm_audio_component.h>
92 #include <drm/drm_gem_atomic_helper.h>
93 #include <drm/drm_plane_helper.h>
95 #include <acpi/video.h>
97 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
99 #include "dcn/dcn_1_0_offset.h"
100 #include "dcn/dcn_1_0_sh_mask.h"
101 #include "soc15_hw_ip.h"
102 #include "soc15_common.h"
103 #include "vega10_ip_offset.h"
105 #include "gc/gc_11_0_0_offset.h"
106 #include "gc/gc_11_0_0_sh_mask.h"
108 #include "modules/inc/mod_freesync.h"
109 #include "modules/power/power_helpers.h"
111 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
112 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
113 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"
114 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
115 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
116 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
117 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
118 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
119 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
120 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
121 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"
122 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
123 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin"
124 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);
125 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin"
126 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);
127 #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin"
128 MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB);
129 #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin"
130 MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB);
131 #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin"
132 MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB);
134 #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin"
135 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB);
136 #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin"
137 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB);
139 #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin"
140 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
142 #define FIRMWARE_NAVI12_DMCU "amdgpu/navi12_dmcu.bin"
143 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);
145 /* Number of bytes in PSP header for firmware. */
146 #define PSP_HEADER_BYTES 0x100
148 /* Number of bytes in PSP footer for firmware. */
149 #define PSP_FOOTER_BYTES 0x100
154 * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
155 * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM
156 * requests into DC requests, and DC responses into DRM responses.
158 * The root control structure is &struct amdgpu_display_manager.
161 /* basic init/fini API */
162 static int amdgpu_dm_init(struct amdgpu_device *adev);
163 static void amdgpu_dm_fini(struct amdgpu_device *adev);
164 static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector);
166 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)
168 switch (link->dpcd_caps.dongle_type) {
169 case DISPLAY_DONGLE_NONE:
170 return DRM_MODE_SUBCONNECTOR_Native;
171 case DISPLAY_DONGLE_DP_VGA_CONVERTER:
172 return DRM_MODE_SUBCONNECTOR_VGA;
173 case DISPLAY_DONGLE_DP_DVI_CONVERTER:
174 case DISPLAY_DONGLE_DP_DVI_DONGLE:
175 return DRM_MODE_SUBCONNECTOR_DVID;
176 case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
177 case DISPLAY_DONGLE_DP_HDMI_DONGLE:
178 return DRM_MODE_SUBCONNECTOR_HDMIA;
179 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
181 return DRM_MODE_SUBCONNECTOR_Unknown;
185 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector)
187 struct dc_link *link = aconnector->dc_link;
188 struct drm_connector *connector = &aconnector->base;
189 enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
191 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
194 if (aconnector->dc_sink)
195 subconnector = get_subconnector_type(link);
197 drm_object_property_set_value(&connector->base,
198 connector->dev->mode_config.dp_subconnector_property,
203 * initializes drm_device display related structures, based on the information
204 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
205 * drm_encoder, drm_mode_config
207 * Returns 0 on success
209 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
210 /* removes and deallocates the drm structures, created by the above function */
211 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
213 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
214 struct amdgpu_dm_connector *amdgpu_dm_connector,
216 struct amdgpu_encoder *amdgpu_encoder);
217 static int amdgpu_dm_encoder_init(struct drm_device *dev,
218 struct amdgpu_encoder *aencoder,
219 uint32_t link_index);
221 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
223 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
225 static int amdgpu_dm_atomic_check(struct drm_device *dev,
226 struct drm_atomic_state *state);
228 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector);
229 static void handle_hpd_rx_irq(void *param);
232 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
233 struct drm_crtc_state *new_crtc_state);
235 * dm_vblank_get_counter
238 * Get counter for number of vertical blanks
241 * struct amdgpu_device *adev - [in] desired amdgpu device
242 * int disp_idx - [in] which CRTC to get the counter from
245 * Counter for vertical blanks
247 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
249 struct amdgpu_crtc *acrtc = NULL;
251 if (crtc >= adev->mode_info.num_crtc)
254 acrtc = adev->mode_info.crtcs[crtc];
256 if (!acrtc->dm_irq_params.stream) {
257 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
262 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);
265 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
266 u32 *vbl, u32 *position)
268 u32 v_blank_start, v_blank_end, h_position, v_position;
269 struct amdgpu_crtc *acrtc = NULL;
271 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
274 acrtc = adev->mode_info.crtcs[crtc];
276 if (!acrtc->dm_irq_params.stream) {
277 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
283 * TODO rework base driver to use values directly.
284 * for now parse it back into reg-format
286 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream,
292 *position = v_position | (h_position << 16);
293 *vbl = v_blank_start | (v_blank_end << 16);
298 static bool dm_is_idle(void *handle)
304 static int dm_wait_for_idle(void *handle)
310 static bool dm_check_soft_reset(void *handle)
315 static int dm_soft_reset(void *handle)
321 static struct amdgpu_crtc *
322 get_crtc_by_otg_inst(struct amdgpu_device *adev,
325 struct drm_device *dev = adev_to_drm(adev);
326 struct drm_crtc *crtc;
327 struct amdgpu_crtc *amdgpu_crtc;
329 if (WARN_ON(otg_inst == -1))
330 return adev->mode_info.crtcs[0];
332 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
333 amdgpu_crtc = to_amdgpu_crtc(crtc);
335 if (amdgpu_crtc->otg_inst == otg_inst)
342 static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,
343 struct dm_crtc_state *new_state)
345 if (new_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)
347 else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state))
353 static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update,
358 for (i = 0, j = planes_count - 1; i < j; i++, j--)
359 swap(array_of_surface_update[i], array_of_surface_update[j]);
363 * update_planes_and_stream_adapter() - Send planes to be updated in DC
365 * DC has a generic way to update planes and stream via
366 * dc_update_planes_and_stream function; however, DM might need some
367 * adjustments and preparation before calling it. This function is a wrapper
368 * for the dc_update_planes_and_stream that does any required configuration
369 * before passing control to DC.
371 * @dc: Display Core control structure
372 * @update_type: specify whether it is FULL/MEDIUM/FAST update
373 * @planes_count: planes count to update
374 * @stream: stream state
375 * @stream_update: stream update
376 * @array_of_surface_update: dc surface update pointer
379 static inline bool update_planes_and_stream_adapter(struct dc *dc,
382 struct dc_stream_state *stream,
383 struct dc_stream_update *stream_update,
384 struct dc_surface_update *array_of_surface_update)
386 reverse_planes_order(array_of_surface_update, planes_count);
389 * Previous frame finished and HW is ready for optimization.
391 if (update_type == UPDATE_TYPE_FAST)
392 dc_post_update_surfaces_to_stream(dc);
394 return dc_update_planes_and_stream(dc,
395 array_of_surface_update,
402 * dm_pflip_high_irq() - Handle pageflip interrupt
403 * @interrupt_params: ignored
405 * Handles the pageflip interrupt by notifying all interested parties
406 * that the pageflip has been completed.
408 static void dm_pflip_high_irq(void *interrupt_params)
410 struct amdgpu_crtc *amdgpu_crtc;
411 struct common_irq_params *irq_params = interrupt_params;
412 struct amdgpu_device *adev = irq_params->adev;
414 struct drm_pending_vblank_event *e;
415 u32 vpos, hpos, v_blank_start, v_blank_end;
418 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
420 /* IRQ could occur when in initial stage */
421 /* TODO work and BO cleanup */
422 if (amdgpu_crtc == NULL) {
423 DC_LOG_PFLIP("CRTC is null, returning.\n");
427 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
429 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
430 DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p]\n",
431 amdgpu_crtc->pflip_status,
432 AMDGPU_FLIP_SUBMITTED,
433 amdgpu_crtc->crtc_id,
435 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
439 /* page flip completed. */
440 e = amdgpu_crtc->event;
441 amdgpu_crtc->event = NULL;
445 vrr_active = amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc);
447 /* Fixed refresh rate, or VRR scanout position outside front-porch? */
449 !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start,
450 &v_blank_end, &hpos, &vpos) ||
451 (vpos < v_blank_start)) {
452 /* Update to correct count and vblank timestamp if racing with
453 * vblank irq. This also updates to the correct vblank timestamp
454 * even in VRR mode, as scanout is past the front-porch atm.
456 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
458 /* Wake up userspace by sending the pageflip event with proper
459 * count and timestamp of vblank of flip completion.
462 drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
464 /* Event sent, so done with vblank for this flip */
465 drm_crtc_vblank_put(&amdgpu_crtc->base);
468 /* VRR active and inside front-porch: vblank count and
469 * timestamp for pageflip event will only be up to date after
470 * drm_crtc_handle_vblank() has been executed from late vblank
471 * irq handler after start of back-porch (vline 0). We queue the
472 * pageflip event for send-out by drm_crtc_handle_vblank() with
473 * updated timestamp and count, once it runs after us.
475 * We need to open-code this instead of using the helper
476 * drm_crtc_arm_vblank_event(), as that helper would
477 * call drm_crtc_accurate_vblank_count(), which we must
478 * not call in VRR mode while we are in front-porch!
481 /* sequence will be replaced by real count during send-out. */
482 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
483 e->pipe = amdgpu_crtc->crtc_id;
485 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list);
489 /* Keep track of vblank of this flip for flip throttling. We use the
490 * cooked hw counter, as that one incremented at start of this vblank
491 * of pageflip completion, so last_flip_vblank is the forbidden count
492 * for queueing new pageflips if vsync + VRR is enabled.
494 amdgpu_crtc->dm_irq_params.last_flip_vblank =
495 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base);
497 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
498 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
500 DC_LOG_PFLIP("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
501 amdgpu_crtc->crtc_id, amdgpu_crtc,
502 vrr_active, (int) !e);
505 static void dm_vupdate_high_irq(void *interrupt_params)
507 struct common_irq_params *irq_params = interrupt_params;
508 struct amdgpu_device *adev = irq_params->adev;
509 struct amdgpu_crtc *acrtc;
510 struct drm_device *drm_dev;
511 struct drm_vblank_crtc *vblank;
512 ktime_t frame_duration_ns, previous_timestamp;
516 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
519 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
520 drm_dev = acrtc->base.dev;
521 vblank = &drm_dev->vblank[acrtc->base.index];
522 previous_timestamp = atomic64_read(&irq_params->previous_timestamp);
523 frame_duration_ns = vblank->time - previous_timestamp;
525 if (frame_duration_ns > 0) {
526 trace_amdgpu_refresh_rate_track(acrtc->base.index,
528 ktime_divns(NSEC_PER_SEC, frame_duration_ns));
529 atomic64_set(&irq_params->previous_timestamp, vblank->time);
532 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d\n",
536 /* Core vblank handling is done here after end of front-porch in
537 * vrr mode, as vblank timestamping will give valid results
538 * while now done after front-porch. This will also deliver
539 * page-flip completion events that have been queued to us
540 * if a pageflip happened inside front-porch.
543 amdgpu_dm_crtc_handle_vblank(acrtc);
545 /* BTR processing for pre-DCE12 ASICs */
546 if (acrtc->dm_irq_params.stream &&
547 adev->family < AMDGPU_FAMILY_AI) {
548 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
549 mod_freesync_handle_v_update(
550 adev->dm.freesync_module,
551 acrtc->dm_irq_params.stream,
552 &acrtc->dm_irq_params.vrr_params);
554 dc_stream_adjust_vmin_vmax(
556 acrtc->dm_irq_params.stream,
557 &acrtc->dm_irq_params.vrr_params.adjust);
558 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
565 * dm_crtc_high_irq() - Handles CRTC interrupt
566 * @interrupt_params: used for determining the CRTC instance
568 * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
571 static void dm_crtc_high_irq(void *interrupt_params)
573 struct common_irq_params *irq_params = interrupt_params;
574 struct amdgpu_device *adev = irq_params->adev;
575 struct amdgpu_crtc *acrtc;
579 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
583 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
585 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,
586 vrr_active, acrtc->dm_irq_params.active_planes);
589 * Core vblank handling at start of front-porch is only possible
590 * in non-vrr mode, as only there vblank timestamping will give
591 * valid results while done in front-porch. Otherwise defer it
592 * to dm_vupdate_high_irq after end of front-porch.
595 amdgpu_dm_crtc_handle_vblank(acrtc);
598 * Following stuff must happen at start of vblank, for crc
599 * computation and below-the-range btr support in vrr mode.
601 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
603 /* BTR updates need to happen before VUPDATE on Vega and above. */
604 if (adev->family < AMDGPU_FAMILY_AI)
607 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
609 if (acrtc->dm_irq_params.stream &&
610 acrtc->dm_irq_params.vrr_params.supported &&
611 acrtc->dm_irq_params.freesync_config.state ==
612 VRR_STATE_ACTIVE_VARIABLE) {
613 mod_freesync_handle_v_update(adev->dm.freesync_module,
614 acrtc->dm_irq_params.stream,
615 &acrtc->dm_irq_params.vrr_params);
617 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,
618 &acrtc->dm_irq_params.vrr_params.adjust);
622 * If there aren't any active_planes then DCH HUBP may be clock-gated.
623 * In that case, pageflip completion interrupts won't fire and pageflip
624 * completion events won't get delivered. Prevent this by sending
625 * pending pageflip events from here if a flip is still pending.
627 * If any planes are enabled, use dm_pflip_high_irq() instead, to
628 * avoid race conditions between flip programming and completion,
629 * which could cause too early flip completion events.
631 if (adev->family >= AMDGPU_FAMILY_RV &&
632 acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
633 acrtc->dm_irq_params.active_planes == 0) {
635 drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
637 drm_crtc_vblank_put(&acrtc->base);
639 acrtc->pflip_status = AMDGPU_FLIP_NONE;
642 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
645 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
647 * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for
648 * DCN generation ASICs
649 * @interrupt_params: interrupt parameters
651 * Used to set crc window/read out crc value at vertical line 0 position
653 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)
655 struct common_irq_params *irq_params = interrupt_params;
656 struct amdgpu_device *adev = irq_params->adev;
657 struct amdgpu_crtc *acrtc;
659 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0);
664 amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base);
666 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */
669 * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command.
670 * @adev: amdgpu_device pointer
671 * @notify: dmub notification structure
673 * Dmub AUX or SET_CONFIG command completion processing callback
674 * Copies dmub notification to DM which is to be read by AUX command.
675 * issuing thread and also signals the event to wake up the thread.
677 static void dmub_aux_setconfig_callback(struct amdgpu_device *adev,
678 struct dmub_notification *notify)
680 if (adev->dm.dmub_notify)
681 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification));
682 if (notify->type == DMUB_NOTIFICATION_AUX_REPLY)
683 complete(&adev->dm.dmub_aux_transfer_done);
687 * dmub_hpd_callback - DMUB HPD interrupt processing callback.
688 * @adev: amdgpu_device pointer
689 * @notify: dmub notification structure
691 * Dmub Hpd interrupt processing callback. Gets displayindex through the
692 * ink index and calls helper to do the processing.
694 static void dmub_hpd_callback(struct amdgpu_device *adev,
695 struct dmub_notification *notify)
697 struct amdgpu_dm_connector *aconnector;
698 struct amdgpu_dm_connector *hpd_aconnector = NULL;
699 struct drm_connector *connector;
700 struct drm_connector_list_iter iter;
701 struct dc_link *link;
703 struct drm_device *dev;
708 if (notify == NULL) {
709 DRM_ERROR("DMUB HPD callback notification was NULL");
713 if (notify->link_index > adev->dm.dc->link_count) {
714 DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index);
718 link_index = notify->link_index;
719 link = adev->dm.dc->links[link_index];
722 drm_connector_list_iter_begin(dev, &iter);
723 drm_for_each_connector_iter(connector, &iter) {
724 aconnector = to_amdgpu_dm_connector(connector);
725 if (link && aconnector->dc_link == link) {
726 if (notify->type == DMUB_NOTIFICATION_HPD)
727 DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index);
728 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
729 DRM_INFO("DMUB HPD IRQ callback: link_index=%u\n", link_index);
731 DRM_WARN("DMUB Unknown HPD callback type %d, link_index=%u\n",
732 notify->type, link_index);
734 hpd_aconnector = aconnector;
738 drm_connector_list_iter_end(&iter);
740 if (hpd_aconnector) {
741 if (notify->type == DMUB_NOTIFICATION_HPD)
742 handle_hpd_irq_helper(hpd_aconnector);
743 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
744 handle_hpd_rx_irq(hpd_aconnector);
749 * register_dmub_notify_callback - Sets callback for DMUB notify
750 * @adev: amdgpu_device pointer
751 * @type: Type of dmub notification
752 * @callback: Dmub interrupt callback function
753 * @dmub_int_thread_offload: offload indicator
755 * API to register a dmub callback handler for a dmub notification
756 * Also sets indicator whether callback processing to be offloaded.
757 * to dmub interrupt handling thread
758 * Return: true if successfully registered, false if there is existing registration
760 static bool register_dmub_notify_callback(struct amdgpu_device *adev,
761 enum dmub_notification_type type,
762 dmub_notify_interrupt_callback_t callback,
763 bool dmub_int_thread_offload)
765 if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) {
766 adev->dm.dmub_callback[type] = callback;
767 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload;
774 static void dm_handle_hpd_work(struct work_struct *work)
776 struct dmub_hpd_work *dmub_hpd_wrk;
778 dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work);
780 if (!dmub_hpd_wrk->dmub_notify) {
781 DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL");
785 if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) {
786 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev,
787 dmub_hpd_wrk->dmub_notify);
790 kfree(dmub_hpd_wrk->dmub_notify);
795 #define DMUB_TRACE_MAX_READ 64
797 * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt
798 * @interrupt_params: used for determining the Outbox instance
800 * Handles the Outbox Interrupt
803 static void dm_dmub_outbox1_low_irq(void *interrupt_params)
805 struct dmub_notification notify;
806 struct common_irq_params *irq_params = interrupt_params;
807 struct amdgpu_device *adev = irq_params->adev;
808 struct amdgpu_display_manager *dm = &adev->dm;
809 struct dmcub_trace_buf_entry entry = { 0 };
811 struct dmub_hpd_work *dmub_hpd_wrk;
812 struct dc_link *plink = NULL;
814 if (dc_enable_dmub_notifications(adev->dm.dc) &&
815 irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) {
818 dc_stat_get_dmub_notification(adev->dm.dc, ¬ify);
819 if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) {
820 DRM_ERROR("DM: notify type %d invalid!", notify.type);
823 if (!dm->dmub_callback[notify.type]) {
824 DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type);
827 if (dm->dmub_thread_offload[notify.type] == true) {
828 dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC);
830 DRM_ERROR("Failed to allocate dmub_hpd_wrk");
833 dmub_hpd_wrk->dmub_notify = kmemdup(¬ify, sizeof(struct dmub_notification),
835 if (!dmub_hpd_wrk->dmub_notify) {
837 DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify");
840 INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work);
841 dmub_hpd_wrk->adev = adev;
842 if (notify.type == DMUB_NOTIFICATION_HPD) {
843 plink = adev->dm.dc->links[notify.link_index];
846 notify.hpd_status == DP_HPD_PLUG;
849 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work);
851 dm->dmub_callback[notify.type](adev, ¬ify);
853 } while (notify.pending_notification);
858 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {
859 trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,
860 entry.param0, entry.param1);
862 DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",
863 entry.trace_code, entry.tick_count, entry.param0, entry.param1);
869 } while (count <= DMUB_TRACE_MAX_READ);
871 if (count > DMUB_TRACE_MAX_READ)
872 DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ");
875 static int dm_set_clockgating_state(void *handle,
876 enum amd_clockgating_state state)
881 static int dm_set_powergating_state(void *handle,
882 enum amd_powergating_state state)
887 /* Prototypes of private functions */
888 static int dm_early_init(void *handle);
890 /* Allocate memory for FBC compressed data */
891 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
893 struct drm_device *dev = connector->dev;
894 struct amdgpu_device *adev = drm_to_adev(dev);
895 struct dm_compressor_info *compressor = &adev->dm.compressor;
896 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
897 struct drm_display_mode *mode;
898 unsigned long max_size = 0;
900 if (adev->dm.dc->fbc_compressor == NULL)
903 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
906 if (compressor->bo_ptr)
910 list_for_each_entry(mode, &connector->modes, head) {
911 if (max_size < mode->htotal * mode->vtotal)
912 max_size = mode->htotal * mode->vtotal;
916 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
917 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
918 &compressor->gpu_addr, &compressor->cpu_addr);
921 DRM_ERROR("DM: Failed to initialize FBC\n");
923 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
924 DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
931 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
932 int pipe, bool *enabled,
933 unsigned char *buf, int max_bytes)
935 struct drm_device *dev = dev_get_drvdata(kdev);
936 struct amdgpu_device *adev = drm_to_adev(dev);
937 struct drm_connector *connector;
938 struct drm_connector_list_iter conn_iter;
939 struct amdgpu_dm_connector *aconnector;
944 mutex_lock(&adev->dm.audio_lock);
946 drm_connector_list_iter_begin(dev, &conn_iter);
947 drm_for_each_connector_iter(connector, &conn_iter) {
948 aconnector = to_amdgpu_dm_connector(connector);
949 if (aconnector->audio_inst != port)
953 ret = drm_eld_size(connector->eld);
954 memcpy(buf, connector->eld, min(max_bytes, ret));
958 drm_connector_list_iter_end(&conn_iter);
960 mutex_unlock(&adev->dm.audio_lock);
962 DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
967 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
968 .get_eld = amdgpu_dm_audio_component_get_eld,
971 static int amdgpu_dm_audio_component_bind(struct device *kdev,
972 struct device *hda_kdev, void *data)
974 struct drm_device *dev = dev_get_drvdata(kdev);
975 struct amdgpu_device *adev = drm_to_adev(dev);
976 struct drm_audio_component *acomp = data;
978 acomp->ops = &amdgpu_dm_audio_component_ops;
980 adev->dm.audio_component = acomp;
985 static void amdgpu_dm_audio_component_unbind(struct device *kdev,
986 struct device *hda_kdev, void *data)
988 struct drm_device *dev = dev_get_drvdata(kdev);
989 struct amdgpu_device *adev = drm_to_adev(dev);
990 struct drm_audio_component *acomp = data;
994 adev->dm.audio_component = NULL;
997 static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
998 .bind = amdgpu_dm_audio_component_bind,
999 .unbind = amdgpu_dm_audio_component_unbind,
1002 static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
1009 adev->mode_info.audio.enabled = true;
1011 adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
1013 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1014 adev->mode_info.audio.pin[i].channels = -1;
1015 adev->mode_info.audio.pin[i].rate = -1;
1016 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1017 adev->mode_info.audio.pin[i].status_bits = 0;
1018 adev->mode_info.audio.pin[i].category_code = 0;
1019 adev->mode_info.audio.pin[i].connected = false;
1020 adev->mode_info.audio.pin[i].id =
1021 adev->dm.dc->res_pool->audios[i]->inst;
1022 adev->mode_info.audio.pin[i].offset = 0;
1025 ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1029 adev->dm.audio_registered = true;
1034 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
1039 if (!adev->mode_info.audio.enabled)
1042 if (adev->dm.audio_registered) {
1043 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1044 adev->dm.audio_registered = false;
1047 /* TODO: Disable audio? */
1049 adev->mode_info.audio.enabled = false;
1052 static void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
1054 struct drm_audio_component *acomp = adev->dm.audio_component;
1056 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
1057 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
1059 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
1064 static int dm_dmub_hw_init(struct amdgpu_device *adev)
1066 const struct dmcub_firmware_header_v1_0 *hdr;
1067 struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1068 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
1069 const struct firmware *dmub_fw = adev->dm.dmub_fw;
1070 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
1071 struct abm *abm = adev->dm.dc->res_pool->abm;
1072 struct dmub_srv_hw_params hw_params;
1073 enum dmub_status status;
1074 const unsigned char *fw_inst_const, *fw_bss_data;
1075 u32 i, fw_inst_const_size, fw_bss_data_size;
1076 bool has_hw_support;
1079 /* DMUB isn't supported on the ASIC. */
1083 DRM_ERROR("No framebuffer info for DMUB service.\n");
1088 /* Firmware required for DMUB support. */
1089 DRM_ERROR("No firmware provided for DMUB.\n");
1093 status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
1094 if (status != DMUB_STATUS_OK) {
1095 DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
1099 if (!has_hw_support) {
1100 DRM_INFO("DMUB unsupported on ASIC\n");
1104 /* Reset DMCUB if it was previously running - before we overwrite its memory. */
1105 status = dmub_srv_hw_reset(dmub_srv);
1106 if (status != DMUB_STATUS_OK)
1107 DRM_WARN("Error resetting DMUB HW: %d\n", status);
1109 hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
1111 fw_inst_const = dmub_fw->data +
1112 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1115 fw_bss_data = dmub_fw->data +
1116 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1117 le32_to_cpu(hdr->inst_const_bytes);
1119 /* Copy firmware and bios info into FB memory. */
1120 fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
1121 PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
1123 fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
1125 /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP,
1126 * amdgpu_ucode_init_single_fw will load dmub firmware
1127 * fw_inst_const part to cw0; otherwise, the firmware back door load
1128 * will be done by dm_dmub_hw_init
1130 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1131 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
1132 fw_inst_const_size);
1135 if (fw_bss_data_size)
1136 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr,
1137 fw_bss_data, fw_bss_data_size);
1139 /* Copy firmware bios info into FB memory. */
1140 memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,
1143 /* Reset regions that need to be reset. */
1144 memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,
1145 fb_info->fb[DMUB_WINDOW_4_MAILBOX].size);
1147 memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,
1148 fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size);
1150 memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,
1151 fb_info->fb[DMUB_WINDOW_6_FW_STATE].size);
1153 /* Initialize hardware. */
1154 memset(&hw_params, 0, sizeof(hw_params));
1155 hw_params.fb_base = adev->gmc.fb_start;
1156 hw_params.fb_offset = adev->vm_manager.vram_base_offset;
1158 /* backdoor load firmware and trigger dmub running */
1159 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
1160 hw_params.load_inst_const = true;
1163 hw_params.psp_version = dmcu->psp_version;
1165 for (i = 0; i < fb_info->num_fb; ++i)
1166 hw_params.fb[i] = &fb_info->fb[i];
1168 switch (adev->ip_versions[DCE_HWIP][0]) {
1169 case IP_VERSION(3, 1, 3):
1170 case IP_VERSION(3, 1, 4):
1171 hw_params.dpia_supported = true;
1172 hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia;
1178 status = dmub_srv_hw_init(dmub_srv, &hw_params);
1179 if (status != DMUB_STATUS_OK) {
1180 DRM_ERROR("Error initializing DMUB HW: %d\n", status);
1184 /* Wait for firmware load to finish. */
1185 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1186 if (status != DMUB_STATUS_OK)
1187 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1189 /* Init DMCU and ABM if available. */
1191 dmcu->funcs->dmcu_init(dmcu);
1192 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
1195 if (!adev->dm.dc->ctx->dmub_srv)
1196 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
1197 if (!adev->dm.dc->ctx->dmub_srv) {
1198 DRM_ERROR("Couldn't allocate DC DMUB server!\n");
1202 DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
1203 adev->dm.dmcub_fw_version);
1208 static void dm_dmub_hw_resume(struct amdgpu_device *adev)
1210 struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1211 enum dmub_status status;
1215 /* DMUB isn't supported on the ASIC. */
1219 status = dmub_srv_is_hw_init(dmub_srv, &init);
1220 if (status != DMUB_STATUS_OK)
1221 DRM_WARN("DMUB hardware init check failed: %d\n", status);
1223 if (status == DMUB_STATUS_OK && init) {
1224 /* Wait for firmware load to finish. */
1225 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1226 if (status != DMUB_STATUS_OK)
1227 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1229 /* Perform the full hardware initialization. */
1230 dm_dmub_hw_init(adev);
1234 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
1237 u32 logical_addr_low;
1238 u32 logical_addr_high;
1239 u32 agp_base, agp_bot, agp_top;
1240 PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;
1242 memset(pa_config, 0, sizeof(*pa_config));
1245 agp_bot = adev->gmc.agp_start >> 24;
1246 agp_top = adev->gmc.agp_end >> 24;
1248 /* AGP aperture is disabled */
1249 if (agp_bot == agp_top) {
1250 logical_addr_low = adev->gmc.fb_start >> 18;
1251 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1253 * Raven2 has a HW issue that it is unable to use the vram which
1254 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1255 * workaround that increase system aperture high address (add 1)
1256 * to get rid of the VM fault and hardware hang.
1258 logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1;
1260 logical_addr_high = adev->gmc.fb_end >> 18;
1262 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
1263 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1265 * Raven2 has a HW issue that it is unable to use the vram which
1266 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1267 * workaround that increase system aperture high address (add 1)
1268 * to get rid of the VM fault and hardware hang.
1270 logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
1272 logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
1275 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
1277 page_table_start.high_part = upper_32_bits(adev->gmc.gart_start >>
1278 AMDGPU_GPU_PAGE_SHIFT);
1279 page_table_start.low_part = lower_32_bits(adev->gmc.gart_start >>
1280 AMDGPU_GPU_PAGE_SHIFT);
1281 page_table_end.high_part = upper_32_bits(adev->gmc.gart_end >>
1282 AMDGPU_GPU_PAGE_SHIFT);
1283 page_table_end.low_part = lower_32_bits(adev->gmc.gart_end >>
1284 AMDGPU_GPU_PAGE_SHIFT);
1285 page_table_base.high_part = upper_32_bits(pt_base);
1286 page_table_base.low_part = lower_32_bits(pt_base);
1288 pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
1289 pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18;
1291 pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24;
1292 pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24;
1293 pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24;
1295 pa_config->system_aperture.fb_base = adev->gmc.fb_start;
1296 pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset;
1297 pa_config->system_aperture.fb_top = adev->gmc.fb_end;
1299 pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12;
1300 pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12;
1301 pa_config->gart_config.page_table_base_addr = page_table_base.quad_part;
1303 pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support;
1307 static void force_connector_state(
1308 struct amdgpu_dm_connector *aconnector,
1309 enum drm_connector_force force_state)
1311 struct drm_connector *connector = &aconnector->base;
1313 mutex_lock(&connector->dev->mode_config.mutex);
1314 aconnector->base.force = force_state;
1315 mutex_unlock(&connector->dev->mode_config.mutex);
1317 mutex_lock(&aconnector->hpd_lock);
1318 drm_kms_helper_connector_hotplug_event(connector);
1319 mutex_unlock(&aconnector->hpd_lock);
1322 static void dm_handle_hpd_rx_offload_work(struct work_struct *work)
1324 struct hpd_rx_irq_offload_work *offload_work;
1325 struct amdgpu_dm_connector *aconnector;
1326 struct dc_link *dc_link;
1327 struct amdgpu_device *adev;
1328 enum dc_connection_type new_connection_type = dc_connection_none;
1329 unsigned long flags;
1330 union test_response test_response;
1332 memset(&test_response, 0, sizeof(test_response));
1334 offload_work = container_of(work, struct hpd_rx_irq_offload_work, work);
1335 aconnector = offload_work->offload_wq->aconnector;
1338 DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work");
1342 adev = drm_to_adev(aconnector->base.dev);
1343 dc_link = aconnector->dc_link;
1345 mutex_lock(&aconnector->hpd_lock);
1346 if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
1347 DRM_ERROR("KMS: Failed to detect connector\n");
1348 mutex_unlock(&aconnector->hpd_lock);
1350 if (new_connection_type == dc_connection_none)
1353 if (amdgpu_in_reset(adev))
1356 if (offload_work->data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
1357 offload_work->data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
1358 dm_handle_mst_sideband_msg_ready_event(&aconnector->mst_mgr, DOWN_OR_UP_MSG_RDY_EVENT);
1359 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1360 offload_work->offload_wq->is_handling_mst_msg_rdy_event = false;
1361 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1365 mutex_lock(&adev->dm.dc_lock);
1366 if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
1367 dc_link_dp_handle_automated_test(dc_link);
1369 if (aconnector->timing_changed) {
1370 /* force connector disconnect and reconnect */
1371 force_connector_state(aconnector, DRM_FORCE_OFF);
1373 force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED);
1376 test_response.bits.ACK = 1;
1378 core_link_write_dpcd(
1382 sizeof(test_response));
1383 } else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) &&
1384 dc_link_check_link_loss_status(dc_link, &offload_work->data) &&
1385 dc_link_dp_allow_hpd_rx_irq(dc_link)) {
1386 /* offload_work->data is from handle_hpd_rx_irq->
1387 * schedule_hpd_rx_offload_work.this is defer handle
1388 * for hpd short pulse. upon here, link status may be
1389 * changed, need get latest link status from dpcd
1390 * registers. if link status is good, skip run link
1393 union hpd_irq_data irq_data;
1395 memset(&irq_data, 0, sizeof(irq_data));
1397 /* before dc_link_dp_handle_link_loss, allow new link lost handle
1398 * request be added to work queue if link lost at end of dc_link_
1399 * dp_handle_link_loss
1401 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1402 offload_work->offload_wq->is_handling_link_loss = false;
1403 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1405 if ((dc_link_dp_read_hpd_rx_irq_data(dc_link, &irq_data) == DC_OK) &&
1406 dc_link_check_link_loss_status(dc_link, &irq_data))
1407 dc_link_dp_handle_link_loss(dc_link);
1409 mutex_unlock(&adev->dm.dc_lock);
1412 kfree(offload_work);
1416 static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc)
1418 int max_caps = dc->caps.max_links;
1420 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL;
1422 hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL);
1424 if (!hpd_rx_offload_wq)
1428 for (i = 0; i < max_caps; i++) {
1429 hpd_rx_offload_wq[i].wq =
1430 create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq");
1432 if (hpd_rx_offload_wq[i].wq == NULL) {
1433 DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!");
1437 spin_lock_init(&hpd_rx_offload_wq[i].offload_lock);
1440 return hpd_rx_offload_wq;
1443 for (i = 0; i < max_caps; i++) {
1444 if (hpd_rx_offload_wq[i].wq)
1445 destroy_workqueue(hpd_rx_offload_wq[i].wq);
1447 kfree(hpd_rx_offload_wq);
1451 struct amdgpu_stutter_quirk {
1459 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = {
1460 /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */
1461 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },
1465 static bool dm_should_disable_stutter(struct pci_dev *pdev)
1467 const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list;
1469 while (p && p->chip_device != 0) {
1470 if (pdev->vendor == p->chip_vendor &&
1471 pdev->device == p->chip_device &&
1472 pdev->subsystem_vendor == p->subsys_vendor &&
1473 pdev->subsystem_device == p->subsys_device &&
1474 pdev->revision == p->revision) {
1482 static const struct dmi_system_id hpd_disconnect_quirk_table[] = {
1485 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1486 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"),
1491 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1492 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"),
1497 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1498 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"),
1503 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1504 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"),
1509 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1510 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"),
1515 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1516 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"),
1521 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1522 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"),
1527 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1528 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"),
1533 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1534 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"),
1538 /* TODO: refactor this from a fixed table to a dynamic option */
1541 static void retrieve_dmi_info(struct amdgpu_display_manager *dm)
1543 const struct dmi_system_id *dmi_id;
1545 dm->aux_hpd_discon_quirk = false;
1547 dmi_id = dmi_first_match(hpd_disconnect_quirk_table);
1549 dm->aux_hpd_discon_quirk = true;
1550 DRM_INFO("aux_hpd_discon_quirk attached\n");
1554 static int amdgpu_dm_init(struct amdgpu_device *adev)
1556 struct dc_init_data init_data;
1557 struct dc_callback_init init_params;
1560 adev->dm.ddev = adev_to_drm(adev);
1561 adev->dm.adev = adev;
1563 /* Zero all the fields */
1564 memset(&init_data, 0, sizeof(init_data));
1565 memset(&init_params, 0, sizeof(init_params));
1567 mutex_init(&adev->dm.dpia_aux_lock);
1568 mutex_init(&adev->dm.dc_lock);
1569 mutex_init(&adev->dm.audio_lock);
1571 if (amdgpu_dm_irq_init(adev)) {
1572 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
1576 init_data.asic_id.chip_family = adev->family;
1578 init_data.asic_id.pci_revision_id = adev->pdev->revision;
1579 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
1580 init_data.asic_id.chip_id = adev->pdev->device;
1582 init_data.asic_id.vram_width = adev->gmc.vram_width;
1583 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
1584 init_data.asic_id.atombios_base_address =
1585 adev->mode_info.atom_context->bios;
1587 init_data.driver = adev;
1589 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
1591 if (!adev->dm.cgs_device) {
1592 DRM_ERROR("amdgpu: failed to create cgs device.\n");
1596 init_data.cgs_device = adev->dm.cgs_device;
1598 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
1600 switch (adev->ip_versions[DCE_HWIP][0]) {
1601 case IP_VERSION(2, 1, 0):
1602 switch (adev->dm.dmcub_fw_version) {
1603 case 0: /* development */
1604 case 0x1: /* linux-firmware.git hash 6d9f399 */
1605 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */
1606 init_data.flags.disable_dmcu = false;
1609 init_data.flags.disable_dmcu = true;
1612 case IP_VERSION(2, 0, 3):
1613 init_data.flags.disable_dmcu = true;
1619 switch (adev->asic_type) {
1622 init_data.flags.gpu_vm_support = true;
1625 switch (adev->ip_versions[DCE_HWIP][0]) {
1626 case IP_VERSION(1, 0, 0):
1627 case IP_VERSION(1, 0, 1):
1628 /* enable S/G on PCO and RV2 */
1629 if ((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
1630 (adev->apu_flags & AMD_APU_IS_PICASSO))
1631 init_data.flags.gpu_vm_support = true;
1633 case IP_VERSION(2, 1, 0):
1634 case IP_VERSION(3, 0, 1):
1635 case IP_VERSION(3, 1, 2):
1636 case IP_VERSION(3, 1, 3):
1637 case IP_VERSION(3, 1, 4):
1638 case IP_VERSION(3, 1, 5):
1639 case IP_VERSION(3, 1, 6):
1640 init_data.flags.gpu_vm_support = true;
1647 if (init_data.flags.gpu_vm_support &&
1648 (amdgpu_sg_display == 0))
1649 init_data.flags.gpu_vm_support = false;
1651 if (init_data.flags.gpu_vm_support)
1652 adev->mode_info.gpu_vm_support = true;
1654 if (amdgpu_dc_feature_mask & DC_FBC_MASK)
1655 init_data.flags.fbc_support = true;
1657 if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
1658 init_data.flags.multi_mon_pp_mclk_switch = true;
1660 if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
1661 init_data.flags.disable_fractional_pwm = true;
1663 if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING)
1664 init_data.flags.edp_no_power_sequencing = true;
1666 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A)
1667 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true;
1668 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)
1669 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;
1671 init_data.flags.seamless_boot_edp_requested = false;
1673 if (check_seamless_boot_capability(adev)) {
1674 init_data.flags.seamless_boot_edp_requested = true;
1675 init_data.flags.allow_seamless_boot_optimization = true;
1676 DRM_INFO("Seamless boot condition check passed\n");
1679 init_data.flags.enable_mipi_converter_optimization = true;
1681 init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];
1682 init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];
1684 INIT_LIST_HEAD(&adev->dm.da_list);
1686 retrieve_dmi_info(&adev->dm);
1688 /* Display Core create. */
1689 adev->dm.dc = dc_create(&init_data);
1692 DRM_INFO("Display Core v%s initialized on %s\n", DC_VER,
1693 dce_version_to_string(adev->dm.dc->ctx->dce_version));
1695 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
1699 if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
1700 adev->dm.dc->debug.force_single_disp_pipe_split = false;
1701 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
1704 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
1705 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
1706 if (dm_should_disable_stutter(adev->pdev))
1707 adev->dm.dc->debug.disable_stutter = true;
1709 if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
1710 adev->dm.dc->debug.disable_stutter = true;
1712 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC)
1713 adev->dm.dc->debug.disable_dsc = true;
1715 if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
1716 adev->dm.dc->debug.disable_clock_gate = true;
1718 if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH)
1719 adev->dm.dc->debug.force_subvp_mclk_switch = true;
1721 adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm;
1723 /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */
1724 adev->dm.dc->debug.ignore_cable_id = true;
1726 /* TODO: There is a new drm mst change where the freedom of
1727 * vc_next_start_slot update is revoked/moved into drm, instead of in
1728 * driver. This forces us to make sure to get vc_next_start_slot updated
1729 * in drm function each time without considering if mst_state is active
1730 * or not. Otherwise, next time hotplug will give wrong start_slot
1731 * number. We are implementing a temporary solution to even notify drm
1732 * mst deallocation when link is no longer of MST type when uncommitting
1733 * the stream so we will have more time to work on a proper solution.
1734 * Ideally when dm_helpers_dp_mst_stop_top_mgr message is triggered, we
1735 * should notify drm to do a complete "reset" of its states and stop
1736 * calling further drm mst functions when link is no longer of an MST
1737 * type. This could happen when we unplug an MST hubs/displays. When
1738 * uncommit stream comes later after unplug, we should just reset
1739 * hardware states only.
1741 adev->dm.dc->debug.temp_mst_deallocation_sequence = true;
1743 if (adev->dm.dc->caps.dp_hdmi21_pcon_support)
1744 DRM_INFO("DP-HDMI FRL PCON supported\n");
1746 r = dm_dmub_hw_init(adev);
1748 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
1752 dc_hardware_init(adev->dm.dc);
1754 adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc);
1755 if (!adev->dm.hpd_rx_offload_wq) {
1756 DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n");
1760 if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) {
1761 struct dc_phy_addr_space_config pa_config;
1763 mmhub_read_system_context(adev, &pa_config);
1765 // Call the DC init_memory func
1766 dc_setup_system_context(adev->dm.dc, &pa_config);
1769 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
1770 if (!adev->dm.freesync_module) {
1772 "amdgpu: failed to initialize freesync_module.\n");
1774 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
1775 adev->dm.freesync_module);
1777 amdgpu_dm_init_color_mod();
1779 if (adev->dm.dc->caps.max_links > 0) {
1780 adev->dm.vblank_control_workqueue =
1781 create_singlethread_workqueue("dm_vblank_control_workqueue");
1782 if (!adev->dm.vblank_control_workqueue)
1783 DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n");
1786 if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
1787 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
1789 if (!adev->dm.hdcp_workqueue)
1790 DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
1792 DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
1794 dc_init_callbacks(adev->dm.dc, &init_params);
1796 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
1797 init_completion(&adev->dm.dmub_aux_transfer_done);
1798 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL);
1799 if (!adev->dm.dmub_notify) {
1800 DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify");
1804 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq");
1805 if (!adev->dm.delayed_hpd_wq) {
1806 DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n");
1810 amdgpu_dm_outbox_init(adev);
1811 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY,
1812 dmub_aux_setconfig_callback, false)) {
1813 DRM_ERROR("amdgpu: fail to register dmub aux callback");
1816 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true)) {
1817 DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1820 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true)) {
1821 DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1826 /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive.
1827 * It is expected that DMUB will resend any pending notifications at this point, for
1828 * example HPD from DPIA.
1830 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
1831 dc_enable_dmub_outbox(adev->dm.dc);
1833 /* DPIA trace goes to dmesg logs only if outbox is enabled */
1834 if (amdgpu_dc_debug_mask & DC_ENABLE_DPIA_TRACE)
1835 dc_dmub_srv_enable_dpia_trace(adev->dm.dc);
1838 if (amdgpu_dm_initialize_drm_device(adev)) {
1840 "amdgpu: failed to initialize sw for display support.\n");
1844 /* create fake encoders for MST */
1845 dm_dp_create_fake_mst_encoders(adev);
1847 /* TODO: Add_display_info? */
1849 /* TODO use dynamic cursor width */
1850 adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
1851 adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
1853 if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
1855 "amdgpu: failed to initialize sw for display support.\n");
1859 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1860 adev->dm.secure_display_ctxs = amdgpu_dm_crtc_secure_display_create_contexts(adev);
1861 if (!adev->dm.secure_display_ctxs)
1862 DRM_ERROR("amdgpu: failed to initialize secure display contexts.\n");
1865 DRM_DEBUG_DRIVER("KMS initialized.\n");
1869 amdgpu_dm_fini(adev);
1874 static int amdgpu_dm_early_fini(void *handle)
1876 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1878 amdgpu_dm_audio_fini(adev);
1883 static void amdgpu_dm_fini(struct amdgpu_device *adev)
1887 if (adev->dm.vblank_control_workqueue) {
1888 destroy_workqueue(adev->dm.vblank_control_workqueue);
1889 adev->dm.vblank_control_workqueue = NULL;
1892 amdgpu_dm_destroy_drm_device(&adev->dm);
1894 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1895 if (adev->dm.secure_display_ctxs) {
1896 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1897 if (adev->dm.secure_display_ctxs[i].crtc) {
1898 flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work);
1899 flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work);
1902 kfree(adev->dm.secure_display_ctxs);
1903 adev->dm.secure_display_ctxs = NULL;
1906 if (adev->dm.hdcp_workqueue) {
1907 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue);
1908 adev->dm.hdcp_workqueue = NULL;
1912 dc_deinit_callbacks(adev->dm.dc);
1915 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
1917 if (dc_enable_dmub_notifications(adev->dm.dc)) {
1918 kfree(adev->dm.dmub_notify);
1919 adev->dm.dmub_notify = NULL;
1920 destroy_workqueue(adev->dm.delayed_hpd_wq);
1921 adev->dm.delayed_hpd_wq = NULL;
1924 if (adev->dm.dmub_bo)
1925 amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
1926 &adev->dm.dmub_bo_gpu_addr,
1927 &adev->dm.dmub_bo_cpu_addr);
1929 if (adev->dm.hpd_rx_offload_wq) {
1930 for (i = 0; i < adev->dm.dc->caps.max_links; i++) {
1931 if (adev->dm.hpd_rx_offload_wq[i].wq) {
1932 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq);
1933 adev->dm.hpd_rx_offload_wq[i].wq = NULL;
1937 kfree(adev->dm.hpd_rx_offload_wq);
1938 adev->dm.hpd_rx_offload_wq = NULL;
1941 /* DC Destroy TODO: Replace destroy DAL */
1943 dc_destroy(&adev->dm.dc);
1945 * TODO: pageflip, vlank interrupt
1947 * amdgpu_dm_irq_fini(adev);
1950 if (adev->dm.cgs_device) {
1951 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
1952 adev->dm.cgs_device = NULL;
1954 if (adev->dm.freesync_module) {
1955 mod_freesync_destroy(adev->dm.freesync_module);
1956 adev->dm.freesync_module = NULL;
1959 mutex_destroy(&adev->dm.audio_lock);
1960 mutex_destroy(&adev->dm.dc_lock);
1961 mutex_destroy(&adev->dm.dpia_aux_lock);
1964 static int load_dmcu_fw(struct amdgpu_device *adev)
1966 const char *fw_name_dmcu = NULL;
1968 const struct dmcu_firmware_header_v1_0 *hdr;
1970 switch (adev->asic_type) {
1971 #if defined(CONFIG_DRM_AMD_DC_SI)
1986 case CHIP_POLARIS11:
1987 case CHIP_POLARIS10:
1988 case CHIP_POLARIS12:
1995 fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
1998 if (ASICREV_IS_PICASSO(adev->external_rev_id))
1999 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
2000 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
2001 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
2006 switch (adev->ip_versions[DCE_HWIP][0]) {
2007 case IP_VERSION(2, 0, 2):
2008 case IP_VERSION(2, 0, 3):
2009 case IP_VERSION(2, 0, 0):
2010 case IP_VERSION(2, 1, 0):
2011 case IP_VERSION(3, 0, 0):
2012 case IP_VERSION(3, 0, 2):
2013 case IP_VERSION(3, 0, 3):
2014 case IP_VERSION(3, 0, 1):
2015 case IP_VERSION(3, 1, 2):
2016 case IP_VERSION(3, 1, 3):
2017 case IP_VERSION(3, 1, 4):
2018 case IP_VERSION(3, 1, 5):
2019 case IP_VERSION(3, 1, 6):
2020 case IP_VERSION(3, 2, 0):
2021 case IP_VERSION(3, 2, 1):
2026 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2030 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2031 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
2035 r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, fw_name_dmcu);
2037 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
2038 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
2039 adev->dm.fw_dmcu = NULL;
2043 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
2045 amdgpu_ucode_release(&adev->dm.fw_dmcu);
2049 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
2050 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
2051 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
2052 adev->firmware.fw_size +=
2053 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2055 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
2056 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
2057 adev->firmware.fw_size +=
2058 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2060 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
2062 DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
2067 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
2069 struct amdgpu_device *adev = ctx;
2071 return dm_read_reg(adev->dm.dc->ctx, address);
2074 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
2077 struct amdgpu_device *adev = ctx;
2079 return dm_write_reg(adev->dm.dc->ctx, address, value);
2082 static int dm_dmub_sw_init(struct amdgpu_device *adev)
2084 struct dmub_srv_create_params create_params;
2085 struct dmub_srv_region_params region_params;
2086 struct dmub_srv_region_info region_info;
2087 struct dmub_srv_fb_params fb_params;
2088 struct dmub_srv_fb_info *fb_info;
2089 struct dmub_srv *dmub_srv;
2090 const struct dmcub_firmware_header_v1_0 *hdr;
2091 enum dmub_asic dmub_asic;
2092 enum dmub_status status;
2095 switch (adev->ip_versions[DCE_HWIP][0]) {
2096 case IP_VERSION(2, 1, 0):
2097 dmub_asic = DMUB_ASIC_DCN21;
2099 case IP_VERSION(3, 0, 0):
2100 dmub_asic = DMUB_ASIC_DCN30;
2102 case IP_VERSION(3, 0, 1):
2103 dmub_asic = DMUB_ASIC_DCN301;
2105 case IP_VERSION(3, 0, 2):
2106 dmub_asic = DMUB_ASIC_DCN302;
2108 case IP_VERSION(3, 0, 3):
2109 dmub_asic = DMUB_ASIC_DCN303;
2111 case IP_VERSION(3, 1, 2):
2112 case IP_VERSION(3, 1, 3):
2113 dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31;
2115 case IP_VERSION(3, 1, 4):
2116 dmub_asic = DMUB_ASIC_DCN314;
2118 case IP_VERSION(3, 1, 5):
2119 dmub_asic = DMUB_ASIC_DCN315;
2121 case IP_VERSION(3, 1, 6):
2122 dmub_asic = DMUB_ASIC_DCN316;
2124 case IP_VERSION(3, 2, 0):
2125 dmub_asic = DMUB_ASIC_DCN32;
2127 case IP_VERSION(3, 2, 1):
2128 dmub_asic = DMUB_ASIC_DCN321;
2131 /* ASIC doesn't support DMUB. */
2135 hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
2136 adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
2138 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2139 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
2140 AMDGPU_UCODE_ID_DMCUB;
2141 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw =
2143 adev->firmware.fw_size +=
2144 ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
2146 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
2147 adev->dm.dmcub_fw_version);
2151 adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
2152 dmub_srv = adev->dm.dmub_srv;
2155 DRM_ERROR("Failed to allocate DMUB service!\n");
2159 memset(&create_params, 0, sizeof(create_params));
2160 create_params.user_ctx = adev;
2161 create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
2162 create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
2163 create_params.asic = dmub_asic;
2165 /* Create the DMUB service. */
2166 status = dmub_srv_create(dmub_srv, &create_params);
2167 if (status != DMUB_STATUS_OK) {
2168 DRM_ERROR("Error creating DMUB service: %d\n", status);
2172 /* Calculate the size of all the regions for the DMUB service. */
2173 memset(®ion_params, 0, sizeof(region_params));
2175 region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
2176 PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
2177 region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
2178 region_params.vbios_size = adev->bios_size;
2179 region_params.fw_bss_data = region_params.bss_data_size ?
2180 adev->dm.dmub_fw->data +
2181 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2182 le32_to_cpu(hdr->inst_const_bytes) : NULL;
2183 region_params.fw_inst_const =
2184 adev->dm.dmub_fw->data +
2185 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2188 status = dmub_srv_calc_region_info(dmub_srv, ®ion_params,
2191 if (status != DMUB_STATUS_OK) {
2192 DRM_ERROR("Error calculating DMUB region info: %d\n", status);
2197 * Allocate a framebuffer based on the total size of all the regions.
2198 * TODO: Move this into GART.
2200 r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
2201 AMDGPU_GEM_DOMAIN_VRAM |
2202 AMDGPU_GEM_DOMAIN_GTT,
2204 &adev->dm.dmub_bo_gpu_addr,
2205 &adev->dm.dmub_bo_cpu_addr);
2209 /* Rebase the regions on the framebuffer address. */
2210 memset(&fb_params, 0, sizeof(fb_params));
2211 fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr;
2212 fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr;
2213 fb_params.region_info = ®ion_info;
2215 adev->dm.dmub_fb_info =
2216 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);
2217 fb_info = adev->dm.dmub_fb_info;
2221 "Failed to allocate framebuffer info for DMUB service!\n");
2225 status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info);
2226 if (status != DMUB_STATUS_OK) {
2227 DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
2234 static int dm_sw_init(void *handle)
2236 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2239 r = dm_dmub_sw_init(adev);
2243 return load_dmcu_fw(adev);
2246 static int dm_sw_fini(void *handle)
2248 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2250 kfree(adev->dm.dmub_fb_info);
2251 adev->dm.dmub_fb_info = NULL;
2253 if (adev->dm.dmub_srv) {
2254 dmub_srv_destroy(adev->dm.dmub_srv);
2255 adev->dm.dmub_srv = NULL;
2258 amdgpu_ucode_release(&adev->dm.dmub_fw);
2259 amdgpu_ucode_release(&adev->dm.fw_dmcu);
2264 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
2266 struct amdgpu_dm_connector *aconnector;
2267 struct drm_connector *connector;
2268 struct drm_connector_list_iter iter;
2271 drm_connector_list_iter_begin(dev, &iter);
2272 drm_for_each_connector_iter(connector, &iter) {
2273 aconnector = to_amdgpu_dm_connector(connector);
2274 if (aconnector->dc_link->type == dc_connection_mst_branch &&
2275 aconnector->mst_mgr.aux) {
2276 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
2278 aconnector->base.base.id);
2280 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
2282 DRM_ERROR("DM_MST: Failed to start MST\n");
2283 aconnector->dc_link->type =
2284 dc_connection_single;
2285 ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2286 aconnector->dc_link);
2291 drm_connector_list_iter_end(&iter);
2296 static int dm_late_init(void *handle)
2298 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2300 struct dmcu_iram_parameters params;
2301 unsigned int linear_lut[16];
2303 struct dmcu *dmcu = NULL;
2305 dmcu = adev->dm.dc->res_pool->dmcu;
2307 for (i = 0; i < 16; i++)
2308 linear_lut[i] = 0xFFFF * i / 15;
2311 params.backlight_ramping_override = false;
2312 params.backlight_ramping_start = 0xCCCC;
2313 params.backlight_ramping_reduction = 0xCCCCCCCC;
2314 params.backlight_lut_array_size = 16;
2315 params.backlight_lut_array = linear_lut;
2317 /* Min backlight level after ABM reduction, Don't allow below 1%
2318 * 0xFFFF x 0.01 = 0x28F
2320 params.min_abm_backlight = 0x28F;
2321 /* In the case where abm is implemented on dmcub,
2322 * dmcu object will be null.
2323 * ABM 2.4 and up are implemented on dmcub.
2326 if (!dmcu_load_iram(dmcu, params))
2328 } else if (adev->dm.dc->ctx->dmub_srv) {
2329 struct dc_link *edp_links[MAX_NUM_EDP];
2332 dc_get_edp_links(adev->dm.dc, edp_links, &edp_num);
2333 for (i = 0; i < edp_num; i++) {
2334 if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i))
2339 return detect_mst_link_for_all_connectors(adev_to_drm(adev));
2342 static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr)
2348 mutex_lock(&mgr->lock);
2349 if (!mgr->mst_primary)
2352 if (drm_dp_read_dpcd_caps(mgr->aux, mgr->dpcd) < 0) {
2353 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n");
2357 ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
2360 DP_UPSTREAM_IS_SRC);
2362 drm_dbg_kms(mgr->dev, "mst write failed - undocked during suspend?\n");
2366 /* Some hubs forget their guids after they resume */
2367 ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, guid, 16);
2369 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n");
2373 if (memchr_inv(guid, 0, 16) == NULL) {
2374 tmp64 = get_jiffies_64();
2375 memcpy(&guid[0], &tmp64, sizeof(u64));
2376 memcpy(&guid[8], &tmp64, sizeof(u64));
2378 ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, guid, 16);
2381 drm_dbg_kms(mgr->dev, "check mstb guid failed - undocked during suspend?\n");
2386 memcpy(mgr->mst_primary->guid, guid, 16);
2389 mutex_unlock(&mgr->lock);
2392 static void s3_handle_mst(struct drm_device *dev, bool suspend)
2394 struct amdgpu_dm_connector *aconnector;
2395 struct drm_connector *connector;
2396 struct drm_connector_list_iter iter;
2397 struct drm_dp_mst_topology_mgr *mgr;
2399 drm_connector_list_iter_begin(dev, &iter);
2400 drm_for_each_connector_iter(connector, &iter) {
2401 aconnector = to_amdgpu_dm_connector(connector);
2402 if (aconnector->dc_link->type != dc_connection_mst_branch ||
2403 aconnector->mst_root)
2406 mgr = &aconnector->mst_mgr;
2409 drm_dp_mst_topology_mgr_suspend(mgr);
2411 /* if extended timeout is supported in hardware,
2412 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
2413 * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
2415 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
2416 if (!dp_is_lttpr_present(aconnector->dc_link))
2417 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
2419 /* TODO: move resume_mst_branch_status() into drm mst resume again
2420 * once topology probing work is pulled out from mst resume into mst
2421 * resume 2nd step. mst resume 2nd step should be called after old
2422 * state getting restored (i.e. drm_atomic_helper_resume()).
2424 resume_mst_branch_status(mgr);
2427 drm_connector_list_iter_end(&iter);
2430 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
2434 /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
2435 * on window driver dc implementation.
2436 * For Navi1x, clock settings of dcn watermarks are fixed. the settings
2437 * should be passed to smu during boot up and resume from s3.
2438 * boot up: dc calculate dcn watermark clock settings within dc_create,
2439 * dcn20_resource_construct
2440 * then call pplib functions below to pass the settings to smu:
2441 * smu_set_watermarks_for_clock_ranges
2442 * smu_set_watermarks_table
2443 * navi10_set_watermarks_table
2444 * smu_write_watermarks_table
2446 * For Renoir, clock settings of dcn watermark are also fixed values.
2447 * dc has implemented different flow for window driver:
2448 * dc_hardware_init / dc_set_power_state
2453 * smu_set_watermarks_for_clock_ranges
2454 * renoir_set_watermarks_table
2455 * smu_write_watermarks_table
2458 * dc_hardware_init -> amdgpu_dm_init
2459 * dc_set_power_state --> dm_resume
2461 * therefore, this function apply to navi10/12/14 but not Renoir
2464 switch (adev->ip_versions[DCE_HWIP][0]) {
2465 case IP_VERSION(2, 0, 2):
2466 case IP_VERSION(2, 0, 0):
2472 ret = amdgpu_dpm_write_watermarks_table(adev);
2474 DRM_ERROR("Failed to update WMTABLE!\n");
2482 * dm_hw_init() - Initialize DC device
2483 * @handle: The base driver device containing the amdgpu_dm device.
2485 * Initialize the &struct amdgpu_display_manager device. This involves calling
2486 * the initializers of each DM component, then populating the struct with them.
2488 * Although the function implies hardware initialization, both hardware and
2489 * software are initialized here. Splitting them out to their relevant init
2490 * hooks is a future TODO item.
2492 * Some notable things that are initialized here:
2494 * - Display Core, both software and hardware
2495 * - DC modules that we need (freesync and color management)
2496 * - DRM software states
2497 * - Interrupt sources and handlers
2499 * - Debug FS entries, if enabled
2501 static int dm_hw_init(void *handle)
2503 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2504 /* Create DAL display manager */
2505 amdgpu_dm_init(adev);
2506 amdgpu_dm_hpd_init(adev);
2512 * dm_hw_fini() - Teardown DC device
2513 * @handle: The base driver device containing the amdgpu_dm device.
2515 * Teardown components within &struct amdgpu_display_manager that require
2516 * cleanup. This involves cleaning up the DRM device, DC, and any modules that
2517 * were loaded. Also flush IRQ workqueues and disable them.
2519 static int dm_hw_fini(void *handle)
2521 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2523 amdgpu_dm_hpd_fini(adev);
2525 amdgpu_dm_irq_fini(adev);
2526 amdgpu_dm_fini(adev);
2531 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
2532 struct dc_state *state, bool enable)
2534 enum dc_irq_source irq_source;
2535 struct amdgpu_crtc *acrtc;
2539 for (i = 0; i < state->stream_count; i++) {
2540 acrtc = get_crtc_by_otg_inst(
2541 adev, state->stream_status[i].primary_otg_inst);
2543 if (acrtc && state->stream_status[i].plane_count != 0) {
2544 irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst;
2545 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
2547 DRM_WARN("Failed to %s pflip interrupts\n",
2548 enable ? "enable" : "disable");
2551 if (amdgpu_dm_crtc_vrr_active(to_dm_crtc_state(acrtc->base.state)))
2552 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, true);
2554 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, false);
2557 DRM_WARN("Failed to %sable vupdate interrupt\n", enable ? "en" : "dis");
2559 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
2560 /* During gpu-reset we disable and then enable vblank irq, so
2561 * don't use amdgpu_irq_get/put() to avoid refcount change.
2563 if (!dc_interrupt_set(adev->dm.dc, irq_source, enable))
2564 DRM_WARN("Failed to %sable vblank interrupt\n", enable ? "en" : "dis");
2570 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
2572 struct dc_state *context = NULL;
2573 enum dc_status res = DC_ERROR_UNEXPECTED;
2575 struct dc_stream_state *del_streams[MAX_PIPES];
2576 int del_streams_count = 0;
2578 memset(del_streams, 0, sizeof(del_streams));
2580 context = dc_create_state(dc);
2581 if (context == NULL)
2582 goto context_alloc_fail;
2584 dc_resource_state_copy_construct_current(dc, context);
2586 /* First remove from context all streams */
2587 for (i = 0; i < context->stream_count; i++) {
2588 struct dc_stream_state *stream = context->streams[i];
2590 del_streams[del_streams_count++] = stream;
2593 /* Remove all planes for removed streams and then remove the streams */
2594 for (i = 0; i < del_streams_count; i++) {
2595 if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) {
2596 res = DC_FAIL_DETACH_SURFACES;
2600 res = dc_remove_stream_from_ctx(dc, context, del_streams[i]);
2605 res = dc_commit_streams(dc, context->streams, context->stream_count);
2608 dc_release_state(context);
2614 static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm)
2618 if (dm->hpd_rx_offload_wq) {
2619 for (i = 0; i < dm->dc->caps.max_links; i++)
2620 flush_workqueue(dm->hpd_rx_offload_wq[i].wq);
2624 static int dm_suspend(void *handle)
2626 struct amdgpu_device *adev = handle;
2627 struct amdgpu_display_manager *dm = &adev->dm;
2630 if (amdgpu_in_reset(adev)) {
2631 mutex_lock(&dm->dc_lock);
2633 dc_allow_idle_optimizations(adev->dm.dc, false);
2635 dm->cached_dc_state = dc_copy_state(dm->dc->current_state);
2637 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
2639 amdgpu_dm_commit_zero_streams(dm->dc);
2641 amdgpu_dm_irq_suspend(adev);
2643 hpd_rx_irq_work_suspend(dm);
2648 WARN_ON(adev->dm.cached_state);
2649 adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));
2651 s3_handle_mst(adev_to_drm(adev), true);
2653 amdgpu_dm_irq_suspend(adev);
2655 hpd_rx_irq_work_suspend(dm);
2657 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
2662 struct amdgpu_dm_connector *
2663 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
2664 struct drm_crtc *crtc)
2667 struct drm_connector_state *new_con_state;
2668 struct drm_connector *connector;
2669 struct drm_crtc *crtc_from_state;
2671 for_each_new_connector_in_state(state, connector, new_con_state, i) {
2672 crtc_from_state = new_con_state->crtc;
2674 if (crtc_from_state == crtc)
2675 return to_amdgpu_dm_connector(connector);
2681 static void emulated_link_detect(struct dc_link *link)
2683 struct dc_sink_init_data sink_init_data = { 0 };
2684 struct display_sink_capability sink_caps = { 0 };
2685 enum dc_edid_status edid_status;
2686 struct dc_context *dc_ctx = link->ctx;
2687 struct dc_sink *sink = NULL;
2688 struct dc_sink *prev_sink = NULL;
2690 link->type = dc_connection_none;
2691 prev_sink = link->local_sink;
2694 dc_sink_release(prev_sink);
2696 switch (link->connector_signal) {
2697 case SIGNAL_TYPE_HDMI_TYPE_A: {
2698 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2699 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
2703 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
2704 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2705 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
2709 case SIGNAL_TYPE_DVI_DUAL_LINK: {
2710 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2711 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
2715 case SIGNAL_TYPE_LVDS: {
2716 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2717 sink_caps.signal = SIGNAL_TYPE_LVDS;
2721 case SIGNAL_TYPE_EDP: {
2722 sink_caps.transaction_type =
2723 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2724 sink_caps.signal = SIGNAL_TYPE_EDP;
2728 case SIGNAL_TYPE_DISPLAY_PORT: {
2729 sink_caps.transaction_type =
2730 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2731 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
2736 DC_ERROR("Invalid connector type! signal:%d\n",
2737 link->connector_signal);
2741 sink_init_data.link = link;
2742 sink_init_data.sink_signal = sink_caps.signal;
2744 sink = dc_sink_create(&sink_init_data);
2746 DC_ERROR("Failed to create sink!\n");
2750 /* dc_sink_create returns a new reference */
2751 link->local_sink = sink;
2753 edid_status = dm_helpers_read_local_edid(
2758 if (edid_status != EDID_OK)
2759 DC_ERROR("Failed to read EDID");
2763 static void dm_gpureset_commit_state(struct dc_state *dc_state,
2764 struct amdgpu_display_manager *dm)
2767 struct dc_surface_update surface_updates[MAX_SURFACES];
2768 struct dc_plane_info plane_infos[MAX_SURFACES];
2769 struct dc_scaling_info scaling_infos[MAX_SURFACES];
2770 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
2771 struct dc_stream_update stream_update;
2775 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
2778 dm_error("Failed to allocate update bundle\n");
2782 for (k = 0; k < dc_state->stream_count; k++) {
2783 bundle->stream_update.stream = dc_state->streams[k];
2785 for (m = 0; m < dc_state->stream_status->plane_count; m++) {
2786 bundle->surface_updates[m].surface =
2787 dc_state->stream_status->plane_states[m];
2788 bundle->surface_updates[m].surface->force_full_update =
2792 update_planes_and_stream_adapter(dm->dc,
2794 dc_state->stream_status->plane_count,
2795 dc_state->streams[k],
2796 &bundle->stream_update,
2797 bundle->surface_updates);
2804 static int dm_resume(void *handle)
2806 struct amdgpu_device *adev = handle;
2807 struct drm_device *ddev = adev_to_drm(adev);
2808 struct amdgpu_display_manager *dm = &adev->dm;
2809 struct amdgpu_dm_connector *aconnector;
2810 struct drm_connector *connector;
2811 struct drm_connector_list_iter iter;
2812 struct drm_crtc *crtc;
2813 struct drm_crtc_state *new_crtc_state;
2814 struct dm_crtc_state *dm_new_crtc_state;
2815 struct drm_plane *plane;
2816 struct drm_plane_state *new_plane_state;
2817 struct dm_plane_state *dm_new_plane_state;
2818 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
2819 enum dc_connection_type new_connection_type = dc_connection_none;
2820 struct dc_state *dc_state;
2822 bool need_hotplug = false;
2824 if (amdgpu_in_reset(adev)) {
2825 dc_state = dm->cached_dc_state;
2828 * The dc->current_state is backed up into dm->cached_dc_state
2829 * before we commit 0 streams.
2831 * DC will clear link encoder assignments on the real state
2832 * but the changes won't propagate over to the copy we made
2833 * before the 0 streams commit.
2835 * DC expects that link encoder assignments are *not* valid
2836 * when committing a state, so as a workaround we can copy
2837 * off of the current state.
2839 * We lose the previous assignments, but we had already
2840 * commit 0 streams anyway.
2842 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state);
2844 r = dm_dmub_hw_init(adev);
2846 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
2848 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2851 amdgpu_dm_irq_resume_early(adev);
2853 for (i = 0; i < dc_state->stream_count; i++) {
2854 dc_state->streams[i]->mode_changed = true;
2855 for (j = 0; j < dc_state->stream_status[i].plane_count; j++) {
2856 dc_state->stream_status[i].plane_states[j]->update_flags.raw
2861 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2862 amdgpu_dm_outbox_init(adev);
2863 dc_enable_dmub_outbox(adev->dm.dc);
2866 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
2868 dm_gpureset_commit_state(dm->cached_dc_state, dm);
2870 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true);
2872 dc_release_state(dm->cached_dc_state);
2873 dm->cached_dc_state = NULL;
2875 amdgpu_dm_irq_resume_late(adev);
2877 mutex_unlock(&dm->dc_lock);
2881 /* Recreate dc_state - DC invalidates it when setting power state to S3. */
2882 dc_release_state(dm_state->context);
2883 dm_state->context = dc_create_state(dm->dc);
2884 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
2885 dc_resource_state_construct(dm->dc, dm_state->context);
2887 /* Before powering on DC we need to re-initialize DMUB. */
2888 dm_dmub_hw_resume(adev);
2890 /* Re-enable outbox interrupts for DPIA. */
2891 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2892 amdgpu_dm_outbox_init(adev);
2893 dc_enable_dmub_outbox(adev->dm.dc);
2896 /* power on hardware */
2897 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2899 /* program HPD filter */
2903 * early enable HPD Rx IRQ, should be done before set mode as short
2904 * pulse interrupts are used for MST
2906 amdgpu_dm_irq_resume_early(adev);
2908 /* On resume we need to rewrite the MSTM control bits to enable MST*/
2909 s3_handle_mst(ddev, false);
2912 drm_connector_list_iter_begin(ddev, &iter);
2913 drm_for_each_connector_iter(connector, &iter) {
2914 aconnector = to_amdgpu_dm_connector(connector);
2916 if (!aconnector->dc_link)
2920 * this is the case when traversing through already created end sink
2921 * MST connectors, should be skipped
2923 if (aconnector && aconnector->mst_root)
2926 mutex_lock(&aconnector->hpd_lock);
2927 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
2928 DRM_ERROR("KMS: Failed to detect connector\n");
2930 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2931 emulated_link_detect(aconnector->dc_link);
2933 mutex_lock(&dm->dc_lock);
2934 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
2935 mutex_unlock(&dm->dc_lock);
2938 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
2939 aconnector->fake_enable = false;
2941 if (aconnector->dc_sink)
2942 dc_sink_release(aconnector->dc_sink);
2943 aconnector->dc_sink = NULL;
2944 amdgpu_dm_update_connector_after_detect(aconnector);
2945 mutex_unlock(&aconnector->hpd_lock);
2947 drm_connector_list_iter_end(&iter);
2949 /* Force mode set in atomic commit */
2950 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
2951 new_crtc_state->active_changed = true;
2954 * atomic_check is expected to create the dc states. We need to release
2955 * them here, since they were duplicated as part of the suspend
2958 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
2959 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
2960 if (dm_new_crtc_state->stream) {
2961 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
2962 dc_stream_release(dm_new_crtc_state->stream);
2963 dm_new_crtc_state->stream = NULL;
2967 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
2968 dm_new_plane_state = to_dm_plane_state(new_plane_state);
2969 if (dm_new_plane_state->dc_state) {
2970 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
2971 dc_plane_state_release(dm_new_plane_state->dc_state);
2972 dm_new_plane_state->dc_state = NULL;
2976 drm_atomic_helper_resume(ddev, dm->cached_state);
2978 dm->cached_state = NULL;
2980 /* Do mst topology probing after resuming cached state*/
2981 drm_connector_list_iter_begin(ddev, &iter);
2982 drm_for_each_connector_iter(connector, &iter) {
2983 aconnector = to_amdgpu_dm_connector(connector);
2984 if (aconnector->dc_link->type != dc_connection_mst_branch ||
2985 aconnector->mst_root)
2988 ret = drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr, true);
2991 dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2992 aconnector->dc_link);
2993 need_hotplug = true;
2996 drm_connector_list_iter_end(&iter);
2999 drm_kms_helper_hotplug_event(ddev);
3001 amdgpu_dm_irq_resume_late(adev);
3003 amdgpu_dm_smu_write_watermarks_table(adev);
3011 * DM (and consequently DC) is registered in the amdgpu base driver as a IP
3012 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
3013 * the base driver's device list to be initialized and torn down accordingly.
3015 * The functions to do so are provided as hooks in &struct amd_ip_funcs.
3018 static const struct amd_ip_funcs amdgpu_dm_funcs = {
3020 .early_init = dm_early_init,
3021 .late_init = dm_late_init,
3022 .sw_init = dm_sw_init,
3023 .sw_fini = dm_sw_fini,
3024 .early_fini = amdgpu_dm_early_fini,
3025 .hw_init = dm_hw_init,
3026 .hw_fini = dm_hw_fini,
3027 .suspend = dm_suspend,
3028 .resume = dm_resume,
3029 .is_idle = dm_is_idle,
3030 .wait_for_idle = dm_wait_for_idle,
3031 .check_soft_reset = dm_check_soft_reset,
3032 .soft_reset = dm_soft_reset,
3033 .set_clockgating_state = dm_set_clockgating_state,
3034 .set_powergating_state = dm_set_powergating_state,
3037 const struct amdgpu_ip_block_version dm_ip_block = {
3038 .type = AMD_IP_BLOCK_TYPE_DCE,
3042 .funcs = &amdgpu_dm_funcs,
3052 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
3053 .fb_create = amdgpu_display_user_framebuffer_create,
3054 .get_format_info = amdgpu_dm_plane_get_format_info,
3055 .atomic_check = amdgpu_dm_atomic_check,
3056 .atomic_commit = drm_atomic_helper_commit,
3059 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
3060 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail,
3061 .atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
3064 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
3066 struct amdgpu_dm_backlight_caps *caps;
3067 struct drm_connector *conn_base;
3068 struct amdgpu_device *adev;
3069 struct drm_luminance_range_info *luminance_range;
3071 if (aconnector->bl_idx == -1 ||
3072 aconnector->dc_link->connector_signal != SIGNAL_TYPE_EDP)
3075 conn_base = &aconnector->base;
3076 adev = drm_to_adev(conn_base->dev);
3078 caps = &adev->dm.backlight_caps[aconnector->bl_idx];
3079 caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
3080 caps->aux_support = false;
3082 if (caps->ext_caps->bits.oled == 1
3085 * caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
3086 * caps->ext_caps->bits.hdr_aux_backlight_control == 1
3088 caps->aux_support = true;
3090 if (amdgpu_backlight == 0)
3091 caps->aux_support = false;
3092 else if (amdgpu_backlight == 1)
3093 caps->aux_support = true;
3095 luminance_range = &conn_base->display_info.luminance_range;
3097 if (luminance_range->max_luminance) {
3098 caps->aux_min_input_signal = luminance_range->min_luminance;
3099 caps->aux_max_input_signal = luminance_range->max_luminance;
3101 caps->aux_min_input_signal = 0;
3102 caps->aux_max_input_signal = 512;
3106 void amdgpu_dm_update_connector_after_detect(
3107 struct amdgpu_dm_connector *aconnector)
3109 struct drm_connector *connector = &aconnector->base;
3110 struct drm_device *dev = connector->dev;
3111 struct dc_sink *sink;
3113 /* MST handled by drm_mst framework */
3114 if (aconnector->mst_mgr.mst_state == true)
3117 sink = aconnector->dc_link->local_sink;
3119 dc_sink_retain(sink);
3122 * Edid mgmt connector gets first update only in mode_valid hook and then
3123 * the connector sink is set to either fake or physical sink depends on link status.
3124 * Skip if already done during boot.
3126 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
3127 && aconnector->dc_em_sink) {
3130 * For S3 resume with headless use eml_sink to fake stream
3131 * because on resume connector->sink is set to NULL
3133 mutex_lock(&dev->mode_config.mutex);
3136 if (aconnector->dc_sink) {
3137 amdgpu_dm_update_freesync_caps(connector, NULL);
3139 * retain and release below are used to
3140 * bump up refcount for sink because the link doesn't point
3141 * to it anymore after disconnect, so on next crtc to connector
3142 * reshuffle by UMD we will get into unwanted dc_sink release
3144 dc_sink_release(aconnector->dc_sink);
3146 aconnector->dc_sink = sink;
3147 dc_sink_retain(aconnector->dc_sink);
3148 amdgpu_dm_update_freesync_caps(connector,
3151 amdgpu_dm_update_freesync_caps(connector, NULL);
3152 if (!aconnector->dc_sink) {
3153 aconnector->dc_sink = aconnector->dc_em_sink;
3154 dc_sink_retain(aconnector->dc_sink);
3158 mutex_unlock(&dev->mode_config.mutex);
3161 dc_sink_release(sink);
3166 * TODO: temporary guard to look for proper fix
3167 * if this sink is MST sink, we should not do anything
3169 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3170 dc_sink_release(sink);
3174 if (aconnector->dc_sink == sink) {
3176 * We got a DP short pulse (Link Loss, DP CTS, etc...).
3179 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
3180 aconnector->connector_id);
3182 dc_sink_release(sink);
3186 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
3187 aconnector->connector_id, aconnector->dc_sink, sink);
3189 mutex_lock(&dev->mode_config.mutex);
3192 * 1. Update status of the drm connector
3193 * 2. Send an event and let userspace tell us what to do
3197 * TODO: check if we still need the S3 mode update workaround.
3198 * If yes, put it here.
3200 if (aconnector->dc_sink) {
3201 amdgpu_dm_update_freesync_caps(connector, NULL);
3202 dc_sink_release(aconnector->dc_sink);
3205 aconnector->dc_sink = sink;
3206 dc_sink_retain(aconnector->dc_sink);
3207 if (sink->dc_edid.length == 0) {
3208 aconnector->edid = NULL;
3209 if (aconnector->dc_link->aux_mode) {
3210 drm_dp_cec_unset_edid(
3211 &aconnector->dm_dp_aux.aux);
3215 (struct edid *)sink->dc_edid.raw_edid;
3217 if (aconnector->dc_link->aux_mode)
3218 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
3222 if (!aconnector->timing_requested) {
3223 aconnector->timing_requested =
3224 kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL);
3225 if (!aconnector->timing_requested)
3226 dm_error("failed to create aconnector->requested_timing\n");
3229 drm_connector_update_edid_property(connector, aconnector->edid);
3230 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
3231 update_connector_ext_caps(aconnector);
3233 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
3234 amdgpu_dm_update_freesync_caps(connector, NULL);
3235 drm_connector_update_edid_property(connector, NULL);
3236 aconnector->num_modes = 0;
3237 dc_sink_release(aconnector->dc_sink);
3238 aconnector->dc_sink = NULL;
3239 aconnector->edid = NULL;
3240 kfree(aconnector->timing_requested);
3241 aconnector->timing_requested = NULL;
3242 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
3243 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
3244 connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
3247 mutex_unlock(&dev->mode_config.mutex);
3249 update_subconnector_property(aconnector);
3252 dc_sink_release(sink);
3255 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)
3257 struct drm_connector *connector = &aconnector->base;
3258 struct drm_device *dev = connector->dev;
3259 enum dc_connection_type new_connection_type = dc_connection_none;
3260 struct amdgpu_device *adev = drm_to_adev(dev);
3261 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
3264 if (adev->dm.disable_hpd_irq)
3268 * In case of failure or MST no need to update connector status or notify the OS
3269 * since (for MST case) MST does this in its own context.
3271 mutex_lock(&aconnector->hpd_lock);
3273 if (adev->dm.hdcp_workqueue) {
3274 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
3275 dm_con_state->update_hdcp = true;
3277 if (aconnector->fake_enable)
3278 aconnector->fake_enable = false;
3280 aconnector->timing_changed = false;
3282 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
3283 DRM_ERROR("KMS: Failed to detect connector\n");
3285 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3286 emulated_link_detect(aconnector->dc_link);
3288 drm_modeset_lock_all(dev);
3289 dm_restore_drm_connector_state(dev, connector);
3290 drm_modeset_unlock_all(dev);
3292 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3293 drm_kms_helper_connector_hotplug_event(connector);
3295 mutex_lock(&adev->dm.dc_lock);
3296 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3297 mutex_unlock(&adev->dm.dc_lock);
3299 amdgpu_dm_update_connector_after_detect(aconnector);
3301 drm_modeset_lock_all(dev);
3302 dm_restore_drm_connector_state(dev, connector);
3303 drm_modeset_unlock_all(dev);
3305 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3306 drm_kms_helper_connector_hotplug_event(connector);
3309 mutex_unlock(&aconnector->hpd_lock);
3313 static void handle_hpd_irq(void *param)
3315 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3317 handle_hpd_irq_helper(aconnector);
3321 static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq,
3322 union hpd_irq_data hpd_irq_data)
3324 struct hpd_rx_irq_offload_work *offload_work =
3325 kzalloc(sizeof(*offload_work), GFP_KERNEL);
3327 if (!offload_work) {
3328 DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n");
3332 INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work);
3333 offload_work->data = hpd_irq_data;
3334 offload_work->offload_wq = offload_wq;
3336 queue_work(offload_wq->wq, &offload_work->work);
3337 DRM_DEBUG_KMS("queue work to handle hpd_rx offload work");
3340 static void handle_hpd_rx_irq(void *param)
3342 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3343 struct drm_connector *connector = &aconnector->base;
3344 struct drm_device *dev = connector->dev;
3345 struct dc_link *dc_link = aconnector->dc_link;
3346 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
3347 bool result = false;
3348 enum dc_connection_type new_connection_type = dc_connection_none;
3349 struct amdgpu_device *adev = drm_to_adev(dev);
3350 union hpd_irq_data hpd_irq_data;
3351 bool link_loss = false;
3352 bool has_left_work = false;
3353 int idx = dc_link->link_index;
3354 struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx];
3356 memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
3358 if (adev->dm.disable_hpd_irq)
3362 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
3363 * conflict, after implement i2c helper, this mutex should be
3366 mutex_lock(&aconnector->hpd_lock);
3368 result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data,
3369 &link_loss, true, &has_left_work);
3374 if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3375 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3379 if (dc_link_dp_allow_hpd_rx_irq(dc_link)) {
3380 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
3381 hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
3385 * DOWN_REP_MSG_RDY is also handled by polling method
3386 * mgr->cbs->poll_hpd_irq()
3388 spin_lock(&offload_wq->offload_lock);
3389 skip = offload_wq->is_handling_mst_msg_rdy_event;
3392 offload_wq->is_handling_mst_msg_rdy_event = true;
3394 spin_unlock(&offload_wq->offload_lock);
3397 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3405 spin_lock(&offload_wq->offload_lock);
3406 skip = offload_wq->is_handling_link_loss;
3409 offload_wq->is_handling_link_loss = true;
3411 spin_unlock(&offload_wq->offload_lock);
3414 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3421 if (result && !is_mst_root_connector) {
3422 /* Downstream Port status changed. */
3423 if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
3424 DRM_ERROR("KMS: Failed to detect connector\n");
3426 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3427 emulated_link_detect(dc_link);
3429 if (aconnector->fake_enable)
3430 aconnector->fake_enable = false;
3432 amdgpu_dm_update_connector_after_detect(aconnector);
3435 drm_modeset_lock_all(dev);
3436 dm_restore_drm_connector_state(dev, connector);
3437 drm_modeset_unlock_all(dev);
3439 drm_kms_helper_connector_hotplug_event(connector);
3443 mutex_lock(&adev->dm.dc_lock);
3444 ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX);
3445 mutex_unlock(&adev->dm.dc_lock);
3448 if (aconnector->fake_enable)
3449 aconnector->fake_enable = false;
3451 amdgpu_dm_update_connector_after_detect(aconnector);
3453 drm_modeset_lock_all(dev);
3454 dm_restore_drm_connector_state(dev, connector);
3455 drm_modeset_unlock_all(dev);
3457 drm_kms_helper_connector_hotplug_event(connector);
3461 if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
3462 if (adev->dm.hdcp_workqueue)
3463 hdcp_handle_cpirq(adev->dm.hdcp_workqueue, aconnector->base.index);
3466 if (dc_link->type != dc_connection_mst_branch)
3467 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
3469 mutex_unlock(&aconnector->hpd_lock);
3472 static void register_hpd_handlers(struct amdgpu_device *adev)
3474 struct drm_device *dev = adev_to_drm(adev);
3475 struct drm_connector *connector;
3476 struct amdgpu_dm_connector *aconnector;
3477 const struct dc_link *dc_link;
3478 struct dc_interrupt_params int_params = {0};
3480 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3481 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3483 list_for_each_entry(connector,
3484 &dev->mode_config.connector_list, head) {
3486 aconnector = to_amdgpu_dm_connector(connector);
3487 dc_link = aconnector->dc_link;
3489 if (dc_link->irq_source_hpd != DC_IRQ_SOURCE_INVALID) {
3490 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3491 int_params.irq_source = dc_link->irq_source_hpd;
3493 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3495 (void *) aconnector);
3498 if (dc_link->irq_source_hpd_rx != DC_IRQ_SOURCE_INVALID) {
3500 /* Also register for DP short pulse (hpd_rx). */
3501 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3502 int_params.irq_source = dc_link->irq_source_hpd_rx;
3504 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3506 (void *) aconnector);
3509 if (adev->dm.hpd_rx_offload_wq)
3510 adev->dm.hpd_rx_offload_wq[connector->index].aconnector =
3515 #if defined(CONFIG_DRM_AMD_DC_SI)
3516 /* Register IRQ sources and initialize IRQ callbacks */
3517 static int dce60_register_irq_handlers(struct amdgpu_device *adev)
3519 struct dc *dc = adev->dm.dc;
3520 struct common_irq_params *c_irq_params;
3521 struct dc_interrupt_params int_params = {0};
3524 unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3526 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3527 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3530 * Actions of amdgpu_irq_add_id():
3531 * 1. Register a set() function with base driver.
3532 * Base driver will call set() function to enable/disable an
3533 * interrupt in DC hardware.
3534 * 2. Register amdgpu_dm_irq_handler().
3535 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3536 * coming from DC hardware.
3537 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3538 * for acknowledging and handling.
3541 /* Use VBLANK interrupt */
3542 for (i = 0; i < adev->mode_info.num_crtc; i++) {
3543 r = amdgpu_irq_add_id(adev, client_id, i + 1, &adev->crtc_irq);
3545 DRM_ERROR("Failed to add crtc irq id!\n");
3549 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3550 int_params.irq_source =
3551 dc_interrupt_to_irq_source(dc, i + 1, 0);
3553 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3555 c_irq_params->adev = adev;
3556 c_irq_params->irq_src = int_params.irq_source;
3558 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3559 dm_crtc_high_irq, c_irq_params);
3562 /* Use GRPH_PFLIP interrupt */
3563 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3564 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3565 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3567 DRM_ERROR("Failed to add page flip irq id!\n");
3571 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3572 int_params.irq_source =
3573 dc_interrupt_to_irq_source(dc, i, 0);
3575 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3577 c_irq_params->adev = adev;
3578 c_irq_params->irq_src = int_params.irq_source;
3580 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3581 dm_pflip_high_irq, c_irq_params);
3586 r = amdgpu_irq_add_id(adev, client_id,
3587 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3589 DRM_ERROR("Failed to add hpd irq id!\n");
3593 register_hpd_handlers(adev);
3599 /* Register IRQ sources and initialize IRQ callbacks */
3600 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
3602 struct dc *dc = adev->dm.dc;
3603 struct common_irq_params *c_irq_params;
3604 struct dc_interrupt_params int_params = {0};
3607 unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3609 if (adev->family >= AMDGPU_FAMILY_AI)
3610 client_id = SOC15_IH_CLIENTID_DCE;
3612 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3613 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3616 * Actions of amdgpu_irq_add_id():
3617 * 1. Register a set() function with base driver.
3618 * Base driver will call set() function to enable/disable an
3619 * interrupt in DC hardware.
3620 * 2. Register amdgpu_dm_irq_handler().
3621 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3622 * coming from DC hardware.
3623 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3624 * for acknowledging and handling.
3627 /* Use VBLANK interrupt */
3628 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
3629 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
3631 DRM_ERROR("Failed to add crtc irq id!\n");
3635 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3636 int_params.irq_source =
3637 dc_interrupt_to_irq_source(dc, i, 0);
3639 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3641 c_irq_params->adev = adev;
3642 c_irq_params->irq_src = int_params.irq_source;
3644 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3645 dm_crtc_high_irq, c_irq_params);
3648 /* Use VUPDATE interrupt */
3649 for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
3650 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
3652 DRM_ERROR("Failed to add vupdate irq id!\n");
3656 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3657 int_params.irq_source =
3658 dc_interrupt_to_irq_source(dc, i, 0);
3660 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3662 c_irq_params->adev = adev;
3663 c_irq_params->irq_src = int_params.irq_source;
3665 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3666 dm_vupdate_high_irq, c_irq_params);
3669 /* Use GRPH_PFLIP interrupt */
3670 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3671 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3672 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3674 DRM_ERROR("Failed to add page flip irq id!\n");
3678 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3679 int_params.irq_source =
3680 dc_interrupt_to_irq_source(dc, i, 0);
3682 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3684 c_irq_params->adev = adev;
3685 c_irq_params->irq_src = int_params.irq_source;
3687 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3688 dm_pflip_high_irq, c_irq_params);
3693 r = amdgpu_irq_add_id(adev, client_id,
3694 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3696 DRM_ERROR("Failed to add hpd irq id!\n");
3700 register_hpd_handlers(adev);
3705 /* Register IRQ sources and initialize IRQ callbacks */
3706 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
3708 struct dc *dc = adev->dm.dc;
3709 struct common_irq_params *c_irq_params;
3710 struct dc_interrupt_params int_params = {0};
3713 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3714 static const unsigned int vrtl_int_srcid[] = {
3715 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL,
3716 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL,
3717 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL,
3718 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL,
3719 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL,
3720 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL
3724 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3725 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3728 * Actions of amdgpu_irq_add_id():
3729 * 1. Register a set() function with base driver.
3730 * Base driver will call set() function to enable/disable an
3731 * interrupt in DC hardware.
3732 * 2. Register amdgpu_dm_irq_handler().
3733 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3734 * coming from DC hardware.
3735 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3736 * for acknowledging and handling.
3739 /* Use VSTARTUP interrupt */
3740 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
3741 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
3743 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
3746 DRM_ERROR("Failed to add crtc irq id!\n");
3750 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3751 int_params.irq_source =
3752 dc_interrupt_to_irq_source(dc, i, 0);
3754 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3756 c_irq_params->adev = adev;
3757 c_irq_params->irq_src = int_params.irq_source;
3759 amdgpu_dm_irq_register_interrupt(
3760 adev, &int_params, dm_crtc_high_irq, c_irq_params);
3763 /* Use otg vertical line interrupt */
3764 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3765 for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) {
3766 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE,
3767 vrtl_int_srcid[i], &adev->vline0_irq);
3770 DRM_ERROR("Failed to add vline0 irq id!\n");
3774 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3775 int_params.irq_source =
3776 dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0);
3778 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) {
3779 DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]);
3783 c_irq_params = &adev->dm.vline0_params[int_params.irq_source
3784 - DC_IRQ_SOURCE_DC1_VLINE0];
3786 c_irq_params->adev = adev;
3787 c_irq_params->irq_src = int_params.irq_source;
3789 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3790 dm_dcn_vertical_interrupt0_high_irq, c_irq_params);
3794 /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
3795 * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
3796 * to trigger at end of each vblank, regardless of state of the lock,
3797 * matching DCE behaviour.
3799 for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
3800 i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
3802 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
3805 DRM_ERROR("Failed to add vupdate irq id!\n");
3809 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3810 int_params.irq_source =
3811 dc_interrupt_to_irq_source(dc, i, 0);
3813 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3815 c_irq_params->adev = adev;
3816 c_irq_params->irq_src = int_params.irq_source;
3818 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3819 dm_vupdate_high_irq, c_irq_params);
3822 /* Use GRPH_PFLIP interrupt */
3823 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
3824 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1;
3826 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
3828 DRM_ERROR("Failed to add page flip irq id!\n");
3832 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3833 int_params.irq_source =
3834 dc_interrupt_to_irq_source(dc, i, 0);
3836 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3838 c_irq_params->adev = adev;
3839 c_irq_params->irq_src = int_params.irq_source;
3841 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3842 dm_pflip_high_irq, c_irq_params);
3847 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
3850 DRM_ERROR("Failed to add hpd irq id!\n");
3854 register_hpd_handlers(adev);
3858 /* Register Outbox IRQ sources and initialize IRQ callbacks */
3859 static int register_outbox_irq_handlers(struct amdgpu_device *adev)
3861 struct dc *dc = adev->dm.dc;
3862 struct common_irq_params *c_irq_params;
3863 struct dc_interrupt_params int_params = {0};
3866 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3867 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3869 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT,
3870 &adev->dmub_outbox_irq);
3872 DRM_ERROR("Failed to add outbox irq id!\n");
3876 if (dc->ctx->dmub_srv) {
3877 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT;
3878 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3879 int_params.irq_source =
3880 dc_interrupt_to_irq_source(dc, i, 0);
3882 c_irq_params = &adev->dm.dmub_outbox_params[0];
3884 c_irq_params->adev = adev;
3885 c_irq_params->irq_src = int_params.irq_source;
3887 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3888 dm_dmub_outbox1_low_irq, c_irq_params);
3895 * Acquires the lock for the atomic state object and returns
3896 * the new atomic state.
3898 * This should only be called during atomic check.
3900 int dm_atomic_get_state(struct drm_atomic_state *state,
3901 struct dm_atomic_state **dm_state)
3903 struct drm_device *dev = state->dev;
3904 struct amdgpu_device *adev = drm_to_adev(dev);
3905 struct amdgpu_display_manager *dm = &adev->dm;
3906 struct drm_private_state *priv_state;
3911 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
3912 if (IS_ERR(priv_state))
3913 return PTR_ERR(priv_state);
3915 *dm_state = to_dm_atomic_state(priv_state);
3920 static struct dm_atomic_state *
3921 dm_atomic_get_new_state(struct drm_atomic_state *state)
3923 struct drm_device *dev = state->dev;
3924 struct amdgpu_device *adev = drm_to_adev(dev);
3925 struct amdgpu_display_manager *dm = &adev->dm;
3926 struct drm_private_obj *obj;
3927 struct drm_private_state *new_obj_state;
3930 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
3931 if (obj->funcs == dm->atomic_obj.funcs)
3932 return to_dm_atomic_state(new_obj_state);
3938 static struct drm_private_state *
3939 dm_atomic_duplicate_state(struct drm_private_obj *obj)
3941 struct dm_atomic_state *old_state, *new_state;
3943 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
3947 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
3949 old_state = to_dm_atomic_state(obj->state);
3951 if (old_state && old_state->context)
3952 new_state->context = dc_copy_state(old_state->context);
3954 if (!new_state->context) {
3959 return &new_state->base;
3962 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
3963 struct drm_private_state *state)
3965 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
3967 if (dm_state && dm_state->context)
3968 dc_release_state(dm_state->context);
3973 static struct drm_private_state_funcs dm_atomic_state_funcs = {
3974 .atomic_duplicate_state = dm_atomic_duplicate_state,
3975 .atomic_destroy_state = dm_atomic_destroy_state,
3978 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
3980 struct dm_atomic_state *state;
3983 adev->mode_info.mode_config_initialized = true;
3985 adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
3986 adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
3988 adev_to_drm(adev)->mode_config.max_width = 16384;
3989 adev_to_drm(adev)->mode_config.max_height = 16384;
3991 adev_to_drm(adev)->mode_config.preferred_depth = 24;
3992 if (adev->asic_type == CHIP_HAWAII)
3993 /* disable prefer shadow for now due to hibernation issues */
3994 adev_to_drm(adev)->mode_config.prefer_shadow = 0;
3996 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
3997 /* indicates support for immediate flip */
3998 adev_to_drm(adev)->mode_config.async_page_flip = true;
4000 state = kzalloc(sizeof(*state), GFP_KERNEL);
4004 state->context = dc_create_state(adev->dm.dc);
4005 if (!state->context) {
4010 dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
4012 drm_atomic_private_obj_init(adev_to_drm(adev),
4013 &adev->dm.atomic_obj,
4015 &dm_atomic_state_funcs);
4017 r = amdgpu_display_modeset_create_props(adev);
4019 dc_release_state(state->context);
4024 r = amdgpu_dm_audio_init(adev);
4026 dc_release_state(state->context);
4034 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
4035 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
4036 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
4038 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
4041 #if defined(CONFIG_ACPI)
4042 struct amdgpu_dm_backlight_caps caps;
4044 memset(&caps, 0, sizeof(caps));
4046 if (dm->backlight_caps[bl_idx].caps_valid)
4049 amdgpu_acpi_get_backlight_caps(&caps);
4050 if (caps.caps_valid) {
4051 dm->backlight_caps[bl_idx].caps_valid = true;
4052 if (caps.aux_support)
4054 dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal;
4055 dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal;
4057 dm->backlight_caps[bl_idx].min_input_signal =
4058 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4059 dm->backlight_caps[bl_idx].max_input_signal =
4060 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4063 if (dm->backlight_caps[bl_idx].aux_support)
4066 dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4067 dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4071 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
4072 unsigned int *min, unsigned int *max)
4077 if (caps->aux_support) {
4078 // Firmware limits are in nits, DC API wants millinits.
4079 *max = 1000 * caps->aux_max_input_signal;
4080 *min = 1000 * caps->aux_min_input_signal;
4082 // Firmware limits are 8-bit, PWM control is 16-bit.
4083 *max = 0x101 * caps->max_input_signal;
4084 *min = 0x101 * caps->min_input_signal;
4089 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
4090 uint32_t brightness)
4092 unsigned int min, max;
4094 if (!get_brightness_range(caps, &min, &max))
4097 // Rescale 0..255 to min..max
4098 return min + DIV_ROUND_CLOSEST((max - min) * brightness,
4099 AMDGPU_MAX_BL_LEVEL);
4102 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
4103 uint32_t brightness)
4105 unsigned int min, max;
4107 if (!get_brightness_range(caps, &min, &max))
4110 if (brightness < min)
4112 // Rescale min..max to 0..255
4113 return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),
4117 static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
4119 u32 user_brightness)
4121 struct amdgpu_dm_backlight_caps caps;
4122 struct dc_link *link;
4126 amdgpu_dm_update_backlight_caps(dm, bl_idx);
4127 caps = dm->backlight_caps[bl_idx];
4129 dm->brightness[bl_idx] = user_brightness;
4130 /* update scratch register */
4132 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]);
4133 brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]);
4134 link = (struct dc_link *)dm->backlight_link[bl_idx];
4136 /* Change brightness based on AUX property */
4137 if (caps.aux_support) {
4138 rc = dc_link_set_backlight_level_nits(link, true, brightness,
4139 AUX_BL_DEFAULT_TRANSITION_TIME_MS);
4141 DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx);
4143 rc = dc_link_set_backlight_level(link, brightness, 0);
4145 DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx);
4149 dm->actual_brightness[bl_idx] = user_brightness;
4152 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
4154 struct amdgpu_display_manager *dm = bl_get_data(bd);
4157 for (i = 0; i < dm->num_of_edps; i++) {
4158 if (bd == dm->backlight_dev[i])
4161 if (i >= AMDGPU_DM_MAX_NUM_EDP)
4163 amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness);
4168 static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm,
4172 struct amdgpu_dm_backlight_caps caps;
4173 struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx];
4175 amdgpu_dm_update_backlight_caps(dm, bl_idx);
4176 caps = dm->backlight_caps[bl_idx];
4178 if (caps.aux_support) {
4182 rc = dc_link_get_backlight_level_nits(link, &avg, &peak);
4184 return dm->brightness[bl_idx];
4185 return convert_brightness_to_user(&caps, avg);
4188 ret = dc_link_get_backlight_level(link);
4190 if (ret == DC_ERROR_UNEXPECTED)
4191 return dm->brightness[bl_idx];
4193 return convert_brightness_to_user(&caps, ret);
4196 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
4198 struct amdgpu_display_manager *dm = bl_get_data(bd);
4201 for (i = 0; i < dm->num_of_edps; i++) {
4202 if (bd == dm->backlight_dev[i])
4205 if (i >= AMDGPU_DM_MAX_NUM_EDP)
4207 return amdgpu_dm_backlight_get_level(dm, i);
4210 static const struct backlight_ops amdgpu_dm_backlight_ops = {
4211 .options = BL_CORE_SUSPENDRESUME,
4212 .get_brightness = amdgpu_dm_backlight_get_brightness,
4213 .update_status = amdgpu_dm_backlight_update_status,
4217 amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector)
4219 struct drm_device *drm = aconnector->base.dev;
4220 struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm;
4221 struct backlight_properties props = { 0 };
4224 if (aconnector->bl_idx == -1)
4227 if (!acpi_video_backlight_use_native()) {
4228 drm_info(drm, "Skipping amdgpu DM backlight registration\n");
4229 /* Try registering an ACPI video backlight device instead. */
4230 acpi_video_register_backlight();
4234 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
4235 props.brightness = AMDGPU_MAX_BL_LEVEL;
4236 props.type = BACKLIGHT_RAW;
4238 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
4239 drm->primary->index + aconnector->bl_idx);
4241 dm->backlight_dev[aconnector->bl_idx] =
4242 backlight_device_register(bl_name, aconnector->base.kdev, dm,
4243 &amdgpu_dm_backlight_ops, &props);
4245 if (IS_ERR(dm->backlight_dev[aconnector->bl_idx])) {
4246 DRM_ERROR("DM: Backlight registration failed!\n");
4247 dm->backlight_dev[aconnector->bl_idx] = NULL;
4249 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4252 static int initialize_plane(struct amdgpu_display_manager *dm,
4253 struct amdgpu_mode_info *mode_info, int plane_id,
4254 enum drm_plane_type plane_type,
4255 const struct dc_plane_cap *plane_cap)
4257 struct drm_plane *plane;
4258 unsigned long possible_crtcs;
4261 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
4263 DRM_ERROR("KMS: Failed to allocate plane\n");
4266 plane->type = plane_type;
4269 * HACK: IGT tests expect that the primary plane for a CRTC
4270 * can only have one possible CRTC. Only expose support for
4271 * any CRTC if they're not going to be used as a primary plane
4272 * for a CRTC - like overlay or underlay planes.
4274 possible_crtcs = 1 << plane_id;
4275 if (plane_id >= dm->dc->caps.max_streams)
4276 possible_crtcs = 0xff;
4278 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
4281 DRM_ERROR("KMS: Failed to initialize plane\n");
4287 mode_info->planes[plane_id] = plane;
4293 static void setup_backlight_device(struct amdgpu_display_manager *dm,
4294 struct amdgpu_dm_connector *aconnector)
4296 struct dc_link *link = aconnector->dc_link;
4297 int bl_idx = dm->num_of_edps;
4299 if (!(link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) ||
4300 link->type == dc_connection_none)
4303 if (dm->num_of_edps >= AMDGPU_DM_MAX_NUM_EDP) {
4304 drm_warn(adev_to_drm(dm->adev), "Too much eDP connections, skipping backlight setup for additional eDPs\n");
4308 aconnector->bl_idx = bl_idx;
4310 amdgpu_dm_update_backlight_caps(dm, bl_idx);
4311 dm->brightness[bl_idx] = AMDGPU_MAX_BL_LEVEL;
4312 dm->backlight_link[bl_idx] = link;
4315 update_connector_ext_caps(aconnector);
4318 static void amdgpu_set_panel_orientation(struct drm_connector *connector);
4321 * In this architecture, the association
4322 * connector -> encoder -> crtc
4323 * id not really requried. The crtc and connector will hold the
4324 * display_index as an abstraction to use with DAL component
4326 * Returns 0 on success
4328 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4330 struct amdgpu_display_manager *dm = &adev->dm;
4332 struct amdgpu_dm_connector *aconnector = NULL;
4333 struct amdgpu_encoder *aencoder = NULL;
4334 struct amdgpu_mode_info *mode_info = &adev->mode_info;
4337 enum dc_connection_type new_connection_type = dc_connection_none;
4338 const struct dc_plane_cap *plane;
4339 bool psr_feature_enabled = false;
4340 bool replay_feature_enabled = false;
4341 int max_overlay = dm->dc->caps.max_slave_planes;
4343 dm->display_indexes_num = dm->dc->caps.max_streams;
4344 /* Update the actual used number of crtc */
4345 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
4347 amdgpu_dm_set_irq_funcs(adev);
4349 link_cnt = dm->dc->caps.max_links;
4350 if (amdgpu_dm_mode_config_init(dm->adev)) {
4351 DRM_ERROR("DM: Failed to initialize mode config\n");
4355 /* There is one primary plane per CRTC */
4356 primary_planes = dm->dc->caps.max_streams;
4357 ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
4360 * Initialize primary planes, implicit planes for legacy IOCTLS.
4361 * Order is reversed to match iteration order in atomic check.
4363 for (i = (primary_planes - 1); i >= 0; i--) {
4364 plane = &dm->dc->caps.planes[i];
4366 if (initialize_plane(dm, mode_info, i,
4367 DRM_PLANE_TYPE_PRIMARY, plane)) {
4368 DRM_ERROR("KMS: Failed to initialize primary plane\n");
4374 * Initialize overlay planes, index starting after primary planes.
4375 * These planes have a higher DRM index than the primary planes since
4376 * they should be considered as having a higher z-order.
4377 * Order is reversed to match iteration order in atomic check.
4379 * Only support DCN for now, and only expose one so we don't encourage
4380 * userspace to use up all the pipes.
4382 for (i = 0; i < dm->dc->caps.max_planes; ++i) {
4383 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
4385 /* Do not create overlay if MPO disabled */
4386 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO)
4389 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
4392 if (!plane->pixel_format_support.argb8888)
4395 if (max_overlay-- == 0)
4398 if (initialize_plane(dm, NULL, primary_planes + i,
4399 DRM_PLANE_TYPE_OVERLAY, plane)) {
4400 DRM_ERROR("KMS: Failed to initialize overlay plane\n");
4405 for (i = 0; i < dm->dc->caps.max_streams; i++)
4406 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
4407 DRM_ERROR("KMS: Failed to initialize crtc\n");
4411 /* Use Outbox interrupt */
4412 switch (adev->ip_versions[DCE_HWIP][0]) {
4413 case IP_VERSION(3, 0, 0):
4414 case IP_VERSION(3, 1, 2):
4415 case IP_VERSION(3, 1, 3):
4416 case IP_VERSION(3, 1, 4):
4417 case IP_VERSION(3, 1, 5):
4418 case IP_VERSION(3, 1, 6):
4419 case IP_VERSION(3, 2, 0):
4420 case IP_VERSION(3, 2, 1):
4421 case IP_VERSION(2, 1, 0):
4422 if (register_outbox_irq_handlers(dm->adev)) {
4423 DRM_ERROR("DM: Failed to initialize IRQ\n");
4428 DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",
4429 adev->ip_versions[DCE_HWIP][0]);
4432 /* Determine whether to enable PSR support by default. */
4433 if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) {
4434 switch (adev->ip_versions[DCE_HWIP][0]) {
4435 case IP_VERSION(3, 1, 2):
4436 case IP_VERSION(3, 1, 3):
4437 case IP_VERSION(3, 1, 4):
4438 case IP_VERSION(3, 1, 5):
4439 case IP_VERSION(3, 1, 6):
4440 case IP_VERSION(3, 2, 0):
4441 case IP_VERSION(3, 2, 1):
4442 psr_feature_enabled = true;
4445 psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK;
4450 if (!(amdgpu_dc_debug_mask & DC_DISABLE_REPLAY)) {
4451 switch (adev->ip_versions[DCE_HWIP][0]) {
4452 case IP_VERSION(3, 1, 4):
4453 case IP_VERSION(3, 1, 5):
4454 case IP_VERSION(3, 1, 6):
4455 case IP_VERSION(3, 2, 0):
4456 case IP_VERSION(3, 2, 1):
4457 replay_feature_enabled = true;
4460 replay_feature_enabled = amdgpu_dc_feature_mask & DC_REPLAY_MASK;
4464 /* loops over all connectors on the board */
4465 for (i = 0; i < link_cnt; i++) {
4466 struct dc_link *link = NULL;
4468 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
4470 "KMS: Cannot support more than %d display indexes\n",
4471 AMDGPU_DM_MAX_DISPLAY_INDEX);
4475 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
4479 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
4483 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
4484 DRM_ERROR("KMS: Failed to initialize encoder\n");
4488 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
4489 DRM_ERROR("KMS: Failed to initialize connector\n");
4493 link = dc_get_link_at_index(dm->dc, i);
4495 if (!dc_link_detect_connection_type(link, &new_connection_type))
4496 DRM_ERROR("KMS: Failed to detect connector\n");
4498 if (aconnector->base.force && new_connection_type == dc_connection_none) {
4499 emulated_link_detect(link);
4500 amdgpu_dm_update_connector_after_detect(aconnector);
4504 mutex_lock(&dm->dc_lock);
4505 ret = dc_link_detect(link, DETECT_REASON_BOOT);
4506 mutex_unlock(&dm->dc_lock);
4509 amdgpu_dm_update_connector_after_detect(aconnector);
4510 setup_backlight_device(dm, aconnector);
4513 * Disable psr if replay can be enabled
4515 if (replay_feature_enabled && amdgpu_dm_setup_replay(link, aconnector))
4516 psr_feature_enabled = false;
4518 if (psr_feature_enabled)
4519 amdgpu_dm_set_psr_caps(link);
4521 /* TODO: Fix vblank control helpers to delay PSR entry to allow this when
4522 * PSR is also supported.
4524 if (link->psr_settings.psr_feature_enabled)
4525 adev_to_drm(adev)->vblank_disable_immediate = false;
4528 amdgpu_set_panel_orientation(&aconnector->base);
4531 /* Software is initialized. Now we can register interrupt handlers. */
4532 switch (adev->asic_type) {
4533 #if defined(CONFIG_DRM_AMD_DC_SI)
4538 if (dce60_register_irq_handlers(dm->adev)) {
4539 DRM_ERROR("DM: Failed to initialize IRQ\n");
4553 case CHIP_POLARIS11:
4554 case CHIP_POLARIS10:
4555 case CHIP_POLARIS12:
4560 if (dce110_register_irq_handlers(dm->adev)) {
4561 DRM_ERROR("DM: Failed to initialize IRQ\n");
4566 switch (adev->ip_versions[DCE_HWIP][0]) {
4567 case IP_VERSION(1, 0, 0):
4568 case IP_VERSION(1, 0, 1):
4569 case IP_VERSION(2, 0, 2):
4570 case IP_VERSION(2, 0, 3):
4571 case IP_VERSION(2, 0, 0):
4572 case IP_VERSION(2, 1, 0):
4573 case IP_VERSION(3, 0, 0):
4574 case IP_VERSION(3, 0, 2):
4575 case IP_VERSION(3, 0, 3):
4576 case IP_VERSION(3, 0, 1):
4577 case IP_VERSION(3, 1, 2):
4578 case IP_VERSION(3, 1, 3):
4579 case IP_VERSION(3, 1, 4):
4580 case IP_VERSION(3, 1, 5):
4581 case IP_VERSION(3, 1, 6):
4582 case IP_VERSION(3, 2, 0):
4583 case IP_VERSION(3, 2, 1):
4584 if (dcn10_register_irq_handlers(dm->adev)) {
4585 DRM_ERROR("DM: Failed to initialize IRQ\n");
4590 DRM_ERROR("Unsupported DCE IP versions: 0x%X\n",
4591 adev->ip_versions[DCE_HWIP][0]);
4605 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4607 drm_atomic_private_obj_fini(&dm->atomic_obj);
4610 /******************************************************************************
4611 * amdgpu_display_funcs functions
4612 *****************************************************************************/
4615 * dm_bandwidth_update - program display watermarks
4617 * @adev: amdgpu_device pointer
4619 * Calculate and program the display watermarks and line buffer allocation.
4621 static void dm_bandwidth_update(struct amdgpu_device *adev)
4623 /* TODO: implement later */
4626 static const struct amdgpu_display_funcs dm_display_funcs = {
4627 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
4628 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
4629 .backlight_set_level = NULL, /* never called for DC */
4630 .backlight_get_level = NULL, /* never called for DC */
4631 .hpd_sense = NULL,/* called unconditionally */
4632 .hpd_set_polarity = NULL, /* called unconditionally */
4633 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4634 .page_flip_get_scanoutpos =
4635 dm_crtc_get_scanoutpos,/* called unconditionally */
4636 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
4637 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
4640 #if defined(CONFIG_DEBUG_KERNEL_DC)
4642 static ssize_t s3_debug_store(struct device *device,
4643 struct device_attribute *attr,
4649 struct drm_device *drm_dev = dev_get_drvdata(device);
4650 struct amdgpu_device *adev = drm_to_adev(drm_dev);
4652 ret = kstrtoint(buf, 0, &s3_state);
4657 drm_kms_helper_hotplug_event(adev_to_drm(adev));
4662 return ret == 0 ? count : 0;
4665 DEVICE_ATTR_WO(s3_debug);
4669 static int dm_init_microcode(struct amdgpu_device *adev)
4674 switch (adev->ip_versions[DCE_HWIP][0]) {
4675 case IP_VERSION(2, 1, 0):
4676 fw_name_dmub = FIRMWARE_RENOIR_DMUB;
4677 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
4678 fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
4680 case IP_VERSION(3, 0, 0):
4681 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
4682 fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
4684 fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
4686 case IP_VERSION(3, 0, 1):
4687 fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
4689 case IP_VERSION(3, 0, 2):
4690 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
4692 case IP_VERSION(3, 0, 3):
4693 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;
4695 case IP_VERSION(3, 1, 2):
4696 case IP_VERSION(3, 1, 3):
4697 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
4699 case IP_VERSION(3, 1, 4):
4700 fw_name_dmub = FIRMWARE_DCN_314_DMUB;
4702 case IP_VERSION(3, 1, 5):
4703 fw_name_dmub = FIRMWARE_DCN_315_DMUB;
4705 case IP_VERSION(3, 1, 6):
4706 fw_name_dmub = FIRMWARE_DCN316_DMUB;
4708 case IP_VERSION(3, 2, 0):
4709 fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB;
4711 case IP_VERSION(3, 2, 1):
4712 fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB;
4715 /* ASIC doesn't support DMUB. */
4718 r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, fw_name_dmub);
4720 DRM_ERROR("DMUB firmware loading failed: %d\n", r);
4724 static int dm_early_init(void *handle)
4726 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4727 struct amdgpu_mode_info *mode_info = &adev->mode_info;
4728 struct atom_context *ctx = mode_info->atom_context;
4729 int index = GetIndexIntoMasterTable(DATA, Object_Header);
4732 /* if there is no object header, skip DM */
4733 if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
4734 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
4735 dev_info(adev->dev, "No object header, skipping DM\n");
4739 switch (adev->asic_type) {
4740 #if defined(CONFIG_DRM_AMD_DC_SI)
4744 adev->mode_info.num_crtc = 6;
4745 adev->mode_info.num_hpd = 6;
4746 adev->mode_info.num_dig = 6;
4749 adev->mode_info.num_crtc = 2;
4750 adev->mode_info.num_hpd = 2;
4751 adev->mode_info.num_dig = 2;
4756 adev->mode_info.num_crtc = 6;
4757 adev->mode_info.num_hpd = 6;
4758 adev->mode_info.num_dig = 6;
4761 adev->mode_info.num_crtc = 4;
4762 adev->mode_info.num_hpd = 6;
4763 adev->mode_info.num_dig = 7;
4767 adev->mode_info.num_crtc = 2;
4768 adev->mode_info.num_hpd = 6;
4769 adev->mode_info.num_dig = 6;
4773 adev->mode_info.num_crtc = 6;
4774 adev->mode_info.num_hpd = 6;
4775 adev->mode_info.num_dig = 7;
4778 adev->mode_info.num_crtc = 3;
4779 adev->mode_info.num_hpd = 6;
4780 adev->mode_info.num_dig = 9;
4783 adev->mode_info.num_crtc = 2;
4784 adev->mode_info.num_hpd = 6;
4785 adev->mode_info.num_dig = 9;
4787 case CHIP_POLARIS11:
4788 case CHIP_POLARIS12:
4789 adev->mode_info.num_crtc = 5;
4790 adev->mode_info.num_hpd = 5;
4791 adev->mode_info.num_dig = 5;
4793 case CHIP_POLARIS10:
4795 adev->mode_info.num_crtc = 6;
4796 adev->mode_info.num_hpd = 6;
4797 adev->mode_info.num_dig = 6;
4802 adev->mode_info.num_crtc = 6;
4803 adev->mode_info.num_hpd = 6;
4804 adev->mode_info.num_dig = 6;
4808 switch (adev->ip_versions[DCE_HWIP][0]) {
4809 case IP_VERSION(2, 0, 2):
4810 case IP_VERSION(3, 0, 0):
4811 adev->mode_info.num_crtc = 6;
4812 adev->mode_info.num_hpd = 6;
4813 adev->mode_info.num_dig = 6;
4815 case IP_VERSION(2, 0, 0):
4816 case IP_VERSION(3, 0, 2):
4817 adev->mode_info.num_crtc = 5;
4818 adev->mode_info.num_hpd = 5;
4819 adev->mode_info.num_dig = 5;
4821 case IP_VERSION(2, 0, 3):
4822 case IP_VERSION(3, 0, 3):
4823 adev->mode_info.num_crtc = 2;
4824 adev->mode_info.num_hpd = 2;
4825 adev->mode_info.num_dig = 2;
4827 case IP_VERSION(1, 0, 0):
4828 case IP_VERSION(1, 0, 1):
4829 case IP_VERSION(3, 0, 1):
4830 case IP_VERSION(2, 1, 0):
4831 case IP_VERSION(3, 1, 2):
4832 case IP_VERSION(3, 1, 3):
4833 case IP_VERSION(3, 1, 4):
4834 case IP_VERSION(3, 1, 5):
4835 case IP_VERSION(3, 1, 6):
4836 case IP_VERSION(3, 2, 0):
4837 case IP_VERSION(3, 2, 1):
4838 adev->mode_info.num_crtc = 4;
4839 adev->mode_info.num_hpd = 4;
4840 adev->mode_info.num_dig = 4;
4843 DRM_ERROR("Unsupported DCE IP versions: 0x%x\n",
4844 adev->ip_versions[DCE_HWIP][0]);
4850 if (adev->mode_info.funcs == NULL)
4851 adev->mode_info.funcs = &dm_display_funcs;
4854 * Note: Do NOT change adev->audio_endpt_rreg and
4855 * adev->audio_endpt_wreg because they are initialised in
4856 * amdgpu_device_init()
4858 #if defined(CONFIG_DEBUG_KERNEL_DC)
4860 adev_to_drm(adev)->dev,
4861 &dev_attr_s3_debug);
4863 adev->dc_enabled = true;
4865 return dm_init_microcode(adev);
4868 static bool modereset_required(struct drm_crtc_state *crtc_state)
4870 return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
4873 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
4875 drm_encoder_cleanup(encoder);
4879 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
4880 .destroy = amdgpu_dm_encoder_destroy,
4884 fill_plane_color_attributes(const struct drm_plane_state *plane_state,
4885 const enum surface_pixel_format format,
4886 enum dc_color_space *color_space)
4890 *color_space = COLOR_SPACE_SRGB;
4892 /* DRM color properties only affect non-RGB formats. */
4893 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
4896 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
4898 switch (plane_state->color_encoding) {
4899 case DRM_COLOR_YCBCR_BT601:
4901 *color_space = COLOR_SPACE_YCBCR601;
4903 *color_space = COLOR_SPACE_YCBCR601_LIMITED;
4906 case DRM_COLOR_YCBCR_BT709:
4908 *color_space = COLOR_SPACE_YCBCR709;
4910 *color_space = COLOR_SPACE_YCBCR709_LIMITED;
4913 case DRM_COLOR_YCBCR_BT2020:
4915 *color_space = COLOR_SPACE_2020_YCBCR;
4928 fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
4929 const struct drm_plane_state *plane_state,
4930 const u64 tiling_flags,
4931 struct dc_plane_info *plane_info,
4932 struct dc_plane_address *address,
4934 bool force_disable_dcc)
4936 const struct drm_framebuffer *fb = plane_state->fb;
4937 const struct amdgpu_framebuffer *afb =
4938 to_amdgpu_framebuffer(plane_state->fb);
4941 memset(plane_info, 0, sizeof(*plane_info));
4943 switch (fb->format->format) {
4945 plane_info->format =
4946 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
4948 case DRM_FORMAT_RGB565:
4949 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
4951 case DRM_FORMAT_XRGB8888:
4952 case DRM_FORMAT_ARGB8888:
4953 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
4955 case DRM_FORMAT_XRGB2101010:
4956 case DRM_FORMAT_ARGB2101010:
4957 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
4959 case DRM_FORMAT_XBGR2101010:
4960 case DRM_FORMAT_ABGR2101010:
4961 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
4963 case DRM_FORMAT_XBGR8888:
4964 case DRM_FORMAT_ABGR8888:
4965 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
4967 case DRM_FORMAT_NV21:
4968 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
4970 case DRM_FORMAT_NV12:
4971 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
4973 case DRM_FORMAT_P010:
4974 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb;
4976 case DRM_FORMAT_XRGB16161616F:
4977 case DRM_FORMAT_ARGB16161616F:
4978 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F;
4980 case DRM_FORMAT_XBGR16161616F:
4981 case DRM_FORMAT_ABGR16161616F:
4982 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;
4984 case DRM_FORMAT_XRGB16161616:
4985 case DRM_FORMAT_ARGB16161616:
4986 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616;
4988 case DRM_FORMAT_XBGR16161616:
4989 case DRM_FORMAT_ABGR16161616:
4990 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616;
4994 "Unsupported screen format %p4cc\n",
4995 &fb->format->format);
4999 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
5000 case DRM_MODE_ROTATE_0:
5001 plane_info->rotation = ROTATION_ANGLE_0;
5003 case DRM_MODE_ROTATE_90:
5004 plane_info->rotation = ROTATION_ANGLE_90;
5006 case DRM_MODE_ROTATE_180:
5007 plane_info->rotation = ROTATION_ANGLE_180;
5009 case DRM_MODE_ROTATE_270:
5010 plane_info->rotation = ROTATION_ANGLE_270;
5013 plane_info->rotation = ROTATION_ANGLE_0;
5018 plane_info->visible = true;
5019 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
5021 plane_info->layer_index = plane_state->normalized_zpos;
5023 ret = fill_plane_color_attributes(plane_state, plane_info->format,
5024 &plane_info->color_space);
5028 ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format,
5029 plane_info->rotation, tiling_flags,
5030 &plane_info->tiling_info,
5031 &plane_info->plane_size,
5032 &plane_info->dcc, address,
5033 tmz_surface, force_disable_dcc);
5037 amdgpu_dm_plane_fill_blending_from_plane_state(
5038 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha,
5039 &plane_info->global_alpha, &plane_info->global_alpha_value);
5044 static int fill_dc_plane_attributes(struct amdgpu_device *adev,
5045 struct dc_plane_state *dc_plane_state,
5046 struct drm_plane_state *plane_state,
5047 struct drm_crtc_state *crtc_state)
5049 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5050 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb;
5051 struct dc_scaling_info scaling_info;
5052 struct dc_plane_info plane_info;
5054 bool force_disable_dcc = false;
5056 ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info);
5060 dc_plane_state->src_rect = scaling_info.src_rect;
5061 dc_plane_state->dst_rect = scaling_info.dst_rect;
5062 dc_plane_state->clip_rect = scaling_info.clip_rect;
5063 dc_plane_state->scaling_quality = scaling_info.scaling_quality;
5065 force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
5066 ret = fill_dc_plane_info_and_addr(adev, plane_state,
5069 &dc_plane_state->address,
5075 dc_plane_state->format = plane_info.format;
5076 dc_plane_state->color_space = plane_info.color_space;
5077 dc_plane_state->format = plane_info.format;
5078 dc_plane_state->plane_size = plane_info.plane_size;
5079 dc_plane_state->rotation = plane_info.rotation;
5080 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
5081 dc_plane_state->stereo_format = plane_info.stereo_format;
5082 dc_plane_state->tiling_info = plane_info.tiling_info;
5083 dc_plane_state->visible = plane_info.visible;
5084 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
5085 dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha;
5086 dc_plane_state->global_alpha = plane_info.global_alpha;
5087 dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
5088 dc_plane_state->dcc = plane_info.dcc;
5089 dc_plane_state->layer_index = plane_info.layer_index;
5090 dc_plane_state->flip_int_enabled = true;
5093 * Always set input transfer function, since plane state is refreshed
5096 ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
5103 static inline void fill_dc_dirty_rect(struct drm_plane *plane,
5104 struct rect *dirty_rect, int32_t x,
5105 s32 y, s32 width, s32 height,
5108 WARN_ON(*i >= DC_MAX_DIRTY_RECTS);
5112 dirty_rect->width = width;
5113 dirty_rect->height = height;
5117 "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n",
5118 plane->base.id, width, height);
5121 "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)",
5122 plane->base.id, x, y, width, height);
5128 * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates
5130 * @plane: DRM plane containing dirty regions that need to be flushed to the eDP
5132 * @old_plane_state: Old state of @plane
5133 * @new_plane_state: New state of @plane
5134 * @crtc_state: New state of CRTC connected to the @plane
5135 * @flip_addrs: DC flip tracking struct, which also tracts dirty rects
5136 * @dirty_regions_changed: dirty regions changed
5138 * For PSR SU, DC informs the DMUB uController of dirty rectangle regions
5139 * (referred to as "damage clips" in DRM nomenclature) that require updating on
5140 * the eDP remote buffer. The responsibility of specifying the dirty regions is
5143 * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the
5144 * plane with regions that require flushing to the eDP remote buffer. In
5145 * addition, certain use cases - such as cursor and multi-plane overlay (MPO) -
5146 * implicitly provide damage clips without any client support via the plane
5149 static void fill_dc_dirty_rects(struct drm_plane *plane,
5150 struct drm_plane_state *old_plane_state,
5151 struct drm_plane_state *new_plane_state,
5152 struct drm_crtc_state *crtc_state,
5153 struct dc_flip_addrs *flip_addrs,
5154 bool *dirty_regions_changed)
5156 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5157 struct rect *dirty_rects = flip_addrs->dirty_rects;
5159 struct drm_mode_rect *clips;
5163 *dirty_regions_changed = false;
5166 * Cursor plane has it's own dirty rect update interface. See
5167 * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data
5169 if (plane->type == DRM_PLANE_TYPE_CURSOR)
5172 num_clips = drm_plane_get_damage_clips_count(new_plane_state);
5173 clips = drm_plane_get_damage_clips(new_plane_state);
5175 if (!dm_crtc_state->mpo_requested) {
5176 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS)
5179 for (; flip_addrs->dirty_rect_count < num_clips; clips++)
5180 fill_dc_dirty_rect(new_plane_state->plane,
5181 &dirty_rects[flip_addrs->dirty_rect_count],
5182 clips->x1, clips->y1,
5183 clips->x2 - clips->x1, clips->y2 - clips->y1,
5184 &flip_addrs->dirty_rect_count,
5190 * MPO is requested. Add entire plane bounding box to dirty rects if
5191 * flipped to or damaged.
5193 * If plane is moved or resized, also add old bounding box to dirty
5196 fb_changed = old_plane_state->fb->base.id !=
5197 new_plane_state->fb->base.id;
5198 bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x ||
5199 old_plane_state->crtc_y != new_plane_state->crtc_y ||
5200 old_plane_state->crtc_w != new_plane_state->crtc_w ||
5201 old_plane_state->crtc_h != new_plane_state->crtc_h);
5204 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n",
5205 new_plane_state->plane->base.id,
5206 bb_changed, fb_changed, num_clips);
5208 *dirty_regions_changed = bb_changed;
5210 if ((num_clips + (bb_changed ? 2 : 0)) > DC_MAX_DIRTY_RECTS)
5214 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5215 new_plane_state->crtc_x,
5216 new_plane_state->crtc_y,
5217 new_plane_state->crtc_w,
5218 new_plane_state->crtc_h, &i, false);
5220 /* Add old plane bounding-box if plane is moved or resized */
5221 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5222 old_plane_state->crtc_x,
5223 old_plane_state->crtc_y,
5224 old_plane_state->crtc_w,
5225 old_plane_state->crtc_h, &i, false);
5229 for (; i < num_clips; clips++)
5230 fill_dc_dirty_rect(new_plane_state->plane,
5231 &dirty_rects[i], clips->x1,
5232 clips->y1, clips->x2 - clips->x1,
5233 clips->y2 - clips->y1, &i, false);
5234 } else if (fb_changed && !bb_changed) {
5235 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5236 new_plane_state->crtc_x,
5237 new_plane_state->crtc_y,
5238 new_plane_state->crtc_w,
5239 new_plane_state->crtc_h, &i, false);
5242 flip_addrs->dirty_rect_count = i;
5246 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0,
5247 dm_crtc_state->base.mode.crtc_hdisplay,
5248 dm_crtc_state->base.mode.crtc_vdisplay,
5249 &flip_addrs->dirty_rect_count, true);
5252 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
5253 const struct dm_connector_state *dm_state,
5254 struct dc_stream_state *stream)
5256 enum amdgpu_rmx_type rmx_type;
5258 struct rect src = { 0 }; /* viewport in composition space*/
5259 struct rect dst = { 0 }; /* stream addressable area */
5261 /* no mode. nothing to be done */
5265 /* Full screen scaling by default */
5266 src.width = mode->hdisplay;
5267 src.height = mode->vdisplay;
5268 dst.width = stream->timing.h_addressable;
5269 dst.height = stream->timing.v_addressable;
5272 rmx_type = dm_state->scaling;
5273 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
5274 if (src.width * dst.height <
5275 src.height * dst.width) {
5276 /* height needs less upscaling/more downscaling */
5277 dst.width = src.width *
5278 dst.height / src.height;
5280 /* width needs less upscaling/more downscaling */
5281 dst.height = src.height *
5282 dst.width / src.width;
5284 } else if (rmx_type == RMX_CENTER) {
5288 dst.x = (stream->timing.h_addressable - dst.width) / 2;
5289 dst.y = (stream->timing.v_addressable - dst.height) / 2;
5291 if (dm_state->underscan_enable) {
5292 dst.x += dm_state->underscan_hborder / 2;
5293 dst.y += dm_state->underscan_vborder / 2;
5294 dst.width -= dm_state->underscan_hborder;
5295 dst.height -= dm_state->underscan_vborder;
5302 DRM_DEBUG_KMS("Destination Rectangle x:%d y:%d width:%d height:%d\n",
5303 dst.x, dst.y, dst.width, dst.height);
5307 static enum dc_color_depth
5308 convert_color_depth_from_display_info(const struct drm_connector *connector,
5309 bool is_y420, int requested_bpc)
5316 /* Cap display bpc based on HDMI 2.0 HF-VSDB */
5317 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)
5319 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
5321 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
5324 bpc = (uint8_t)connector->display_info.bpc;
5325 /* Assume 8 bpc by default if no bpc is specified. */
5326 bpc = bpc ? bpc : 8;
5329 if (requested_bpc > 0) {
5331 * Cap display bpc based on the user requested value.
5333 * The value for state->max_bpc may not correctly updated
5334 * depending on when the connector gets added to the state
5335 * or if this was called outside of atomic check, so it
5336 * can't be used directly.
5338 bpc = min_t(u8, bpc, requested_bpc);
5340 /* Round down to the nearest even number. */
5341 bpc = bpc - (bpc & 1);
5347 * Temporary Work around, DRM doesn't parse color depth for
5348 * EDID revision before 1.4
5349 * TODO: Fix edid parsing
5351 return COLOR_DEPTH_888;
5353 return COLOR_DEPTH_666;
5355 return COLOR_DEPTH_888;
5357 return COLOR_DEPTH_101010;
5359 return COLOR_DEPTH_121212;
5361 return COLOR_DEPTH_141414;
5363 return COLOR_DEPTH_161616;
5365 return COLOR_DEPTH_UNDEFINED;
5369 static enum dc_aspect_ratio
5370 get_aspect_ratio(const struct drm_display_mode *mode_in)
5372 /* 1-1 mapping, since both enums follow the HDMI spec. */
5373 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
5376 static enum dc_color_space
5377 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing,
5378 const struct drm_connector_state *connector_state)
5380 enum dc_color_space color_space = COLOR_SPACE_SRGB;
5382 switch (connector_state->colorspace) {
5383 case DRM_MODE_COLORIMETRY_BT601_YCC:
5384 if (dc_crtc_timing->flags.Y_ONLY)
5385 color_space = COLOR_SPACE_YCBCR601_LIMITED;
5387 color_space = COLOR_SPACE_YCBCR601;
5389 case DRM_MODE_COLORIMETRY_BT709_YCC:
5390 if (dc_crtc_timing->flags.Y_ONLY)
5391 color_space = COLOR_SPACE_YCBCR709_LIMITED;
5393 color_space = COLOR_SPACE_YCBCR709;
5395 case DRM_MODE_COLORIMETRY_OPRGB:
5396 color_space = COLOR_SPACE_ADOBERGB;
5398 case DRM_MODE_COLORIMETRY_BT2020_RGB:
5399 case DRM_MODE_COLORIMETRY_BT2020_YCC:
5400 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB)
5401 color_space = COLOR_SPACE_2020_RGB_FULLRANGE;
5403 color_space = COLOR_SPACE_2020_YCBCR;
5405 case DRM_MODE_COLORIMETRY_DEFAULT: // ITU601
5407 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) {
5408 color_space = COLOR_SPACE_SRGB;
5410 * 27030khz is the separation point between HDTV and SDTV
5411 * according to HDMI spec, we use YCbCr709 and YCbCr601
5414 } else if (dc_crtc_timing->pix_clk_100hz > 270300) {
5415 if (dc_crtc_timing->flags.Y_ONLY)
5417 COLOR_SPACE_YCBCR709_LIMITED;
5419 color_space = COLOR_SPACE_YCBCR709;
5421 if (dc_crtc_timing->flags.Y_ONLY)
5423 COLOR_SPACE_YCBCR601_LIMITED;
5425 color_space = COLOR_SPACE_YCBCR601;
5433 static bool adjust_colour_depth_from_display_info(
5434 struct dc_crtc_timing *timing_out,
5435 const struct drm_display_info *info)
5437 enum dc_color_depth depth = timing_out->display_color_depth;
5441 normalized_clk = timing_out->pix_clk_100hz / 10;
5442 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
5443 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
5444 normalized_clk /= 2;
5445 /* Adjusting pix clock following on HDMI spec based on colour depth */
5447 case COLOR_DEPTH_888:
5449 case COLOR_DEPTH_101010:
5450 normalized_clk = (normalized_clk * 30) / 24;
5452 case COLOR_DEPTH_121212:
5453 normalized_clk = (normalized_clk * 36) / 24;
5455 case COLOR_DEPTH_161616:
5456 normalized_clk = (normalized_clk * 48) / 24;
5459 /* The above depths are the only ones valid for HDMI. */
5462 if (normalized_clk <= info->max_tmds_clock) {
5463 timing_out->display_color_depth = depth;
5466 } while (--depth > COLOR_DEPTH_666);
5470 static void fill_stream_properties_from_drm_display_mode(
5471 struct dc_stream_state *stream,
5472 const struct drm_display_mode *mode_in,
5473 const struct drm_connector *connector,
5474 const struct drm_connector_state *connector_state,
5475 const struct dc_stream_state *old_stream,
5478 struct dc_crtc_timing *timing_out = &stream->timing;
5479 const struct drm_display_info *info = &connector->display_info;
5480 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5481 struct hdmi_vendor_infoframe hv_frame;
5482 struct hdmi_avi_infoframe avi_frame;
5484 memset(&hv_frame, 0, sizeof(hv_frame));
5485 memset(&avi_frame, 0, sizeof(avi_frame));
5487 timing_out->h_border_left = 0;
5488 timing_out->h_border_right = 0;
5489 timing_out->v_border_top = 0;
5490 timing_out->v_border_bottom = 0;
5491 /* TODO: un-hardcode */
5492 if (drm_mode_is_420_only(info, mode_in)
5493 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5494 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5495 else if (drm_mode_is_420_also(info, mode_in)
5496 && aconnector->force_yuv420_output)
5497 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5498 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444)
5499 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5500 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
5502 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
5504 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
5505 timing_out->display_color_depth = convert_color_depth_from_display_info(
5507 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420),
5509 timing_out->scan_type = SCANNING_TYPE_NODATA;
5510 timing_out->hdmi_vic = 0;
5513 timing_out->vic = old_stream->timing.vic;
5514 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
5515 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
5517 timing_out->vic = drm_match_cea_mode(mode_in);
5518 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
5519 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
5520 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
5521 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
5524 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5525 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
5526 timing_out->vic = avi_frame.video_code;
5527 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
5528 timing_out->hdmi_vic = hv_frame.vic;
5531 if (is_freesync_video_mode(mode_in, aconnector)) {
5532 timing_out->h_addressable = mode_in->hdisplay;
5533 timing_out->h_total = mode_in->htotal;
5534 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start;
5535 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay;
5536 timing_out->v_total = mode_in->vtotal;
5537 timing_out->v_addressable = mode_in->vdisplay;
5538 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay;
5539 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start;
5540 timing_out->pix_clk_100hz = mode_in->clock * 10;
5542 timing_out->h_addressable = mode_in->crtc_hdisplay;
5543 timing_out->h_total = mode_in->crtc_htotal;
5544 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
5545 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
5546 timing_out->v_total = mode_in->crtc_vtotal;
5547 timing_out->v_addressable = mode_in->crtc_vdisplay;
5548 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
5549 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
5550 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
5553 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
5555 stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
5556 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
5557 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5558 if (!adjust_colour_depth_from_display_info(timing_out, info) &&
5559 drm_mode_is_420_also(info, mode_in) &&
5560 timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
5561 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5562 adjust_colour_depth_from_display_info(timing_out, info);
5566 stream->output_color_space = get_output_color_space(timing_out, connector_state);
5569 static void fill_audio_info(struct audio_info *audio_info,
5570 const struct drm_connector *drm_connector,
5571 const struct dc_sink *dc_sink)
5574 int cea_revision = 0;
5575 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
5577 audio_info->manufacture_id = edid_caps->manufacturer_id;
5578 audio_info->product_id = edid_caps->product_id;
5580 cea_revision = drm_connector->display_info.cea_rev;
5582 strscpy(audio_info->display_name,
5583 edid_caps->display_name,
5584 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
5586 if (cea_revision >= 3) {
5587 audio_info->mode_count = edid_caps->audio_mode_count;
5589 for (i = 0; i < audio_info->mode_count; ++i) {
5590 audio_info->modes[i].format_code =
5591 (enum audio_format_code)
5592 (edid_caps->audio_modes[i].format_code);
5593 audio_info->modes[i].channel_count =
5594 edid_caps->audio_modes[i].channel_count;
5595 audio_info->modes[i].sample_rates.all =
5596 edid_caps->audio_modes[i].sample_rate;
5597 audio_info->modes[i].sample_size =
5598 edid_caps->audio_modes[i].sample_size;
5602 audio_info->flags.all = edid_caps->speaker_flags;
5604 /* TODO: We only check for the progressive mode, check for interlace mode too */
5605 if (drm_connector->latency_present[0]) {
5606 audio_info->video_latency = drm_connector->video_latency[0];
5607 audio_info->audio_latency = drm_connector->audio_latency[0];
5610 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
5615 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
5616 struct drm_display_mode *dst_mode)
5618 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
5619 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
5620 dst_mode->crtc_clock = src_mode->crtc_clock;
5621 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
5622 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
5623 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
5624 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
5625 dst_mode->crtc_htotal = src_mode->crtc_htotal;
5626 dst_mode->crtc_hskew = src_mode->crtc_hskew;
5627 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
5628 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
5629 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
5630 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
5631 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
5635 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
5636 const struct drm_display_mode *native_mode,
5639 if (scale_enabled) {
5640 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5641 } else if (native_mode->clock == drm_mode->clock &&
5642 native_mode->htotal == drm_mode->htotal &&
5643 native_mode->vtotal == drm_mode->vtotal) {
5644 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5646 /* no scaling nor amdgpu inserted, no need to patch */
5650 static struct dc_sink *
5651 create_fake_sink(struct amdgpu_dm_connector *aconnector)
5653 struct dc_sink_init_data sink_init_data = { 0 };
5654 struct dc_sink *sink = NULL;
5656 sink_init_data.link = aconnector->dc_link;
5657 sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
5659 sink = dc_sink_create(&sink_init_data);
5661 DRM_ERROR("Failed to create sink!\n");
5664 sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
5669 static void set_multisync_trigger_params(
5670 struct dc_stream_state *stream)
5672 struct dc_stream_state *master = NULL;
5674 if (stream->triggered_crtc_reset.enabled) {
5675 master = stream->triggered_crtc_reset.event_source;
5676 stream->triggered_crtc_reset.event =
5677 master->timing.flags.VSYNC_POSITIVE_POLARITY ?
5678 CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING;
5679 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL;
5683 static void set_master_stream(struct dc_stream_state *stream_set[],
5686 int j, highest_rfr = 0, master_stream = 0;
5688 for (j = 0; j < stream_count; j++) {
5689 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
5690 int refresh_rate = 0;
5692 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
5693 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
5694 if (refresh_rate > highest_rfr) {
5695 highest_rfr = refresh_rate;
5700 for (j = 0; j < stream_count; j++) {
5702 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
5706 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
5709 struct dc_stream_state *stream;
5711 if (context->stream_count < 2)
5713 for (i = 0; i < context->stream_count ; i++) {
5714 if (!context->streams[i])
5717 * TODO: add a function to read AMD VSDB bits and set
5718 * crtc_sync_master.multi_sync_enabled flag
5719 * For now it's set to false
5723 set_master_stream(context->streams, context->stream_count);
5725 for (i = 0; i < context->stream_count ; i++) {
5726 stream = context->streams[i];
5731 set_multisync_trigger_params(stream);
5736 * DOC: FreeSync Video
5738 * When a userspace application wants to play a video, the content follows a
5739 * standard format definition that usually specifies the FPS for that format.
5740 * The below list illustrates some video format and the expected FPS,
5743 * - TV/NTSC (23.976 FPS)
5746 * - TV/NTSC (29.97 FPS)
5747 * - TV/NTSC (30 FPS)
5748 * - Cinema HFR (48 FPS)
5750 * - Commonly used (60 FPS)
5751 * - Multiples of 24 (48,72,96 FPS)
5753 * The list of standards video format is not huge and can be added to the
5754 * connector modeset list beforehand. With that, userspace can leverage
5755 * FreeSync to extends the front porch in order to attain the target refresh
5756 * rate. Such a switch will happen seamlessly, without screen blanking or
5757 * reprogramming of the output in any other way. If the userspace requests a
5758 * modesetting change compatible with FreeSync modes that only differ in the
5759 * refresh rate, DC will skip the full update and avoid blink during the
5760 * transition. For example, the video player can change the modesetting from
5761 * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without
5762 * causing any display blink. This same concept can be applied to a mode
5765 static struct drm_display_mode *
5766 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
5767 bool use_probed_modes)
5769 struct drm_display_mode *m, *m_pref = NULL;
5770 u16 current_refresh, highest_refresh;
5771 struct list_head *list_head = use_probed_modes ?
5772 &aconnector->base.probed_modes :
5773 &aconnector->base.modes;
5775 if (aconnector->freesync_vid_base.clock != 0)
5776 return &aconnector->freesync_vid_base;
5778 /* Find the preferred mode */
5779 list_for_each_entry(m, list_head, head) {
5780 if (m->type & DRM_MODE_TYPE_PREFERRED) {
5787 /* Probably an EDID with no preferred mode. Fallback to first entry */
5788 m_pref = list_first_entry_or_null(
5789 &aconnector->base.modes, struct drm_display_mode, head);
5791 DRM_DEBUG_DRIVER("No preferred mode found in EDID\n");
5796 highest_refresh = drm_mode_vrefresh(m_pref);
5799 * Find the mode with highest refresh rate with same resolution.
5800 * For some monitors, preferred mode is not the mode with highest
5801 * supported refresh rate.
5803 list_for_each_entry(m, list_head, head) {
5804 current_refresh = drm_mode_vrefresh(m);
5806 if (m->hdisplay == m_pref->hdisplay &&
5807 m->vdisplay == m_pref->vdisplay &&
5808 highest_refresh < current_refresh) {
5809 highest_refresh = current_refresh;
5814 drm_mode_copy(&aconnector->freesync_vid_base, m_pref);
5818 static bool is_freesync_video_mode(const struct drm_display_mode *mode,
5819 struct amdgpu_dm_connector *aconnector)
5821 struct drm_display_mode *high_mode;
5824 high_mode = get_highest_refresh_rate_mode(aconnector, false);
5825 if (!high_mode || !mode)
5828 timing_diff = high_mode->vtotal - mode->vtotal;
5830 if (high_mode->clock == 0 || high_mode->clock != mode->clock ||
5831 high_mode->hdisplay != mode->hdisplay ||
5832 high_mode->vdisplay != mode->vdisplay ||
5833 high_mode->hsync_start != mode->hsync_start ||
5834 high_mode->hsync_end != mode->hsync_end ||
5835 high_mode->htotal != mode->htotal ||
5836 high_mode->hskew != mode->hskew ||
5837 high_mode->vscan != mode->vscan ||
5838 high_mode->vsync_start - mode->vsync_start != timing_diff ||
5839 high_mode->vsync_end - mode->vsync_end != timing_diff)
5845 static void update_dsc_caps(struct amdgpu_dm_connector *aconnector,
5846 struct dc_sink *sink, struct dc_stream_state *stream,
5847 struct dsc_dec_dpcd_caps *dsc_caps)
5849 stream->timing.flags.DSC = 0;
5850 dsc_caps->is_dsc_supported = false;
5852 if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
5853 sink->sink_signal == SIGNAL_TYPE_EDP)) {
5854 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE ||
5855 sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
5856 dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
5857 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
5858 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
5864 static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
5865 struct dc_sink *sink, struct dc_stream_state *stream,
5866 struct dsc_dec_dpcd_caps *dsc_caps,
5867 uint32_t max_dsc_target_bpp_limit_override)
5869 const struct dc_link_settings *verified_link_cap = NULL;
5870 u32 link_bw_in_kbps;
5871 u32 edp_min_bpp_x16, edp_max_bpp_x16;
5872 struct dc *dc = sink->ctx->dc;
5873 struct dc_dsc_bw_range bw_range = {0};
5874 struct dc_dsc_config dsc_cfg = {0};
5875 struct dc_dsc_config_options dsc_options = {0};
5877 dc_dsc_get_default_config_option(dc, &dsc_options);
5878 dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5880 verified_link_cap = dc_link_get_link_cap(stream->link);
5881 link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap);
5882 edp_min_bpp_x16 = 8 * 16;
5883 edp_max_bpp_x16 = 8 * 16;
5885 if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel)
5886 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel;
5888 if (edp_max_bpp_x16 < edp_min_bpp_x16)
5889 edp_min_bpp_x16 = edp_max_bpp_x16;
5891 if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0],
5892 dc->debug.dsc_min_slice_height_override,
5893 edp_min_bpp_x16, edp_max_bpp_x16,
5896 dc_link_get_highest_encoding_format(aconnector->dc_link),
5899 if (bw_range.max_kbps < link_bw_in_kbps) {
5900 if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5905 dc_link_get_highest_encoding_format(aconnector->dc_link),
5907 stream->timing.dsc_cfg = dsc_cfg;
5908 stream->timing.flags.DSC = 1;
5909 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16;
5915 if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5920 dc_link_get_highest_encoding_format(aconnector->dc_link),
5922 stream->timing.dsc_cfg = dsc_cfg;
5923 stream->timing.flags.DSC = 1;
5928 static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
5929 struct dc_sink *sink, struct dc_stream_state *stream,
5930 struct dsc_dec_dpcd_caps *dsc_caps)
5932 struct drm_connector *drm_connector = &aconnector->base;
5933 u32 link_bandwidth_kbps;
5934 struct dc *dc = sink->ctx->dc;
5935 u32 max_supported_bw_in_kbps, timing_bw_in_kbps;
5936 u32 dsc_max_supported_bw_in_kbps;
5937 u32 max_dsc_target_bpp_limit_override =
5938 drm_connector->display_info.max_dsc_bpp;
5939 struct dc_dsc_config_options dsc_options = {0};
5941 dc_dsc_get_default_config_option(dc, &dsc_options);
5942 dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5944 link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
5945 dc_link_get_link_cap(aconnector->dc_link));
5947 /* Set DSC policy according to dsc_clock_en */
5948 dc_dsc_policy_set_enable_dsc_when_not_needed(
5949 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);
5951 if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP &&
5952 !aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&
5953 dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
5955 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);
5957 } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
5958 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
5959 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5962 link_bandwidth_kbps,
5964 dc_link_get_highest_encoding_format(aconnector->dc_link),
5965 &stream->timing.dsc_cfg)) {
5966 stream->timing.flags.DSC = 1;
5967 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name);
5969 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
5970 timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing,
5971 dc_link_get_highest_encoding_format(aconnector->dc_link));
5972 max_supported_bw_in_kbps = link_bandwidth_kbps;
5973 dsc_max_supported_bw_in_kbps = link_bandwidth_kbps;
5975 if (timing_bw_in_kbps > max_supported_bw_in_kbps &&
5976 max_supported_bw_in_kbps > 0 &&
5977 dsc_max_supported_bw_in_kbps > 0)
5978 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5981 dsc_max_supported_bw_in_kbps,
5983 dc_link_get_highest_encoding_format(aconnector->dc_link),
5984 &stream->timing.dsc_cfg)) {
5985 stream->timing.flags.DSC = 1;
5986 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n",
5987 __func__, drm_connector->name);
5992 /* Overwrite the stream flag if DSC is enabled through debugfs */
5993 if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
5994 stream->timing.flags.DSC = 1;
5996 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
5997 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
5999 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
6000 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
6002 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
6003 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
6006 static struct dc_stream_state *
6007 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6008 const struct drm_display_mode *drm_mode,
6009 const struct dm_connector_state *dm_state,
6010 const struct dc_stream_state *old_stream,
6013 struct drm_display_mode *preferred_mode = NULL;
6014 struct drm_connector *drm_connector;
6015 const struct drm_connector_state *con_state = &dm_state->base;
6016 struct dc_stream_state *stream = NULL;
6017 struct drm_display_mode mode;
6018 struct drm_display_mode saved_mode;
6019 struct drm_display_mode *freesync_mode = NULL;
6020 bool native_mode_found = false;
6021 bool recalculate_timing = false;
6022 bool scale = dm_state->scaling != RMX_OFF;
6024 int preferred_refresh = 0;
6025 enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN;
6026 struct dsc_dec_dpcd_caps dsc_caps;
6028 struct dc_sink *sink = NULL;
6030 drm_mode_init(&mode, drm_mode);
6031 memset(&saved_mode, 0, sizeof(saved_mode));
6033 if (aconnector == NULL) {
6034 DRM_ERROR("aconnector is NULL!\n");
6038 drm_connector = &aconnector->base;
6040 if (!aconnector->dc_sink) {
6041 sink = create_fake_sink(aconnector);
6045 sink = aconnector->dc_sink;
6046 dc_sink_retain(sink);
6049 stream = dc_create_stream_for_sink(sink);
6051 if (stream == NULL) {
6052 DRM_ERROR("Failed to create stream for sink!\n");
6056 stream->dm_stream_context = aconnector;
6058 stream->timing.flags.LTE_340MCSC_SCRAMBLE =
6059 drm_connector->display_info.hdmi.scdc.scrambling.low_rates;
6061 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
6062 /* Search for preferred mode */
6063 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
6064 native_mode_found = true;
6068 if (!native_mode_found)
6069 preferred_mode = list_first_entry_or_null(
6070 &aconnector->base.modes,
6071 struct drm_display_mode,
6074 mode_refresh = drm_mode_vrefresh(&mode);
6076 if (preferred_mode == NULL) {
6078 * This may not be an error, the use case is when we have no
6079 * usermode calls to reset and set mode upon hotplug. In this
6080 * case, we call set mode ourselves to restore the previous mode
6081 * and the modelist may not be filled in time.
6083 DRM_DEBUG_DRIVER("No preferred mode found\n");
6085 recalculate_timing = is_freesync_video_mode(&mode, aconnector);
6086 if (recalculate_timing) {
6087 freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
6088 drm_mode_copy(&saved_mode, &mode);
6089 drm_mode_copy(&mode, freesync_mode);
6091 decide_crtc_timing_for_drm_display_mode(
6092 &mode, preferred_mode, scale);
6094 preferred_refresh = drm_mode_vrefresh(preferred_mode);
6098 if (recalculate_timing)
6099 drm_mode_set_crtcinfo(&saved_mode, 0);
6102 * If scaling is enabled and refresh rate didn't change
6103 * we copy the vic and polarities of the old timings
6105 if (!scale || mode_refresh != preferred_refresh)
6106 fill_stream_properties_from_drm_display_mode(
6107 stream, &mode, &aconnector->base, con_state, NULL,
6110 fill_stream_properties_from_drm_display_mode(
6111 stream, &mode, &aconnector->base, con_state, old_stream,
6114 if (aconnector->timing_changed) {
6115 DC_LOG_DEBUG("%s: overriding timing for automated test, bpc %d, changing to %d\n",
6117 stream->timing.display_color_depth,
6118 aconnector->timing_requested->display_color_depth);
6119 stream->timing = *aconnector->timing_requested;
6122 /* SST DSC determination policy */
6123 update_dsc_caps(aconnector, sink, stream, &dsc_caps);
6124 if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported)
6125 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps);
6127 update_stream_scaling_settings(&mode, dm_state, stream);
6130 &stream->audio_info,
6134 update_stream_signal(stream, sink);
6136 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
6137 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);
6139 if (stream->link->psr_settings.psr_feature_enabled || stream->link->replay_settings.replay_feature_enabled) {
6141 // should decide stream support vsc sdp colorimetry capability
6142 // before building vsc info packet
6144 stream->use_vsc_sdp_for_colorimetry = false;
6145 if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
6146 stream->use_vsc_sdp_for_colorimetry =
6147 aconnector->dc_sink->is_vsc_sdp_colorimetry_supported;
6149 if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
6150 stream->use_vsc_sdp_for_colorimetry = true;
6152 if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22)
6153 tf = TRANSFER_FUNC_GAMMA_22;
6154 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);
6155 aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
6159 dc_sink_release(sink);
6164 static enum drm_connector_status
6165 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
6168 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6172 * 1. This interface is NOT called in context of HPD irq.
6173 * 2. This interface *is called* in context of user-mode ioctl. Which
6174 * makes it a bad place for *any* MST-related activity.
6177 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
6178 !aconnector->fake_enable)
6179 connected = (aconnector->dc_sink != NULL);
6181 connected = (aconnector->base.force == DRM_FORCE_ON ||
6182 aconnector->base.force == DRM_FORCE_ON_DIGITAL);
6184 update_subconnector_property(aconnector);
6186 return (connected ? connector_status_connected :
6187 connector_status_disconnected);
6190 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
6191 struct drm_connector_state *connector_state,
6192 struct drm_property *property,
6195 struct drm_device *dev = connector->dev;
6196 struct amdgpu_device *adev = drm_to_adev(dev);
6197 struct dm_connector_state *dm_old_state =
6198 to_dm_connector_state(connector->state);
6199 struct dm_connector_state *dm_new_state =
6200 to_dm_connector_state(connector_state);
6204 if (property == dev->mode_config.scaling_mode_property) {
6205 enum amdgpu_rmx_type rmx_type;
6208 case DRM_MODE_SCALE_CENTER:
6209 rmx_type = RMX_CENTER;
6211 case DRM_MODE_SCALE_ASPECT:
6212 rmx_type = RMX_ASPECT;
6214 case DRM_MODE_SCALE_FULLSCREEN:
6215 rmx_type = RMX_FULL;
6217 case DRM_MODE_SCALE_NONE:
6223 if (dm_old_state->scaling == rmx_type)
6226 dm_new_state->scaling = rmx_type;
6228 } else if (property == adev->mode_info.underscan_hborder_property) {
6229 dm_new_state->underscan_hborder = val;
6231 } else if (property == adev->mode_info.underscan_vborder_property) {
6232 dm_new_state->underscan_vborder = val;
6234 } else if (property == adev->mode_info.underscan_property) {
6235 dm_new_state->underscan_enable = val;
6237 } else if (property == adev->mode_info.abm_level_property) {
6238 dm_new_state->abm_level = val;
6245 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
6246 const struct drm_connector_state *state,
6247 struct drm_property *property,
6250 struct drm_device *dev = connector->dev;
6251 struct amdgpu_device *adev = drm_to_adev(dev);
6252 struct dm_connector_state *dm_state =
6253 to_dm_connector_state(state);
6256 if (property == dev->mode_config.scaling_mode_property) {
6257 switch (dm_state->scaling) {
6259 *val = DRM_MODE_SCALE_CENTER;
6262 *val = DRM_MODE_SCALE_ASPECT;
6265 *val = DRM_MODE_SCALE_FULLSCREEN;
6269 *val = DRM_MODE_SCALE_NONE;
6273 } else if (property == adev->mode_info.underscan_hborder_property) {
6274 *val = dm_state->underscan_hborder;
6276 } else if (property == adev->mode_info.underscan_vborder_property) {
6277 *val = dm_state->underscan_vborder;
6279 } else if (property == adev->mode_info.underscan_property) {
6280 *val = dm_state->underscan_enable;
6282 } else if (property == adev->mode_info.abm_level_property) {
6283 *val = dm_state->abm_level;
6290 static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
6292 struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
6294 drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
6297 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
6299 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6300 struct amdgpu_device *adev = drm_to_adev(connector->dev);
6301 struct amdgpu_display_manager *dm = &adev->dm;
6304 * Call only if mst_mgr was initialized before since it's not done
6305 * for all connector types.
6307 if (aconnector->mst_mgr.dev)
6308 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);
6310 if (aconnector->bl_idx != -1) {
6311 backlight_device_unregister(dm->backlight_dev[aconnector->bl_idx]);
6312 dm->backlight_dev[aconnector->bl_idx] = NULL;
6315 if (aconnector->dc_em_sink)
6316 dc_sink_release(aconnector->dc_em_sink);
6317 aconnector->dc_em_sink = NULL;
6318 if (aconnector->dc_sink)
6319 dc_sink_release(aconnector->dc_sink);
6320 aconnector->dc_sink = NULL;
6322 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
6323 drm_connector_unregister(connector);
6324 drm_connector_cleanup(connector);
6325 if (aconnector->i2c) {
6326 i2c_del_adapter(&aconnector->i2c->base);
6327 kfree(aconnector->i2c);
6329 kfree(aconnector->dm_dp_aux.aux.name);
6334 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
6336 struct dm_connector_state *state =
6337 to_dm_connector_state(connector->state);
6339 if (connector->state)
6340 __drm_atomic_helper_connector_destroy_state(connector->state);
6344 state = kzalloc(sizeof(*state), GFP_KERNEL);
6347 state->scaling = RMX_OFF;
6348 state->underscan_enable = false;
6349 state->underscan_hborder = 0;
6350 state->underscan_vborder = 0;
6351 state->base.max_requested_bpc = 8;
6352 state->vcpi_slots = 0;
6355 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
6356 state->abm_level = amdgpu_dm_abm_level;
6358 __drm_atomic_helper_connector_reset(connector, &state->base);
6362 struct drm_connector_state *
6363 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
6365 struct dm_connector_state *state =
6366 to_dm_connector_state(connector->state);
6368 struct dm_connector_state *new_state =
6369 kmemdup(state, sizeof(*state), GFP_KERNEL);
6374 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
6376 new_state->freesync_capable = state->freesync_capable;
6377 new_state->abm_level = state->abm_level;
6378 new_state->scaling = state->scaling;
6379 new_state->underscan_enable = state->underscan_enable;
6380 new_state->underscan_hborder = state->underscan_hborder;
6381 new_state->underscan_vborder = state->underscan_vborder;
6382 new_state->vcpi_slots = state->vcpi_slots;
6383 new_state->pbn = state->pbn;
6384 return &new_state->base;
6388 amdgpu_dm_connector_late_register(struct drm_connector *connector)
6390 struct amdgpu_dm_connector *amdgpu_dm_connector =
6391 to_amdgpu_dm_connector(connector);
6394 amdgpu_dm_register_backlight_device(amdgpu_dm_connector);
6396 if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
6397 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
6398 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
6399 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
6404 #if defined(CONFIG_DEBUG_FS)
6405 connector_debugfs_init(amdgpu_dm_connector);
6411 static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector)
6413 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6414 struct dc_link *dc_link = aconnector->dc_link;
6415 struct dc_sink *dc_em_sink = aconnector->dc_em_sink;
6418 if (!connector->edid_override)
6421 drm_edid_override_connector_update(&aconnector->base);
6422 edid = aconnector->base.edid_blob_ptr->data;
6423 aconnector->edid = edid;
6425 /* Update emulated (virtual) sink's EDID */
6426 if (dc_em_sink && dc_link) {
6427 memset(&dc_em_sink->edid_caps, 0, sizeof(struct dc_edid_caps));
6428 memmove(dc_em_sink->dc_edid.raw_edid, edid, (edid->extensions + 1) * EDID_LENGTH);
6429 dm_helpers_parse_edid_caps(
6431 &dc_em_sink->dc_edid,
6432 &dc_em_sink->edid_caps);
6436 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
6437 .reset = amdgpu_dm_connector_funcs_reset,
6438 .detect = amdgpu_dm_connector_detect,
6439 .fill_modes = drm_helper_probe_single_connector_modes,
6440 .destroy = amdgpu_dm_connector_destroy,
6441 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
6442 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6443 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
6444 .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
6445 .late_register = amdgpu_dm_connector_late_register,
6446 .early_unregister = amdgpu_dm_connector_unregister,
6447 .force = amdgpu_dm_connector_funcs_force
6450 static int get_modes(struct drm_connector *connector)
6452 return amdgpu_dm_connector_get_modes(connector);
6455 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
6457 struct dc_sink_init_data init_params = {
6458 .link = aconnector->dc_link,
6459 .sink_signal = SIGNAL_TYPE_VIRTUAL
6463 if (!aconnector->base.edid_blob_ptr) {
6464 /* if connector->edid_override valid, pass
6465 * it to edid_override to edid_blob_ptr
6468 drm_edid_override_connector_update(&aconnector->base);
6470 if (!aconnector->base.edid_blob_ptr) {
6471 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
6472 aconnector->base.name);
6474 aconnector->base.force = DRM_FORCE_OFF;
6479 edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
6481 aconnector->edid = edid;
6483 aconnector->dc_em_sink = dc_link_add_remote_sink(
6484 aconnector->dc_link,
6486 (edid->extensions + 1) * EDID_LENGTH,
6489 if (aconnector->base.force == DRM_FORCE_ON) {
6490 aconnector->dc_sink = aconnector->dc_link->local_sink ?
6491 aconnector->dc_link->local_sink :
6492 aconnector->dc_em_sink;
6493 dc_sink_retain(aconnector->dc_sink);
6497 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
6499 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
6502 * In case of headless boot with force on for DP managed connector
6503 * Those settings have to be != 0 to get initial modeset
6505 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
6506 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
6507 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
6510 create_eml_sink(aconnector);
6513 static enum dc_status dm_validate_stream_and_context(struct dc *dc,
6514 struct dc_stream_state *stream)
6516 enum dc_status dc_result = DC_ERROR_UNEXPECTED;
6517 struct dc_plane_state *dc_plane_state = NULL;
6518 struct dc_state *dc_state = NULL;
6523 dc_plane_state = dc_create_plane_state(dc);
6524 if (!dc_plane_state)
6527 dc_state = dc_create_state(dc);
6531 /* populate stream to plane */
6532 dc_plane_state->src_rect.height = stream->src.height;
6533 dc_plane_state->src_rect.width = stream->src.width;
6534 dc_plane_state->dst_rect.height = stream->src.height;
6535 dc_plane_state->dst_rect.width = stream->src.width;
6536 dc_plane_state->clip_rect.height = stream->src.height;
6537 dc_plane_state->clip_rect.width = stream->src.width;
6538 dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256;
6539 dc_plane_state->plane_size.surface_size.height = stream->src.height;
6540 dc_plane_state->plane_size.surface_size.width = stream->src.width;
6541 dc_plane_state->plane_size.chroma_size.height = stream->src.height;
6542 dc_plane_state->plane_size.chroma_size.width = stream->src.width;
6543 dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
6544 dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN;
6545 dc_plane_state->rotation = ROTATION_ANGLE_0;
6546 dc_plane_state->is_tiling_rotated = false;
6547 dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL;
6549 dc_result = dc_validate_stream(dc, stream);
6550 if (dc_result == DC_OK)
6551 dc_result = dc_validate_plane(dc, dc_plane_state);
6553 if (dc_result == DC_OK)
6554 dc_result = dc_add_stream_to_ctx(dc, dc_state, stream);
6556 if (dc_result == DC_OK && !dc_add_plane_to_context(
6561 dc_result = DC_FAIL_ATTACH_SURFACES;
6563 if (dc_result == DC_OK)
6564 dc_result = dc_validate_global_state(dc, dc_state, true);
6568 dc_release_state(dc_state);
6571 dc_plane_state_release(dc_plane_state);
6576 struct dc_stream_state *
6577 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6578 const struct drm_display_mode *drm_mode,
6579 const struct dm_connector_state *dm_state,
6580 const struct dc_stream_state *old_stream)
6582 struct drm_connector *connector = &aconnector->base;
6583 struct amdgpu_device *adev = drm_to_adev(connector->dev);
6584 struct dc_stream_state *stream;
6585 const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL;
6586 int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8;
6587 enum dc_status dc_result = DC_OK;
6590 stream = create_stream_for_sink(aconnector, drm_mode,
6591 dm_state, old_stream,
6593 if (stream == NULL) {
6594 DRM_ERROR("Failed to create stream for sink!\n");
6598 dc_result = dc_validate_stream(adev->dm.dc, stream);
6599 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
6600 dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream);
6602 if (dc_result == DC_OK)
6603 dc_result = dm_validate_stream_and_context(adev->dm.dc, stream);
6605 if (dc_result != DC_OK) {
6606 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",
6611 dc_status_to_str(dc_result));
6613 dc_stream_release(stream);
6615 requested_bpc -= 2; /* lower bpc to retry validation */
6618 } while (stream == NULL && requested_bpc >= 6);
6620 if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) {
6621 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n");
6623 aconnector->force_yuv420_output = true;
6624 stream = create_validate_stream_for_sink(aconnector, drm_mode,
6625 dm_state, old_stream);
6626 aconnector->force_yuv420_output = false;
6632 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
6633 struct drm_display_mode *mode)
6635 int result = MODE_ERROR;
6636 struct dc_sink *dc_sink;
6637 /* TODO: Unhardcode stream count */
6638 struct dc_stream_state *stream;
6639 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6641 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
6642 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
6646 * Only run this the first time mode_valid is called to initilialize
6649 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
6650 !aconnector->dc_em_sink)
6651 handle_edid_mgmt(aconnector);
6653 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
6655 if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL &&
6656 aconnector->base.force != DRM_FORCE_ON) {
6657 DRM_ERROR("dc_sink is NULL!\n");
6661 drm_mode_set_crtcinfo(mode, 0);
6663 stream = create_validate_stream_for_sink(aconnector, mode,
6664 to_dm_connector_state(connector->state),
6667 dc_stream_release(stream);
6672 /* TODO: error handling*/
6676 static int fill_hdr_info_packet(const struct drm_connector_state *state,
6677 struct dc_info_packet *out)
6679 struct hdmi_drm_infoframe frame;
6680 unsigned char buf[30]; /* 26 + 4 */
6684 memset(out, 0, sizeof(*out));
6686 if (!state->hdr_output_metadata)
6689 ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
6693 len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
6697 /* Static metadata is a fixed 26 bytes + 4 byte header. */
6701 /* Prepare the infopacket for DC. */
6702 switch (state->connector->connector_type) {
6703 case DRM_MODE_CONNECTOR_HDMIA:
6704 out->hb0 = 0x87; /* type */
6705 out->hb1 = 0x01; /* version */
6706 out->hb2 = 0x1A; /* length */
6707 out->sb[0] = buf[3]; /* checksum */
6711 case DRM_MODE_CONNECTOR_DisplayPort:
6712 case DRM_MODE_CONNECTOR_eDP:
6713 out->hb0 = 0x00; /* sdp id, zero */
6714 out->hb1 = 0x87; /* type */
6715 out->hb2 = 0x1D; /* payload len - 1 */
6716 out->hb3 = (0x13 << 2); /* sdp version */
6717 out->sb[0] = 0x01; /* version */
6718 out->sb[1] = 0x1A; /* length */
6726 memcpy(&out->sb[i], &buf[4], 26);
6729 print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
6730 sizeof(out->sb), false);
6736 amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
6737 struct drm_atomic_state *state)
6739 struct drm_connector_state *new_con_state =
6740 drm_atomic_get_new_connector_state(state, conn);
6741 struct drm_connector_state *old_con_state =
6742 drm_atomic_get_old_connector_state(state, conn);
6743 struct drm_crtc *crtc = new_con_state->crtc;
6744 struct drm_crtc_state *new_crtc_state;
6745 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn);
6748 trace_amdgpu_dm_connector_atomic_check(new_con_state);
6750 if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
6751 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr);
6759 if (new_con_state->colorspace != old_con_state->colorspace) {
6760 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6761 if (IS_ERR(new_crtc_state))
6762 return PTR_ERR(new_crtc_state);
6764 new_crtc_state->mode_changed = true;
6767 if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) {
6768 struct dc_info_packet hdr_infopacket;
6770 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
6774 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6775 if (IS_ERR(new_crtc_state))
6776 return PTR_ERR(new_crtc_state);
6779 * DC considers the stream backends changed if the
6780 * static metadata changes. Forcing the modeset also
6781 * gives a simple way for userspace to switch from
6782 * 8bpc to 10bpc when setting the metadata to enter
6785 * Changing the static metadata after it's been
6786 * set is permissible, however. So only force a
6787 * modeset if we're entering or exiting HDR.
6789 new_crtc_state->mode_changed = new_crtc_state->mode_changed ||
6790 !old_con_state->hdr_output_metadata ||
6791 !new_con_state->hdr_output_metadata;
6797 static const struct drm_connector_helper_funcs
6798 amdgpu_dm_connector_helper_funcs = {
6800 * If hotplugging a second bigger display in FB Con mode, bigger resolution
6801 * modes will be filtered by drm_mode_validate_size(), and those modes
6802 * are missing after user start lightdm. So we need to renew modes list.
6803 * in get_modes call back, not just return the modes count
6805 .get_modes = get_modes,
6806 .mode_valid = amdgpu_dm_connector_mode_valid,
6807 .atomic_check = amdgpu_dm_connector_atomic_check,
6810 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
6815 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth)
6817 switch (display_color_depth) {
6818 case COLOR_DEPTH_666:
6820 case COLOR_DEPTH_888:
6822 case COLOR_DEPTH_101010:
6824 case COLOR_DEPTH_121212:
6826 case COLOR_DEPTH_141414:
6828 case COLOR_DEPTH_161616:
6836 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
6837 struct drm_crtc_state *crtc_state,
6838 struct drm_connector_state *conn_state)
6840 struct drm_atomic_state *state = crtc_state->state;
6841 struct drm_connector *connector = conn_state->connector;
6842 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6843 struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state);
6844 const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
6845 struct drm_dp_mst_topology_mgr *mst_mgr;
6846 struct drm_dp_mst_port *mst_port;
6847 struct drm_dp_mst_topology_state *mst_state;
6848 enum dc_color_depth color_depth;
6850 bool is_y420 = false;
6852 if (!aconnector->mst_output_port)
6855 mst_port = aconnector->mst_output_port;
6856 mst_mgr = &aconnector->mst_root->mst_mgr;
6858 if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
6861 mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr);
6862 if (IS_ERR(mst_state))
6863 return PTR_ERR(mst_state);
6865 if (!mst_state->pbn_div)
6866 mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link);
6868 if (!state->duplicated) {
6869 int max_bpc = conn_state->max_requested_bpc;
6871 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
6872 aconnector->force_yuv420_output;
6873 color_depth = convert_color_depth_from_display_info(connector,
6876 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
6877 clock = adjusted_mode->clock;
6878 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
6881 dm_new_connector_state->vcpi_slots =
6882 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port,
6883 dm_new_connector_state->pbn);
6884 if (dm_new_connector_state->vcpi_slots < 0) {
6885 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
6886 return dm_new_connector_state->vcpi_slots;
6891 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
6892 .disable = dm_encoder_helper_disable,
6893 .atomic_check = dm_encoder_helper_atomic_check
6896 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
6897 struct dc_state *dc_state,
6898 struct dsc_mst_fairness_vars *vars)
6900 struct dc_stream_state *stream = NULL;
6901 struct drm_connector *connector;
6902 struct drm_connector_state *new_con_state;
6903 struct amdgpu_dm_connector *aconnector;
6904 struct dm_connector_state *dm_conn_state;
6906 int vcpi, pbn_div, pbn, slot_num = 0;
6908 for_each_new_connector_in_state(state, connector, new_con_state, i) {
6910 aconnector = to_amdgpu_dm_connector(connector);
6912 if (!aconnector->mst_output_port)
6915 if (!new_con_state || !new_con_state->crtc)
6918 dm_conn_state = to_dm_connector_state(new_con_state);
6920 for (j = 0; j < dc_state->stream_count; j++) {
6921 stream = dc_state->streams[j];
6925 if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector)
6934 pbn_div = dm_mst_get_pbn_divider(stream->link);
6935 /* pbn is calculated by compute_mst_dsc_configs_for_state*/
6936 for (j = 0; j < dc_state->stream_count; j++) {
6937 if (vars[j].aconnector == aconnector) {
6943 if (j == dc_state->stream_count)
6946 slot_num = DIV_ROUND_UP(pbn, pbn_div);
6948 if (stream->timing.flags.DSC != 1) {
6949 dm_conn_state->pbn = pbn;
6950 dm_conn_state->vcpi_slots = slot_num;
6952 ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port,
6953 dm_conn_state->pbn, false);
6960 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true);
6964 dm_conn_state->pbn = pbn;
6965 dm_conn_state->vcpi_slots = vcpi;
6970 static int to_drm_connector_type(enum signal_type st)
6973 case SIGNAL_TYPE_HDMI_TYPE_A:
6974 return DRM_MODE_CONNECTOR_HDMIA;
6975 case SIGNAL_TYPE_EDP:
6976 return DRM_MODE_CONNECTOR_eDP;
6977 case SIGNAL_TYPE_LVDS:
6978 return DRM_MODE_CONNECTOR_LVDS;
6979 case SIGNAL_TYPE_RGB:
6980 return DRM_MODE_CONNECTOR_VGA;
6981 case SIGNAL_TYPE_DISPLAY_PORT:
6982 case SIGNAL_TYPE_DISPLAY_PORT_MST:
6983 return DRM_MODE_CONNECTOR_DisplayPort;
6984 case SIGNAL_TYPE_DVI_DUAL_LINK:
6985 case SIGNAL_TYPE_DVI_SINGLE_LINK:
6986 return DRM_MODE_CONNECTOR_DVID;
6987 case SIGNAL_TYPE_VIRTUAL:
6988 return DRM_MODE_CONNECTOR_VIRTUAL;
6991 return DRM_MODE_CONNECTOR_Unknown;
6995 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
6997 struct drm_encoder *encoder;
6999 /* There is only one encoder per connector */
7000 drm_connector_for_each_possible_encoder(connector, encoder)
7006 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
7008 struct drm_encoder *encoder;
7009 struct amdgpu_encoder *amdgpu_encoder;
7011 encoder = amdgpu_dm_connector_to_encoder(connector);
7013 if (encoder == NULL)
7016 amdgpu_encoder = to_amdgpu_encoder(encoder);
7018 amdgpu_encoder->native_mode.clock = 0;
7020 if (!list_empty(&connector->probed_modes)) {
7021 struct drm_display_mode *preferred_mode = NULL;
7023 list_for_each_entry(preferred_mode,
7024 &connector->probed_modes,
7026 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
7027 amdgpu_encoder->native_mode = *preferred_mode;
7035 static struct drm_display_mode *
7036 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
7038 int hdisplay, int vdisplay)
7040 struct drm_device *dev = encoder->dev;
7041 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
7042 struct drm_display_mode *mode = NULL;
7043 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
7045 mode = drm_mode_duplicate(dev, native_mode);
7050 mode->hdisplay = hdisplay;
7051 mode->vdisplay = vdisplay;
7052 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7053 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
7059 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
7060 struct drm_connector *connector)
7062 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
7063 struct drm_display_mode *mode = NULL;
7064 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
7065 struct amdgpu_dm_connector *amdgpu_dm_connector =
7066 to_amdgpu_dm_connector(connector);
7070 char name[DRM_DISPLAY_MODE_LEN];
7073 } common_modes[] = {
7074 { "640x480", 640, 480},
7075 { "800x600", 800, 600},
7076 { "1024x768", 1024, 768},
7077 { "1280x720", 1280, 720},
7078 { "1280x800", 1280, 800},
7079 {"1280x1024", 1280, 1024},
7080 { "1440x900", 1440, 900},
7081 {"1680x1050", 1680, 1050},
7082 {"1600x1200", 1600, 1200},
7083 {"1920x1080", 1920, 1080},
7084 {"1920x1200", 1920, 1200}
7087 n = ARRAY_SIZE(common_modes);
7089 for (i = 0; i < n; i++) {
7090 struct drm_display_mode *curmode = NULL;
7091 bool mode_existed = false;
7093 if (common_modes[i].w > native_mode->hdisplay ||
7094 common_modes[i].h > native_mode->vdisplay ||
7095 (common_modes[i].w == native_mode->hdisplay &&
7096 common_modes[i].h == native_mode->vdisplay))
7099 list_for_each_entry(curmode, &connector->probed_modes, head) {
7100 if (common_modes[i].w == curmode->hdisplay &&
7101 common_modes[i].h == curmode->vdisplay) {
7102 mode_existed = true;
7110 mode = amdgpu_dm_create_common_mode(encoder,
7111 common_modes[i].name, common_modes[i].w,
7116 drm_mode_probed_add(connector, mode);
7117 amdgpu_dm_connector->num_modes++;
7121 static void amdgpu_set_panel_orientation(struct drm_connector *connector)
7123 struct drm_encoder *encoder;
7124 struct amdgpu_encoder *amdgpu_encoder;
7125 const struct drm_display_mode *native_mode;
7127 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
7128 connector->connector_type != DRM_MODE_CONNECTOR_LVDS)
7131 mutex_lock(&connector->dev->mode_config.mutex);
7132 amdgpu_dm_connector_get_modes(connector);
7133 mutex_unlock(&connector->dev->mode_config.mutex);
7135 encoder = amdgpu_dm_connector_to_encoder(connector);
7139 amdgpu_encoder = to_amdgpu_encoder(encoder);
7141 native_mode = &amdgpu_encoder->native_mode;
7142 if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0)
7145 drm_connector_set_panel_orientation_with_quirk(connector,
7146 DRM_MODE_PANEL_ORIENTATION_UNKNOWN,
7147 native_mode->hdisplay,
7148 native_mode->vdisplay);
7151 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
7154 struct amdgpu_dm_connector *amdgpu_dm_connector =
7155 to_amdgpu_dm_connector(connector);
7158 /* empty probed_modes */
7159 INIT_LIST_HEAD(&connector->probed_modes);
7160 amdgpu_dm_connector->num_modes =
7161 drm_add_edid_modes(connector, edid);
7163 /* sorting the probed modes before calling function
7164 * amdgpu_dm_get_native_mode() since EDID can have
7165 * more than one preferred mode. The modes that are
7166 * later in the probed mode list could be of higher
7167 * and preferred resolution. For example, 3840x2160
7168 * resolution in base EDID preferred timing and 4096x2160
7169 * preferred resolution in DID extension block later.
7171 drm_mode_sort(&connector->probed_modes);
7172 amdgpu_dm_get_native_mode(connector);
7174 /* Freesync capabilities are reset by calling
7175 * drm_add_edid_modes() and need to be
7178 amdgpu_dm_update_freesync_caps(connector, edid);
7180 amdgpu_dm_connector->num_modes = 0;
7184 static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector,
7185 struct drm_display_mode *mode)
7187 struct drm_display_mode *m;
7189 list_for_each_entry(m, &aconnector->base.probed_modes, head) {
7190 if (drm_mode_equal(m, mode))
7197 static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)
7199 const struct drm_display_mode *m;
7200 struct drm_display_mode *new_mode;
7202 u32 new_modes_count = 0;
7204 /* Standard FPS values
7213 * 60 - Commonly used
7214 * 48,72,96,120 - Multiples of 24
7216 static const u32 common_rates[] = {
7217 23976, 24000, 25000, 29970, 30000,
7218 48000, 50000, 60000, 72000, 96000, 120000
7222 * Find mode with highest refresh rate with the same resolution
7223 * as the preferred mode. Some monitors report a preferred mode
7224 * with lower resolution than the highest refresh rate supported.
7227 m = get_highest_refresh_rate_mode(aconnector, true);
7231 for (i = 0; i < ARRAY_SIZE(common_rates); i++) {
7232 u64 target_vtotal, target_vtotal_diff;
7235 if (drm_mode_vrefresh(m) * 1000 < common_rates[i])
7238 if (common_rates[i] < aconnector->min_vfreq * 1000 ||
7239 common_rates[i] > aconnector->max_vfreq * 1000)
7242 num = (unsigned long long)m->clock * 1000 * 1000;
7243 den = common_rates[i] * (unsigned long long)m->htotal;
7244 target_vtotal = div_u64(num, den);
7245 target_vtotal_diff = target_vtotal - m->vtotal;
7247 /* Check for illegal modes */
7248 if (m->vsync_start + target_vtotal_diff < m->vdisplay ||
7249 m->vsync_end + target_vtotal_diff < m->vsync_start ||
7250 m->vtotal + target_vtotal_diff < m->vsync_end)
7253 new_mode = drm_mode_duplicate(aconnector->base.dev, m);
7257 new_mode->vtotal += (u16)target_vtotal_diff;
7258 new_mode->vsync_start += (u16)target_vtotal_diff;
7259 new_mode->vsync_end += (u16)target_vtotal_diff;
7260 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7261 new_mode->type |= DRM_MODE_TYPE_DRIVER;
7263 if (!is_duplicate_mode(aconnector, new_mode)) {
7264 drm_mode_probed_add(&aconnector->base, new_mode);
7265 new_modes_count += 1;
7267 drm_mode_destroy(aconnector->base.dev, new_mode);
7270 return new_modes_count;
7273 static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector,
7276 struct amdgpu_dm_connector *amdgpu_dm_connector =
7277 to_amdgpu_dm_connector(connector);
7282 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
7283 amdgpu_dm_connector->num_modes +=
7284 add_fs_modes(amdgpu_dm_connector);
7287 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
7289 struct amdgpu_dm_connector *amdgpu_dm_connector =
7290 to_amdgpu_dm_connector(connector);
7291 struct drm_encoder *encoder;
7292 struct edid *edid = amdgpu_dm_connector->edid;
7293 struct dc_link_settings *verified_link_cap =
7294 &amdgpu_dm_connector->dc_link->verified_link_cap;
7295 const struct dc *dc = amdgpu_dm_connector->dc_link->dc;
7297 encoder = amdgpu_dm_connector_to_encoder(connector);
7299 if (!drm_edid_is_valid(edid)) {
7300 amdgpu_dm_connector->num_modes =
7301 drm_add_modes_noedid(connector, 640, 480);
7302 if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING)
7303 amdgpu_dm_connector->num_modes +=
7304 drm_add_modes_noedid(connector, 1920, 1080);
7306 amdgpu_dm_connector_ddc_get_modes(connector, edid);
7307 amdgpu_dm_connector_add_common_modes(encoder, connector);
7308 amdgpu_dm_connector_add_freesync_modes(connector, edid);
7310 amdgpu_dm_fbc_init(connector);
7312 return amdgpu_dm_connector->num_modes;
7315 static const u32 supported_colorspaces =
7316 BIT(DRM_MODE_COLORIMETRY_BT709_YCC) |
7317 BIT(DRM_MODE_COLORIMETRY_OPRGB) |
7318 BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) |
7319 BIT(DRM_MODE_COLORIMETRY_BT2020_YCC);
7321 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
7322 struct amdgpu_dm_connector *aconnector,
7324 struct dc_link *link,
7327 struct amdgpu_device *adev = drm_to_adev(dm->ddev);
7330 * Some of the properties below require access to state, like bpc.
7331 * Allocate some default initial connector state with our reset helper.
7333 if (aconnector->base.funcs->reset)
7334 aconnector->base.funcs->reset(&aconnector->base);
7336 aconnector->connector_id = link_index;
7337 aconnector->bl_idx = -1;
7338 aconnector->dc_link = link;
7339 aconnector->base.interlace_allowed = false;
7340 aconnector->base.doublescan_allowed = false;
7341 aconnector->base.stereo_allowed = false;
7342 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
7343 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
7344 aconnector->audio_inst = -1;
7345 aconnector->pack_sdp_v1_3 = false;
7346 aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE;
7347 memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info));
7348 mutex_init(&aconnector->hpd_lock);
7349 mutex_init(&aconnector->handle_mst_msg_ready);
7352 * configure support HPD hot plug connector_>polled default value is 0
7353 * which means HPD hot plug not supported
7355 switch (connector_type) {
7356 case DRM_MODE_CONNECTOR_HDMIA:
7357 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7358 aconnector->base.ycbcr_420_allowed =
7359 link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
7361 case DRM_MODE_CONNECTOR_DisplayPort:
7362 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7363 link->link_enc = link_enc_cfg_get_link_enc(link);
7364 ASSERT(link->link_enc);
7366 aconnector->base.ycbcr_420_allowed =
7367 link->link_enc->features.dp_ycbcr420_supported ? true : false;
7369 case DRM_MODE_CONNECTOR_DVID:
7370 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7376 drm_object_attach_property(&aconnector->base.base,
7377 dm->ddev->mode_config.scaling_mode_property,
7378 DRM_MODE_SCALE_NONE);
7380 drm_object_attach_property(&aconnector->base.base,
7381 adev->mode_info.underscan_property,
7383 drm_object_attach_property(&aconnector->base.base,
7384 adev->mode_info.underscan_hborder_property,
7386 drm_object_attach_property(&aconnector->base.base,
7387 adev->mode_info.underscan_vborder_property,
7390 if (!aconnector->mst_root)
7391 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
7393 aconnector->base.state->max_bpc = 16;
7394 aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
7396 if (connector_type == DRM_MODE_CONNECTOR_eDP &&
7397 (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) {
7398 drm_object_attach_property(&aconnector->base.base,
7399 adev->mode_info.abm_level_property, 0);
7402 if (connector_type == DRM_MODE_CONNECTOR_HDMIA) {
7403 if (!drm_mode_create_hdmi_colorspace_property(&aconnector->base, supported_colorspaces))
7404 drm_connector_attach_colorspace_property(&aconnector->base);
7405 } else if ((connector_type == DRM_MODE_CONNECTOR_DisplayPort && !aconnector->mst_root) ||
7406 connector_type == DRM_MODE_CONNECTOR_eDP) {
7407 if (!drm_mode_create_dp_colorspace_property(&aconnector->base, supported_colorspaces))
7408 drm_connector_attach_colorspace_property(&aconnector->base);
7411 if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
7412 connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
7413 connector_type == DRM_MODE_CONNECTOR_eDP) {
7414 drm_connector_attach_hdr_output_metadata_property(&aconnector->base);
7416 if (!aconnector->mst_root)
7417 drm_connector_attach_vrr_capable_property(&aconnector->base);
7419 if (adev->dm.hdcp_workqueue)
7420 drm_connector_attach_content_protection_property(&aconnector->base, true);
7424 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
7425 struct i2c_msg *msgs, int num)
7427 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
7428 struct ddc_service *ddc_service = i2c->ddc_service;
7429 struct i2c_command cmd;
7433 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
7438 cmd.number_of_payloads = num;
7439 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
7442 for (i = 0; i < num; i++) {
7443 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
7444 cmd.payloads[i].address = msgs[i].addr;
7445 cmd.payloads[i].length = msgs[i].len;
7446 cmd.payloads[i].data = msgs[i].buf;
7450 ddc_service->ctx->dc,
7451 ddc_service->link->link_index,
7455 kfree(cmd.payloads);
7459 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
7461 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
7464 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
7465 .master_xfer = amdgpu_dm_i2c_xfer,
7466 .functionality = amdgpu_dm_i2c_func,
7469 static struct amdgpu_i2c_adapter *
7470 create_i2c(struct ddc_service *ddc_service,
7474 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
7475 struct amdgpu_i2c_adapter *i2c;
7477 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
7480 i2c->base.owner = THIS_MODULE;
7481 i2c->base.class = I2C_CLASS_DDC;
7482 i2c->base.dev.parent = &adev->pdev->dev;
7483 i2c->base.algo = &amdgpu_dm_i2c_algo;
7484 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
7485 i2c_set_adapdata(&i2c->base, i2c);
7486 i2c->ddc_service = ddc_service;
7493 * Note: this function assumes that dc_link_detect() was called for the
7494 * dc_link which will be represented by this aconnector.
7496 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
7497 struct amdgpu_dm_connector *aconnector,
7499 struct amdgpu_encoder *aencoder)
7503 struct dc *dc = dm->dc;
7504 struct dc_link *link = dc_get_link_at_index(dc, link_index);
7505 struct amdgpu_i2c_adapter *i2c;
7507 link->priv = aconnector;
7510 i2c = create_i2c(link->ddc, link->link_index, &res);
7512 DRM_ERROR("Failed to create i2c adapter data\n");
7516 aconnector->i2c = i2c;
7517 res = i2c_add_adapter(&i2c->base);
7520 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
7524 connector_type = to_drm_connector_type(link->connector_signal);
7526 res = drm_connector_init_with_ddc(
7529 &amdgpu_dm_connector_funcs,
7534 DRM_ERROR("connector_init failed\n");
7535 aconnector->connector_id = -1;
7539 drm_connector_helper_add(
7541 &amdgpu_dm_connector_helper_funcs);
7543 amdgpu_dm_connector_init_helper(
7550 drm_connector_attach_encoder(
7551 &aconnector->base, &aencoder->base);
7553 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
7554 || connector_type == DRM_MODE_CONNECTOR_eDP)
7555 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);
7560 aconnector->i2c = NULL;
7565 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
7567 switch (adev->mode_info.num_crtc) {
7584 static int amdgpu_dm_encoder_init(struct drm_device *dev,
7585 struct amdgpu_encoder *aencoder,
7586 uint32_t link_index)
7588 struct amdgpu_device *adev = drm_to_adev(dev);
7590 int res = drm_encoder_init(dev,
7592 &amdgpu_dm_encoder_funcs,
7593 DRM_MODE_ENCODER_TMDS,
7596 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
7599 aencoder->encoder_id = link_index;
7601 aencoder->encoder_id = -1;
7603 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
7608 static void manage_dm_interrupts(struct amdgpu_device *adev,
7609 struct amdgpu_crtc *acrtc,
7613 * We have no guarantee that the frontend index maps to the same
7614 * backend index - some even map to more than one.
7616 * TODO: Use a different interrupt or check DC itself for the mapping.
7619 amdgpu_display_crtc_idx_to_irq_type(
7624 drm_crtc_vblank_on(&acrtc->base);
7627 &adev->pageflip_irq,
7629 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7636 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7644 &adev->pageflip_irq,
7646 drm_crtc_vblank_off(&acrtc->base);
7650 static void dm_update_pflip_irq_state(struct amdgpu_device *adev,
7651 struct amdgpu_crtc *acrtc)
7654 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
7657 * This reads the current state for the IRQ and force reapplies
7658 * the setting to hardware.
7660 amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type);
7664 is_scaling_state_different(const struct dm_connector_state *dm_state,
7665 const struct dm_connector_state *old_dm_state)
7667 if (dm_state->scaling != old_dm_state->scaling)
7669 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
7670 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
7672 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
7673 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
7675 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
7676 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
7681 static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state,
7682 struct drm_crtc_state *old_crtc_state,
7683 struct drm_connector_state *new_conn_state,
7684 struct drm_connector_state *old_conn_state,
7685 const struct drm_connector *connector,
7686 struct hdcp_workqueue *hdcp_w)
7688 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7689 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
7691 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
7692 connector->index, connector->status, connector->dpms);
7693 pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
7694 old_conn_state->content_protection, new_conn_state->content_protection);
7697 pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7698 old_crtc_state->enable,
7699 old_crtc_state->active,
7700 old_crtc_state->mode_changed,
7701 old_crtc_state->active_changed,
7702 old_crtc_state->connectors_changed);
7705 pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7706 new_crtc_state->enable,
7707 new_crtc_state->active,
7708 new_crtc_state->mode_changed,
7709 new_crtc_state->active_changed,
7710 new_crtc_state->connectors_changed);
7712 /* hdcp content type change */
7713 if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type &&
7714 new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
7715 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7716 pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__);
7720 /* CP is being re enabled, ignore this */
7721 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
7722 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7723 if (new_crtc_state && new_crtc_state->mode_changed) {
7724 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7725 pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__);
7728 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
7729 pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__);
7733 /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED
7735 * Handles: UNDESIRED -> ENABLED
7737 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
7738 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
7739 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7741 /* Stream removed and re-enabled
7743 * Can sometimes overlap with the HPD case,
7744 * thus set update_hdcp to false to avoid
7745 * setting HDCP multiple times.
7747 * Handles: DESIRED -> DESIRED (Special case)
7749 if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) &&
7750 new_conn_state->crtc && new_conn_state->crtc->enabled &&
7751 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7752 dm_con_state->update_hdcp = false;
7753 pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n",
7758 /* Hot-plug, headless s3, dpms
7760 * Only start HDCP if the display is connected/enabled.
7761 * update_hdcp flag will be set to false until the next
7764 * Handles: DESIRED -> DESIRED (Special case)
7766 if (dm_con_state->update_hdcp &&
7767 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
7768 connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
7769 dm_con_state->update_hdcp = false;
7770 pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n",
7775 if (old_conn_state->content_protection == new_conn_state->content_protection) {
7776 if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7777 if (new_crtc_state && new_crtc_state->mode_changed) {
7778 pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n",
7782 pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n",
7787 pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__);
7791 if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) {
7792 pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n",
7797 pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__);
7801 static void remove_stream(struct amdgpu_device *adev,
7802 struct amdgpu_crtc *acrtc,
7803 struct dc_stream_state *stream)
7805 /* this is the update mode case */
7807 acrtc->otg_inst = -1;
7808 acrtc->enabled = false;
7811 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
7814 assert_spin_locked(&acrtc->base.dev->event_lock);
7815 WARN_ON(acrtc->event);
7817 acrtc->event = acrtc->base.state->event;
7819 /* Set the flip status */
7820 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
7822 /* Mark this event as consumed */
7823 acrtc->base.state->event = NULL;
7825 DC_LOG_PFLIP("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
7829 static void update_freesync_state_on_stream(
7830 struct amdgpu_display_manager *dm,
7831 struct dm_crtc_state *new_crtc_state,
7832 struct dc_stream_state *new_stream,
7833 struct dc_plane_state *surface,
7834 u32 flip_timestamp_in_us)
7836 struct mod_vrr_params vrr_params;
7837 struct dc_info_packet vrr_infopacket = {0};
7838 struct amdgpu_device *adev = dm->adev;
7839 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7840 unsigned long flags;
7841 bool pack_sdp_v1_3 = false;
7842 struct amdgpu_dm_connector *aconn;
7843 enum vrr_packet_type packet_type = PACKET_TYPE_VRR;
7849 * TODO: Determine why min/max totals and vrefresh can be 0 here.
7850 * For now it's sufficient to just guard against these conditions.
7853 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7856 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7857 vrr_params = acrtc->dm_irq_params.vrr_params;
7860 mod_freesync_handle_preflip(
7861 dm->freesync_module,
7864 flip_timestamp_in_us,
7867 if (adev->family < AMDGPU_FAMILY_AI &&
7868 amdgpu_dm_crtc_vrr_active(new_crtc_state)) {
7869 mod_freesync_handle_v_update(dm->freesync_module,
7870 new_stream, &vrr_params);
7872 /* Need to call this before the frame ends. */
7873 dc_stream_adjust_vmin_vmax(dm->dc,
7874 new_crtc_state->stream,
7875 &vrr_params.adjust);
7879 aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context;
7881 if (aconn && (aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST || aconn->vsdb_info.replay_mode)) {
7882 pack_sdp_v1_3 = aconn->pack_sdp_v1_3;
7884 if (aconn->vsdb_info.amd_vsdb_version == 1)
7885 packet_type = PACKET_TYPE_FS_V1;
7886 else if (aconn->vsdb_info.amd_vsdb_version == 2)
7887 packet_type = PACKET_TYPE_FS_V2;
7888 else if (aconn->vsdb_info.amd_vsdb_version == 3)
7889 packet_type = PACKET_TYPE_FS_V3;
7891 mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL,
7892 &new_stream->adaptive_sync_infopacket);
7895 mod_freesync_build_vrr_infopacket(
7896 dm->freesync_module,
7900 TRANSFER_FUNC_UNKNOWN,
7904 new_crtc_state->freesync_vrr_info_changed |=
7905 (memcmp(&new_crtc_state->vrr_infopacket,
7907 sizeof(vrr_infopacket)) != 0);
7909 acrtc->dm_irq_params.vrr_params = vrr_params;
7910 new_crtc_state->vrr_infopacket = vrr_infopacket;
7912 new_stream->vrr_infopacket = vrr_infopacket;
7913 new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params);
7915 if (new_crtc_state->freesync_vrr_info_changed)
7916 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
7917 new_crtc_state->base.crtc->base.id,
7918 (int)new_crtc_state->base.vrr_enabled,
7919 (int)vrr_params.state);
7921 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7924 static void update_stream_irq_parameters(
7925 struct amdgpu_display_manager *dm,
7926 struct dm_crtc_state *new_crtc_state)
7928 struct dc_stream_state *new_stream = new_crtc_state->stream;
7929 struct mod_vrr_params vrr_params;
7930 struct mod_freesync_config config = new_crtc_state->freesync_config;
7931 struct amdgpu_device *adev = dm->adev;
7932 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7933 unsigned long flags;
7939 * TODO: Determine why min/max totals and vrefresh can be 0 here.
7940 * For now it's sufficient to just guard against these conditions.
7942 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7945 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7946 vrr_params = acrtc->dm_irq_params.vrr_params;
7948 if (new_crtc_state->vrr_supported &&
7949 config.min_refresh_in_uhz &&
7950 config.max_refresh_in_uhz) {
7952 * if freesync compatible mode was set, config.state will be set
7955 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz &&
7956 (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) ||
7957 new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) {
7958 vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz;
7959 vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz;
7960 vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz;
7961 vrr_params.state = VRR_STATE_ACTIVE_FIXED;
7963 config.state = new_crtc_state->base.vrr_enabled ?
7964 VRR_STATE_ACTIVE_VARIABLE :
7968 config.state = VRR_STATE_UNSUPPORTED;
7971 mod_freesync_build_vrr_params(dm->freesync_module,
7973 &config, &vrr_params);
7975 new_crtc_state->freesync_config = config;
7976 /* Copy state for access from DM IRQ handler */
7977 acrtc->dm_irq_params.freesync_config = config;
7978 acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes;
7979 acrtc->dm_irq_params.vrr_params = vrr_params;
7980 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7983 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
7984 struct dm_crtc_state *new_state)
7986 bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state);
7987 bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state);
7989 if (!old_vrr_active && new_vrr_active) {
7990 /* Transition VRR inactive -> active:
7991 * While VRR is active, we must not disable vblank irq, as a
7992 * reenable after disable would compute bogus vblank/pflip
7993 * timestamps if it likely happened inside display front-porch.
7995 * We also need vupdate irq for the actual core vblank handling
7998 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0);
7999 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0);
8000 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
8001 __func__, new_state->base.crtc->base.id);
8002 } else if (old_vrr_active && !new_vrr_active) {
8003 /* Transition VRR active -> inactive:
8004 * Allow vblank irq disable again for fixed refresh rate.
8006 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0);
8007 drm_crtc_vblank_put(new_state->base.crtc);
8008 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
8009 __func__, new_state->base.crtc->base.id);
8013 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
8015 struct drm_plane *plane;
8016 struct drm_plane_state *old_plane_state;
8020 * TODO: Make this per-stream so we don't issue redundant updates for
8021 * commits with multiple streams.
8023 for_each_old_plane_in_state(state, plane, old_plane_state, i)
8024 if (plane->type == DRM_PLANE_TYPE_CURSOR)
8025 amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state);
8028 static inline uint32_t get_mem_type(struct drm_framebuffer *fb)
8030 struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]);
8032 return abo->tbo.resource ? abo->tbo.resource->mem_type : 0;
8035 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
8036 struct drm_device *dev,
8037 struct amdgpu_display_manager *dm,
8038 struct drm_crtc *pcrtc,
8039 bool wait_for_vblank)
8042 u64 timestamp_ns = ktime_get_ns();
8043 struct drm_plane *plane;
8044 struct drm_plane_state *old_plane_state, *new_plane_state;
8045 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
8046 struct drm_crtc_state *new_pcrtc_state =
8047 drm_atomic_get_new_crtc_state(state, pcrtc);
8048 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
8049 struct dm_crtc_state *dm_old_crtc_state =
8050 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
8051 int planes_count = 0, vpos, hpos;
8052 unsigned long flags;
8053 u32 target_vblank, last_flip_vblank;
8054 bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state);
8055 bool cursor_update = false;
8056 bool pflip_present = false;
8057 bool dirty_rects_changed = false;
8059 struct dc_surface_update surface_updates[MAX_SURFACES];
8060 struct dc_plane_info plane_infos[MAX_SURFACES];
8061 struct dc_scaling_info scaling_infos[MAX_SURFACES];
8062 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
8063 struct dc_stream_update stream_update;
8066 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
8069 dm_error("Failed to allocate update bundle\n");
8074 * Disable the cursor first if we're disabling all the planes.
8075 * It'll remain on the screen after the planes are re-enabled
8078 if (acrtc_state->active_planes == 0)
8079 amdgpu_dm_commit_cursors(state);
8081 /* update planes when needed */
8082 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
8083 struct drm_crtc *crtc = new_plane_state->crtc;
8084 struct drm_crtc_state *new_crtc_state;
8085 struct drm_framebuffer *fb = new_plane_state->fb;
8086 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb;
8087 bool plane_needs_flip;
8088 struct dc_plane_state *dc_plane;
8089 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
8091 /* Cursor plane is handled after stream updates */
8092 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
8093 if ((fb && crtc == pcrtc) ||
8094 (old_plane_state->fb && old_plane_state->crtc == pcrtc))
8095 cursor_update = true;
8100 if (!fb || !crtc || pcrtc != crtc)
8103 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
8104 if (!new_crtc_state->active)
8107 dc_plane = dm_new_plane_state->dc_state;
8111 bundle->surface_updates[planes_count].surface = dc_plane;
8112 if (new_pcrtc_state->color_mgmt_changed) {
8113 bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
8114 bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
8115 bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;
8118 amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state,
8119 &bundle->scaling_infos[planes_count]);
8121 bundle->surface_updates[planes_count].scaling_info =
8122 &bundle->scaling_infos[planes_count];
8124 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
8126 pflip_present = pflip_present || plane_needs_flip;
8128 if (!plane_needs_flip) {
8133 fill_dc_plane_info_and_addr(
8134 dm->adev, new_plane_state,
8136 &bundle->plane_infos[planes_count],
8137 &bundle->flip_addrs[planes_count].address,
8138 afb->tmz_surface, false);
8140 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n",
8141 new_plane_state->plane->index,
8142 bundle->plane_infos[planes_count].dcc.enable);
8144 bundle->surface_updates[planes_count].plane_info =
8145 &bundle->plane_infos[planes_count];
8147 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled ||
8148 acrtc_state->stream->link->replay_settings.replay_feature_enabled) {
8149 fill_dc_dirty_rects(plane, old_plane_state,
8150 new_plane_state, new_crtc_state,
8151 &bundle->flip_addrs[planes_count],
8152 &dirty_rects_changed);
8155 * If the dirty regions changed, PSR-SU need to be disabled temporarily
8156 * and enabled it again after dirty regions are stable to avoid video glitch.
8157 * PSR-SU will be enabled in vblank_control_worker() if user pause the video
8158 * during the PSR-SU was disabled.
8160 if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8161 acrtc_attach->dm_irq_params.allow_psr_entry &&
8162 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8163 !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8165 dirty_rects_changed) {
8166 mutex_lock(&dm->dc_lock);
8167 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns =
8169 if (acrtc_state->stream->link->psr_settings.psr_allow_active)
8170 amdgpu_dm_psr_disable(acrtc_state->stream);
8171 mutex_unlock(&dm->dc_lock);
8176 * Only allow immediate flips for fast updates that don't
8177 * change memory domain, FB pitch, DCC state, rotation or
8180 * dm_crtc_helper_atomic_check() only accepts async flips with
8183 if (crtc->state->async_flip &&
8184 (acrtc_state->update_type != UPDATE_TYPE_FAST ||
8185 get_mem_type(old_plane_state->fb) != get_mem_type(fb)))
8186 drm_warn_once(state->dev,
8187 "[PLANE:%d:%s] async flip with non-fast update\n",
8188 plane->base.id, plane->name);
8190 bundle->flip_addrs[planes_count].flip_immediate =
8191 crtc->state->async_flip &&
8192 acrtc_state->update_type == UPDATE_TYPE_FAST &&
8193 get_mem_type(old_plane_state->fb) == get_mem_type(fb);
8195 timestamp_ns = ktime_get_ns();
8196 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
8197 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
8198 bundle->surface_updates[planes_count].surface = dc_plane;
8200 if (!bundle->surface_updates[planes_count].surface) {
8201 DRM_ERROR("No surface for CRTC: id=%d\n",
8202 acrtc_attach->crtc_id);
8206 if (plane == pcrtc->primary)
8207 update_freesync_state_on_stream(
8210 acrtc_state->stream,
8212 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
8214 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n",
8216 bundle->flip_addrs[planes_count].address.grph.addr.high_part,
8217 bundle->flip_addrs[planes_count].address.grph.addr.low_part);
8223 if (pflip_present) {
8225 /* Use old throttling in non-vrr fixed refresh rate mode
8226 * to keep flip scheduling based on target vblank counts
8227 * working in a backwards compatible way, e.g., for
8228 * clients using the GLX_OML_sync_control extension or
8229 * DRI3/Present extension with defined target_msc.
8231 last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);
8233 /* For variable refresh rate mode only:
8234 * Get vblank of last completed flip to avoid > 1 vrr
8235 * flips per video frame by use of throttling, but allow
8236 * flip programming anywhere in the possibly large
8237 * variable vrr vblank interval for fine-grained flip
8238 * timing control and more opportunity to avoid stutter
8239 * on late submission of flips.
8241 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8242 last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank;
8243 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8246 target_vblank = last_flip_vblank + wait_for_vblank;
8249 * Wait until we're out of the vertical blank period before the one
8250 * targeted by the flip
8252 while ((acrtc_attach->enabled &&
8253 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
8254 0, &vpos, &hpos, NULL,
8255 NULL, &pcrtc->hwmode)
8256 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
8257 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
8258 (int)(target_vblank -
8259 amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) {
8260 usleep_range(1000, 1100);
8264 * Prepare the flip event for the pageflip interrupt to handle.
8266 * This only works in the case where we've already turned on the
8267 * appropriate hardware blocks (eg. HUBP) so in the transition case
8268 * from 0 -> n planes we have to skip a hardware generated event
8269 * and rely on sending it from software.
8271 if (acrtc_attach->base.state->event &&
8272 acrtc_state->active_planes > 0) {
8273 drm_crtc_vblank_get(pcrtc);
8275 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8277 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
8278 prepare_flip_isr(acrtc_attach);
8280 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8283 if (acrtc_state->stream) {
8284 if (acrtc_state->freesync_vrr_info_changed)
8285 bundle->stream_update.vrr_infopacket =
8286 &acrtc_state->stream->vrr_infopacket;
8288 } else if (cursor_update && acrtc_state->active_planes > 0 &&
8289 acrtc_attach->base.state->event) {
8290 drm_crtc_vblank_get(pcrtc);
8292 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8294 acrtc_attach->event = acrtc_attach->base.state->event;
8295 acrtc_attach->base.state->event = NULL;
8297 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8300 /* Update the planes if changed or disable if we don't have any. */
8301 if ((planes_count || acrtc_state->active_planes == 0) &&
8302 acrtc_state->stream) {
8304 * If PSR or idle optimizations are enabled then flush out
8305 * any pending work before hardware programming.
8307 if (dm->vblank_control_workqueue)
8308 flush_workqueue(dm->vblank_control_workqueue);
8310 bundle->stream_update.stream = acrtc_state->stream;
8311 if (new_pcrtc_state->mode_changed) {
8312 bundle->stream_update.src = acrtc_state->stream->src;
8313 bundle->stream_update.dst = acrtc_state->stream->dst;
8316 if (new_pcrtc_state->color_mgmt_changed) {
8318 * TODO: This isn't fully correct since we've actually
8319 * already modified the stream in place.
8321 bundle->stream_update.gamut_remap =
8322 &acrtc_state->stream->gamut_remap_matrix;
8323 bundle->stream_update.output_csc_transform =
8324 &acrtc_state->stream->csc_color_matrix;
8325 bundle->stream_update.out_transfer_func =
8326 acrtc_state->stream->out_transfer_func;
8329 acrtc_state->stream->abm_level = acrtc_state->abm_level;
8330 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
8331 bundle->stream_update.abm_level = &acrtc_state->abm_level;
8333 mutex_lock(&dm->dc_lock);
8334 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8335 acrtc_state->stream->link->psr_settings.psr_allow_active)
8336 amdgpu_dm_psr_disable(acrtc_state->stream);
8337 mutex_unlock(&dm->dc_lock);
8340 * If FreeSync state on the stream has changed then we need to
8341 * re-adjust the min/max bounds now that DC doesn't handle this
8342 * as part of commit.
8344 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) {
8345 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8346 dc_stream_adjust_vmin_vmax(
8347 dm->dc, acrtc_state->stream,
8348 &acrtc_attach->dm_irq_params.vrr_params.adjust);
8349 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8351 mutex_lock(&dm->dc_lock);
8352 update_planes_and_stream_adapter(dm->dc,
8353 acrtc_state->update_type,
8355 acrtc_state->stream,
8356 &bundle->stream_update,
8357 bundle->surface_updates);
8360 * Enable or disable the interrupts on the backend.
8362 * Most pipes are put into power gating when unused.
8364 * When power gating is enabled on a pipe we lose the
8365 * interrupt enablement state when power gating is disabled.
8367 * So we need to update the IRQ control state in hardware
8368 * whenever the pipe turns on (since it could be previously
8369 * power gated) or off (since some pipes can't be power gated
8372 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes)
8373 dm_update_pflip_irq_state(drm_to_adev(dev),
8376 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8377 acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
8378 !acrtc_state->stream->link->psr_settings.psr_feature_enabled)
8379 amdgpu_dm_link_setup_psr(acrtc_state->stream);
8381 /* Decrement skip count when PSR is enabled and we're doing fast updates. */
8382 if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
8383 acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8384 struct amdgpu_dm_connector *aconn =
8385 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
8387 if (aconn->psr_skip_count > 0)
8388 aconn->psr_skip_count--;
8390 /* Allow PSR when skip count is 0. */
8391 acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count;
8394 * If sink supports PSR SU, there is no need to rely on
8395 * a vblank event disable request to enable PSR. PSR SU
8396 * can be enabled immediately once OS demonstrates an
8397 * adequate number of fast atomic commits to notify KMD
8398 * of update events. See `vblank_control_worker()`.
8400 if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8401 acrtc_attach->dm_irq_params.allow_psr_entry &&
8402 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8403 !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8405 !acrtc_state->stream->link->psr_settings.psr_allow_active &&
8407 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) >
8409 amdgpu_dm_psr_enable(acrtc_state->stream);
8411 acrtc_attach->dm_irq_params.allow_psr_entry = false;
8414 mutex_unlock(&dm->dc_lock);
8418 * Update cursor state *after* programming all the planes.
8419 * This avoids redundant programming in the case where we're going
8420 * to be disabling a single plane - those pipes are being disabled.
8422 if (acrtc_state->active_planes)
8423 amdgpu_dm_commit_cursors(state);
8429 static void amdgpu_dm_commit_audio(struct drm_device *dev,
8430 struct drm_atomic_state *state)
8432 struct amdgpu_device *adev = drm_to_adev(dev);
8433 struct amdgpu_dm_connector *aconnector;
8434 struct drm_connector *connector;
8435 struct drm_connector_state *old_con_state, *new_con_state;
8436 struct drm_crtc_state *new_crtc_state;
8437 struct dm_crtc_state *new_dm_crtc_state;
8438 const struct dc_stream_status *status;
8441 /* Notify device removals. */
8442 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8443 if (old_con_state->crtc != new_con_state->crtc) {
8444 /* CRTC changes require notification. */
8448 if (!new_con_state->crtc)
8451 new_crtc_state = drm_atomic_get_new_crtc_state(
8452 state, new_con_state->crtc);
8454 if (!new_crtc_state)
8457 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8461 aconnector = to_amdgpu_dm_connector(connector);
8463 mutex_lock(&adev->dm.audio_lock);
8464 inst = aconnector->audio_inst;
8465 aconnector->audio_inst = -1;
8466 mutex_unlock(&adev->dm.audio_lock);
8468 amdgpu_dm_audio_eld_notify(adev, inst);
8471 /* Notify audio device additions. */
8472 for_each_new_connector_in_state(state, connector, new_con_state, i) {
8473 if (!new_con_state->crtc)
8476 new_crtc_state = drm_atomic_get_new_crtc_state(
8477 state, new_con_state->crtc);
8479 if (!new_crtc_state)
8482 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8485 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
8486 if (!new_dm_crtc_state->stream)
8489 status = dc_stream_get_status(new_dm_crtc_state->stream);
8493 aconnector = to_amdgpu_dm_connector(connector);
8495 mutex_lock(&adev->dm.audio_lock);
8496 inst = status->audio_inst;
8497 aconnector->audio_inst = inst;
8498 mutex_unlock(&adev->dm.audio_lock);
8500 amdgpu_dm_audio_eld_notify(adev, inst);
8505 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
8506 * @crtc_state: the DRM CRTC state
8507 * @stream_state: the DC stream state.
8509 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
8510 * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
8512 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
8513 struct dc_stream_state *stream_state)
8515 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
8518 static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,
8519 struct dc_state *dc_state)
8521 struct drm_device *dev = state->dev;
8522 struct amdgpu_device *adev = drm_to_adev(dev);
8523 struct amdgpu_display_manager *dm = &adev->dm;
8524 struct drm_crtc *crtc;
8525 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8526 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8527 bool mode_set_reset_required = false;
8530 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
8531 new_crtc_state, i) {
8532 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8534 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8536 if (old_crtc_state->active &&
8537 (!new_crtc_state->active ||
8538 drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8539 manage_dm_interrupts(adev, acrtc, false);
8540 dc_stream_release(dm_old_crtc_state->stream);
8544 drm_atomic_helper_calc_timestamping_constants(state);
8546 /* update changed items */
8547 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8548 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8550 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8551 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8553 drm_dbg_state(state->dev,
8554 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n",
8556 new_crtc_state->enable,
8557 new_crtc_state->active,
8558 new_crtc_state->planes_changed,
8559 new_crtc_state->mode_changed,
8560 new_crtc_state->active_changed,
8561 new_crtc_state->connectors_changed);
8563 /* Disable cursor if disabling crtc */
8564 if (old_crtc_state->active && !new_crtc_state->active) {
8565 struct dc_cursor_position position;
8567 memset(&position, 0, sizeof(position));
8568 mutex_lock(&dm->dc_lock);
8569 dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position);
8570 mutex_unlock(&dm->dc_lock);
8573 /* Copy all transient state flags into dc state */
8574 if (dm_new_crtc_state->stream) {
8575 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
8576 dm_new_crtc_state->stream);
8579 /* handles headless hotplug case, updating new_state and
8580 * aconnector as needed
8583 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
8585 DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
8587 if (!dm_new_crtc_state->stream) {
8589 * this could happen because of issues with
8590 * userspace notifications delivery.
8591 * In this case userspace tries to set mode on
8592 * display which is disconnected in fact.
8593 * dc_sink is NULL in this case on aconnector.
8594 * We expect reset mode will come soon.
8596 * This can also happen when unplug is done
8597 * during resume sequence ended
8599 * In this case, we want to pretend we still
8600 * have a sink to keep the pipe running so that
8601 * hw state is consistent with the sw state
8603 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
8604 __func__, acrtc->base.base.id);
8608 if (dm_old_crtc_state->stream)
8609 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8611 pm_runtime_get_noresume(dev->dev);
8613 acrtc->enabled = true;
8614 acrtc->hw_mode = new_crtc_state->mode;
8615 crtc->hwmode = new_crtc_state->mode;
8616 mode_set_reset_required = true;
8617 } else if (modereset_required(new_crtc_state)) {
8618 DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
8619 /* i.e. reset mode */
8620 if (dm_old_crtc_state->stream)
8621 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8623 mode_set_reset_required = true;
8625 } /* for_each_crtc_in_state() */
8627 /* if there mode set or reset, disable eDP PSR */
8628 if (mode_set_reset_required) {
8629 if (dm->vblank_control_workqueue)
8630 flush_workqueue(dm->vblank_control_workqueue);
8632 amdgpu_dm_psr_disable_all(dm);
8635 dm_enable_per_frame_crtc_master_sync(dc_state);
8636 mutex_lock(&dm->dc_lock);
8637 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
8639 /* Allow idle optimization when vblank count is 0 for display off */
8640 if (dm->active_vblank_irq_count == 0)
8641 dc_allow_idle_optimizations(dm->dc, true);
8642 mutex_unlock(&dm->dc_lock);
8644 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8645 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8647 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8649 if (dm_new_crtc_state->stream != NULL) {
8650 const struct dc_stream_status *status =
8651 dc_stream_get_status(dm_new_crtc_state->stream);
8654 status = dc_stream_get_status_from_state(dc_state,
8655 dm_new_crtc_state->stream);
8657 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
8659 acrtc->otg_inst = status->primary_otg_inst;
8665 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
8666 * @state: The atomic state to commit
8668 * This will tell DC to commit the constructed DC state from atomic_check,
8669 * programming the hardware. Any failures here implies a hardware failure, since
8670 * atomic check should have filtered anything non-kosher.
8672 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
8674 struct drm_device *dev = state->dev;
8675 struct amdgpu_device *adev = drm_to_adev(dev);
8676 struct amdgpu_display_manager *dm = &adev->dm;
8677 struct dm_atomic_state *dm_state;
8678 struct dc_state *dc_state = NULL;
8680 struct drm_crtc *crtc;
8681 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8682 unsigned long flags;
8683 bool wait_for_vblank = true;
8684 struct drm_connector *connector;
8685 struct drm_connector_state *old_con_state, *new_con_state;
8686 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8687 int crtc_disable_count = 0;
8689 trace_amdgpu_dm_atomic_commit_tail_begin(state);
8691 drm_atomic_helper_update_legacy_modeset_state(dev, state);
8692 drm_dp_mst_atomic_wait_for_dependencies(state);
8694 dm_state = dm_atomic_get_new_state(state);
8695 if (dm_state && dm_state->context) {
8696 dc_state = dm_state->context;
8697 amdgpu_dm_commit_streams(state, dc_state);
8700 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8701 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8702 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8703 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8705 if (!adev->dm.hdcp_workqueue)
8708 pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i);
8713 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
8714 connector->index, connector->status, connector->dpms);
8715 pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
8716 old_con_state->content_protection, new_con_state->content_protection);
8718 if (aconnector->dc_sink) {
8719 if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
8720 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) {
8721 pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n",
8722 aconnector->dc_sink->edid_caps.display_name);
8726 new_crtc_state = NULL;
8727 old_crtc_state = NULL;
8730 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8731 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8735 pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8736 old_crtc_state->enable,
8737 old_crtc_state->active,
8738 old_crtc_state->mode_changed,
8739 old_crtc_state->active_changed,
8740 old_crtc_state->connectors_changed);
8743 pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8744 new_crtc_state->enable,
8745 new_crtc_state->active,
8746 new_crtc_state->mode_changed,
8747 new_crtc_state->active_changed,
8748 new_crtc_state->connectors_changed);
8751 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8752 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8753 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8754 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8756 if (!adev->dm.hdcp_workqueue)
8759 new_crtc_state = NULL;
8760 old_crtc_state = NULL;
8763 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8764 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8767 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8769 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
8770 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
8771 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
8772 new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
8773 dm_new_con_state->update_hdcp = true;
8777 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state,
8778 old_con_state, connector, adev->dm.hdcp_workqueue)) {
8779 /* when display is unplugged from mst hub, connctor will
8780 * be destroyed within dm_dp_mst_connector_destroy. connector
8781 * hdcp perperties, like type, undesired, desired, enabled,
8782 * will be lost. So, save hdcp properties into hdcp_work within
8783 * amdgpu_dm_atomic_commit_tail. if the same display is
8784 * plugged back with same display index, its hdcp properties
8785 * will be retrieved from hdcp_work within dm_dp_mst_get_modes
8788 bool enable_encryption = false;
8790 if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED)
8791 enable_encryption = true;
8793 if (aconnector->dc_link && aconnector->dc_sink &&
8794 aconnector->dc_link->type == dc_connection_mst_branch) {
8795 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
8796 struct hdcp_workqueue *hdcp_w =
8797 &hdcp_work[aconnector->dc_link->link_index];
8799 hdcp_w->hdcp_content_type[connector->index] =
8800 new_con_state->hdcp_content_type;
8801 hdcp_w->content_protection[connector->index] =
8802 new_con_state->content_protection;
8805 if (new_crtc_state && new_crtc_state->mode_changed &&
8806 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED)
8807 enable_encryption = true;
8809 DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption);
8811 hdcp_update_display(
8812 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
8813 new_con_state->hdcp_content_type, enable_encryption);
8817 /* Handle connector state changes */
8818 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8819 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8820 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
8821 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8822 struct dc_surface_update *dummy_updates;
8823 struct dc_stream_update stream_update;
8824 struct dc_info_packet hdr_packet;
8825 struct dc_stream_status *status = NULL;
8826 bool abm_changed, hdr_changed, scaling_changed;
8828 memset(&stream_update, 0, sizeof(stream_update));
8831 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8832 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8835 /* Skip any modesets/resets */
8836 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
8839 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8840 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8842 scaling_changed = is_scaling_state_different(dm_new_con_state,
8845 abm_changed = dm_new_crtc_state->abm_level !=
8846 dm_old_crtc_state->abm_level;
8849 !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state);
8851 if (!scaling_changed && !abm_changed && !hdr_changed)
8854 stream_update.stream = dm_new_crtc_state->stream;
8855 if (scaling_changed) {
8856 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
8857 dm_new_con_state, dm_new_crtc_state->stream);
8859 stream_update.src = dm_new_crtc_state->stream->src;
8860 stream_update.dst = dm_new_crtc_state->stream->dst;
8864 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
8866 stream_update.abm_level = &dm_new_crtc_state->abm_level;
8870 fill_hdr_info_packet(new_con_state, &hdr_packet);
8871 stream_update.hdr_static_metadata = &hdr_packet;
8874 status = dc_stream_get_status(dm_new_crtc_state->stream);
8876 if (WARN_ON(!status))
8879 WARN_ON(!status->plane_count);
8882 * TODO: DC refuses to perform stream updates without a dc_surface_update.
8883 * Here we create an empty update on each plane.
8884 * To fix this, DC should permit updating only stream properties.
8886 dummy_updates = kzalloc(sizeof(struct dc_surface_update) * MAX_SURFACES, GFP_ATOMIC);
8887 for (j = 0; j < status->plane_count; j++)
8888 dummy_updates[j].surface = status->plane_states[0];
8891 mutex_lock(&dm->dc_lock);
8892 dc_update_planes_and_stream(dm->dc,
8894 status->plane_count,
8895 dm_new_crtc_state->stream,
8897 mutex_unlock(&dm->dc_lock);
8898 kfree(dummy_updates);
8902 * Enable interrupts for CRTCs that are newly enabled or went through
8903 * a modeset. It was intentionally deferred until after the front end
8904 * state was modified to wait until the OTG was on and so the IRQ
8905 * handlers didn't access stale or invalid state.
8907 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8908 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8909 #ifdef CONFIG_DEBUG_FS
8910 enum amdgpu_dm_pipe_crc_source cur_crc_src;
8912 /* Count number of newly disabled CRTCs for dropping PM refs later. */
8913 if (old_crtc_state->active && !new_crtc_state->active)
8914 crtc_disable_count++;
8916 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8917 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8919 /* For freesync config update on crtc state and params for irq */
8920 update_stream_irq_parameters(dm, dm_new_crtc_state);
8922 #ifdef CONFIG_DEBUG_FS
8923 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8924 cur_crc_src = acrtc->dm_irq_params.crc_src;
8925 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8928 if (new_crtc_state->active &&
8929 (!old_crtc_state->active ||
8930 drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8931 dc_stream_retain(dm_new_crtc_state->stream);
8932 acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
8933 manage_dm_interrupts(adev, acrtc, true);
8935 /* Handle vrr on->off / off->on transitions */
8936 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state);
8938 #ifdef CONFIG_DEBUG_FS
8939 if (new_crtc_state->active &&
8940 (!old_crtc_state->active ||
8941 drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8943 * Frontend may have changed so reapply the CRC capture
8944 * settings for the stream.
8946 if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
8947 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
8948 if (amdgpu_dm_crc_window_is_activated(crtc)) {
8949 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8950 acrtc->dm_irq_params.window_param.update_win = true;
8953 * It takes 2 frames for HW to stably generate CRC when
8954 * resuming from suspend, so we set skip_frame_cnt 2.
8956 acrtc->dm_irq_params.window_param.skip_frame_cnt = 2;
8957 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8960 if (amdgpu_dm_crtc_configure_crc_source(
8961 crtc, dm_new_crtc_state, cur_crc_src))
8962 DRM_DEBUG_DRIVER("Failed to configure crc source");
8968 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
8969 if (new_crtc_state->async_flip)
8970 wait_for_vblank = false;
8972 /* update planes when needed per crtc*/
8973 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
8974 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8976 if (dm_new_crtc_state->stream)
8977 amdgpu_dm_commit_planes(state, dev, dm, crtc, wait_for_vblank);
8980 /* Update audio instances for each connector. */
8981 amdgpu_dm_commit_audio(dev, state);
8983 /* restore the backlight level */
8984 for (i = 0; i < dm->num_of_edps; i++) {
8985 if (dm->backlight_dev[i] &&
8986 (dm->actual_brightness[i] != dm->brightness[i]))
8987 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
8991 * send vblank event on all events not handled in flip and
8992 * mark consumed event for drm_atomic_helper_commit_hw_done
8994 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8995 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8997 if (new_crtc_state->event)
8998 drm_send_event_locked(dev, &new_crtc_state->event->base);
9000 new_crtc_state->event = NULL;
9002 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
9004 /* Signal HW programming completion */
9005 drm_atomic_helper_commit_hw_done(state);
9007 if (wait_for_vblank)
9008 drm_atomic_helper_wait_for_flip_done(dev, state);
9010 drm_atomic_helper_cleanup_planes(dev, state);
9012 /* Don't free the memory if we are hitting this as part of suspend.
9013 * This way we don't free any memory during suspend; see
9014 * amdgpu_bo_free_kernel(). The memory will be freed in the first
9015 * non-suspend modeset or when the driver is torn down.
9017 if (!adev->in_suspend) {
9018 /* return the stolen vga memory back to VRAM */
9019 if (!adev->mman.keep_stolen_vga_memory)
9020 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
9021 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
9025 * Finally, drop a runtime PM reference for each newly disabled CRTC,
9026 * so we can put the GPU into runtime suspend if we're not driving any
9029 for (i = 0; i < crtc_disable_count; i++)
9030 pm_runtime_put_autosuspend(dev->dev);
9031 pm_runtime_mark_last_busy(dev->dev);
9034 static int dm_force_atomic_commit(struct drm_connector *connector)
9037 struct drm_device *ddev = connector->dev;
9038 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
9039 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
9040 struct drm_plane *plane = disconnected_acrtc->base.primary;
9041 struct drm_connector_state *conn_state;
9042 struct drm_crtc_state *crtc_state;
9043 struct drm_plane_state *plane_state;
9048 state->acquire_ctx = ddev->mode_config.acquire_ctx;
9050 /* Construct an atomic state to restore previous display setting */
9053 * Attach connectors to drm_atomic_state
9055 conn_state = drm_atomic_get_connector_state(state, connector);
9057 ret = PTR_ERR_OR_ZERO(conn_state);
9061 /* Attach crtc to drm_atomic_state*/
9062 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
9064 ret = PTR_ERR_OR_ZERO(crtc_state);
9068 /* force a restore */
9069 crtc_state->mode_changed = true;
9071 /* Attach plane to drm_atomic_state */
9072 plane_state = drm_atomic_get_plane_state(state, plane);
9074 ret = PTR_ERR_OR_ZERO(plane_state);
9078 /* Call commit internally with the state we just constructed */
9079 ret = drm_atomic_commit(state);
9082 drm_atomic_state_put(state);
9084 DRM_ERROR("Restoring old state failed with %i\n", ret);
9090 * This function handles all cases when set mode does not come upon hotplug.
9091 * This includes when a display is unplugged then plugged back into the
9092 * same port and when running without usermode desktop manager supprot
9094 void dm_restore_drm_connector_state(struct drm_device *dev,
9095 struct drm_connector *connector)
9097 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
9098 struct amdgpu_crtc *disconnected_acrtc;
9099 struct dm_crtc_state *acrtc_state;
9101 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
9104 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
9105 if (!disconnected_acrtc)
9108 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
9109 if (!acrtc_state->stream)
9113 * If the previous sink is not released and different from the current,
9114 * we deduce we are in a state where we can not rely on usermode call
9115 * to turn on the display, so we do it here
9117 if (acrtc_state->stream->sink != aconnector->dc_sink)
9118 dm_force_atomic_commit(&aconnector->base);
9122 * Grabs all modesetting locks to serialize against any blocking commits,
9123 * Waits for completion of all non blocking commits.
9125 static int do_aquire_global_lock(struct drm_device *dev,
9126 struct drm_atomic_state *state)
9128 struct drm_crtc *crtc;
9129 struct drm_crtc_commit *commit;
9133 * Adding all modeset locks to aquire_ctx will
9134 * ensure that when the framework release it the
9135 * extra locks we are locking here will get released to
9137 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
9141 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9142 spin_lock(&crtc->commit_lock);
9143 commit = list_first_entry_or_null(&crtc->commit_list,
9144 struct drm_crtc_commit, commit_entry);
9146 drm_crtc_commit_get(commit);
9147 spin_unlock(&crtc->commit_lock);
9153 * Make sure all pending HW programming completed and
9156 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
9159 ret = wait_for_completion_interruptible_timeout(
9160 &commit->flip_done, 10*HZ);
9163 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done timed out\n",
9164 crtc->base.id, crtc->name);
9166 drm_crtc_commit_put(commit);
9169 return ret < 0 ? ret : 0;
9172 static void get_freesync_config_for_crtc(
9173 struct dm_crtc_state *new_crtc_state,
9174 struct dm_connector_state *new_con_state)
9176 struct mod_freesync_config config = {0};
9177 struct amdgpu_dm_connector *aconnector =
9178 to_amdgpu_dm_connector(new_con_state->base.connector);
9179 struct drm_display_mode *mode = &new_crtc_state->base.mode;
9180 int vrefresh = drm_mode_vrefresh(mode);
9181 bool fs_vid_mode = false;
9183 new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
9184 vrefresh >= aconnector->min_vfreq &&
9185 vrefresh <= aconnector->max_vfreq;
9187 if (new_crtc_state->vrr_supported) {
9188 new_crtc_state->stream->ignore_msa_timing_param = true;
9189 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
9191 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000;
9192 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000;
9193 config.vsif_supported = true;
9197 config.state = VRR_STATE_ACTIVE_FIXED;
9198 config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz;
9200 } else if (new_crtc_state->base.vrr_enabled) {
9201 config.state = VRR_STATE_ACTIVE_VARIABLE;
9203 config.state = VRR_STATE_INACTIVE;
9207 new_crtc_state->freesync_config = config;
9210 static void reset_freesync_config_for_crtc(
9211 struct dm_crtc_state *new_crtc_state)
9213 new_crtc_state->vrr_supported = false;
9215 memset(&new_crtc_state->vrr_infopacket, 0,
9216 sizeof(new_crtc_state->vrr_infopacket));
9220 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
9221 struct drm_crtc_state *new_crtc_state)
9223 const struct drm_display_mode *old_mode, *new_mode;
9225 if (!old_crtc_state || !new_crtc_state)
9228 old_mode = &old_crtc_state->mode;
9229 new_mode = &new_crtc_state->mode;
9231 if (old_mode->clock == new_mode->clock &&
9232 old_mode->hdisplay == new_mode->hdisplay &&
9233 old_mode->vdisplay == new_mode->vdisplay &&
9234 old_mode->htotal == new_mode->htotal &&
9235 old_mode->vtotal != new_mode->vtotal &&
9236 old_mode->hsync_start == new_mode->hsync_start &&
9237 old_mode->vsync_start != new_mode->vsync_start &&
9238 old_mode->hsync_end == new_mode->hsync_end &&
9239 old_mode->vsync_end != new_mode->vsync_end &&
9240 old_mode->hskew == new_mode->hskew &&
9241 old_mode->vscan == new_mode->vscan &&
9242 (old_mode->vsync_end - old_mode->vsync_start) ==
9243 (new_mode->vsync_end - new_mode->vsync_start))
9249 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state)
9252 struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
9254 dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;
9256 num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000;
9257 den = (unsigned long long)new_crtc_state->mode.htotal *
9258 (unsigned long long)new_crtc_state->mode.vtotal;
9260 res = div_u64(num, den);
9261 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
9264 static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
9265 struct drm_atomic_state *state,
9266 struct drm_crtc *crtc,
9267 struct drm_crtc_state *old_crtc_state,
9268 struct drm_crtc_state *new_crtc_state,
9270 bool *lock_and_validation_needed)
9272 struct dm_atomic_state *dm_state = NULL;
9273 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9274 struct dc_stream_state *new_stream;
9278 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
9279 * update changed items
9281 struct amdgpu_crtc *acrtc = NULL;
9282 struct amdgpu_dm_connector *aconnector = NULL;
9283 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
9284 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
9288 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9289 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9290 acrtc = to_amdgpu_crtc(crtc);
9291 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
9293 /* TODO This hack should go away */
9294 if (aconnector && enable) {
9295 /* Make sure fake sink is created in plug-in scenario */
9296 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
9298 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
9301 if (IS_ERR(drm_new_conn_state)) {
9302 ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
9306 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
9307 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
9309 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9312 new_stream = create_validate_stream_for_sink(aconnector,
9313 &new_crtc_state->mode,
9315 dm_old_crtc_state->stream);
9318 * we can have no stream on ACTION_SET if a display
9319 * was disconnected during S3, in this case it is not an
9320 * error, the OS will be updated after detection, and
9321 * will do the right thing on next atomic commit
9325 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
9326 __func__, acrtc->base.base.id);
9332 * TODO: Check VSDB bits to decide whether this should
9333 * be enabled or not.
9335 new_stream->triggered_crtc_reset.enabled =
9336 dm->force_timing_sync;
9338 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9340 ret = fill_hdr_info_packet(drm_new_conn_state,
9341 &new_stream->hdr_static_metadata);
9346 * If we already removed the old stream from the context
9347 * (and set the new stream to NULL) then we can't reuse
9348 * the old stream even if the stream and scaling are unchanged.
9349 * We'll hit the BUG_ON and black screen.
9351 * TODO: Refactor this function to allow this check to work
9352 * in all conditions.
9354 if (dm_new_crtc_state->stream &&
9355 is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))
9358 if (dm_new_crtc_state->stream &&
9359 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9360 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
9361 new_crtc_state->mode_changed = false;
9362 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
9363 new_crtc_state->mode_changed);
9367 /* mode_changed flag may get updated above, need to check again */
9368 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9371 drm_dbg_state(state->dev,
9372 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n",
9374 new_crtc_state->enable,
9375 new_crtc_state->active,
9376 new_crtc_state->planes_changed,
9377 new_crtc_state->mode_changed,
9378 new_crtc_state->active_changed,
9379 new_crtc_state->connectors_changed);
9381 /* Remove stream for any changed/disabled CRTC */
9384 if (!dm_old_crtc_state->stream)
9387 /* Unset freesync video if it was active before */
9388 if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) {
9389 dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE;
9390 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0;
9393 /* Now check if we should set freesync video mode */
9394 if (dm_new_crtc_state->stream &&
9395 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9396 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream) &&
9397 is_timing_unchanged_for_freesync(new_crtc_state,
9399 new_crtc_state->mode_changed = false;
9401 "Mode change not required for front porch change, setting mode_changed to %d",
9402 new_crtc_state->mode_changed);
9404 set_freesync_fixed_config(dm_new_crtc_state);
9407 } else if (aconnector &&
9408 is_freesync_video_mode(&new_crtc_state->mode,
9410 struct drm_display_mode *high_mode;
9412 high_mode = get_highest_refresh_rate_mode(aconnector, false);
9413 if (!drm_mode_equal(&new_crtc_state->mode, high_mode))
9414 set_freesync_fixed_config(dm_new_crtc_state);
9417 ret = dm_atomic_get_state(state, &dm_state);
9421 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
9424 /* i.e. reset mode */
9425 if (dc_remove_stream_from_ctx(
9428 dm_old_crtc_state->stream) != DC_OK) {
9433 dc_stream_release(dm_old_crtc_state->stream);
9434 dm_new_crtc_state->stream = NULL;
9436 reset_freesync_config_for_crtc(dm_new_crtc_state);
9438 *lock_and_validation_needed = true;
9440 } else {/* Add stream for any updated/enabled CRTC */
9442 * Quick fix to prevent NULL pointer on new_stream when
9443 * added MST connectors not found in existing crtc_state in the chained mode
9444 * TODO: need to dig out the root cause of that
9449 if (modereset_required(new_crtc_state))
9452 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream,
9453 dm_old_crtc_state->stream)) {
9455 WARN_ON(dm_new_crtc_state->stream);
9457 ret = dm_atomic_get_state(state, &dm_state);
9461 dm_new_crtc_state->stream = new_stream;
9463 dc_stream_retain(new_stream);
9465 DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n",
9468 if (dc_add_stream_to_ctx(
9471 dm_new_crtc_state->stream) != DC_OK) {
9476 *lock_and_validation_needed = true;
9481 /* Release extra reference */
9483 dc_stream_release(new_stream);
9486 * We want to do dc stream updates that do not require a
9487 * full modeset below.
9489 if (!(enable && aconnector && new_crtc_state->active))
9492 * Given above conditions, the dc state cannot be NULL because:
9493 * 1. We're in the process of enabling CRTCs (just been added
9494 * to the dc context, or already is on the context)
9495 * 2. Has a valid connector attached, and
9496 * 3. Is currently active and enabled.
9497 * => The dc stream state currently exists.
9499 BUG_ON(dm_new_crtc_state->stream == NULL);
9501 /* Scaling or underscan settings */
9502 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) ||
9503 drm_atomic_crtc_needs_modeset(new_crtc_state))
9504 update_stream_scaling_settings(
9505 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
9508 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9511 * Color management settings. We also update color properties
9512 * when a modeset is needed, to ensure it gets reprogrammed.
9514 if (dm_new_crtc_state->base.color_mgmt_changed ||
9515 drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9516 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
9521 /* Update Freesync settings. */
9522 get_freesync_config_for_crtc(dm_new_crtc_state,
9529 dc_stream_release(new_stream);
9533 static bool should_reset_plane(struct drm_atomic_state *state,
9534 struct drm_plane *plane,
9535 struct drm_plane_state *old_plane_state,
9536 struct drm_plane_state *new_plane_state)
9538 struct drm_plane *other;
9539 struct drm_plane_state *old_other_state, *new_other_state;
9540 struct drm_crtc_state *new_crtc_state;
9544 * TODO: Remove this hack once the checks below are sufficient
9545 * enough to determine when we need to reset all the planes on
9548 if (state->allow_modeset)
9551 /* Exit early if we know that we're adding or removing the plane. */
9552 if (old_plane_state->crtc != new_plane_state->crtc)
9555 /* old crtc == new_crtc == NULL, plane not in context. */
9556 if (!new_plane_state->crtc)
9560 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
9562 if (!new_crtc_state)
9565 /* CRTC Degamma changes currently require us to recreate planes. */
9566 if (new_crtc_state->color_mgmt_changed)
9569 if (drm_atomic_crtc_needs_modeset(new_crtc_state))
9573 * If there are any new primary or overlay planes being added or
9574 * removed then the z-order can potentially change. To ensure
9575 * correct z-order and pipe acquisition the current DC architecture
9576 * requires us to remove and recreate all existing planes.
9578 * TODO: Come up with a more elegant solution for this.
9580 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
9581 struct amdgpu_framebuffer *old_afb, *new_afb;
9583 if (other->type == DRM_PLANE_TYPE_CURSOR)
9586 if (old_other_state->crtc != new_plane_state->crtc &&
9587 new_other_state->crtc != new_plane_state->crtc)
9590 if (old_other_state->crtc != new_other_state->crtc)
9593 /* Src/dst size and scaling updates. */
9594 if (old_other_state->src_w != new_other_state->src_w ||
9595 old_other_state->src_h != new_other_state->src_h ||
9596 old_other_state->crtc_w != new_other_state->crtc_w ||
9597 old_other_state->crtc_h != new_other_state->crtc_h)
9600 /* Rotation / mirroring updates. */
9601 if (old_other_state->rotation != new_other_state->rotation)
9604 /* Blending updates. */
9605 if (old_other_state->pixel_blend_mode !=
9606 new_other_state->pixel_blend_mode)
9609 /* Alpha updates. */
9610 if (old_other_state->alpha != new_other_state->alpha)
9613 /* Colorspace changes. */
9614 if (old_other_state->color_range != new_other_state->color_range ||
9615 old_other_state->color_encoding != new_other_state->color_encoding)
9618 /* Framebuffer checks fall at the end. */
9619 if (!old_other_state->fb || !new_other_state->fb)
9622 /* Pixel format changes can require bandwidth updates. */
9623 if (old_other_state->fb->format != new_other_state->fb->format)
9626 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb;
9627 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb;
9629 /* Tiling and DCC changes also require bandwidth updates. */
9630 if (old_afb->tiling_flags != new_afb->tiling_flags ||
9631 old_afb->base.modifier != new_afb->base.modifier)
9638 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,
9639 struct drm_plane_state *new_plane_state,
9640 struct drm_framebuffer *fb)
9642 struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev);
9643 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
9647 if (fb->width > new_acrtc->max_cursor_width ||
9648 fb->height > new_acrtc->max_cursor_height) {
9649 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n",
9650 new_plane_state->fb->width,
9651 new_plane_state->fb->height);
9654 if (new_plane_state->src_w != fb->width << 16 ||
9655 new_plane_state->src_h != fb->height << 16) {
9656 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9660 /* Pitch in pixels */
9661 pitch = fb->pitches[0] / fb->format->cpp[0];
9663 if (fb->width != pitch) {
9664 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d",
9673 /* FB pitch is supported by cursor plane */
9676 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch);
9680 /* Core DRM takes care of checking FB modifiers, so we only need to
9681 * check tiling flags when the FB doesn't have a modifier.
9683 if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) {
9684 if (adev->family < AMDGPU_FAMILY_AI) {
9685 linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &&
9686 AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &&
9687 AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0;
9689 linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;
9692 DRM_DEBUG_ATOMIC("Cursor FB not linear");
9700 static int dm_update_plane_state(struct dc *dc,
9701 struct drm_atomic_state *state,
9702 struct drm_plane *plane,
9703 struct drm_plane_state *old_plane_state,
9704 struct drm_plane_state *new_plane_state,
9706 bool *lock_and_validation_needed,
9707 bool *is_top_most_overlay)
9710 struct dm_atomic_state *dm_state = NULL;
9711 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
9712 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9713 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
9714 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
9715 struct amdgpu_crtc *new_acrtc;
9720 new_plane_crtc = new_plane_state->crtc;
9721 old_plane_crtc = old_plane_state->crtc;
9722 dm_new_plane_state = to_dm_plane_state(new_plane_state);
9723 dm_old_plane_state = to_dm_plane_state(old_plane_state);
9725 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
9726 if (!enable || !new_plane_crtc ||
9727 drm_atomic_plane_disabling(plane->state, new_plane_state))
9730 new_acrtc = to_amdgpu_crtc(new_plane_crtc);
9732 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) {
9733 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9737 if (new_plane_state->fb) {
9738 ret = dm_check_cursor_fb(new_acrtc, new_plane_state,
9739 new_plane_state->fb);
9747 needs_reset = should_reset_plane(state, plane, old_plane_state,
9750 /* Remove any changed/removed planes */
9755 if (!old_plane_crtc)
9758 old_crtc_state = drm_atomic_get_old_crtc_state(
9759 state, old_plane_crtc);
9760 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9762 if (!dm_old_crtc_state->stream)
9765 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
9766 plane->base.id, old_plane_crtc->base.id);
9768 ret = dm_atomic_get_state(state, &dm_state);
9772 if (!dc_remove_plane_from_context(
9774 dm_old_crtc_state->stream,
9775 dm_old_plane_state->dc_state,
9776 dm_state->context)) {
9781 if (dm_old_plane_state->dc_state)
9782 dc_plane_state_release(dm_old_plane_state->dc_state);
9784 dm_new_plane_state->dc_state = NULL;
9786 *lock_and_validation_needed = true;
9788 } else { /* Add new planes */
9789 struct dc_plane_state *dc_new_plane_state;
9791 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
9794 if (!new_plane_crtc)
9797 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
9798 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9800 if (!dm_new_crtc_state->stream)
9806 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state);
9810 WARN_ON(dm_new_plane_state->dc_state);
9812 dc_new_plane_state = dc_create_plane_state(dc);
9813 if (!dc_new_plane_state)
9816 /* Block top most plane from being a video plane */
9817 if (plane->type == DRM_PLANE_TYPE_OVERLAY) {
9818 if (is_video_format(new_plane_state->fb->format->format) && *is_top_most_overlay)
9821 *is_top_most_overlay = false;
9824 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n",
9825 plane->base.id, new_plane_crtc->base.id);
9827 ret = fill_dc_plane_attributes(
9828 drm_to_adev(new_plane_crtc->dev),
9833 dc_plane_state_release(dc_new_plane_state);
9837 ret = dm_atomic_get_state(state, &dm_state);
9839 dc_plane_state_release(dc_new_plane_state);
9844 * Any atomic check errors that occur after this will
9845 * not need a release. The plane state will be attached
9846 * to the stream, and therefore part of the atomic
9847 * state. It'll be released when the atomic state is
9850 if (!dc_add_plane_to_context(
9852 dm_new_crtc_state->stream,
9854 dm_state->context)) {
9856 dc_plane_state_release(dc_new_plane_state);
9860 dm_new_plane_state->dc_state = dc_new_plane_state;
9862 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY);
9864 /* Tell DC to do a full surface update every time there
9865 * is a plane change. Inefficient, but works for now.
9867 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
9869 *lock_and_validation_needed = true;
9876 static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state,
9877 int *src_w, int *src_h)
9879 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
9880 case DRM_MODE_ROTATE_90:
9881 case DRM_MODE_ROTATE_270:
9882 *src_w = plane_state->src_h >> 16;
9883 *src_h = plane_state->src_w >> 16;
9885 case DRM_MODE_ROTATE_0:
9886 case DRM_MODE_ROTATE_180:
9888 *src_w = plane_state->src_w >> 16;
9889 *src_h = plane_state->src_h >> 16;
9895 dm_get_plane_scale(struct drm_plane_state *plane_state,
9896 int *out_plane_scale_w, int *out_plane_scale_h)
9898 int plane_src_w, plane_src_h;
9900 dm_get_oriented_plane_size(plane_state, &plane_src_w, &plane_src_h);
9901 *out_plane_scale_w = plane_state->crtc_w * 1000 / plane_src_w;
9902 *out_plane_scale_h = plane_state->crtc_h * 1000 / plane_src_h;
9905 static int dm_check_crtc_cursor(struct drm_atomic_state *state,
9906 struct drm_crtc *crtc,
9907 struct drm_crtc_state *new_crtc_state)
9909 struct drm_plane *cursor = crtc->cursor, *underlying;
9910 struct drm_plane_state *new_cursor_state, *new_underlying_state;
9912 int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h;
9914 /* On DCE and DCN there is no dedicated hardware cursor plane. We get a
9915 * cursor per pipe but it's going to inherit the scaling and
9916 * positioning from the underlying pipe. Check the cursor plane's
9917 * blending properties match the underlying planes'.
9920 new_cursor_state = drm_atomic_get_plane_state(state, cursor);
9921 if (IS_ERR(new_cursor_state))
9922 return PTR_ERR(new_cursor_state);
9924 if (!new_cursor_state->fb)
9927 dm_get_plane_scale(new_cursor_state, &cursor_scale_w, &cursor_scale_h);
9929 /* Need to check all enabled planes, even if this commit doesn't change
9932 i = drm_atomic_add_affected_planes(state, crtc);
9936 for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) {
9937 /* Narrow down to non-cursor planes on the same CRTC as the cursor */
9938 if (new_underlying_state->crtc != crtc || underlying == crtc->cursor)
9941 /* Ignore disabled planes */
9942 if (!new_underlying_state->fb)
9945 dm_get_plane_scale(new_underlying_state,
9946 &underlying_scale_w, &underlying_scale_h);
9948 if (cursor_scale_w != underlying_scale_w ||
9949 cursor_scale_h != underlying_scale_h) {
9950 drm_dbg_atomic(crtc->dev,
9951 "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n",
9952 cursor->base.id, cursor->name, underlying->base.id, underlying->name);
9956 /* If this plane covers the whole CRTC, no need to check planes underneath */
9957 if (new_underlying_state->crtc_x <= 0 &&
9958 new_underlying_state->crtc_y <= 0 &&
9959 new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay &&
9960 new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay)
9967 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
9969 struct drm_connector *connector;
9970 struct drm_connector_state *conn_state, *old_conn_state;
9971 struct amdgpu_dm_connector *aconnector = NULL;
9974 for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) {
9975 if (!conn_state->crtc)
9976 conn_state = old_conn_state;
9978 if (conn_state->crtc != crtc)
9981 aconnector = to_amdgpu_dm_connector(connector);
9982 if (!aconnector->mst_output_port || !aconnector->mst_root)
9991 return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr);
9995 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
9997 * @dev: The DRM device
9998 * @state: The atomic state to commit
10000 * Validate that the given atomic state is programmable by DC into hardware.
10001 * This involves constructing a &struct dc_state reflecting the new hardware
10002 * state we wish to commit, then querying DC to see if it is programmable. It's
10003 * important not to modify the existing DC state. Otherwise, atomic_check
10004 * may unexpectedly commit hardware changes.
10006 * When validating the DC state, it's important that the right locks are
10007 * acquired. For full updates case which removes/adds/updates streams on one
10008 * CRTC while flipping on another CRTC, acquiring global lock will guarantee
10009 * that any such full update commit will wait for completion of any outstanding
10010 * flip using DRMs synchronization events.
10012 * Note that DM adds the affected connectors for all CRTCs in state, when that
10013 * might not seem necessary. This is because DC stream creation requires the
10014 * DC sink, which is tied to the DRM connector state. Cleaning this up should
10015 * be possible but non-trivial - a possible TODO item.
10017 * Return: -Error code if validation failed.
10019 static int amdgpu_dm_atomic_check(struct drm_device *dev,
10020 struct drm_atomic_state *state)
10022 struct amdgpu_device *adev = drm_to_adev(dev);
10023 struct dm_atomic_state *dm_state = NULL;
10024 struct dc *dc = adev->dm.dc;
10025 struct drm_connector *connector;
10026 struct drm_connector_state *old_con_state, *new_con_state;
10027 struct drm_crtc *crtc;
10028 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
10029 struct drm_plane *plane;
10030 struct drm_plane_state *old_plane_state, *new_plane_state;
10031 enum dc_status status;
10033 bool lock_and_validation_needed = false;
10034 bool is_top_most_overlay = true;
10035 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
10036 struct drm_dp_mst_topology_mgr *mgr;
10037 struct drm_dp_mst_topology_state *mst_state;
10038 struct dsc_mst_fairness_vars vars[MAX_PIPES];
10040 trace_amdgpu_dm_atomic_check_begin(state);
10042 ret = drm_atomic_helper_check_modeset(dev, state);
10044 DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n");
10048 /* Check connector changes */
10049 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
10050 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
10051 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10053 /* Skip connectors that are disabled or part of modeset already. */
10054 if (!new_con_state->crtc)
10057 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc);
10058 if (IS_ERR(new_crtc_state)) {
10059 DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n");
10060 ret = PTR_ERR(new_crtc_state);
10064 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level ||
10065 dm_old_con_state->scaling != dm_new_con_state->scaling)
10066 new_crtc_state->connectors_changed = true;
10069 if (dc_resource_is_dsc_encoding_supported(dc)) {
10070 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10071 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
10072 ret = add_affected_mst_dsc_crtcs(state, crtc);
10074 DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n");
10080 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10081 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
10083 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
10084 !new_crtc_state->color_mgmt_changed &&
10085 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled &&
10086 dm_old_crtc_state->dsc_force_changed == false)
10089 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state);
10091 DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n");
10095 if (!new_crtc_state->enable)
10098 ret = drm_atomic_add_affected_connectors(state, crtc);
10100 DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n");
10104 ret = drm_atomic_add_affected_planes(state, crtc);
10106 DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n");
10110 if (dm_old_crtc_state->dsc_force_changed)
10111 new_crtc_state->mode_changed = true;
10115 * Add all primary and overlay planes on the CRTC to the state
10116 * whenever a plane is enabled to maintain correct z-ordering
10117 * and to enable fast surface updates.
10119 drm_for_each_crtc(crtc, dev) {
10120 bool modified = false;
10122 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
10123 if (plane->type == DRM_PLANE_TYPE_CURSOR)
10126 if (new_plane_state->crtc == crtc ||
10127 old_plane_state->crtc == crtc) {
10136 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
10137 if (plane->type == DRM_PLANE_TYPE_CURSOR)
10141 drm_atomic_get_plane_state(state, plane);
10143 if (IS_ERR(new_plane_state)) {
10144 ret = PTR_ERR(new_plane_state);
10145 DRM_DEBUG_DRIVER("new_plane_state is BAD\n");
10152 * DC consults the zpos (layer_index in DC terminology) to determine the
10153 * hw plane on which to enable the hw cursor (see
10154 * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in
10155 * atomic state, so call drm helper to normalize zpos.
10157 ret = drm_atomic_normalize_zpos(dev, state);
10159 drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n");
10163 /* Remove exiting planes if they are modified */
10164 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10165 if (old_plane_state->fb && new_plane_state->fb &&
10166 get_mem_type(old_plane_state->fb) !=
10167 get_mem_type(new_plane_state->fb))
10168 lock_and_validation_needed = true;
10170 ret = dm_update_plane_state(dc, state, plane,
10174 &lock_and_validation_needed,
10175 &is_top_most_overlay);
10177 DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10182 /* Disable all crtcs which require disable */
10183 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10184 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10188 &lock_and_validation_needed);
10190 DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n");
10195 /* Enable all crtcs which require enable */
10196 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10197 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10201 &lock_and_validation_needed);
10203 DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n");
10208 /* Add new/modified planes */
10209 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10210 ret = dm_update_plane_state(dc, state, plane,
10214 &lock_and_validation_needed,
10215 &is_top_most_overlay);
10217 DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10222 if (dc_resource_is_dsc_encoding_supported(dc)) {
10223 ret = pre_validate_dsc(state, &dm_state, vars);
10228 /* Run this here since we want to validate the streams we created */
10229 ret = drm_atomic_helper_check_planes(dev, state);
10231 DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n");
10235 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10236 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
10237 if (dm_new_crtc_state->mpo_requested)
10238 DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc);
10241 /* Check cursor planes scaling */
10242 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10243 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state);
10245 DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n");
10250 if (state->legacy_cursor_update) {
10252 * This is a fast cursor update coming from the plane update
10253 * helper, check if it can be done asynchronously for better
10256 state->async_update =
10257 !drm_atomic_helper_async_check(dev, state);
10260 * Skip the remaining global validation if this is an async
10261 * update. Cursor updates can be done without affecting
10262 * state or bandwidth calcs and this avoids the performance
10263 * penalty of locking the private state object and
10264 * allocating a new dc_state.
10266 if (state->async_update)
10270 /* Check scaling and underscan changes*/
10271 /* TODO Removed scaling changes validation due to inability to commit
10272 * new stream into context w\o causing full reset. Need to
10273 * decide how to handle.
10275 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
10276 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
10277 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10278 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
10280 /* Skip any modesets/resets */
10281 if (!acrtc || drm_atomic_crtc_needs_modeset(
10282 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
10285 /* Skip any thing not scale or underscan changes */
10286 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
10289 lock_and_validation_needed = true;
10292 /* set the slot info for each mst_state based on the link encoding format */
10293 for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
10294 struct amdgpu_dm_connector *aconnector;
10295 struct drm_connector *connector;
10296 struct drm_connector_list_iter iter;
10297 u8 link_coding_cap;
10299 drm_connector_list_iter_begin(dev, &iter);
10300 drm_for_each_connector_iter(connector, &iter) {
10301 if (connector->index == mst_state->mgr->conn_base_id) {
10302 aconnector = to_amdgpu_dm_connector(connector);
10303 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link);
10304 drm_dp_mst_update_slots(mst_state, link_coding_cap);
10309 drm_connector_list_iter_end(&iter);
10313 * Streams and planes are reset when there are changes that affect
10314 * bandwidth. Anything that affects bandwidth needs to go through
10315 * DC global validation to ensure that the configuration can be applied
10318 * We have to currently stall out here in atomic_check for outstanding
10319 * commits to finish in this case because our IRQ handlers reference
10320 * DRM state directly - we can end up disabling interrupts too early
10323 * TODO: Remove this stall and drop DM state private objects.
10325 if (lock_and_validation_needed) {
10326 ret = dm_atomic_get_state(state, &dm_state);
10328 DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n");
10332 ret = do_aquire_global_lock(dev, state);
10334 DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n");
10338 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars);
10340 DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n");
10345 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars);
10347 DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n");
10352 * Perform validation of MST topology in the state:
10353 * We need to perform MST atomic check before calling
10354 * dc_validate_global_state(), or there is a chance
10355 * to get stuck in an infinite loop and hang eventually.
10357 ret = drm_dp_mst_atomic_check(state);
10359 DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n");
10362 status = dc_validate_global_state(dc, dm_state->context, true);
10363 if (status != DC_OK) {
10364 DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)",
10365 dc_status_to_str(status), status);
10371 * The commit is a fast update. Fast updates shouldn't change
10372 * the DC context, affect global validation, and can have their
10373 * commit work done in parallel with other commits not touching
10374 * the same resource. If we have a new DC context as part of
10375 * the DM atomic state from validation we need to free it and
10376 * retain the existing one instead.
10378 * Furthermore, since the DM atomic state only contains the DC
10379 * context and can safely be annulled, we can free the state
10380 * and clear the associated private object now to free
10381 * some memory and avoid a possible use-after-free later.
10384 for (i = 0; i < state->num_private_objs; i++) {
10385 struct drm_private_obj *obj = state->private_objs[i].ptr;
10387 if (obj->funcs == adev->dm.atomic_obj.funcs) {
10388 int j = state->num_private_objs-1;
10390 dm_atomic_destroy_state(obj,
10391 state->private_objs[i].state);
10393 /* If i is not at the end of the array then the
10394 * last element needs to be moved to where i was
10395 * before the array can safely be truncated.
10398 state->private_objs[i] =
10399 state->private_objs[j];
10401 state->private_objs[j].ptr = NULL;
10402 state->private_objs[j].state = NULL;
10403 state->private_objs[j].old_state = NULL;
10404 state->private_objs[j].new_state = NULL;
10406 state->num_private_objs = j;
10412 /* Store the overall update type for use later in atomic check. */
10413 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10414 struct dm_crtc_state *dm_new_crtc_state =
10415 to_dm_crtc_state(new_crtc_state);
10418 * Only allow async flips for fast updates that don't change
10419 * the FB pitch, the DCC state, rotation, etc.
10421 if (new_crtc_state->async_flip && lock_and_validation_needed) {
10422 drm_dbg_atomic(crtc->dev,
10423 "[CRTC:%d:%s] async flips are only supported for fast updates\n",
10424 crtc->base.id, crtc->name);
10429 dm_new_crtc_state->update_type = lock_and_validation_needed ?
10430 UPDATE_TYPE_FULL : UPDATE_TYPE_FAST;
10433 /* Must be success */
10436 trace_amdgpu_dm_atomic_check_finish(state, ret);
10441 if (ret == -EDEADLK)
10442 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
10443 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
10444 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
10446 DRM_DEBUG_DRIVER("Atomic check failed with err: %d\n", ret);
10448 trace_amdgpu_dm_atomic_check_finish(state, ret);
10453 static bool is_dp_capable_without_timing_msa(struct dc *dc,
10454 struct amdgpu_dm_connector *amdgpu_dm_connector)
10457 bool capable = false;
10459 if (amdgpu_dm_connector->dc_link &&
10460 dm_helpers_dp_read_dpcd(
10462 amdgpu_dm_connector->dc_link,
10463 DP_DOWN_STREAM_PORT_COUNT,
10465 sizeof(dpcd_data))) {
10466 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
10472 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,
10473 unsigned int offset,
10474 unsigned int total_length,
10476 unsigned int length,
10477 struct amdgpu_hdmi_vsdb_info *vsdb)
10480 union dmub_rb_cmd cmd;
10481 struct dmub_cmd_send_edid_cea *input;
10482 struct dmub_cmd_edid_cea_output *output;
10484 if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES)
10487 memset(&cmd, 0, sizeof(cmd));
10489 input = &cmd.edid_cea.data.input;
10491 cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA;
10492 cmd.edid_cea.header.sub_type = 0;
10493 cmd.edid_cea.header.payload_bytes =
10494 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header);
10495 input->offset = offset;
10496 input->length = length;
10497 input->cea_total_length = total_length;
10498 memcpy(input->payload, data, length);
10500 res = dm_execute_dmub_cmd(dm->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY);
10502 DRM_ERROR("EDID CEA parser failed\n");
10506 output = &cmd.edid_cea.data.output;
10508 if (output->type == DMUB_CMD__EDID_CEA_ACK) {
10509 if (!output->ack.success) {
10510 DRM_ERROR("EDID CEA ack failed at offset %d\n",
10511 output->ack.offset);
10513 } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) {
10514 if (!output->amd_vsdb.vsdb_found)
10517 vsdb->freesync_supported = output->amd_vsdb.freesync_supported;
10518 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version;
10519 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate;
10520 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate;
10522 DRM_WARN("Unknown EDID CEA parser results\n");
10529 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm,
10530 u8 *edid_ext, int len,
10531 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10535 /* send extension block to DMCU for parsing */
10536 for (i = 0; i < len; i += 8) {
10540 /* send 8 bytes a time */
10541 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8))
10545 /* EDID block sent completed, expect result */
10546 int version, min_rate, max_rate;
10548 res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate);
10550 /* amd vsdb found */
10551 vsdb_info->freesync_supported = 1;
10552 vsdb_info->amd_vsdb_version = version;
10553 vsdb_info->min_refresh_rate_hz = min_rate;
10554 vsdb_info->max_refresh_rate_hz = max_rate;
10562 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset);
10570 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm,
10571 u8 *edid_ext, int len,
10572 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10576 /* send extension block to DMCU for parsing */
10577 for (i = 0; i < len; i += 8) {
10578 /* send 8 bytes a time */
10579 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info))
10583 return vsdb_info->freesync_supported;
10586 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
10587 u8 *edid_ext, int len,
10588 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10590 struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
10593 mutex_lock(&adev->dm.dc_lock);
10594 if (adev->dm.dmub_srv)
10595 ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info);
10597 ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info);
10598 mutex_unlock(&adev->dm.dc_lock);
10602 static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector,
10603 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
10605 u8 *edid_ext = NULL;
10609 if (edid == NULL || edid->extensions == 0)
10612 /* Find DisplayID extension */
10613 for (i = 0; i < edid->extensions; i++) {
10614 edid_ext = (void *)(edid + (i + 1));
10615 if (edid_ext[0] == DISPLAYID_EXT)
10619 while (j < EDID_LENGTH) {
10620 struct amd_vsdb_block *amd_vsdb = (struct amd_vsdb_block *)&edid_ext[j];
10621 unsigned int ieeeId = (amd_vsdb->ieee_id[2] << 16) | (amd_vsdb->ieee_id[1] << 8) | (amd_vsdb->ieee_id[0]);
10623 if (ieeeId == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID &&
10624 amd_vsdb->version == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3) {
10625 vsdb_info->replay_mode = (amd_vsdb->feature_caps & AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE) ? true : false;
10626 vsdb_info->amd_vsdb_version = HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3;
10627 DRM_DEBUG_KMS("Panel supports Replay Mode: %d\n", vsdb_info->replay_mode);
10637 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
10638 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
10640 u8 *edid_ext = NULL;
10642 bool valid_vsdb_found = false;
10644 /*----- drm_find_cea_extension() -----*/
10645 /* No EDID or EDID extensions */
10646 if (edid == NULL || edid->extensions == 0)
10649 /* Find CEA extension */
10650 for (i = 0; i < edid->extensions; i++) {
10651 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1);
10652 if (edid_ext[0] == CEA_EXT)
10656 if (i == edid->extensions)
10659 /*----- cea_db_offsets() -----*/
10660 if (edid_ext[0] != CEA_EXT)
10663 valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info);
10665 return valid_vsdb_found ? i : -ENODEV;
10669 * amdgpu_dm_update_freesync_caps - Update Freesync capabilities
10671 * @connector: Connector to query.
10672 * @edid: EDID from monitor
10674 * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep
10675 * track of some of the display information in the internal data struct used by
10676 * amdgpu_dm. This function checks which type of connector we need to set the
10677 * FreeSync parameters.
10679 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
10683 struct detailed_timing *timing;
10684 struct detailed_non_pixel *data;
10685 struct detailed_data_monitor_range *range;
10686 struct amdgpu_dm_connector *amdgpu_dm_connector =
10687 to_amdgpu_dm_connector(connector);
10688 struct dm_connector_state *dm_con_state = NULL;
10689 struct dc_sink *sink;
10691 struct drm_device *dev = connector->dev;
10692 struct amdgpu_device *adev = drm_to_adev(dev);
10693 struct amdgpu_hdmi_vsdb_info vsdb_info = {0};
10694 bool freesync_capable = false;
10695 enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE;
10697 if (!connector->state) {
10698 DRM_ERROR("%s - Connector has no state", __func__);
10702 sink = amdgpu_dm_connector->dc_sink ?
10703 amdgpu_dm_connector->dc_sink :
10704 amdgpu_dm_connector->dc_em_sink;
10706 if (!edid || !sink) {
10707 dm_con_state = to_dm_connector_state(connector->state);
10709 amdgpu_dm_connector->min_vfreq = 0;
10710 amdgpu_dm_connector->max_vfreq = 0;
10711 amdgpu_dm_connector->pixel_clock_mhz = 0;
10712 connector->display_info.monitor_range.min_vfreq = 0;
10713 connector->display_info.monitor_range.max_vfreq = 0;
10714 freesync_capable = false;
10719 dm_con_state = to_dm_connector_state(connector->state);
10721 if (!adev->dm.freesync_module)
10724 if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
10725 || sink->sink_signal == SIGNAL_TYPE_EDP) {
10726 bool edid_check_required = false;
10729 edid_check_required = is_dp_capable_without_timing_msa(
10731 amdgpu_dm_connector);
10734 if (edid_check_required == true && (edid->version > 1 ||
10735 (edid->version == 1 && edid->revision > 1))) {
10736 for (i = 0; i < 4; i++) {
10738 timing = &edid->detailed_timings[i];
10739 data = &timing->data.other_data;
10740 range = &data->data.range;
10742 * Check if monitor has continuous frequency mode
10744 if (data->type != EDID_DETAIL_MONITOR_RANGE)
10747 * Check for flag range limits only. If flag == 1 then
10748 * no additional timing information provided.
10749 * Default GTF, GTF Secondary curve and CVT are not
10752 if (range->flags != 1)
10755 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
10756 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
10757 amdgpu_dm_connector->pixel_clock_mhz =
10758 range->pixel_clock_mhz * 10;
10760 connector->display_info.monitor_range.min_vfreq = range->min_vfreq;
10761 connector->display_info.monitor_range.max_vfreq = range->max_vfreq;
10766 if (amdgpu_dm_connector->max_vfreq -
10767 amdgpu_dm_connector->min_vfreq > 10) {
10769 freesync_capable = true;
10772 parse_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10774 if (vsdb_info.replay_mode) {
10775 amdgpu_dm_connector->vsdb_info.replay_mode = vsdb_info.replay_mode;
10776 amdgpu_dm_connector->vsdb_info.amd_vsdb_version = vsdb_info.amd_vsdb_version;
10777 amdgpu_dm_connector->as_type = ADAPTIVE_SYNC_TYPE_EDP;
10780 } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
10781 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10782 if (i >= 0 && vsdb_info.freesync_supported) {
10783 timing = &edid->detailed_timings[i];
10784 data = &timing->data.other_data;
10786 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10787 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10788 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10789 freesync_capable = true;
10791 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10792 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10796 as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link);
10798 if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {
10799 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10800 if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) {
10802 amdgpu_dm_connector->pack_sdp_v1_3 = true;
10803 amdgpu_dm_connector->as_type = as_type;
10804 amdgpu_dm_connector->vsdb_info = vsdb_info;
10806 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10807 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10808 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10809 freesync_capable = true;
10811 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10812 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10818 dm_con_state->freesync_capable = freesync_capable;
10820 if (connector->vrr_capable_property)
10821 drm_connector_set_vrr_capable_property(connector,
10825 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
10827 struct amdgpu_device *adev = drm_to_adev(dev);
10828 struct dc *dc = adev->dm.dc;
10831 mutex_lock(&adev->dm.dc_lock);
10832 if (dc->current_state) {
10833 for (i = 0; i < dc->current_state->stream_count; ++i)
10834 dc->current_state->streams[i]
10835 ->triggered_crtc_reset.enabled =
10836 adev->dm.force_timing_sync;
10838 dm_enable_per_frame_crtc_master_sync(dc->current_state);
10839 dc_trigger_sync(dc, dc->current_state);
10841 mutex_unlock(&adev->dm.dc_lock);
10844 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
10845 u32 value, const char *func_name)
10847 #ifdef DM_CHECK_ADDR_0
10848 if (address == 0) {
10849 DC_ERR("invalid register write. address = 0");
10853 cgs_write_register(ctx->cgs_device, address, value);
10854 trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
10857 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
10858 const char *func_name)
10861 #ifdef DM_CHECK_ADDR_0
10862 if (address == 0) {
10863 DC_ERR("invalid register read; address = 0\n");
10868 if (ctx->dmub_srv &&
10869 ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
10870 !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
10875 value = cgs_read_register(ctx->cgs_device, address);
10877 trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
10882 int amdgpu_dm_process_dmub_aux_transfer_sync(
10883 struct dc_context *ctx,
10884 unsigned int link_index,
10885 struct aux_payload *payload,
10886 enum aux_return_code_type *operation_result)
10888 struct amdgpu_device *adev = ctx->driver_context;
10889 struct dmub_notification *p_notify = adev->dm.dmub_notify;
10892 mutex_lock(&adev->dm.dpia_aux_lock);
10893 if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) {
10894 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE;
10898 if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10899 DRM_ERROR("wait_for_completion_timeout timeout!");
10900 *operation_result = AUX_RET_ERROR_TIMEOUT;
10904 if (p_notify->result != AUX_RET_SUCCESS) {
10906 * Transient states before tunneling is enabled could
10907 * lead to this error. We can ignore this for now.
10909 if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) {
10910 DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n",
10911 payload->address, payload->length,
10914 *operation_result = AUX_RET_ERROR_INVALID_REPLY;
10919 payload->reply[0] = adev->dm.dmub_notify->aux_reply.command;
10920 if (!payload->write && p_notify->aux_reply.length &&
10921 (payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) {
10923 if (payload->length != p_notify->aux_reply.length) {
10924 DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n",
10925 p_notify->aux_reply.length,
10926 payload->address, payload->length);
10927 *operation_result = AUX_RET_ERROR_INVALID_REPLY;
10931 memcpy(payload->data, p_notify->aux_reply.data,
10932 p_notify->aux_reply.length);
10936 ret = p_notify->aux_reply.length;
10937 *operation_result = p_notify->result;
10939 reinit_completion(&adev->dm.dmub_aux_transfer_done);
10940 mutex_unlock(&adev->dm.dpia_aux_lock);
10944 int amdgpu_dm_process_dmub_set_config_sync(
10945 struct dc_context *ctx,
10946 unsigned int link_index,
10947 struct set_config_cmd_payload *payload,
10948 enum set_config_status *operation_result)
10950 struct amdgpu_device *adev = ctx->driver_context;
10951 bool is_cmd_complete;
10954 mutex_lock(&adev->dm.dpia_aux_lock);
10955 is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc,
10956 link_index, payload, adev->dm.dmub_notify);
10958 if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10960 *operation_result = adev->dm.dmub_notify->sc_status;
10962 DRM_ERROR("wait_for_completion_timeout timeout!");
10964 *operation_result = SET_CONFIG_UNKNOWN_ERROR;
10967 if (!is_cmd_complete)
10968 reinit_completion(&adev->dm.dmub_aux_transfer_done);
10969 mutex_unlock(&adev->dm.dpia_aux_lock);
10974 * Check whether seamless boot is supported.
10976 * So far we only support seamless boot on CHIP_VANGOGH.
10977 * If everything goes well, we may consider expanding
10978 * seamless boot to other ASICs.
10980 bool check_seamless_boot_capability(struct amdgpu_device *adev)
10982 switch (adev->ip_versions[DCE_HWIP][0]) {
10983 case IP_VERSION(3, 0, 1):
10984 if (!adev->mman.keep_stolen_vga_memory)
10994 bool dm_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
10996 return dc_dmub_srv_cmd_run(ctx->dmub_srv, cmd, wait_type);
10999 bool dm_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
11001 return dc_dmub_srv_cmd_run_list(ctx->dmub_srv, count, cmd, wait_type);