drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 /* The caprices of the preprocessor require that this be declared right here */
  27 #define CREATE_TRACE_POINTS
  28
  29 #include "dm_services_types.h"
  30 #include "dc.h"
  31 #include "link_enc_cfg.h"
  32 #include "dc/inc/core_types.h"
  33 #include "dal_asic_id.h"
  34 #include "dmub/dmub_srv.h"
  35 #include "dc/inc/hw/dmcu.h"
  36 #include "dc/inc/hw/abm.h"
  37 #include "dc/dc_dmub_srv.h"
  38 #include "dc/dc_edid_parser.h"
  39 #include "dc/dc_stat.h"
  40 #include "amdgpu_dm_trace.h"
  41 #include "dpcd_defs.h"
  42 #include "link/protocols/link_dpcd.h"
  43 #include "link_service_types.h"
  44 #include "link/protocols/link_dp_capability.h"
  45 #include "link/protocols/link_ddc.h"
  46
  47 #include "vid.h"
  48 #include "amdgpu.h"
  49 #include "amdgpu_display.h"
  50 #include "amdgpu_ucode.h"
  51 #include "atom.h"
  52 #include "amdgpu_dm.h"
  53 #include "amdgpu_dm_plane.h"
  54 #include "amdgpu_dm_crtc.h"
  55 #include "amdgpu_dm_hdcp.h"
  56 #include <drm/display/drm_hdcp_helper.h>
  57 #include "amdgpu_pm.h"
  58 #include "amdgpu_atombios.h"
  59
  60 #include "amd_shared.h"
  61 #include "amdgpu_dm_irq.h"
  62 #include "dm_helpers.h"
  63 #include "amdgpu_dm_mst_types.h"
  64 #if defined(CONFIG_DEBUG_FS)
  65 #include "amdgpu_dm_debugfs.h"
  66 #endif
  67 #include "amdgpu_dm_psr.h"
  68
  69 #include "ivsrcid/ivsrcid_vislands30.h"
  70
  71 #include <linux/backlight.h>
  72 #include <linux/module.h>
  73 #include <linux/moduleparam.h>
  74 #include <linux/types.h>
  75 #include <linux/pm_runtime.h>
  76 #include <linux/pci.h>
  77 #include <linux/firmware.h>
  78 #include <linux/component.h>
  79 #include <linux/dmi.h>
  80
  81 #include <drm/display/drm_dp_mst_helper.h>
  82 #include <drm/display/drm_hdmi_helper.h>
  83 #include <drm/drm_atomic.h>
  84 #include <drm/drm_atomic_uapi.h>
  85 #include <drm/drm_atomic_helper.h>
  86 #include <drm/drm_blend.h>
  87 #include <drm/drm_fourcc.h>
  88 #include <drm/drm_edid.h>
  89 #include <drm/drm_vblank.h>
  90 #include <drm/drm_audio_component.h>
  91 #include <drm/drm_gem_atomic_helper.h>
  92 #include <drm/drm_plane_helper.h>
  93
  94 #include <acpi/video.h>
  95
  96 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
  97
  98 #include "dcn/dcn_1_0_offset.h"
  99 #include "dcn/dcn_1_0_sh_mask.h"
 100 #include "soc15_hw_ip.h"
 101 #include "soc15_common.h"
 102 #include "vega10_ip_offset.h"
 103
 104 #include "gc/gc_11_0_0_offset.h"
 105 #include "gc/gc_11_0_0_sh_mask.h"
 106
 107 #include "modules/inc/mod_freesync.h"
 108 #include "modules/power/power_helpers.h"
 109
 110 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
 111 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
 112 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"
 113 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
 114 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
 115 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
 116 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
 117 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
 118 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
 119 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
 120 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"
 121 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
 122 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin"
 123 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);
 124 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin"
 125 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);
 126 #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin"
 127 MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB);
 128 #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin"
 129 MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB);
 130 #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin"
 131 MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB);
 132
 133 #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin"
 134 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB);
 135 #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin"
 136 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB);
 137
 138 #define FIRMWARE_RAVEN_DMCU             "amdgpu/raven_dmcu.bin"
 139 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
 140
 141 #define FIRMWARE_NAVI12_DMCU            "amdgpu/navi12_dmcu.bin"
 142 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);
 143
 144 /* Number of bytes in PSP header for firmware. */
 145 #define PSP_HEADER_BYTES 0x100
 146
 147 /* Number of bytes in PSP footer for firmware. */
 148 #define PSP_FOOTER_BYTES 0x100
 149
 150 /**
 151  * DOC: overview
 152  *
 153  * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
 154  * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM
 155  * requests into DC requests, and DC responses into DRM responses.
 156  *
 157  * The root control structure is &struct amdgpu_display_manager.
 158  */
 159
 160 /* basic init/fini API */
 161 static int amdgpu_dm_init(struct amdgpu_device *adev);
 162 static void amdgpu_dm_fini(struct amdgpu_device *adev);
 163 static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector);
 164
 165 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)
 166 {
 167         switch (link->dpcd_caps.dongle_type) {
 168         case DISPLAY_DONGLE_NONE:
 169                 return DRM_MODE_SUBCONNECTOR_Native;
 170         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
 171                 return DRM_MODE_SUBCONNECTOR_VGA;
 172         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
 173         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 174                 return DRM_MODE_SUBCONNECTOR_DVID;
 175         case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
 176         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 177                 return DRM_MODE_SUBCONNECTOR_HDMIA;
 178         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 179         default:
 180                 return DRM_MODE_SUBCONNECTOR_Unknown;
 181         }
 182 }
 183
 184 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector)
 185 {
 186         struct dc_link *link = aconnector->dc_link;
 187         struct drm_connector *connector = &aconnector->base;
 188         enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
 189
 190         if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
 191                 return;
 192
 193         if (aconnector->dc_sink)
 194                 subconnector = get_subconnector_type(link);
 195
 196         drm_object_property_set_value(&connector->base,
 197                         connector->dev->mode_config.dp_subconnector_property,
 198                         subconnector);
 199 }
 200
 201 /*
 202  * initializes drm_device display related structures, based on the information
 203  * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
 204  * drm_encoder, drm_mode_config
 205  *
 206  * Returns 0 on success
 207  */
 208 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
 209 /* removes and deallocates the drm structures, created by the above function */
 210 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
 211
 212 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
 213                                     struct amdgpu_dm_connector *amdgpu_dm_connector,
 214                                     u32 link_index,
 215                                     struct amdgpu_encoder *amdgpu_encoder);
 216 static int amdgpu_dm_encoder_init(struct drm_device *dev,
 217                                   struct amdgpu_encoder *aencoder,
 218                                   uint32_t link_index);
 219
 220 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
 221
 222 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
 223
 224 static int amdgpu_dm_atomic_check(struct drm_device *dev,
 225                                   struct drm_atomic_state *state);
 226
 227 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector);
 228 static void handle_hpd_rx_irq(void *param);
 229
 230 static bool
 231 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
 232                                  struct drm_crtc_state *new_crtc_state);
 233 /*
 234  * dm_vblank_get_counter
 235  *
 236  * @brief
 237  * Get counter for number of vertical blanks
 238  *
 239  * @param
 240  * struct amdgpu_device *adev - [in] desired amdgpu device
 241  * int disp_idx - [in] which CRTC to get the counter from
 242  *
 243  * @return
 244  * Counter for vertical blanks
 245  */
 246 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 247 {
 248         if (crtc >= adev->mode_info.num_crtc)
 249                 return 0;
 250         else {
 251                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 252
 253                 if (acrtc->dm_irq_params.stream == NULL) {
 254                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 255                                   crtc);
 256                         return 0;
 257                 }
 258
 259                 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);
 260         }
 261 }
 262
 263 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 264                                   u32 *vbl, u32 *position)
 265 {
 266         u32 v_blank_start, v_blank_end, h_position, v_position;
 267
 268         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 269                 return -EINVAL;
 270         else {
 271                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 272
 273                 if (acrtc->dm_irq_params.stream ==  NULL) {
 274                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 275                                   crtc);
 276                         return 0;
 277                 }
 278
 279                 /*
 280                  * TODO rework base driver to use values directly.
 281                  * for now parse it back into reg-format
 282                  */
 283                 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream,
 284                                          &v_blank_start,
 285                                          &v_blank_end,
 286                                          &h_position,
 287                                          &v_position);
 288
 289                 *position = v_position | (h_position << 16);
 290                 *vbl = v_blank_start | (v_blank_end << 16);
 291         }
 292
 293         return 0;
 294 }
 295
 296 static bool dm_is_idle(void *handle)
 297 {
 298         /* XXX todo */
 299         return true;
 300 }
 301
 302 static int dm_wait_for_idle(void *handle)
 303 {
 304         /* XXX todo */
 305         return 0;
 306 }
 307
 308 static bool dm_check_soft_reset(void *handle)
 309 {
 310         return false;
 311 }
 312
 313 static int dm_soft_reset(void *handle)
 314 {
 315         /* XXX todo */
 316         return 0;
 317 }
 318
 319 static struct amdgpu_crtc *
 320 get_crtc_by_otg_inst(struct amdgpu_device *adev,
 321                      int otg_inst)
 322 {
 323         struct drm_device *dev = adev_to_drm(adev);
 324         struct drm_crtc *crtc;
 325         struct amdgpu_crtc *amdgpu_crtc;
 326
 327         if (WARN_ON(otg_inst == -1))
 328                 return adev->mode_info.crtcs[0];
 329
 330         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 331                 amdgpu_crtc = to_amdgpu_crtc(crtc);
 332
 333                 if (amdgpu_crtc->otg_inst == otg_inst)
 334                         return amdgpu_crtc;
 335         }
 336
 337         return NULL;
 338 }
 339
 340 static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,
 341                                               struct dm_crtc_state *new_state)
 342 {
 343         if (new_state->freesync_config.state ==  VRR_STATE_ACTIVE_FIXED)
 344                 return true;
 345         else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state))
 346                 return true;
 347         else
 348                 return false;
 349 }
 350
 351 static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update,
 352                                         int planes_count)
 353 {
 354         int i, j;
 355
 356         for (i = 0, j = planes_count - 1; i < j; i++, j--)
 357                 swap(array_of_surface_update[i], array_of_surface_update[j]);
 358 }
 359
 360 /**
 361  * update_planes_and_stream_adapter() - Send planes to be updated in DC
 362  *
 363  * DC has a generic way to update planes and stream via
 364  * dc_update_planes_and_stream function; however, DM might need some
 365  * adjustments and preparation before calling it. This function is a wrapper
 366  * for the dc_update_planes_and_stream that does any required configuration
 367  * before passing control to DC.
 368  */
 369 static inline bool update_planes_and_stream_adapter(struct dc *dc,
 370                                                     int update_type,
 371                                                     int planes_count,
 372                                                     struct dc_stream_state *stream,
 373                                                     struct dc_stream_update *stream_update,
 374                                                     struct dc_surface_update *array_of_surface_update)
 375 {
 376         reverse_planes_order(array_of_surface_update, planes_count);
 377
 378         /*
 379          * Previous frame finished and HW is ready for optimization.
 380          */
 381         if (update_type == UPDATE_TYPE_FAST)
 382                 dc_post_update_surfaces_to_stream(dc);
 383
 384         return dc_update_planes_and_stream(dc,
 385                                            array_of_surface_update,
 386                                            planes_count,
 387                                            stream,
 388                                            stream_update);
 389 }
 390
 391 /**
 392  * dm_pflip_high_irq() - Handle pageflip interrupt
 393  * @interrupt_params: ignored
 394  *
 395  * Handles the pageflip interrupt by notifying all interested parties
 396  * that the pageflip has been completed.
 397  */
 398 static void dm_pflip_high_irq(void *interrupt_params)
 399 {
 400         struct amdgpu_crtc *amdgpu_crtc;
 401         struct common_irq_params *irq_params = interrupt_params;
 402         struct amdgpu_device *adev = irq_params->adev;
 403         unsigned long flags;
 404         struct drm_pending_vblank_event *e;
 405         u32 vpos, hpos, v_blank_start, v_blank_end;
 406         bool vrr_active;
 407
 408         amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
 409
 410         /* IRQ could occur when in initial stage */
 411         /* TODO work and BO cleanup */
 412         if (amdgpu_crtc == NULL) {
 413                 DC_LOG_PFLIP("CRTC is null, returning.\n");
 414                 return;
 415         }
 416
 417         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 418
 419         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
 420                 DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
 421                                                  amdgpu_crtc->pflip_status,
 422                                                  AMDGPU_FLIP_SUBMITTED,
 423                                                  amdgpu_crtc->crtc_id,
 424                                                  amdgpu_crtc);
 425                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 426                 return;
 427         }
 428
 429         /* page flip completed. */
 430         e = amdgpu_crtc->event;
 431         amdgpu_crtc->event = NULL;
 432
 433         WARN_ON(!e);
 434
 435         vrr_active = amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc);
 436
 437         /* Fixed refresh rate, or VRR scanout position outside front-porch? */
 438         if (!vrr_active ||
 439             !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start,
 440                                       &v_blank_end, &hpos, &vpos) ||
 441             (vpos < v_blank_start)) {
 442                 /* Update to correct count and vblank timestamp if racing with
 443                  * vblank irq. This also updates to the correct vblank timestamp
 444                  * even in VRR mode, as scanout is past the front-porch atm.
 445                  */
 446                 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
 447
 448                 /* Wake up userspace by sending the pageflip event with proper
 449                  * count and timestamp of vblank of flip completion.
 450                  */
 451                 if (e) {
 452                         drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
 453
 454                         /* Event sent, so done with vblank for this flip */
 455                         drm_crtc_vblank_put(&amdgpu_crtc->base);
 456                 }
 457         } else if (e) {
 458                 /* VRR active and inside front-porch: vblank count and
 459                  * timestamp for pageflip event will only be up to date after
 460                  * drm_crtc_handle_vblank() has been executed from late vblank
 461                  * irq handler after start of back-porch (vline 0). We queue the
 462                  * pageflip event for send-out by drm_crtc_handle_vblank() with
 463                  * updated timestamp and count, once it runs after us.
 464                  *
 465                  * We need to open-code this instead of using the helper
 466                  * drm_crtc_arm_vblank_event(), as that helper would
 467                  * call drm_crtc_accurate_vblank_count(), which we must
 468                  * not call in VRR mode while we are in front-porch!
 469                  */
 470
 471                 /* sequence will be replaced by real count during send-out. */
 472                 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
 473                 e->pipe = amdgpu_crtc->crtc_id;
 474
 475                 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list);
 476                 e = NULL;
 477         }
 478
 479         /* Keep track of vblank of this flip for flip throttling. We use the
 480          * cooked hw counter, as that one incremented at start of this vblank
 481          * of pageflip completion, so last_flip_vblank is the forbidden count
 482          * for queueing new pageflips if vsync + VRR is enabled.
 483          */
 484         amdgpu_crtc->dm_irq_params.last_flip_vblank =
 485                 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base);
 486
 487         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
 488         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 489
 490         DC_LOG_PFLIP("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
 491                      amdgpu_crtc->crtc_id, amdgpu_crtc,
 492                      vrr_active, (int) !e);
 493 }
 494
 495 static void dm_vupdate_high_irq(void *interrupt_params)
 496 {
 497         struct common_irq_params *irq_params = interrupt_params;
 498         struct amdgpu_device *adev = irq_params->adev;
 499         struct amdgpu_crtc *acrtc;
 500         struct drm_device *drm_dev;
 501         struct drm_vblank_crtc *vblank;
 502         ktime_t frame_duration_ns, previous_timestamp;
 503         unsigned long flags;
 504         int vrr_active;
 505
 506         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
 507
 508         if (acrtc) {
 509                 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
 510                 drm_dev = acrtc->base.dev;
 511                 vblank = &drm_dev->vblank[acrtc->base.index];
 512                 previous_timestamp = atomic64_read(&irq_params->previous_timestamp);
 513                 frame_duration_ns = vblank->time - previous_timestamp;
 514
 515                 if (frame_duration_ns > 0) {
 516                         trace_amdgpu_refresh_rate_track(acrtc->base.index,
 517                                                 frame_duration_ns,
 518                                                 ktime_divns(NSEC_PER_SEC, frame_duration_ns));
 519                         atomic64_set(&irq_params->previous_timestamp, vblank->time);
 520                 }
 521
 522                 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d\n",
 523                               acrtc->crtc_id,
 524                               vrr_active);
 525
 526                 /* Core vblank handling is done here after end of front-porch in
 527                  * vrr mode, as vblank timestamping will give valid results
 528                  * while now done after front-porch. This will also deliver
 529                  * page-flip completion events that have been queued to us
 530                  * if a pageflip happened inside front-porch.
 531                  */
 532                 if (vrr_active) {
 533                         amdgpu_dm_crtc_handle_vblank(acrtc);
 534
 535                         /* BTR processing for pre-DCE12 ASICs */
 536                         if (acrtc->dm_irq_params.stream &&
 537                             adev->family < AMDGPU_FAMILY_AI) {
 538                                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 539                                 mod_freesync_handle_v_update(
 540                                     adev->dm.freesync_module,
 541                                     acrtc->dm_irq_params.stream,
 542                                     &acrtc->dm_irq_params.vrr_params);
 543
 544                                 dc_stream_adjust_vmin_vmax(
 545                                     adev->dm.dc,
 546                                     acrtc->dm_irq_params.stream,
 547                                     &acrtc->dm_irq_params.vrr_params.adjust);
 548                                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 549                         }
 550                 }
 551         }
 552 }
 553
 554 /**
 555  * dm_crtc_high_irq() - Handles CRTC interrupt
 556  * @interrupt_params: used for determining the CRTC instance
 557  *
 558  * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
 559  * event handler.
 560  */
 561 static void dm_crtc_high_irq(void *interrupt_params)
 562 {
 563         struct common_irq_params *irq_params = interrupt_params;
 564         struct amdgpu_device *adev = irq_params->adev;
 565         struct amdgpu_crtc *acrtc;
 566         unsigned long flags;
 567         int vrr_active;
 568
 569         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
 570         if (!acrtc)
 571                 return;
 572
 573         vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
 574
 575         DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,
 576                       vrr_active, acrtc->dm_irq_params.active_planes);
 577
 578         /**
 579          * Core vblank handling at start of front-porch is only possible
 580          * in non-vrr mode, as only there vblank timestamping will give
 581          * valid results while done in front-porch. Otherwise defer it
 582          * to dm_vupdate_high_irq after end of front-porch.
 583          */
 584         if (!vrr_active)
 585                 amdgpu_dm_crtc_handle_vblank(acrtc);
 586
 587         /**
 588          * Following stuff must happen at start of vblank, for crc
 589          * computation and below-the-range btr support in vrr mode.
 590          */
 591         amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
 592
 593         /* BTR updates need to happen before VUPDATE on Vega and above. */
 594         if (adev->family < AMDGPU_FAMILY_AI)
 595                 return;
 596
 597         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 598
 599         if (acrtc->dm_irq_params.stream &&
 600             acrtc->dm_irq_params.vrr_params.supported &&
 601             acrtc->dm_irq_params.freesync_config.state ==
 602                     VRR_STATE_ACTIVE_VARIABLE) {
 603                 mod_freesync_handle_v_update(adev->dm.freesync_module,
 604                                              acrtc->dm_irq_params.stream,
 605                                              &acrtc->dm_irq_params.vrr_params);
 606
 607                 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,
 608                                            &acrtc->dm_irq_params.vrr_params.adjust);
 609         }
 610
 611         /*
 612          * If there aren't any active_planes then DCH HUBP may be clock-gated.
 613          * In that case, pageflip completion interrupts won't fire and pageflip
 614          * completion events won't get delivered. Prevent this by sending
 615          * pending pageflip events from here if a flip is still pending.
 616          *
 617          * If any planes are enabled, use dm_pflip_high_irq() instead, to
 618          * avoid race conditions between flip programming and completion,
 619          * which could cause too early flip completion events.
 620          */
 621         if (adev->family >= AMDGPU_FAMILY_RV &&
 622             acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
 623             acrtc->dm_irq_params.active_planes == 0) {
 624                 if (acrtc->event) {
 625                         drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
 626                         acrtc->event = NULL;
 627                         drm_crtc_vblank_put(&acrtc->base);
 628                 }
 629                 acrtc->pflip_status = AMDGPU_FLIP_NONE;
 630         }
 631
 632         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 633 }
 634
 635 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
 636 /**
 637  * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for
 638  * DCN generation ASICs
 639  * @interrupt_params: interrupt parameters
 640  *
 641  * Used to set crc window/read out crc value at vertical line 0 position
 642  */
 643 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)
 644 {
 645         struct common_irq_params *irq_params = interrupt_params;
 646         struct amdgpu_device *adev = irq_params->adev;
 647         struct amdgpu_crtc *acrtc;
 648
 649         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0);
 650
 651         if (!acrtc)
 652                 return;
 653
 654         amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base);
 655 }
 656 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */
 657
 658 /**
 659  * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command.
 660  * @adev: amdgpu_device pointer
 661  * @notify: dmub notification structure
 662  *
 663  * Dmub AUX or SET_CONFIG command completion processing callback
 664  * Copies dmub notification to DM which is to be read by AUX command.
 665  * issuing thread and also signals the event to wake up the thread.
 666  */
 667 static void dmub_aux_setconfig_callback(struct amdgpu_device *adev,
 668                                         struct dmub_notification *notify)
 669 {
 670         if (adev->dm.dmub_notify)
 671                 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification));
 672         if (notify->type == DMUB_NOTIFICATION_AUX_REPLY)
 673                 complete(&adev->dm.dmub_aux_transfer_done);
 674 }
 675
 676 /**
 677  * dmub_hpd_callback - DMUB HPD interrupt processing callback.
 678  * @adev: amdgpu_device pointer
 679  * @notify: dmub notification structure
 680  *
 681  * Dmub Hpd interrupt processing callback. Gets displayindex through the
 682  * ink index and calls helper to do the processing.
 683  */
 684 static void dmub_hpd_callback(struct amdgpu_device *adev,
 685                               struct dmub_notification *notify)
 686 {
 687         struct amdgpu_dm_connector *aconnector;
 688         struct amdgpu_dm_connector *hpd_aconnector = NULL;
 689         struct drm_connector *connector;
 690         struct drm_connector_list_iter iter;
 691         struct dc_link *link;
 692         u8 link_index = 0;
 693         struct drm_device *dev;
 694
 695         if (adev == NULL)
 696                 return;
 697
 698         if (notify == NULL) {
 699                 DRM_ERROR("DMUB HPD callback notification was NULL");
 700                 return;
 701         }
 702
 703         if (notify->link_index > adev->dm.dc->link_count) {
 704                 DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index);
 705                 return;
 706         }
 707
 708         link_index = notify->link_index;
 709         link = adev->dm.dc->links[link_index];
 710         dev = adev->dm.ddev;
 711
 712         drm_connector_list_iter_begin(dev, &iter);
 713         drm_for_each_connector_iter(connector, &iter) {
 714                 aconnector = to_amdgpu_dm_connector(connector);
 715                 if (link && aconnector->dc_link == link) {
 716                         DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index);
 717                         hpd_aconnector = aconnector;
 718                         break;
 719                 }
 720         }
 721         drm_connector_list_iter_end(&iter);
 722
 723         if (hpd_aconnector) {
 724                 if (notify->type == DMUB_NOTIFICATION_HPD)
 725                         handle_hpd_irq_helper(hpd_aconnector);
 726                 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
 727                         handle_hpd_rx_irq(hpd_aconnector);
 728         }
 729 }
 730
 731 /**
 732  * register_dmub_notify_callback - Sets callback for DMUB notify
 733  * @adev: amdgpu_device pointer
 734  * @type: Type of dmub notification
 735  * @callback: Dmub interrupt callback function
 736  * @dmub_int_thread_offload: offload indicator
 737  *
 738  * API to register a dmub callback handler for a dmub notification
 739  * Also sets indicator whether callback processing to be offloaded.
 740  * to dmub interrupt handling thread
 741  * Return: true if successfully registered, false if there is existing registration
 742  */
 743 static bool register_dmub_notify_callback(struct amdgpu_device *adev,
 744                                           enum dmub_notification_type type,
 745                                           dmub_notify_interrupt_callback_t callback,
 746                                           bool dmub_int_thread_offload)
 747 {
 748         if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) {
 749                 adev->dm.dmub_callback[type] = callback;
 750                 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload;
 751         } else
 752                 return false;
 753
 754         return true;
 755 }
 756
 757 static void dm_handle_hpd_work(struct work_struct *work)
 758 {
 759         struct dmub_hpd_work *dmub_hpd_wrk;
 760
 761         dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work);
 762
 763         if (!dmub_hpd_wrk->dmub_notify) {
 764                 DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL");
 765                 return;
 766         }
 767
 768         if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) {
 769                 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev,
 770                 dmub_hpd_wrk->dmub_notify);
 771         }
 772
 773         kfree(dmub_hpd_wrk->dmub_notify);
 774         kfree(dmub_hpd_wrk);
 775
 776 }
 777
 778 #define DMUB_TRACE_MAX_READ 64
 779 /**
 780  * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt
 781  * @interrupt_params: used for determining the Outbox instance
 782  *
 783  * Handles the Outbox Interrupt
 784  * event handler.
 785  */
 786 static void dm_dmub_outbox1_low_irq(void *interrupt_params)
 787 {
 788         struct dmub_notification notify;
 789         struct common_irq_params *irq_params = interrupt_params;
 790         struct amdgpu_device *adev = irq_params->adev;
 791         struct amdgpu_display_manager *dm = &adev->dm;
 792         struct dmcub_trace_buf_entry entry = { 0 };
 793         u32 count = 0;
 794         struct dmub_hpd_work *dmub_hpd_wrk;
 795         struct dc_link *plink = NULL;
 796
 797         if (dc_enable_dmub_notifications(adev->dm.dc) &&
 798                 irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) {
 799
 800                 do {
 801                         dc_stat_get_dmub_notification(adev->dm.dc, &notify);
 802                         if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) {
 803                                 DRM_ERROR("DM: notify type %d invalid!", notify.type);
 804                                 continue;
 805                         }
 806                         if (!dm->dmub_callback[notify.type]) {
 807                                 DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type);
 808                                 continue;
 809                         }
 810                         if (dm->dmub_thread_offload[notify.type] == true) {
 811                                 dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC);
 812                                 if (!dmub_hpd_wrk) {
 813                                         DRM_ERROR("Failed to allocate dmub_hpd_wrk");
 814                                         return;
 815                                 }
 816                                 dmub_hpd_wrk->dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_ATOMIC);
 817                                 if (!dmub_hpd_wrk->dmub_notify) {
 818                                         kfree(dmub_hpd_wrk);
 819                                         DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify");
 820                                         return;
 821                                 }
 822                                 INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work);
 823                                 if (dmub_hpd_wrk->dmub_notify)
 824                                         memcpy(dmub_hpd_wrk->dmub_notify, &notify, sizeof(struct dmub_notification));
 825                                 dmub_hpd_wrk->adev = adev;
 826                                 if (notify.type == DMUB_NOTIFICATION_HPD) {
 827                                         plink = adev->dm.dc->links[notify.link_index];
 828                                         if (plink) {
 829                                                 plink->hpd_status =
 830                                                         notify.hpd_status == DP_HPD_PLUG;
 831                                         }
 832                                 }
 833                                 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work);
 834                         } else {
 835                                 dm->dmub_callback[notify.type](adev, &notify);
 836                         }
 837                 } while (notify.pending_notification);
 838         }
 839
 840
 841         do {
 842                 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {
 843                         trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,
 844                                                         entry.param0, entry.param1);
 845
 846                         DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",
 847                                  entry.trace_code, entry.tick_count, entry.param0, entry.param1);
 848                 } else
 849                         break;
 850
 851                 count++;
 852
 853         } while (count <= DMUB_TRACE_MAX_READ);
 854
 855         if (count > DMUB_TRACE_MAX_READ)
 856                 DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ");
 857 }
 858
 859 static int dm_set_clockgating_state(void *handle,
 860                   enum amd_clockgating_state state)
 861 {
 862         return 0;
 863 }
 864
 865 static int dm_set_powergating_state(void *handle,
 866                   enum amd_powergating_state state)
 867 {
 868         return 0;
 869 }
 870
 871 /* Prototypes of private functions */
 872 static int dm_early_init(void* handle);
 873
 874 /* Allocate memory for FBC compressed data  */
 875 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
 876 {
 877         struct drm_device *dev = connector->dev;
 878         struct amdgpu_device *adev = drm_to_adev(dev);
 879         struct dm_compressor_info *compressor = &adev->dm.compressor;
 880         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
 881         struct drm_display_mode *mode;
 882         unsigned long max_size = 0;
 883
 884         if (adev->dm.dc->fbc_compressor == NULL)
 885                 return;
 886
 887         if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
 888                 return;
 889
 890         if (compressor->bo_ptr)
 891                 return;
 892
 893
 894         list_for_each_entry(mode, &connector->modes, head) {
 895                 if (max_size < mode->htotal * mode->vtotal)
 896                         max_size = mode->htotal * mode->vtotal;
 897         }
 898
 899         if (max_size) {
 900                 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
 901                             AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
 902                             &compressor->gpu_addr, &compressor->cpu_addr);
 903
 904                 if (r)
 905                         DRM_ERROR("DM: Failed to initialize FBC\n");
 906                 else {
 907                         adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
 908                         DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
 909                 }
 910
 911         }
 912
 913 }
 914
 915 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
 916                                           int pipe, bool *enabled,
 917                                           unsigned char *buf, int max_bytes)
 918 {
 919         struct drm_device *dev = dev_get_drvdata(kdev);
 920         struct amdgpu_device *adev = drm_to_adev(dev);
 921         struct drm_connector *connector;
 922         struct drm_connector_list_iter conn_iter;
 923         struct amdgpu_dm_connector *aconnector;
 924         int ret = 0;
 925
 926         *enabled = false;
 927
 928         mutex_lock(&adev->dm.audio_lock);
 929
 930         drm_connector_list_iter_begin(dev, &conn_iter);
 931         drm_for_each_connector_iter(connector, &conn_iter) {
 932                 aconnector = to_amdgpu_dm_connector(connector);
 933                 if (aconnector->audio_inst != port)
 934                         continue;
 935
 936                 *enabled = true;
 937                 ret = drm_eld_size(connector->eld);
 938                 memcpy(buf, connector->eld, min(max_bytes, ret));
 939
 940                 break;
 941         }
 942         drm_connector_list_iter_end(&conn_iter);
 943
 944         mutex_unlock(&adev->dm.audio_lock);
 945
 946         DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
 947
 948         return ret;
 949 }
 950
 951 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
 952         .get_eld = amdgpu_dm_audio_component_get_eld,
 953 };
 954
 955 static int amdgpu_dm_audio_component_bind(struct device *kdev,
 956                                        struct device *hda_kdev, void *data)
 957 {
 958         struct drm_device *dev = dev_get_drvdata(kdev);
 959         struct amdgpu_device *adev = drm_to_adev(dev);
 960         struct drm_audio_component *acomp = data;
 961
 962         acomp->ops = &amdgpu_dm_audio_component_ops;
 963         acomp->dev = kdev;
 964         adev->dm.audio_component = acomp;
 965
 966         return 0;
 967 }
 968
 969 static void amdgpu_dm_audio_component_unbind(struct device *kdev,
 970                                           struct device *hda_kdev, void *data)
 971 {
 972         struct drm_device *dev = dev_get_drvdata(kdev);
 973         struct amdgpu_device *adev = drm_to_adev(dev);
 974         struct drm_audio_component *acomp = data;
 975
 976         acomp->ops = NULL;
 977         acomp->dev = NULL;
 978         adev->dm.audio_component = NULL;
 979 }
 980
 981 static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
 982         .bind   = amdgpu_dm_audio_component_bind,
 983         .unbind = amdgpu_dm_audio_component_unbind,
 984 };
 985
 986 static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
 987 {
 988         int i, ret;
 989
 990         if (!amdgpu_audio)
 991                 return 0;
 992
 993         adev->mode_info.audio.enabled = true;
 994
 995         adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
 996
 997         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
 998                 adev->mode_info.audio.pin[i].channels = -1;
 999                 adev->mode_info.audio.pin[i].rate = -1;
1000                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1001                 adev->mode_info.audio.pin[i].status_bits = 0;
1002                 adev->mode_info.audio.pin[i].category_code = 0;
1003                 adev->mode_info.audio.pin[i].connected = false;
1004                 adev->mode_info.audio.pin[i].id =
1005                         adev->dm.dc->res_pool->audios[i]->inst;
1006                 adev->mode_info.audio.pin[i].offset = 0;
1007         }
1008
1009         ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1010         if (ret < 0)
1011                 return ret;
1012
1013         adev->dm.audio_registered = true;
1014
1015         return 0;
1016 }
1017
1018 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
1019 {
1020         if (!amdgpu_audio)
1021                 return;
1022
1023         if (!adev->mode_info.audio.enabled)
1024                 return;
1025
1026         if (adev->dm.audio_registered) {
1027                 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1028                 adev->dm.audio_registered = false;
1029         }
1030
1031         /* TODO: Disable audio? */
1032
1033         adev->mode_info.audio.enabled = false;
1034 }
1035
1036 static  void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
1037 {
1038         struct drm_audio_component *acomp = adev->dm.audio_component;
1039
1040         if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
1041                 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
1042
1043                 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
1044                                                  pin, -1);
1045         }
1046 }
1047
1048 static int dm_dmub_hw_init(struct amdgpu_device *adev)
1049 {
1050         const struct dmcub_firmware_header_v1_0 *hdr;
1051         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1052         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
1053         const struct firmware *dmub_fw = adev->dm.dmub_fw;
1054         struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
1055         struct abm *abm = adev->dm.dc->res_pool->abm;
1056         struct dmub_srv_hw_params hw_params;
1057         enum dmub_status status;
1058         const unsigned char *fw_inst_const, *fw_bss_data;
1059         u32 i, fw_inst_const_size, fw_bss_data_size;
1060         bool has_hw_support;
1061
1062         if (!dmub_srv)
1063                 /* DMUB isn't supported on the ASIC. */
1064                 return 0;
1065
1066         if (!fb_info) {
1067                 DRM_ERROR("No framebuffer info for DMUB service.\n");
1068                 return -EINVAL;
1069         }
1070
1071         if (!dmub_fw) {
1072                 /* Firmware required for DMUB support. */
1073                 DRM_ERROR("No firmware provided for DMUB.\n");
1074                 return -EINVAL;
1075         }
1076
1077         status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
1078         if (status != DMUB_STATUS_OK) {
1079                 DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
1080                 return -EINVAL;
1081         }
1082
1083         if (!has_hw_support) {
1084                 DRM_INFO("DMUB unsupported on ASIC\n");
1085                 return 0;
1086         }
1087
1088         /* Reset DMCUB if it was previously running - before we overwrite its memory. */
1089         status = dmub_srv_hw_reset(dmub_srv);
1090         if (status != DMUB_STATUS_OK)
1091                 DRM_WARN("Error resetting DMUB HW: %d\n", status);
1092
1093         hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
1094
1095         fw_inst_const = dmub_fw->data +
1096                         le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1097                         PSP_HEADER_BYTES;
1098
1099         fw_bss_data = dmub_fw->data +
1100                       le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1101                       le32_to_cpu(hdr->inst_const_bytes);
1102
1103         /* Copy firmware and bios info into FB memory. */
1104         fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
1105                              PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
1106
1107         fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
1108
1109         /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP,
1110          * amdgpu_ucode_init_single_fw will load dmub firmware
1111          * fw_inst_const part to cw0; otherwise, the firmware back door load
1112          * will be done by dm_dmub_hw_init
1113          */
1114         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1115                 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
1116                                 fw_inst_const_size);
1117         }
1118
1119         if (fw_bss_data_size)
1120                 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr,
1121                        fw_bss_data, fw_bss_data_size);
1122
1123         /* Copy firmware bios info into FB memory. */
1124         memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,
1125                adev->bios_size);
1126
1127         /* Reset regions that need to be reset. */
1128         memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,
1129         fb_info->fb[DMUB_WINDOW_4_MAILBOX].size);
1130
1131         memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,
1132                fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size);
1133
1134         memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,
1135                fb_info->fb[DMUB_WINDOW_6_FW_STATE].size);
1136
1137         /* Initialize hardware. */
1138         memset(&hw_params, 0, sizeof(hw_params));
1139         hw_params.fb_base = adev->gmc.fb_start;
1140         hw_params.fb_offset = adev->vm_manager.vram_base_offset;
1141
1142         /* backdoor load firmware and trigger dmub running */
1143         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
1144                 hw_params.load_inst_const = true;
1145
1146         if (dmcu)
1147                 hw_params.psp_version = dmcu->psp_version;
1148
1149         for (i = 0; i < fb_info->num_fb; ++i)
1150                 hw_params.fb[i] = &fb_info->fb[i];
1151
1152         switch (adev->ip_versions[DCE_HWIP][0]) {
1153         case IP_VERSION(3, 1, 3):
1154         case IP_VERSION(3, 1, 4):
1155                 hw_params.dpia_supported = true;
1156                 hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia;
1157                 break;
1158         default:
1159                 break;
1160         }
1161
1162         status = dmub_srv_hw_init(dmub_srv, &hw_params);
1163         if (status != DMUB_STATUS_OK) {
1164                 DRM_ERROR("Error initializing DMUB HW: %d\n", status);
1165                 return -EINVAL;
1166         }
1167
1168         /* Wait for firmware load to finish. */
1169         status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1170         if (status != DMUB_STATUS_OK)
1171                 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1172
1173         /* Init DMCU and ABM if available. */
1174         if (dmcu && abm) {
1175                 dmcu->funcs->dmcu_init(dmcu);
1176                 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
1177         }
1178
1179         if (!adev->dm.dc->ctx->dmub_srv)
1180                 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
1181         if (!adev->dm.dc->ctx->dmub_srv) {
1182                 DRM_ERROR("Couldn't allocate DC DMUB server!\n");
1183                 return -ENOMEM;
1184         }
1185
1186         DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
1187                  adev->dm.dmcub_fw_version);
1188
1189         return 0;
1190 }
1191
1192 static void dm_dmub_hw_resume(struct amdgpu_device *adev)
1193 {
1194         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1195         enum dmub_status status;
1196         bool init;
1197
1198         if (!dmub_srv) {
1199                 /* DMUB isn't supported on the ASIC. */
1200                 return;
1201         }
1202
1203         status = dmub_srv_is_hw_init(dmub_srv, &init);
1204         if (status != DMUB_STATUS_OK)
1205                 DRM_WARN("DMUB hardware init check failed: %d\n", status);
1206
1207         if (status == DMUB_STATUS_OK && init) {
1208                 /* Wait for firmware load to finish. */
1209                 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1210                 if (status != DMUB_STATUS_OK)
1211                         DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1212         } else {
1213                 /* Perform the full hardware initialization. */
1214                 dm_dmub_hw_init(adev);
1215         }
1216 }
1217
1218 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
1219 {
1220         u64 pt_base;
1221         u32 logical_addr_low;
1222         u32 logical_addr_high;
1223         u32 agp_base, agp_bot, agp_top;
1224         PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;
1225
1226         memset(pa_config, 0, sizeof(*pa_config));
1227
1228         agp_base = 0;
1229         agp_bot = adev->gmc.agp_start >> 24;
1230         agp_top = adev->gmc.agp_end >> 24;
1231
1232         /* AGP aperture is disabled */
1233         if (agp_bot == agp_top) {
1234                 logical_addr_low = adev->gmc.fb_start >> 18;
1235                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1236                         /*
1237                          * Raven2 has a HW issue that it is unable to use the vram which
1238                          * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1239                          * workaround that increase system aperture high address (add 1)
1240                          * to get rid of the VM fault and hardware hang.
1241                          */
1242                         logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1;
1243                 else
1244                         logical_addr_high = adev->gmc.fb_end >> 18;
1245         } else {
1246                 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
1247                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1248                         /*
1249                          * Raven2 has a HW issue that it is unable to use the vram which
1250                          * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1251                          * workaround that increase system aperture high address (add 1)
1252                          * to get rid of the VM fault and hardware hang.
1253                          */
1254                         logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
1255                 else
1256                         logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
1257         }
1258
1259         pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
1260
1261         page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF;
1262         page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12);
1263         page_table_end.high_part = (u32)(adev->gmc.gart_end >> 44) & 0xF;
1264         page_table_end.low_part = (u32)(adev->gmc.gart_end >> 12);
1265         page_table_base.high_part = upper_32_bits(pt_base) & 0xF;
1266         page_table_base.low_part = lower_32_bits(pt_base);
1267
1268         pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
1269         pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18;
1270
1271         pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24 ;
1272         pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24;
1273         pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24;
1274
1275         pa_config->system_aperture.fb_base = adev->gmc.fb_start;
1276         pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset;
1277         pa_config->system_aperture.fb_top = adev->gmc.fb_end;
1278
1279         pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12;
1280         pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12;
1281         pa_config->gart_config.page_table_base_addr = page_table_base.quad_part;
1282
1283         pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support;
1284
1285 }
1286
1287 static void force_connector_state(
1288         struct amdgpu_dm_connector *aconnector,
1289         enum drm_connector_force force_state)
1290 {
1291         struct drm_connector *connector = &aconnector->base;
1292
1293         mutex_lock(&connector->dev->mode_config.mutex);
1294         aconnector->base.force = force_state;
1295         mutex_unlock(&connector->dev->mode_config.mutex);
1296
1297         mutex_lock(&aconnector->hpd_lock);
1298         drm_kms_helper_connector_hotplug_event(connector);
1299         mutex_unlock(&aconnector->hpd_lock);
1300 }
1301
1302 static void dm_handle_hpd_rx_offload_work(struct work_struct *work)
1303 {
1304         struct hpd_rx_irq_offload_work *offload_work;
1305         struct amdgpu_dm_connector *aconnector;
1306         struct dc_link *dc_link;
1307         struct amdgpu_device *adev;
1308         enum dc_connection_type new_connection_type = dc_connection_none;
1309         unsigned long flags;
1310         union test_response test_response;
1311
1312         memset(&test_response, 0, sizeof(test_response));
1313
1314         offload_work = container_of(work, struct hpd_rx_irq_offload_work, work);
1315         aconnector = offload_work->offload_wq->aconnector;
1316
1317         if (!aconnector) {
1318                 DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work");
1319                 goto skip;
1320         }
1321
1322         adev = drm_to_adev(aconnector->base.dev);
1323         dc_link = aconnector->dc_link;
1324
1325         mutex_lock(&aconnector->hpd_lock);
1326         if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
1327                 DRM_ERROR("KMS: Failed to detect connector\n");
1328         mutex_unlock(&aconnector->hpd_lock);
1329
1330         if (new_connection_type == dc_connection_none)
1331                 goto skip;
1332
1333         if (amdgpu_in_reset(adev))
1334                 goto skip;
1335
1336         mutex_lock(&adev->dm.dc_lock);
1337         if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
1338                 dc_link_dp_handle_automated_test(dc_link);
1339
1340                 if (aconnector->timing_changed) {
1341                         /* force connector disconnect and reconnect */
1342                         force_connector_state(aconnector, DRM_FORCE_OFF);
1343                         msleep(100);
1344                         force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED);
1345                 }
1346
1347                 test_response.bits.ACK = 1;
1348
1349                 core_link_write_dpcd(
1350                 dc_link,
1351                 DP_TEST_RESPONSE,
1352                 &test_response.raw,
1353                 sizeof(test_response));
1354         }
1355         else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) &&
1356                         dc_link_check_link_loss_status(dc_link, &offload_work->data) &&
1357                         dc_link_dp_allow_hpd_rx_irq(dc_link)) {
1358                 /* offload_work->data is from handle_hpd_rx_irq->
1359                  * schedule_hpd_rx_offload_work.this is defer handle
1360                  * for hpd short pulse. upon here, link status may be
1361                  * changed, need get latest link status from dpcd
1362                  * registers. if link status is good, skip run link
1363                  * training again.
1364                  */
1365                 union hpd_irq_data irq_data;
1366
1367                 memset(&irq_data, 0, sizeof(irq_data));
1368
1369                 /* before dc_link_dp_handle_link_loss, allow new link lost handle
1370                  * request be added to work queue if link lost at end of dc_link_
1371                  * dp_handle_link_loss
1372                  */
1373                 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1374                 offload_work->offload_wq->is_handling_link_loss = false;
1375                 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1376
1377                 if ((dc_link_dp_read_hpd_rx_irq_data(dc_link, &irq_data) == DC_OK) &&
1378                         dc_link_check_link_loss_status(dc_link, &irq_data))
1379                         dc_link_dp_handle_link_loss(dc_link);
1380         }
1381         mutex_unlock(&adev->dm.dc_lock);
1382
1383 skip:
1384         kfree(offload_work);
1385
1386 }
1387
1388 static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc)
1389 {
1390         int max_caps = dc->caps.max_links;
1391         int i = 0;
1392         struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL;
1393
1394         hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL);
1395
1396         if (!hpd_rx_offload_wq)
1397                 return NULL;
1398
1399
1400         for (i = 0; i < max_caps; i++) {
1401                 hpd_rx_offload_wq[i].wq =
1402                                     create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq");
1403
1404                 if (hpd_rx_offload_wq[i].wq == NULL) {
1405                         DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!");
1406                         goto out_err;
1407                 }
1408
1409                 spin_lock_init(&hpd_rx_offload_wq[i].offload_lock);
1410         }
1411
1412         return hpd_rx_offload_wq;
1413
1414 out_err:
1415         for (i = 0; i < max_caps; i++) {
1416                 if (hpd_rx_offload_wq[i].wq)
1417                         destroy_workqueue(hpd_rx_offload_wq[i].wq);
1418         }
1419         kfree(hpd_rx_offload_wq);
1420         return NULL;
1421 }
1422
1423 struct amdgpu_stutter_quirk {
1424         u16 chip_vendor;
1425         u16 chip_device;
1426         u16 subsys_vendor;
1427         u16 subsys_device;
1428         u8 revision;
1429 };
1430
1431 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = {
1432         /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */
1433         { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },
1434         { 0, 0, 0, 0, 0 },
1435 };
1436
1437 static bool dm_should_disable_stutter(struct pci_dev *pdev)
1438 {
1439         const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list;
1440
1441         while (p && p->chip_device != 0) {
1442                 if (pdev->vendor == p->chip_vendor &&
1443                     pdev->device == p->chip_device &&
1444                     pdev->subsystem_vendor == p->subsys_vendor &&
1445                     pdev->subsystem_device == p->subsys_device &&
1446                     pdev->revision == p->revision) {
1447                         return true;
1448                 }
1449                 ++p;
1450         }
1451         return false;
1452 }
1453
1454 static const struct dmi_system_id hpd_disconnect_quirk_table[] = {
1455         {
1456                 .matches = {
1457                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1458                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"),
1459                 },
1460         },
1461         {
1462                 .matches = {
1463                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1464                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"),
1465                 },
1466         },
1467         {
1468                 .matches = {
1469                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1470                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"),
1471                 },
1472         },
1473         {
1474                 .matches = {
1475                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1476                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"),
1477                 },
1478         },
1479         {
1480                 .matches = {
1481                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1482                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"),
1483                 },
1484         },
1485         {
1486                 .matches = {
1487                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1488                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"),
1489                 },
1490         },
1491         {
1492                 .matches = {
1493                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1494                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"),
1495                 },
1496         },
1497         {
1498                 .matches = {
1499                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1500                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"),
1501                 },
1502         },
1503         {
1504                 .matches = {
1505                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1506                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"),
1507                 },
1508         },
1509         {}
1510         /* TODO: refactor this from a fixed table to a dynamic option */
1511 };
1512
1513 static void retrieve_dmi_info(struct amdgpu_display_manager *dm)
1514 {
1515         const struct dmi_system_id *dmi_id;
1516
1517         dm->aux_hpd_discon_quirk = false;
1518
1519         dmi_id = dmi_first_match(hpd_disconnect_quirk_table);
1520         if (dmi_id) {
1521                 dm->aux_hpd_discon_quirk = true;
1522                 DRM_INFO("aux_hpd_discon_quirk attached\n");
1523         }
1524 }
1525
1526 static int amdgpu_dm_init(struct amdgpu_device *adev)
1527 {
1528         struct dc_init_data init_data;
1529         struct dc_callback_init init_params;
1530         int r;
1531
1532         adev->dm.ddev = adev_to_drm(adev);
1533         adev->dm.adev = adev;
1534
1535         /* Zero all the fields */
1536         memset(&init_data, 0, sizeof(init_data));
1537         memset(&init_params, 0, sizeof(init_params));
1538
1539         mutex_init(&adev->dm.dpia_aux_lock);
1540         mutex_init(&adev->dm.dc_lock);
1541         mutex_init(&adev->dm.audio_lock);
1542
1543         if(amdgpu_dm_irq_init(adev)) {
1544                 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
1545                 goto error;
1546         }
1547
1548         init_data.asic_id.chip_family = adev->family;
1549
1550         init_data.asic_id.pci_revision_id = adev->pdev->revision;
1551         init_data.asic_id.hw_internal_rev = adev->external_rev_id;
1552         init_data.asic_id.chip_id = adev->pdev->device;
1553
1554         init_data.asic_id.vram_width = adev->gmc.vram_width;
1555         /* TODO: initialize init_data.asic_id.vram_type here!!!! */
1556         init_data.asic_id.atombios_base_address =
1557                 adev->mode_info.atom_context->bios;
1558
1559         init_data.driver = adev;
1560
1561         adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
1562
1563         if (!adev->dm.cgs_device) {
1564                 DRM_ERROR("amdgpu: failed to create cgs device.\n");
1565                 goto error;
1566         }
1567
1568         init_data.cgs_device = adev->dm.cgs_device;
1569
1570         init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
1571
1572         switch (adev->ip_versions[DCE_HWIP][0]) {
1573         case IP_VERSION(2, 1, 0):
1574                 switch (adev->dm.dmcub_fw_version) {
1575                 case 0: /* development */
1576                 case 0x1: /* linux-firmware.git hash 6d9f399 */
1577                 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */
1578                         init_data.flags.disable_dmcu = false;
1579                         break;
1580                 default:
1581                         init_data.flags.disable_dmcu = true;
1582                 }
1583                 break;
1584         case IP_VERSION(2, 0, 3):
1585                 init_data.flags.disable_dmcu = true;
1586                 break;
1587         default:
1588                 break;
1589         }
1590
1591         switch (adev->asic_type) {
1592         case CHIP_CARRIZO:
1593         case CHIP_STONEY:
1594                 init_data.flags.gpu_vm_support = true;
1595                 break;
1596         default:
1597                 switch (adev->ip_versions[DCE_HWIP][0]) {
1598                 case IP_VERSION(1, 0, 0):
1599                 case IP_VERSION(1, 0, 1):
1600                         /* enable S/G on PCO and RV2 */
1601                         if ((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
1602                             (adev->apu_flags & AMD_APU_IS_PICASSO))
1603                                 init_data.flags.gpu_vm_support = true;
1604                         break;
1605                 case IP_VERSION(2, 1, 0):
1606                 case IP_VERSION(3, 0, 1):
1607                 case IP_VERSION(3, 1, 2):
1608                 case IP_VERSION(3, 1, 3):
1609                 case IP_VERSION(3, 1, 4):
1610                 case IP_VERSION(3, 1, 5):
1611                 case IP_VERSION(3, 1, 6):
1612                         init_data.flags.gpu_vm_support = true;
1613                         break;
1614                 default:
1615                         break;
1616                 }
1617                 break;
1618         }
1619         if (init_data.flags.gpu_vm_support &&
1620             (amdgpu_sg_display == 0))
1621                 init_data.flags.gpu_vm_support = false;
1622
1623         if (init_data.flags.gpu_vm_support)
1624                 adev->mode_info.gpu_vm_support = true;
1625
1626         if (amdgpu_dc_feature_mask & DC_FBC_MASK)
1627                 init_data.flags.fbc_support = true;
1628
1629         if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
1630                 init_data.flags.multi_mon_pp_mclk_switch = true;
1631
1632         if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
1633                 init_data.flags.disable_fractional_pwm = true;
1634
1635         if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING)
1636                 init_data.flags.edp_no_power_sequencing = true;
1637
1638         if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A)
1639                 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true;
1640         if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)
1641                 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;
1642
1643         /* Disable SubVP + DRR config by default */
1644         init_data.flags.disable_subvp_drr = true;
1645         if (amdgpu_dc_feature_mask & DC_ENABLE_SUBVP_DRR)
1646                 init_data.flags.disable_subvp_drr = false;
1647
1648         init_data.flags.seamless_boot_edp_requested = false;
1649
1650         if (check_seamless_boot_capability(adev)) {
1651                 init_data.flags.seamless_boot_edp_requested = true;
1652                 init_data.flags.allow_seamless_boot_optimization = true;
1653                 DRM_INFO("Seamless boot condition check passed\n");
1654         }
1655
1656         init_data.flags.enable_mipi_converter_optimization = true;
1657
1658         init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];
1659         init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];
1660
1661         INIT_LIST_HEAD(&adev->dm.da_list);
1662
1663         retrieve_dmi_info(&adev->dm);
1664
1665         /* Display Core create. */
1666         adev->dm.dc = dc_create(&init_data);
1667
1668         if (adev->dm.dc) {
1669                 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
1670         } else {
1671                 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
1672                 goto error;
1673         }
1674
1675         if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
1676                 adev->dm.dc->debug.force_single_disp_pipe_split = false;
1677                 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
1678         }
1679
1680         if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
1681                 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
1682         if (dm_should_disable_stutter(adev->pdev))
1683                 adev->dm.dc->debug.disable_stutter = true;
1684
1685         if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
1686                 adev->dm.dc->debug.disable_stutter = true;
1687
1688         if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) {
1689                 adev->dm.dc->debug.disable_dsc = true;
1690         }
1691
1692         if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
1693                 adev->dm.dc->debug.disable_clock_gate = true;
1694
1695         if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH)
1696                 adev->dm.dc->debug.force_subvp_mclk_switch = true;
1697
1698         adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm;
1699
1700         /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */
1701         adev->dm.dc->debug.ignore_cable_id = true;
1702
1703         /* TODO: There is a new drm mst change where the freedom of
1704          * vc_next_start_slot update is revoked/moved into drm, instead of in
1705          * driver. This forces us to make sure to get vc_next_start_slot updated
1706          * in drm function each time without considering if mst_state is active
1707          * or not. Otherwise, next time hotplug will give wrong start_slot
1708          * number. We are implementing a temporary solution to even notify drm
1709          * mst deallocation when link is no longer of MST type when uncommitting
1710          * the stream so we will have more time to work on a proper solution.
1711          * Ideally when dm_helpers_dp_mst_stop_top_mgr message is triggered, we
1712          * should notify drm to do a complete "reset" of its states and stop
1713          * calling further drm mst functions when link is no longer of an MST
1714          * type. This could happen when we unplug an MST hubs/displays. When
1715          * uncommit stream comes later after unplug, we should just reset
1716          * hardware states only.
1717          */
1718         adev->dm.dc->debug.temp_mst_deallocation_sequence = true;
1719
1720         if (adev->dm.dc->caps.dp_hdmi21_pcon_support)
1721                 DRM_INFO("DP-HDMI FRL PCON supported\n");
1722
1723         r = dm_dmub_hw_init(adev);
1724         if (r) {
1725                 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
1726                 goto error;
1727         }
1728
1729         dc_hardware_init(adev->dm.dc);
1730
1731         adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc);
1732         if (!adev->dm.hpd_rx_offload_wq) {
1733                 DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n");
1734                 goto error;
1735         }
1736
1737         if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) {
1738                 struct dc_phy_addr_space_config pa_config;
1739
1740                 mmhub_read_system_context(adev, &pa_config);
1741
1742                 // Call the DC init_memory func
1743                 dc_setup_system_context(adev->dm.dc, &pa_config);
1744         }
1745
1746         adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
1747         if (!adev->dm.freesync_module) {
1748                 DRM_ERROR(
1749                 "amdgpu: failed to initialize freesync_module.\n");
1750         } else
1751                 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
1752                                 adev->dm.freesync_module);
1753
1754         amdgpu_dm_init_color_mod();
1755
1756         if (adev->dm.dc->caps.max_links > 0) {
1757                 adev->dm.vblank_control_workqueue =
1758                         create_singlethread_workqueue("dm_vblank_control_workqueue");
1759                 if (!adev->dm.vblank_control_workqueue)
1760                         DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n");
1761         }
1762
1763         if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
1764                 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
1765
1766                 if (!adev->dm.hdcp_workqueue)
1767                         DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
1768                 else
1769                         DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
1770
1771                 dc_init_callbacks(adev->dm.dc, &init_params);
1772         }
1773 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1774         adev->dm.secure_display_ctxs = amdgpu_dm_crtc_secure_display_create_contexts(adev);
1775         if (!adev->dm.secure_display_ctxs) {
1776                 DRM_ERROR("amdgpu: failed to initialize secure_display_ctxs.\n");
1777         }
1778 #endif
1779         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
1780                 init_completion(&adev->dm.dmub_aux_transfer_done);
1781                 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL);
1782                 if (!adev->dm.dmub_notify) {
1783                         DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify");
1784                         goto error;
1785                 }
1786
1787                 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq");
1788                 if (!adev->dm.delayed_hpd_wq) {
1789                         DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n");
1790                         goto error;
1791                 }
1792
1793                 amdgpu_dm_outbox_init(adev);
1794                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY,
1795                         dmub_aux_setconfig_callback, false)) {
1796                         DRM_ERROR("amdgpu: fail to register dmub aux callback");
1797                         goto error;
1798                 }
1799                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true)) {
1800                         DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1801                         goto error;
1802                 }
1803                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true)) {
1804                         DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1805                         goto error;
1806                 }
1807         }
1808
1809         /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive.
1810          * It is expected that DMUB will resend any pending notifications at this point, for
1811          * example HPD from DPIA.
1812          */
1813         if (dc_is_dmub_outbox_supported(adev->dm.dc))
1814                 dc_enable_dmub_outbox(adev->dm.dc);
1815
1816         if (amdgpu_dm_initialize_drm_device(adev)) {
1817                 DRM_ERROR(
1818                 "amdgpu: failed to initialize sw for display support.\n");
1819                 goto error;
1820         }
1821
1822         /* create fake encoders for MST */
1823         dm_dp_create_fake_mst_encoders(adev);
1824
1825         /* TODO: Add_display_info? */
1826
1827         /* TODO use dynamic cursor width */
1828         adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
1829         adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
1830
1831         if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
1832                 DRM_ERROR(
1833                 "amdgpu: failed to initialize sw for display support.\n");
1834                 goto error;
1835         }
1836
1837
1838         DRM_DEBUG_DRIVER("KMS initialized.\n");
1839
1840         return 0;
1841 error:
1842         amdgpu_dm_fini(adev);
1843
1844         return -EINVAL;
1845 }
1846
1847 static int amdgpu_dm_early_fini(void *handle)
1848 {
1849         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1850
1851         amdgpu_dm_audio_fini(adev);
1852
1853         return 0;
1854 }
1855
1856 static void amdgpu_dm_fini(struct amdgpu_device *adev)
1857 {
1858         int i;
1859
1860         if (adev->dm.vblank_control_workqueue) {
1861                 destroy_workqueue(adev->dm.vblank_control_workqueue);
1862                 adev->dm.vblank_control_workqueue = NULL;
1863         }
1864
1865         amdgpu_dm_destroy_drm_device(&adev->dm);
1866
1867 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1868         if (adev->dm.secure_display_ctxs) {
1869                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1870                         if (adev->dm.secure_display_ctxs[i].crtc) {
1871                                 flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work);
1872                                 flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work);
1873                         }
1874                 }
1875                 kfree(adev->dm.secure_display_ctxs);
1876                 adev->dm.secure_display_ctxs = NULL;
1877         }
1878 #endif
1879         if (adev->dm.hdcp_workqueue) {
1880                 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue);
1881                 adev->dm.hdcp_workqueue = NULL;
1882         }
1883
1884         if (adev->dm.dc)
1885                 dc_deinit_callbacks(adev->dm.dc);
1886
1887         dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
1888
1889         if (dc_enable_dmub_notifications(adev->dm.dc)) {
1890                 kfree(adev->dm.dmub_notify);
1891                 adev->dm.dmub_notify = NULL;
1892                 destroy_workqueue(adev->dm.delayed_hpd_wq);
1893                 adev->dm.delayed_hpd_wq = NULL;
1894         }
1895
1896         if (adev->dm.dmub_bo)
1897                 amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
1898                                       &adev->dm.dmub_bo_gpu_addr,
1899                                       &adev->dm.dmub_bo_cpu_addr);
1900
1901         if (adev->dm.hpd_rx_offload_wq) {
1902                 for (i = 0; i < adev->dm.dc->caps.max_links; i++) {
1903                         if (adev->dm.hpd_rx_offload_wq[i].wq) {
1904                                 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq);
1905                                 adev->dm.hpd_rx_offload_wq[i].wq = NULL;
1906                         }
1907                 }
1908
1909                 kfree(adev->dm.hpd_rx_offload_wq);
1910                 adev->dm.hpd_rx_offload_wq = NULL;
1911         }
1912
1913         /* DC Destroy TODO: Replace destroy DAL */
1914         if (adev->dm.dc)
1915                 dc_destroy(&adev->dm.dc);
1916         /*
1917          * TODO: pageflip, vlank interrupt
1918          *
1919          * amdgpu_dm_irq_fini(adev);
1920          */
1921
1922         if (adev->dm.cgs_device) {
1923                 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
1924                 adev->dm.cgs_device = NULL;
1925         }
1926         if (adev->dm.freesync_module) {
1927                 mod_freesync_destroy(adev->dm.freesync_module);
1928                 adev->dm.freesync_module = NULL;
1929         }
1930
1931         mutex_destroy(&adev->dm.audio_lock);
1932         mutex_destroy(&adev->dm.dc_lock);
1933         mutex_destroy(&adev->dm.dpia_aux_lock);
1934
1935         return;
1936 }
1937
1938 static int load_dmcu_fw(struct amdgpu_device *adev)
1939 {
1940         const char *fw_name_dmcu = NULL;
1941         int r;
1942         const struct dmcu_firmware_header_v1_0 *hdr;
1943
1944         switch(adev->asic_type) {
1945 #if defined(CONFIG_DRM_AMD_DC_SI)
1946         case CHIP_TAHITI:
1947         case CHIP_PITCAIRN:
1948         case CHIP_VERDE:
1949         case CHIP_OLAND:
1950 #endif
1951         case CHIP_BONAIRE:
1952         case CHIP_HAWAII:
1953         case CHIP_KAVERI:
1954         case CHIP_KABINI:
1955         case CHIP_MULLINS:
1956         case CHIP_TONGA:
1957         case CHIP_FIJI:
1958         case CHIP_CARRIZO:
1959         case CHIP_STONEY:
1960         case CHIP_POLARIS11:
1961         case CHIP_POLARIS10:
1962         case CHIP_POLARIS12:
1963         case CHIP_VEGAM:
1964         case CHIP_VEGA10:
1965         case CHIP_VEGA12:
1966         case CHIP_VEGA20:
1967                 return 0;
1968         case CHIP_NAVI12:
1969                 fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
1970                 break;
1971         case CHIP_RAVEN:
1972                 if (ASICREV_IS_PICASSO(adev->external_rev_id))
1973                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1974                 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
1975                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1976                 else
1977                         return 0;
1978                 break;
1979         default:
1980                 switch (adev->ip_versions[DCE_HWIP][0]) {
1981                 case IP_VERSION(2, 0, 2):
1982                 case IP_VERSION(2, 0, 3):
1983                 case IP_VERSION(2, 0, 0):
1984                 case IP_VERSION(2, 1, 0):
1985                 case IP_VERSION(3, 0, 0):
1986                 case IP_VERSION(3, 0, 2):
1987                 case IP_VERSION(3, 0, 3):
1988                 case IP_VERSION(3, 0, 1):
1989                 case IP_VERSION(3, 1, 2):
1990                 case IP_VERSION(3, 1, 3):
1991                 case IP_VERSION(3, 1, 4):
1992                 case IP_VERSION(3, 1, 5):
1993                 case IP_VERSION(3, 1, 6):
1994                 case IP_VERSION(3, 2, 0):
1995                 case IP_VERSION(3, 2, 1):
1996                         return 0;
1997                 default:
1998                         break;
1999                 }
2000                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2001                 return -EINVAL;
2002         }
2003
2004         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2005                 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
2006                 return 0;
2007         }
2008
2009         r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, fw_name_dmcu);
2010         if (r == -ENODEV) {
2011                 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
2012                 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
2013                 adev->dm.fw_dmcu = NULL;
2014                 return 0;
2015         }
2016         if (r) {
2017                 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
2018                         fw_name_dmcu);
2019                 amdgpu_ucode_release(&adev->dm.fw_dmcu);
2020                 return r;
2021         }
2022
2023         hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
2024         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
2025         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
2026         adev->firmware.fw_size +=
2027                 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2028
2029         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
2030         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
2031         adev->firmware.fw_size +=
2032                 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2033
2034         adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
2035
2036         DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
2037
2038         return 0;
2039 }
2040
2041 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
2042 {
2043         struct amdgpu_device *adev = ctx;
2044
2045         return dm_read_reg(adev->dm.dc->ctx, address);
2046 }
2047
2048 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
2049                                      uint32_t value)
2050 {
2051         struct amdgpu_device *adev = ctx;
2052
2053         return dm_write_reg(adev->dm.dc->ctx, address, value);
2054 }
2055
2056 static int dm_dmub_sw_init(struct amdgpu_device *adev)
2057 {
2058         struct dmub_srv_create_params create_params;
2059         struct dmub_srv_region_params region_params;
2060         struct dmub_srv_region_info region_info;
2061         struct dmub_srv_fb_params fb_params;
2062         struct dmub_srv_fb_info *fb_info;
2063         struct dmub_srv *dmub_srv;
2064         const struct dmcub_firmware_header_v1_0 *hdr;
2065         enum dmub_asic dmub_asic;
2066         enum dmub_status status;
2067         int r;
2068
2069         switch (adev->ip_versions[DCE_HWIP][0]) {
2070         case IP_VERSION(2, 1, 0):
2071                 dmub_asic = DMUB_ASIC_DCN21;
2072                 break;
2073         case IP_VERSION(3, 0, 0):
2074                 dmub_asic = DMUB_ASIC_DCN30;
2075                 break;
2076         case IP_VERSION(3, 0, 1):
2077                 dmub_asic = DMUB_ASIC_DCN301;
2078                 break;
2079         case IP_VERSION(3, 0, 2):
2080                 dmub_asic = DMUB_ASIC_DCN302;
2081                 break;
2082         case IP_VERSION(3, 0, 3):
2083                 dmub_asic = DMUB_ASIC_DCN303;
2084                 break;
2085         case IP_VERSION(3, 1, 2):
2086         case IP_VERSION(3, 1, 3):
2087                 dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31;
2088                 break;
2089         case IP_VERSION(3, 1, 4):
2090                 dmub_asic = DMUB_ASIC_DCN314;
2091                 break;
2092         case IP_VERSION(3, 1, 5):
2093                 dmub_asic = DMUB_ASIC_DCN315;
2094                 break;
2095         case IP_VERSION(3, 1, 6):
2096                 dmub_asic = DMUB_ASIC_DCN316;
2097                 break;
2098         case IP_VERSION(3, 2, 0):
2099                 dmub_asic = DMUB_ASIC_DCN32;
2100                 break;
2101         case IP_VERSION(3, 2, 1):
2102                 dmub_asic = DMUB_ASIC_DCN321;
2103                 break;
2104         default:
2105                 /* ASIC doesn't support DMUB. */
2106                 return 0;
2107         }
2108
2109         hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
2110         adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
2111
2112         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2113                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
2114                         AMDGPU_UCODE_ID_DMCUB;
2115                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw =
2116                         adev->dm.dmub_fw;
2117                 adev->firmware.fw_size +=
2118                         ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
2119
2120                 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
2121                          adev->dm.dmcub_fw_version);
2122         }
2123
2124
2125         adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
2126         dmub_srv = adev->dm.dmub_srv;
2127
2128         if (!dmub_srv) {
2129                 DRM_ERROR("Failed to allocate DMUB service!\n");
2130                 return -ENOMEM;
2131         }
2132
2133         memset(&create_params, 0, sizeof(create_params));
2134         create_params.user_ctx = adev;
2135         create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
2136         create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
2137         create_params.asic = dmub_asic;
2138
2139         /* Create the DMUB service. */
2140         status = dmub_srv_create(dmub_srv, &create_params);
2141         if (status != DMUB_STATUS_OK) {
2142                 DRM_ERROR("Error creating DMUB service: %d\n", status);
2143                 return -EINVAL;
2144         }
2145
2146         /* Calculate the size of all the regions for the DMUB service. */
2147         memset(&region_params, 0, sizeof(region_params));
2148
2149         region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
2150                                         PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
2151         region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
2152         region_params.vbios_size = adev->bios_size;
2153         region_params.fw_bss_data = region_params.bss_data_size ?
2154                 adev->dm.dmub_fw->data +
2155                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2156                 le32_to_cpu(hdr->inst_const_bytes) : NULL;
2157         region_params.fw_inst_const =
2158                 adev->dm.dmub_fw->data +
2159                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2160                 PSP_HEADER_BYTES;
2161
2162         status = dmub_srv_calc_region_info(dmub_srv, &region_params,
2163                                            &region_info);
2164
2165         if (status != DMUB_STATUS_OK) {
2166                 DRM_ERROR("Error calculating DMUB region info: %d\n", status);
2167                 return -EINVAL;
2168         }
2169
2170         /*
2171          * Allocate a framebuffer based on the total size of all the regions.
2172          * TODO: Move this into GART.
2173          */
2174         r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
2175                                     AMDGPU_GEM_DOMAIN_VRAM |
2176                                     AMDGPU_GEM_DOMAIN_GTT,
2177                                     &adev->dm.dmub_bo,
2178                                     &adev->dm.dmub_bo_gpu_addr,
2179                                     &adev->dm.dmub_bo_cpu_addr);
2180         if (r)
2181                 return r;
2182
2183         /* Rebase the regions on the framebuffer address. */
2184         memset(&fb_params, 0, sizeof(fb_params));
2185         fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr;
2186         fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr;
2187         fb_params.region_info = &region_info;
2188
2189         adev->dm.dmub_fb_info =
2190                 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);
2191         fb_info = adev->dm.dmub_fb_info;
2192
2193         if (!fb_info) {
2194                 DRM_ERROR(
2195                         "Failed to allocate framebuffer info for DMUB service!\n");
2196                 return -ENOMEM;
2197         }
2198
2199         status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info);
2200         if (status != DMUB_STATUS_OK) {
2201                 DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
2202                 return -EINVAL;
2203         }
2204
2205         return 0;
2206 }
2207
2208 static int dm_sw_init(void *handle)
2209 {
2210         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2211         int r;
2212
2213         r = dm_dmub_sw_init(adev);
2214         if (r)
2215                 return r;
2216
2217         return load_dmcu_fw(adev);
2218 }
2219
2220 static int dm_sw_fini(void *handle)
2221 {
2222         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2223
2224         kfree(adev->dm.dmub_fb_info);
2225         adev->dm.dmub_fb_info = NULL;
2226
2227         if (adev->dm.dmub_srv) {
2228                 dmub_srv_destroy(adev->dm.dmub_srv);
2229                 adev->dm.dmub_srv = NULL;
2230         }
2231
2232         amdgpu_ucode_release(&adev->dm.dmub_fw);
2233         amdgpu_ucode_release(&adev->dm.fw_dmcu);
2234
2235         return 0;
2236 }
2237
2238 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
2239 {
2240         struct amdgpu_dm_connector *aconnector;
2241         struct drm_connector *connector;
2242         struct drm_connector_list_iter iter;
2243         int ret = 0;
2244
2245         drm_connector_list_iter_begin(dev, &iter);
2246         drm_for_each_connector_iter(connector, &iter) {
2247                 aconnector = to_amdgpu_dm_connector(connector);
2248                 if (aconnector->dc_link->type == dc_connection_mst_branch &&
2249                     aconnector->mst_mgr.aux) {
2250                         DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
2251                                          aconnector,
2252                                          aconnector->base.base.id);
2253
2254                         ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
2255                         if (ret < 0) {
2256                                 DRM_ERROR("DM_MST: Failed to start MST\n");
2257                                 aconnector->dc_link->type =
2258                                         dc_connection_single;
2259                                 ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2260                                                                      aconnector->dc_link);
2261                                 break;
2262                         }
2263                 }
2264         }
2265         drm_connector_list_iter_end(&iter);
2266
2267         return ret;
2268 }
2269
2270 static int dm_late_init(void *handle)
2271 {
2272         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2273
2274         struct dmcu_iram_parameters params;
2275         unsigned int linear_lut[16];
2276         int i;
2277         struct dmcu *dmcu = NULL;
2278
2279         dmcu = adev->dm.dc->res_pool->dmcu;
2280
2281         for (i = 0; i < 16; i++)
2282                 linear_lut[i] = 0xFFFF * i / 15;
2283
2284         params.set = 0;
2285         params.backlight_ramping_override = false;
2286         params.backlight_ramping_start = 0xCCCC;
2287         params.backlight_ramping_reduction = 0xCCCCCCCC;
2288         params.backlight_lut_array_size = 16;
2289         params.backlight_lut_array = linear_lut;
2290
2291         /* Min backlight level after ABM reduction,  Don't allow below 1%
2292          * 0xFFFF x 0.01 = 0x28F
2293          */
2294         params.min_abm_backlight = 0x28F;
2295         /* In the case where abm is implemented on dmcub,
2296         * dmcu object will be null.
2297         * ABM 2.4 and up are implemented on dmcub.
2298         */
2299         if (dmcu) {
2300                 if (!dmcu_load_iram(dmcu, params))
2301                         return -EINVAL;
2302         } else if (adev->dm.dc->ctx->dmub_srv) {
2303                 struct dc_link *edp_links[MAX_NUM_EDP];
2304                 int edp_num;
2305
2306                 dc_get_edp_links(adev->dm.dc, edp_links, &edp_num);
2307                 for (i = 0; i < edp_num; i++) {
2308                         if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i))
2309                                 return -EINVAL;
2310                 }
2311         }
2312
2313         return detect_mst_link_for_all_connectors(adev_to_drm(adev));
2314 }
2315
2316 static void s3_handle_mst(struct drm_device *dev, bool suspend)
2317 {
2318         struct amdgpu_dm_connector *aconnector;
2319         struct drm_connector *connector;
2320         struct drm_connector_list_iter iter;
2321         struct drm_dp_mst_topology_mgr *mgr;
2322         int ret;
2323         bool need_hotplug = false;
2324
2325         drm_connector_list_iter_begin(dev, &iter);
2326         drm_for_each_connector_iter(connector, &iter) {
2327                 aconnector = to_amdgpu_dm_connector(connector);
2328                 if (aconnector->dc_link->type != dc_connection_mst_branch ||
2329                     aconnector->mst_root)
2330                         continue;
2331
2332                 mgr = &aconnector->mst_mgr;
2333
2334                 if (suspend) {
2335                         drm_dp_mst_topology_mgr_suspend(mgr);
2336                 } else {
2337                         /* if extended timeout is supported in hardware,
2338                          * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
2339                          * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
2340                          */
2341                         try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
2342                         if (!dp_is_lttpr_present(aconnector->dc_link))
2343                                 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
2344
2345                         ret = drm_dp_mst_topology_mgr_resume(mgr, true);
2346                         if (ret < 0) {
2347                                 dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2348                                         aconnector->dc_link);
2349                                 need_hotplug = true;
2350                         }
2351                 }
2352         }
2353         drm_connector_list_iter_end(&iter);
2354
2355         if (need_hotplug)
2356                 drm_kms_helper_hotplug_event(dev);
2357 }
2358
2359 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
2360 {
2361         int ret = 0;
2362
2363         /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
2364          * on window driver dc implementation.
2365          * For Navi1x, clock settings of dcn watermarks are fixed. the settings
2366          * should be passed to smu during boot up and resume from s3.
2367          * boot up: dc calculate dcn watermark clock settings within dc_create,
2368          * dcn20_resource_construct
2369          * then call pplib functions below to pass the settings to smu:
2370          * smu_set_watermarks_for_clock_ranges
2371          * smu_set_watermarks_table
2372          * navi10_set_watermarks_table
2373          * smu_write_watermarks_table
2374          *
2375          * For Renoir, clock settings of dcn watermark are also fixed values.
2376          * dc has implemented different flow for window driver:
2377          * dc_hardware_init / dc_set_power_state
2378          * dcn10_init_hw
2379          * notify_wm_ranges
2380          * set_wm_ranges
2381          * -- Linux
2382          * smu_set_watermarks_for_clock_ranges
2383          * renoir_set_watermarks_table
2384          * smu_write_watermarks_table
2385          *
2386          * For Linux,
2387          * dc_hardware_init -> amdgpu_dm_init
2388          * dc_set_power_state --> dm_resume
2389          *
2390          * therefore, this function apply to navi10/12/14 but not Renoir
2391          * *
2392          */
2393         switch (adev->ip_versions[DCE_HWIP][0]) {
2394         case IP_VERSION(2, 0, 2):
2395         case IP_VERSION(2, 0, 0):
2396                 break;
2397         default:
2398                 return 0;
2399         }
2400
2401         ret = amdgpu_dpm_write_watermarks_table(adev);
2402         if (ret) {
2403                 DRM_ERROR("Failed to update WMTABLE!\n");
2404                 return ret;
2405         }
2406
2407         return 0;
2408 }
2409
2410 /**
2411  * dm_hw_init() - Initialize DC device
2412  * @handle: The base driver device containing the amdgpu_dm device.
2413  *
2414  * Initialize the &struct amdgpu_display_manager device. This involves calling
2415  * the initializers of each DM component, then populating the struct with them.
2416  *
2417  * Although the function implies hardware initialization, both hardware and
2418  * software are initialized here. Splitting them out to their relevant init
2419  * hooks is a future TODO item.
2420  *
2421  * Some notable things that are initialized here:
2422  *
2423  * - Display Core, both software and hardware
2424  * - DC modules that we need (freesync and color management)
2425  * - DRM software states
2426  * - Interrupt sources and handlers
2427  * - Vblank support
2428  * - Debug FS entries, if enabled
2429  */
2430 static int dm_hw_init(void *handle)
2431 {
2432         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2433         /* Create DAL display manager */
2434         amdgpu_dm_init(adev);
2435         amdgpu_dm_hpd_init(adev);
2436
2437         return 0;
2438 }
2439
2440 /**
2441  * dm_hw_fini() - Teardown DC device
2442  * @handle: The base driver device containing the amdgpu_dm device.
2443  *
2444  * Teardown components within &struct amdgpu_display_manager that require
2445  * cleanup. This involves cleaning up the DRM device, DC, and any modules that
2446  * were loaded. Also flush IRQ workqueues and disable them.
2447  */
2448 static int dm_hw_fini(void *handle)
2449 {
2450         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2451
2452         amdgpu_dm_hpd_fini(adev);
2453
2454         amdgpu_dm_irq_fini(adev);
2455         amdgpu_dm_fini(adev);
2456         return 0;
2457 }
2458
2459
2460 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
2461                                  struct dc_state *state, bool enable)
2462 {
2463         enum dc_irq_source irq_source;
2464         struct amdgpu_crtc *acrtc;
2465         int rc = -EBUSY;
2466         int i = 0;
2467
2468         for (i = 0; i < state->stream_count; i++) {
2469                 acrtc = get_crtc_by_otg_inst(
2470                                 adev, state->stream_status[i].primary_otg_inst);
2471
2472                 if (acrtc && state->stream_status[i].plane_count != 0) {
2473                         irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst;
2474                         rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
2475                         DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n",
2476                                       acrtc->crtc_id, enable ? "en" : "dis", rc);
2477                         if (rc)
2478                                 DRM_WARN("Failed to %s pflip interrupts\n",
2479                                          enable ? "enable" : "disable");
2480
2481                         if (enable) {
2482                                 rc = amdgpu_dm_crtc_enable_vblank(&acrtc->base);
2483                                 if (rc)
2484                                         DRM_WARN("Failed to enable vblank interrupts\n");
2485                         } else {
2486                                 amdgpu_dm_crtc_disable_vblank(&acrtc->base);
2487                         }
2488
2489                 }
2490         }
2491
2492 }
2493
2494 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
2495 {
2496         struct dc_state *context = NULL;
2497         enum dc_status res = DC_ERROR_UNEXPECTED;
2498         int i;
2499         struct dc_stream_state *del_streams[MAX_PIPES];
2500         int del_streams_count = 0;
2501
2502         memset(del_streams, 0, sizeof(del_streams));
2503
2504         context = dc_create_state(dc);
2505         if (context == NULL)
2506                 goto context_alloc_fail;
2507
2508         dc_resource_state_copy_construct_current(dc, context);
2509
2510         /* First remove from context all streams */
2511         for (i = 0; i < context->stream_count; i++) {
2512                 struct dc_stream_state *stream = context->streams[i];
2513
2514                 del_streams[del_streams_count++] = stream;
2515         }
2516
2517         /* Remove all planes for removed streams and then remove the streams */
2518         for (i = 0; i < del_streams_count; i++) {
2519                 if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) {
2520                         res = DC_FAIL_DETACH_SURFACES;
2521                         goto fail;
2522                 }
2523
2524                 res = dc_remove_stream_from_ctx(dc, context, del_streams[i]);
2525                 if (res != DC_OK)
2526                         goto fail;
2527         }
2528
2529         res = dc_commit_streams(dc, context->streams, context->stream_count);
2530
2531 fail:
2532         dc_release_state(context);
2533
2534 context_alloc_fail:
2535         return res;
2536 }
2537
2538 static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm)
2539 {
2540         int i;
2541
2542         if (dm->hpd_rx_offload_wq) {
2543                 for (i = 0; i < dm->dc->caps.max_links; i++)
2544                         flush_workqueue(dm->hpd_rx_offload_wq[i].wq);
2545         }
2546 }
2547
2548 static int dm_suspend(void *handle)
2549 {
2550         struct amdgpu_device *adev = handle;
2551         struct amdgpu_display_manager *dm = &adev->dm;
2552         int ret = 0;
2553
2554         if (amdgpu_in_reset(adev)) {
2555                 mutex_lock(&dm->dc_lock);
2556
2557                 dc_allow_idle_optimizations(adev->dm.dc, false);
2558
2559                 dm->cached_dc_state = dc_copy_state(dm->dc->current_state);
2560
2561                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
2562
2563                 amdgpu_dm_commit_zero_streams(dm->dc);
2564
2565                 amdgpu_dm_irq_suspend(adev);
2566
2567                 hpd_rx_irq_work_suspend(dm);
2568
2569                 return ret;
2570         }
2571
2572         WARN_ON(adev->dm.cached_state);
2573         adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));
2574
2575         s3_handle_mst(adev_to_drm(adev), true);
2576
2577         amdgpu_dm_irq_suspend(adev);
2578
2579         hpd_rx_irq_work_suspend(dm);
2580
2581         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
2582
2583         return 0;
2584 }
2585
2586 struct amdgpu_dm_connector *
2587 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
2588                                              struct drm_crtc *crtc)
2589 {
2590         u32 i;
2591         struct drm_connector_state *new_con_state;
2592         struct drm_connector *connector;
2593         struct drm_crtc *crtc_from_state;
2594
2595         for_each_new_connector_in_state(state, connector, new_con_state, i) {
2596                 crtc_from_state = new_con_state->crtc;
2597
2598                 if (crtc_from_state == crtc)
2599                         return to_amdgpu_dm_connector(connector);
2600         }
2601
2602         return NULL;
2603 }
2604
2605 static void emulated_link_detect(struct dc_link *link)
2606 {
2607         struct dc_sink_init_data sink_init_data = { 0 };
2608         struct display_sink_capability sink_caps = { 0 };
2609         enum dc_edid_status edid_status;
2610         struct dc_context *dc_ctx = link->ctx;
2611         struct dc_sink *sink = NULL;
2612         struct dc_sink *prev_sink = NULL;
2613
2614         link->type = dc_connection_none;
2615         prev_sink = link->local_sink;
2616
2617         if (prev_sink)
2618                 dc_sink_release(prev_sink);
2619
2620         switch (link->connector_signal) {
2621         case SIGNAL_TYPE_HDMI_TYPE_A: {
2622                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2623                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
2624                 break;
2625         }
2626
2627         case SIGNAL_TYPE_DVI_SINGLE_LINK: {
2628                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2629                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
2630                 break;
2631         }
2632
2633         case SIGNAL_TYPE_DVI_DUAL_LINK: {
2634                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2635                 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
2636                 break;
2637         }
2638
2639         case SIGNAL_TYPE_LVDS: {
2640                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2641                 sink_caps.signal = SIGNAL_TYPE_LVDS;
2642                 break;
2643         }
2644
2645         case SIGNAL_TYPE_EDP: {
2646                 sink_caps.transaction_type =
2647                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2648                 sink_caps.signal = SIGNAL_TYPE_EDP;
2649                 break;
2650         }
2651
2652         case SIGNAL_TYPE_DISPLAY_PORT: {
2653                 sink_caps.transaction_type =
2654                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2655                 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
2656                 break;
2657         }
2658
2659         default:
2660                 DC_ERROR("Invalid connector type! signal:%d\n",
2661                         link->connector_signal);
2662                 return;
2663         }
2664
2665         sink_init_data.link = link;
2666         sink_init_data.sink_signal = sink_caps.signal;
2667
2668         sink = dc_sink_create(&sink_init_data);
2669         if (!sink) {
2670                 DC_ERROR("Failed to create sink!\n");
2671                 return;
2672         }
2673
2674         /* dc_sink_create returns a new reference */
2675         link->local_sink = sink;
2676
2677         edid_status = dm_helpers_read_local_edid(
2678                         link->ctx,
2679                         link,
2680                         sink);
2681
2682         if (edid_status != EDID_OK)
2683                 DC_ERROR("Failed to read EDID");
2684
2685 }
2686
2687 static void dm_gpureset_commit_state(struct dc_state *dc_state,
2688                                      struct amdgpu_display_manager *dm)
2689 {
2690         struct {
2691                 struct dc_surface_update surface_updates[MAX_SURFACES];
2692                 struct dc_plane_info plane_infos[MAX_SURFACES];
2693                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
2694                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
2695                 struct dc_stream_update stream_update;
2696         } * bundle;
2697         int k, m;
2698
2699         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
2700
2701         if (!bundle) {
2702                 dm_error("Failed to allocate update bundle\n");
2703                 goto cleanup;
2704         }
2705
2706         for (k = 0; k < dc_state->stream_count; k++) {
2707                 bundle->stream_update.stream = dc_state->streams[k];
2708
2709                 for (m = 0; m < dc_state->stream_status->plane_count; m++) {
2710                         bundle->surface_updates[m].surface =
2711                                 dc_state->stream_status->plane_states[m];
2712                         bundle->surface_updates[m].surface->force_full_update =
2713                                 true;
2714                 }
2715
2716                 update_planes_and_stream_adapter(dm->dc,
2717                                          UPDATE_TYPE_FULL,
2718                                          dc_state->stream_status->plane_count,
2719                                          dc_state->streams[k],
2720                                          &bundle->stream_update,
2721                                          bundle->surface_updates);
2722         }
2723
2724 cleanup:
2725         kfree(bundle);
2726
2727         return;
2728 }
2729
2730 static int dm_resume(void *handle)
2731 {
2732         struct amdgpu_device *adev = handle;
2733         struct drm_device *ddev = adev_to_drm(adev);
2734         struct amdgpu_display_manager *dm = &adev->dm;
2735         struct amdgpu_dm_connector *aconnector;
2736         struct drm_connector *connector;
2737         struct drm_connector_list_iter iter;
2738         struct drm_crtc *crtc;
2739         struct drm_crtc_state *new_crtc_state;
2740         struct dm_crtc_state *dm_new_crtc_state;
2741         struct drm_plane *plane;
2742         struct drm_plane_state *new_plane_state;
2743         struct dm_plane_state *dm_new_plane_state;
2744         struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
2745         enum dc_connection_type new_connection_type = dc_connection_none;
2746         struct dc_state *dc_state;
2747         int i, r, j;
2748
2749         if (amdgpu_in_reset(adev)) {
2750                 dc_state = dm->cached_dc_state;
2751
2752                 /*
2753                  * The dc->current_state is backed up into dm->cached_dc_state
2754                  * before we commit 0 streams.
2755                  *
2756                  * DC will clear link encoder assignments on the real state
2757                  * but the changes won't propagate over to the copy we made
2758                  * before the 0 streams commit.
2759                  *
2760                  * DC expects that link encoder assignments are *not* valid
2761                  * when committing a state, so as a workaround we can copy
2762                  * off of the current state.
2763                  *
2764                  * We lose the previous assignments, but we had already
2765                  * commit 0 streams anyway.
2766                  */
2767                 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state);
2768
2769                 r = dm_dmub_hw_init(adev);
2770                 if (r)
2771                         DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
2772
2773                 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2774                 dc_resume(dm->dc);
2775
2776                 amdgpu_dm_irq_resume_early(adev);
2777
2778                 for (i = 0; i < dc_state->stream_count; i++) {
2779                         dc_state->streams[i]->mode_changed = true;
2780                         for (j = 0; j < dc_state->stream_status[i].plane_count; j++) {
2781                                 dc_state->stream_status[i].plane_states[j]->update_flags.raw
2782                                         = 0xffffffff;
2783                         }
2784                 }
2785
2786                 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2787                         amdgpu_dm_outbox_init(adev);
2788                         dc_enable_dmub_outbox(adev->dm.dc);
2789                 }
2790
2791                 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
2792
2793                 dm_gpureset_commit_state(dm->cached_dc_state, dm);
2794
2795                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true);
2796
2797                 dc_release_state(dm->cached_dc_state);
2798                 dm->cached_dc_state = NULL;
2799
2800                 amdgpu_dm_irq_resume_late(adev);
2801
2802                 mutex_unlock(&dm->dc_lock);
2803
2804                 return 0;
2805         }
2806         /* Recreate dc_state - DC invalidates it when setting power state to S3. */
2807         dc_release_state(dm_state->context);
2808         dm_state->context = dc_create_state(dm->dc);
2809         /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
2810         dc_resource_state_construct(dm->dc, dm_state->context);
2811
2812         /* Before powering on DC we need to re-initialize DMUB. */
2813         dm_dmub_hw_resume(adev);
2814
2815         /* Re-enable outbox interrupts for DPIA. */
2816         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2817                 amdgpu_dm_outbox_init(adev);
2818                 dc_enable_dmub_outbox(adev->dm.dc);
2819         }
2820
2821         /* power on hardware */
2822         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2823
2824         /* program HPD filter */
2825         dc_resume(dm->dc);
2826
2827         /*
2828          * early enable HPD Rx IRQ, should be done before set mode as short
2829          * pulse interrupts are used for MST
2830          */
2831         amdgpu_dm_irq_resume_early(adev);
2832
2833         /* On resume we need to rewrite the MSTM control bits to enable MST*/
2834         s3_handle_mst(ddev, false);
2835
2836         /* Do detection*/
2837         drm_connector_list_iter_begin(ddev, &iter);
2838         drm_for_each_connector_iter(connector, &iter) {
2839                 aconnector = to_amdgpu_dm_connector(connector);
2840
2841                 if (!aconnector->dc_link)
2842                         continue;
2843
2844                 /*
2845                  * this is the case when traversing through already created
2846                  * MST connectors, should be skipped
2847                  */
2848                 if (aconnector->dc_link->type == dc_connection_mst_branch)
2849                         continue;
2850
2851                 mutex_lock(&aconnector->hpd_lock);
2852                 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
2853                         DRM_ERROR("KMS: Failed to detect connector\n");
2854
2855                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2856                         emulated_link_detect(aconnector->dc_link);
2857                 } else {
2858                         mutex_lock(&dm->dc_lock);
2859                         dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
2860                         mutex_unlock(&dm->dc_lock);
2861                 }
2862
2863                 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
2864                         aconnector->fake_enable = false;
2865
2866                 if (aconnector->dc_sink)
2867                         dc_sink_release(aconnector->dc_sink);
2868                 aconnector->dc_sink = NULL;
2869                 amdgpu_dm_update_connector_after_detect(aconnector);
2870                 mutex_unlock(&aconnector->hpd_lock);
2871         }
2872         drm_connector_list_iter_end(&iter);
2873
2874         /* Force mode set in atomic commit */
2875         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
2876                 new_crtc_state->active_changed = true;
2877
2878         /*
2879          * atomic_check is expected to create the dc states. We need to release
2880          * them here, since they were duplicated as part of the suspend
2881          * procedure.
2882          */
2883         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
2884                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
2885                 if (dm_new_crtc_state->stream) {
2886                         WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
2887                         dc_stream_release(dm_new_crtc_state->stream);
2888                         dm_new_crtc_state->stream = NULL;
2889                 }
2890         }
2891
2892         for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
2893                 dm_new_plane_state = to_dm_plane_state(new_plane_state);
2894                 if (dm_new_plane_state->dc_state) {
2895                         WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
2896                         dc_plane_state_release(dm_new_plane_state->dc_state);
2897                         dm_new_plane_state->dc_state = NULL;
2898                 }
2899         }
2900
2901         drm_atomic_helper_resume(ddev, dm->cached_state);
2902
2903         dm->cached_state = NULL;
2904
2905         amdgpu_dm_irq_resume_late(adev);
2906
2907         amdgpu_dm_smu_write_watermarks_table(adev);
2908
2909         return 0;
2910 }
2911
2912 /**
2913  * DOC: DM Lifecycle
2914  *
2915  * DM (and consequently DC) is registered in the amdgpu base driver as a IP
2916  * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
2917  * the base driver's device list to be initialized and torn down accordingly.
2918  *
2919  * The functions to do so are provided as hooks in &struct amd_ip_funcs.
2920  */
2921
2922 static const struct amd_ip_funcs amdgpu_dm_funcs = {
2923         .name = "dm",
2924         .early_init = dm_early_init,
2925         .late_init = dm_late_init,
2926         .sw_init = dm_sw_init,
2927         .sw_fini = dm_sw_fini,
2928         .early_fini = amdgpu_dm_early_fini,
2929         .hw_init = dm_hw_init,
2930         .hw_fini = dm_hw_fini,
2931         .suspend = dm_suspend,
2932         .resume = dm_resume,
2933         .is_idle = dm_is_idle,
2934         .wait_for_idle = dm_wait_for_idle,
2935         .check_soft_reset = dm_check_soft_reset,
2936         .soft_reset = dm_soft_reset,
2937         .set_clockgating_state = dm_set_clockgating_state,
2938         .set_powergating_state = dm_set_powergating_state,
2939 };
2940
2941 const struct amdgpu_ip_block_version dm_ip_block =
2942 {
2943         .type = AMD_IP_BLOCK_TYPE_DCE,
2944         .major = 1,
2945         .minor = 0,
2946         .rev = 0,
2947         .funcs = &amdgpu_dm_funcs,
2948 };
2949
2950
2951 /**
2952  * DOC: atomic
2953  *
2954  * *WIP*
2955  */
2956
2957 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
2958         .fb_create = amdgpu_display_user_framebuffer_create,
2959         .get_format_info = amdgpu_dm_plane_get_format_info,
2960         .atomic_check = amdgpu_dm_atomic_check,
2961         .atomic_commit = drm_atomic_helper_commit,
2962 };
2963
2964 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
2965         .atomic_commit_tail = amdgpu_dm_atomic_commit_tail,
2966         .atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
2967 };
2968
2969 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
2970 {
2971         struct amdgpu_dm_backlight_caps *caps;
2972         struct amdgpu_display_manager *dm;
2973         struct drm_connector *conn_base;
2974         struct amdgpu_device *adev;
2975         struct dc_link *link = NULL;
2976         struct drm_luminance_range_info *luminance_range;
2977         int i;
2978
2979         if (!aconnector || !aconnector->dc_link)
2980                 return;
2981
2982         link = aconnector->dc_link;
2983         if (link->connector_signal != SIGNAL_TYPE_EDP)
2984                 return;
2985
2986         conn_base = &aconnector->base;
2987         adev = drm_to_adev(conn_base->dev);
2988         dm = &adev->dm;
2989         for (i = 0; i < dm->num_of_edps; i++) {
2990                 if (link == dm->backlight_link[i])
2991                         break;
2992         }
2993         if (i >= dm->num_of_edps)
2994                 return;
2995         caps = &dm->backlight_caps[i];
2996         caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
2997         caps->aux_support = false;
2998
2999         if (caps->ext_caps->bits.oled == 1 /*||
3000             caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
3001             caps->ext_caps->bits.hdr_aux_backlight_control == 1*/)
3002                 caps->aux_support = true;
3003
3004         if (amdgpu_backlight == 0)
3005                 caps->aux_support = false;
3006         else if (amdgpu_backlight == 1)
3007                 caps->aux_support = true;
3008
3009         luminance_range = &conn_base->display_info.luminance_range;
3010         caps->aux_min_input_signal = luminance_range->min_luminance;
3011         caps->aux_max_input_signal = luminance_range->max_luminance;
3012 }
3013
3014 void amdgpu_dm_update_connector_after_detect(
3015                 struct amdgpu_dm_connector *aconnector)
3016 {
3017         struct drm_connector *connector = &aconnector->base;
3018         struct drm_device *dev = connector->dev;
3019         struct dc_sink *sink;
3020
3021         /* MST handled by drm_mst framework */
3022         if (aconnector->mst_mgr.mst_state == true)
3023                 return;
3024
3025         sink = aconnector->dc_link->local_sink;
3026         if (sink)
3027                 dc_sink_retain(sink);
3028
3029         /*
3030          * Edid mgmt connector gets first update only in mode_valid hook and then
3031          * the connector sink is set to either fake or physical sink depends on link status.
3032          * Skip if already done during boot.
3033          */
3034         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
3035                         && aconnector->dc_em_sink) {
3036
3037                 /*
3038                  * For S3 resume with headless use eml_sink to fake stream
3039                  * because on resume connector->sink is set to NULL
3040                  */
3041                 mutex_lock(&dev->mode_config.mutex);
3042
3043                 if (sink) {
3044                         if (aconnector->dc_sink) {
3045                                 amdgpu_dm_update_freesync_caps(connector, NULL);
3046                                 /*
3047                                  * retain and release below are used to
3048                                  * bump up refcount for sink because the link doesn't point
3049                                  * to it anymore after disconnect, so on next crtc to connector
3050                                  * reshuffle by UMD we will get into unwanted dc_sink release
3051                                  */
3052                                 dc_sink_release(aconnector->dc_sink);
3053                         }
3054                         aconnector->dc_sink = sink;
3055                         dc_sink_retain(aconnector->dc_sink);
3056                         amdgpu_dm_update_freesync_caps(connector,
3057                                         aconnector->edid);
3058                 } else {
3059                         amdgpu_dm_update_freesync_caps(connector, NULL);
3060                         if (!aconnector->dc_sink) {
3061                                 aconnector->dc_sink = aconnector->dc_em_sink;
3062                                 dc_sink_retain(aconnector->dc_sink);
3063                         }
3064                 }
3065
3066                 mutex_unlock(&dev->mode_config.mutex);
3067
3068                 if (sink)
3069                         dc_sink_release(sink);
3070                 return;
3071         }
3072
3073         /*
3074          * TODO: temporary guard to look for proper fix
3075          * if this sink is MST sink, we should not do anything
3076          */
3077         if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3078                 dc_sink_release(sink);
3079                 return;
3080         }
3081
3082         if (aconnector->dc_sink == sink) {
3083                 /*
3084                  * We got a DP short pulse (Link Loss, DP CTS, etc...).
3085                  * Do nothing!!
3086                  */
3087                 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
3088                                 aconnector->connector_id);
3089                 if (sink)
3090                         dc_sink_release(sink);
3091                 return;
3092         }
3093
3094         DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
3095                 aconnector->connector_id, aconnector->dc_sink, sink);
3096
3097         mutex_lock(&dev->mode_config.mutex);
3098
3099         /*
3100          * 1. Update status of the drm connector
3101          * 2. Send an event and let userspace tell us what to do
3102          */
3103         if (sink) {
3104                 /*
3105                  * TODO: check if we still need the S3 mode update workaround.
3106                  * If yes, put it here.
3107                  */
3108                 if (aconnector->dc_sink) {
3109                         amdgpu_dm_update_freesync_caps(connector, NULL);
3110                         dc_sink_release(aconnector->dc_sink);
3111                 }
3112
3113                 aconnector->dc_sink = sink;
3114                 dc_sink_retain(aconnector->dc_sink);
3115                 if (sink->dc_edid.length == 0) {
3116                         aconnector->edid = NULL;
3117                         if (aconnector->dc_link->aux_mode) {
3118                                 drm_dp_cec_unset_edid(
3119                                         &aconnector->dm_dp_aux.aux);
3120                         }
3121                 } else {
3122                         aconnector->edid =
3123                                 (struct edid *)sink->dc_edid.raw_edid;
3124
3125                         if (aconnector->dc_link->aux_mode)
3126                                 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
3127                                                     aconnector->edid);
3128                 }
3129
3130                 aconnector->timing_requested = kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL);
3131                 if (!aconnector->timing_requested)
3132                         dm_error("%s: failed to create aconnector->requested_timing\n", __func__);
3133
3134                 drm_connector_update_edid_property(connector, aconnector->edid);
3135                 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
3136                 update_connector_ext_caps(aconnector);
3137         } else {
3138                 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
3139                 amdgpu_dm_update_freesync_caps(connector, NULL);
3140                 drm_connector_update_edid_property(connector, NULL);
3141                 aconnector->num_modes = 0;
3142                 dc_sink_release(aconnector->dc_sink);
3143                 aconnector->dc_sink = NULL;
3144                 aconnector->edid = NULL;
3145                 kfree(aconnector->timing_requested);
3146                 aconnector->timing_requested = NULL;
3147                 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
3148                 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
3149                         connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
3150         }
3151
3152         mutex_unlock(&dev->mode_config.mutex);
3153
3154         update_subconnector_property(aconnector);
3155
3156         if (sink)
3157                 dc_sink_release(sink);
3158 }
3159
3160 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)
3161 {
3162         struct drm_connector *connector = &aconnector->base;
3163         struct drm_device *dev = connector->dev;
3164         enum dc_connection_type new_connection_type = dc_connection_none;
3165         struct amdgpu_device *adev = drm_to_adev(dev);
3166         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
3167         bool ret = false;
3168
3169         if (adev->dm.disable_hpd_irq)
3170                 return;
3171
3172         /*
3173          * In case of failure or MST no need to update connector status or notify the OS
3174          * since (for MST case) MST does this in its own context.
3175          */
3176         mutex_lock(&aconnector->hpd_lock);
3177
3178         if (adev->dm.hdcp_workqueue) {
3179                 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
3180                 dm_con_state->update_hdcp = true;
3181         }
3182         if (aconnector->fake_enable)
3183                 aconnector->fake_enable = false;
3184
3185         aconnector->timing_changed = false;
3186
3187         if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
3188                 DRM_ERROR("KMS: Failed to detect connector\n");
3189
3190         if (aconnector->base.force && new_connection_type == dc_connection_none) {
3191                 emulated_link_detect(aconnector->dc_link);
3192
3193                 drm_modeset_lock_all(dev);
3194                 dm_restore_drm_connector_state(dev, connector);
3195                 drm_modeset_unlock_all(dev);
3196
3197                 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3198                         drm_kms_helper_connector_hotplug_event(connector);
3199         } else {
3200                 mutex_lock(&adev->dm.dc_lock);
3201                 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3202                 mutex_unlock(&adev->dm.dc_lock);
3203                 if (ret) {
3204                         amdgpu_dm_update_connector_after_detect(aconnector);
3205
3206                         drm_modeset_lock_all(dev);
3207                         dm_restore_drm_connector_state(dev, connector);
3208                         drm_modeset_unlock_all(dev);
3209
3210                         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3211                                 drm_kms_helper_connector_hotplug_event(connector);
3212                 }
3213         }
3214         mutex_unlock(&aconnector->hpd_lock);
3215
3216 }
3217
3218 static void handle_hpd_irq(void *param)
3219 {
3220         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3221
3222         handle_hpd_irq_helper(aconnector);
3223
3224 }
3225
3226 static void dm_handle_mst_sideband_msg(struct amdgpu_dm_connector *aconnector)
3227 {
3228         u8 esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
3229         u8 dret;
3230         bool new_irq_handled = false;
3231         int dpcd_addr;
3232         int dpcd_bytes_to_read;
3233
3234         const int max_process_count = 30;
3235         int process_count = 0;
3236
3237         const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
3238
3239         if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
3240                 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
3241                 /* DPCD 0x200 - 0x201 for downstream IRQ */
3242                 dpcd_addr = DP_SINK_COUNT;
3243         } else {
3244                 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
3245                 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
3246                 dpcd_addr = DP_SINK_COUNT_ESI;
3247         }
3248
3249         dret = drm_dp_dpcd_read(
3250                 &aconnector->dm_dp_aux.aux,
3251                 dpcd_addr,
3252                 esi,
3253                 dpcd_bytes_to_read);
3254
3255         while (dret == dpcd_bytes_to_read &&
3256                 process_count < max_process_count) {
3257                 u8 retry;
3258                 dret = 0;
3259
3260                 process_count++;
3261
3262                 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3263                 /* handle HPD short pulse irq */
3264                 if (aconnector->mst_mgr.mst_state)
3265                         drm_dp_mst_hpd_irq(
3266                                 &aconnector->mst_mgr,
3267                                 esi,
3268                                 &new_irq_handled);
3269
3270                 if (new_irq_handled) {
3271                         /* ACK at DPCD to notify down stream */
3272                         const int ack_dpcd_bytes_to_write =
3273                                 dpcd_bytes_to_read - 1;
3274
3275                         for (retry = 0; retry < 3; retry++) {
3276                                 u8 wret;
3277
3278                                 wret = drm_dp_dpcd_write(
3279                                         &aconnector->dm_dp_aux.aux,
3280                                         dpcd_addr + 1,
3281                                         &esi[1],
3282                                         ack_dpcd_bytes_to_write);
3283                                 if (wret == ack_dpcd_bytes_to_write)
3284                                         break;
3285                         }
3286
3287                         /* check if there is new irq to be handled */
3288                         dret = drm_dp_dpcd_read(
3289                                 &aconnector->dm_dp_aux.aux,
3290                                 dpcd_addr,
3291                                 esi,
3292                                 dpcd_bytes_to_read);
3293
3294                         new_irq_handled = false;
3295                 } else {
3296                         break;
3297                 }
3298         }
3299
3300         if (process_count == max_process_count)
3301                 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
3302 }
3303
3304 static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq,
3305                                                         union hpd_irq_data hpd_irq_data)
3306 {
3307         struct hpd_rx_irq_offload_work *offload_work =
3308                                 kzalloc(sizeof(*offload_work), GFP_KERNEL);
3309
3310         if (!offload_work) {
3311                 DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n");
3312                 return;
3313         }
3314
3315         INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work);
3316         offload_work->data = hpd_irq_data;
3317         offload_work->offload_wq = offload_wq;
3318
3319         queue_work(offload_wq->wq, &offload_work->work);
3320         DRM_DEBUG_KMS("queue work to handle hpd_rx offload work");
3321 }
3322
3323 static void handle_hpd_rx_irq(void *param)
3324 {
3325         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3326         struct drm_connector *connector = &aconnector->base;
3327         struct drm_device *dev = connector->dev;
3328         struct dc_link *dc_link = aconnector->dc_link;
3329         bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
3330         bool result = false;
3331         enum dc_connection_type new_connection_type = dc_connection_none;
3332         struct amdgpu_device *adev = drm_to_adev(dev);
3333         union hpd_irq_data hpd_irq_data;
3334         bool link_loss = false;
3335         bool has_left_work = false;
3336         int idx = dc_link->link_index;
3337         struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx];
3338
3339         memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
3340
3341         if (adev->dm.disable_hpd_irq)
3342                 return;
3343
3344         /*
3345          * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
3346          * conflict, after implement i2c helper, this mutex should be
3347          * retired.
3348          */
3349         mutex_lock(&aconnector->hpd_lock);
3350
3351         result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data,
3352                                                 &link_loss, true, &has_left_work);
3353
3354         if (!has_left_work)
3355                 goto out;
3356
3357         if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3358                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3359                 goto out;
3360         }
3361
3362         if (dc_link_dp_allow_hpd_rx_irq(dc_link)) {
3363                 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
3364                         hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
3365                         dm_handle_mst_sideband_msg(aconnector);
3366                         goto out;
3367                 }
3368
3369                 if (link_loss) {
3370                         bool skip = false;
3371
3372                         spin_lock(&offload_wq->offload_lock);
3373                         skip = offload_wq->is_handling_link_loss;
3374
3375                         if (!skip)
3376                                 offload_wq->is_handling_link_loss = true;
3377
3378                         spin_unlock(&offload_wq->offload_lock);
3379
3380                         if (!skip)
3381                                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3382
3383                         goto out;
3384                 }
3385         }
3386
3387 out:
3388         if (result && !is_mst_root_connector) {
3389                 /* Downstream Port status changed. */
3390                 if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
3391                         DRM_ERROR("KMS: Failed to detect connector\n");
3392
3393                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3394                         emulated_link_detect(dc_link);
3395
3396                         if (aconnector->fake_enable)
3397                                 aconnector->fake_enable = false;
3398
3399                         amdgpu_dm_update_connector_after_detect(aconnector);
3400
3401
3402                         drm_modeset_lock_all(dev);
3403                         dm_restore_drm_connector_state(dev, connector);
3404                         drm_modeset_unlock_all(dev);
3405
3406                         drm_kms_helper_connector_hotplug_event(connector);
3407                 } else {
3408                         bool ret = false;
3409
3410                         mutex_lock(&adev->dm.dc_lock);
3411                         ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX);
3412                         mutex_unlock(&adev->dm.dc_lock);
3413
3414                         if (ret) {
3415                                 if (aconnector->fake_enable)
3416                                         aconnector->fake_enable = false;
3417
3418                                 amdgpu_dm_update_connector_after_detect(aconnector);
3419
3420                                 drm_modeset_lock_all(dev);
3421                                 dm_restore_drm_connector_state(dev, connector);
3422                                 drm_modeset_unlock_all(dev);
3423
3424                                 drm_kms_helper_connector_hotplug_event(connector);
3425                         }
3426                 }
3427         }
3428         if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
3429                 if (adev->dm.hdcp_workqueue)
3430                         hdcp_handle_cpirq(adev->dm.hdcp_workqueue,  aconnector->base.index);
3431         }
3432
3433         if (dc_link->type != dc_connection_mst_branch)
3434                 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
3435
3436         mutex_unlock(&aconnector->hpd_lock);
3437 }
3438
3439 static void register_hpd_handlers(struct amdgpu_device *adev)
3440 {
3441         struct drm_device *dev = adev_to_drm(adev);
3442         struct drm_connector *connector;
3443         struct amdgpu_dm_connector *aconnector;
3444         const struct dc_link *dc_link;
3445         struct dc_interrupt_params int_params = {0};
3446
3447         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3448         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3449
3450         list_for_each_entry(connector,
3451                         &dev->mode_config.connector_list, head) {
3452
3453                 aconnector = to_amdgpu_dm_connector(connector);
3454                 dc_link = aconnector->dc_link;
3455
3456                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
3457                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3458                         int_params.irq_source = dc_link->irq_source_hpd;
3459
3460                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
3461                                         handle_hpd_irq,
3462                                         (void *) aconnector);
3463                 }
3464
3465                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
3466
3467                         /* Also register for DP short pulse (hpd_rx). */
3468                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3469                         int_params.irq_source = dc_link->irq_source_hpd_rx;
3470
3471                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
3472                                         handle_hpd_rx_irq,
3473                                         (void *) aconnector);
3474
3475                         if (adev->dm.hpd_rx_offload_wq)
3476                                 adev->dm.hpd_rx_offload_wq[dc_link->link_index].aconnector =
3477                                         aconnector;
3478                 }
3479         }
3480 }
3481
3482 #if defined(CONFIG_DRM_AMD_DC_SI)
3483 /* Register IRQ sources and initialize IRQ callbacks */
3484 static int dce60_register_irq_handlers(struct amdgpu_device *adev)
3485 {
3486         struct dc *dc = adev->dm.dc;
3487         struct common_irq_params *c_irq_params;
3488         struct dc_interrupt_params int_params = {0};
3489         int r;
3490         int i;
3491         unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3492
3493         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3494         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3495
3496         /*
3497          * Actions of amdgpu_irq_add_id():
3498          * 1. Register a set() function with base driver.
3499          *    Base driver will call set() function to enable/disable an
3500          *    interrupt in DC hardware.
3501          * 2. Register amdgpu_dm_irq_handler().
3502          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3503          *    coming from DC hardware.
3504          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3505          *    for acknowledging and handling. */
3506
3507         /* Use VBLANK interrupt */
3508         for (i = 0; i < adev->mode_info.num_crtc; i++) {
3509                 r = amdgpu_irq_add_id(adev, client_id, i+1 , &adev->crtc_irq);
3510                 if (r) {
3511                         DRM_ERROR("Failed to add crtc irq id!\n");
3512                         return r;
3513                 }
3514
3515                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3516                 int_params.irq_source =
3517                         dc_interrupt_to_irq_source(dc, i+1 , 0);
3518
3519                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3520
3521                 c_irq_params->adev = adev;
3522                 c_irq_params->irq_src = int_params.irq_source;
3523
3524                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3525                                 dm_crtc_high_irq, c_irq_params);
3526         }
3527
3528         /* Use GRPH_PFLIP interrupt */
3529         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3530                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3531                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3532                 if (r) {
3533                         DRM_ERROR("Failed to add page flip irq id!\n");
3534                         return r;
3535                 }
3536
3537                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3538                 int_params.irq_source =
3539                         dc_interrupt_to_irq_source(dc, i, 0);
3540
3541                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3542
3543                 c_irq_params->adev = adev;
3544                 c_irq_params->irq_src = int_params.irq_source;
3545
3546                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3547                                 dm_pflip_high_irq, c_irq_params);
3548
3549         }
3550
3551         /* HPD */
3552         r = amdgpu_irq_add_id(adev, client_id,
3553                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3554         if (r) {
3555                 DRM_ERROR("Failed to add hpd irq id!\n");
3556                 return r;
3557         }
3558
3559         register_hpd_handlers(adev);
3560
3561         return 0;
3562 }
3563 #endif
3564
3565 /* Register IRQ sources and initialize IRQ callbacks */
3566 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
3567 {
3568         struct dc *dc = adev->dm.dc;
3569         struct common_irq_params *c_irq_params;
3570         struct dc_interrupt_params int_params = {0};
3571         int r;
3572         int i;
3573         unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3574
3575         if (adev->family >= AMDGPU_FAMILY_AI)
3576                 client_id = SOC15_IH_CLIENTID_DCE;
3577
3578         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3579         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3580
3581         /*
3582          * Actions of amdgpu_irq_add_id():
3583          * 1. Register a set() function with base driver.
3584          *    Base driver will call set() function to enable/disable an
3585          *    interrupt in DC hardware.
3586          * 2. Register amdgpu_dm_irq_handler().
3587          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3588          *    coming from DC hardware.
3589          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3590          *    for acknowledging and handling. */
3591
3592         /* Use VBLANK interrupt */
3593         for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
3594                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
3595                 if (r) {
3596                         DRM_ERROR("Failed to add crtc irq id!\n");
3597                         return r;
3598                 }
3599
3600                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3601                 int_params.irq_source =
3602                         dc_interrupt_to_irq_source(dc, i, 0);
3603
3604                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3605
3606                 c_irq_params->adev = adev;
3607                 c_irq_params->irq_src = int_params.irq_source;
3608
3609                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3610                                 dm_crtc_high_irq, c_irq_params);
3611         }
3612
3613         /* Use VUPDATE interrupt */
3614         for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
3615                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
3616                 if (r) {
3617                         DRM_ERROR("Failed to add vupdate irq id!\n");
3618                         return r;
3619                 }
3620
3621                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3622                 int_params.irq_source =
3623                         dc_interrupt_to_irq_source(dc, i, 0);
3624
3625                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3626
3627                 c_irq_params->adev = adev;
3628                 c_irq_params->irq_src = int_params.irq_source;
3629
3630                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3631                                 dm_vupdate_high_irq, c_irq_params);
3632         }
3633
3634         /* Use GRPH_PFLIP interrupt */
3635         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3636                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3637                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3638                 if (r) {
3639                         DRM_ERROR("Failed to add page flip irq id!\n");
3640                         return r;
3641                 }
3642
3643                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3644                 int_params.irq_source =
3645                         dc_interrupt_to_irq_source(dc, i, 0);
3646
3647                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3648
3649                 c_irq_params->adev = adev;
3650                 c_irq_params->irq_src = int_params.irq_source;
3651
3652                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3653                                 dm_pflip_high_irq, c_irq_params);
3654
3655         }
3656
3657         /* HPD */
3658         r = amdgpu_irq_add_id(adev, client_id,
3659                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3660         if (r) {
3661                 DRM_ERROR("Failed to add hpd irq id!\n");
3662                 return r;
3663         }
3664
3665         register_hpd_handlers(adev);
3666
3667         return 0;
3668 }
3669
3670 /* Register IRQ sources and initialize IRQ callbacks */
3671 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
3672 {
3673         struct dc *dc = adev->dm.dc;
3674         struct common_irq_params *c_irq_params;
3675         struct dc_interrupt_params int_params = {0};
3676         int r;
3677         int i;
3678 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3679         static const unsigned int vrtl_int_srcid[] = {
3680                 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL,
3681                 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL,
3682                 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL,
3683                 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL,
3684                 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL,
3685                 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL
3686         };
3687 #endif
3688
3689         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3690         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3691
3692         /*
3693          * Actions of amdgpu_irq_add_id():
3694          * 1. Register a set() function with base driver.
3695          *    Base driver will call set() function to enable/disable an
3696          *    interrupt in DC hardware.
3697          * 2. Register amdgpu_dm_irq_handler().
3698          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3699          *    coming from DC hardware.
3700          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3701          *    for acknowledging and handling.
3702          */
3703
3704         /* Use VSTARTUP interrupt */
3705         for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
3706                         i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
3707                         i++) {
3708                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
3709
3710                 if (r) {
3711                         DRM_ERROR("Failed to add crtc irq id!\n");
3712                         return r;
3713                 }
3714
3715                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3716                 int_params.irq_source =
3717                         dc_interrupt_to_irq_source(dc, i, 0);
3718
3719                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3720
3721                 c_irq_params->adev = adev;
3722                 c_irq_params->irq_src = int_params.irq_source;
3723
3724                 amdgpu_dm_irq_register_interrupt(
3725                         adev, &int_params, dm_crtc_high_irq, c_irq_params);
3726         }
3727
3728         /* Use otg vertical line interrupt */
3729 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3730         for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) {
3731                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE,
3732                                 vrtl_int_srcid[i], &adev->vline0_irq);
3733
3734                 if (r) {
3735                         DRM_ERROR("Failed to add vline0 irq id!\n");
3736                         return r;
3737                 }
3738
3739                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3740                 int_params.irq_source =
3741                         dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0);
3742
3743                 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) {
3744                         DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]);
3745                         break;
3746                 }
3747
3748                 c_irq_params = &adev->dm.vline0_params[int_params.irq_source
3749                                         - DC_IRQ_SOURCE_DC1_VLINE0];
3750
3751                 c_irq_params->adev = adev;
3752                 c_irq_params->irq_src = int_params.irq_source;
3753
3754                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3755                                 dm_dcn_vertical_interrupt0_high_irq, c_irq_params);
3756         }
3757 #endif
3758
3759         /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
3760          * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
3761          * to trigger at end of each vblank, regardless of state of the lock,
3762          * matching DCE behaviour.
3763          */
3764         for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
3765              i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
3766              i++) {
3767                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
3768
3769                 if (r) {
3770                         DRM_ERROR("Failed to add vupdate irq id!\n");
3771                         return r;
3772                 }
3773
3774                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3775                 int_params.irq_source =
3776                         dc_interrupt_to_irq_source(dc, i, 0);
3777
3778                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3779
3780                 c_irq_params->adev = adev;
3781                 c_irq_params->irq_src = int_params.irq_source;
3782
3783                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3784                                 dm_vupdate_high_irq, c_irq_params);
3785         }
3786
3787         /* Use GRPH_PFLIP interrupt */
3788         for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
3789                         i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1;
3790                         i++) {
3791                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
3792                 if (r) {
3793                         DRM_ERROR("Failed to add page flip irq id!\n");
3794                         return r;
3795                 }
3796
3797                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3798                 int_params.irq_source =
3799                         dc_interrupt_to_irq_source(dc, i, 0);
3800
3801                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3802
3803                 c_irq_params->adev = adev;
3804                 c_irq_params->irq_src = int_params.irq_source;
3805
3806                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3807                                 dm_pflip_high_irq, c_irq_params);
3808
3809         }
3810
3811         /* HPD */
3812         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
3813                         &adev->hpd_irq);
3814         if (r) {
3815                 DRM_ERROR("Failed to add hpd irq id!\n");
3816                 return r;
3817         }
3818
3819         register_hpd_handlers(adev);
3820
3821         return 0;
3822 }
3823 /* Register Outbox IRQ sources and initialize IRQ callbacks */
3824 static int register_outbox_irq_handlers(struct amdgpu_device *adev)
3825 {
3826         struct dc *dc = adev->dm.dc;
3827         struct common_irq_params *c_irq_params;
3828         struct dc_interrupt_params int_params = {0};
3829         int r, i;
3830
3831         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3832         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3833
3834         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT,
3835                         &adev->dmub_outbox_irq);
3836         if (r) {
3837                 DRM_ERROR("Failed to add outbox irq id!\n");
3838                 return r;
3839         }
3840
3841         if (dc->ctx->dmub_srv) {
3842                 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT;
3843                 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3844                 int_params.irq_source =
3845                 dc_interrupt_to_irq_source(dc, i, 0);
3846
3847                 c_irq_params = &adev->dm.dmub_outbox_params[0];
3848
3849                 c_irq_params->adev = adev;
3850                 c_irq_params->irq_src = int_params.irq_source;
3851
3852                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3853                                 dm_dmub_outbox1_low_irq, c_irq_params);
3854         }
3855
3856         return 0;
3857 }
3858
3859 /*
3860  * Acquires the lock for the atomic state object and returns
3861  * the new atomic state.
3862  *
3863  * This should only be called during atomic check.
3864  */
3865 int dm_atomic_get_state(struct drm_atomic_state *state,
3866                         struct dm_atomic_state **dm_state)
3867 {
3868         struct drm_device *dev = state->dev;
3869         struct amdgpu_device *adev = drm_to_adev(dev);
3870         struct amdgpu_display_manager *dm = &adev->dm;
3871         struct drm_private_state *priv_state;
3872
3873         if (*dm_state)
3874                 return 0;
3875
3876         priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
3877         if (IS_ERR(priv_state))
3878                 return PTR_ERR(priv_state);
3879
3880         *dm_state = to_dm_atomic_state(priv_state);
3881
3882         return 0;
3883 }
3884
3885 static struct dm_atomic_state *
3886 dm_atomic_get_new_state(struct drm_atomic_state *state)
3887 {
3888         struct drm_device *dev = state->dev;
3889         struct amdgpu_device *adev = drm_to_adev(dev);
3890         struct amdgpu_display_manager *dm = &adev->dm;
3891         struct drm_private_obj *obj;
3892         struct drm_private_state *new_obj_state;
3893         int i;
3894
3895         for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
3896                 if (obj->funcs == dm->atomic_obj.funcs)
3897                         return to_dm_atomic_state(new_obj_state);
3898         }
3899
3900         return NULL;
3901 }
3902
3903 static struct drm_private_state *
3904 dm_atomic_duplicate_state(struct drm_private_obj *obj)
3905 {
3906         struct dm_atomic_state *old_state, *new_state;
3907
3908         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
3909         if (!new_state)
3910                 return NULL;
3911
3912         __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
3913
3914         old_state = to_dm_atomic_state(obj->state);
3915
3916         if (old_state && old_state->context)
3917                 new_state->context = dc_copy_state(old_state->context);
3918
3919         if (!new_state->context) {
3920                 kfree(new_state);
3921                 return NULL;
3922         }
3923
3924         return &new_state->base;
3925 }
3926
3927 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
3928                                     struct drm_private_state *state)
3929 {
3930         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
3931
3932         if (dm_state && dm_state->context)
3933                 dc_release_state(dm_state->context);
3934
3935         kfree(dm_state);
3936 }
3937
3938 static struct drm_private_state_funcs dm_atomic_state_funcs = {
3939         .atomic_duplicate_state = dm_atomic_duplicate_state,
3940         .atomic_destroy_state = dm_atomic_destroy_state,
3941 };
3942
3943 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
3944 {
3945         struct dm_atomic_state *state;
3946         int r;
3947
3948         adev->mode_info.mode_config_initialized = true;
3949
3950         adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
3951         adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
3952
3953         adev_to_drm(adev)->mode_config.max_width = 16384;
3954         adev_to_drm(adev)->mode_config.max_height = 16384;
3955
3956         adev_to_drm(adev)->mode_config.preferred_depth = 24;
3957         if (adev->asic_type == CHIP_HAWAII)
3958                 /* disable prefer shadow for now due to hibernation issues */
3959                 adev_to_drm(adev)->mode_config.prefer_shadow = 0;
3960         else
3961                 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
3962         /* indicates support for immediate flip */
3963         adev_to_drm(adev)->mode_config.async_page_flip = true;
3964
3965         state = kzalloc(sizeof(*state), GFP_KERNEL);
3966         if (!state)
3967                 return -ENOMEM;
3968
3969         state->context = dc_create_state(adev->dm.dc);
3970         if (!state->context) {
3971                 kfree(state);
3972                 return -ENOMEM;
3973         }
3974
3975         dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
3976
3977         drm_atomic_private_obj_init(adev_to_drm(adev),
3978                                     &adev->dm.atomic_obj,
3979                                     &state->base,
3980                                     &dm_atomic_state_funcs);
3981
3982         r = amdgpu_display_modeset_create_props(adev);
3983         if (r) {
3984                 dc_release_state(state->context);
3985                 kfree(state);
3986                 return r;
3987         }
3988
3989         r = amdgpu_dm_audio_init(adev);
3990         if (r) {
3991                 dc_release_state(state->context);
3992                 kfree(state);
3993                 return r;
3994         }
3995
3996         return 0;
3997 }
3998
3999 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
4000 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
4001 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
4002
4003 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
4004                                             int bl_idx)
4005 {
4006 #if defined(CONFIG_ACPI)
4007         struct amdgpu_dm_backlight_caps caps;
4008
4009         memset(&caps, 0, sizeof(caps));
4010
4011         if (dm->backlight_caps[bl_idx].caps_valid)
4012                 return;
4013
4014         amdgpu_acpi_get_backlight_caps(&caps);
4015         if (caps.caps_valid) {
4016                 dm->backlight_caps[bl_idx].caps_valid = true;
4017                 if (caps.aux_support)
4018                         return;
4019                 dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal;
4020                 dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal;
4021         } else {
4022                 dm->backlight_caps[bl_idx].min_input_signal =
4023                                 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4024                 dm->backlight_caps[bl_idx].max_input_signal =
4025                                 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4026         }
4027 #else
4028         if (dm->backlight_caps[bl_idx].aux_support)
4029                 return;
4030
4031         dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4032         dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4033 #endif
4034 }
4035
4036 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
4037                                 unsigned *min, unsigned *max)
4038 {
4039         if (!caps)
4040                 return 0;
4041
4042         if (caps->aux_support) {
4043                 // Firmware limits are in nits, DC API wants millinits.
4044                 *max = 1000 * caps->aux_max_input_signal;
4045                 *min = 1000 * caps->aux_min_input_signal;
4046         } else {
4047                 // Firmware limits are 8-bit, PWM control is 16-bit.
4048                 *max = 0x101 * caps->max_input_signal;
4049                 *min = 0x101 * caps->min_input_signal;
4050         }
4051         return 1;
4052 }
4053
4054 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
4055                                         uint32_t brightness)
4056 {
4057         unsigned min, max;
4058
4059         if (!get_brightness_range(caps, &min, &max))
4060                 return brightness;
4061
4062         // Rescale 0..255 to min..max
4063         return min + DIV_ROUND_CLOSEST((max - min) * brightness,
4064                                        AMDGPU_MAX_BL_LEVEL);
4065 }
4066
4067 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
4068                                       uint32_t brightness)
4069 {
4070         unsigned min, max;
4071
4072         if (!get_brightness_range(caps, &min, &max))
4073                 return brightness;
4074
4075         if (brightness < min)
4076                 return 0;
4077         // Rescale min..max to 0..255
4078         return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),
4079                                  max - min);
4080 }
4081
4082 static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
4083                                          int bl_idx,
4084                                          u32 user_brightness)
4085 {
4086         struct amdgpu_dm_backlight_caps caps;
4087         struct dc_link *link;
4088         u32 brightness;
4089         bool rc;
4090
4091         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4092         caps = dm->backlight_caps[bl_idx];
4093
4094         dm->brightness[bl_idx] = user_brightness;
4095         /* update scratch register */
4096         if (bl_idx == 0)
4097                 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]);
4098         brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]);
4099         link = (struct dc_link *)dm->backlight_link[bl_idx];
4100
4101         /* Change brightness based on AUX property */
4102         if (caps.aux_support) {
4103                 rc = dc_link_set_backlight_level_nits(link, true, brightness,
4104                                                       AUX_BL_DEFAULT_TRANSITION_TIME_MS);
4105                 if (!rc)
4106                         DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx);
4107         } else {
4108                 rc = dc_link_set_backlight_level(link, brightness, 0);
4109                 if (!rc)
4110                         DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx);
4111         }
4112
4113         if (rc)
4114                 dm->actual_brightness[bl_idx] = user_brightness;
4115 }
4116
4117 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
4118 {
4119         struct amdgpu_display_manager *dm = bl_get_data(bd);
4120         int i;
4121
4122         for (i = 0; i < dm->num_of_edps; i++) {
4123                 if (bd == dm->backlight_dev[i])
4124                         break;
4125         }
4126         if (i >= AMDGPU_DM_MAX_NUM_EDP)
4127                 i = 0;
4128         amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness);
4129
4130         return 0;
4131 }
4132
4133 static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm,
4134                                          int bl_idx)
4135 {
4136         struct amdgpu_dm_backlight_caps caps;
4137         struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx];
4138
4139         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4140         caps = dm->backlight_caps[bl_idx];
4141
4142         if (caps.aux_support) {
4143                 u32 avg, peak;
4144                 bool rc;
4145
4146                 rc = dc_link_get_backlight_level_nits(link, &avg, &peak);
4147                 if (!rc)
4148                         return dm->brightness[bl_idx];
4149                 return convert_brightness_to_user(&caps, avg);
4150         } else {
4151                 int ret = dc_link_get_backlight_level(link);
4152
4153                 if (ret == DC_ERROR_UNEXPECTED)
4154                         return dm->brightness[bl_idx];
4155                 return convert_brightness_to_user(&caps, ret);
4156         }
4157 }
4158
4159 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
4160 {
4161         struct amdgpu_display_manager *dm = bl_get_data(bd);
4162         int i;
4163
4164         for (i = 0; i < dm->num_of_edps; i++) {
4165                 if (bd == dm->backlight_dev[i])
4166                         break;
4167         }
4168         if (i >= AMDGPU_DM_MAX_NUM_EDP)
4169                 i = 0;
4170         return amdgpu_dm_backlight_get_level(dm, i);
4171 }
4172
4173 static const struct backlight_ops amdgpu_dm_backlight_ops = {
4174         .options = BL_CORE_SUSPENDRESUME,
4175         .get_brightness = amdgpu_dm_backlight_get_brightness,
4176         .update_status  = amdgpu_dm_backlight_update_status,
4177 };
4178
4179 static void
4180 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
4181 {
4182         char bl_name[16];
4183         struct backlight_properties props = { 0 };
4184
4185         amdgpu_dm_update_backlight_caps(dm, dm->num_of_edps);
4186         dm->brightness[dm->num_of_edps] = AMDGPU_MAX_BL_LEVEL;
4187
4188         if (!acpi_video_backlight_use_native()) {
4189                 drm_info(adev_to_drm(dm->adev), "Skipping amdgpu DM backlight registration\n");
4190                 /* Try registering an ACPI video backlight device instead. */
4191                 acpi_video_register_backlight();
4192                 return;
4193         }
4194
4195         props.max_brightness = AMDGPU_MAX_BL_LEVEL;
4196         props.brightness = AMDGPU_MAX_BL_LEVEL;
4197         props.type = BACKLIGHT_RAW;
4198
4199         snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
4200                  adev_to_drm(dm->adev)->primary->index + dm->num_of_edps);
4201
4202         dm->backlight_dev[dm->num_of_edps] = backlight_device_register(bl_name,
4203                                                                        adev_to_drm(dm->adev)->dev,
4204                                                                        dm,
4205                                                                        &amdgpu_dm_backlight_ops,
4206                                                                        &props);
4207
4208         if (IS_ERR(dm->backlight_dev[dm->num_of_edps]))
4209                 DRM_ERROR("DM: Backlight registration failed!\n");
4210         else
4211                 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4212 }
4213
4214 static int initialize_plane(struct amdgpu_display_manager *dm,
4215                             struct amdgpu_mode_info *mode_info, int plane_id,
4216                             enum drm_plane_type plane_type,
4217                             const struct dc_plane_cap *plane_cap)
4218 {
4219         struct drm_plane *plane;
4220         unsigned long possible_crtcs;
4221         int ret = 0;
4222
4223         plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
4224         if (!plane) {
4225                 DRM_ERROR("KMS: Failed to allocate plane\n");
4226                 return -ENOMEM;
4227         }
4228         plane->type = plane_type;
4229
4230         /*
4231          * HACK: IGT tests expect that the primary plane for a CRTC
4232          * can only have one possible CRTC. Only expose support for
4233          * any CRTC if they're not going to be used as a primary plane
4234          * for a CRTC - like overlay or underlay planes.
4235          */
4236         possible_crtcs = 1 << plane_id;
4237         if (plane_id >= dm->dc->caps.max_streams)
4238                 possible_crtcs = 0xff;
4239
4240         ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
4241
4242         if (ret) {
4243                 DRM_ERROR("KMS: Failed to initialize plane\n");
4244                 kfree(plane);
4245                 return ret;
4246         }
4247
4248         if (mode_info)
4249                 mode_info->planes[plane_id] = plane;
4250
4251         return ret;
4252 }
4253
4254
4255 static void register_backlight_device(struct amdgpu_display_manager *dm,
4256                                       struct dc_link *link)
4257 {
4258         if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
4259             link->type != dc_connection_none) {
4260                 /*
4261                  * Event if registration failed, we should continue with
4262                  * DM initialization because not having a backlight control
4263                  * is better then a black screen.
4264                  */
4265                 if (!dm->backlight_dev[dm->num_of_edps])
4266                         amdgpu_dm_register_backlight_device(dm);
4267
4268                 if (dm->backlight_dev[dm->num_of_edps]) {
4269                         dm->backlight_link[dm->num_of_edps] = link;
4270                         dm->num_of_edps++;
4271                 }
4272         }
4273 }
4274
4275 static void amdgpu_set_panel_orientation(struct drm_connector *connector);
4276
4277 /*
4278  * In this architecture, the association
4279  * connector -> encoder -> crtc
4280  * id not really requried. The crtc and connector will hold the
4281  * display_index as an abstraction to use with DAL component
4282  *
4283  * Returns 0 on success
4284  */
4285 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4286 {
4287         struct amdgpu_display_manager *dm = &adev->dm;
4288         s32 i;
4289         struct amdgpu_dm_connector *aconnector = NULL;
4290         struct amdgpu_encoder *aencoder = NULL;
4291         struct amdgpu_mode_info *mode_info = &adev->mode_info;
4292         u32 link_cnt;
4293         s32 primary_planes;
4294         enum dc_connection_type new_connection_type = dc_connection_none;
4295         const struct dc_plane_cap *plane;
4296         bool psr_feature_enabled = false;
4297         int max_overlay = dm->dc->caps.max_slave_planes;
4298
4299         dm->display_indexes_num = dm->dc->caps.max_streams;
4300         /* Update the actual used number of crtc */
4301         adev->mode_info.num_crtc = adev->dm.display_indexes_num;
4302
4303         amdgpu_dm_set_irq_funcs(adev);
4304
4305         link_cnt = dm->dc->caps.max_links;
4306         if (amdgpu_dm_mode_config_init(dm->adev)) {
4307                 DRM_ERROR("DM: Failed to initialize mode config\n");
4308                 return -EINVAL;
4309         }
4310
4311         /* There is one primary plane per CRTC */
4312         primary_planes = dm->dc->caps.max_streams;
4313         ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
4314
4315         /*
4316          * Initialize primary planes, implicit planes for legacy IOCTLS.
4317          * Order is reversed to match iteration order in atomic check.
4318          */
4319         for (i = (primary_planes - 1); i >= 0; i--) {
4320                 plane = &dm->dc->caps.planes[i];
4321
4322                 if (initialize_plane(dm, mode_info, i,
4323                                      DRM_PLANE_TYPE_PRIMARY, plane)) {
4324                         DRM_ERROR("KMS: Failed to initialize primary plane\n");
4325                         goto fail;
4326                 }
4327         }
4328
4329         /*
4330          * Initialize overlay planes, index starting after primary planes.
4331          * These planes have a higher DRM index than the primary planes since
4332          * they should be considered as having a higher z-order.
4333          * Order is reversed to match iteration order in atomic check.
4334          *
4335          * Only support DCN for now, and only expose one so we don't encourage
4336          * userspace to use up all the pipes.
4337          */
4338         for (i = 0; i < dm->dc->caps.max_planes; ++i) {
4339                 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
4340
4341                 /* Do not create overlay if MPO disabled */
4342                 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO)
4343                         break;
4344
4345                 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
4346                         continue;
4347
4348                 if (!plane->pixel_format_support.argb8888)
4349                         continue;
4350
4351                 if (max_overlay-- == 0)
4352                         break;
4353
4354                 if (initialize_plane(dm, NULL, primary_planes + i,
4355                                      DRM_PLANE_TYPE_OVERLAY, plane)) {
4356                         DRM_ERROR("KMS: Failed to initialize overlay plane\n");
4357                         goto fail;
4358                 }
4359         }
4360
4361         for (i = 0; i < dm->dc->caps.max_streams; i++)
4362                 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
4363                         DRM_ERROR("KMS: Failed to initialize crtc\n");
4364                         goto fail;
4365                 }
4366
4367         /* Use Outbox interrupt */
4368         switch (adev->ip_versions[DCE_HWIP][0]) {
4369         case IP_VERSION(3, 0, 0):
4370         case IP_VERSION(3, 1, 2):
4371         case IP_VERSION(3, 1, 3):
4372         case IP_VERSION(3, 1, 4):
4373         case IP_VERSION(3, 1, 5):
4374         case IP_VERSION(3, 1, 6):
4375         case IP_VERSION(3, 2, 0):
4376         case IP_VERSION(3, 2, 1):
4377         case IP_VERSION(2, 1, 0):
4378                 if (register_outbox_irq_handlers(dm->adev)) {
4379                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4380                         goto fail;
4381                 }
4382                 break;
4383         default:
4384                 DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",
4385                               adev->ip_versions[DCE_HWIP][0]);
4386         }
4387
4388         /* Determine whether to enable PSR support by default. */
4389         if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) {
4390                 switch (adev->ip_versions[DCE_HWIP][0]) {
4391                 case IP_VERSION(3, 1, 2):
4392                 case IP_VERSION(3, 1, 3):
4393                 case IP_VERSION(3, 1, 4):
4394                 case IP_VERSION(3, 1, 5):
4395                 case IP_VERSION(3, 1, 6):
4396                 case IP_VERSION(3, 2, 0):
4397                 case IP_VERSION(3, 2, 1):
4398                         psr_feature_enabled = true;
4399                         break;
4400                 default:
4401                         psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK;
4402                         break;
4403                 }
4404         }
4405
4406         /* loops over all connectors on the board */
4407         for (i = 0; i < link_cnt; i++) {
4408                 struct dc_link *link = NULL;
4409
4410                 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
4411                         DRM_ERROR(
4412                                 "KMS: Cannot support more than %d display indexes\n",
4413                                         AMDGPU_DM_MAX_DISPLAY_INDEX);
4414                         continue;
4415                 }
4416
4417                 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
4418                 if (!aconnector)
4419                         goto fail;
4420
4421                 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
4422                 if (!aencoder)
4423                         goto fail;
4424
4425                 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
4426                         DRM_ERROR("KMS: Failed to initialize encoder\n");
4427                         goto fail;
4428                 }
4429
4430                 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
4431                         DRM_ERROR("KMS: Failed to initialize connector\n");
4432                         goto fail;
4433                 }
4434
4435                 link = dc_get_link_at_index(dm->dc, i);
4436
4437                 if (!dc_link_detect_connection_type(link, &new_connection_type))
4438                         DRM_ERROR("KMS: Failed to detect connector\n");
4439
4440                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
4441                         emulated_link_detect(link);
4442                         amdgpu_dm_update_connector_after_detect(aconnector);
4443                 } else {
4444                         bool ret = false;
4445
4446                         mutex_lock(&dm->dc_lock);
4447                         ret = dc_link_detect(link, DETECT_REASON_BOOT);
4448                         mutex_unlock(&dm->dc_lock);
4449
4450                         if (ret) {
4451                                 amdgpu_dm_update_connector_after_detect(aconnector);
4452                                 register_backlight_device(dm, link);
4453
4454                                 if (dm->num_of_edps)
4455                                         update_connector_ext_caps(aconnector);
4456
4457                                 if (psr_feature_enabled)
4458                                         amdgpu_dm_set_psr_caps(link);
4459
4460                                 /* TODO: Fix vblank control helpers to delay PSR entry to allow this when
4461                                  * PSR is also supported.
4462                                  */
4463                                 if (link->psr_settings.psr_feature_enabled)
4464                                         adev_to_drm(adev)->vblank_disable_immediate = false;
4465                         }
4466                 }
4467                 amdgpu_set_panel_orientation(&aconnector->base);
4468         }
4469
4470         /* If we didn't find a panel, notify the acpi video detection */
4471         if (dm->adev->flags & AMD_IS_APU && dm->num_of_edps == 0)
4472                 acpi_video_report_nolcd();
4473
4474         /* Software is initialized. Now we can register interrupt handlers. */
4475         switch (adev->asic_type) {
4476 #if defined(CONFIG_DRM_AMD_DC_SI)
4477         case CHIP_TAHITI:
4478         case CHIP_PITCAIRN:
4479         case CHIP_VERDE:
4480         case CHIP_OLAND:
4481                 if (dce60_register_irq_handlers(dm->adev)) {
4482                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4483                         goto fail;
4484                 }
4485                 break;
4486 #endif
4487         case CHIP_BONAIRE:
4488         case CHIP_HAWAII:
4489         case CHIP_KAVERI:
4490         case CHIP_KABINI:
4491         case CHIP_MULLINS:
4492         case CHIP_TONGA:
4493         case CHIP_FIJI:
4494         case CHIP_CARRIZO:
4495         case CHIP_STONEY:
4496         case CHIP_POLARIS11:
4497         case CHIP_POLARIS10:
4498         case CHIP_POLARIS12:
4499         case CHIP_VEGAM:
4500         case CHIP_VEGA10:
4501         case CHIP_VEGA12:
4502         case CHIP_VEGA20:
4503                 if (dce110_register_irq_handlers(dm->adev)) {
4504                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4505                         goto fail;
4506                 }
4507                 break;
4508         default:
4509                 switch (adev->ip_versions[DCE_HWIP][0]) {
4510                 case IP_VERSION(1, 0, 0):
4511                 case IP_VERSION(1, 0, 1):
4512                 case IP_VERSION(2, 0, 2):
4513                 case IP_VERSION(2, 0, 3):
4514                 case IP_VERSION(2, 0, 0):
4515                 case IP_VERSION(2, 1, 0):
4516                 case IP_VERSION(3, 0, 0):
4517                 case IP_VERSION(3, 0, 2):
4518                 case IP_VERSION(3, 0, 3):
4519                 case IP_VERSION(3, 0, 1):
4520                 case IP_VERSION(3, 1, 2):
4521                 case IP_VERSION(3, 1, 3):
4522                 case IP_VERSION(3, 1, 4):
4523                 case IP_VERSION(3, 1, 5):
4524                 case IP_VERSION(3, 1, 6):
4525                 case IP_VERSION(3, 2, 0):
4526                 case IP_VERSION(3, 2, 1):
4527                         if (dcn10_register_irq_handlers(dm->adev)) {
4528                                 DRM_ERROR("DM: Failed to initialize IRQ\n");
4529                                 goto fail;
4530                         }
4531                         break;
4532                 default:
4533                         DRM_ERROR("Unsupported DCE IP versions: 0x%X\n",
4534                                         adev->ip_versions[DCE_HWIP][0]);
4535                         goto fail;
4536                 }
4537                 break;
4538         }
4539
4540         return 0;
4541 fail:
4542         kfree(aencoder);
4543         kfree(aconnector);
4544
4545         return -EINVAL;
4546 }
4547
4548 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4549 {
4550         drm_atomic_private_obj_fini(&dm->atomic_obj);
4551         return;
4552 }
4553
4554 /******************************************************************************
4555  * amdgpu_display_funcs functions
4556  *****************************************************************************/
4557
4558 /*
4559  * dm_bandwidth_update - program display watermarks
4560  *
4561  * @adev: amdgpu_device pointer
4562  *
4563  * Calculate and program the display watermarks and line buffer allocation.
4564  */
4565 static void dm_bandwidth_update(struct amdgpu_device *adev)
4566 {
4567         /* TODO: implement later */
4568 }
4569
4570 static const struct amdgpu_display_funcs dm_display_funcs = {
4571         .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
4572         .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
4573         .backlight_set_level = NULL, /* never called for DC */
4574         .backlight_get_level = NULL, /* never called for DC */
4575         .hpd_sense = NULL,/* called unconditionally */
4576         .hpd_set_polarity = NULL, /* called unconditionally */
4577         .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4578         .page_flip_get_scanoutpos =
4579                 dm_crtc_get_scanoutpos,/* called unconditionally */
4580         .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
4581         .add_connector = NULL, /* VBIOS parsing. DAL does it. */
4582 };
4583
4584 #if defined(CONFIG_DEBUG_KERNEL_DC)
4585
4586 static ssize_t s3_debug_store(struct device *device,
4587                               struct device_attribute *attr,
4588                               const char *buf,
4589                               size_t count)
4590 {
4591         int ret;
4592         int s3_state;
4593         struct drm_device *drm_dev = dev_get_drvdata(device);
4594         struct amdgpu_device *adev = drm_to_adev(drm_dev);
4595
4596         ret = kstrtoint(buf, 0, &s3_state);
4597
4598         if (ret == 0) {
4599                 if (s3_state) {
4600                         dm_resume(adev);
4601                         drm_kms_helper_hotplug_event(adev_to_drm(adev));
4602                 } else
4603                         dm_suspend(adev);
4604         }
4605
4606         return ret == 0 ? count : 0;
4607 }
4608
4609 DEVICE_ATTR_WO(s3_debug);
4610
4611 #endif
4612
4613 static int dm_init_microcode(struct amdgpu_device *adev)
4614 {
4615         char *fw_name_dmub;
4616         int r;
4617
4618         switch (adev->ip_versions[DCE_HWIP][0]) {
4619         case IP_VERSION(2, 1, 0):
4620                 fw_name_dmub = FIRMWARE_RENOIR_DMUB;
4621                 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
4622                         fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
4623                 break;
4624         case IP_VERSION(3, 0, 0):
4625                 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
4626                         fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
4627                 else
4628                         fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
4629                 break;
4630         case IP_VERSION(3, 0, 1):
4631                 fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
4632                 break;
4633         case IP_VERSION(3, 0, 2):
4634                 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
4635                 break;
4636         case IP_VERSION(3, 0, 3):
4637                 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;
4638                 break;
4639         case IP_VERSION(3, 1, 2):
4640         case IP_VERSION(3, 1, 3):
4641                 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
4642                 break;
4643         case IP_VERSION(3, 1, 4):
4644                 fw_name_dmub = FIRMWARE_DCN_314_DMUB;
4645                 break;
4646         case IP_VERSION(3, 1, 5):
4647                 fw_name_dmub = FIRMWARE_DCN_315_DMUB;
4648                 break;
4649         case IP_VERSION(3, 1, 6):
4650                 fw_name_dmub = FIRMWARE_DCN316_DMUB;
4651                 break;
4652         case IP_VERSION(3, 2, 0):
4653                 fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB;
4654                 break;
4655         case IP_VERSION(3, 2, 1):
4656                 fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB;
4657                 break;
4658         default:
4659                 /* ASIC doesn't support DMUB. */
4660                 return 0;
4661         }
4662         r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, fw_name_dmub);
4663         if (r)
4664                 DRM_ERROR("DMUB firmware loading failed: %d\n", r);
4665         return r;
4666 }
4667
4668 static int dm_early_init(void *handle)
4669 {
4670         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4671         struct amdgpu_mode_info *mode_info = &adev->mode_info;
4672         struct atom_context *ctx = mode_info->atom_context;
4673         int index = GetIndexIntoMasterTable(DATA, Object_Header);
4674         u16 data_offset;
4675
4676         /* if there is no object header, skip DM */
4677         if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
4678                 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
4679                 dev_info(adev->dev, "No object header, skipping DM\n");
4680                 return -ENOENT;
4681         }
4682
4683         switch (adev->asic_type) {
4684 #if defined(CONFIG_DRM_AMD_DC_SI)
4685         case CHIP_TAHITI:
4686         case CHIP_PITCAIRN:
4687         case CHIP_VERDE:
4688                 adev->mode_info.num_crtc = 6;
4689                 adev->mode_info.num_hpd = 6;
4690                 adev->mode_info.num_dig = 6;
4691                 break;
4692         case CHIP_OLAND:
4693                 adev->mode_info.num_crtc = 2;
4694                 adev->mode_info.num_hpd = 2;
4695                 adev->mode_info.num_dig = 2;
4696                 break;
4697 #endif
4698         case CHIP_BONAIRE:
4699         case CHIP_HAWAII:
4700                 adev->mode_info.num_crtc = 6;
4701                 adev->mode_info.num_hpd = 6;
4702                 adev->mode_info.num_dig = 6;
4703                 break;
4704         case CHIP_KAVERI:
4705                 adev->mode_info.num_crtc = 4;
4706                 adev->mode_info.num_hpd = 6;
4707                 adev->mode_info.num_dig = 7;
4708                 break;
4709         case CHIP_KABINI:
4710         case CHIP_MULLINS:
4711                 adev->mode_info.num_crtc = 2;
4712                 adev->mode_info.num_hpd = 6;
4713                 adev->mode_info.num_dig = 6;
4714                 break;
4715         case CHIP_FIJI:
4716         case CHIP_TONGA:
4717                 adev->mode_info.num_crtc = 6;
4718                 adev->mode_info.num_hpd = 6;
4719                 adev->mode_info.num_dig = 7;
4720                 break;
4721         case CHIP_CARRIZO:
4722                 adev->mode_info.num_crtc = 3;
4723                 adev->mode_info.num_hpd = 6;
4724                 adev->mode_info.num_dig = 9;
4725                 break;
4726         case CHIP_STONEY:
4727                 adev->mode_info.num_crtc = 2;
4728                 adev->mode_info.num_hpd = 6;
4729                 adev->mode_info.num_dig = 9;
4730                 break;
4731         case CHIP_POLARIS11:
4732         case CHIP_POLARIS12:
4733                 adev->mode_info.num_crtc = 5;
4734                 adev->mode_info.num_hpd = 5;
4735                 adev->mode_info.num_dig = 5;
4736                 break;
4737         case CHIP_POLARIS10:
4738         case CHIP_VEGAM:
4739                 adev->mode_info.num_crtc = 6;
4740                 adev->mode_info.num_hpd = 6;
4741                 adev->mode_info.num_dig = 6;
4742                 break;
4743         case CHIP_VEGA10:
4744         case CHIP_VEGA12:
4745         case CHIP_VEGA20:
4746                 adev->mode_info.num_crtc = 6;
4747                 adev->mode_info.num_hpd = 6;
4748                 adev->mode_info.num_dig = 6;
4749                 break;
4750         default:
4751
4752                 switch (adev->ip_versions[DCE_HWIP][0]) {
4753                 case IP_VERSION(2, 0, 2):
4754                 case IP_VERSION(3, 0, 0):
4755                         adev->mode_info.num_crtc = 6;
4756                         adev->mode_info.num_hpd = 6;
4757                         adev->mode_info.num_dig = 6;
4758                         break;
4759                 case IP_VERSION(2, 0, 0):
4760                 case IP_VERSION(3, 0, 2):
4761                         adev->mode_info.num_crtc = 5;
4762                         adev->mode_info.num_hpd = 5;
4763                         adev->mode_info.num_dig = 5;
4764                         break;
4765                 case IP_VERSION(2, 0, 3):
4766                 case IP_VERSION(3, 0, 3):
4767                         adev->mode_info.num_crtc = 2;
4768                         adev->mode_info.num_hpd = 2;
4769                         adev->mode_info.num_dig = 2;
4770                         break;
4771                 case IP_VERSION(1, 0, 0):
4772                 case IP_VERSION(1, 0, 1):
4773                 case IP_VERSION(3, 0, 1):
4774                 case IP_VERSION(2, 1, 0):
4775                 case IP_VERSION(3, 1, 2):
4776                 case IP_VERSION(3, 1, 3):
4777                 case IP_VERSION(3, 1, 4):
4778                 case IP_VERSION(3, 1, 5):
4779                 case IP_VERSION(3, 1, 6):
4780                 case IP_VERSION(3, 2, 0):
4781                 case IP_VERSION(3, 2, 1):
4782                         adev->mode_info.num_crtc = 4;
4783                         adev->mode_info.num_hpd = 4;
4784                         adev->mode_info.num_dig = 4;
4785                         break;
4786                 default:
4787                         DRM_ERROR("Unsupported DCE IP versions: 0x%x\n",
4788                                         adev->ip_versions[DCE_HWIP][0]);
4789                         return -EINVAL;
4790                 }
4791                 break;
4792         }
4793
4794         if (adev->mode_info.funcs == NULL)
4795                 adev->mode_info.funcs = &dm_display_funcs;
4796
4797         /*
4798          * Note: Do NOT change adev->audio_endpt_rreg and
4799          * adev->audio_endpt_wreg because they are initialised in
4800          * amdgpu_device_init()
4801          */
4802 #if defined(CONFIG_DEBUG_KERNEL_DC)
4803         device_create_file(
4804                 adev_to_drm(adev)->dev,
4805                 &dev_attr_s3_debug);
4806 #endif
4807         adev->dc_enabled = true;
4808
4809         return dm_init_microcode(adev);
4810 }
4811
4812 static bool modereset_required(struct drm_crtc_state *crtc_state)
4813 {
4814         return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
4815 }
4816
4817 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
4818 {
4819         drm_encoder_cleanup(encoder);
4820         kfree(encoder);
4821 }
4822
4823 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
4824         .destroy = amdgpu_dm_encoder_destroy,
4825 };
4826
4827 static int
4828 fill_plane_color_attributes(const struct drm_plane_state *plane_state,
4829                             const enum surface_pixel_format format,
4830                             enum dc_color_space *color_space)
4831 {
4832         bool full_range;
4833
4834         *color_space = COLOR_SPACE_SRGB;
4835
4836         /* DRM color properties only affect non-RGB formats. */
4837         if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
4838                 return 0;
4839
4840         full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
4841
4842         switch (plane_state->color_encoding) {
4843         case DRM_COLOR_YCBCR_BT601:
4844                 if (full_range)
4845                         *color_space = COLOR_SPACE_YCBCR601;
4846                 else
4847                         *color_space = COLOR_SPACE_YCBCR601_LIMITED;
4848                 break;
4849
4850         case DRM_COLOR_YCBCR_BT709:
4851                 if (full_range)
4852                         *color_space = COLOR_SPACE_YCBCR709;
4853                 else
4854                         *color_space = COLOR_SPACE_YCBCR709_LIMITED;
4855                 break;
4856
4857         case DRM_COLOR_YCBCR_BT2020:
4858                 if (full_range)
4859                         *color_space = COLOR_SPACE_2020_YCBCR;
4860                 else
4861                         return -EINVAL;
4862                 break;
4863
4864         default:
4865                 return -EINVAL;
4866         }
4867
4868         return 0;
4869 }
4870
4871 static int
4872 fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
4873                             const struct drm_plane_state *plane_state,
4874                             const u64 tiling_flags,
4875                             struct dc_plane_info *plane_info,
4876                             struct dc_plane_address *address,
4877                             bool tmz_surface,
4878                             bool force_disable_dcc)
4879 {
4880         const struct drm_framebuffer *fb = plane_state->fb;
4881         const struct amdgpu_framebuffer *afb =
4882                 to_amdgpu_framebuffer(plane_state->fb);
4883         int ret;
4884
4885         memset(plane_info, 0, sizeof(*plane_info));
4886
4887         switch (fb->format->format) {
4888         case DRM_FORMAT_C8:
4889                 plane_info->format =
4890                         SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
4891                 break;
4892         case DRM_FORMAT_RGB565:
4893                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
4894                 break;
4895         case DRM_FORMAT_XRGB8888:
4896         case DRM_FORMAT_ARGB8888:
4897                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
4898                 break;
4899         case DRM_FORMAT_XRGB2101010:
4900         case DRM_FORMAT_ARGB2101010:
4901                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
4902                 break;
4903         case DRM_FORMAT_XBGR2101010:
4904         case DRM_FORMAT_ABGR2101010:
4905                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
4906                 break;
4907         case DRM_FORMAT_XBGR8888:
4908         case DRM_FORMAT_ABGR8888:
4909                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
4910                 break;
4911         case DRM_FORMAT_NV21:
4912                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
4913                 break;
4914         case DRM_FORMAT_NV12:
4915                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
4916                 break;
4917         case DRM_FORMAT_P010:
4918                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb;
4919                 break;
4920         case DRM_FORMAT_XRGB16161616F:
4921         case DRM_FORMAT_ARGB16161616F:
4922                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F;
4923                 break;
4924         case DRM_FORMAT_XBGR16161616F:
4925         case DRM_FORMAT_ABGR16161616F:
4926                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;
4927                 break;
4928         case DRM_FORMAT_XRGB16161616:
4929         case DRM_FORMAT_ARGB16161616:
4930                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616;
4931                 break;
4932         case DRM_FORMAT_XBGR16161616:
4933         case DRM_FORMAT_ABGR16161616:
4934                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616;
4935                 break;
4936         default:
4937                 DRM_ERROR(
4938                         "Unsupported screen format %p4cc\n",
4939                         &fb->format->format);
4940                 return -EINVAL;
4941         }
4942
4943         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
4944         case DRM_MODE_ROTATE_0:
4945                 plane_info->rotation = ROTATION_ANGLE_0;
4946                 break;
4947         case DRM_MODE_ROTATE_90:
4948                 plane_info->rotation = ROTATION_ANGLE_90;
4949                 break;
4950         case DRM_MODE_ROTATE_180:
4951                 plane_info->rotation = ROTATION_ANGLE_180;
4952                 break;
4953         case DRM_MODE_ROTATE_270:
4954                 plane_info->rotation = ROTATION_ANGLE_270;
4955                 break;
4956         default:
4957                 plane_info->rotation = ROTATION_ANGLE_0;
4958                 break;
4959         }
4960
4961
4962         plane_info->visible = true;
4963         plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
4964
4965         plane_info->layer_index = plane_state->normalized_zpos;
4966
4967         ret = fill_plane_color_attributes(plane_state, plane_info->format,
4968                                           &plane_info->color_space);
4969         if (ret)
4970                 return ret;
4971
4972         ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format,
4973                                            plane_info->rotation, tiling_flags,
4974                                            &plane_info->tiling_info,
4975                                            &plane_info->plane_size,
4976                                            &plane_info->dcc, address,
4977                                            tmz_surface, force_disable_dcc);
4978         if (ret)
4979                 return ret;
4980
4981         amdgpu_dm_plane_fill_blending_from_plane_state(
4982                 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha,
4983                 &plane_info->global_alpha, &plane_info->global_alpha_value);
4984
4985         return 0;
4986 }
4987
4988 static int fill_dc_plane_attributes(struct amdgpu_device *adev,
4989                                     struct dc_plane_state *dc_plane_state,
4990                                     struct drm_plane_state *plane_state,
4991                                     struct drm_crtc_state *crtc_state)
4992 {
4993         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
4994         struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb;
4995         struct dc_scaling_info scaling_info;
4996         struct dc_plane_info plane_info;
4997         int ret;
4998         bool force_disable_dcc = false;
4999
5000         ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info);
5001         if (ret)
5002                 return ret;
5003
5004         dc_plane_state->src_rect = scaling_info.src_rect;
5005         dc_plane_state->dst_rect = scaling_info.dst_rect;
5006         dc_plane_state->clip_rect = scaling_info.clip_rect;
5007         dc_plane_state->scaling_quality = scaling_info.scaling_quality;
5008
5009         force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
5010         ret = fill_dc_plane_info_and_addr(adev, plane_state,
5011                                           afb->tiling_flags,
5012                                           &plane_info,
5013                                           &dc_plane_state->address,
5014                                           afb->tmz_surface,
5015                                           force_disable_dcc);
5016         if (ret)
5017                 return ret;
5018
5019         dc_plane_state->format = plane_info.format;
5020         dc_plane_state->color_space = plane_info.color_space;
5021         dc_plane_state->format = plane_info.format;
5022         dc_plane_state->plane_size = plane_info.plane_size;
5023         dc_plane_state->rotation = plane_info.rotation;
5024         dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
5025         dc_plane_state->stereo_format = plane_info.stereo_format;
5026         dc_plane_state->tiling_info = plane_info.tiling_info;
5027         dc_plane_state->visible = plane_info.visible;
5028         dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
5029         dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha;
5030         dc_plane_state->global_alpha = plane_info.global_alpha;
5031         dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
5032         dc_plane_state->dcc = plane_info.dcc;
5033         dc_plane_state->layer_index = plane_info.layer_index;
5034         dc_plane_state->flip_int_enabled = true;
5035
5036         /*
5037          * Always set input transfer function, since plane state is refreshed
5038          * every time.
5039          */
5040         ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
5041         if (ret)
5042                 return ret;
5043
5044         return 0;
5045 }
5046
5047 static inline void fill_dc_dirty_rect(struct drm_plane *plane,
5048                                       struct rect *dirty_rect, int32_t x,
5049                                       s32 y, s32 width, s32 height,
5050                                       int *i, bool ffu)
5051 {
5052         if (*i > DC_MAX_DIRTY_RECTS)
5053                 return;
5054
5055         if (*i == DC_MAX_DIRTY_RECTS)
5056                 goto out;
5057
5058         dirty_rect->x = x;
5059         dirty_rect->y = y;
5060         dirty_rect->width = width;
5061         dirty_rect->height = height;
5062
5063         if (ffu)
5064                 drm_dbg(plane->dev,
5065                         "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n",
5066                         plane->base.id, width, height);
5067         else
5068                 drm_dbg(plane->dev,
5069                         "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)",
5070                         plane->base.id, x, y, width, height);
5071
5072 out:
5073         (*i)++;
5074 }
5075
5076 /**
5077  * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates
5078  *
5079  * @plane: DRM plane containing dirty regions that need to be flushed to the eDP
5080  *         remote fb
5081  * @old_plane_state: Old state of @plane
5082  * @new_plane_state: New state of @plane
5083  * @crtc_state: New state of CRTC connected to the @plane
5084  * @flip_addrs: DC flip tracking struct, which also tracts dirty rects
5085  * @dirty_regions_changed: dirty regions changed
5086  *
5087  * For PSR SU, DC informs the DMUB uController of dirty rectangle regions
5088  * (referred to as "damage clips" in DRM nomenclature) that require updating on
5089  * the eDP remote buffer. The responsibility of specifying the dirty regions is
5090  * amdgpu_dm's.
5091  *
5092  * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the
5093  * plane with regions that require flushing to the eDP remote buffer. In
5094  * addition, certain use cases - such as cursor and multi-plane overlay (MPO) -
5095  * implicitly provide damage clips without any client support via the plane
5096  * bounds.
5097  */
5098 static void fill_dc_dirty_rects(struct drm_plane *plane,
5099                                 struct drm_plane_state *old_plane_state,
5100                                 struct drm_plane_state *new_plane_state,
5101                                 struct drm_crtc_state *crtc_state,
5102                                 struct dc_flip_addrs *flip_addrs,
5103                                 bool *dirty_regions_changed)
5104 {
5105         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5106         struct rect *dirty_rects = flip_addrs->dirty_rects;
5107         u32 num_clips;
5108         struct drm_mode_rect *clips;
5109         bool bb_changed;
5110         bool fb_changed;
5111         u32 i = 0;
5112         *dirty_regions_changed = false;
5113
5114         /*
5115          * Cursor plane has it's own dirty rect update interface. See
5116          * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data
5117          */
5118         if (plane->type == DRM_PLANE_TYPE_CURSOR)
5119                 return;
5120
5121         num_clips = drm_plane_get_damage_clips_count(new_plane_state);
5122         clips = drm_plane_get_damage_clips(new_plane_state);
5123
5124         if (!dm_crtc_state->mpo_requested) {
5125                 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS)
5126                         goto ffu;
5127
5128                 for (; flip_addrs->dirty_rect_count < num_clips; clips++)
5129                         fill_dc_dirty_rect(new_plane_state->plane,
5130                                            &dirty_rects[i], clips->x1,
5131                                            clips->y1, clips->x2 - clips->x1,
5132                                            clips->y2 - clips->y1,
5133                                            &flip_addrs->dirty_rect_count,
5134                                            false);
5135                 return;
5136         }
5137
5138         /*
5139          * MPO is requested. Add entire plane bounding box to dirty rects if
5140          * flipped to or damaged.
5141          *
5142          * If plane is moved or resized, also add old bounding box to dirty
5143          * rects.
5144          */
5145         fb_changed = old_plane_state->fb->base.id !=
5146                      new_plane_state->fb->base.id;
5147         bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x ||
5148                       old_plane_state->crtc_y != new_plane_state->crtc_y ||
5149                       old_plane_state->crtc_w != new_plane_state->crtc_w ||
5150                       old_plane_state->crtc_h != new_plane_state->crtc_h);
5151
5152         drm_dbg(plane->dev,
5153                 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n",
5154                 new_plane_state->plane->base.id,
5155                 bb_changed, fb_changed, num_clips);
5156
5157         *dirty_regions_changed = bb_changed;
5158
5159         if (bb_changed) {
5160                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5161                                    new_plane_state->crtc_x,
5162                                    new_plane_state->crtc_y,
5163                                    new_plane_state->crtc_w,
5164                                    new_plane_state->crtc_h, &i, false);
5165
5166                 /* Add old plane bounding-box if plane is moved or resized */
5167                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5168                                    old_plane_state->crtc_x,
5169                                    old_plane_state->crtc_y,
5170                                    old_plane_state->crtc_w,
5171                                    old_plane_state->crtc_h, &i, false);
5172         }
5173
5174         if (num_clips) {
5175                 for (; i < num_clips; clips++)
5176                         fill_dc_dirty_rect(new_plane_state->plane,
5177                                            &dirty_rects[i], clips->x1,
5178                                            clips->y1, clips->x2 - clips->x1,
5179                                            clips->y2 - clips->y1, &i, false);
5180         } else if (fb_changed && !bb_changed) {
5181                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5182                                    new_plane_state->crtc_x,
5183                                    new_plane_state->crtc_y,
5184                                    new_plane_state->crtc_w,
5185                                    new_plane_state->crtc_h, &i, false);
5186         }
5187
5188         if (i > DC_MAX_DIRTY_RECTS)
5189                 goto ffu;
5190
5191         flip_addrs->dirty_rect_count = i;
5192         return;
5193
5194 ffu:
5195         fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0,
5196                            dm_crtc_state->base.mode.crtc_hdisplay,
5197                            dm_crtc_state->base.mode.crtc_vdisplay,
5198                            &flip_addrs->dirty_rect_count, true);
5199 }
5200
5201 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
5202                                            const struct dm_connector_state *dm_state,
5203                                            struct dc_stream_state *stream)
5204 {
5205         enum amdgpu_rmx_type rmx_type;
5206
5207         struct rect src = { 0 }; /* viewport in composition space*/
5208         struct rect dst = { 0 }; /* stream addressable area */
5209
5210         /* no mode. nothing to be done */
5211         if (!mode)
5212                 return;
5213
5214         /* Full screen scaling by default */
5215         src.width = mode->hdisplay;
5216         src.height = mode->vdisplay;
5217         dst.width = stream->timing.h_addressable;
5218         dst.height = stream->timing.v_addressable;
5219
5220         if (dm_state) {
5221                 rmx_type = dm_state->scaling;
5222                 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
5223                         if (src.width * dst.height <
5224                                         src.height * dst.width) {
5225                                 /* height needs less upscaling/more downscaling */
5226                                 dst.width = src.width *
5227                                                 dst.height / src.height;
5228                         } else {
5229                                 /* width needs less upscaling/more downscaling */
5230                                 dst.height = src.height *
5231                                                 dst.width / src.width;
5232                         }
5233                 } else if (rmx_type == RMX_CENTER) {
5234                         dst = src;
5235                 }
5236
5237                 dst.x = (stream->timing.h_addressable - dst.width) / 2;
5238                 dst.y = (stream->timing.v_addressable - dst.height) / 2;
5239
5240                 if (dm_state->underscan_enable) {
5241                         dst.x += dm_state->underscan_hborder / 2;
5242                         dst.y += dm_state->underscan_vborder / 2;
5243                         dst.width -= dm_state->underscan_hborder;
5244                         dst.height -= dm_state->underscan_vborder;
5245                 }
5246         }
5247
5248         stream->src = src;
5249         stream->dst = dst;
5250
5251         DRM_DEBUG_KMS("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",
5252                       dst.x, dst.y, dst.width, dst.height);
5253
5254 }
5255
5256 static enum dc_color_depth
5257 convert_color_depth_from_display_info(const struct drm_connector *connector,
5258                                       bool is_y420, int requested_bpc)
5259 {
5260         u8 bpc;
5261
5262         if (is_y420) {
5263                 bpc = 8;
5264
5265                 /* Cap display bpc based on HDMI 2.0 HF-VSDB */
5266                 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)
5267                         bpc = 16;
5268                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
5269                         bpc = 12;
5270                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
5271                         bpc = 10;
5272         } else {
5273                 bpc = (uint8_t)connector->display_info.bpc;
5274                 /* Assume 8 bpc by default if no bpc is specified. */
5275                 bpc = bpc ? bpc : 8;
5276         }
5277
5278         if (requested_bpc > 0) {
5279                 /*
5280                  * Cap display bpc based on the user requested value.
5281                  *
5282                  * The value for state->max_bpc may not correctly updated
5283                  * depending on when the connector gets added to the state
5284                  * or if this was called outside of atomic check, so it
5285                  * can't be used directly.
5286                  */
5287                 bpc = min_t(u8, bpc, requested_bpc);
5288
5289                 /* Round down to the nearest even number. */
5290                 bpc = bpc - (bpc & 1);
5291         }
5292
5293         switch (bpc) {
5294         case 0:
5295                 /*
5296                  * Temporary Work around, DRM doesn't parse color depth for
5297                  * EDID revision before 1.4
5298                  * TODO: Fix edid parsing
5299                  */
5300                 return COLOR_DEPTH_888;
5301         case 6:
5302                 return COLOR_DEPTH_666;
5303         case 8:
5304                 return COLOR_DEPTH_888;
5305         case 10:
5306                 return COLOR_DEPTH_101010;
5307         case 12:
5308                 return COLOR_DEPTH_121212;
5309         case 14:
5310                 return COLOR_DEPTH_141414;
5311         case 16:
5312                 return COLOR_DEPTH_161616;
5313         default:
5314                 return COLOR_DEPTH_UNDEFINED;
5315         }
5316 }
5317
5318 static enum dc_aspect_ratio
5319 get_aspect_ratio(const struct drm_display_mode *mode_in)
5320 {
5321         /* 1-1 mapping, since both enums follow the HDMI spec. */
5322         return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
5323 }
5324
5325 static enum dc_color_space
5326 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
5327 {
5328         enum dc_color_space color_space = COLOR_SPACE_SRGB;
5329
5330         switch (dc_crtc_timing->pixel_encoding) {
5331         case PIXEL_ENCODING_YCBCR422:
5332         case PIXEL_ENCODING_YCBCR444:
5333         case PIXEL_ENCODING_YCBCR420:
5334         {
5335                 /*
5336                  * 27030khz is the separation point between HDTV and SDTV
5337                  * according to HDMI spec, we use YCbCr709 and YCbCr601
5338                  * respectively
5339                  */
5340                 if (dc_crtc_timing->pix_clk_100hz > 270300) {
5341                         if (dc_crtc_timing->flags.Y_ONLY)
5342                                 color_space =
5343                                         COLOR_SPACE_YCBCR709_LIMITED;
5344                         else
5345                                 color_space = COLOR_SPACE_YCBCR709;
5346                 } else {
5347                         if (dc_crtc_timing->flags.Y_ONLY)
5348                                 color_space =
5349                                         COLOR_SPACE_YCBCR601_LIMITED;
5350                         else
5351                                 color_space = COLOR_SPACE_YCBCR601;
5352                 }
5353
5354         }
5355         break;
5356         case PIXEL_ENCODING_RGB:
5357                 color_space = COLOR_SPACE_SRGB;
5358                 break;
5359
5360         default:
5361                 WARN_ON(1);
5362                 break;
5363         }
5364
5365         return color_space;
5366 }
5367
5368 static bool adjust_colour_depth_from_display_info(
5369         struct dc_crtc_timing *timing_out,
5370         const struct drm_display_info *info)
5371 {
5372         enum dc_color_depth depth = timing_out->display_color_depth;
5373         int normalized_clk;
5374         do {
5375                 normalized_clk = timing_out->pix_clk_100hz / 10;
5376                 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
5377                 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
5378                         normalized_clk /= 2;
5379                 /* Adjusting pix clock following on HDMI spec based on colour depth */
5380                 switch (depth) {
5381                 case COLOR_DEPTH_888:
5382                         break;
5383                 case COLOR_DEPTH_101010:
5384                         normalized_clk = (normalized_clk * 30) / 24;
5385                         break;
5386                 case COLOR_DEPTH_121212:
5387                         normalized_clk = (normalized_clk * 36) / 24;
5388                         break;
5389                 case COLOR_DEPTH_161616:
5390                         normalized_clk = (normalized_clk * 48) / 24;
5391                         break;
5392                 default:
5393                         /* The above depths are the only ones valid for HDMI. */
5394                         return false;
5395                 }
5396                 if (normalized_clk <= info->max_tmds_clock) {
5397                         timing_out->display_color_depth = depth;
5398                         return true;
5399                 }
5400         } while (--depth > COLOR_DEPTH_666);
5401         return false;
5402 }
5403
5404 static void fill_stream_properties_from_drm_display_mode(
5405         struct dc_stream_state *stream,
5406         const struct drm_display_mode *mode_in,
5407         const struct drm_connector *connector,
5408         const struct drm_connector_state *connector_state,
5409         const struct dc_stream_state *old_stream,
5410         int requested_bpc)
5411 {
5412         struct dc_crtc_timing *timing_out = &stream->timing;
5413         const struct drm_display_info *info = &connector->display_info;
5414         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5415         struct hdmi_vendor_infoframe hv_frame;
5416         struct hdmi_avi_infoframe avi_frame;
5417
5418         memset(&hv_frame, 0, sizeof(hv_frame));
5419         memset(&avi_frame, 0, sizeof(avi_frame));
5420
5421         timing_out->h_border_left = 0;
5422         timing_out->h_border_right = 0;
5423         timing_out->v_border_top = 0;
5424         timing_out->v_border_bottom = 0;
5425         /* TODO: un-hardcode */
5426         if (drm_mode_is_420_only(info, mode_in)
5427                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5428                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5429         else if (drm_mode_is_420_also(info, mode_in)
5430                         && aconnector->force_yuv420_output)
5431                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5432         else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444)
5433                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5434                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
5435         else
5436                 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
5437
5438         timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
5439         timing_out->display_color_depth = convert_color_depth_from_display_info(
5440                 connector,
5441                 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420),
5442                 requested_bpc);
5443         timing_out->scan_type = SCANNING_TYPE_NODATA;
5444         timing_out->hdmi_vic = 0;
5445
5446         if (old_stream) {
5447                 timing_out->vic = old_stream->timing.vic;
5448                 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
5449                 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
5450         } else {
5451                 timing_out->vic = drm_match_cea_mode(mode_in);
5452                 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
5453                         timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
5454                 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
5455                         timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
5456         }
5457
5458         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5459                 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
5460                 timing_out->vic = avi_frame.video_code;
5461                 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
5462                 timing_out->hdmi_vic = hv_frame.vic;
5463         }
5464
5465         if (is_freesync_video_mode(mode_in, aconnector)) {
5466                 timing_out->h_addressable = mode_in->hdisplay;
5467                 timing_out->h_total = mode_in->htotal;
5468                 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start;
5469                 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay;
5470                 timing_out->v_total = mode_in->vtotal;
5471                 timing_out->v_addressable = mode_in->vdisplay;
5472                 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay;
5473                 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start;
5474                 timing_out->pix_clk_100hz = mode_in->clock * 10;
5475         } else {
5476                 timing_out->h_addressable = mode_in->crtc_hdisplay;
5477                 timing_out->h_total = mode_in->crtc_htotal;
5478                 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
5479                 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
5480                 timing_out->v_total = mode_in->crtc_vtotal;
5481                 timing_out->v_addressable = mode_in->crtc_vdisplay;
5482                 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
5483                 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
5484                 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
5485         }
5486
5487         timing_out->aspect_ratio = get_aspect_ratio(mode_in);
5488
5489         stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
5490         stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
5491         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5492                 if (!adjust_colour_depth_from_display_info(timing_out, info) &&
5493                     drm_mode_is_420_also(info, mode_in) &&
5494                     timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
5495                         timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5496                         adjust_colour_depth_from_display_info(timing_out, info);
5497                 }
5498         }
5499
5500         stream->output_color_space = get_output_color_space(timing_out);
5501 }
5502
5503 static void fill_audio_info(struct audio_info *audio_info,
5504                             const struct drm_connector *drm_connector,
5505                             const struct dc_sink *dc_sink)
5506 {
5507         int i = 0;
5508         int cea_revision = 0;
5509         const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
5510
5511         audio_info->manufacture_id = edid_caps->manufacturer_id;
5512         audio_info->product_id = edid_caps->product_id;
5513
5514         cea_revision = drm_connector->display_info.cea_rev;
5515
5516         strscpy(audio_info->display_name,
5517                 edid_caps->display_name,
5518                 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
5519
5520         if (cea_revision >= 3) {
5521                 audio_info->mode_count = edid_caps->audio_mode_count;
5522
5523                 for (i = 0; i < audio_info->mode_count; ++i) {
5524                         audio_info->modes[i].format_code =
5525                                         (enum audio_format_code)
5526                                         (edid_caps->audio_modes[i].format_code);
5527                         audio_info->modes[i].channel_count =
5528                                         edid_caps->audio_modes[i].channel_count;
5529                         audio_info->modes[i].sample_rates.all =
5530                                         edid_caps->audio_modes[i].sample_rate;
5531                         audio_info->modes[i].sample_size =
5532                                         edid_caps->audio_modes[i].sample_size;
5533                 }
5534         }
5535
5536         audio_info->flags.all = edid_caps->speaker_flags;
5537
5538         /* TODO: We only check for the progressive mode, check for interlace mode too */
5539         if (drm_connector->latency_present[0]) {
5540                 audio_info->video_latency = drm_connector->video_latency[0];
5541                 audio_info->audio_latency = drm_connector->audio_latency[0];
5542         }
5543
5544         /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
5545
5546 }
5547
5548 static void
5549 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
5550                                       struct drm_display_mode *dst_mode)
5551 {
5552         dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
5553         dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
5554         dst_mode->crtc_clock = src_mode->crtc_clock;
5555         dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
5556         dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
5557         dst_mode->crtc_hsync_start =  src_mode->crtc_hsync_start;
5558         dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
5559         dst_mode->crtc_htotal = src_mode->crtc_htotal;
5560         dst_mode->crtc_hskew = src_mode->crtc_hskew;
5561         dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
5562         dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
5563         dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
5564         dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
5565         dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
5566 }
5567
5568 static void
5569 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
5570                                         const struct drm_display_mode *native_mode,
5571                                         bool scale_enabled)
5572 {
5573         if (scale_enabled) {
5574                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5575         } else if (native_mode->clock == drm_mode->clock &&
5576                         native_mode->htotal == drm_mode->htotal &&
5577                         native_mode->vtotal == drm_mode->vtotal) {
5578                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5579         } else {
5580                 /* no scaling nor amdgpu inserted, no need to patch */
5581         }
5582 }
5583
5584 static struct dc_sink *
5585 create_fake_sink(struct amdgpu_dm_connector *aconnector)
5586 {
5587         struct dc_sink_init_data sink_init_data = { 0 };
5588         struct dc_sink *sink = NULL;
5589         sink_init_data.link = aconnector->dc_link;
5590         sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
5591
5592         sink = dc_sink_create(&sink_init_data);
5593         if (!sink) {
5594                 DRM_ERROR("Failed to create sink!\n");
5595                 return NULL;
5596         }
5597         sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
5598
5599         return sink;
5600 }
5601
5602 static void set_multisync_trigger_params(
5603                 struct dc_stream_state *stream)
5604 {
5605         struct dc_stream_state *master = NULL;
5606
5607         if (stream->triggered_crtc_reset.enabled) {
5608                 master = stream->triggered_crtc_reset.event_source;
5609                 stream->triggered_crtc_reset.event =
5610                         master->timing.flags.VSYNC_POSITIVE_POLARITY ?
5611                         CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING;
5612                 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL;
5613         }
5614 }
5615
5616 static void set_master_stream(struct dc_stream_state *stream_set[],
5617                               int stream_count)
5618 {
5619         int j, highest_rfr = 0, master_stream = 0;
5620
5621         for (j = 0;  j < stream_count; j++) {
5622                 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
5623                         int refresh_rate = 0;
5624
5625                         refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
5626                                 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
5627                         if (refresh_rate > highest_rfr) {
5628                                 highest_rfr = refresh_rate;
5629                                 master_stream = j;
5630                         }
5631                 }
5632         }
5633         for (j = 0;  j < stream_count; j++) {
5634                 if (stream_set[j])
5635                         stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
5636         }
5637 }
5638
5639 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
5640 {
5641         int i = 0;
5642         struct dc_stream_state *stream;
5643
5644         if (context->stream_count < 2)
5645                 return;
5646         for (i = 0; i < context->stream_count ; i++) {
5647                 if (!context->streams[i])
5648                         continue;
5649                 /*
5650                  * TODO: add a function to read AMD VSDB bits and set
5651                  * crtc_sync_master.multi_sync_enabled flag
5652                  * For now it's set to false
5653                  */
5654         }
5655
5656         set_master_stream(context->streams, context->stream_count);
5657
5658         for (i = 0; i < context->stream_count ; i++) {
5659                 stream = context->streams[i];
5660
5661                 if (!stream)
5662                         continue;
5663
5664                 set_multisync_trigger_params(stream);
5665         }
5666 }
5667
5668 /**
5669  * DOC: FreeSync Video
5670  *
5671  * When a userspace application wants to play a video, the content follows a
5672  * standard format definition that usually specifies the FPS for that format.
5673  * The below list illustrates some video format and the expected FPS,
5674  * respectively:
5675  *
5676  * - TV/NTSC (23.976 FPS)
5677  * - Cinema (24 FPS)
5678  * - TV/PAL (25 FPS)
5679  * - TV/NTSC (29.97 FPS)
5680  * - TV/NTSC (30 FPS)
5681  * - Cinema HFR (48 FPS)
5682  * - TV/PAL (50 FPS)
5683  * - Commonly used (60 FPS)
5684  * - Multiples of 24 (48,72,96 FPS)
5685  *
5686  * The list of standards video format is not huge and can be added to the
5687  * connector modeset list beforehand. With that, userspace can leverage
5688  * FreeSync to extends the front porch in order to attain the target refresh
5689  * rate. Such a switch will happen seamlessly, without screen blanking or
5690  * reprogramming of the output in any other way. If the userspace requests a
5691  * modesetting change compatible with FreeSync modes that only differ in the
5692  * refresh rate, DC will skip the full update and avoid blink during the
5693  * transition. For example, the video player can change the modesetting from
5694  * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without
5695  * causing any display blink. This same concept can be applied to a mode
5696  * setting change.
5697  */
5698 static struct drm_display_mode *
5699 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
5700                 bool use_probed_modes)
5701 {
5702         struct drm_display_mode *m, *m_pref = NULL;
5703         u16 current_refresh, highest_refresh;
5704         struct list_head *list_head = use_probed_modes ?
5705                 &aconnector->base.probed_modes :
5706                 &aconnector->base.modes;
5707
5708         if (aconnector->freesync_vid_base.clock != 0)
5709                 return &aconnector->freesync_vid_base;
5710
5711         /* Find the preferred mode */
5712         list_for_each_entry (m, list_head, head) {
5713                 if (m->type & DRM_MODE_TYPE_PREFERRED) {
5714                         m_pref = m;
5715                         break;
5716                 }
5717         }
5718
5719         if (!m_pref) {
5720                 /* Probably an EDID with no preferred mode. Fallback to first entry */
5721                 m_pref = list_first_entry_or_null(
5722                                 &aconnector->base.modes, struct drm_display_mode, head);
5723                 if (!m_pref) {
5724                         DRM_DEBUG_DRIVER("No preferred mode found in EDID\n");
5725                         return NULL;
5726                 }
5727         }
5728
5729         highest_refresh = drm_mode_vrefresh(m_pref);
5730
5731         /*
5732          * Find the mode with highest refresh rate with same resolution.
5733          * For some monitors, preferred mode is not the mode with highest
5734          * supported refresh rate.
5735          */
5736         list_for_each_entry (m, list_head, head) {
5737                 current_refresh  = drm_mode_vrefresh(m);
5738
5739                 if (m->hdisplay == m_pref->hdisplay &&
5740                     m->vdisplay == m_pref->vdisplay &&
5741                     highest_refresh < current_refresh) {
5742                         highest_refresh = current_refresh;
5743                         m_pref = m;
5744                 }
5745         }
5746
5747         drm_mode_copy(&aconnector->freesync_vid_base, m_pref);
5748         return m_pref;
5749 }
5750
5751 static bool is_freesync_video_mode(const struct drm_display_mode *mode,
5752                 struct amdgpu_dm_connector *aconnector)
5753 {
5754         struct drm_display_mode *high_mode;
5755         int timing_diff;
5756
5757         high_mode = get_highest_refresh_rate_mode(aconnector, false);
5758         if (!high_mode || !mode)
5759                 return false;
5760
5761         timing_diff = high_mode->vtotal - mode->vtotal;
5762
5763         if (high_mode->clock == 0 || high_mode->clock != mode->clock ||
5764             high_mode->hdisplay != mode->hdisplay ||
5765             high_mode->vdisplay != mode->vdisplay ||
5766             high_mode->hsync_start != mode->hsync_start ||
5767             high_mode->hsync_end != mode->hsync_end ||
5768             high_mode->htotal != mode->htotal ||
5769             high_mode->hskew != mode->hskew ||
5770             high_mode->vscan != mode->vscan ||
5771             high_mode->vsync_start - mode->vsync_start != timing_diff ||
5772             high_mode->vsync_end - mode->vsync_end != timing_diff)
5773                 return false;
5774         else
5775                 return true;
5776 }
5777
5778 static void update_dsc_caps(struct amdgpu_dm_connector *aconnector,
5779                             struct dc_sink *sink, struct dc_stream_state *stream,
5780                             struct dsc_dec_dpcd_caps *dsc_caps)
5781 {
5782         stream->timing.flags.DSC = 0;
5783         dsc_caps->is_dsc_supported = false;
5784
5785         if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
5786             sink->sink_signal == SIGNAL_TYPE_EDP)) {
5787                 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE ||
5788                         sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
5789                         dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
5790                                 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
5791                                 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
5792                                 dsc_caps);
5793         }
5794 }
5795
5796
5797 static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
5798                                     struct dc_sink *sink, struct dc_stream_state *stream,
5799                                     struct dsc_dec_dpcd_caps *dsc_caps,
5800                                     uint32_t max_dsc_target_bpp_limit_override)
5801 {
5802         const struct dc_link_settings *verified_link_cap = NULL;
5803         u32 link_bw_in_kbps;
5804         u32 edp_min_bpp_x16, edp_max_bpp_x16;
5805         struct dc *dc = sink->ctx->dc;
5806         struct dc_dsc_bw_range bw_range = {0};
5807         struct dc_dsc_config dsc_cfg = {0};
5808         struct dc_dsc_config_options dsc_options = {0};
5809
5810         dc_dsc_get_default_config_option(dc, &dsc_options);
5811         dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5812
5813         verified_link_cap = dc_link_get_link_cap(stream->link);
5814         link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap);
5815         edp_min_bpp_x16 = 8 * 16;
5816         edp_max_bpp_x16 = 8 * 16;
5817
5818         if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel)
5819                 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel;
5820
5821         if (edp_max_bpp_x16 < edp_min_bpp_x16)
5822                 edp_min_bpp_x16 = edp_max_bpp_x16;
5823
5824         if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0],
5825                                 dc->debug.dsc_min_slice_height_override,
5826                                 edp_min_bpp_x16, edp_max_bpp_x16,
5827                                 dsc_caps,
5828                                 &stream->timing,
5829                                 &bw_range)) {
5830
5831                 if (bw_range.max_kbps < link_bw_in_kbps) {
5832                         if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5833                                         dsc_caps,
5834                                         &dsc_options,
5835                                         0,
5836                                         &stream->timing,
5837                                         &dsc_cfg)) {
5838                                 stream->timing.dsc_cfg = dsc_cfg;
5839                                 stream->timing.flags.DSC = 1;
5840                                 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16;
5841                         }
5842                         return;
5843                 }
5844         }
5845
5846         if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5847                                 dsc_caps,
5848                                 &dsc_options,
5849                                 link_bw_in_kbps,
5850                                 &stream->timing,
5851                                 &dsc_cfg)) {
5852                 stream->timing.dsc_cfg = dsc_cfg;
5853                 stream->timing.flags.DSC = 1;
5854         }
5855 }
5856
5857
5858 static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
5859                                         struct dc_sink *sink, struct dc_stream_state *stream,
5860                                         struct dsc_dec_dpcd_caps *dsc_caps)
5861 {
5862         struct drm_connector *drm_connector = &aconnector->base;
5863         u32 link_bandwidth_kbps;
5864         struct dc *dc = sink->ctx->dc;
5865         u32 max_supported_bw_in_kbps, timing_bw_in_kbps;
5866         u32 dsc_max_supported_bw_in_kbps;
5867         u32 max_dsc_target_bpp_limit_override =
5868                 drm_connector->display_info.max_dsc_bpp;
5869         struct dc_dsc_config_options dsc_options = {0};
5870
5871         dc_dsc_get_default_config_option(dc, &dsc_options);
5872         dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5873
5874         link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
5875                                                         dc_link_get_link_cap(aconnector->dc_link));
5876
5877         /* Set DSC policy according to dsc_clock_en */
5878         dc_dsc_policy_set_enable_dsc_when_not_needed(
5879                 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);
5880
5881         if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP &&
5882             !aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&
5883             dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
5884
5885                 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);
5886
5887         } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
5888                 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
5889                         if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5890                                                 dsc_caps,
5891                                                 &dsc_options,
5892                                                 link_bandwidth_kbps,
5893                                                 &stream->timing,
5894                                                 &stream->timing.dsc_cfg)) {
5895                                 stream->timing.flags.DSC = 1;
5896                                 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name);
5897                         }
5898                 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
5899                         timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
5900                         max_supported_bw_in_kbps = link_bandwidth_kbps;
5901                         dsc_max_supported_bw_in_kbps = link_bandwidth_kbps;
5902
5903                         if (timing_bw_in_kbps > max_supported_bw_in_kbps &&
5904                                         max_supported_bw_in_kbps > 0 &&
5905                                         dsc_max_supported_bw_in_kbps > 0)
5906                                 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5907                                                 dsc_caps,
5908                                                 &dsc_options,
5909                                                 dsc_max_supported_bw_in_kbps,
5910                                                 &stream->timing,
5911                                                 &stream->timing.dsc_cfg)) {
5912                                         stream->timing.flags.DSC = 1;
5913                                         DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n",
5914                                                                          __func__, drm_connector->name);
5915                                 }
5916                 }
5917         }
5918
5919         /* Overwrite the stream flag if DSC is enabled through debugfs */
5920         if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
5921                 stream->timing.flags.DSC = 1;
5922
5923         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
5924                 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
5925
5926         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
5927                 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
5928
5929         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
5930                 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
5931 }
5932
5933 static struct dc_stream_state *
5934 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
5935                        const struct drm_display_mode *drm_mode,
5936                        const struct dm_connector_state *dm_state,
5937                        const struct dc_stream_state *old_stream,
5938                        int requested_bpc)
5939 {
5940         struct drm_display_mode *preferred_mode = NULL;
5941         struct drm_connector *drm_connector;
5942         const struct drm_connector_state *con_state =
5943                 dm_state ? &dm_state->base : NULL;
5944         struct dc_stream_state *stream = NULL;
5945         struct drm_display_mode mode;
5946         struct drm_display_mode saved_mode;
5947         struct drm_display_mode *freesync_mode = NULL;
5948         bool native_mode_found = false;
5949         bool recalculate_timing = false;
5950         bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
5951         int mode_refresh;
5952         int preferred_refresh = 0;
5953         enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN;
5954         struct dsc_dec_dpcd_caps dsc_caps;
5955
5956         struct dc_sink *sink = NULL;
5957
5958         drm_mode_init(&mode, drm_mode);
5959         memset(&saved_mode, 0, sizeof(saved_mode));
5960
5961         if (aconnector == NULL) {
5962                 DRM_ERROR("aconnector is NULL!\n");
5963                 return stream;
5964         }
5965
5966         drm_connector = &aconnector->base;
5967
5968         if (!aconnector->dc_sink) {
5969                 sink = create_fake_sink(aconnector);
5970                 if (!sink)
5971                         return stream;
5972         } else {
5973                 sink = aconnector->dc_sink;
5974                 dc_sink_retain(sink);
5975         }
5976
5977         stream = dc_create_stream_for_sink(sink);
5978
5979         if (stream == NULL) {
5980                 DRM_ERROR("Failed to create stream for sink!\n");
5981                 goto finish;
5982         }
5983
5984         stream->dm_stream_context = aconnector;
5985
5986         stream->timing.flags.LTE_340MCSC_SCRAMBLE =
5987                 drm_connector->display_info.hdmi.scdc.scrambling.low_rates;
5988
5989         list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
5990                 /* Search for preferred mode */
5991                 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
5992                         native_mode_found = true;
5993                         break;
5994                 }
5995         }
5996         if (!native_mode_found)
5997                 preferred_mode = list_first_entry_or_null(
5998                                 &aconnector->base.modes,
5999                                 struct drm_display_mode,
6000                                 head);
6001
6002         mode_refresh = drm_mode_vrefresh(&mode);
6003
6004         if (preferred_mode == NULL) {
6005                 /*
6006                  * This may not be an error, the use case is when we have no
6007                  * usermode calls to reset and set mode upon hotplug. In this
6008                  * case, we call set mode ourselves to restore the previous mode
6009                  * and the modelist may not be filled in in time.
6010                  */
6011                 DRM_DEBUG_DRIVER("No preferred mode found\n");
6012         } else {
6013                 recalculate_timing = amdgpu_freesync_vid_mode &&
6014                                  is_freesync_video_mode(&mode, aconnector);
6015                 if (recalculate_timing) {
6016                         freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
6017                         drm_mode_copy(&saved_mode, &mode);
6018                         drm_mode_copy(&mode, freesync_mode);
6019                 } else {
6020                         decide_crtc_timing_for_drm_display_mode(
6021                                         &mode, preferred_mode, scale);
6022
6023                         preferred_refresh = drm_mode_vrefresh(preferred_mode);
6024                 }
6025         }
6026
6027         if (recalculate_timing)
6028                 drm_mode_set_crtcinfo(&saved_mode, 0);
6029         else if (!dm_state)
6030                 drm_mode_set_crtcinfo(&mode, 0);
6031
6032         /*
6033         * If scaling is enabled and refresh rate didn't change
6034         * we copy the vic and polarities of the old timings
6035         */
6036         if (!scale || mode_refresh != preferred_refresh)
6037                 fill_stream_properties_from_drm_display_mode(
6038                         stream, &mode, &aconnector->base, con_state, NULL,
6039                         requested_bpc);
6040         else
6041                 fill_stream_properties_from_drm_display_mode(
6042                         stream, &mode, &aconnector->base, con_state, old_stream,
6043                         requested_bpc);
6044
6045         if (aconnector->timing_changed) {
6046                 DC_LOG_DEBUG("%s: overriding timing for automated test, bpc %d, changing to %d\n",
6047                                 __func__,
6048                                 stream->timing.display_color_depth,
6049                                 aconnector->timing_requested->display_color_depth);
6050                 stream->timing = *aconnector->timing_requested;
6051         }
6052
6053         /* SST DSC determination policy */
6054         update_dsc_caps(aconnector, sink, stream, &dsc_caps);
6055         if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported)
6056                 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps);
6057
6058         update_stream_scaling_settings(&mode, dm_state, stream);
6059
6060         fill_audio_info(
6061                 &stream->audio_info,
6062                 drm_connector,
6063                 sink);
6064
6065         update_stream_signal(stream, sink);
6066
6067         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
6068                 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);
6069
6070         if (stream->link->psr_settings.psr_feature_enabled) {
6071                 //
6072                 // should decide stream support vsc sdp colorimetry capability
6073                 // before building vsc info packet
6074                 //
6075                 stream->use_vsc_sdp_for_colorimetry = false;
6076                 if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
6077                         stream->use_vsc_sdp_for_colorimetry =
6078                                 aconnector->dc_sink->is_vsc_sdp_colorimetry_supported;
6079                 } else {
6080                         if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
6081                                 stream->use_vsc_sdp_for_colorimetry = true;
6082                 }
6083                 if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22)
6084                         tf = TRANSFER_FUNC_GAMMA_22;
6085                 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);
6086                 aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
6087
6088         }
6089 finish:
6090         dc_sink_release(sink);
6091
6092         return stream;
6093 }
6094
6095 static enum drm_connector_status
6096 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
6097 {
6098         bool connected;
6099         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6100
6101         /*
6102          * Notes:
6103          * 1. This interface is NOT called in context of HPD irq.
6104          * 2. This interface *is called* in context of user-mode ioctl. Which
6105          * makes it a bad place for *any* MST-related activity.
6106          */
6107
6108         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
6109             !aconnector->fake_enable)
6110                 connected = (aconnector->dc_sink != NULL);
6111         else
6112                 connected = (aconnector->base.force == DRM_FORCE_ON ||
6113                                 aconnector->base.force == DRM_FORCE_ON_DIGITAL);
6114
6115         update_subconnector_property(aconnector);
6116
6117         return (connected ? connector_status_connected :
6118                         connector_status_disconnected);
6119 }
6120
6121 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
6122                                             struct drm_connector_state *connector_state,
6123                                             struct drm_property *property,
6124                                             uint64_t val)
6125 {
6126         struct drm_device *dev = connector->dev;
6127         struct amdgpu_device *adev = drm_to_adev(dev);
6128         struct dm_connector_state *dm_old_state =
6129                 to_dm_connector_state(connector->state);
6130         struct dm_connector_state *dm_new_state =
6131                 to_dm_connector_state(connector_state);
6132
6133         int ret = -EINVAL;
6134
6135         if (property == dev->mode_config.scaling_mode_property) {
6136                 enum amdgpu_rmx_type rmx_type;
6137
6138                 switch (val) {
6139                 case DRM_MODE_SCALE_CENTER:
6140                         rmx_type = RMX_CENTER;
6141                         break;
6142                 case DRM_MODE_SCALE_ASPECT:
6143                         rmx_type = RMX_ASPECT;
6144                         break;
6145                 case DRM_MODE_SCALE_FULLSCREEN:
6146                         rmx_type = RMX_FULL;
6147                         break;
6148                 case DRM_MODE_SCALE_NONE:
6149                 default:
6150                         rmx_type = RMX_OFF;
6151                         break;
6152                 }
6153
6154                 if (dm_old_state->scaling == rmx_type)
6155                         return 0;
6156
6157                 dm_new_state->scaling = rmx_type;
6158                 ret = 0;
6159         } else if (property == adev->mode_info.underscan_hborder_property) {
6160                 dm_new_state->underscan_hborder = val;
6161                 ret = 0;
6162         } else if (property == adev->mode_info.underscan_vborder_property) {
6163                 dm_new_state->underscan_vborder = val;
6164                 ret = 0;
6165         } else if (property == adev->mode_info.underscan_property) {
6166                 dm_new_state->underscan_enable = val;
6167                 ret = 0;
6168         } else if (property == adev->mode_info.abm_level_property) {
6169                 dm_new_state->abm_level = val;
6170                 ret = 0;
6171         }
6172
6173         return ret;
6174 }
6175
6176 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
6177                                             const struct drm_connector_state *state,
6178                                             struct drm_property *property,
6179                                             uint64_t *val)
6180 {
6181         struct drm_device *dev = connector->dev;
6182         struct amdgpu_device *adev = drm_to_adev(dev);
6183         struct dm_connector_state *dm_state =
6184                 to_dm_connector_state(state);
6185         int ret = -EINVAL;
6186
6187         if (property == dev->mode_config.scaling_mode_property) {
6188                 switch (dm_state->scaling) {
6189                 case RMX_CENTER:
6190                         *val = DRM_MODE_SCALE_CENTER;
6191                         break;
6192                 case RMX_ASPECT:
6193                         *val = DRM_MODE_SCALE_ASPECT;
6194                         break;
6195                 case RMX_FULL:
6196                         *val = DRM_MODE_SCALE_FULLSCREEN;
6197                         break;
6198                 case RMX_OFF:
6199                 default:
6200                         *val = DRM_MODE_SCALE_NONE;
6201                         break;
6202                 }
6203                 ret = 0;
6204         } else if (property == adev->mode_info.underscan_hborder_property) {
6205                 *val = dm_state->underscan_hborder;
6206                 ret = 0;
6207         } else if (property == adev->mode_info.underscan_vborder_property) {
6208                 *val = dm_state->underscan_vborder;
6209                 ret = 0;
6210         } else if (property == adev->mode_info.underscan_property) {
6211                 *val = dm_state->underscan_enable;
6212                 ret = 0;
6213         } else if (property == adev->mode_info.abm_level_property) {
6214                 *val = dm_state->abm_level;
6215                 ret = 0;
6216         }
6217
6218         return ret;
6219 }
6220
6221 static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
6222 {
6223         struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
6224
6225         drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
6226 }
6227
6228 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
6229 {
6230         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6231         const struct dc_link *link = aconnector->dc_link;
6232         struct amdgpu_device *adev = drm_to_adev(connector->dev);
6233         struct amdgpu_display_manager *dm = &adev->dm;
6234         int i;
6235
6236         /*
6237          * Call only if mst_mgr was initialized before since it's not done
6238          * for all connector types.
6239          */
6240         if (aconnector->mst_mgr.dev)
6241                 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);
6242
6243         for (i = 0; i < dm->num_of_edps; i++) {
6244                 if ((link == dm->backlight_link[i]) && dm->backlight_dev[i]) {
6245                         backlight_device_unregister(dm->backlight_dev[i]);
6246                         dm->backlight_dev[i] = NULL;
6247                 }
6248         }
6249
6250         if (aconnector->dc_em_sink)
6251                 dc_sink_release(aconnector->dc_em_sink);
6252         aconnector->dc_em_sink = NULL;
6253         if (aconnector->dc_sink)
6254                 dc_sink_release(aconnector->dc_sink);
6255         aconnector->dc_sink = NULL;
6256
6257         drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
6258         drm_connector_unregister(connector);
6259         drm_connector_cleanup(connector);
6260         if (aconnector->i2c) {
6261                 i2c_del_adapter(&aconnector->i2c->base);
6262                 kfree(aconnector->i2c);
6263         }
6264         kfree(aconnector->dm_dp_aux.aux.name);
6265
6266         kfree(connector);
6267 }
6268
6269 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
6270 {
6271         struct dm_connector_state *state =
6272                 to_dm_connector_state(connector->state);
6273
6274         if (connector->state)
6275                 __drm_atomic_helper_connector_destroy_state(connector->state);
6276
6277         kfree(state);
6278
6279         state = kzalloc(sizeof(*state), GFP_KERNEL);
6280
6281         if (state) {
6282                 state->scaling = RMX_OFF;
6283                 state->underscan_enable = false;
6284                 state->underscan_hborder = 0;
6285                 state->underscan_vborder = 0;
6286                 state->base.max_requested_bpc = 8;
6287                 state->vcpi_slots = 0;
6288                 state->pbn = 0;
6289
6290                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
6291                         state->abm_level = amdgpu_dm_abm_level;
6292
6293                 __drm_atomic_helper_connector_reset(connector, &state->base);
6294         }
6295 }
6296
6297 struct drm_connector_state *
6298 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
6299 {
6300         struct dm_connector_state *state =
6301                 to_dm_connector_state(connector->state);
6302
6303         struct dm_connector_state *new_state =
6304                         kmemdup(state, sizeof(*state), GFP_KERNEL);
6305
6306         if (!new_state)
6307                 return NULL;
6308
6309         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
6310
6311         new_state->freesync_capable = state->freesync_capable;
6312         new_state->abm_level = state->abm_level;
6313         new_state->scaling = state->scaling;
6314         new_state->underscan_enable = state->underscan_enable;
6315         new_state->underscan_hborder = state->underscan_hborder;
6316         new_state->underscan_vborder = state->underscan_vborder;
6317         new_state->vcpi_slots = state->vcpi_slots;
6318         new_state->pbn = state->pbn;
6319         return &new_state->base;
6320 }
6321
6322 static int
6323 amdgpu_dm_connector_late_register(struct drm_connector *connector)
6324 {
6325         struct amdgpu_dm_connector *amdgpu_dm_connector =
6326                 to_amdgpu_dm_connector(connector);
6327         int r;
6328
6329         if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
6330             (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
6331                 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
6332                 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
6333                 if (r)
6334                         return r;
6335         }
6336
6337 #if defined(CONFIG_DEBUG_FS)
6338         connector_debugfs_init(amdgpu_dm_connector);
6339 #endif
6340
6341         return 0;
6342 }
6343
6344 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
6345         .reset = amdgpu_dm_connector_funcs_reset,
6346         .detect = amdgpu_dm_connector_detect,
6347         .fill_modes = drm_helper_probe_single_connector_modes,
6348         .destroy = amdgpu_dm_connector_destroy,
6349         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
6350         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6351         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
6352         .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
6353         .late_register = amdgpu_dm_connector_late_register,
6354         .early_unregister = amdgpu_dm_connector_unregister
6355 };
6356
6357 static int get_modes(struct drm_connector *connector)
6358 {
6359         return amdgpu_dm_connector_get_modes(connector);
6360 }
6361
6362 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
6363 {
6364         struct dc_sink_init_data init_params = {
6365                         .link = aconnector->dc_link,
6366                         .sink_signal = SIGNAL_TYPE_VIRTUAL
6367         };
6368         struct edid *edid;
6369
6370         if (!aconnector->base.edid_blob_ptr) {
6371                 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
6372                                 aconnector->base.name);
6373
6374                 aconnector->base.force = DRM_FORCE_OFF;
6375                 return;
6376         }
6377
6378         edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
6379
6380         aconnector->edid = edid;
6381
6382         aconnector->dc_em_sink = dc_link_add_remote_sink(
6383                 aconnector->dc_link,
6384                 (uint8_t *)edid,
6385                 (edid->extensions + 1) * EDID_LENGTH,
6386                 &init_params);
6387
6388         if (aconnector->base.force == DRM_FORCE_ON) {
6389                 aconnector->dc_sink = aconnector->dc_link->local_sink ?
6390                 aconnector->dc_link->local_sink :
6391                 aconnector->dc_em_sink;
6392                 dc_sink_retain(aconnector->dc_sink);
6393         }
6394 }
6395
6396 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
6397 {
6398         struct dc_link *link = (struct dc_link *)aconnector->dc_link;
6399
6400         /*
6401          * In case of headless boot with force on for DP managed connector
6402          * Those settings have to be != 0 to get initial modeset
6403          */
6404         if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
6405                 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
6406                 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
6407         }
6408
6409         create_eml_sink(aconnector);
6410 }
6411
6412 static enum dc_status dm_validate_stream_and_context(struct dc *dc,
6413                                                 struct dc_stream_state *stream)
6414 {
6415         enum dc_status dc_result = DC_ERROR_UNEXPECTED;
6416         struct dc_plane_state *dc_plane_state = NULL;
6417         struct dc_state *dc_state = NULL;
6418
6419         if (!stream)
6420                 goto cleanup;
6421
6422         dc_plane_state = dc_create_plane_state(dc);
6423         if (!dc_plane_state)
6424                 goto cleanup;
6425
6426         dc_state = dc_create_state(dc);
6427         if (!dc_state)
6428                 goto cleanup;
6429
6430         /* populate stream to plane */
6431         dc_plane_state->src_rect.height  = stream->src.height;
6432         dc_plane_state->src_rect.width   = stream->src.width;
6433         dc_plane_state->dst_rect.height  = stream->src.height;
6434         dc_plane_state->dst_rect.width   = stream->src.width;
6435         dc_plane_state->clip_rect.height = stream->src.height;
6436         dc_plane_state->clip_rect.width  = stream->src.width;
6437         dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256;
6438         dc_plane_state->plane_size.surface_size.height = stream->src.height;
6439         dc_plane_state->plane_size.surface_size.width  = stream->src.width;
6440         dc_plane_state->plane_size.chroma_size.height  = stream->src.height;
6441         dc_plane_state->plane_size.chroma_size.width   = stream->src.width;
6442         dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
6443         dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN;
6444         dc_plane_state->rotation = ROTATION_ANGLE_0;
6445         dc_plane_state->is_tiling_rotated = false;
6446         dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL;
6447
6448         dc_result = dc_validate_stream(dc, stream);
6449         if (dc_result == DC_OK)
6450                 dc_result = dc_validate_plane(dc, dc_plane_state);
6451
6452         if (dc_result == DC_OK)
6453                 dc_result = dc_add_stream_to_ctx(dc, dc_state, stream);
6454
6455         if (dc_result == DC_OK && !dc_add_plane_to_context(
6456                                                 dc,
6457                                                 stream,
6458                                                 dc_plane_state,
6459                                                 dc_state))
6460                 dc_result = DC_FAIL_ATTACH_SURFACES;
6461
6462         if (dc_result == DC_OK)
6463                 dc_result = dc_validate_global_state(dc, dc_state, true);
6464
6465 cleanup:
6466         if (dc_state)
6467                 dc_release_state(dc_state);
6468
6469         if (dc_plane_state)
6470                 dc_plane_state_release(dc_plane_state);
6471
6472         return dc_result;
6473 }
6474
6475 struct dc_stream_state *
6476 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6477                                 const struct drm_display_mode *drm_mode,
6478                                 const struct dm_connector_state *dm_state,
6479                                 const struct dc_stream_state *old_stream)
6480 {
6481         struct drm_connector *connector = &aconnector->base;
6482         struct amdgpu_device *adev = drm_to_adev(connector->dev);
6483         struct dc_stream_state *stream;
6484         const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL;
6485         int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8;
6486         enum dc_status dc_result = DC_OK;
6487
6488         do {
6489                 stream = create_stream_for_sink(aconnector, drm_mode,
6490                                                 dm_state, old_stream,
6491                                                 requested_bpc);
6492                 if (stream == NULL) {
6493                         DRM_ERROR("Failed to create stream for sink!\n");
6494                         break;
6495                 }
6496
6497                 dc_result = dc_validate_stream(adev->dm.dc, stream);
6498                 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
6499                         dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream);
6500
6501                 if (dc_result == DC_OK)
6502                         dc_result = dm_validate_stream_and_context(adev->dm.dc, stream);
6503
6504                 if (dc_result != DC_OK) {
6505                         DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",
6506                                       drm_mode->hdisplay,
6507                                       drm_mode->vdisplay,
6508                                       drm_mode->clock,
6509                                       dc_result,
6510                                       dc_status_to_str(dc_result));
6511
6512                         dc_stream_release(stream);
6513                         stream = NULL;
6514                         requested_bpc -= 2; /* lower bpc to retry validation */
6515                 }
6516
6517         } while (stream == NULL && requested_bpc >= 6);
6518
6519         if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) {
6520                 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n");
6521
6522                 aconnector->force_yuv420_output = true;
6523                 stream = create_validate_stream_for_sink(aconnector, drm_mode,
6524                                                 dm_state, old_stream);
6525                 aconnector->force_yuv420_output = false;
6526         }
6527
6528         return stream;
6529 }
6530
6531 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
6532                                    struct drm_display_mode *mode)
6533 {
6534         int result = MODE_ERROR;
6535         struct dc_sink *dc_sink;
6536         /* TODO: Unhardcode stream count */
6537         struct dc_stream_state *stream;
6538         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6539
6540         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
6541                         (mode->flags & DRM_MODE_FLAG_DBLSCAN))
6542                 return result;
6543
6544         /*
6545          * Only run this the first time mode_valid is called to initilialize
6546          * EDID mgmt
6547          */
6548         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
6549                 !aconnector->dc_em_sink)
6550                 handle_edid_mgmt(aconnector);
6551
6552         dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
6553
6554         if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL &&
6555                                 aconnector->base.force != DRM_FORCE_ON) {
6556                 DRM_ERROR("dc_sink is NULL!\n");
6557                 goto fail;
6558         }
6559
6560         stream = create_validate_stream_for_sink(aconnector, mode, NULL, NULL);
6561         if (stream) {
6562                 dc_stream_release(stream);
6563                 result = MODE_OK;
6564         }
6565
6566 fail:
6567         /* TODO: error handling*/
6568         return result;
6569 }
6570
6571 static int fill_hdr_info_packet(const struct drm_connector_state *state,
6572                                 struct dc_info_packet *out)
6573 {
6574         struct hdmi_drm_infoframe frame;
6575         unsigned char buf[30]; /* 26 + 4 */
6576         ssize_t len;
6577         int ret, i;
6578
6579         memset(out, 0, sizeof(*out));
6580
6581         if (!state->hdr_output_metadata)
6582                 return 0;
6583
6584         ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
6585         if (ret)
6586                 return ret;
6587
6588         len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
6589         if (len < 0)
6590                 return (int)len;
6591
6592         /* Static metadata is a fixed 26 bytes + 4 byte header. */
6593         if (len != 30)
6594                 return -EINVAL;
6595
6596         /* Prepare the infopacket for DC. */
6597         switch (state->connector->connector_type) {
6598         case DRM_MODE_CONNECTOR_HDMIA:
6599                 out->hb0 = 0x87; /* type */
6600                 out->hb1 = 0x01; /* version */
6601                 out->hb2 = 0x1A; /* length */
6602                 out->sb[0] = buf[3]; /* checksum */
6603                 i = 1;
6604                 break;
6605
6606         case DRM_MODE_CONNECTOR_DisplayPort:
6607         case DRM_MODE_CONNECTOR_eDP:
6608                 out->hb0 = 0x00; /* sdp id, zero */
6609                 out->hb1 = 0x87; /* type */
6610                 out->hb2 = 0x1D; /* payload len - 1 */
6611                 out->hb3 = (0x13 << 2); /* sdp version */
6612                 out->sb[0] = 0x01; /* version */
6613                 out->sb[1] = 0x1A; /* length */
6614                 i = 2;
6615                 break;
6616
6617         default:
6618                 return -EINVAL;
6619         }
6620
6621         memcpy(&out->sb[i], &buf[4], 26);
6622         out->valid = true;
6623
6624         print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
6625                        sizeof(out->sb), false);
6626
6627         return 0;
6628 }
6629
6630 static int
6631 amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
6632                                  struct drm_atomic_state *state)
6633 {
6634         struct drm_connector_state *new_con_state =
6635                 drm_atomic_get_new_connector_state(state, conn);
6636         struct drm_connector_state *old_con_state =
6637                 drm_atomic_get_old_connector_state(state, conn);
6638         struct drm_crtc *crtc = new_con_state->crtc;
6639         struct drm_crtc_state *new_crtc_state;
6640         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn);
6641         int ret;
6642
6643         trace_amdgpu_dm_connector_atomic_check(new_con_state);
6644
6645         if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
6646                 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr);
6647                 if (ret < 0)
6648                         return ret;
6649         }
6650
6651         if (!crtc)
6652                 return 0;
6653
6654         if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) {
6655                 struct dc_info_packet hdr_infopacket;
6656
6657                 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
6658                 if (ret)
6659                         return ret;
6660
6661                 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6662                 if (IS_ERR(new_crtc_state))
6663                         return PTR_ERR(new_crtc_state);
6664
6665                 /*
6666                  * DC considers the stream backends changed if the
6667                  * static metadata changes. Forcing the modeset also
6668                  * gives a simple way for userspace to switch from
6669                  * 8bpc to 10bpc when setting the metadata to enter
6670                  * or exit HDR.
6671                  *
6672                  * Changing the static metadata after it's been
6673                  * set is permissible, however. So only force a
6674                  * modeset if we're entering or exiting HDR.
6675                  */
6676                 new_crtc_state->mode_changed =
6677                         !old_con_state->hdr_output_metadata ||
6678                         !new_con_state->hdr_output_metadata;
6679         }
6680
6681         return 0;
6682 }
6683
6684 static const struct drm_connector_helper_funcs
6685 amdgpu_dm_connector_helper_funcs = {
6686         /*
6687          * If hotplugging a second bigger display in FB Con mode, bigger resolution
6688          * modes will be filtered by drm_mode_validate_size(), and those modes
6689          * are missing after user start lightdm. So we need to renew modes list.
6690          * in get_modes call back, not just return the modes count
6691          */
6692         .get_modes = get_modes,
6693         .mode_valid = amdgpu_dm_connector_mode_valid,
6694         .atomic_check = amdgpu_dm_connector_atomic_check,
6695 };
6696
6697 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
6698 {
6699
6700 }
6701
6702 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth)
6703 {
6704         switch (display_color_depth) {
6705         case COLOR_DEPTH_666:
6706                 return 6;
6707         case COLOR_DEPTH_888:
6708                 return 8;
6709         case COLOR_DEPTH_101010:
6710                 return 10;
6711         case COLOR_DEPTH_121212:
6712                 return 12;
6713         case COLOR_DEPTH_141414:
6714                 return 14;
6715         case COLOR_DEPTH_161616:
6716                 return 16;
6717         default:
6718                 break;
6719         }
6720         return 0;
6721 }
6722
6723 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
6724                                           struct drm_crtc_state *crtc_state,
6725                                           struct drm_connector_state *conn_state)
6726 {
6727         struct drm_atomic_state *state = crtc_state->state;
6728         struct drm_connector *connector = conn_state->connector;
6729         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6730         struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state);
6731         const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
6732         struct drm_dp_mst_topology_mgr *mst_mgr;
6733         struct drm_dp_mst_port *mst_port;
6734         struct drm_dp_mst_topology_state *mst_state;
6735         enum dc_color_depth color_depth;
6736         int clock, bpp = 0;
6737         bool is_y420 = false;
6738
6739         if (!aconnector->mst_output_port || !aconnector->dc_sink)
6740                 return 0;
6741
6742         mst_port = aconnector->mst_output_port;
6743         mst_mgr = &aconnector->mst_root->mst_mgr;
6744
6745         if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
6746                 return 0;
6747
6748         mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr);
6749         if (IS_ERR(mst_state))
6750                 return PTR_ERR(mst_state);
6751
6752         if (!mst_state->pbn_div)
6753                 mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link);
6754
6755         if (!state->duplicated) {
6756                 int max_bpc = conn_state->max_requested_bpc;
6757                 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
6758                           aconnector->force_yuv420_output;
6759                 color_depth = convert_color_depth_from_display_info(connector,
6760                                                                     is_y420,
6761                                                                     max_bpc);
6762                 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
6763                 clock = adjusted_mode->clock;
6764                 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
6765         }
6766
6767         dm_new_connector_state->vcpi_slots =
6768                 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port,
6769                                               dm_new_connector_state->pbn);
6770         if (dm_new_connector_state->vcpi_slots < 0) {
6771                 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
6772                 return dm_new_connector_state->vcpi_slots;
6773         }
6774         return 0;
6775 }
6776
6777 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
6778         .disable = dm_encoder_helper_disable,
6779         .atomic_check = dm_encoder_helper_atomic_check
6780 };
6781
6782 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
6783                                             struct dc_state *dc_state,
6784                                             struct dsc_mst_fairness_vars *vars)
6785 {
6786         struct dc_stream_state *stream = NULL;
6787         struct drm_connector *connector;
6788         struct drm_connector_state *new_con_state;
6789         struct amdgpu_dm_connector *aconnector;
6790         struct dm_connector_state *dm_conn_state;
6791         int i, j, ret;
6792         int vcpi, pbn_div, pbn, slot_num = 0;
6793
6794         for_each_new_connector_in_state(state, connector, new_con_state, i) {
6795
6796                 aconnector = to_amdgpu_dm_connector(connector);
6797
6798                 if (!aconnector->mst_output_port)
6799                         continue;
6800
6801                 if (!new_con_state || !new_con_state->crtc)
6802                         continue;
6803
6804                 dm_conn_state = to_dm_connector_state(new_con_state);
6805
6806                 for (j = 0; j < dc_state->stream_count; j++) {
6807                         stream = dc_state->streams[j];
6808                         if (!stream)
6809                                 continue;
6810
6811                         if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector)
6812                                 break;
6813
6814                         stream = NULL;
6815                 }
6816
6817                 if (!stream)
6818                         continue;
6819
6820                 pbn_div = dm_mst_get_pbn_divider(stream->link);
6821                 /* pbn is calculated by compute_mst_dsc_configs_for_state*/
6822                 for (j = 0; j < dc_state->stream_count; j++) {
6823                         if (vars[j].aconnector == aconnector) {
6824                                 pbn = vars[j].pbn;
6825                                 break;
6826                         }
6827                 }
6828
6829                 if (j == dc_state->stream_count)
6830                         continue;
6831
6832                 slot_num = DIV_ROUND_UP(pbn, pbn_div);
6833
6834                 if (stream->timing.flags.DSC != 1) {
6835                         dm_conn_state->pbn = pbn;
6836                         dm_conn_state->vcpi_slots = slot_num;
6837
6838                         ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port,
6839                                                            dm_conn_state->pbn, false);
6840                         if (ret < 0)
6841                                 return ret;
6842
6843                         continue;
6844                 }
6845
6846                 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true);
6847                 if (vcpi < 0)
6848                         return vcpi;
6849
6850                 dm_conn_state->pbn = pbn;
6851                 dm_conn_state->vcpi_slots = vcpi;
6852         }
6853         return 0;
6854 }
6855
6856 static int to_drm_connector_type(enum signal_type st)
6857 {
6858         switch (st) {
6859         case SIGNAL_TYPE_HDMI_TYPE_A:
6860                 return DRM_MODE_CONNECTOR_HDMIA;
6861         case SIGNAL_TYPE_EDP:
6862                 return DRM_MODE_CONNECTOR_eDP;
6863         case SIGNAL_TYPE_LVDS:
6864                 return DRM_MODE_CONNECTOR_LVDS;
6865         case SIGNAL_TYPE_RGB:
6866                 return DRM_MODE_CONNECTOR_VGA;
6867         case SIGNAL_TYPE_DISPLAY_PORT:
6868         case SIGNAL_TYPE_DISPLAY_PORT_MST:
6869                 return DRM_MODE_CONNECTOR_DisplayPort;
6870         case SIGNAL_TYPE_DVI_DUAL_LINK:
6871         case SIGNAL_TYPE_DVI_SINGLE_LINK:
6872                 return DRM_MODE_CONNECTOR_DVID;
6873         case SIGNAL_TYPE_VIRTUAL:
6874                 return DRM_MODE_CONNECTOR_VIRTUAL;
6875
6876         default:
6877                 return DRM_MODE_CONNECTOR_Unknown;
6878         }
6879 }
6880
6881 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
6882 {
6883         struct drm_encoder *encoder;
6884
6885         /* There is only one encoder per connector */
6886         drm_connector_for_each_possible_encoder(connector, encoder)
6887                 return encoder;
6888
6889         return NULL;
6890 }
6891
6892 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
6893 {
6894         struct drm_encoder *encoder;
6895         struct amdgpu_encoder *amdgpu_encoder;
6896
6897         encoder = amdgpu_dm_connector_to_encoder(connector);
6898
6899         if (encoder == NULL)
6900                 return;
6901
6902         amdgpu_encoder = to_amdgpu_encoder(encoder);
6903
6904         amdgpu_encoder->native_mode.clock = 0;
6905
6906         if (!list_empty(&connector->probed_modes)) {
6907                 struct drm_display_mode *preferred_mode = NULL;
6908
6909                 list_for_each_entry(preferred_mode,
6910                                     &connector->probed_modes,
6911                                     head) {
6912                         if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
6913                                 amdgpu_encoder->native_mode = *preferred_mode;
6914
6915                         break;
6916                 }
6917
6918         }
6919 }
6920
6921 static struct drm_display_mode *
6922 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
6923                              char *name,
6924                              int hdisplay, int vdisplay)
6925 {
6926         struct drm_device *dev = encoder->dev;
6927         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
6928         struct drm_display_mode *mode = NULL;
6929         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
6930
6931         mode = drm_mode_duplicate(dev, native_mode);
6932
6933         if (mode == NULL)
6934                 return NULL;
6935
6936         mode->hdisplay = hdisplay;
6937         mode->vdisplay = vdisplay;
6938         mode->type &= ~DRM_MODE_TYPE_PREFERRED;
6939         strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
6940
6941         return mode;
6942
6943 }
6944
6945 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
6946                                                  struct drm_connector *connector)
6947 {
6948         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
6949         struct drm_display_mode *mode = NULL;
6950         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
6951         struct amdgpu_dm_connector *amdgpu_dm_connector =
6952                                 to_amdgpu_dm_connector(connector);
6953         int i;
6954         int n;
6955         struct mode_size {
6956                 char name[DRM_DISPLAY_MODE_LEN];
6957                 int w;
6958                 int h;
6959         } common_modes[] = {
6960                 {  "640x480",  640,  480},
6961                 {  "800x600",  800,  600},
6962                 { "1024x768", 1024,  768},
6963                 { "1280x720", 1280,  720},
6964                 { "1280x800", 1280,  800},
6965                 {"1280x1024", 1280, 1024},
6966                 { "1440x900", 1440,  900},
6967                 {"1680x1050", 1680, 1050},
6968                 {"1600x1200", 1600, 1200},
6969                 {"1920x1080", 1920, 1080},
6970                 {"1920x1200", 1920, 1200}
6971         };
6972
6973         n = ARRAY_SIZE(common_modes);
6974
6975         for (i = 0; i < n; i++) {
6976                 struct drm_display_mode *curmode = NULL;
6977                 bool mode_existed = false;
6978
6979                 if (common_modes[i].w > native_mode->hdisplay ||
6980                     common_modes[i].h > native_mode->vdisplay ||
6981                    (common_modes[i].w == native_mode->hdisplay &&
6982                     common_modes[i].h == native_mode->vdisplay))
6983                         continue;
6984
6985                 list_for_each_entry(curmode, &connector->probed_modes, head) {
6986                         if (common_modes[i].w == curmode->hdisplay &&
6987                             common_modes[i].h == curmode->vdisplay) {
6988                                 mode_existed = true;
6989                                 break;
6990                         }
6991                 }
6992
6993                 if (mode_existed)
6994                         continue;
6995
6996                 mode = amdgpu_dm_create_common_mode(encoder,
6997                                 common_modes[i].name, common_modes[i].w,
6998                                 common_modes[i].h);
6999                 if (!mode)
7000                         continue;
7001
7002                 drm_mode_probed_add(connector, mode);
7003                 amdgpu_dm_connector->num_modes++;
7004         }
7005 }
7006
7007 static void amdgpu_set_panel_orientation(struct drm_connector *connector)
7008 {
7009         struct drm_encoder *encoder;
7010         struct amdgpu_encoder *amdgpu_encoder;
7011         const struct drm_display_mode *native_mode;
7012
7013         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
7014             connector->connector_type != DRM_MODE_CONNECTOR_LVDS)
7015                 return;
7016
7017         mutex_lock(&connector->dev->mode_config.mutex);
7018         amdgpu_dm_connector_get_modes(connector);
7019         mutex_unlock(&connector->dev->mode_config.mutex);
7020
7021         encoder = amdgpu_dm_connector_to_encoder(connector);
7022         if (!encoder)
7023                 return;
7024
7025         amdgpu_encoder = to_amdgpu_encoder(encoder);
7026
7027         native_mode = &amdgpu_encoder->native_mode;
7028         if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0)
7029                 return;
7030
7031         drm_connector_set_panel_orientation_with_quirk(connector,
7032                                                        DRM_MODE_PANEL_ORIENTATION_UNKNOWN,
7033                                                        native_mode->hdisplay,
7034                                                        native_mode->vdisplay);
7035 }
7036
7037 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
7038                                               struct edid *edid)
7039 {
7040         struct amdgpu_dm_connector *amdgpu_dm_connector =
7041                         to_amdgpu_dm_connector(connector);
7042
7043         if (edid) {
7044                 /* empty probed_modes */
7045                 INIT_LIST_HEAD(&connector->probed_modes);
7046                 amdgpu_dm_connector->num_modes =
7047                                 drm_add_edid_modes(connector, edid);
7048
7049                 /* sorting the probed modes before calling function
7050                  * amdgpu_dm_get_native_mode() since EDID can have
7051                  * more than one preferred mode. The modes that are
7052                  * later in the probed mode list could be of higher
7053                  * and preferred resolution. For example, 3840x2160
7054                  * resolution in base EDID preferred timing and 4096x2160
7055                  * preferred resolution in DID extension block later.
7056                  */
7057                 drm_mode_sort(&connector->probed_modes);
7058                 amdgpu_dm_get_native_mode(connector);
7059
7060                 /* Freesync capabilities are reset by calling
7061                  * drm_add_edid_modes() and need to be
7062                  * restored here.
7063                  */
7064                 amdgpu_dm_update_freesync_caps(connector, edid);
7065         } else {
7066                 amdgpu_dm_connector->num_modes = 0;
7067         }
7068 }
7069
7070 static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector,
7071                               struct drm_display_mode *mode)
7072 {
7073         struct drm_display_mode *m;
7074
7075         list_for_each_entry (m, &aconnector->base.probed_modes, head) {
7076                 if (drm_mode_equal(m, mode))
7077                         return true;
7078         }
7079
7080         return false;
7081 }
7082
7083 static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)
7084 {
7085         const struct drm_display_mode *m;
7086         struct drm_display_mode *new_mode;
7087         uint i;
7088         u32 new_modes_count = 0;
7089
7090         /* Standard FPS values
7091          *
7092          * 23.976       - TV/NTSC
7093          * 24           - Cinema
7094          * 25           - TV/PAL
7095          * 29.97        - TV/NTSC
7096          * 30           - TV/NTSC
7097          * 48           - Cinema HFR
7098          * 50           - TV/PAL
7099          * 60           - Commonly used
7100          * 48,72,96,120 - Multiples of 24
7101          */
7102         static const u32 common_rates[] = {
7103                 23976, 24000, 25000, 29970, 30000,
7104                 48000, 50000, 60000, 72000, 96000, 120000
7105         };
7106
7107         /*
7108          * Find mode with highest refresh rate with the same resolution
7109          * as the preferred mode. Some monitors report a preferred mode
7110          * with lower resolution than the highest refresh rate supported.
7111          */
7112
7113         m = get_highest_refresh_rate_mode(aconnector, true);
7114         if (!m)
7115                 return 0;
7116
7117         for (i = 0; i < ARRAY_SIZE(common_rates); i++) {
7118                 u64 target_vtotal, target_vtotal_diff;
7119                 u64 num, den;
7120
7121                 if (drm_mode_vrefresh(m) * 1000 < common_rates[i])
7122                         continue;
7123
7124                 if (common_rates[i] < aconnector->min_vfreq * 1000 ||
7125                     common_rates[i] > aconnector->max_vfreq * 1000)
7126                         continue;
7127
7128                 num = (unsigned long long)m->clock * 1000 * 1000;
7129                 den = common_rates[i] * (unsigned long long)m->htotal;
7130                 target_vtotal = div_u64(num, den);
7131                 target_vtotal_diff = target_vtotal - m->vtotal;
7132
7133                 /* Check for illegal modes */
7134                 if (m->vsync_start + target_vtotal_diff < m->vdisplay ||
7135                     m->vsync_end + target_vtotal_diff < m->vsync_start ||
7136                     m->vtotal + target_vtotal_diff < m->vsync_end)
7137                         continue;
7138
7139                 new_mode = drm_mode_duplicate(aconnector->base.dev, m);
7140                 if (!new_mode)
7141                         goto out;
7142
7143                 new_mode->vtotal += (u16)target_vtotal_diff;
7144                 new_mode->vsync_start += (u16)target_vtotal_diff;
7145                 new_mode->vsync_end += (u16)target_vtotal_diff;
7146                 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7147                 new_mode->type |= DRM_MODE_TYPE_DRIVER;
7148
7149                 if (!is_duplicate_mode(aconnector, new_mode)) {
7150                         drm_mode_probed_add(&aconnector->base, new_mode);
7151                         new_modes_count += 1;
7152                 } else
7153                         drm_mode_destroy(aconnector->base.dev, new_mode);
7154         }
7155  out:
7156         return new_modes_count;
7157 }
7158
7159 static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector,
7160                                                    struct edid *edid)
7161 {
7162         struct amdgpu_dm_connector *amdgpu_dm_connector =
7163                 to_amdgpu_dm_connector(connector);
7164
7165         if (!(amdgpu_freesync_vid_mode && edid))
7166                 return;
7167
7168         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
7169                 amdgpu_dm_connector->num_modes +=
7170                         add_fs_modes(amdgpu_dm_connector);
7171 }
7172
7173 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
7174 {
7175         struct amdgpu_dm_connector *amdgpu_dm_connector =
7176                         to_amdgpu_dm_connector(connector);
7177         struct drm_encoder *encoder;
7178         struct edid *edid = amdgpu_dm_connector->edid;
7179         struct dc_link_settings *verified_link_cap =
7180                         &amdgpu_dm_connector->dc_link->verified_link_cap;
7181
7182         encoder = amdgpu_dm_connector_to_encoder(connector);
7183
7184         if (!drm_edid_is_valid(edid)) {
7185                 amdgpu_dm_connector->num_modes =
7186                                 drm_add_modes_noedid(connector, 640, 480);
7187                 if (link_dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING)
7188                         amdgpu_dm_connector->num_modes +=
7189                                 drm_add_modes_noedid(connector, 1920, 1080);
7190         } else {
7191                 amdgpu_dm_connector_ddc_get_modes(connector, edid);
7192                 amdgpu_dm_connector_add_common_modes(encoder, connector);
7193                 amdgpu_dm_connector_add_freesync_modes(connector, edid);
7194         }
7195         amdgpu_dm_fbc_init(connector);
7196
7197         return amdgpu_dm_connector->num_modes;
7198 }
7199
7200 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
7201                                      struct amdgpu_dm_connector *aconnector,
7202                                      int connector_type,
7203                                      struct dc_link *link,
7204                                      int link_index)
7205 {
7206         struct amdgpu_device *adev = drm_to_adev(dm->ddev);
7207
7208         /*
7209          * Some of the properties below require access to state, like bpc.
7210          * Allocate some default initial connector state with our reset helper.
7211          */
7212         if (aconnector->base.funcs->reset)
7213                 aconnector->base.funcs->reset(&aconnector->base);
7214
7215         aconnector->connector_id = link_index;
7216         aconnector->dc_link = link;
7217         aconnector->base.interlace_allowed = false;
7218         aconnector->base.doublescan_allowed = false;
7219         aconnector->base.stereo_allowed = false;
7220         aconnector->base.dpms = DRM_MODE_DPMS_OFF;
7221         aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
7222         aconnector->audio_inst = -1;
7223         aconnector->pack_sdp_v1_3 = false;
7224         aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE;
7225         memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info));
7226         mutex_init(&aconnector->hpd_lock);
7227
7228         /*
7229          * configure support HPD hot plug connector_>polled default value is 0
7230          * which means HPD hot plug not supported
7231          */
7232         switch (connector_type) {
7233         case DRM_MODE_CONNECTOR_HDMIA:
7234                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7235                 aconnector->base.ycbcr_420_allowed =
7236                         link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
7237                 break;
7238         case DRM_MODE_CONNECTOR_DisplayPort:
7239                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7240                 link->link_enc = link_enc_cfg_get_link_enc(link);
7241                 ASSERT(link->link_enc);
7242                 if (link->link_enc)
7243                         aconnector->base.ycbcr_420_allowed =
7244                         link->link_enc->features.dp_ycbcr420_supported ? true : false;
7245                 break;
7246         case DRM_MODE_CONNECTOR_DVID:
7247                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7248                 break;
7249         default:
7250                 break;
7251         }
7252
7253         drm_object_attach_property(&aconnector->base.base,
7254                                 dm->ddev->mode_config.scaling_mode_property,
7255                                 DRM_MODE_SCALE_NONE);
7256
7257         drm_object_attach_property(&aconnector->base.base,
7258                                 adev->mode_info.underscan_property,
7259                                 UNDERSCAN_OFF);
7260         drm_object_attach_property(&aconnector->base.base,
7261                                 adev->mode_info.underscan_hborder_property,
7262                                 0);
7263         drm_object_attach_property(&aconnector->base.base,
7264                                 adev->mode_info.underscan_vborder_property,
7265                                 0);
7266
7267         if (!aconnector->mst_root)
7268                 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
7269
7270         /* This defaults to the max in the range, but we want 8bpc for non-edp. */
7271         aconnector->base.state->max_bpc = 16;
7272         aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
7273
7274         if (connector_type == DRM_MODE_CONNECTOR_eDP &&
7275             (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) {
7276                 drm_object_attach_property(&aconnector->base.base,
7277                                 adev->mode_info.abm_level_property, 0);
7278         }
7279
7280         if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
7281             connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
7282             connector_type == DRM_MODE_CONNECTOR_eDP) {
7283                 drm_connector_attach_hdr_output_metadata_property(&aconnector->base);
7284
7285                 if (!aconnector->mst_root)
7286                         drm_connector_attach_vrr_capable_property(&aconnector->base);
7287
7288                 if (adev->dm.hdcp_workqueue)
7289                         drm_connector_attach_content_protection_property(&aconnector->base, true);
7290         }
7291 }
7292
7293 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
7294                               struct i2c_msg *msgs, int num)
7295 {
7296         struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
7297         struct ddc_service *ddc_service = i2c->ddc_service;
7298         struct i2c_command cmd;
7299         int i;
7300         int result = -EIO;
7301
7302         cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
7303
7304         if (!cmd.payloads)
7305                 return result;
7306
7307         cmd.number_of_payloads = num;
7308         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
7309         cmd.speed = 100;
7310
7311         for (i = 0; i < num; i++) {
7312                 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
7313                 cmd.payloads[i].address = msgs[i].addr;
7314                 cmd.payloads[i].length = msgs[i].len;
7315                 cmd.payloads[i].data = msgs[i].buf;
7316         }
7317
7318         if (dc_submit_i2c(
7319                         ddc_service->ctx->dc,
7320                         ddc_service->link->link_index,
7321                         &cmd))
7322                 result = num;
7323
7324         kfree(cmd.payloads);
7325         return result;
7326 }
7327
7328 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
7329 {
7330         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
7331 }
7332
7333 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
7334         .master_xfer = amdgpu_dm_i2c_xfer,
7335         .functionality = amdgpu_dm_i2c_func,
7336 };
7337
7338 static struct amdgpu_i2c_adapter *
7339 create_i2c(struct ddc_service *ddc_service,
7340            int link_index,
7341            int *res)
7342 {
7343         struct amdgpu_device *adev = ddc_service->ctx->driver_context;
7344         struct amdgpu_i2c_adapter *i2c;
7345
7346         i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
7347         if (!i2c)
7348                 return NULL;
7349         i2c->base.owner = THIS_MODULE;
7350         i2c->base.class = I2C_CLASS_DDC;
7351         i2c->base.dev.parent = &adev->pdev->dev;
7352         i2c->base.algo = &amdgpu_dm_i2c_algo;
7353         snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
7354         i2c_set_adapdata(&i2c->base, i2c);
7355         i2c->ddc_service = ddc_service;
7356
7357         return i2c;
7358 }
7359
7360
7361 /*
7362  * Note: this function assumes that dc_link_detect() was called for the
7363  * dc_link which will be represented by this aconnector.
7364  */
7365 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
7366                                     struct amdgpu_dm_connector *aconnector,
7367                                     u32 link_index,
7368                                     struct amdgpu_encoder *aencoder)
7369 {
7370         int res = 0;
7371         int connector_type;
7372         struct dc *dc = dm->dc;
7373         struct dc_link *link = dc_get_link_at_index(dc, link_index);
7374         struct amdgpu_i2c_adapter *i2c;
7375
7376         link->priv = aconnector;
7377
7378         DRM_DEBUG_DRIVER("%s()\n", __func__);
7379
7380         i2c = create_i2c(link->ddc, link->link_index, &res);
7381         if (!i2c) {
7382                 DRM_ERROR("Failed to create i2c adapter data\n");
7383                 return -ENOMEM;
7384         }
7385
7386         aconnector->i2c = i2c;
7387         res = i2c_add_adapter(&i2c->base);
7388
7389         if (res) {
7390                 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
7391                 goto out_free;
7392         }
7393
7394         connector_type = to_drm_connector_type(link->connector_signal);
7395
7396         res = drm_connector_init_with_ddc(
7397                         dm->ddev,
7398                         &aconnector->base,
7399                         &amdgpu_dm_connector_funcs,
7400                         connector_type,
7401                         &i2c->base);
7402
7403         if (res) {
7404                 DRM_ERROR("connector_init failed\n");
7405                 aconnector->connector_id = -1;
7406                 goto out_free;
7407         }
7408
7409         drm_connector_helper_add(
7410                         &aconnector->base,
7411                         &amdgpu_dm_connector_helper_funcs);
7412
7413         amdgpu_dm_connector_init_helper(
7414                 dm,
7415                 aconnector,
7416                 connector_type,
7417                 link,
7418                 link_index);
7419
7420         drm_connector_attach_encoder(
7421                 &aconnector->base, &aencoder->base);
7422
7423         if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
7424                 || connector_type == DRM_MODE_CONNECTOR_eDP)
7425                 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);
7426
7427 out_free:
7428         if (res) {
7429                 kfree(i2c);
7430                 aconnector->i2c = NULL;
7431         }
7432         return res;
7433 }
7434
7435 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
7436 {
7437         switch (adev->mode_info.num_crtc) {
7438         case 1:
7439                 return 0x1;
7440         case 2:
7441                 return 0x3;
7442         case 3:
7443                 return 0x7;
7444         case 4:
7445                 return 0xf;
7446         case 5:
7447                 return 0x1f;
7448         case 6:
7449         default:
7450                 return 0x3f;
7451         }
7452 }
7453
7454 static int amdgpu_dm_encoder_init(struct drm_device *dev,
7455                                   struct amdgpu_encoder *aencoder,
7456                                   uint32_t link_index)
7457 {
7458         struct amdgpu_device *adev = drm_to_adev(dev);
7459
7460         int res = drm_encoder_init(dev,
7461                                    &aencoder->base,
7462                                    &amdgpu_dm_encoder_funcs,
7463                                    DRM_MODE_ENCODER_TMDS,
7464                                    NULL);
7465
7466         aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
7467
7468         if (!res)
7469                 aencoder->encoder_id = link_index;
7470         else
7471                 aencoder->encoder_id = -1;
7472
7473         drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
7474
7475         return res;
7476 }
7477
7478 static void manage_dm_interrupts(struct amdgpu_device *adev,
7479                                  struct amdgpu_crtc *acrtc,
7480                                  bool enable)
7481 {
7482         /*
7483          * We have no guarantee that the frontend index maps to the same
7484          * backend index - some even map to more than one.
7485          *
7486          * TODO: Use a different interrupt or check DC itself for the mapping.
7487          */
7488         int irq_type =
7489                 amdgpu_display_crtc_idx_to_irq_type(
7490                         adev,
7491                         acrtc->crtc_id);
7492
7493         if (enable) {
7494                 drm_crtc_vblank_on(&acrtc->base);
7495                 amdgpu_irq_get(
7496                         adev,
7497                         &adev->pageflip_irq,
7498                         irq_type);
7499 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7500                 amdgpu_irq_get(
7501                         adev,
7502                         &adev->vline0_irq,
7503                         irq_type);
7504 #endif
7505         } else {
7506 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7507                 amdgpu_irq_put(
7508                         adev,
7509                         &adev->vline0_irq,
7510                         irq_type);
7511 #endif
7512                 amdgpu_irq_put(
7513                         adev,
7514                         &adev->pageflip_irq,
7515                         irq_type);
7516                 drm_crtc_vblank_off(&acrtc->base);
7517         }
7518 }
7519
7520 static void dm_update_pflip_irq_state(struct amdgpu_device *adev,
7521                                       struct amdgpu_crtc *acrtc)
7522 {
7523         int irq_type =
7524                 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
7525
7526         /**
7527          * This reads the current state for the IRQ and force reapplies
7528          * the setting to hardware.
7529          */
7530         amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type);
7531 }
7532
7533 static bool
7534 is_scaling_state_different(const struct dm_connector_state *dm_state,
7535                            const struct dm_connector_state *old_dm_state)
7536 {
7537         if (dm_state->scaling != old_dm_state->scaling)
7538                 return true;
7539         if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
7540                 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
7541                         return true;
7542         } else  if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
7543                 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
7544                         return true;
7545         } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
7546                    dm_state->underscan_vborder != old_dm_state->underscan_vborder)
7547                 return true;
7548         return false;
7549 }
7550
7551 static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state,
7552                                             struct drm_crtc_state *old_crtc_state,
7553                                             struct drm_connector_state *new_conn_state,
7554                                             struct drm_connector_state *old_conn_state,
7555                                             const struct drm_connector *connector,
7556                                             struct hdcp_workqueue *hdcp_w)
7557 {
7558         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7559         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
7560
7561         pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
7562                 connector->index, connector->status, connector->dpms);
7563         pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
7564                 old_conn_state->content_protection, new_conn_state->content_protection);
7565
7566         if (old_crtc_state)
7567                 pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7568                 old_crtc_state->enable,
7569                 old_crtc_state->active,
7570                 old_crtc_state->mode_changed,
7571                 old_crtc_state->active_changed,
7572                 old_crtc_state->connectors_changed);
7573
7574         if (new_crtc_state)
7575                 pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7576                 new_crtc_state->enable,
7577                 new_crtc_state->active,
7578                 new_crtc_state->mode_changed,
7579                 new_crtc_state->active_changed,
7580                 new_crtc_state->connectors_changed);
7581
7582         /* hdcp content type change */
7583         if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type &&
7584             new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
7585                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7586                 pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__);
7587                 return true;
7588         }
7589
7590         /* CP is being re enabled, ignore this */
7591         if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
7592             new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7593                 if (new_crtc_state && new_crtc_state->mode_changed) {
7594                         new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7595                         pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__);
7596                         return true;
7597                 }
7598                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
7599                 pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__);
7600                 return false;
7601         }
7602
7603         /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED
7604          *
7605          * Handles:     UNDESIRED -> ENABLED
7606          */
7607         if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
7608             new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
7609                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7610
7611         /* Stream removed and re-enabled
7612          *
7613          * Can sometimes overlap with the HPD case,
7614          * thus set update_hdcp to false to avoid
7615          * setting HDCP multiple times.
7616          *
7617          * Handles:     DESIRED -> DESIRED (Special case)
7618          */
7619         if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) &&
7620                 new_conn_state->crtc && new_conn_state->crtc->enabled &&
7621                 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7622                 dm_con_state->update_hdcp = false;
7623                 pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n",
7624                         __func__);
7625                 return true;
7626         }
7627
7628         /* Hot-plug, headless s3, dpms
7629          *
7630          * Only start HDCP if the display is connected/enabled.
7631          * update_hdcp flag will be set to false until the next
7632          * HPD comes in.
7633          *
7634          * Handles:     DESIRED -> DESIRED (Special case)
7635          */
7636         if (dm_con_state->update_hdcp &&
7637         new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
7638         connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
7639                 dm_con_state->update_hdcp = false;
7640                 pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n",
7641                         __func__);
7642                 return true;
7643         }
7644
7645         if (old_conn_state->content_protection == new_conn_state->content_protection) {
7646                 if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7647                         if (new_crtc_state && new_crtc_state->mode_changed) {
7648                                 pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n",
7649                                         __func__);
7650                                 return true;
7651                         }
7652                         pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n",
7653                                 __func__);
7654                         return false;
7655                 }
7656
7657                 pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__);
7658                 return false;
7659         }
7660
7661         if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) {
7662                 pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n",
7663                         __func__);
7664                 return true;
7665         }
7666
7667         pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__);
7668         return false;
7669 }
7670
7671 static void remove_stream(struct amdgpu_device *adev,
7672                           struct amdgpu_crtc *acrtc,
7673                           struct dc_stream_state *stream)
7674 {
7675         /* this is the update mode case */
7676
7677         acrtc->otg_inst = -1;
7678         acrtc->enabled = false;
7679 }
7680
7681 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
7682 {
7683
7684         assert_spin_locked(&acrtc->base.dev->event_lock);
7685         WARN_ON(acrtc->event);
7686
7687         acrtc->event = acrtc->base.state->event;
7688
7689         /* Set the flip status */
7690         acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
7691
7692         /* Mark this event as consumed */
7693         acrtc->base.state->event = NULL;
7694
7695         DC_LOG_PFLIP("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
7696                      acrtc->crtc_id);
7697 }
7698
7699 static void update_freesync_state_on_stream(
7700         struct amdgpu_display_manager *dm,
7701         struct dm_crtc_state *new_crtc_state,
7702         struct dc_stream_state *new_stream,
7703         struct dc_plane_state *surface,
7704         u32 flip_timestamp_in_us)
7705 {
7706         struct mod_vrr_params vrr_params;
7707         struct dc_info_packet vrr_infopacket = {0};
7708         struct amdgpu_device *adev = dm->adev;
7709         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7710         unsigned long flags;
7711         bool pack_sdp_v1_3 = false;
7712         struct amdgpu_dm_connector *aconn;
7713         enum vrr_packet_type packet_type = PACKET_TYPE_VRR;
7714
7715         if (!new_stream)
7716                 return;
7717
7718         /*
7719          * TODO: Determine why min/max totals and vrefresh can be 0 here.
7720          * For now it's sufficient to just guard against these conditions.
7721          */
7722
7723         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7724                 return;
7725
7726         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7727         vrr_params = acrtc->dm_irq_params.vrr_params;
7728
7729         if (surface) {
7730                 mod_freesync_handle_preflip(
7731                         dm->freesync_module,
7732                         surface,
7733                         new_stream,
7734                         flip_timestamp_in_us,
7735                         &vrr_params);
7736
7737                 if (adev->family < AMDGPU_FAMILY_AI &&
7738                     amdgpu_dm_crtc_vrr_active(new_crtc_state)) {
7739                         mod_freesync_handle_v_update(dm->freesync_module,
7740                                                      new_stream, &vrr_params);
7741
7742                         /* Need to call this before the frame ends. */
7743                         dc_stream_adjust_vmin_vmax(dm->dc,
7744                                                    new_crtc_state->stream,
7745                                                    &vrr_params.adjust);
7746                 }
7747         }
7748
7749         aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context;
7750
7751         if (aconn && aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {
7752                 pack_sdp_v1_3 = aconn->pack_sdp_v1_3;
7753
7754                 if (aconn->vsdb_info.amd_vsdb_version == 1)
7755                         packet_type = PACKET_TYPE_FS_V1;
7756                 else if (aconn->vsdb_info.amd_vsdb_version == 2)
7757                         packet_type = PACKET_TYPE_FS_V2;
7758                 else if (aconn->vsdb_info.amd_vsdb_version == 3)
7759                         packet_type = PACKET_TYPE_FS_V3;
7760
7761                 mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL,
7762                                         &new_stream->adaptive_sync_infopacket);
7763         }
7764
7765         mod_freesync_build_vrr_infopacket(
7766                 dm->freesync_module,
7767                 new_stream,
7768                 &vrr_params,
7769                 packet_type,
7770                 TRANSFER_FUNC_UNKNOWN,
7771                 &vrr_infopacket,
7772                 pack_sdp_v1_3);
7773
7774         new_crtc_state->freesync_vrr_info_changed |=
7775                 (memcmp(&new_crtc_state->vrr_infopacket,
7776                         &vrr_infopacket,
7777                         sizeof(vrr_infopacket)) != 0);
7778
7779         acrtc->dm_irq_params.vrr_params = vrr_params;
7780         new_crtc_state->vrr_infopacket = vrr_infopacket;
7781
7782         new_stream->vrr_infopacket = vrr_infopacket;
7783         new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params);
7784
7785         if (new_crtc_state->freesync_vrr_info_changed)
7786                 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
7787                               new_crtc_state->base.crtc->base.id,
7788                               (int)new_crtc_state->base.vrr_enabled,
7789                               (int)vrr_params.state);
7790
7791         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7792 }
7793
7794 static void update_stream_irq_parameters(
7795         struct amdgpu_display_manager *dm,
7796         struct dm_crtc_state *new_crtc_state)
7797 {
7798         struct dc_stream_state *new_stream = new_crtc_state->stream;
7799         struct mod_vrr_params vrr_params;
7800         struct mod_freesync_config config = new_crtc_state->freesync_config;
7801         struct amdgpu_device *adev = dm->adev;
7802         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7803         unsigned long flags;
7804
7805         if (!new_stream)
7806                 return;
7807
7808         /*
7809          * TODO: Determine why min/max totals and vrefresh can be 0 here.
7810          * For now it's sufficient to just guard against these conditions.
7811          */
7812         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7813                 return;
7814
7815         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7816         vrr_params = acrtc->dm_irq_params.vrr_params;
7817
7818         if (new_crtc_state->vrr_supported &&
7819             config.min_refresh_in_uhz &&
7820             config.max_refresh_in_uhz) {
7821                 /*
7822                  * if freesync compatible mode was set, config.state will be set
7823                  * in atomic check
7824                  */
7825                 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz &&
7826                     (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) ||
7827                      new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) {
7828                         vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz;
7829                         vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz;
7830                         vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz;
7831                         vrr_params.state = VRR_STATE_ACTIVE_FIXED;
7832                 } else {
7833                         config.state = new_crtc_state->base.vrr_enabled ?
7834                                                      VRR_STATE_ACTIVE_VARIABLE :
7835                                                      VRR_STATE_INACTIVE;
7836                 }
7837         } else {
7838                 config.state = VRR_STATE_UNSUPPORTED;
7839         }
7840
7841         mod_freesync_build_vrr_params(dm->freesync_module,
7842                                       new_stream,
7843                                       &config, &vrr_params);
7844
7845         new_crtc_state->freesync_config = config;
7846         /* Copy state for access from DM IRQ handler */
7847         acrtc->dm_irq_params.freesync_config = config;
7848         acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes;
7849         acrtc->dm_irq_params.vrr_params = vrr_params;
7850         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7851 }
7852
7853 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
7854                                             struct dm_crtc_state *new_state)
7855 {
7856         bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state);
7857         bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state);
7858
7859         if (!old_vrr_active && new_vrr_active) {
7860                 /* Transition VRR inactive -> active:
7861                  * While VRR is active, we must not disable vblank irq, as a
7862                  * reenable after disable would compute bogus vblank/pflip
7863                  * timestamps if it likely happened inside display front-porch.
7864                  *
7865                  * We also need vupdate irq for the actual core vblank handling
7866                  * at end of vblank.
7867                  */
7868                 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0);
7869                 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0);
7870                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
7871                                  __func__, new_state->base.crtc->base.id);
7872         } else if (old_vrr_active && !new_vrr_active) {
7873                 /* Transition VRR active -> inactive:
7874                  * Allow vblank irq disable again for fixed refresh rate.
7875                  */
7876                 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0);
7877                 drm_crtc_vblank_put(new_state->base.crtc);
7878                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
7879                                  __func__, new_state->base.crtc->base.id);
7880         }
7881 }
7882
7883 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
7884 {
7885         struct drm_plane *plane;
7886         struct drm_plane_state *old_plane_state;
7887         int i;
7888
7889         /*
7890          * TODO: Make this per-stream so we don't issue redundant updates for
7891          * commits with multiple streams.
7892          */
7893         for_each_old_plane_in_state(state, plane, old_plane_state, i)
7894                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
7895                         amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state);
7896 }
7897
7898 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
7899                                     struct dc_state *dc_state,
7900                                     struct drm_device *dev,
7901                                     struct amdgpu_display_manager *dm,
7902                                     struct drm_crtc *pcrtc,
7903                                     bool wait_for_vblank)
7904 {
7905         u32 i;
7906         u64 timestamp_ns = ktime_get_ns();
7907         struct drm_plane *plane;
7908         struct drm_plane_state *old_plane_state, *new_plane_state;
7909         struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
7910         struct drm_crtc_state *new_pcrtc_state =
7911                         drm_atomic_get_new_crtc_state(state, pcrtc);
7912         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
7913         struct dm_crtc_state *dm_old_crtc_state =
7914                         to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
7915         int planes_count = 0, vpos, hpos;
7916         unsigned long flags;
7917         u32 target_vblank, last_flip_vblank;
7918         bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state);
7919         bool cursor_update = false;
7920         bool pflip_present = false;
7921         bool dirty_rects_changed = false;
7922         struct {
7923                 struct dc_surface_update surface_updates[MAX_SURFACES];
7924                 struct dc_plane_info plane_infos[MAX_SURFACES];
7925                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
7926                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
7927                 struct dc_stream_update stream_update;
7928         } *bundle;
7929
7930         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
7931
7932         if (!bundle) {
7933                 dm_error("Failed to allocate update bundle\n");
7934                 goto cleanup;
7935         }
7936
7937         /*
7938          * Disable the cursor first if we're disabling all the planes.
7939          * It'll remain on the screen after the planes are re-enabled
7940          * if we don't.
7941          */
7942         if (acrtc_state->active_planes == 0)
7943                 amdgpu_dm_commit_cursors(state);
7944
7945         /* update planes when needed */
7946         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
7947                 struct drm_crtc *crtc = new_plane_state->crtc;
7948                 struct drm_crtc_state *new_crtc_state;
7949                 struct drm_framebuffer *fb = new_plane_state->fb;
7950                 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb;
7951                 bool plane_needs_flip;
7952                 struct dc_plane_state *dc_plane;
7953                 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
7954
7955                 /* Cursor plane is handled after stream updates */
7956                 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
7957                         if ((fb && crtc == pcrtc) ||
7958                             (old_plane_state->fb && old_plane_state->crtc == pcrtc))
7959                                 cursor_update = true;
7960
7961                         continue;
7962                 }
7963
7964                 if (!fb || !crtc || pcrtc != crtc)
7965                         continue;
7966
7967                 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
7968                 if (!new_crtc_state->active)
7969                         continue;
7970
7971                 dc_plane = dm_new_plane_state->dc_state;
7972
7973                 bundle->surface_updates[planes_count].surface = dc_plane;
7974                 if (new_pcrtc_state->color_mgmt_changed) {
7975                         bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
7976                         bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
7977                         bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;
7978                 }
7979
7980                 amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state,
7981                                      &bundle->scaling_infos[planes_count]);
7982
7983                 bundle->surface_updates[planes_count].scaling_info =
7984                         &bundle->scaling_infos[planes_count];
7985
7986                 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
7987
7988                 pflip_present = pflip_present || plane_needs_flip;
7989
7990                 if (!plane_needs_flip) {
7991                         planes_count += 1;
7992                         continue;
7993                 }
7994
7995                 fill_dc_plane_info_and_addr(
7996                         dm->adev, new_plane_state,
7997                         afb->tiling_flags,
7998                         &bundle->plane_infos[planes_count],
7999                         &bundle->flip_addrs[planes_count].address,
8000                         afb->tmz_surface, false);
8001
8002                 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n",
8003                                  new_plane_state->plane->index,
8004                                  bundle->plane_infos[planes_count].dcc.enable);
8005
8006                 bundle->surface_updates[planes_count].plane_info =
8007                         &bundle->plane_infos[planes_count];
8008
8009                 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8010                         fill_dc_dirty_rects(plane, old_plane_state,
8011                                             new_plane_state, new_crtc_state,
8012                                             &bundle->flip_addrs[planes_count],
8013                                             &dirty_rects_changed);
8014
8015                         /*
8016                          * If the dirty regions changed, PSR-SU need to be disabled temporarily
8017                          * and enabled it again after dirty regions are stable to avoid video glitch.
8018                          * PSR-SU will be enabled in vblank_control_worker() if user pause the video
8019                          * during the PSR-SU was disabled.
8020                          */
8021                         if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8022                             acrtc_attach->dm_irq_params.allow_psr_entry &&
8023 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8024                             !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8025 #endif
8026                             dirty_rects_changed) {
8027                                 mutex_lock(&dm->dc_lock);
8028                                 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns =
8029                                 timestamp_ns;
8030                                 if (acrtc_state->stream->link->psr_settings.psr_allow_active)
8031                                         amdgpu_dm_psr_disable(acrtc_state->stream);
8032                                 mutex_unlock(&dm->dc_lock);
8033                         }
8034                 }
8035
8036                 /*
8037                  * Only allow immediate flips for fast updates that don't
8038                  * change FB pitch, DCC state, rotation or mirroing.
8039                  */
8040                 bundle->flip_addrs[planes_count].flip_immediate =
8041                         crtc->state->async_flip &&
8042                         acrtc_state->update_type == UPDATE_TYPE_FAST;
8043
8044                 timestamp_ns = ktime_get_ns();
8045                 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
8046                 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
8047                 bundle->surface_updates[planes_count].surface = dc_plane;
8048
8049                 if (!bundle->surface_updates[planes_count].surface) {
8050                         DRM_ERROR("No surface for CRTC: id=%d\n",
8051                                         acrtc_attach->crtc_id);
8052                         continue;
8053                 }
8054
8055                 if (plane == pcrtc->primary)
8056                         update_freesync_state_on_stream(
8057                                 dm,
8058                                 acrtc_state,
8059                                 acrtc_state->stream,
8060                                 dc_plane,
8061                                 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
8062
8063                 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n",
8064                                  __func__,
8065                                  bundle->flip_addrs[planes_count].address.grph.addr.high_part,
8066                                  bundle->flip_addrs[planes_count].address.grph.addr.low_part);
8067
8068                 planes_count += 1;
8069
8070         }
8071
8072         if (pflip_present) {
8073                 if (!vrr_active) {
8074                         /* Use old throttling in non-vrr fixed refresh rate mode
8075                          * to keep flip scheduling based on target vblank counts
8076                          * working in a backwards compatible way, e.g., for
8077                          * clients using the GLX_OML_sync_control extension or
8078                          * DRI3/Present extension with defined target_msc.
8079                          */
8080                         last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);
8081                 }
8082                 else {
8083                         /* For variable refresh rate mode only:
8084                          * Get vblank of last completed flip to avoid > 1 vrr
8085                          * flips per video frame by use of throttling, but allow
8086                          * flip programming anywhere in the possibly large
8087                          * variable vrr vblank interval for fine-grained flip
8088                          * timing control and more opportunity to avoid stutter
8089                          * on late submission of flips.
8090                          */
8091                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8092                         last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank;
8093                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8094                 }
8095
8096                 target_vblank = last_flip_vblank + wait_for_vblank;
8097
8098                 /*
8099                  * Wait until we're out of the vertical blank period before the one
8100                  * targeted by the flip
8101                  */
8102                 while ((acrtc_attach->enabled &&
8103                         (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
8104                                                             0, &vpos, &hpos, NULL,
8105                                                             NULL, &pcrtc->hwmode)
8106                          & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
8107                         (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
8108                         (int)(target_vblank -
8109                           amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) {
8110                         usleep_range(1000, 1100);
8111                 }
8112
8113                 /**
8114                  * Prepare the flip event for the pageflip interrupt to handle.
8115                  *
8116                  * This only works in the case where we've already turned on the
8117                  * appropriate hardware blocks (eg. HUBP) so in the transition case
8118                  * from 0 -> n planes we have to skip a hardware generated event
8119                  * and rely on sending it from software.
8120                  */
8121                 if (acrtc_attach->base.state->event &&
8122                     acrtc_state->active_planes > 0) {
8123                         drm_crtc_vblank_get(pcrtc);
8124
8125                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8126
8127                         WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
8128                         prepare_flip_isr(acrtc_attach);
8129
8130                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8131                 }
8132
8133                 if (acrtc_state->stream) {
8134                         if (acrtc_state->freesync_vrr_info_changed)
8135                                 bundle->stream_update.vrr_infopacket =
8136                                         &acrtc_state->stream->vrr_infopacket;
8137                 }
8138         } else if (cursor_update && acrtc_state->active_planes > 0 &&
8139                    acrtc_attach->base.state->event) {
8140                 drm_crtc_vblank_get(pcrtc);
8141
8142                 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8143
8144                 acrtc_attach->event = acrtc_attach->base.state->event;
8145                 acrtc_attach->base.state->event = NULL;
8146
8147                 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8148         }
8149
8150         /* Update the planes if changed or disable if we don't have any. */
8151         if ((planes_count || acrtc_state->active_planes == 0) &&
8152                 acrtc_state->stream) {
8153                 /*
8154                  * If PSR or idle optimizations are enabled then flush out
8155                  * any pending work before hardware programming.
8156                  */
8157                 if (dm->vblank_control_workqueue)
8158                         flush_workqueue(dm->vblank_control_workqueue);
8159
8160                 bundle->stream_update.stream = acrtc_state->stream;
8161                 if (new_pcrtc_state->mode_changed) {
8162                         bundle->stream_update.src = acrtc_state->stream->src;
8163                         bundle->stream_update.dst = acrtc_state->stream->dst;
8164                 }
8165
8166                 if (new_pcrtc_state->color_mgmt_changed) {
8167                         /*
8168                          * TODO: This isn't fully correct since we've actually
8169                          * already modified the stream in place.
8170                          */
8171                         bundle->stream_update.gamut_remap =
8172                                 &acrtc_state->stream->gamut_remap_matrix;
8173                         bundle->stream_update.output_csc_transform =
8174                                 &acrtc_state->stream->csc_color_matrix;
8175                         bundle->stream_update.out_transfer_func =
8176                                 acrtc_state->stream->out_transfer_func;
8177                 }
8178
8179                 acrtc_state->stream->abm_level = acrtc_state->abm_level;
8180                 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
8181                         bundle->stream_update.abm_level = &acrtc_state->abm_level;
8182
8183                 /*
8184                  * If FreeSync state on the stream has changed then we need to
8185                  * re-adjust the min/max bounds now that DC doesn't handle this
8186                  * as part of commit.
8187                  */
8188                 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) {
8189                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8190                         dc_stream_adjust_vmin_vmax(
8191                                 dm->dc, acrtc_state->stream,
8192                                 &acrtc_attach->dm_irq_params.vrr_params.adjust);
8193                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8194                 }
8195                 mutex_lock(&dm->dc_lock);
8196                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8197                                 acrtc_state->stream->link->psr_settings.psr_allow_active)
8198                         amdgpu_dm_psr_disable(acrtc_state->stream);
8199
8200                 update_planes_and_stream_adapter(dm->dc,
8201                                          acrtc_state->update_type,
8202                                          planes_count,
8203                                          acrtc_state->stream,
8204                                          &bundle->stream_update,
8205                                          bundle->surface_updates);
8206
8207                 /**
8208                  * Enable or disable the interrupts on the backend.
8209                  *
8210                  * Most pipes are put into power gating when unused.
8211                  *
8212                  * When power gating is enabled on a pipe we lose the
8213                  * interrupt enablement state when power gating is disabled.
8214                  *
8215                  * So we need to update the IRQ control state in hardware
8216                  * whenever the pipe turns on (since it could be previously
8217                  * power gated) or off (since some pipes can't be power gated
8218                  * on some ASICs).
8219                  */
8220                 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes)
8221                         dm_update_pflip_irq_state(drm_to_adev(dev),
8222                                                   acrtc_attach);
8223
8224                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8225                                 acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
8226                                 !acrtc_state->stream->link->psr_settings.psr_feature_enabled)
8227                         amdgpu_dm_link_setup_psr(acrtc_state->stream);
8228
8229                 /* Decrement skip count when PSR is enabled and we're doing fast updates. */
8230                 if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
8231                     acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8232                         struct amdgpu_dm_connector *aconn =
8233                                 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
8234
8235                         if (aconn->psr_skip_count > 0)
8236                                 aconn->psr_skip_count--;
8237
8238                         /* Allow PSR when skip count is 0. */
8239                         acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count;
8240
8241                         /*
8242                          * If sink supports PSR SU, there is no need to rely on
8243                          * a vblank event disable request to enable PSR. PSR SU
8244                          * can be enabled immediately once OS demonstrates an
8245                          * adequate number of fast atomic commits to notify KMD
8246                          * of update events. See `vblank_control_worker()`.
8247                          */
8248                         if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8249                             acrtc_attach->dm_irq_params.allow_psr_entry &&
8250 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8251                             !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8252 #endif
8253                             !acrtc_state->stream->link->psr_settings.psr_allow_active &&
8254                             (timestamp_ns -
8255                             acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) >
8256                             500000000)
8257                                 amdgpu_dm_psr_enable(acrtc_state->stream);
8258                 } else {
8259                         acrtc_attach->dm_irq_params.allow_psr_entry = false;
8260                 }
8261
8262                 mutex_unlock(&dm->dc_lock);
8263         }
8264
8265         /*
8266          * Update cursor state *after* programming all the planes.
8267          * This avoids redundant programming in the case where we're going
8268          * to be disabling a single plane - those pipes are being disabled.
8269          */
8270         if (acrtc_state->active_planes)
8271                 amdgpu_dm_commit_cursors(state);
8272
8273 cleanup:
8274         kfree(bundle);
8275 }
8276
8277 static void amdgpu_dm_commit_audio(struct drm_device *dev,
8278                                    struct drm_atomic_state *state)
8279 {
8280         struct amdgpu_device *adev = drm_to_adev(dev);
8281         struct amdgpu_dm_connector *aconnector;
8282         struct drm_connector *connector;
8283         struct drm_connector_state *old_con_state, *new_con_state;
8284         struct drm_crtc_state *new_crtc_state;
8285         struct dm_crtc_state *new_dm_crtc_state;
8286         const struct dc_stream_status *status;
8287         int i, inst;
8288
8289         /* Notify device removals. */
8290         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8291                 if (old_con_state->crtc != new_con_state->crtc) {
8292                         /* CRTC changes require notification. */
8293                         goto notify;
8294                 }
8295
8296                 if (!new_con_state->crtc)
8297                         continue;
8298
8299                 new_crtc_state = drm_atomic_get_new_crtc_state(
8300                         state, new_con_state->crtc);
8301
8302                 if (!new_crtc_state)
8303                         continue;
8304
8305                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8306                         continue;
8307
8308         notify:
8309                 aconnector = to_amdgpu_dm_connector(connector);
8310
8311                 mutex_lock(&adev->dm.audio_lock);
8312                 inst = aconnector->audio_inst;
8313                 aconnector->audio_inst = -1;
8314                 mutex_unlock(&adev->dm.audio_lock);
8315
8316                 amdgpu_dm_audio_eld_notify(adev, inst);
8317         }
8318
8319         /* Notify audio device additions. */
8320         for_each_new_connector_in_state(state, connector, new_con_state, i) {
8321                 if (!new_con_state->crtc)
8322                         continue;
8323
8324                 new_crtc_state = drm_atomic_get_new_crtc_state(
8325                         state, new_con_state->crtc);
8326
8327                 if (!new_crtc_state)
8328                         continue;
8329
8330                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8331                         continue;
8332
8333                 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
8334                 if (!new_dm_crtc_state->stream)
8335                         continue;
8336
8337                 status = dc_stream_get_status(new_dm_crtc_state->stream);
8338                 if (!status)
8339                         continue;
8340
8341                 aconnector = to_amdgpu_dm_connector(connector);
8342
8343                 mutex_lock(&adev->dm.audio_lock);
8344                 inst = status->audio_inst;
8345                 aconnector->audio_inst = inst;
8346                 mutex_unlock(&adev->dm.audio_lock);
8347
8348                 amdgpu_dm_audio_eld_notify(adev, inst);
8349         }
8350 }
8351
8352 /*
8353  * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
8354  * @crtc_state: the DRM CRTC state
8355  * @stream_state: the DC stream state.
8356  *
8357  * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
8358  * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
8359  */
8360 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
8361                                                 struct dc_stream_state *stream_state)
8362 {
8363         stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
8364 }
8365
8366 /**
8367  * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
8368  * @state: The atomic state to commit
8369  *
8370  * This will tell DC to commit the constructed DC state from atomic_check,
8371  * programming the hardware. Any failures here implies a hardware failure, since
8372  * atomic check should have filtered anything non-kosher.
8373  */
8374 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
8375 {
8376         struct drm_device *dev = state->dev;
8377         struct amdgpu_device *adev = drm_to_adev(dev);
8378         struct amdgpu_display_manager *dm = &adev->dm;
8379         struct dm_atomic_state *dm_state;
8380         struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
8381         u32 i, j;
8382         struct drm_crtc *crtc;
8383         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8384         unsigned long flags;
8385         bool wait_for_vblank = true;
8386         struct drm_connector *connector;
8387         struct drm_connector_state *old_con_state, *new_con_state;
8388         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8389         int crtc_disable_count = 0;
8390         bool mode_set_reset_required = false;
8391         int r;
8392
8393         trace_amdgpu_dm_atomic_commit_tail_begin(state);
8394
8395         r = drm_atomic_helper_wait_for_fences(dev, state, false);
8396         if (unlikely(r))
8397                 DRM_ERROR("Waiting for fences timed out!");
8398
8399         drm_atomic_helper_update_legacy_modeset_state(dev, state);
8400         drm_dp_mst_atomic_wait_for_dependencies(state);
8401
8402         dm_state = dm_atomic_get_new_state(state);
8403         if (dm_state && dm_state->context) {
8404                 dc_state = dm_state->context;
8405         } else {
8406                 /* No state changes, retain current state. */
8407                 dc_state_temp = dc_create_state(dm->dc);
8408                 ASSERT(dc_state_temp);
8409                 dc_state = dc_state_temp;
8410                 dc_resource_state_copy_construct_current(dm->dc, dc_state);
8411         }
8412
8413         for_each_oldnew_crtc_in_state (state, crtc, old_crtc_state,
8414                                        new_crtc_state, i) {
8415                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8416
8417                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8418
8419                 if (old_crtc_state->active &&
8420                     (!new_crtc_state->active ||
8421                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8422                         manage_dm_interrupts(adev, acrtc, false);
8423                         dc_stream_release(dm_old_crtc_state->stream);
8424                 }
8425         }
8426
8427         drm_atomic_helper_calc_timestamping_constants(state);
8428
8429         /* update changed items */
8430         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8431                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8432
8433                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8434                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8435
8436                 drm_dbg_state(state->dev,
8437                         "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
8438                         "planes_changed:%d, mode_changed:%d,active_changed:%d,"
8439                         "connectors_changed:%d\n",
8440                         acrtc->crtc_id,
8441                         new_crtc_state->enable,
8442                         new_crtc_state->active,
8443                         new_crtc_state->planes_changed,
8444                         new_crtc_state->mode_changed,
8445                         new_crtc_state->active_changed,
8446                         new_crtc_state->connectors_changed);
8447
8448                 /* Disable cursor if disabling crtc */
8449                 if (old_crtc_state->active && !new_crtc_state->active) {
8450                         struct dc_cursor_position position;
8451
8452                         memset(&position, 0, sizeof(position));
8453                         mutex_lock(&dm->dc_lock);
8454                         dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position);
8455                         mutex_unlock(&dm->dc_lock);
8456                 }
8457
8458                 /* Copy all transient state flags into dc state */
8459                 if (dm_new_crtc_state->stream) {
8460                         amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
8461                                                             dm_new_crtc_state->stream);
8462                 }
8463
8464                 /* handles headless hotplug case, updating new_state and
8465                  * aconnector as needed
8466                  */
8467
8468                 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
8469
8470                         DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
8471
8472                         if (!dm_new_crtc_state->stream) {
8473                                 /*
8474                                  * this could happen because of issues with
8475                                  * userspace notifications delivery.
8476                                  * In this case userspace tries to set mode on
8477                                  * display which is disconnected in fact.
8478                                  * dc_sink is NULL in this case on aconnector.
8479                                  * We expect reset mode will come soon.
8480                                  *
8481                                  * This can also happen when unplug is done
8482                                  * during resume sequence ended
8483                                  *
8484                                  * In this case, we want to pretend we still
8485                                  * have a sink to keep the pipe running so that
8486                                  * hw state is consistent with the sw state
8487                                  */
8488                                 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
8489                                                 __func__, acrtc->base.base.id);
8490                                 continue;
8491                         }
8492
8493                         if (dm_old_crtc_state->stream)
8494                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8495
8496                         pm_runtime_get_noresume(dev->dev);
8497
8498                         acrtc->enabled = true;
8499                         acrtc->hw_mode = new_crtc_state->mode;
8500                         crtc->hwmode = new_crtc_state->mode;
8501                         mode_set_reset_required = true;
8502                 } else if (modereset_required(new_crtc_state)) {
8503                         DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
8504                         /* i.e. reset mode */
8505                         if (dm_old_crtc_state->stream)
8506                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8507
8508                         mode_set_reset_required = true;
8509                 }
8510         } /* for_each_crtc_in_state() */
8511
8512         if (dc_state) {
8513                 /* if there mode set or reset, disable eDP PSR */
8514                 if (mode_set_reset_required) {
8515                         if (dm->vblank_control_workqueue)
8516                                 flush_workqueue(dm->vblank_control_workqueue);
8517
8518                         amdgpu_dm_psr_disable_all(dm);
8519                 }
8520
8521                 dm_enable_per_frame_crtc_master_sync(dc_state);
8522                 mutex_lock(&dm->dc_lock);
8523                 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
8524
8525                 /* Allow idle optimization when vblank count is 0 for display off */
8526                 if (dm->active_vblank_irq_count == 0)
8527                         dc_allow_idle_optimizations(dm->dc, true);
8528                 mutex_unlock(&dm->dc_lock);
8529         }
8530
8531         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8532                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8533
8534                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8535
8536                 if (dm_new_crtc_state->stream != NULL) {
8537                         const struct dc_stream_status *status =
8538                                         dc_stream_get_status(dm_new_crtc_state->stream);
8539
8540                         if (!status)
8541                                 status = dc_stream_get_status_from_state(dc_state,
8542                                                                          dm_new_crtc_state->stream);
8543                         if (!status)
8544                                 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
8545                         else
8546                                 acrtc->otg_inst = status->primary_otg_inst;
8547                 }
8548         }
8549         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8550                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8551                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8552                 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8553
8554                 pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i);
8555
8556                 if (!connector)
8557                         continue;
8558
8559                 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
8560                         connector->index, connector->status, connector->dpms);
8561                 pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
8562                         old_con_state->content_protection, new_con_state->content_protection);
8563
8564                 if (aconnector->dc_sink) {
8565                         if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
8566                                 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) {
8567                                 pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n",
8568                                 aconnector->dc_sink->edid_caps.display_name);
8569                         }
8570                 }
8571
8572                 new_crtc_state = NULL;
8573                 old_crtc_state = NULL;
8574
8575                 if (acrtc) {
8576                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8577                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8578                 }
8579
8580                 if (old_crtc_state)
8581                         pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8582                         old_crtc_state->enable,
8583                         old_crtc_state->active,
8584                         old_crtc_state->mode_changed,
8585                         old_crtc_state->active_changed,
8586                         old_crtc_state->connectors_changed);
8587
8588                 if (new_crtc_state)
8589                         pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8590                         new_crtc_state->enable,
8591                         new_crtc_state->active,
8592                         new_crtc_state->mode_changed,
8593                         new_crtc_state->active_changed,
8594                         new_crtc_state->connectors_changed);
8595         }
8596
8597         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8598                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8599                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8600                 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8601
8602                 new_crtc_state = NULL;
8603                 old_crtc_state = NULL;
8604
8605                 if (acrtc) {
8606                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8607                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8608                 }
8609
8610                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8611
8612                 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
8613                     connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
8614                         hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
8615                         new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
8616                         dm_new_con_state->update_hdcp = true;
8617                         continue;
8618                 }
8619
8620                 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state,
8621                                                                                         old_con_state, connector, adev->dm.hdcp_workqueue)) {
8622                         /* when display is unplugged from mst hub, connctor will
8623                          * be destroyed within dm_dp_mst_connector_destroy. connector
8624                          * hdcp perperties, like type, undesired, desired, enabled,
8625                          * will be lost. So, save hdcp properties into hdcp_work within
8626                          * amdgpu_dm_atomic_commit_tail. if the same display is
8627                          * plugged back with same display index, its hdcp properties
8628                          * will be retrieved from hdcp_work within dm_dp_mst_get_modes
8629                          */
8630
8631                         bool enable_encryption = false;
8632
8633                         if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED)
8634                                 enable_encryption = true;
8635
8636                         if (aconnector->dc_link && aconnector->dc_sink &&
8637                                 aconnector->dc_link->type == dc_connection_mst_branch) {
8638                                 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
8639                                 struct hdcp_workqueue *hdcp_w =
8640                                         &hdcp_work[aconnector->dc_link->link_index];
8641
8642                                 hdcp_w->hdcp_content_type[connector->index] =
8643                                         new_con_state->hdcp_content_type;
8644                                 hdcp_w->content_protection[connector->index] =
8645                                         new_con_state->content_protection;
8646                         }
8647
8648                         if (new_crtc_state && new_crtc_state->mode_changed &&
8649                                 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED)
8650                                 enable_encryption = true;
8651
8652                         DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption);
8653
8654                         hdcp_update_display(
8655                                 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
8656                                 new_con_state->hdcp_content_type, enable_encryption);
8657                 }
8658         }
8659
8660         /* Handle connector state changes */
8661         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8662                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8663                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
8664                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8665                 struct dc_surface_update dummy_updates[MAX_SURFACES];
8666                 struct dc_stream_update stream_update;
8667                 struct dc_info_packet hdr_packet;
8668                 struct dc_stream_status *status = NULL;
8669                 bool abm_changed, hdr_changed, scaling_changed;
8670
8671                 memset(&dummy_updates, 0, sizeof(dummy_updates));
8672                 memset(&stream_update, 0, sizeof(stream_update));
8673
8674                 if (acrtc) {
8675                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8676                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8677                 }
8678
8679                 /* Skip any modesets/resets */
8680                 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
8681                         continue;
8682
8683                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8684                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8685
8686                 scaling_changed = is_scaling_state_different(dm_new_con_state,
8687                                                              dm_old_con_state);
8688
8689                 abm_changed = dm_new_crtc_state->abm_level !=
8690                               dm_old_crtc_state->abm_level;
8691
8692                 hdr_changed =
8693                         !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state);
8694
8695                 if (!scaling_changed && !abm_changed && !hdr_changed)
8696                         continue;
8697
8698                 stream_update.stream = dm_new_crtc_state->stream;
8699                 if (scaling_changed) {
8700                         update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
8701                                         dm_new_con_state, dm_new_crtc_state->stream);
8702
8703                         stream_update.src = dm_new_crtc_state->stream->src;
8704                         stream_update.dst = dm_new_crtc_state->stream->dst;
8705                 }
8706
8707                 if (abm_changed) {
8708                         dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
8709
8710                         stream_update.abm_level = &dm_new_crtc_state->abm_level;
8711                 }
8712
8713                 if (hdr_changed) {
8714                         fill_hdr_info_packet(new_con_state, &hdr_packet);
8715                         stream_update.hdr_static_metadata = &hdr_packet;
8716                 }
8717
8718                 status = dc_stream_get_status(dm_new_crtc_state->stream);
8719
8720                 if (WARN_ON(!status))
8721                         continue;
8722
8723                 WARN_ON(!status->plane_count);
8724
8725                 /*
8726                  * TODO: DC refuses to perform stream updates without a dc_surface_update.
8727                  * Here we create an empty update on each plane.
8728                  * To fix this, DC should permit updating only stream properties.
8729                  */
8730                 for (j = 0; j < status->plane_count; j++)
8731                         dummy_updates[j].surface = status->plane_states[0];
8732
8733
8734                 mutex_lock(&dm->dc_lock);
8735                 dc_update_planes_and_stream(dm->dc,
8736                                             dummy_updates,
8737                                             status->plane_count,
8738                                             dm_new_crtc_state->stream,
8739                                             &stream_update);
8740                 mutex_unlock(&dm->dc_lock);
8741         }
8742
8743         /**
8744          * Enable interrupts for CRTCs that are newly enabled or went through
8745          * a modeset. It was intentionally deferred until after the front end
8746          * state was modified to wait until the OTG was on and so the IRQ
8747          * handlers didn't access stale or invalid state.
8748          */
8749         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8750                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8751 #ifdef CONFIG_DEBUG_FS
8752                 enum amdgpu_dm_pipe_crc_source cur_crc_src;
8753 #endif
8754                 /* Count number of newly disabled CRTCs for dropping PM refs later. */
8755                 if (old_crtc_state->active && !new_crtc_state->active)
8756                         crtc_disable_count++;
8757
8758                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8759                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8760
8761                 /* For freesync config update on crtc state and params for irq */
8762                 update_stream_irq_parameters(dm, dm_new_crtc_state);
8763
8764 #ifdef CONFIG_DEBUG_FS
8765                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8766                 cur_crc_src = acrtc->dm_irq_params.crc_src;
8767                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8768 #endif
8769
8770                 if (new_crtc_state->active &&
8771                     (!old_crtc_state->active ||
8772                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8773                         dc_stream_retain(dm_new_crtc_state->stream);
8774                         acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
8775                         manage_dm_interrupts(adev, acrtc, true);
8776                 }
8777                 /* Handle vrr on->off / off->on transitions */
8778                 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state);
8779
8780 #ifdef CONFIG_DEBUG_FS
8781                 if (new_crtc_state->active &&
8782                     (!old_crtc_state->active ||
8783                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8784                         /**
8785                          * Frontend may have changed so reapply the CRC capture
8786                          * settings for the stream.
8787                          */
8788                         if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
8789 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
8790                                 if (amdgpu_dm_crc_window_is_activated(crtc)) {
8791                                         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8792                                         acrtc->dm_irq_params.window_param.update_win = true;
8793
8794                                         /**
8795                                          * It takes 2 frames for HW to stably generate CRC when
8796                                          * resuming from suspend, so we set skip_frame_cnt 2.
8797                                          */
8798                                         acrtc->dm_irq_params.window_param.skip_frame_cnt = 2;
8799                                         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8800                                 }
8801 #endif
8802                                 if (amdgpu_dm_crtc_configure_crc_source(
8803                                         crtc, dm_new_crtc_state, cur_crc_src))
8804                                         DRM_DEBUG_DRIVER("Failed to configure crc source");
8805                         }
8806                 }
8807 #endif
8808         }
8809
8810         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
8811                 if (new_crtc_state->async_flip)
8812                         wait_for_vblank = false;
8813
8814         /* update planes when needed per crtc*/
8815         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
8816                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8817
8818                 if (dm_new_crtc_state->stream)
8819                         amdgpu_dm_commit_planes(state, dc_state, dev,
8820                                                 dm, crtc, wait_for_vblank);
8821         }
8822
8823         /* Update audio instances for each connector. */
8824         amdgpu_dm_commit_audio(dev, state);
8825
8826         /* restore the backlight level */
8827         for (i = 0; i < dm->num_of_edps; i++) {
8828                 if (dm->backlight_dev[i] &&
8829                     (dm->actual_brightness[i] != dm->brightness[i]))
8830                         amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
8831         }
8832
8833         /*
8834          * send vblank event on all events not handled in flip and
8835          * mark consumed event for drm_atomic_helper_commit_hw_done
8836          */
8837         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8838         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8839
8840                 if (new_crtc_state->event)
8841                         drm_send_event_locked(dev, &new_crtc_state->event->base);
8842
8843                 new_crtc_state->event = NULL;
8844         }
8845         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8846
8847         /* Signal HW programming completion */
8848         drm_atomic_helper_commit_hw_done(state);
8849
8850         if (wait_for_vblank)
8851                 drm_atomic_helper_wait_for_flip_done(dev, state);
8852
8853         drm_atomic_helper_cleanup_planes(dev, state);
8854
8855         /* return the stolen vga memory back to VRAM */
8856         if (!adev->mman.keep_stolen_vga_memory)
8857                 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
8858         amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
8859
8860         /*
8861          * Finally, drop a runtime PM reference for each newly disabled CRTC,
8862          * so we can put the GPU into runtime suspend if we're not driving any
8863          * displays anymore
8864          */
8865         for (i = 0; i < crtc_disable_count; i++)
8866                 pm_runtime_put_autosuspend(dev->dev);
8867         pm_runtime_mark_last_busy(dev->dev);
8868
8869         if (dc_state_temp)
8870                 dc_release_state(dc_state_temp);
8871 }
8872
8873 static int dm_force_atomic_commit(struct drm_connector *connector)
8874 {
8875         int ret = 0;
8876         struct drm_device *ddev = connector->dev;
8877         struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
8878         struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
8879         struct drm_plane *plane = disconnected_acrtc->base.primary;
8880         struct drm_connector_state *conn_state;
8881         struct drm_crtc_state *crtc_state;
8882         struct drm_plane_state *plane_state;
8883
8884         if (!state)
8885                 return -ENOMEM;
8886
8887         state->acquire_ctx = ddev->mode_config.acquire_ctx;
8888
8889         /* Construct an atomic state to restore previous display setting */
8890
8891         /*
8892          * Attach connectors to drm_atomic_state
8893          */
8894         conn_state = drm_atomic_get_connector_state(state, connector);
8895
8896         ret = PTR_ERR_OR_ZERO(conn_state);
8897         if (ret)
8898                 goto out;
8899
8900         /* Attach crtc to drm_atomic_state*/
8901         crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
8902
8903         ret = PTR_ERR_OR_ZERO(crtc_state);
8904         if (ret)
8905                 goto out;
8906
8907         /* force a restore */
8908         crtc_state->mode_changed = true;
8909
8910         /* Attach plane to drm_atomic_state */
8911         plane_state = drm_atomic_get_plane_state(state, plane);
8912
8913         ret = PTR_ERR_OR_ZERO(plane_state);
8914         if (ret)
8915                 goto out;
8916
8917         /* Call commit internally with the state we just constructed */
8918         ret = drm_atomic_commit(state);
8919
8920 out:
8921         drm_atomic_state_put(state);
8922         if (ret)
8923                 DRM_ERROR("Restoring old state failed with %i\n", ret);
8924
8925         return ret;
8926 }
8927
8928 /*
8929  * This function handles all cases when set mode does not come upon hotplug.
8930  * This includes when a display is unplugged then plugged back into the
8931  * same port and when running without usermode desktop manager supprot
8932  */
8933 void dm_restore_drm_connector_state(struct drm_device *dev,
8934                                     struct drm_connector *connector)
8935 {
8936         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8937         struct amdgpu_crtc *disconnected_acrtc;
8938         struct dm_crtc_state *acrtc_state;
8939
8940         if (!aconnector->dc_sink || !connector->state || !connector->encoder)
8941                 return;
8942
8943         disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
8944         if (!disconnected_acrtc)
8945                 return;
8946
8947         acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
8948         if (!acrtc_state->stream)
8949                 return;
8950
8951         /*
8952          * If the previous sink is not released and different from the current,
8953          * we deduce we are in a state where we can not rely on usermode call
8954          * to turn on the display, so we do it here
8955          */
8956         if (acrtc_state->stream->sink != aconnector->dc_sink)
8957                 dm_force_atomic_commit(&aconnector->base);
8958 }
8959
8960 /*
8961  * Grabs all modesetting locks to serialize against any blocking commits,
8962  * Waits for completion of all non blocking commits.
8963  */
8964 static int do_aquire_global_lock(struct drm_device *dev,
8965                                  struct drm_atomic_state *state)
8966 {
8967         struct drm_crtc *crtc;
8968         struct drm_crtc_commit *commit;
8969         long ret;
8970
8971         /*
8972          * Adding all modeset locks to aquire_ctx will
8973          * ensure that when the framework release it the
8974          * extra locks we are locking here will get released to
8975          */
8976         ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
8977         if (ret)
8978                 return ret;
8979
8980         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8981                 spin_lock(&crtc->commit_lock);
8982                 commit = list_first_entry_or_null(&crtc->commit_list,
8983                                 struct drm_crtc_commit, commit_entry);
8984                 if (commit)
8985                         drm_crtc_commit_get(commit);
8986                 spin_unlock(&crtc->commit_lock);
8987
8988                 if (!commit)
8989                         continue;
8990
8991                 /*
8992                  * Make sure all pending HW programming completed and
8993                  * page flips done
8994                  */
8995                 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
8996
8997                 if (ret > 0)
8998                         ret = wait_for_completion_interruptible_timeout(
8999                                         &commit->flip_done, 10*HZ);
9000
9001                 if (ret == 0)
9002                         DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
9003                                   "timed out\n", crtc->base.id, crtc->name);
9004
9005                 drm_crtc_commit_put(commit);
9006         }
9007
9008         return ret < 0 ? ret : 0;
9009 }
9010
9011 static void get_freesync_config_for_crtc(
9012         struct dm_crtc_state *new_crtc_state,
9013         struct dm_connector_state *new_con_state)
9014 {
9015         struct mod_freesync_config config = {0};
9016         struct amdgpu_dm_connector *aconnector =
9017                         to_amdgpu_dm_connector(new_con_state->base.connector);
9018         struct drm_display_mode *mode = &new_crtc_state->base.mode;
9019         int vrefresh = drm_mode_vrefresh(mode);
9020         bool fs_vid_mode = false;
9021
9022         new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
9023                                         vrefresh >= aconnector->min_vfreq &&
9024                                         vrefresh <= aconnector->max_vfreq;
9025
9026         if (new_crtc_state->vrr_supported) {
9027                 new_crtc_state->stream->ignore_msa_timing_param = true;
9028                 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
9029
9030                 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000;
9031                 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000;
9032                 config.vsif_supported = true;
9033                 config.btr = true;
9034
9035                 if (fs_vid_mode) {
9036                         config.state = VRR_STATE_ACTIVE_FIXED;
9037                         config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz;
9038                         goto out;
9039                 } else if (new_crtc_state->base.vrr_enabled) {
9040                         config.state = VRR_STATE_ACTIVE_VARIABLE;
9041                 } else {
9042                         config.state = VRR_STATE_INACTIVE;
9043                 }
9044         }
9045 out:
9046         new_crtc_state->freesync_config = config;
9047 }
9048
9049 static void reset_freesync_config_for_crtc(
9050         struct dm_crtc_state *new_crtc_state)
9051 {
9052         new_crtc_state->vrr_supported = false;
9053
9054         memset(&new_crtc_state->vrr_infopacket, 0,
9055                sizeof(new_crtc_state->vrr_infopacket));
9056 }
9057
9058 static bool
9059 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
9060                                  struct drm_crtc_state *new_crtc_state)
9061 {
9062         const struct drm_display_mode *old_mode, *new_mode;
9063
9064         if (!old_crtc_state || !new_crtc_state)
9065                 return false;
9066
9067         old_mode = &old_crtc_state->mode;
9068         new_mode = &new_crtc_state->mode;
9069
9070         if (old_mode->clock       == new_mode->clock &&
9071             old_mode->hdisplay    == new_mode->hdisplay &&
9072             old_mode->vdisplay    == new_mode->vdisplay &&
9073             old_mode->htotal      == new_mode->htotal &&
9074             old_mode->vtotal      != new_mode->vtotal &&
9075             old_mode->hsync_start == new_mode->hsync_start &&
9076             old_mode->vsync_start != new_mode->vsync_start &&
9077             old_mode->hsync_end   == new_mode->hsync_end &&
9078             old_mode->vsync_end   != new_mode->vsync_end &&
9079             old_mode->hskew       == new_mode->hskew &&
9080             old_mode->vscan       == new_mode->vscan &&
9081             (old_mode->vsync_end - old_mode->vsync_start) ==
9082             (new_mode->vsync_end - new_mode->vsync_start))
9083                 return true;
9084
9085         return false;
9086 }
9087
9088 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) {
9089         u64 num, den, res;
9090         struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
9091
9092         dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;
9093
9094         num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000;
9095         den = (unsigned long long)new_crtc_state->mode.htotal *
9096               (unsigned long long)new_crtc_state->mode.vtotal;
9097
9098         res = div_u64(num, den);
9099         dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
9100 }
9101
9102 static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
9103                          struct drm_atomic_state *state,
9104                          struct drm_crtc *crtc,
9105                          struct drm_crtc_state *old_crtc_state,
9106                          struct drm_crtc_state *new_crtc_state,
9107                          bool enable,
9108                          bool *lock_and_validation_needed)
9109 {
9110         struct dm_atomic_state *dm_state = NULL;
9111         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9112         struct dc_stream_state *new_stream;
9113         int ret = 0;
9114
9115         /*
9116          * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
9117          * update changed items
9118          */
9119         struct amdgpu_crtc *acrtc = NULL;
9120         struct amdgpu_dm_connector *aconnector = NULL;
9121         struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
9122         struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
9123
9124         new_stream = NULL;
9125
9126         dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9127         dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9128         acrtc = to_amdgpu_crtc(crtc);
9129         aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
9130
9131         /* TODO This hack should go away */
9132         if (aconnector && enable) {
9133                 /* Make sure fake sink is created in plug-in scenario */
9134                 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
9135                                                             &aconnector->base);
9136                 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
9137                                                             &aconnector->base);
9138
9139                 if (IS_ERR(drm_new_conn_state)) {
9140                         ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
9141                         goto fail;
9142                 }
9143
9144                 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
9145                 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
9146
9147                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9148                         goto skip_modeset;
9149
9150                 new_stream = create_validate_stream_for_sink(aconnector,
9151                                                              &new_crtc_state->mode,
9152                                                              dm_new_conn_state,
9153                                                              dm_old_crtc_state->stream);
9154
9155                 /*
9156                  * we can have no stream on ACTION_SET if a display
9157                  * was disconnected during S3, in this case it is not an
9158                  * error, the OS will be updated after detection, and
9159                  * will do the right thing on next atomic commit
9160                  */
9161
9162                 if (!new_stream) {
9163                         DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
9164                                         __func__, acrtc->base.base.id);
9165                         ret = -ENOMEM;
9166                         goto fail;
9167                 }
9168
9169                 /*
9170                  * TODO: Check VSDB bits to decide whether this should
9171                  * be enabled or not.
9172                  */
9173                 new_stream->triggered_crtc_reset.enabled =
9174                         dm->force_timing_sync;
9175
9176                 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9177
9178                 ret = fill_hdr_info_packet(drm_new_conn_state,
9179                                            &new_stream->hdr_static_metadata);
9180                 if (ret)
9181                         goto fail;
9182
9183                 /*
9184                  * If we already removed the old stream from the context
9185                  * (and set the new stream to NULL) then we can't reuse
9186                  * the old stream even if the stream and scaling are unchanged.
9187                  * We'll hit the BUG_ON and black screen.
9188                  *
9189                  * TODO: Refactor this function to allow this check to work
9190                  * in all conditions.
9191                  */
9192                 if (amdgpu_freesync_vid_mode &&
9193                     dm_new_crtc_state->stream &&
9194                     is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))
9195                         goto skip_modeset;
9196
9197                 if (dm_new_crtc_state->stream &&
9198                     dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9199                     dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
9200                         new_crtc_state->mode_changed = false;
9201                         DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
9202                                          new_crtc_state->mode_changed);
9203                 }
9204         }
9205
9206         /* mode_changed flag may get updated above, need to check again */
9207         if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9208                 goto skip_modeset;
9209
9210         drm_dbg_state(state->dev,
9211                 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
9212                 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
9213                 "connectors_changed:%d\n",
9214                 acrtc->crtc_id,
9215                 new_crtc_state->enable,
9216                 new_crtc_state->active,
9217                 new_crtc_state->planes_changed,
9218                 new_crtc_state->mode_changed,
9219                 new_crtc_state->active_changed,
9220                 new_crtc_state->connectors_changed);
9221
9222         /* Remove stream for any changed/disabled CRTC */
9223         if (!enable) {
9224
9225                 if (!dm_old_crtc_state->stream)
9226                         goto skip_modeset;
9227
9228                 /* Unset freesync video if it was active before */
9229                 if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) {
9230                         dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE;
9231                         dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0;
9232                 }
9233
9234                 /* Now check if we should set freesync video mode */
9235                 if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream &&
9236                     is_timing_unchanged_for_freesync(new_crtc_state,
9237                                                      old_crtc_state)) {
9238                         new_crtc_state->mode_changed = false;
9239                         DRM_DEBUG_DRIVER(
9240                                 "Mode change not required for front porch change, "
9241                                 "setting mode_changed to %d",
9242                                 new_crtc_state->mode_changed);
9243
9244                         set_freesync_fixed_config(dm_new_crtc_state);
9245
9246                         goto skip_modeset;
9247                 } else if (amdgpu_freesync_vid_mode && aconnector &&
9248                            is_freesync_video_mode(&new_crtc_state->mode,
9249                                                   aconnector)) {
9250                         struct drm_display_mode *high_mode;
9251
9252                         high_mode = get_highest_refresh_rate_mode(aconnector, false);
9253                         if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) {
9254                                 set_freesync_fixed_config(dm_new_crtc_state);
9255                         }
9256                 }
9257
9258                 ret = dm_atomic_get_state(state, &dm_state);
9259                 if (ret)
9260                         goto fail;
9261
9262                 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
9263                                 crtc->base.id);
9264
9265                 /* i.e. reset mode */
9266                 if (dc_remove_stream_from_ctx(
9267                                 dm->dc,
9268                                 dm_state->context,
9269                                 dm_old_crtc_state->stream) != DC_OK) {
9270                         ret = -EINVAL;
9271                         goto fail;
9272                 }
9273
9274                 dc_stream_release(dm_old_crtc_state->stream);
9275                 dm_new_crtc_state->stream = NULL;
9276
9277                 reset_freesync_config_for_crtc(dm_new_crtc_state);
9278
9279                 *lock_and_validation_needed = true;
9280
9281         } else {/* Add stream for any updated/enabled CRTC */
9282                 /*
9283                  * Quick fix to prevent NULL pointer on new_stream when
9284                  * added MST connectors not found in existing crtc_state in the chained mode
9285                  * TODO: need to dig out the root cause of that
9286                  */
9287                 if (!aconnector)
9288                         goto skip_modeset;
9289
9290                 if (modereset_required(new_crtc_state))
9291                         goto skip_modeset;
9292
9293                 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream,
9294                                      dm_old_crtc_state->stream)) {
9295
9296                         WARN_ON(dm_new_crtc_state->stream);
9297
9298                         ret = dm_atomic_get_state(state, &dm_state);
9299                         if (ret)
9300                                 goto fail;
9301
9302                         dm_new_crtc_state->stream = new_stream;
9303
9304                         dc_stream_retain(new_stream);
9305
9306                         DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n",
9307                                          crtc->base.id);
9308
9309                         if (dc_add_stream_to_ctx(
9310                                         dm->dc,
9311                                         dm_state->context,
9312                                         dm_new_crtc_state->stream) != DC_OK) {
9313                                 ret = -EINVAL;
9314                                 goto fail;
9315                         }
9316
9317                         *lock_and_validation_needed = true;
9318                 }
9319         }
9320
9321 skip_modeset:
9322         /* Release extra reference */
9323         if (new_stream)
9324                  dc_stream_release(new_stream);
9325
9326         /*
9327          * We want to do dc stream updates that do not require a
9328          * full modeset below.
9329          */
9330         if (!(enable && aconnector && new_crtc_state->active))
9331                 return 0;
9332         /*
9333          * Given above conditions, the dc state cannot be NULL because:
9334          * 1. We're in the process of enabling CRTCs (just been added
9335          *    to the dc context, or already is on the context)
9336          * 2. Has a valid connector attached, and
9337          * 3. Is currently active and enabled.
9338          * => The dc stream state currently exists.
9339          */
9340         BUG_ON(dm_new_crtc_state->stream == NULL);
9341
9342         /* Scaling or underscan settings */
9343         if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) ||
9344                                 drm_atomic_crtc_needs_modeset(new_crtc_state))
9345                 update_stream_scaling_settings(
9346                         &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
9347
9348         /* ABM settings */
9349         dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9350
9351         /*
9352          * Color management settings. We also update color properties
9353          * when a modeset is needed, to ensure it gets reprogrammed.
9354          */
9355         if (dm_new_crtc_state->base.color_mgmt_changed ||
9356             drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9357                 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
9358                 if (ret)
9359                         goto fail;
9360         }
9361
9362         /* Update Freesync settings. */
9363         get_freesync_config_for_crtc(dm_new_crtc_state,
9364                                      dm_new_conn_state);
9365
9366         return ret;
9367
9368 fail:
9369         if (new_stream)
9370                 dc_stream_release(new_stream);
9371         return ret;
9372 }
9373
9374 static bool should_reset_plane(struct drm_atomic_state *state,
9375                                struct drm_plane *plane,
9376                                struct drm_plane_state *old_plane_state,
9377                                struct drm_plane_state *new_plane_state)
9378 {
9379         struct drm_plane *other;
9380         struct drm_plane_state *old_other_state, *new_other_state;
9381         struct drm_crtc_state *new_crtc_state;
9382         int i;
9383
9384         /*
9385          * TODO: Remove this hack once the checks below are sufficient
9386          * enough to determine when we need to reset all the planes on
9387          * the stream.
9388          */
9389         if (state->allow_modeset)
9390                 return true;
9391
9392         /* Exit early if we know that we're adding or removing the plane. */
9393         if (old_plane_state->crtc != new_plane_state->crtc)
9394                 return true;
9395
9396         /* old crtc == new_crtc == NULL, plane not in context. */
9397         if (!new_plane_state->crtc)
9398                 return false;
9399
9400         new_crtc_state =
9401                 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
9402
9403         if (!new_crtc_state)
9404                 return true;
9405
9406         /* CRTC Degamma changes currently require us to recreate planes. */
9407         if (new_crtc_state->color_mgmt_changed)
9408                 return true;
9409
9410         if (drm_atomic_crtc_needs_modeset(new_crtc_state))
9411                 return true;
9412
9413         /*
9414          * If there are any new primary or overlay planes being added or
9415          * removed then the z-order can potentially change. To ensure
9416          * correct z-order and pipe acquisition the current DC architecture
9417          * requires us to remove and recreate all existing planes.
9418          *
9419          * TODO: Come up with a more elegant solution for this.
9420          */
9421         for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
9422                 struct amdgpu_framebuffer *old_afb, *new_afb;
9423                 if (other->type == DRM_PLANE_TYPE_CURSOR)
9424                         continue;
9425
9426                 if (old_other_state->crtc != new_plane_state->crtc &&
9427                     new_other_state->crtc != new_plane_state->crtc)
9428                         continue;
9429
9430                 if (old_other_state->crtc != new_other_state->crtc)
9431                         return true;
9432
9433                 /* Src/dst size and scaling updates. */
9434                 if (old_other_state->src_w != new_other_state->src_w ||
9435                     old_other_state->src_h != new_other_state->src_h ||
9436                     old_other_state->crtc_w != new_other_state->crtc_w ||
9437                     old_other_state->crtc_h != new_other_state->crtc_h)
9438                         return true;
9439
9440                 /* Rotation / mirroring updates. */
9441                 if (old_other_state->rotation != new_other_state->rotation)
9442                         return true;
9443
9444                 /* Blending updates. */
9445                 if (old_other_state->pixel_blend_mode !=
9446                     new_other_state->pixel_blend_mode)
9447                         return true;
9448
9449                 /* Alpha updates. */
9450                 if (old_other_state->alpha != new_other_state->alpha)
9451                         return true;
9452
9453                 /* Colorspace changes. */
9454                 if (old_other_state->color_range != new_other_state->color_range ||
9455                     old_other_state->color_encoding != new_other_state->color_encoding)
9456                         return true;
9457
9458                 /* Framebuffer checks fall at the end. */
9459                 if (!old_other_state->fb || !new_other_state->fb)
9460                         continue;
9461
9462                 /* Pixel format changes can require bandwidth updates. */
9463                 if (old_other_state->fb->format != new_other_state->fb->format)
9464                         return true;
9465
9466                 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb;
9467                 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb;
9468
9469                 /* Tiling and DCC changes also require bandwidth updates. */
9470                 if (old_afb->tiling_flags != new_afb->tiling_flags ||
9471                     old_afb->base.modifier != new_afb->base.modifier)
9472                         return true;
9473         }
9474
9475         return false;
9476 }
9477
9478 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,
9479                               struct drm_plane_state *new_plane_state,
9480                               struct drm_framebuffer *fb)
9481 {
9482         struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev);
9483         struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
9484         unsigned int pitch;
9485         bool linear;
9486
9487         if (fb->width > new_acrtc->max_cursor_width ||
9488             fb->height > new_acrtc->max_cursor_height) {
9489                 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n",
9490                                  new_plane_state->fb->width,
9491                                  new_plane_state->fb->height);
9492                 return -EINVAL;
9493         }
9494         if (new_plane_state->src_w != fb->width << 16 ||
9495             new_plane_state->src_h != fb->height << 16) {
9496                 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9497                 return -EINVAL;
9498         }
9499
9500         /* Pitch in pixels */
9501         pitch = fb->pitches[0] / fb->format->cpp[0];
9502
9503         if (fb->width != pitch) {
9504                 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d",
9505                                  fb->width, pitch);
9506                 return -EINVAL;
9507         }
9508
9509         switch (pitch) {
9510         case 64:
9511         case 128:
9512         case 256:
9513                 /* FB pitch is supported by cursor plane */
9514                 break;
9515         default:
9516                 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch);
9517                 return -EINVAL;
9518         }
9519
9520         /* Core DRM takes care of checking FB modifiers, so we only need to
9521          * check tiling flags when the FB doesn't have a modifier. */
9522         if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) {
9523                 if (adev->family < AMDGPU_FAMILY_AI) {
9524                         linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &&
9525                                  AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &&
9526                                  AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0;
9527                 } else {
9528                         linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;
9529                 }
9530                 if (!linear) {
9531                         DRM_DEBUG_ATOMIC("Cursor FB not linear");
9532                         return -EINVAL;
9533                 }
9534         }
9535
9536         return 0;
9537 }
9538
9539 static int dm_update_plane_state(struct dc *dc,
9540                                  struct drm_atomic_state *state,
9541                                  struct drm_plane *plane,
9542                                  struct drm_plane_state *old_plane_state,
9543                                  struct drm_plane_state *new_plane_state,
9544                                  bool enable,
9545                                  bool *lock_and_validation_needed,
9546                                  bool *is_top_most_overlay)
9547 {
9548
9549         struct dm_atomic_state *dm_state = NULL;
9550         struct drm_crtc *new_plane_crtc, *old_plane_crtc;
9551         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9552         struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
9553         struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
9554         struct amdgpu_crtc *new_acrtc;
9555         bool needs_reset;
9556         int ret = 0;
9557
9558
9559         new_plane_crtc = new_plane_state->crtc;
9560         old_plane_crtc = old_plane_state->crtc;
9561         dm_new_plane_state = to_dm_plane_state(new_plane_state);
9562         dm_old_plane_state = to_dm_plane_state(old_plane_state);
9563
9564         if (plane->type == DRM_PLANE_TYPE_CURSOR) {
9565                 if (!enable || !new_plane_crtc ||
9566                         drm_atomic_plane_disabling(plane->state, new_plane_state))
9567                         return 0;
9568
9569                 new_acrtc = to_amdgpu_crtc(new_plane_crtc);
9570
9571                 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) {
9572                         DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9573                         return -EINVAL;
9574                 }
9575
9576                 if (new_plane_state->fb) {
9577                         ret = dm_check_cursor_fb(new_acrtc, new_plane_state,
9578                                                  new_plane_state->fb);
9579                         if (ret)
9580                                 return ret;
9581                 }
9582
9583                 return 0;
9584         }
9585
9586         needs_reset = should_reset_plane(state, plane, old_plane_state,
9587                                          new_plane_state);
9588
9589         /* Remove any changed/removed planes */
9590         if (!enable) {
9591                 if (!needs_reset)
9592                         return 0;
9593
9594                 if (!old_plane_crtc)
9595                         return 0;
9596
9597                 old_crtc_state = drm_atomic_get_old_crtc_state(
9598                                 state, old_plane_crtc);
9599                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9600
9601                 if (!dm_old_crtc_state->stream)
9602                         return 0;
9603
9604                 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
9605                                 plane->base.id, old_plane_crtc->base.id);
9606
9607                 ret = dm_atomic_get_state(state, &dm_state);
9608                 if (ret)
9609                         return ret;
9610
9611                 if (!dc_remove_plane_from_context(
9612                                 dc,
9613                                 dm_old_crtc_state->stream,
9614                                 dm_old_plane_state->dc_state,
9615                                 dm_state->context)) {
9616
9617                         return -EINVAL;
9618                 }
9619
9620
9621                 dc_plane_state_release(dm_old_plane_state->dc_state);
9622                 dm_new_plane_state->dc_state = NULL;
9623
9624                 *lock_and_validation_needed = true;
9625
9626         } else { /* Add new planes */
9627                 struct dc_plane_state *dc_new_plane_state;
9628
9629                 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
9630                         return 0;
9631
9632                 if (!new_plane_crtc)
9633                         return 0;
9634
9635                 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
9636                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9637
9638                 if (!dm_new_crtc_state->stream)
9639                         return 0;
9640
9641                 if (!needs_reset)
9642                         return 0;
9643
9644                 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state);
9645                 if (ret)
9646                         return ret;
9647
9648                 WARN_ON(dm_new_plane_state->dc_state);
9649
9650                 dc_new_plane_state = dc_create_plane_state(dc);
9651                 if (!dc_new_plane_state)
9652                         return -ENOMEM;
9653
9654                 /* Block top most plane from being a video plane */
9655                 if (plane->type == DRM_PLANE_TYPE_OVERLAY) {
9656                         if (is_video_format(new_plane_state->fb->format->format) && *is_top_most_overlay)
9657                                 return -EINVAL;
9658                         else
9659                                 *is_top_most_overlay = false;
9660                 }
9661
9662                 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n",
9663                                  plane->base.id, new_plane_crtc->base.id);
9664
9665                 ret = fill_dc_plane_attributes(
9666                         drm_to_adev(new_plane_crtc->dev),
9667                         dc_new_plane_state,
9668                         new_plane_state,
9669                         new_crtc_state);
9670                 if (ret) {
9671                         dc_plane_state_release(dc_new_plane_state);
9672                         return ret;
9673                 }
9674
9675                 ret = dm_atomic_get_state(state, &dm_state);
9676                 if (ret) {
9677                         dc_plane_state_release(dc_new_plane_state);
9678                         return ret;
9679                 }
9680
9681                 /*
9682                  * Any atomic check errors that occur after this will
9683                  * not need a release. The plane state will be attached
9684                  * to the stream, and therefore part of the atomic
9685                  * state. It'll be released when the atomic state is
9686                  * cleaned.
9687                  */
9688                 if (!dc_add_plane_to_context(
9689                                 dc,
9690                                 dm_new_crtc_state->stream,
9691                                 dc_new_plane_state,
9692                                 dm_state->context)) {
9693
9694                         dc_plane_state_release(dc_new_plane_state);
9695                         return -EINVAL;
9696                 }
9697
9698                 dm_new_plane_state->dc_state = dc_new_plane_state;
9699
9700                 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY);
9701
9702                 /* Tell DC to do a full surface update every time there
9703                  * is a plane change. Inefficient, but works for now.
9704                  */
9705                 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
9706
9707                 *lock_and_validation_needed = true;
9708         }
9709
9710
9711         return ret;
9712 }
9713
9714 static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state,
9715                                        int *src_w, int *src_h)
9716 {
9717         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
9718         case DRM_MODE_ROTATE_90:
9719         case DRM_MODE_ROTATE_270:
9720                 *src_w = plane_state->src_h >> 16;
9721                 *src_h = plane_state->src_w >> 16;
9722                 break;
9723         case DRM_MODE_ROTATE_0:
9724         case DRM_MODE_ROTATE_180:
9725         default:
9726                 *src_w = plane_state->src_w >> 16;
9727                 *src_h = plane_state->src_h >> 16;
9728                 break;
9729         }
9730 }
9731
9732 static int dm_check_crtc_cursor(struct drm_atomic_state *state,
9733                                 struct drm_crtc *crtc,
9734                                 struct drm_crtc_state *new_crtc_state)
9735 {
9736         struct drm_plane *cursor = crtc->cursor, *underlying;
9737         struct drm_plane_state *new_cursor_state, *new_underlying_state;
9738         int i;
9739         int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h;
9740         int cursor_src_w, cursor_src_h;
9741         int underlying_src_w, underlying_src_h;
9742
9743         /* On DCE and DCN there is no dedicated hardware cursor plane. We get a
9744          * cursor per pipe but it's going to inherit the scaling and
9745          * positioning from the underlying pipe. Check the cursor plane's
9746          * blending properties match the underlying planes'. */
9747
9748         new_cursor_state = drm_atomic_get_new_plane_state(state, cursor);
9749         if (!new_cursor_state || !new_cursor_state->fb) {
9750                 return 0;
9751         }
9752
9753         dm_get_oriented_plane_size(new_cursor_state, &cursor_src_w, &cursor_src_h);
9754         cursor_scale_w = new_cursor_state->crtc_w * 1000 / cursor_src_w;
9755         cursor_scale_h = new_cursor_state->crtc_h * 1000 / cursor_src_h;
9756
9757         for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) {
9758                 /* Narrow down to non-cursor planes on the same CRTC as the cursor */
9759                 if (new_underlying_state->crtc != crtc || underlying == crtc->cursor)
9760                         continue;
9761
9762                 /* Ignore disabled planes */
9763                 if (!new_underlying_state->fb)
9764                         continue;
9765
9766                 dm_get_oriented_plane_size(new_underlying_state,
9767                                            &underlying_src_w, &underlying_src_h);
9768                 underlying_scale_w = new_underlying_state->crtc_w * 1000 / underlying_src_w;
9769                 underlying_scale_h = new_underlying_state->crtc_h * 1000 / underlying_src_h;
9770
9771                 if (cursor_scale_w != underlying_scale_w ||
9772                     cursor_scale_h != underlying_scale_h) {
9773                         drm_dbg_atomic(crtc->dev,
9774                                        "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n",
9775                                        cursor->base.id, cursor->name, underlying->base.id, underlying->name);
9776                         return -EINVAL;
9777                 }
9778
9779                 /* If this plane covers the whole CRTC, no need to check planes underneath */
9780                 if (new_underlying_state->crtc_x <= 0 &&
9781                     new_underlying_state->crtc_y <= 0 &&
9782                     new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay &&
9783                     new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay)
9784                         break;
9785         }
9786
9787         return 0;
9788 }
9789
9790 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
9791 {
9792         struct drm_connector *connector;
9793         struct drm_connector_state *conn_state, *old_conn_state;
9794         struct amdgpu_dm_connector *aconnector = NULL;
9795         int i;
9796         for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) {
9797                 if (!conn_state->crtc)
9798                         conn_state = old_conn_state;
9799
9800                 if (conn_state->crtc != crtc)
9801                         continue;
9802
9803                 aconnector = to_amdgpu_dm_connector(connector);
9804                 if (!aconnector->mst_output_port || !aconnector->mst_root)
9805                         aconnector = NULL;
9806                 else
9807                         break;
9808         }
9809
9810         if (!aconnector)
9811                 return 0;
9812
9813         return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr);
9814 }
9815
9816 /**
9817  * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
9818  *
9819  * @dev: The DRM device
9820  * @state: The atomic state to commit
9821  *
9822  * Validate that the given atomic state is programmable by DC into hardware.
9823  * This involves constructing a &struct dc_state reflecting the new hardware
9824  * state we wish to commit, then querying DC to see if it is programmable. It's
9825  * important not to modify the existing DC state. Otherwise, atomic_check
9826  * may unexpectedly commit hardware changes.
9827  *
9828  * When validating the DC state, it's important that the right locks are
9829  * acquired. For full updates case which removes/adds/updates streams on one
9830  * CRTC while flipping on another CRTC, acquiring global lock will guarantee
9831  * that any such full update commit will wait for completion of any outstanding
9832  * flip using DRMs synchronization events.
9833  *
9834  * Note that DM adds the affected connectors for all CRTCs in state, when that
9835  * might not seem necessary. This is because DC stream creation requires the
9836  * DC sink, which is tied to the DRM connector state. Cleaning this up should
9837  * be possible but non-trivial - a possible TODO item.
9838  *
9839  * Return: -Error code if validation failed.
9840  */
9841 static int amdgpu_dm_atomic_check(struct drm_device *dev,
9842                                   struct drm_atomic_state *state)
9843 {
9844         struct amdgpu_device *adev = drm_to_adev(dev);
9845         struct dm_atomic_state *dm_state = NULL;
9846         struct dc *dc = adev->dm.dc;
9847         struct drm_connector *connector;
9848         struct drm_connector_state *old_con_state, *new_con_state;
9849         struct drm_crtc *crtc;
9850         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9851         struct drm_plane *plane;
9852         struct drm_plane_state *old_plane_state, *new_plane_state;
9853         enum dc_status status;
9854         int ret, i;
9855         bool lock_and_validation_needed = false;
9856         bool is_top_most_overlay = true;
9857         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9858         struct drm_dp_mst_topology_mgr *mgr;
9859         struct drm_dp_mst_topology_state *mst_state;
9860         struct dsc_mst_fairness_vars vars[MAX_PIPES];
9861
9862         trace_amdgpu_dm_atomic_check_begin(state);
9863
9864         ret = drm_atomic_helper_check_modeset(dev, state);
9865         if (ret) {
9866                 DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n");
9867                 goto fail;
9868         }
9869
9870         /* Check connector changes */
9871         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9872                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
9873                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9874
9875                 /* Skip connectors that are disabled or part of modeset already. */
9876                 if (!new_con_state->crtc)
9877                         continue;
9878
9879                 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc);
9880                 if (IS_ERR(new_crtc_state)) {
9881                         DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n");
9882                         ret = PTR_ERR(new_crtc_state);
9883                         goto fail;
9884                 }
9885
9886                 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level ||
9887                     dm_old_con_state->scaling != dm_new_con_state->scaling)
9888                         new_crtc_state->connectors_changed = true;
9889         }
9890
9891         if (dc_resource_is_dsc_encoding_supported(dc)) {
9892                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9893                         if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9894                                 ret = add_affected_mst_dsc_crtcs(state, crtc);
9895                                 if (ret) {
9896                                         DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n");
9897                                         goto fail;
9898                                 }
9899                         }
9900                 }
9901         }
9902         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9903                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9904
9905                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
9906                     !new_crtc_state->color_mgmt_changed &&
9907                     old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled &&
9908                         dm_old_crtc_state->dsc_force_changed == false)
9909                         continue;
9910
9911                 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state);
9912                 if (ret) {
9913                         DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n");
9914                         goto fail;
9915                 }
9916
9917                 if (!new_crtc_state->enable)
9918                         continue;
9919
9920                 ret = drm_atomic_add_affected_connectors(state, crtc);
9921                 if (ret) {
9922                         DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n");
9923                         goto fail;
9924                 }
9925
9926                 ret = drm_atomic_add_affected_planes(state, crtc);
9927                 if (ret) {
9928                         DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n");
9929                         goto fail;
9930                 }
9931
9932                 if (dm_old_crtc_state->dsc_force_changed)
9933                         new_crtc_state->mode_changed = true;
9934         }
9935
9936         /*
9937          * Add all primary and overlay planes on the CRTC to the state
9938          * whenever a plane is enabled to maintain correct z-ordering
9939          * and to enable fast surface updates.
9940          */
9941         drm_for_each_crtc(crtc, dev) {
9942                 bool modified = false;
9943
9944                 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
9945                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
9946                                 continue;
9947
9948                         if (new_plane_state->crtc == crtc ||
9949                             old_plane_state->crtc == crtc) {
9950                                 modified = true;
9951                                 break;
9952                         }
9953                 }
9954
9955                 if (!modified)
9956                         continue;
9957
9958                 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
9959                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
9960                                 continue;
9961
9962                         new_plane_state =
9963                                 drm_atomic_get_plane_state(state, plane);
9964
9965                         if (IS_ERR(new_plane_state)) {
9966                                 ret = PTR_ERR(new_plane_state);
9967                                 DRM_DEBUG_DRIVER("new_plane_state is BAD\n");
9968                                 goto fail;
9969                         }
9970                 }
9971         }
9972
9973         /*
9974          * DC consults the zpos (layer_index in DC terminology) to determine the
9975          * hw plane on which to enable the hw cursor (see
9976          * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in
9977          * atomic state, so call drm helper to normalize zpos.
9978          */
9979         ret = drm_atomic_normalize_zpos(dev, state);
9980         if (ret) {
9981                 drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n");
9982                 goto fail;
9983         }
9984
9985         /* Remove exiting planes if they are modified */
9986         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
9987                 ret = dm_update_plane_state(dc, state, plane,
9988                                             old_plane_state,
9989                                             new_plane_state,
9990                                             false,
9991                                             &lock_and_validation_needed,
9992                                             &is_top_most_overlay);
9993                 if (ret) {
9994                         DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
9995                         goto fail;
9996                 }
9997         }
9998
9999         /* Disable all crtcs which require disable */
10000         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10001                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10002                                            old_crtc_state,
10003                                            new_crtc_state,
10004                                            false,
10005                                            &lock_and_validation_needed);
10006                 if (ret) {
10007                         DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n");
10008                         goto fail;
10009                 }
10010         }
10011
10012         /* Enable all crtcs which require enable */
10013         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10014                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10015                                            old_crtc_state,
10016                                            new_crtc_state,
10017                                            true,
10018                                            &lock_and_validation_needed);
10019                 if (ret) {
10020                         DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n");
10021                         goto fail;
10022                 }
10023         }
10024
10025         /* Add new/modified planes */
10026         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10027                 ret = dm_update_plane_state(dc, state, plane,
10028                                             old_plane_state,
10029                                             new_plane_state,
10030                                             true,
10031                                             &lock_and_validation_needed,
10032                                             &is_top_most_overlay);
10033                 if (ret) {
10034                         DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10035                         goto fail;
10036                 }
10037         }
10038
10039         if (dc_resource_is_dsc_encoding_supported(dc)) {
10040                 ret = pre_validate_dsc(state, &dm_state, vars);
10041                 if (ret != 0)
10042                         goto fail;
10043         }
10044
10045         /* Run this here since we want to validate the streams we created */
10046         ret = drm_atomic_helper_check_planes(dev, state);
10047         if (ret) {
10048                 DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n");
10049                 goto fail;
10050         }
10051
10052         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10053                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
10054                 if (dm_new_crtc_state->mpo_requested)
10055                         DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc);
10056         }
10057
10058         /* Check cursor planes scaling */
10059         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10060                 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state);
10061                 if (ret) {
10062                         DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n");
10063                         goto fail;
10064                 }
10065         }
10066
10067         if (state->legacy_cursor_update) {
10068                 /*
10069                  * This is a fast cursor update coming from the plane update
10070                  * helper, check if it can be done asynchronously for better
10071                  * performance.
10072                  */
10073                 state->async_update =
10074                         !drm_atomic_helper_async_check(dev, state);
10075
10076                 /*
10077                  * Skip the remaining global validation if this is an async
10078                  * update. Cursor updates can be done without affecting
10079                  * state or bandwidth calcs and this avoids the performance
10080                  * penalty of locking the private state object and
10081                  * allocating a new dc_state.
10082                  */
10083                 if (state->async_update)
10084                         return 0;
10085         }
10086
10087         /* Check scaling and underscan changes*/
10088         /* TODO Removed scaling changes validation due to inability to commit
10089          * new stream into context w\o causing full reset. Need to
10090          * decide how to handle.
10091          */
10092         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
10093                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
10094                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10095                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
10096
10097                 /* Skip any modesets/resets */
10098                 if (!acrtc || drm_atomic_crtc_needs_modeset(
10099                                 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
10100                         continue;
10101
10102                 /* Skip any thing not scale or underscan changes */
10103                 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
10104                         continue;
10105
10106                 lock_and_validation_needed = true;
10107         }
10108
10109         /* set the slot info for each mst_state based on the link encoding format */
10110         for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
10111                 struct amdgpu_dm_connector *aconnector;
10112                 struct drm_connector *connector;
10113                 struct drm_connector_list_iter iter;
10114                 u8 link_coding_cap;
10115
10116                 drm_connector_list_iter_begin(dev, &iter);
10117                 drm_for_each_connector_iter(connector, &iter) {
10118                         if (connector->index == mst_state->mgr->conn_base_id) {
10119                                 aconnector = to_amdgpu_dm_connector(connector);
10120                                 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link);
10121                                 drm_dp_mst_update_slots(mst_state, link_coding_cap);
10122
10123                                 break;
10124                         }
10125                 }
10126                 drm_connector_list_iter_end(&iter);
10127         }
10128
10129         /**
10130          * Streams and planes are reset when there are changes that affect
10131          * bandwidth. Anything that affects bandwidth needs to go through
10132          * DC global validation to ensure that the configuration can be applied
10133          * to hardware.
10134          *
10135          * We have to currently stall out here in atomic_check for outstanding
10136          * commits to finish in this case because our IRQ handlers reference
10137          * DRM state directly - we can end up disabling interrupts too early
10138          * if we don't.
10139          *
10140          * TODO: Remove this stall and drop DM state private objects.
10141          */
10142         if (lock_and_validation_needed) {
10143                 ret = dm_atomic_get_state(state, &dm_state);
10144                 if (ret) {
10145                         DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n");
10146                         goto fail;
10147                 }
10148
10149                 ret = do_aquire_global_lock(dev, state);
10150                 if (ret) {
10151                         DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n");
10152                         goto fail;
10153                 }
10154
10155                 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars);
10156                 if (ret) {
10157                         DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n");
10158                         goto fail;
10159                 }
10160
10161                 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars);
10162                 if (ret) {
10163                         DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n");
10164                         goto fail;
10165                 }
10166
10167                 /*
10168                  * Perform validation of MST topology in the state:
10169                  * We need to perform MST atomic check before calling
10170                  * dc_validate_global_state(), or there is a chance
10171                  * to get stuck in an infinite loop and hang eventually.
10172                  */
10173                 ret = drm_dp_mst_atomic_check(state);
10174                 if (ret) {
10175                         DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n");
10176                         goto fail;
10177                 }
10178                 status = dc_validate_global_state(dc, dm_state->context, true);
10179                 if (status != DC_OK) {
10180                         DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)",
10181                                        dc_status_to_str(status), status);
10182                         ret = -EINVAL;
10183                         goto fail;
10184                 }
10185         } else {
10186                 /*
10187                  * The commit is a fast update. Fast updates shouldn't change
10188                  * the DC context, affect global validation, and can have their
10189                  * commit work done in parallel with other commits not touching
10190                  * the same resource. If we have a new DC context as part of
10191                  * the DM atomic state from validation we need to free it and
10192                  * retain the existing one instead.
10193                  *
10194                  * Furthermore, since the DM atomic state only contains the DC
10195                  * context and can safely be annulled, we can free the state
10196                  * and clear the associated private object now to free
10197                  * some memory and avoid a possible use-after-free later.
10198                  */
10199
10200                 for (i = 0; i < state->num_private_objs; i++) {
10201                         struct drm_private_obj *obj = state->private_objs[i].ptr;
10202
10203                         if (obj->funcs == adev->dm.atomic_obj.funcs) {
10204                                 int j = state->num_private_objs-1;
10205
10206                                 dm_atomic_destroy_state(obj,
10207                                                 state->private_objs[i].state);
10208
10209                                 /* If i is not at the end of the array then the
10210                                  * last element needs to be moved to where i was
10211                                  * before the array can safely be truncated.
10212                                  */
10213                                 if (i != j)
10214                                         state->private_objs[i] =
10215                                                 state->private_objs[j];
10216
10217                                 state->private_objs[j].ptr = NULL;
10218                                 state->private_objs[j].state = NULL;
10219                                 state->private_objs[j].old_state = NULL;
10220                                 state->private_objs[j].new_state = NULL;
10221
10222                                 state->num_private_objs = j;
10223                                 break;
10224                         }
10225                 }
10226         }
10227
10228         /* Store the overall update type for use later in atomic check. */
10229         for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
10230                 struct dm_crtc_state *dm_new_crtc_state =
10231                         to_dm_crtc_state(new_crtc_state);
10232
10233                 dm_new_crtc_state->update_type = lock_and_validation_needed ?
10234                                                          UPDATE_TYPE_FULL :
10235                                                          UPDATE_TYPE_FAST;
10236         }
10237
10238         /* Must be success */
10239         WARN_ON(ret);
10240
10241         trace_amdgpu_dm_atomic_check_finish(state, ret);
10242
10243         return ret;
10244
10245 fail:
10246         if (ret == -EDEADLK)
10247                 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
10248         else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
10249                 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
10250         else
10251                 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
10252
10253         trace_amdgpu_dm_atomic_check_finish(state, ret);
10254
10255         return ret;
10256 }
10257
10258 static bool is_dp_capable_without_timing_msa(struct dc *dc,
10259                                              struct amdgpu_dm_connector *amdgpu_dm_connector)
10260 {
10261         u8 dpcd_data;
10262         bool capable = false;
10263
10264         if (amdgpu_dm_connector->dc_link &&
10265                 dm_helpers_dp_read_dpcd(
10266                                 NULL,
10267                                 amdgpu_dm_connector->dc_link,
10268                                 DP_DOWN_STREAM_PORT_COUNT,
10269                                 &dpcd_data,
10270                                 sizeof(dpcd_data))) {
10271                 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
10272         }
10273
10274         return capable;
10275 }
10276
10277 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,
10278                 unsigned int offset,
10279                 unsigned int total_length,
10280                 u8 *data,
10281                 unsigned int length,
10282                 struct amdgpu_hdmi_vsdb_info *vsdb)
10283 {
10284         bool res;
10285         union dmub_rb_cmd cmd;
10286         struct dmub_cmd_send_edid_cea *input;
10287         struct dmub_cmd_edid_cea_output *output;
10288
10289         if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES)
10290                 return false;
10291
10292         memset(&cmd, 0, sizeof(cmd));
10293
10294         input = &cmd.edid_cea.data.input;
10295
10296         cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA;
10297         cmd.edid_cea.header.sub_type = 0;
10298         cmd.edid_cea.header.payload_bytes =
10299                 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header);
10300         input->offset = offset;
10301         input->length = length;
10302         input->cea_total_length = total_length;
10303         memcpy(input->payload, data, length);
10304
10305         res = dc_dmub_srv_cmd_with_reply_data(dm->dc->ctx->dmub_srv, &cmd);
10306         if (!res) {
10307                 DRM_ERROR("EDID CEA parser failed\n");
10308                 return false;
10309         }
10310
10311         output = &cmd.edid_cea.data.output;
10312
10313         if (output->type == DMUB_CMD__EDID_CEA_ACK) {
10314                 if (!output->ack.success) {
10315                         DRM_ERROR("EDID CEA ack failed at offset %d\n",
10316                                         output->ack.offset);
10317                 }
10318         } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) {
10319                 if (!output->amd_vsdb.vsdb_found)
10320                         return false;
10321
10322                 vsdb->freesync_supported = output->amd_vsdb.freesync_supported;
10323                 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version;
10324                 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate;
10325                 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate;
10326         } else {
10327                 DRM_WARN("Unknown EDID CEA parser results\n");
10328                 return false;
10329         }
10330
10331         return true;
10332 }
10333
10334 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm,
10335                 u8 *edid_ext, int len,
10336                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10337 {
10338         int i;
10339
10340         /* send extension block to DMCU for parsing */
10341         for (i = 0; i < len; i += 8) {
10342                 bool res;
10343                 int offset;
10344
10345                 /* send 8 bytes a time */
10346                 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8))
10347                         return false;
10348
10349                 if (i+8 == len) {
10350                         /* EDID block sent completed, expect result */
10351                         int version, min_rate, max_rate;
10352
10353                         res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate);
10354                         if (res) {
10355                                 /* amd vsdb found */
10356                                 vsdb_info->freesync_supported = 1;
10357                                 vsdb_info->amd_vsdb_version = version;
10358                                 vsdb_info->min_refresh_rate_hz = min_rate;
10359                                 vsdb_info->max_refresh_rate_hz = max_rate;
10360                                 return true;
10361                         }
10362                         /* not amd vsdb */
10363                         return false;
10364                 }
10365
10366                 /* check for ack*/
10367                 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset);
10368                 if (!res)
10369                         return false;
10370         }
10371
10372         return false;
10373 }
10374
10375 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm,
10376                 u8 *edid_ext, int len,
10377                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10378 {
10379         int i;
10380
10381         /* send extension block to DMCU for parsing */
10382         for (i = 0; i < len; i += 8) {
10383                 /* send 8 bytes a time */
10384                 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info))
10385                         return false;
10386         }
10387
10388         return vsdb_info->freesync_supported;
10389 }
10390
10391 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
10392                 u8 *edid_ext, int len,
10393                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10394 {
10395         struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
10396         bool ret;
10397
10398         mutex_lock(&adev->dm.dc_lock);
10399         if (adev->dm.dmub_srv)
10400                 ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info);
10401         else
10402                 ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info);
10403         mutex_unlock(&adev->dm.dc_lock);
10404         return ret;
10405 }
10406
10407 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
10408                 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
10409 {
10410         u8 *edid_ext = NULL;
10411         int i;
10412         bool valid_vsdb_found = false;
10413
10414         /*----- drm_find_cea_extension() -----*/
10415         /* No EDID or EDID extensions */
10416         if (edid == NULL || edid->extensions == 0)
10417                 return -ENODEV;
10418
10419         /* Find CEA extension */
10420         for (i = 0; i < edid->extensions; i++) {
10421                 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1);
10422                 if (edid_ext[0] == CEA_EXT)
10423                         break;
10424         }
10425
10426         if (i == edid->extensions)
10427                 return -ENODEV;
10428
10429         /*----- cea_db_offsets() -----*/
10430         if (edid_ext[0] != CEA_EXT)
10431                 return -ENODEV;
10432
10433         valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info);
10434
10435         return valid_vsdb_found ? i : -ENODEV;
10436 }
10437
10438 /**
10439  * amdgpu_dm_update_freesync_caps - Update Freesync capabilities
10440  *
10441  * @connector: Connector to query.
10442  * @edid: EDID from monitor
10443  *
10444  * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep
10445  * track of some of the display information in the internal data struct used by
10446  * amdgpu_dm. This function checks which type of connector we need to set the
10447  * FreeSync parameters.
10448  */
10449 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
10450                                     struct edid *edid)
10451 {
10452         int i = 0;
10453         struct detailed_timing *timing;
10454         struct detailed_non_pixel *data;
10455         struct detailed_data_monitor_range *range;
10456         struct amdgpu_dm_connector *amdgpu_dm_connector =
10457                         to_amdgpu_dm_connector(connector);
10458         struct dm_connector_state *dm_con_state = NULL;
10459         struct dc_sink *sink;
10460
10461         struct drm_device *dev = connector->dev;
10462         struct amdgpu_device *adev = drm_to_adev(dev);
10463         struct amdgpu_hdmi_vsdb_info vsdb_info = {0};
10464         bool freesync_capable = false;
10465         enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE;
10466
10467         if (!connector->state) {
10468                 DRM_ERROR("%s - Connector has no state", __func__);
10469                 goto update;
10470         }
10471
10472         sink = amdgpu_dm_connector->dc_sink ?
10473                 amdgpu_dm_connector->dc_sink :
10474                 amdgpu_dm_connector->dc_em_sink;
10475
10476         if (!edid || !sink) {
10477                 dm_con_state = to_dm_connector_state(connector->state);
10478
10479                 amdgpu_dm_connector->min_vfreq = 0;
10480                 amdgpu_dm_connector->max_vfreq = 0;
10481                 amdgpu_dm_connector->pixel_clock_mhz = 0;
10482                 connector->display_info.monitor_range.min_vfreq = 0;
10483                 connector->display_info.monitor_range.max_vfreq = 0;
10484                 freesync_capable = false;
10485
10486                 goto update;
10487         }
10488
10489         dm_con_state = to_dm_connector_state(connector->state);
10490
10491         if (!adev->dm.freesync_module)
10492                 goto update;
10493
10494         if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
10495                 || sink->sink_signal == SIGNAL_TYPE_EDP) {
10496                 bool edid_check_required = false;
10497
10498                 if (edid) {
10499                         edid_check_required = is_dp_capable_without_timing_msa(
10500                                                 adev->dm.dc,
10501                                                 amdgpu_dm_connector);
10502                 }
10503
10504                 if (edid_check_required == true && (edid->version > 1 ||
10505                    (edid->version == 1 && edid->revision > 1))) {
10506                         for (i = 0; i < 4; i++) {
10507
10508                                 timing  = &edid->detailed_timings[i];
10509                                 data    = &timing->data.other_data;
10510                                 range   = &data->data.range;
10511                                 /*
10512                                  * Check if monitor has continuous frequency mode
10513                                  */
10514                                 if (data->type != EDID_DETAIL_MONITOR_RANGE)
10515                                         continue;
10516                                 /*
10517                                  * Check for flag range limits only. If flag == 1 then
10518                                  * no additional timing information provided.
10519                                  * Default GTF, GTF Secondary curve and CVT are not
10520                                  * supported
10521                                  */
10522                                 if (range->flags != 1)
10523                                         continue;
10524
10525                                 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
10526                                 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
10527                                 amdgpu_dm_connector->pixel_clock_mhz =
10528                                         range->pixel_clock_mhz * 10;
10529
10530                                 connector->display_info.monitor_range.min_vfreq = range->min_vfreq;
10531                                 connector->display_info.monitor_range.max_vfreq = range->max_vfreq;
10532
10533                                 break;
10534                         }
10535
10536                         if (amdgpu_dm_connector->max_vfreq -
10537                             amdgpu_dm_connector->min_vfreq > 10) {
10538
10539                                 freesync_capable = true;
10540                         }
10541                 }
10542         } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
10543                 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10544                 if (i >= 0 && vsdb_info.freesync_supported) {
10545                         timing  = &edid->detailed_timings[i];
10546                         data    = &timing->data.other_data;
10547
10548                         amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10549                         amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10550                         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10551                                 freesync_capable = true;
10552
10553                         connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10554                         connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10555                 }
10556         }
10557
10558         as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link);
10559
10560         if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {
10561                 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10562                 if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) {
10563
10564                         amdgpu_dm_connector->pack_sdp_v1_3 = true;
10565                         amdgpu_dm_connector->as_type = as_type;
10566                         amdgpu_dm_connector->vsdb_info = vsdb_info;
10567
10568                         amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10569                         amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10570                         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10571                                 freesync_capable = true;
10572
10573                         connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10574                         connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10575                 }
10576         }
10577
10578 update:
10579         if (dm_con_state)
10580                 dm_con_state->freesync_capable = freesync_capable;
10581
10582         if (connector->vrr_capable_property)
10583                 drm_connector_set_vrr_capable_property(connector,
10584                                                        freesync_capable);
10585 }
10586
10587 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
10588 {
10589         struct amdgpu_device *adev = drm_to_adev(dev);
10590         struct dc *dc = adev->dm.dc;
10591         int i;
10592
10593         mutex_lock(&adev->dm.dc_lock);
10594         if (dc->current_state) {
10595                 for (i = 0; i < dc->current_state->stream_count; ++i)
10596                         dc->current_state->streams[i]
10597                                 ->triggered_crtc_reset.enabled =
10598                                 adev->dm.force_timing_sync;
10599
10600                 dm_enable_per_frame_crtc_master_sync(dc->current_state);
10601                 dc_trigger_sync(dc, dc->current_state);
10602         }
10603         mutex_unlock(&adev->dm.dc_lock);
10604 }
10605
10606 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
10607                        u32 value, const char *func_name)
10608 {
10609 #ifdef DM_CHECK_ADDR_0
10610         if (address == 0) {
10611                 DC_ERR("invalid register write. address = 0");
10612                 return;
10613         }
10614 #endif
10615         cgs_write_register(ctx->cgs_device, address, value);
10616         trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
10617 }
10618
10619 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
10620                           const char *func_name)
10621 {
10622         u32 value;
10623 #ifdef DM_CHECK_ADDR_0
10624         if (address == 0) {
10625                 DC_ERR("invalid register read; address = 0\n");
10626                 return 0;
10627         }
10628 #endif
10629
10630         if (ctx->dmub_srv &&
10631             ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
10632             !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
10633                 ASSERT(false);
10634                 return 0;
10635         }
10636
10637         value = cgs_read_register(ctx->cgs_device, address);
10638
10639         trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
10640
10641         return value;
10642 }
10643
10644 int amdgpu_dm_process_dmub_aux_transfer_sync(
10645                 struct dc_context *ctx,
10646                 unsigned int link_index,
10647                 struct aux_payload *payload,
10648                 enum aux_return_code_type *operation_result)
10649 {
10650         struct amdgpu_device *adev = ctx->driver_context;
10651         struct dmub_notification *p_notify = adev->dm.dmub_notify;
10652         int ret = -1;
10653
10654         mutex_lock(&adev->dm.dpia_aux_lock);
10655         if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) {
10656                 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE;
10657                 goto out;
10658         }
10659
10660         if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10661                 DRM_ERROR("wait_for_completion_timeout timeout!");
10662                 *operation_result = AUX_RET_ERROR_TIMEOUT;
10663                 goto out;
10664         }
10665
10666         if (p_notify->result != AUX_RET_SUCCESS) {
10667                 /*
10668                  * Transient states before tunneling is enabled could
10669                  * lead to this error. We can ignore this for now.
10670                  */
10671                 if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) {
10672                         DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n",
10673                                         payload->address, payload->length,
10674                                         p_notify->result);
10675                 }
10676                 *operation_result = AUX_RET_ERROR_INVALID_REPLY;
10677                 goto out;
10678         }
10679
10680
10681         payload->reply[0] = adev->dm.dmub_notify->aux_reply.command;
10682         if (!payload->write && p_notify->aux_reply.length &&
10683                         (payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) {
10684
10685                 if (payload->length != p_notify->aux_reply.length) {
10686                         DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n",
10687                                 p_notify->aux_reply.length,
10688                                         payload->address, payload->length);
10689                         *operation_result = AUX_RET_ERROR_INVALID_REPLY;
10690                         goto out;
10691                 }
10692
10693                 memcpy(payload->data, p_notify->aux_reply.data,
10694                                 p_notify->aux_reply.length);
10695         }
10696
10697         /* success */
10698         ret = p_notify->aux_reply.length;
10699         *operation_result = p_notify->result;
10700 out:
10701         reinit_completion(&adev->dm.dmub_aux_transfer_done);
10702         mutex_unlock(&adev->dm.dpia_aux_lock);
10703         return ret;
10704 }
10705
10706 int amdgpu_dm_process_dmub_set_config_sync(
10707                 struct dc_context *ctx,
10708                 unsigned int link_index,
10709                 struct set_config_cmd_payload *payload,
10710                 enum set_config_status *operation_result)
10711 {
10712         struct amdgpu_device *adev = ctx->driver_context;
10713         bool is_cmd_complete;
10714         int ret;
10715
10716         mutex_lock(&adev->dm.dpia_aux_lock);
10717         is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc,
10718                         link_index, payload, adev->dm.dmub_notify);
10719
10720         if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10721                 ret = 0;
10722                 *operation_result = adev->dm.dmub_notify->sc_status;
10723         } else {
10724                 DRM_ERROR("wait_for_completion_timeout timeout!");
10725                 ret = -1;
10726                 *operation_result = SET_CONFIG_UNKNOWN_ERROR;
10727         }
10728
10729         if (!is_cmd_complete)
10730                 reinit_completion(&adev->dm.dmub_aux_transfer_done);
10731         mutex_unlock(&adev->dm.dpia_aux_lock);
10732         return ret;
10733 }
10734
10735 /*
10736  * Check whether seamless boot is supported.
10737  *
10738  * So far we only support seamless boot on CHIP_VANGOGH.
10739  * If everything goes well, we may consider expanding
10740  * seamless boot to other ASICs.
10741  */
10742 bool check_seamless_boot_capability(struct amdgpu_device *adev)
10743 {
10744         switch (adev->ip_versions[DCE_HWIP][0]) {
10745         case IP_VERSION(3, 0, 1):
10746                 if (!adev->mman.keep_stolen_vga_memory)
10747                         return true;
10748                 break;
10749         default:
10750                 break;
10751         }
10752
10753         return false;
10754 }