drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 /* The caprices of the preprocessor require that this be declared right here */
  27 #define CREATE_TRACE_POINTS
  28
  29 #include "dm_services_types.h"
  30 #include "dc.h"
  31 #include "dc_link_dp.h"
  32 #include "link_enc_cfg.h"
  33 #include "dc/inc/core_types.h"
  34 #include "dal_asic_id.h"
  35 #include "dmub/dmub_srv.h"
  36 #include "dc/inc/hw/dmcu.h"
  37 #include "dc/inc/hw/abm.h"
  38 #include "dc/dc_dmub_srv.h"
  39 #include "dc/dc_edid_parser.h"
  40 #include "dc/dc_stat.h"
  41 #include "amdgpu_dm_trace.h"
  42
  43 #include "vid.h"
  44 #include "amdgpu.h"
  45 #include "amdgpu_display.h"
  46 #include "amdgpu_ucode.h"
  47 #include "atom.h"
  48 #include "amdgpu_dm.h"
  49 #include "amdgpu_dm_plane.h"
  50 #include "amdgpu_dm_crtc.h"
  51 #ifdef CONFIG_DRM_AMD_DC_HDCP
  52 #include "amdgpu_dm_hdcp.h"
  53 #include <drm/display/drm_hdcp_helper.h>
  54 #endif
  55 #include "amdgpu_pm.h"
  56 #include "amdgpu_atombios.h"
  57
  58 #include "amd_shared.h"
  59 #include "amdgpu_dm_irq.h"
  60 #include "dm_helpers.h"
  61 #include "amdgpu_dm_mst_types.h"
  62 #if defined(CONFIG_DEBUG_FS)
  63 #include "amdgpu_dm_debugfs.h"
  64 #endif
  65 #include "amdgpu_dm_psr.h"
  66
  67 #include "ivsrcid/ivsrcid_vislands30.h"
  68
  69 #include "i2caux_interface.h"
  70 #include <linux/module.h>
  71 #include <linux/moduleparam.h>
  72 #include <linux/types.h>
  73 #include <linux/pm_runtime.h>
  74 #include <linux/pci.h>
  75 #include <linux/firmware.h>
  76 #include <linux/component.h>
  77 #include <linux/dmi.h>
  78
  79 #include <drm/display/drm_dp_mst_helper.h>
  80 #include <drm/display/drm_hdmi_helper.h>
  81 #include <drm/drm_atomic.h>
  82 #include <drm/drm_atomic_uapi.h>
  83 #include <drm/drm_atomic_helper.h>
  84 #include <drm/drm_blend.h>
  85 #include <drm/drm_fourcc.h>
  86 #include <drm/drm_edid.h>
  87 #include <drm/drm_vblank.h>
  88 #include <drm/drm_audio_component.h>
  89 #include <drm/drm_gem_atomic_helper.h>
  90 #include <drm/drm_plane_helper.h>
  91
  92 #include <acpi/video.h>
  93
  94 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
  95
  96 #include "dcn/dcn_1_0_offset.h"
  97 #include "dcn/dcn_1_0_sh_mask.h"
  98 #include "soc15_hw_ip.h"
  99 #include "soc15_common.h"
 100 #include "vega10_ip_offset.h"
 101
 102 #include "gc/gc_11_0_0_offset.h"
 103 #include "gc/gc_11_0_0_sh_mask.h"
 104
 105 #include "modules/inc/mod_freesync.h"
 106 #include "modules/power/power_helpers.h"
 107 #include "modules/inc/mod_info_packet.h"
 108
 109 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
 110 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
 111 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"
 112 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
 113 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
 114 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
 115 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
 116 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
 117 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
 118 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
 119 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"
 120 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
 121 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin"
 122 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);
 123 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin"
 124 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);
 125 #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin"
 126 MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB);
 127 #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin"
 128 MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB);
 129 #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin"
 130 MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB);
 131
 132 #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin"
 133 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB);
 134 #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin"
 135 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB);
 136
 137 #define FIRMWARE_RAVEN_DMCU             "amdgpu/raven_dmcu.bin"
 138 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
 139
 140 #define FIRMWARE_NAVI12_DMCU            "amdgpu/navi12_dmcu.bin"
 141 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);
 142
 143 /* Number of bytes in PSP header for firmware. */
 144 #define PSP_HEADER_BYTES 0x100
 145
 146 /* Number of bytes in PSP footer for firmware. */
 147 #define PSP_FOOTER_BYTES 0x100
 148
 149 /**
 150  * DOC: overview
 151  *
 152  * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
 153  * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM
 154  * requests into DC requests, and DC responses into DRM responses.
 155  *
 156  * The root control structure is &struct amdgpu_display_manager.
 157  */
 158
 159 /* basic init/fini API */
 160 static int amdgpu_dm_init(struct amdgpu_device *adev);
 161 static void amdgpu_dm_fini(struct amdgpu_device *adev);
 162 static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector);
 163
 164 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)
 165 {
 166         switch (link->dpcd_caps.dongle_type) {
 167         case DISPLAY_DONGLE_NONE:
 168                 return DRM_MODE_SUBCONNECTOR_Native;
 169         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
 170                 return DRM_MODE_SUBCONNECTOR_VGA;
 171         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
 172         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 173                 return DRM_MODE_SUBCONNECTOR_DVID;
 174         case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
 175         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 176                 return DRM_MODE_SUBCONNECTOR_HDMIA;
 177         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 178         default:
 179                 return DRM_MODE_SUBCONNECTOR_Unknown;
 180         }
 181 }
 182
 183 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector)
 184 {
 185         struct dc_link *link = aconnector->dc_link;
 186         struct drm_connector *connector = &aconnector->base;
 187         enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
 188
 189         if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
 190                 return;
 191
 192         if (aconnector->dc_sink)
 193                 subconnector = get_subconnector_type(link);
 194
 195         drm_object_property_set_value(&connector->base,
 196                         connector->dev->mode_config.dp_subconnector_property,
 197                         subconnector);
 198 }
 199
 200 /*
 201  * initializes drm_device display related structures, based on the information
 202  * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
 203  * drm_encoder, drm_mode_config
 204  *
 205  * Returns 0 on success
 206  */
 207 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
 208 /* removes and deallocates the drm structures, created by the above function */
 209 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
 210
 211 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
 212                                     struct amdgpu_dm_connector *amdgpu_dm_connector,
 213                                     uint32_t link_index,
 214                                     struct amdgpu_encoder *amdgpu_encoder);
 215 static int amdgpu_dm_encoder_init(struct drm_device *dev,
 216                                   struct amdgpu_encoder *aencoder,
 217                                   uint32_t link_index);
 218
 219 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
 220
 221 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
 222
 223 static int amdgpu_dm_atomic_check(struct drm_device *dev,
 224                                   struct drm_atomic_state *state);
 225
 226 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector);
 227 static void handle_hpd_rx_irq(void *param);
 228
 229 static bool
 230 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
 231                                  struct drm_crtc_state *new_crtc_state);
 232 /*
 233  * dm_vblank_get_counter
 234  *
 235  * @brief
 236  * Get counter for number of vertical blanks
 237  *
 238  * @param
 239  * struct amdgpu_device *adev - [in] desired amdgpu device
 240  * int disp_idx - [in] which CRTC to get the counter from
 241  *
 242  * @return
 243  * Counter for vertical blanks
 244  */
 245 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 246 {
 247         if (crtc >= adev->mode_info.num_crtc)
 248                 return 0;
 249         else {
 250                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 251
 252                 if (acrtc->dm_irq_params.stream == NULL) {
 253                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 254                                   crtc);
 255                         return 0;
 256                 }
 257
 258                 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);
 259         }
 260 }
 261
 262 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 263                                   u32 *vbl, u32 *position)
 264 {
 265         uint32_t v_blank_start, v_blank_end, h_position, v_position;
 266
 267         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 268                 return -EINVAL;
 269         else {
 270                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 271
 272                 if (acrtc->dm_irq_params.stream ==  NULL) {
 273                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 274                                   crtc);
 275                         return 0;
 276                 }
 277
 278                 /*
 279                  * TODO rework base driver to use values directly.
 280                  * for now parse it back into reg-format
 281                  */
 282                 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream,
 283                                          &v_blank_start,
 284                                          &v_blank_end,
 285                                          &h_position,
 286                                          &v_position);
 287
 288                 *position = v_position | (h_position << 16);
 289                 *vbl = v_blank_start | (v_blank_end << 16);
 290         }
 291
 292         return 0;
 293 }
 294
 295 static bool dm_is_idle(void *handle)
 296 {
 297         /* XXX todo */
 298         return true;
 299 }
 300
 301 static int dm_wait_for_idle(void *handle)
 302 {
 303         /* XXX todo */
 304         return 0;
 305 }
 306
 307 static bool dm_check_soft_reset(void *handle)
 308 {
 309         return false;
 310 }
 311
 312 static int dm_soft_reset(void *handle)
 313 {
 314         /* XXX todo */
 315         return 0;
 316 }
 317
 318 static struct amdgpu_crtc *
 319 get_crtc_by_otg_inst(struct amdgpu_device *adev,
 320                      int otg_inst)
 321 {
 322         struct drm_device *dev = adev_to_drm(adev);
 323         struct drm_crtc *crtc;
 324         struct amdgpu_crtc *amdgpu_crtc;
 325
 326         if (WARN_ON(otg_inst == -1))
 327                 return adev->mode_info.crtcs[0];
 328
 329         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 330                 amdgpu_crtc = to_amdgpu_crtc(crtc);
 331
 332                 if (amdgpu_crtc->otg_inst == otg_inst)
 333                         return amdgpu_crtc;
 334         }
 335
 336         return NULL;
 337 }
 338
 339 static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,
 340                                               struct dm_crtc_state *new_state)
 341 {
 342         if (new_state->freesync_config.state ==  VRR_STATE_ACTIVE_FIXED)
 343                 return true;
 344         else if (amdgpu_dm_vrr_active(old_state) != amdgpu_dm_vrr_active(new_state))
 345                 return true;
 346         else
 347                 return false;
 348 }
 349
 350 /**
 351  * dm_pflip_high_irq() - Handle pageflip interrupt
 352  * @interrupt_params: ignored
 353  *
 354  * Handles the pageflip interrupt by notifying all interested parties
 355  * that the pageflip has been completed.
 356  */
 357 static void dm_pflip_high_irq(void *interrupt_params)
 358 {
 359         struct amdgpu_crtc *amdgpu_crtc;
 360         struct common_irq_params *irq_params = interrupt_params;
 361         struct amdgpu_device *adev = irq_params->adev;
 362         unsigned long flags;
 363         struct drm_pending_vblank_event *e;
 364         uint32_t vpos, hpos, v_blank_start, v_blank_end;
 365         bool vrr_active;
 366
 367         amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
 368
 369         /* IRQ could occur when in initial stage */
 370         /* TODO work and BO cleanup */
 371         if (amdgpu_crtc == NULL) {
 372                 DC_LOG_PFLIP("CRTC is null, returning.\n");
 373                 return;
 374         }
 375
 376         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 377
 378         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
 379                 DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
 380                                                  amdgpu_crtc->pflip_status,
 381                                                  AMDGPU_FLIP_SUBMITTED,
 382                                                  amdgpu_crtc->crtc_id,
 383                                                  amdgpu_crtc);
 384                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 385                 return;
 386         }
 387
 388         /* page flip completed. */
 389         e = amdgpu_crtc->event;
 390         amdgpu_crtc->event = NULL;
 391
 392         WARN_ON(!e);
 393
 394         vrr_active = amdgpu_dm_vrr_active_irq(amdgpu_crtc);
 395
 396         /* Fixed refresh rate, or VRR scanout position outside front-porch? */
 397         if (!vrr_active ||
 398             !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start,
 399                                       &v_blank_end, &hpos, &vpos) ||
 400             (vpos < v_blank_start)) {
 401                 /* Update to correct count and vblank timestamp if racing with
 402                  * vblank irq. This also updates to the correct vblank timestamp
 403                  * even in VRR mode, as scanout is past the front-porch atm.
 404                  */
 405                 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
 406
 407                 /* Wake up userspace by sending the pageflip event with proper
 408                  * count and timestamp of vblank of flip completion.
 409                  */
 410                 if (e) {
 411                         drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
 412
 413                         /* Event sent, so done with vblank for this flip */
 414                         drm_crtc_vblank_put(&amdgpu_crtc->base);
 415                 }
 416         } else if (e) {
 417                 /* VRR active and inside front-porch: vblank count and
 418                  * timestamp for pageflip event will only be up to date after
 419                  * drm_crtc_handle_vblank() has been executed from late vblank
 420                  * irq handler after start of back-porch (vline 0). We queue the
 421                  * pageflip event for send-out by drm_crtc_handle_vblank() with
 422                  * updated timestamp and count, once it runs after us.
 423                  *
 424                  * We need to open-code this instead of using the helper
 425                  * drm_crtc_arm_vblank_event(), as that helper would
 426                  * call drm_crtc_accurate_vblank_count(), which we must
 427                  * not call in VRR mode while we are in front-porch!
 428                  */
 429
 430                 /* sequence will be replaced by real count during send-out. */
 431                 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
 432                 e->pipe = amdgpu_crtc->crtc_id;
 433
 434                 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list);
 435                 e = NULL;
 436         }
 437
 438         /* Keep track of vblank of this flip for flip throttling. We use the
 439          * cooked hw counter, as that one incremented at start of this vblank
 440          * of pageflip completion, so last_flip_vblank is the forbidden count
 441          * for queueing new pageflips if vsync + VRR is enabled.
 442          */
 443         amdgpu_crtc->dm_irq_params.last_flip_vblank =
 444                 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base);
 445
 446         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
 447         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 448
 449         DC_LOG_PFLIP("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
 450                      amdgpu_crtc->crtc_id, amdgpu_crtc,
 451                      vrr_active, (int) !e);
 452 }
 453
 454 static void dm_vupdate_high_irq(void *interrupt_params)
 455 {
 456         struct common_irq_params *irq_params = interrupt_params;
 457         struct amdgpu_device *adev = irq_params->adev;
 458         struct amdgpu_crtc *acrtc;
 459         struct drm_device *drm_dev;
 460         struct drm_vblank_crtc *vblank;
 461         ktime_t frame_duration_ns, previous_timestamp;
 462         unsigned long flags;
 463         int vrr_active;
 464
 465         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
 466
 467         if (acrtc) {
 468                 vrr_active = amdgpu_dm_vrr_active_irq(acrtc);
 469                 drm_dev = acrtc->base.dev;
 470                 vblank = &drm_dev->vblank[acrtc->base.index];
 471                 previous_timestamp = atomic64_read(&irq_params->previous_timestamp);
 472                 frame_duration_ns = vblank->time - previous_timestamp;
 473
 474                 if (frame_duration_ns > 0) {
 475                         trace_amdgpu_refresh_rate_track(acrtc->base.index,
 476                                                 frame_duration_ns,
 477                                                 ktime_divns(NSEC_PER_SEC, frame_duration_ns));
 478                         atomic64_set(&irq_params->previous_timestamp, vblank->time);
 479                 }
 480
 481                 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d\n",
 482                               acrtc->crtc_id,
 483                               vrr_active);
 484
 485                 /* Core vblank handling is done here after end of front-porch in
 486                  * vrr mode, as vblank timestamping will give valid results
 487                  * while now done after front-porch. This will also deliver
 488                  * page-flip completion events that have been queued to us
 489                  * if a pageflip happened inside front-porch.
 490                  */
 491                 if (vrr_active) {
 492                         dm_crtc_handle_vblank(acrtc);
 493
 494                         /* BTR processing for pre-DCE12 ASICs */
 495                         if (acrtc->dm_irq_params.stream &&
 496                             adev->family < AMDGPU_FAMILY_AI) {
 497                                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 498                                 mod_freesync_handle_v_update(
 499                                     adev->dm.freesync_module,
 500                                     acrtc->dm_irq_params.stream,
 501                                     &acrtc->dm_irq_params.vrr_params);
 502
 503                                 dc_stream_adjust_vmin_vmax(
 504                                     adev->dm.dc,
 505                                     acrtc->dm_irq_params.stream,
 506                                     &acrtc->dm_irq_params.vrr_params.adjust);
 507                                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 508                         }
 509                 }
 510         }
 511 }
 512
 513 /**
 514  * dm_crtc_high_irq() - Handles CRTC interrupt
 515  * @interrupt_params: used for determining the CRTC instance
 516  *
 517  * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
 518  * event handler.
 519  */
 520 static void dm_crtc_high_irq(void *interrupt_params)
 521 {
 522         struct common_irq_params *irq_params = interrupt_params;
 523         struct amdgpu_device *adev = irq_params->adev;
 524         struct amdgpu_crtc *acrtc;
 525         unsigned long flags;
 526         int vrr_active;
 527
 528         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
 529         if (!acrtc)
 530                 return;
 531
 532         vrr_active = amdgpu_dm_vrr_active_irq(acrtc);
 533
 534         DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,
 535                       vrr_active, acrtc->dm_irq_params.active_planes);
 536
 537         /**
 538          * Core vblank handling at start of front-porch is only possible
 539          * in non-vrr mode, as only there vblank timestamping will give
 540          * valid results while done in front-porch. Otherwise defer it
 541          * to dm_vupdate_high_irq after end of front-porch.
 542          */
 543         if (!vrr_active)
 544                 dm_crtc_handle_vblank(acrtc);
 545
 546         /**
 547          * Following stuff must happen at start of vblank, for crc
 548          * computation and below-the-range btr support in vrr mode.
 549          */
 550         amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
 551
 552         /* BTR updates need to happen before VUPDATE on Vega and above. */
 553         if (adev->family < AMDGPU_FAMILY_AI)
 554                 return;
 555
 556         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 557
 558         if (acrtc->dm_irq_params.stream &&
 559             acrtc->dm_irq_params.vrr_params.supported &&
 560             acrtc->dm_irq_params.freesync_config.state ==
 561                     VRR_STATE_ACTIVE_VARIABLE) {
 562                 mod_freesync_handle_v_update(adev->dm.freesync_module,
 563                                              acrtc->dm_irq_params.stream,
 564                                              &acrtc->dm_irq_params.vrr_params);
 565
 566                 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,
 567                                            &acrtc->dm_irq_params.vrr_params.adjust);
 568         }
 569
 570         /*
 571          * If there aren't any active_planes then DCH HUBP may be clock-gated.
 572          * In that case, pageflip completion interrupts won't fire and pageflip
 573          * completion events won't get delivered. Prevent this by sending
 574          * pending pageflip events from here if a flip is still pending.
 575          *
 576          * If any planes are enabled, use dm_pflip_high_irq() instead, to
 577          * avoid race conditions between flip programming and completion,
 578          * which could cause too early flip completion events.
 579          */
 580         if (adev->family >= AMDGPU_FAMILY_RV &&
 581             acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
 582             acrtc->dm_irq_params.active_planes == 0) {
 583                 if (acrtc->event) {
 584                         drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
 585                         acrtc->event = NULL;
 586                         drm_crtc_vblank_put(&acrtc->base);
 587                 }
 588                 acrtc->pflip_status = AMDGPU_FLIP_NONE;
 589         }
 590
 591         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 592 }
 593
 594 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
 595 /**
 596  * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for
 597  * DCN generation ASICs
 598  * @interrupt_params: interrupt parameters
 599  *
 600  * Used to set crc window/read out crc value at vertical line 0 position
 601  */
 602 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)
 603 {
 604         struct common_irq_params *irq_params = interrupt_params;
 605         struct amdgpu_device *adev = irq_params->adev;
 606         struct amdgpu_crtc *acrtc;
 607
 608         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0);
 609
 610         if (!acrtc)
 611                 return;
 612
 613         amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base);
 614 }
 615 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */
 616
 617 /**
 618  * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command.
 619  * @adev: amdgpu_device pointer
 620  * @notify: dmub notification structure
 621  *
 622  * Dmub AUX or SET_CONFIG command completion processing callback
 623  * Copies dmub notification to DM which is to be read by AUX command.
 624  * issuing thread and also signals the event to wake up the thread.
 625  */
 626 static void dmub_aux_setconfig_callback(struct amdgpu_device *adev,
 627                                         struct dmub_notification *notify)
 628 {
 629         if (adev->dm.dmub_notify)
 630                 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification));
 631         if (notify->type == DMUB_NOTIFICATION_AUX_REPLY)
 632                 complete(&adev->dm.dmub_aux_transfer_done);
 633 }
 634
 635 /**
 636  * dmub_hpd_callback - DMUB HPD interrupt processing callback.
 637  * @adev: amdgpu_device pointer
 638  * @notify: dmub notification structure
 639  *
 640  * Dmub Hpd interrupt processing callback. Gets displayindex through the
 641  * ink index and calls helper to do the processing.
 642  */
 643 static void dmub_hpd_callback(struct amdgpu_device *adev,
 644                               struct dmub_notification *notify)
 645 {
 646         struct amdgpu_dm_connector *aconnector;
 647         struct amdgpu_dm_connector *hpd_aconnector = NULL;
 648         struct drm_connector *connector;
 649         struct drm_connector_list_iter iter;
 650         struct dc_link *link;
 651         uint8_t link_index = 0;
 652         struct drm_device *dev;
 653
 654         if (adev == NULL)
 655                 return;
 656
 657         if (notify == NULL) {
 658                 DRM_ERROR("DMUB HPD callback notification was NULL");
 659                 return;
 660         }
 661
 662         if (notify->link_index > adev->dm.dc->link_count) {
 663                 DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index);
 664                 return;
 665         }
 666
 667         link_index = notify->link_index;
 668         link = adev->dm.dc->links[link_index];
 669         dev = adev->dm.ddev;
 670
 671         drm_connector_list_iter_begin(dev, &iter);
 672         drm_for_each_connector_iter(connector, &iter) {
 673                 aconnector = to_amdgpu_dm_connector(connector);
 674                 if (link && aconnector->dc_link == link) {
 675                         DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index);
 676                         hpd_aconnector = aconnector;
 677                         break;
 678                 }
 679         }
 680         drm_connector_list_iter_end(&iter);
 681
 682         if (hpd_aconnector) {
 683                 if (notify->type == DMUB_NOTIFICATION_HPD)
 684                         handle_hpd_irq_helper(hpd_aconnector);
 685                 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
 686                         handle_hpd_rx_irq(hpd_aconnector);
 687         }
 688 }
 689
 690 /**
 691  * register_dmub_notify_callback - Sets callback for DMUB notify
 692  * @adev: amdgpu_device pointer
 693  * @type: Type of dmub notification
 694  * @callback: Dmub interrupt callback function
 695  * @dmub_int_thread_offload: offload indicator
 696  *
 697  * API to register a dmub callback handler for a dmub notification
 698  * Also sets indicator whether callback processing to be offloaded.
 699  * to dmub interrupt handling thread
 700  * Return: true if successfully registered, false if there is existing registration
 701  */
 702 static bool register_dmub_notify_callback(struct amdgpu_device *adev,
 703                                           enum dmub_notification_type type,
 704                                           dmub_notify_interrupt_callback_t callback,
 705                                           bool dmub_int_thread_offload)
 706 {
 707         if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) {
 708                 adev->dm.dmub_callback[type] = callback;
 709                 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload;
 710         } else
 711                 return false;
 712
 713         return true;
 714 }
 715
 716 static void dm_handle_hpd_work(struct work_struct *work)
 717 {
 718         struct dmub_hpd_work *dmub_hpd_wrk;
 719
 720         dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work);
 721
 722         if (!dmub_hpd_wrk->dmub_notify) {
 723                 DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL");
 724                 return;
 725         }
 726
 727         if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) {
 728                 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev,
 729                 dmub_hpd_wrk->dmub_notify);
 730         }
 731
 732         kfree(dmub_hpd_wrk->dmub_notify);
 733         kfree(dmub_hpd_wrk);
 734
 735 }
 736
 737 #define DMUB_TRACE_MAX_READ 64
 738 /**
 739  * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt
 740  * @interrupt_params: used for determining the Outbox instance
 741  *
 742  * Handles the Outbox Interrupt
 743  * event handler.
 744  */
 745 static void dm_dmub_outbox1_low_irq(void *interrupt_params)
 746 {
 747         struct dmub_notification notify;
 748         struct common_irq_params *irq_params = interrupt_params;
 749         struct amdgpu_device *adev = irq_params->adev;
 750         struct amdgpu_display_manager *dm = &adev->dm;
 751         struct dmcub_trace_buf_entry entry = { 0 };
 752         uint32_t count = 0;
 753         struct dmub_hpd_work *dmub_hpd_wrk;
 754         struct dc_link *plink = NULL;
 755
 756         if (dc_enable_dmub_notifications(adev->dm.dc) &&
 757                 irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) {
 758
 759                 do {
 760                         dc_stat_get_dmub_notification(adev->dm.dc, &notify);
 761                         if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) {
 762                                 DRM_ERROR("DM: notify type %d invalid!", notify.type);
 763                                 continue;
 764                         }
 765                         if (!dm->dmub_callback[notify.type]) {
 766                                 DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type);
 767                                 continue;
 768                         }
 769                         if (dm->dmub_thread_offload[notify.type] == true) {
 770                                 dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC);
 771                                 if (!dmub_hpd_wrk) {
 772                                         DRM_ERROR("Failed to allocate dmub_hpd_wrk");
 773                                         return;
 774                                 }
 775                                 dmub_hpd_wrk->dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_ATOMIC);
 776                                 if (!dmub_hpd_wrk->dmub_notify) {
 777                                         kfree(dmub_hpd_wrk);
 778                                         DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify");
 779                                         return;
 780                                 }
 781                                 INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work);
 782                                 if (dmub_hpd_wrk->dmub_notify)
 783                                         memcpy(dmub_hpd_wrk->dmub_notify, &notify, sizeof(struct dmub_notification));
 784                                 dmub_hpd_wrk->adev = adev;
 785                                 if (notify.type == DMUB_NOTIFICATION_HPD) {
 786                                         plink = adev->dm.dc->links[notify.link_index];
 787                                         if (plink) {
 788                                                 plink->hpd_status =
 789                                                         notify.hpd_status == DP_HPD_PLUG;
 790                                         }
 791                                 }
 792                                 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work);
 793                         } else {
 794                                 dm->dmub_callback[notify.type](adev, &notify);
 795                         }
 796                 } while (notify.pending_notification);
 797         }
 798
 799
 800         do {
 801                 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {
 802                         trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,
 803                                                         entry.param0, entry.param1);
 804
 805                         DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",
 806                                  entry.trace_code, entry.tick_count, entry.param0, entry.param1);
 807                 } else
 808                         break;
 809
 810                 count++;
 811
 812         } while (count <= DMUB_TRACE_MAX_READ);
 813
 814         if (count > DMUB_TRACE_MAX_READ)
 815                 DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ");
 816 }
 817
 818 static int dm_set_clockgating_state(void *handle,
 819                   enum amd_clockgating_state state)
 820 {
 821         return 0;
 822 }
 823
 824 static int dm_set_powergating_state(void *handle,
 825                   enum amd_powergating_state state)
 826 {
 827         return 0;
 828 }
 829
 830 /* Prototypes of private functions */
 831 static int dm_early_init(void* handle);
 832
 833 /* Allocate memory for FBC compressed data  */
 834 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
 835 {
 836         struct drm_device *dev = connector->dev;
 837         struct amdgpu_device *adev = drm_to_adev(dev);
 838         struct dm_compressor_info *compressor = &adev->dm.compressor;
 839         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
 840         struct drm_display_mode *mode;
 841         unsigned long max_size = 0;
 842
 843         if (adev->dm.dc->fbc_compressor == NULL)
 844                 return;
 845
 846         if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
 847                 return;
 848
 849         if (compressor->bo_ptr)
 850                 return;
 851
 852
 853         list_for_each_entry(mode, &connector->modes, head) {
 854                 if (max_size < mode->htotal * mode->vtotal)
 855                         max_size = mode->htotal * mode->vtotal;
 856         }
 857
 858         if (max_size) {
 859                 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
 860                             AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
 861                             &compressor->gpu_addr, &compressor->cpu_addr);
 862
 863                 if (r)
 864                         DRM_ERROR("DM: Failed to initialize FBC\n");
 865                 else {
 866                         adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
 867                         DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
 868                 }
 869
 870         }
 871
 872 }
 873
 874 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
 875                                           int pipe, bool *enabled,
 876                                           unsigned char *buf, int max_bytes)
 877 {
 878         struct drm_device *dev = dev_get_drvdata(kdev);
 879         struct amdgpu_device *adev = drm_to_adev(dev);
 880         struct drm_connector *connector;
 881         struct drm_connector_list_iter conn_iter;
 882         struct amdgpu_dm_connector *aconnector;
 883         int ret = 0;
 884
 885         *enabled = false;
 886
 887         mutex_lock(&adev->dm.audio_lock);
 888
 889         drm_connector_list_iter_begin(dev, &conn_iter);
 890         drm_for_each_connector_iter(connector, &conn_iter) {
 891                 aconnector = to_amdgpu_dm_connector(connector);
 892                 if (aconnector->audio_inst != port)
 893                         continue;
 894
 895                 *enabled = true;
 896                 ret = drm_eld_size(connector->eld);
 897                 memcpy(buf, connector->eld, min(max_bytes, ret));
 898
 899                 break;
 900         }
 901         drm_connector_list_iter_end(&conn_iter);
 902
 903         mutex_unlock(&adev->dm.audio_lock);
 904
 905         DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
 906
 907         return ret;
 908 }
 909
 910 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
 911         .get_eld = amdgpu_dm_audio_component_get_eld,
 912 };
 913
 914 static int amdgpu_dm_audio_component_bind(struct device *kdev,
 915                                        struct device *hda_kdev, void *data)
 916 {
 917         struct drm_device *dev = dev_get_drvdata(kdev);
 918         struct amdgpu_device *adev = drm_to_adev(dev);
 919         struct drm_audio_component *acomp = data;
 920
 921         acomp->ops = &amdgpu_dm_audio_component_ops;
 922         acomp->dev = kdev;
 923         adev->dm.audio_component = acomp;
 924
 925         return 0;
 926 }
 927
 928 static void amdgpu_dm_audio_component_unbind(struct device *kdev,
 929                                           struct device *hda_kdev, void *data)
 930 {
 931         struct drm_device *dev = dev_get_drvdata(kdev);
 932         struct amdgpu_device *adev = drm_to_adev(dev);
 933         struct drm_audio_component *acomp = data;
 934
 935         acomp->ops = NULL;
 936         acomp->dev = NULL;
 937         adev->dm.audio_component = NULL;
 938 }
 939
 940 static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
 941         .bind   = amdgpu_dm_audio_component_bind,
 942         .unbind = amdgpu_dm_audio_component_unbind,
 943 };
 944
 945 static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
 946 {
 947         int i, ret;
 948
 949         if (!amdgpu_audio)
 950                 return 0;
 951
 952         adev->mode_info.audio.enabled = true;
 953
 954         adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
 955
 956         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
 957                 adev->mode_info.audio.pin[i].channels = -1;
 958                 adev->mode_info.audio.pin[i].rate = -1;
 959                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
 960                 adev->mode_info.audio.pin[i].status_bits = 0;
 961                 adev->mode_info.audio.pin[i].category_code = 0;
 962                 adev->mode_info.audio.pin[i].connected = false;
 963                 adev->mode_info.audio.pin[i].id =
 964                         adev->dm.dc->res_pool->audios[i]->inst;
 965                 adev->mode_info.audio.pin[i].offset = 0;
 966         }
 967
 968         ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
 969         if (ret < 0)
 970                 return ret;
 971
 972         adev->dm.audio_registered = true;
 973
 974         return 0;
 975 }
 976
 977 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
 978 {
 979         if (!amdgpu_audio)
 980                 return;
 981
 982         if (!adev->mode_info.audio.enabled)
 983                 return;
 984
 985         if (adev->dm.audio_registered) {
 986                 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
 987                 adev->dm.audio_registered = false;
 988         }
 989
 990         /* TODO: Disable audio? */
 991
 992         adev->mode_info.audio.enabled = false;
 993 }
 994
 995 static  void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
 996 {
 997         struct drm_audio_component *acomp = adev->dm.audio_component;
 998
 999         if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
1000                 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
1001
1002                 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
1003                                                  pin, -1);
1004         }
1005 }
1006
1007 static int dm_dmub_hw_init(struct amdgpu_device *adev)
1008 {
1009         const struct dmcub_firmware_header_v1_0 *hdr;
1010         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1011         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
1012         const struct firmware *dmub_fw = adev->dm.dmub_fw;
1013         struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
1014         struct abm *abm = adev->dm.dc->res_pool->abm;
1015         struct dmub_srv_hw_params hw_params;
1016         enum dmub_status status;
1017         const unsigned char *fw_inst_const, *fw_bss_data;
1018         uint32_t i, fw_inst_const_size, fw_bss_data_size;
1019         bool has_hw_support;
1020
1021         if (!dmub_srv)
1022                 /* DMUB isn't supported on the ASIC. */
1023                 return 0;
1024
1025         if (!fb_info) {
1026                 DRM_ERROR("No framebuffer info for DMUB service.\n");
1027                 return -EINVAL;
1028         }
1029
1030         if (!dmub_fw) {
1031                 /* Firmware required for DMUB support. */
1032                 DRM_ERROR("No firmware provided for DMUB.\n");
1033                 return -EINVAL;
1034         }
1035
1036         status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
1037         if (status != DMUB_STATUS_OK) {
1038                 DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
1039                 return -EINVAL;
1040         }
1041
1042         if (!has_hw_support) {
1043                 DRM_INFO("DMUB unsupported on ASIC\n");
1044                 return 0;
1045         }
1046
1047         /* Reset DMCUB if it was previously running - before we overwrite its memory. */
1048         status = dmub_srv_hw_reset(dmub_srv);
1049         if (status != DMUB_STATUS_OK)
1050                 DRM_WARN("Error resetting DMUB HW: %d\n", status);
1051
1052         hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
1053
1054         fw_inst_const = dmub_fw->data +
1055                         le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1056                         PSP_HEADER_BYTES;
1057
1058         fw_bss_data = dmub_fw->data +
1059                       le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1060                       le32_to_cpu(hdr->inst_const_bytes);
1061
1062         /* Copy firmware and bios info into FB memory. */
1063         fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
1064                              PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
1065
1066         fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
1067
1068         /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP,
1069          * amdgpu_ucode_init_single_fw will load dmub firmware
1070          * fw_inst_const part to cw0; otherwise, the firmware back door load
1071          * will be done by dm_dmub_hw_init
1072          */
1073         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1074                 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
1075                                 fw_inst_const_size);
1076         }
1077
1078         if (fw_bss_data_size)
1079                 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr,
1080                        fw_bss_data, fw_bss_data_size);
1081
1082         /* Copy firmware bios info into FB memory. */
1083         memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,
1084                adev->bios_size);
1085
1086         /* Reset regions that need to be reset. */
1087         memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,
1088         fb_info->fb[DMUB_WINDOW_4_MAILBOX].size);
1089
1090         memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,
1091                fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size);
1092
1093         memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,
1094                fb_info->fb[DMUB_WINDOW_6_FW_STATE].size);
1095
1096         /* Initialize hardware. */
1097         memset(&hw_params, 0, sizeof(hw_params));
1098         hw_params.fb_base = adev->gmc.fb_start;
1099         hw_params.fb_offset = adev->vm_manager.vram_base_offset;
1100
1101         /* backdoor load firmware and trigger dmub running */
1102         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
1103                 hw_params.load_inst_const = true;
1104
1105         if (dmcu)
1106                 hw_params.psp_version = dmcu->psp_version;
1107
1108         for (i = 0; i < fb_info->num_fb; ++i)
1109                 hw_params.fb[i] = &fb_info->fb[i];
1110
1111         switch (adev->ip_versions[DCE_HWIP][0]) {
1112         case IP_VERSION(3, 1, 3):
1113         case IP_VERSION(3, 1, 4):
1114                 hw_params.dpia_supported = true;
1115                 hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia;
1116                 break;
1117         default:
1118                 break;
1119         }
1120
1121         status = dmub_srv_hw_init(dmub_srv, &hw_params);
1122         if (status != DMUB_STATUS_OK) {
1123                 DRM_ERROR("Error initializing DMUB HW: %d\n", status);
1124                 return -EINVAL;
1125         }
1126
1127         /* Wait for firmware load to finish. */
1128         status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1129         if (status != DMUB_STATUS_OK)
1130                 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1131
1132         /* Init DMCU and ABM if available. */
1133         if (dmcu && abm) {
1134                 dmcu->funcs->dmcu_init(dmcu);
1135                 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
1136         }
1137
1138         if (!adev->dm.dc->ctx->dmub_srv)
1139                 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
1140         if (!adev->dm.dc->ctx->dmub_srv) {
1141                 DRM_ERROR("Couldn't allocate DC DMUB server!\n");
1142                 return -ENOMEM;
1143         }
1144
1145         DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
1146                  adev->dm.dmcub_fw_version);
1147
1148         return 0;
1149 }
1150
1151 static void dm_dmub_hw_resume(struct amdgpu_device *adev)
1152 {
1153         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1154         enum dmub_status status;
1155         bool init;
1156
1157         if (!dmub_srv) {
1158                 /* DMUB isn't supported on the ASIC. */
1159                 return;
1160         }
1161
1162         status = dmub_srv_is_hw_init(dmub_srv, &init);
1163         if (status != DMUB_STATUS_OK)
1164                 DRM_WARN("DMUB hardware init check failed: %d\n", status);
1165
1166         if (status == DMUB_STATUS_OK && init) {
1167                 /* Wait for firmware load to finish. */
1168                 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1169                 if (status != DMUB_STATUS_OK)
1170                         DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1171         } else {
1172                 /* Perform the full hardware initialization. */
1173                 dm_dmub_hw_init(adev);
1174         }
1175 }
1176
1177 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
1178 {
1179         uint64_t pt_base;
1180         uint32_t logical_addr_low;
1181         uint32_t logical_addr_high;
1182         uint32_t agp_base, agp_bot, agp_top;
1183         PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;
1184
1185         memset(pa_config, 0, sizeof(*pa_config));
1186
1187         logical_addr_low  = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
1188         pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
1189
1190         if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1191                 /*
1192                  * Raven2 has a HW issue that it is unable to use the vram which
1193                  * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1194                  * workaround that increase system aperture high address (add 1)
1195                  * to get rid of the VM fault and hardware hang.
1196                  */
1197                 logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
1198         else
1199                 logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
1200
1201         agp_base = 0;
1202         agp_bot = adev->gmc.agp_start >> 24;
1203         agp_top = adev->gmc.agp_end >> 24;
1204
1205
1206         page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF;
1207         page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12);
1208         page_table_end.high_part = (u32)(adev->gmc.gart_end >> 44) & 0xF;
1209         page_table_end.low_part = (u32)(adev->gmc.gart_end >> 12);
1210         page_table_base.high_part = upper_32_bits(pt_base) & 0xF;
1211         page_table_base.low_part = lower_32_bits(pt_base);
1212
1213         pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
1214         pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18;
1215
1216         pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24 ;
1217         pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24;
1218         pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24;
1219
1220         pa_config->system_aperture.fb_base = adev->gmc.fb_start;
1221         pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset;
1222         pa_config->system_aperture.fb_top = adev->gmc.fb_end;
1223
1224         pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12;
1225         pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12;
1226         pa_config->gart_config.page_table_base_addr = page_table_base.quad_part;
1227
1228         pa_config->is_hvm_enabled = 0;
1229
1230 }
1231
1232 static void dm_handle_hpd_rx_offload_work(struct work_struct *work)
1233 {
1234         struct hpd_rx_irq_offload_work *offload_work;
1235         struct amdgpu_dm_connector *aconnector;
1236         struct dc_link *dc_link;
1237         struct amdgpu_device *adev;
1238         enum dc_connection_type new_connection_type = dc_connection_none;
1239         unsigned long flags;
1240
1241         offload_work = container_of(work, struct hpd_rx_irq_offload_work, work);
1242         aconnector = offload_work->offload_wq->aconnector;
1243
1244         if (!aconnector) {
1245                 DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work");
1246                 goto skip;
1247         }
1248
1249         adev = drm_to_adev(aconnector->base.dev);
1250         dc_link = aconnector->dc_link;
1251
1252         mutex_lock(&aconnector->hpd_lock);
1253         if (!dc_link_detect_sink(dc_link, &new_connection_type))
1254                 DRM_ERROR("KMS: Failed to detect connector\n");
1255         mutex_unlock(&aconnector->hpd_lock);
1256
1257         if (new_connection_type == dc_connection_none)
1258                 goto skip;
1259
1260         if (amdgpu_in_reset(adev))
1261                 goto skip;
1262
1263         mutex_lock(&adev->dm.dc_lock);
1264         if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST)
1265                 dc_link_dp_handle_automated_test(dc_link);
1266         else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) &&
1267                         hpd_rx_irq_check_link_loss_status(dc_link, &offload_work->data) &&
1268                         dc_link_dp_allow_hpd_rx_irq(dc_link)) {
1269                 dc_link_dp_handle_link_loss(dc_link);
1270                 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1271                 offload_work->offload_wq->is_handling_link_loss = false;
1272                 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1273         }
1274         mutex_unlock(&adev->dm.dc_lock);
1275
1276 skip:
1277         kfree(offload_work);
1278
1279 }
1280
1281 static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc)
1282 {
1283         int max_caps = dc->caps.max_links;
1284         int i = 0;
1285         struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL;
1286
1287         hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL);
1288
1289         if (!hpd_rx_offload_wq)
1290                 return NULL;
1291
1292
1293         for (i = 0; i < max_caps; i++) {
1294                 hpd_rx_offload_wq[i].wq =
1295                                     create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq");
1296
1297                 if (hpd_rx_offload_wq[i].wq == NULL) {
1298                         DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!");
1299                         goto out_err;
1300                 }
1301
1302                 spin_lock_init(&hpd_rx_offload_wq[i].offload_lock);
1303         }
1304
1305         return hpd_rx_offload_wq;
1306
1307 out_err:
1308         for (i = 0; i < max_caps; i++) {
1309                 if (hpd_rx_offload_wq[i].wq)
1310                         destroy_workqueue(hpd_rx_offload_wq[i].wq);
1311         }
1312         kfree(hpd_rx_offload_wq);
1313         return NULL;
1314 }
1315
1316 struct amdgpu_stutter_quirk {
1317         u16 chip_vendor;
1318         u16 chip_device;
1319         u16 subsys_vendor;
1320         u16 subsys_device;
1321         u8 revision;
1322 };
1323
1324 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = {
1325         /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */
1326         { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },
1327         { 0, 0, 0, 0, 0 },
1328 };
1329
1330 static bool dm_should_disable_stutter(struct pci_dev *pdev)
1331 {
1332         const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list;
1333
1334         while (p && p->chip_device != 0) {
1335                 if (pdev->vendor == p->chip_vendor &&
1336                     pdev->device == p->chip_device &&
1337                     pdev->subsystem_vendor == p->subsys_vendor &&
1338                     pdev->subsystem_device == p->subsys_device &&
1339                     pdev->revision == p->revision) {
1340                         return true;
1341                 }
1342                 ++p;
1343         }
1344         return false;
1345 }
1346
1347 static const struct dmi_system_id hpd_disconnect_quirk_table[] = {
1348         {
1349                 .matches = {
1350                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1351                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"),
1352                 },
1353         },
1354         {
1355                 .matches = {
1356                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1357                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"),
1358                 },
1359         },
1360         {
1361                 .matches = {
1362                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1363                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"),
1364                 },
1365         },
1366         {
1367                 .matches = {
1368                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1369                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"),
1370                 },
1371         },
1372         {
1373                 .matches = {
1374                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1375                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"),
1376                 },
1377         },
1378         {
1379                 .matches = {
1380                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1381                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"),
1382                 },
1383         },
1384         {
1385                 .matches = {
1386                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1387                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"),
1388                 },
1389         },
1390         {
1391                 .matches = {
1392                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1393                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"),
1394                 },
1395         },
1396         {
1397                 .matches = {
1398                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1399                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"),
1400                 },
1401         },
1402         {}
1403         /* TODO: refactor this from a fixed table to a dynamic option */
1404 };
1405
1406 static void retrieve_dmi_info(struct amdgpu_display_manager *dm)
1407 {
1408         const struct dmi_system_id *dmi_id;
1409
1410         dm->aux_hpd_discon_quirk = false;
1411
1412         dmi_id = dmi_first_match(hpd_disconnect_quirk_table);
1413         if (dmi_id) {
1414                 dm->aux_hpd_discon_quirk = true;
1415                 DRM_INFO("aux_hpd_discon_quirk attached\n");
1416         }
1417 }
1418
1419 static int amdgpu_dm_init(struct amdgpu_device *adev)
1420 {
1421         struct dc_init_data init_data;
1422 #ifdef CONFIG_DRM_AMD_DC_HDCP
1423         struct dc_callback_init init_params;
1424 #endif
1425         int r;
1426
1427         adev->dm.ddev = adev_to_drm(adev);
1428         adev->dm.adev = adev;
1429
1430         /* Zero all the fields */
1431         memset(&init_data, 0, sizeof(init_data));
1432 #ifdef CONFIG_DRM_AMD_DC_HDCP
1433         memset(&init_params, 0, sizeof(init_params));
1434 #endif
1435
1436         mutex_init(&adev->dm.dpia_aux_lock);
1437         mutex_init(&adev->dm.dc_lock);
1438         mutex_init(&adev->dm.audio_lock);
1439
1440         if(amdgpu_dm_irq_init(adev)) {
1441                 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
1442                 goto error;
1443         }
1444
1445         init_data.asic_id.chip_family = adev->family;
1446
1447         init_data.asic_id.pci_revision_id = adev->pdev->revision;
1448         init_data.asic_id.hw_internal_rev = adev->external_rev_id;
1449         init_data.asic_id.chip_id = adev->pdev->device;
1450
1451         init_data.asic_id.vram_width = adev->gmc.vram_width;
1452         /* TODO: initialize init_data.asic_id.vram_type here!!!! */
1453         init_data.asic_id.atombios_base_address =
1454                 adev->mode_info.atom_context->bios;
1455
1456         init_data.driver = adev;
1457
1458         adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
1459
1460         if (!adev->dm.cgs_device) {
1461                 DRM_ERROR("amdgpu: failed to create cgs device.\n");
1462                 goto error;
1463         }
1464
1465         init_data.cgs_device = adev->dm.cgs_device;
1466
1467         init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
1468
1469         switch (adev->ip_versions[DCE_HWIP][0]) {
1470         case IP_VERSION(2, 1, 0):
1471                 switch (adev->dm.dmcub_fw_version) {
1472                 case 0: /* development */
1473                 case 0x1: /* linux-firmware.git hash 6d9f399 */
1474                 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */
1475                         init_data.flags.disable_dmcu = false;
1476                         break;
1477                 default:
1478                         init_data.flags.disable_dmcu = true;
1479                 }
1480                 break;
1481         case IP_VERSION(2, 0, 3):
1482                 init_data.flags.disable_dmcu = true;
1483                 break;
1484         default:
1485                 break;
1486         }
1487
1488         switch (adev->asic_type) {
1489         case CHIP_CARRIZO:
1490         case CHIP_STONEY:
1491                 init_data.flags.gpu_vm_support = true;
1492                 break;
1493         default:
1494                 switch (adev->ip_versions[DCE_HWIP][0]) {
1495                 case IP_VERSION(1, 0, 0):
1496                 case IP_VERSION(1, 0, 1):
1497                         /* enable S/G on PCO and RV2 */
1498                         if ((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
1499                             (adev->apu_flags & AMD_APU_IS_PICASSO))
1500                                 init_data.flags.gpu_vm_support = true;
1501                         break;
1502                 case IP_VERSION(2, 1, 0):
1503                 case IP_VERSION(3, 0, 1):
1504                 case IP_VERSION(3, 1, 2):
1505                 case IP_VERSION(3, 1, 3):
1506                 case IP_VERSION(3, 1, 6):
1507                         init_data.flags.gpu_vm_support = true;
1508                         break;
1509                 default:
1510                         break;
1511                 }
1512                 break;
1513         }
1514
1515         if (init_data.flags.gpu_vm_support)
1516                 adev->mode_info.gpu_vm_support = true;
1517
1518         if (amdgpu_dc_feature_mask & DC_FBC_MASK)
1519                 init_data.flags.fbc_support = true;
1520
1521         if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
1522                 init_data.flags.multi_mon_pp_mclk_switch = true;
1523
1524         if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
1525                 init_data.flags.disable_fractional_pwm = true;
1526
1527         if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING)
1528                 init_data.flags.edp_no_power_sequencing = true;
1529
1530         if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A)
1531                 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true;
1532         if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)
1533                 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;
1534
1535         init_data.flags.seamless_boot_edp_requested = false;
1536
1537         if (check_seamless_boot_capability(adev)) {
1538                 init_data.flags.seamless_boot_edp_requested = true;
1539                 init_data.flags.allow_seamless_boot_optimization = true;
1540                 DRM_INFO("Seamless boot condition check passed\n");
1541         }
1542
1543         init_data.flags.enable_mipi_converter_optimization = true;
1544
1545         init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];
1546         init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];
1547
1548         INIT_LIST_HEAD(&adev->dm.da_list);
1549
1550         retrieve_dmi_info(&adev->dm);
1551
1552         /* Display Core create. */
1553         adev->dm.dc = dc_create(&init_data);
1554
1555         if (adev->dm.dc) {
1556                 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
1557         } else {
1558                 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
1559                 goto error;
1560         }
1561
1562         if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
1563                 adev->dm.dc->debug.force_single_disp_pipe_split = false;
1564                 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
1565         }
1566
1567         if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
1568                 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
1569         if (dm_should_disable_stutter(adev->pdev))
1570                 adev->dm.dc->debug.disable_stutter = true;
1571
1572         if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
1573                 adev->dm.dc->debug.disable_stutter = true;
1574
1575         if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) {
1576                 adev->dm.dc->debug.disable_dsc = true;
1577         }
1578
1579         if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
1580                 adev->dm.dc->debug.disable_clock_gate = true;
1581
1582         if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH)
1583                 adev->dm.dc->debug.force_subvp_mclk_switch = true;
1584
1585         adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm;
1586
1587         /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */
1588         adev->dm.dc->debug.ignore_cable_id = true;
1589
1590         r = dm_dmub_hw_init(adev);
1591         if (r) {
1592                 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
1593                 goto error;
1594         }
1595
1596         dc_hardware_init(adev->dm.dc);
1597
1598         adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc);
1599         if (!adev->dm.hpd_rx_offload_wq) {
1600                 DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n");
1601                 goto error;
1602         }
1603
1604         if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) {
1605                 struct dc_phy_addr_space_config pa_config;
1606
1607                 mmhub_read_system_context(adev, &pa_config);
1608
1609                 // Call the DC init_memory func
1610                 dc_setup_system_context(adev->dm.dc, &pa_config);
1611         }
1612
1613         adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
1614         if (!adev->dm.freesync_module) {
1615                 DRM_ERROR(
1616                 "amdgpu: failed to initialize freesync_module.\n");
1617         } else
1618                 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
1619                                 adev->dm.freesync_module);
1620
1621         amdgpu_dm_init_color_mod();
1622
1623         if (adev->dm.dc->caps.max_links > 0) {
1624                 adev->dm.vblank_control_workqueue =
1625                         create_singlethread_workqueue("dm_vblank_control_workqueue");
1626                 if (!adev->dm.vblank_control_workqueue)
1627                         DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n");
1628         }
1629
1630 #ifdef CONFIG_DRM_AMD_DC_HDCP
1631         if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
1632                 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
1633
1634                 if (!adev->dm.hdcp_workqueue)
1635                         DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
1636                 else
1637                         DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
1638
1639                 dc_init_callbacks(adev->dm.dc, &init_params);
1640         }
1641 #endif
1642 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1643         adev->dm.crc_rd_wrk = amdgpu_dm_crtc_secure_display_create_work();
1644 #endif
1645         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
1646                 init_completion(&adev->dm.dmub_aux_transfer_done);
1647                 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL);
1648                 if (!adev->dm.dmub_notify) {
1649                         DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify");
1650                         goto error;
1651                 }
1652
1653                 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq");
1654                 if (!adev->dm.delayed_hpd_wq) {
1655                         DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n");
1656                         goto error;
1657                 }
1658
1659                 amdgpu_dm_outbox_init(adev);
1660                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY,
1661                         dmub_aux_setconfig_callback, false)) {
1662                         DRM_ERROR("amdgpu: fail to register dmub aux callback");
1663                         goto error;
1664                 }
1665                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true)) {
1666                         DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1667                         goto error;
1668                 }
1669                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true)) {
1670                         DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1671                         goto error;
1672                 }
1673         }
1674
1675         /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive.
1676          * It is expected that DMUB will resend any pending notifications at this point, for
1677          * example HPD from DPIA.
1678          */
1679         if (dc_is_dmub_outbox_supported(adev->dm.dc))
1680                 dc_enable_dmub_outbox(adev->dm.dc);
1681
1682         if (amdgpu_dm_initialize_drm_device(adev)) {
1683                 DRM_ERROR(
1684                 "amdgpu: failed to initialize sw for display support.\n");
1685                 goto error;
1686         }
1687
1688         /* create fake encoders for MST */
1689         dm_dp_create_fake_mst_encoders(adev);
1690
1691         /* TODO: Add_display_info? */
1692
1693         /* TODO use dynamic cursor width */
1694         adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
1695         adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
1696
1697         if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
1698                 DRM_ERROR(
1699                 "amdgpu: failed to initialize sw for display support.\n");
1700                 goto error;
1701         }
1702
1703
1704         DRM_DEBUG_DRIVER("KMS initialized.\n");
1705
1706         return 0;
1707 error:
1708         amdgpu_dm_fini(adev);
1709
1710         return -EINVAL;
1711 }
1712
1713 static int amdgpu_dm_early_fini(void *handle)
1714 {
1715         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1716
1717         amdgpu_dm_audio_fini(adev);
1718
1719         return 0;
1720 }
1721
1722 static void amdgpu_dm_fini(struct amdgpu_device *adev)
1723 {
1724         int i;
1725
1726         if (adev->dm.vblank_control_workqueue) {
1727                 destroy_workqueue(adev->dm.vblank_control_workqueue);
1728                 adev->dm.vblank_control_workqueue = NULL;
1729         }
1730
1731         amdgpu_dm_destroy_drm_device(&adev->dm);
1732
1733 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1734         if (adev->dm.crc_rd_wrk) {
1735                 flush_work(&adev->dm.crc_rd_wrk->notify_ta_work);
1736                 kfree(adev->dm.crc_rd_wrk);
1737                 adev->dm.crc_rd_wrk = NULL;
1738         }
1739 #endif
1740 #ifdef CONFIG_DRM_AMD_DC_HDCP
1741         if (adev->dm.hdcp_workqueue) {
1742                 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue);
1743                 adev->dm.hdcp_workqueue = NULL;
1744         }
1745
1746         if (adev->dm.dc)
1747                 dc_deinit_callbacks(adev->dm.dc);
1748 #endif
1749
1750         dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
1751
1752         if (dc_enable_dmub_notifications(adev->dm.dc)) {
1753                 kfree(adev->dm.dmub_notify);
1754                 adev->dm.dmub_notify = NULL;
1755                 destroy_workqueue(adev->dm.delayed_hpd_wq);
1756                 adev->dm.delayed_hpd_wq = NULL;
1757         }
1758
1759         if (adev->dm.dmub_bo)
1760                 amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
1761                                       &adev->dm.dmub_bo_gpu_addr,
1762                                       &adev->dm.dmub_bo_cpu_addr);
1763
1764         if (adev->dm.hpd_rx_offload_wq) {
1765                 for (i = 0; i < adev->dm.dc->caps.max_links; i++) {
1766                         if (adev->dm.hpd_rx_offload_wq[i].wq) {
1767                                 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq);
1768                                 adev->dm.hpd_rx_offload_wq[i].wq = NULL;
1769                         }
1770                 }
1771
1772                 kfree(adev->dm.hpd_rx_offload_wq);
1773                 adev->dm.hpd_rx_offload_wq = NULL;
1774         }
1775
1776         /* DC Destroy TODO: Replace destroy DAL */
1777         if (adev->dm.dc)
1778                 dc_destroy(&adev->dm.dc);
1779         /*
1780          * TODO: pageflip, vlank interrupt
1781          *
1782          * amdgpu_dm_irq_fini(adev);
1783          */
1784
1785         if (adev->dm.cgs_device) {
1786                 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
1787                 adev->dm.cgs_device = NULL;
1788         }
1789         if (adev->dm.freesync_module) {
1790                 mod_freesync_destroy(adev->dm.freesync_module);
1791                 adev->dm.freesync_module = NULL;
1792         }
1793
1794         mutex_destroy(&adev->dm.audio_lock);
1795         mutex_destroy(&adev->dm.dc_lock);
1796         mutex_destroy(&adev->dm.dpia_aux_lock);
1797
1798         return;
1799 }
1800
1801 static int load_dmcu_fw(struct amdgpu_device *adev)
1802 {
1803         const char *fw_name_dmcu = NULL;
1804         int r;
1805         const struct dmcu_firmware_header_v1_0 *hdr;
1806
1807         switch(adev->asic_type) {
1808 #if defined(CONFIG_DRM_AMD_DC_SI)
1809         case CHIP_TAHITI:
1810         case CHIP_PITCAIRN:
1811         case CHIP_VERDE:
1812         case CHIP_OLAND:
1813 #endif
1814         case CHIP_BONAIRE:
1815         case CHIP_HAWAII:
1816         case CHIP_KAVERI:
1817         case CHIP_KABINI:
1818         case CHIP_MULLINS:
1819         case CHIP_TONGA:
1820         case CHIP_FIJI:
1821         case CHIP_CARRIZO:
1822         case CHIP_STONEY:
1823         case CHIP_POLARIS11:
1824         case CHIP_POLARIS10:
1825         case CHIP_POLARIS12:
1826         case CHIP_VEGAM:
1827         case CHIP_VEGA10:
1828         case CHIP_VEGA12:
1829         case CHIP_VEGA20:
1830                 return 0;
1831         case CHIP_NAVI12:
1832                 fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
1833                 break;
1834         case CHIP_RAVEN:
1835                 if (ASICREV_IS_PICASSO(adev->external_rev_id))
1836                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1837                 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
1838                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1839                 else
1840                         return 0;
1841                 break;
1842         default:
1843                 switch (adev->ip_versions[DCE_HWIP][0]) {
1844                 case IP_VERSION(2, 0, 2):
1845                 case IP_VERSION(2, 0, 3):
1846                 case IP_VERSION(2, 0, 0):
1847                 case IP_VERSION(2, 1, 0):
1848                 case IP_VERSION(3, 0, 0):
1849                 case IP_VERSION(3, 0, 2):
1850                 case IP_VERSION(3, 0, 3):
1851                 case IP_VERSION(3, 0, 1):
1852                 case IP_VERSION(3, 1, 2):
1853                 case IP_VERSION(3, 1, 3):
1854                 case IP_VERSION(3, 1, 4):
1855                 case IP_VERSION(3, 1, 5):
1856                 case IP_VERSION(3, 1, 6):
1857                 case IP_VERSION(3, 2, 0):
1858                 case IP_VERSION(3, 2, 1):
1859                         return 0;
1860                 default:
1861                         break;
1862                 }
1863                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
1864                 return -EINVAL;
1865         }
1866
1867         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1868                 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
1869                 return 0;
1870         }
1871
1872         r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev);
1873         if (r == -ENOENT) {
1874                 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
1875                 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
1876                 adev->dm.fw_dmcu = NULL;
1877                 return 0;
1878         }
1879         if (r) {
1880                 dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n",
1881                         fw_name_dmcu);
1882                 return r;
1883         }
1884
1885         r = amdgpu_ucode_validate(adev->dm.fw_dmcu);
1886         if (r) {
1887                 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
1888                         fw_name_dmcu);
1889                 release_firmware(adev->dm.fw_dmcu);
1890                 adev->dm.fw_dmcu = NULL;
1891                 return r;
1892         }
1893
1894         hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
1895         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
1896         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
1897         adev->firmware.fw_size +=
1898                 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
1899
1900         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
1901         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
1902         adev->firmware.fw_size +=
1903                 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
1904
1905         adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
1906
1907         DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
1908
1909         return 0;
1910 }
1911
1912 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
1913 {
1914         struct amdgpu_device *adev = ctx;
1915
1916         return dm_read_reg(adev->dm.dc->ctx, address);
1917 }
1918
1919 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
1920                                      uint32_t value)
1921 {
1922         struct amdgpu_device *adev = ctx;
1923
1924         return dm_write_reg(adev->dm.dc->ctx, address, value);
1925 }
1926
1927 static int dm_dmub_sw_init(struct amdgpu_device *adev)
1928 {
1929         struct dmub_srv_create_params create_params;
1930         struct dmub_srv_region_params region_params;
1931         struct dmub_srv_region_info region_info;
1932         struct dmub_srv_fb_params fb_params;
1933         struct dmub_srv_fb_info *fb_info;
1934         struct dmub_srv *dmub_srv;
1935         const struct dmcub_firmware_header_v1_0 *hdr;
1936         const char *fw_name_dmub;
1937         enum dmub_asic dmub_asic;
1938         enum dmub_status status;
1939         int r;
1940
1941         switch (adev->ip_versions[DCE_HWIP][0]) {
1942         case IP_VERSION(2, 1, 0):
1943                 dmub_asic = DMUB_ASIC_DCN21;
1944                 fw_name_dmub = FIRMWARE_RENOIR_DMUB;
1945                 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
1946                         fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
1947                 break;
1948         case IP_VERSION(3, 0, 0):
1949                 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) {
1950                         dmub_asic = DMUB_ASIC_DCN30;
1951                         fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
1952                 } else {
1953                         dmub_asic = DMUB_ASIC_DCN30;
1954                         fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
1955                 }
1956                 break;
1957         case IP_VERSION(3, 0, 1):
1958                 dmub_asic = DMUB_ASIC_DCN301;
1959                 fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
1960                 break;
1961         case IP_VERSION(3, 0, 2):
1962                 dmub_asic = DMUB_ASIC_DCN302;
1963                 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
1964                 break;
1965         case IP_VERSION(3, 0, 3):
1966                 dmub_asic = DMUB_ASIC_DCN303;
1967                 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;
1968                 break;
1969         case IP_VERSION(3, 1, 2):
1970         case IP_VERSION(3, 1, 3):
1971                 dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31;
1972                 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
1973                 break;
1974         case IP_VERSION(3, 1, 4):
1975                 dmub_asic = DMUB_ASIC_DCN314;
1976                 fw_name_dmub = FIRMWARE_DCN_314_DMUB;
1977                 break;
1978         case IP_VERSION(3, 1, 5):
1979                 dmub_asic = DMUB_ASIC_DCN315;
1980                 fw_name_dmub = FIRMWARE_DCN_315_DMUB;
1981                 break;
1982         case IP_VERSION(3, 1, 6):
1983                 dmub_asic = DMUB_ASIC_DCN316;
1984                 fw_name_dmub = FIRMWARE_DCN316_DMUB;
1985                 break;
1986         case IP_VERSION(3, 2, 0):
1987                 dmub_asic = DMUB_ASIC_DCN32;
1988                 fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB;
1989                 break;
1990         case IP_VERSION(3, 2, 1):
1991                 dmub_asic = DMUB_ASIC_DCN321;
1992                 fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB;
1993                 break;
1994         default:
1995                 /* ASIC doesn't support DMUB. */
1996                 return 0;
1997         }
1998
1999         r = request_firmware_direct(&adev->dm.dmub_fw, fw_name_dmub, adev->dev);
2000         if (r) {
2001                 DRM_ERROR("DMUB firmware loading failed: %d\n", r);
2002                 return 0;
2003         }
2004
2005         r = amdgpu_ucode_validate(adev->dm.dmub_fw);
2006         if (r) {
2007                 DRM_ERROR("Couldn't validate DMUB firmware: %d\n", r);
2008                 return 0;
2009         }
2010
2011         hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
2012         adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
2013
2014         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2015                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
2016                         AMDGPU_UCODE_ID_DMCUB;
2017                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw =
2018                         adev->dm.dmub_fw;
2019                 adev->firmware.fw_size +=
2020                         ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
2021
2022                 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
2023                          adev->dm.dmcub_fw_version);
2024         }
2025
2026
2027         adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
2028         dmub_srv = adev->dm.dmub_srv;
2029
2030         if (!dmub_srv) {
2031                 DRM_ERROR("Failed to allocate DMUB service!\n");
2032                 return -ENOMEM;
2033         }
2034
2035         memset(&create_params, 0, sizeof(create_params));
2036         create_params.user_ctx = adev;
2037         create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
2038         create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
2039         create_params.asic = dmub_asic;
2040
2041         /* Create the DMUB service. */
2042         status = dmub_srv_create(dmub_srv, &create_params);
2043         if (status != DMUB_STATUS_OK) {
2044                 DRM_ERROR("Error creating DMUB service: %d\n", status);
2045                 return -EINVAL;
2046         }
2047
2048         /* Calculate the size of all the regions for the DMUB service. */
2049         memset(&region_params, 0, sizeof(region_params));
2050
2051         region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
2052                                         PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
2053         region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
2054         region_params.vbios_size = adev->bios_size;
2055         region_params.fw_bss_data = region_params.bss_data_size ?
2056                 adev->dm.dmub_fw->data +
2057                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2058                 le32_to_cpu(hdr->inst_const_bytes) : NULL;
2059         region_params.fw_inst_const =
2060                 adev->dm.dmub_fw->data +
2061                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2062                 PSP_HEADER_BYTES;
2063
2064         status = dmub_srv_calc_region_info(dmub_srv, &region_params,
2065                                            &region_info);
2066
2067         if (status != DMUB_STATUS_OK) {
2068                 DRM_ERROR("Error calculating DMUB region info: %d\n", status);
2069                 return -EINVAL;
2070         }
2071
2072         /*
2073          * Allocate a framebuffer based on the total size of all the regions.
2074          * TODO: Move this into GART.
2075          */
2076         r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
2077                                     AMDGPU_GEM_DOMAIN_VRAM, &adev->dm.dmub_bo,
2078                                     &adev->dm.dmub_bo_gpu_addr,
2079                                     &adev->dm.dmub_bo_cpu_addr);
2080         if (r)
2081                 return r;
2082
2083         /* Rebase the regions on the framebuffer address. */
2084         memset(&fb_params, 0, sizeof(fb_params));
2085         fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr;
2086         fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr;
2087         fb_params.region_info = &region_info;
2088
2089         adev->dm.dmub_fb_info =
2090                 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);
2091         fb_info = adev->dm.dmub_fb_info;
2092
2093         if (!fb_info) {
2094                 DRM_ERROR(
2095                         "Failed to allocate framebuffer info for DMUB service!\n");
2096                 return -ENOMEM;
2097         }
2098
2099         status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info);
2100         if (status != DMUB_STATUS_OK) {
2101                 DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
2102                 return -EINVAL;
2103         }
2104
2105         return 0;
2106 }
2107
2108 static int dm_sw_init(void *handle)
2109 {
2110         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2111         int r;
2112
2113         r = dm_dmub_sw_init(adev);
2114         if (r)
2115                 return r;
2116
2117         return load_dmcu_fw(adev);
2118 }
2119
2120 static int dm_sw_fini(void *handle)
2121 {
2122         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2123
2124         kfree(adev->dm.dmub_fb_info);
2125         adev->dm.dmub_fb_info = NULL;
2126
2127         if (adev->dm.dmub_srv) {
2128                 dmub_srv_destroy(adev->dm.dmub_srv);
2129                 adev->dm.dmub_srv = NULL;
2130         }
2131
2132         release_firmware(adev->dm.dmub_fw);
2133         adev->dm.dmub_fw = NULL;
2134
2135         release_firmware(adev->dm.fw_dmcu);
2136         adev->dm.fw_dmcu = NULL;
2137
2138         return 0;
2139 }
2140
2141 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
2142 {
2143         struct amdgpu_dm_connector *aconnector;
2144         struct drm_connector *connector;
2145         struct drm_connector_list_iter iter;
2146         int ret = 0;
2147
2148         drm_connector_list_iter_begin(dev, &iter);
2149         drm_for_each_connector_iter(connector, &iter) {
2150                 aconnector = to_amdgpu_dm_connector(connector);
2151                 if (aconnector->dc_link->type == dc_connection_mst_branch &&
2152                     aconnector->mst_mgr.aux) {
2153                         DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
2154                                          aconnector,
2155                                          aconnector->base.base.id);
2156
2157                         ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
2158                         if (ret < 0) {
2159                                 DRM_ERROR("DM_MST: Failed to start MST\n");
2160                                 aconnector->dc_link->type =
2161                                         dc_connection_single;
2162                                 break;
2163                         }
2164                 }
2165         }
2166         drm_connector_list_iter_end(&iter);
2167
2168         return ret;
2169 }
2170
2171 static int dm_late_init(void *handle)
2172 {
2173         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2174
2175         struct dmcu_iram_parameters params;
2176         unsigned int linear_lut[16];
2177         int i;
2178         struct dmcu *dmcu = NULL;
2179
2180         dmcu = adev->dm.dc->res_pool->dmcu;
2181
2182         for (i = 0; i < 16; i++)
2183                 linear_lut[i] = 0xFFFF * i / 15;
2184
2185         params.set = 0;
2186         params.backlight_ramping_override = false;
2187         params.backlight_ramping_start = 0xCCCC;
2188         params.backlight_ramping_reduction = 0xCCCCCCCC;
2189         params.backlight_lut_array_size = 16;
2190         params.backlight_lut_array = linear_lut;
2191
2192         /* Min backlight level after ABM reduction,  Don't allow below 1%
2193          * 0xFFFF x 0.01 = 0x28F
2194          */
2195         params.min_abm_backlight = 0x28F;
2196         /* In the case where abm is implemented on dmcub,
2197         * dmcu object will be null.
2198         * ABM 2.4 and up are implemented on dmcub.
2199         */
2200         if (dmcu) {
2201                 if (!dmcu_load_iram(dmcu, params))
2202                         return -EINVAL;
2203         } else if (adev->dm.dc->ctx->dmub_srv) {
2204                 struct dc_link *edp_links[MAX_NUM_EDP];
2205                 int edp_num;
2206
2207                 get_edp_links(adev->dm.dc, edp_links, &edp_num);
2208                 for (i = 0; i < edp_num; i++) {
2209                         if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i))
2210                                 return -EINVAL;
2211                 }
2212         }
2213
2214         return detect_mst_link_for_all_connectors(adev_to_drm(adev));
2215 }
2216
2217 static void s3_handle_mst(struct drm_device *dev, bool suspend)
2218 {
2219         struct amdgpu_dm_connector *aconnector;
2220         struct drm_connector *connector;
2221         struct drm_connector_list_iter iter;
2222         struct drm_dp_mst_topology_mgr *mgr;
2223         int ret;
2224         bool need_hotplug = false;
2225
2226         drm_connector_list_iter_begin(dev, &iter);
2227         drm_for_each_connector_iter(connector, &iter) {
2228                 aconnector = to_amdgpu_dm_connector(connector);
2229                 if (aconnector->dc_link->type != dc_connection_mst_branch ||
2230                     aconnector->mst_port)
2231                         continue;
2232
2233                 mgr = &aconnector->mst_mgr;
2234
2235                 if (suspend) {
2236                         drm_dp_mst_topology_mgr_suspend(mgr);
2237                 } else {
2238                         ret = drm_dp_mst_topology_mgr_resume(mgr, true);
2239                         if (ret < 0) {
2240                                 dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2241                                         aconnector->dc_link);
2242                                 need_hotplug = true;
2243                         }
2244                 }
2245         }
2246         drm_connector_list_iter_end(&iter);
2247
2248         if (need_hotplug)
2249                 drm_kms_helper_hotplug_event(dev);
2250 }
2251
2252 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
2253 {
2254         int ret = 0;
2255
2256         /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
2257          * on window driver dc implementation.
2258          * For Navi1x, clock settings of dcn watermarks are fixed. the settings
2259          * should be passed to smu during boot up and resume from s3.
2260          * boot up: dc calculate dcn watermark clock settings within dc_create,
2261          * dcn20_resource_construct
2262          * then call pplib functions below to pass the settings to smu:
2263          * smu_set_watermarks_for_clock_ranges
2264          * smu_set_watermarks_table
2265          * navi10_set_watermarks_table
2266          * smu_write_watermarks_table
2267          *
2268          * For Renoir, clock settings of dcn watermark are also fixed values.
2269          * dc has implemented different flow for window driver:
2270          * dc_hardware_init / dc_set_power_state
2271          * dcn10_init_hw
2272          * notify_wm_ranges
2273          * set_wm_ranges
2274          * -- Linux
2275          * smu_set_watermarks_for_clock_ranges
2276          * renoir_set_watermarks_table
2277          * smu_write_watermarks_table
2278          *
2279          * For Linux,
2280          * dc_hardware_init -> amdgpu_dm_init
2281          * dc_set_power_state --> dm_resume
2282          *
2283          * therefore, this function apply to navi10/12/14 but not Renoir
2284          * *
2285          */
2286         switch (adev->ip_versions[DCE_HWIP][0]) {
2287         case IP_VERSION(2, 0, 2):
2288         case IP_VERSION(2, 0, 0):
2289                 break;
2290         default:
2291                 return 0;
2292         }
2293
2294         ret = amdgpu_dpm_write_watermarks_table(adev);
2295         if (ret) {
2296                 DRM_ERROR("Failed to update WMTABLE!\n");
2297                 return ret;
2298         }
2299
2300         return 0;
2301 }
2302
2303 /**
2304  * dm_hw_init() - Initialize DC device
2305  * @handle: The base driver device containing the amdgpu_dm device.
2306  *
2307  * Initialize the &struct amdgpu_display_manager device. This involves calling
2308  * the initializers of each DM component, then populating the struct with them.
2309  *
2310  * Although the function implies hardware initialization, both hardware and
2311  * software are initialized here. Splitting them out to their relevant init
2312  * hooks is a future TODO item.
2313  *
2314  * Some notable things that are initialized here:
2315  *
2316  * - Display Core, both software and hardware
2317  * - DC modules that we need (freesync and color management)
2318  * - DRM software states
2319  * - Interrupt sources and handlers
2320  * - Vblank support
2321  * - Debug FS entries, if enabled
2322  */
2323 static int dm_hw_init(void *handle)
2324 {
2325         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2326         /* Create DAL display manager */
2327         amdgpu_dm_init(adev);
2328         amdgpu_dm_hpd_init(adev);
2329
2330         return 0;
2331 }
2332
2333 /**
2334  * dm_hw_fini() - Teardown DC device
2335  * @handle: The base driver device containing the amdgpu_dm device.
2336  *
2337  * Teardown components within &struct amdgpu_display_manager that require
2338  * cleanup. This involves cleaning up the DRM device, DC, and any modules that
2339  * were loaded. Also flush IRQ workqueues and disable them.
2340  */
2341 static int dm_hw_fini(void *handle)
2342 {
2343         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2344
2345         amdgpu_dm_hpd_fini(adev);
2346
2347         amdgpu_dm_irq_fini(adev);
2348         amdgpu_dm_fini(adev);
2349         return 0;
2350 }
2351
2352
2353 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
2354                                  struct dc_state *state, bool enable)
2355 {
2356         enum dc_irq_source irq_source;
2357         struct amdgpu_crtc *acrtc;
2358         int rc = -EBUSY;
2359         int i = 0;
2360
2361         for (i = 0; i < state->stream_count; i++) {
2362                 acrtc = get_crtc_by_otg_inst(
2363                                 adev, state->stream_status[i].primary_otg_inst);
2364
2365                 if (acrtc && state->stream_status[i].plane_count != 0) {
2366                         irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst;
2367                         rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
2368                         DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n",
2369                                       acrtc->crtc_id, enable ? "en" : "dis", rc);
2370                         if (rc)
2371                                 DRM_WARN("Failed to %s pflip interrupts\n",
2372                                          enable ? "enable" : "disable");
2373
2374                         if (enable) {
2375                                 rc = dm_enable_vblank(&acrtc->base);
2376                                 if (rc)
2377                                         DRM_WARN("Failed to enable vblank interrupts\n");
2378                         } else {
2379                                 dm_disable_vblank(&acrtc->base);
2380                         }
2381
2382                 }
2383         }
2384
2385 }
2386
2387 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
2388 {
2389         struct dc_state *context = NULL;
2390         enum dc_status res = DC_ERROR_UNEXPECTED;
2391         int i;
2392         struct dc_stream_state *del_streams[MAX_PIPES];
2393         int del_streams_count = 0;
2394
2395         memset(del_streams, 0, sizeof(del_streams));
2396
2397         context = dc_create_state(dc);
2398         if (context == NULL)
2399                 goto context_alloc_fail;
2400
2401         dc_resource_state_copy_construct_current(dc, context);
2402
2403         /* First remove from context all streams */
2404         for (i = 0; i < context->stream_count; i++) {
2405                 struct dc_stream_state *stream = context->streams[i];
2406
2407                 del_streams[del_streams_count++] = stream;
2408         }
2409
2410         /* Remove all planes for removed streams and then remove the streams */
2411         for (i = 0; i < del_streams_count; i++) {
2412                 if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) {
2413                         res = DC_FAIL_DETACH_SURFACES;
2414                         goto fail;
2415                 }
2416
2417                 res = dc_remove_stream_from_ctx(dc, context, del_streams[i]);
2418                 if (res != DC_OK)
2419                         goto fail;
2420         }
2421
2422         res = dc_commit_state(dc, context);
2423
2424 fail:
2425         dc_release_state(context);
2426
2427 context_alloc_fail:
2428         return res;
2429 }
2430
2431 static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm)
2432 {
2433         int i;
2434
2435         if (dm->hpd_rx_offload_wq) {
2436                 for (i = 0; i < dm->dc->caps.max_links; i++)
2437                         flush_workqueue(dm->hpd_rx_offload_wq[i].wq);
2438         }
2439 }
2440
2441 static int dm_suspend(void *handle)
2442 {
2443         struct amdgpu_device *adev = handle;
2444         struct amdgpu_display_manager *dm = &adev->dm;
2445         int ret = 0;
2446
2447         if (amdgpu_in_reset(adev)) {
2448                 mutex_lock(&dm->dc_lock);
2449
2450                 dc_allow_idle_optimizations(adev->dm.dc, false);
2451
2452                 dm->cached_dc_state = dc_copy_state(dm->dc->current_state);
2453
2454                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
2455
2456                 amdgpu_dm_commit_zero_streams(dm->dc);
2457
2458                 amdgpu_dm_irq_suspend(adev);
2459
2460                 hpd_rx_irq_work_suspend(dm);
2461
2462                 return ret;
2463         }
2464
2465         WARN_ON(adev->dm.cached_state);
2466         adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));
2467
2468         s3_handle_mst(adev_to_drm(adev), true);
2469
2470         amdgpu_dm_irq_suspend(adev);
2471
2472         hpd_rx_irq_work_suspend(dm);
2473
2474         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
2475
2476         return 0;
2477 }
2478
2479 struct amdgpu_dm_connector *
2480 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
2481                                              struct drm_crtc *crtc)
2482 {
2483         uint32_t i;
2484         struct drm_connector_state *new_con_state;
2485         struct drm_connector *connector;
2486         struct drm_crtc *crtc_from_state;
2487
2488         for_each_new_connector_in_state(state, connector, new_con_state, i) {
2489                 crtc_from_state = new_con_state->crtc;
2490
2491                 if (crtc_from_state == crtc)
2492                         return to_amdgpu_dm_connector(connector);
2493         }
2494
2495         return NULL;
2496 }
2497
2498 static void emulated_link_detect(struct dc_link *link)
2499 {
2500         struct dc_sink_init_data sink_init_data = { 0 };
2501         struct display_sink_capability sink_caps = { 0 };
2502         enum dc_edid_status edid_status;
2503         struct dc_context *dc_ctx = link->ctx;
2504         struct dc_sink *sink = NULL;
2505         struct dc_sink *prev_sink = NULL;
2506
2507         link->type = dc_connection_none;
2508         prev_sink = link->local_sink;
2509
2510         if (prev_sink)
2511                 dc_sink_release(prev_sink);
2512
2513         switch (link->connector_signal) {
2514         case SIGNAL_TYPE_HDMI_TYPE_A: {
2515                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2516                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
2517                 break;
2518         }
2519
2520         case SIGNAL_TYPE_DVI_SINGLE_LINK: {
2521                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2522                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
2523                 break;
2524         }
2525
2526         case SIGNAL_TYPE_DVI_DUAL_LINK: {
2527                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2528                 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
2529                 break;
2530         }
2531
2532         case SIGNAL_TYPE_LVDS: {
2533                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2534                 sink_caps.signal = SIGNAL_TYPE_LVDS;
2535                 break;
2536         }
2537
2538         case SIGNAL_TYPE_EDP: {
2539                 sink_caps.transaction_type =
2540                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2541                 sink_caps.signal = SIGNAL_TYPE_EDP;
2542                 break;
2543         }
2544
2545         case SIGNAL_TYPE_DISPLAY_PORT: {
2546                 sink_caps.transaction_type =
2547                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2548                 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
2549                 break;
2550         }
2551
2552         default:
2553                 DC_ERROR("Invalid connector type! signal:%d\n",
2554                         link->connector_signal);
2555                 return;
2556         }
2557
2558         sink_init_data.link = link;
2559         sink_init_data.sink_signal = sink_caps.signal;
2560
2561         sink = dc_sink_create(&sink_init_data);
2562         if (!sink) {
2563                 DC_ERROR("Failed to create sink!\n");
2564                 return;
2565         }
2566
2567         /* dc_sink_create returns a new reference */
2568         link->local_sink = sink;
2569
2570         edid_status = dm_helpers_read_local_edid(
2571                         link->ctx,
2572                         link,
2573                         sink);
2574
2575         if (edid_status != EDID_OK)
2576                 DC_ERROR("Failed to read EDID");
2577
2578 }
2579
2580 static void dm_gpureset_commit_state(struct dc_state *dc_state,
2581                                      struct amdgpu_display_manager *dm)
2582 {
2583         struct {
2584                 struct dc_surface_update surface_updates[MAX_SURFACES];
2585                 struct dc_plane_info plane_infos[MAX_SURFACES];
2586                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
2587                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
2588                 struct dc_stream_update stream_update;
2589         } * bundle;
2590         int k, m;
2591
2592         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
2593
2594         if (!bundle) {
2595                 dm_error("Failed to allocate update bundle\n");
2596                 goto cleanup;
2597         }
2598
2599         for (k = 0; k < dc_state->stream_count; k++) {
2600                 bundle->stream_update.stream = dc_state->streams[k];
2601
2602                 for (m = 0; m < dc_state->stream_status->plane_count; m++) {
2603                         bundle->surface_updates[m].surface =
2604                                 dc_state->stream_status->plane_states[m];
2605                         bundle->surface_updates[m].surface->force_full_update =
2606                                 true;
2607                 }
2608                 dc_commit_updates_for_stream(
2609                         dm->dc, bundle->surface_updates,
2610                         dc_state->stream_status->plane_count,
2611                         dc_state->streams[k], &bundle->stream_update, dc_state);
2612         }
2613
2614 cleanup:
2615         kfree(bundle);
2616
2617         return;
2618 }
2619
2620 static int dm_resume(void *handle)
2621 {
2622         struct amdgpu_device *adev = handle;
2623         struct drm_device *ddev = adev_to_drm(adev);
2624         struct amdgpu_display_manager *dm = &adev->dm;
2625         struct amdgpu_dm_connector *aconnector;
2626         struct drm_connector *connector;
2627         struct drm_connector_list_iter iter;
2628         struct drm_crtc *crtc;
2629         struct drm_crtc_state *new_crtc_state;
2630         struct dm_crtc_state *dm_new_crtc_state;
2631         struct drm_plane *plane;
2632         struct drm_plane_state *new_plane_state;
2633         struct dm_plane_state *dm_new_plane_state;
2634         struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
2635         enum dc_connection_type new_connection_type = dc_connection_none;
2636         struct dc_state *dc_state;
2637         int i, r, j;
2638
2639         if (amdgpu_in_reset(adev)) {
2640                 dc_state = dm->cached_dc_state;
2641
2642                 /*
2643                  * The dc->current_state is backed up into dm->cached_dc_state
2644                  * before we commit 0 streams.
2645                  *
2646                  * DC will clear link encoder assignments on the real state
2647                  * but the changes won't propagate over to the copy we made
2648                  * before the 0 streams commit.
2649                  *
2650                  * DC expects that link encoder assignments are *not* valid
2651                  * when committing a state, so as a workaround we can copy
2652                  * off of the current state.
2653                  *
2654                  * We lose the previous assignments, but we had already
2655                  * commit 0 streams anyway.
2656                  */
2657                 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state);
2658
2659                 r = dm_dmub_hw_init(adev);
2660                 if (r)
2661                         DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
2662
2663                 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2664                 dc_resume(dm->dc);
2665
2666                 amdgpu_dm_irq_resume_early(adev);
2667
2668                 for (i = 0; i < dc_state->stream_count; i++) {
2669                         dc_state->streams[i]->mode_changed = true;
2670                         for (j = 0; j < dc_state->stream_status[i].plane_count; j++) {
2671                                 dc_state->stream_status[i].plane_states[j]->update_flags.raw
2672                                         = 0xffffffff;
2673                         }
2674                 }
2675
2676                 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2677                         amdgpu_dm_outbox_init(adev);
2678                         dc_enable_dmub_outbox(adev->dm.dc);
2679                 }
2680
2681                 WARN_ON(!dc_commit_state(dm->dc, dc_state));
2682
2683                 dm_gpureset_commit_state(dm->cached_dc_state, dm);
2684
2685                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true);
2686
2687                 dc_release_state(dm->cached_dc_state);
2688                 dm->cached_dc_state = NULL;
2689
2690                 amdgpu_dm_irq_resume_late(adev);
2691
2692                 mutex_unlock(&dm->dc_lock);
2693
2694                 return 0;
2695         }
2696         /* Recreate dc_state - DC invalidates it when setting power state to S3. */
2697         dc_release_state(dm_state->context);
2698         dm_state->context = dc_create_state(dm->dc);
2699         /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
2700         dc_resource_state_construct(dm->dc, dm_state->context);
2701
2702         /* Before powering on DC we need to re-initialize DMUB. */
2703         dm_dmub_hw_resume(adev);
2704
2705         /* Re-enable outbox interrupts for DPIA. */
2706         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2707                 amdgpu_dm_outbox_init(adev);
2708                 dc_enable_dmub_outbox(adev->dm.dc);
2709         }
2710
2711         /* power on hardware */
2712         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2713
2714         /* program HPD filter */
2715         dc_resume(dm->dc);
2716
2717         /*
2718          * early enable HPD Rx IRQ, should be done before set mode as short
2719          * pulse interrupts are used for MST
2720          */
2721         amdgpu_dm_irq_resume_early(adev);
2722
2723         /* On resume we need to rewrite the MSTM control bits to enable MST*/
2724         s3_handle_mst(ddev, false);
2725
2726         /* Do detection*/
2727         drm_connector_list_iter_begin(ddev, &iter);
2728         drm_for_each_connector_iter(connector, &iter) {
2729                 aconnector = to_amdgpu_dm_connector(connector);
2730
2731                 /*
2732                  * this is the case when traversing through already created
2733                  * MST connectors, should be skipped
2734                  */
2735                 if (aconnector->dc_link &&
2736                     aconnector->dc_link->type == dc_connection_mst_branch)
2737                         continue;
2738
2739                 mutex_lock(&aconnector->hpd_lock);
2740                 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
2741                         DRM_ERROR("KMS: Failed to detect connector\n");
2742
2743                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2744                         emulated_link_detect(aconnector->dc_link);
2745                 } else {
2746                         mutex_lock(&dm->dc_lock);
2747                         dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
2748                         mutex_unlock(&dm->dc_lock);
2749                 }
2750
2751                 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
2752                         aconnector->fake_enable = false;
2753
2754                 if (aconnector->dc_sink)
2755                         dc_sink_release(aconnector->dc_sink);
2756                 aconnector->dc_sink = NULL;
2757                 amdgpu_dm_update_connector_after_detect(aconnector);
2758                 mutex_unlock(&aconnector->hpd_lock);
2759         }
2760         drm_connector_list_iter_end(&iter);
2761
2762         /* Force mode set in atomic commit */
2763         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
2764                 new_crtc_state->active_changed = true;
2765
2766         /*
2767          * atomic_check is expected to create the dc states. We need to release
2768          * them here, since they were duplicated as part of the suspend
2769          * procedure.
2770          */
2771         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
2772                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
2773                 if (dm_new_crtc_state->stream) {
2774                         WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
2775                         dc_stream_release(dm_new_crtc_state->stream);
2776                         dm_new_crtc_state->stream = NULL;
2777                 }
2778         }
2779
2780         for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
2781                 dm_new_plane_state = to_dm_plane_state(new_plane_state);
2782                 if (dm_new_plane_state->dc_state) {
2783                         WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
2784                         dc_plane_state_release(dm_new_plane_state->dc_state);
2785                         dm_new_plane_state->dc_state = NULL;
2786                 }
2787         }
2788
2789         drm_atomic_helper_resume(ddev, dm->cached_state);
2790
2791         dm->cached_state = NULL;
2792
2793         amdgpu_dm_irq_resume_late(adev);
2794
2795         amdgpu_dm_smu_write_watermarks_table(adev);
2796
2797         return 0;
2798 }
2799
2800 /**
2801  * DOC: DM Lifecycle
2802  *
2803  * DM (and consequently DC) is registered in the amdgpu base driver as a IP
2804  * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
2805  * the base driver's device list to be initialized and torn down accordingly.
2806  *
2807  * The functions to do so are provided as hooks in &struct amd_ip_funcs.
2808  */
2809
2810 static const struct amd_ip_funcs amdgpu_dm_funcs = {
2811         .name = "dm",
2812         .early_init = dm_early_init,
2813         .late_init = dm_late_init,
2814         .sw_init = dm_sw_init,
2815         .sw_fini = dm_sw_fini,
2816         .early_fini = amdgpu_dm_early_fini,
2817         .hw_init = dm_hw_init,
2818         .hw_fini = dm_hw_fini,
2819         .suspend = dm_suspend,
2820         .resume = dm_resume,
2821         .is_idle = dm_is_idle,
2822         .wait_for_idle = dm_wait_for_idle,
2823         .check_soft_reset = dm_check_soft_reset,
2824         .soft_reset = dm_soft_reset,
2825         .set_clockgating_state = dm_set_clockgating_state,
2826         .set_powergating_state = dm_set_powergating_state,
2827 };
2828
2829 const struct amdgpu_ip_block_version dm_ip_block =
2830 {
2831         .type = AMD_IP_BLOCK_TYPE_DCE,
2832         .major = 1,
2833         .minor = 0,
2834         .rev = 0,
2835         .funcs = &amdgpu_dm_funcs,
2836 };
2837
2838
2839 /**
2840  * DOC: atomic
2841  *
2842  * *WIP*
2843  */
2844
2845 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
2846         .fb_create = amdgpu_display_user_framebuffer_create,
2847         .get_format_info = amd_get_format_info,
2848         .atomic_check = amdgpu_dm_atomic_check,
2849         .atomic_commit = drm_atomic_helper_commit,
2850 };
2851
2852 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
2853         .atomic_commit_tail = amdgpu_dm_atomic_commit_tail,
2854         .atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
2855 };
2856
2857 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
2858 {
2859         struct amdgpu_dm_backlight_caps *caps;
2860         struct amdgpu_display_manager *dm;
2861         struct drm_connector *conn_base;
2862         struct amdgpu_device *adev;
2863         struct dc_link *link = NULL;
2864         struct drm_luminance_range_info *luminance_range;
2865         int i;
2866
2867         if (!aconnector || !aconnector->dc_link)
2868                 return;
2869
2870         link = aconnector->dc_link;
2871         if (link->connector_signal != SIGNAL_TYPE_EDP)
2872                 return;
2873
2874         conn_base = &aconnector->base;
2875         adev = drm_to_adev(conn_base->dev);
2876         dm = &adev->dm;
2877         for (i = 0; i < dm->num_of_edps; i++) {
2878                 if (link == dm->backlight_link[i])
2879                         break;
2880         }
2881         if (i >= dm->num_of_edps)
2882                 return;
2883         caps = &dm->backlight_caps[i];
2884         caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
2885         caps->aux_support = false;
2886
2887         if (caps->ext_caps->bits.oled == 1 /*||
2888             caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
2889             caps->ext_caps->bits.hdr_aux_backlight_control == 1*/)
2890                 caps->aux_support = true;
2891
2892         if (amdgpu_backlight == 0)
2893                 caps->aux_support = false;
2894         else if (amdgpu_backlight == 1)
2895                 caps->aux_support = true;
2896
2897         luminance_range = &conn_base->display_info.luminance_range;
2898         caps->aux_min_input_signal = luminance_range->min_luminance;
2899         caps->aux_max_input_signal = luminance_range->max_luminance;
2900 }
2901
2902 void amdgpu_dm_update_connector_after_detect(
2903                 struct amdgpu_dm_connector *aconnector)
2904 {
2905         struct drm_connector *connector = &aconnector->base;
2906         struct drm_device *dev = connector->dev;
2907         struct dc_sink *sink;
2908
2909         /* MST handled by drm_mst framework */
2910         if (aconnector->mst_mgr.mst_state == true)
2911                 return;
2912
2913         sink = aconnector->dc_link->local_sink;
2914         if (sink)
2915                 dc_sink_retain(sink);
2916
2917         /*
2918          * Edid mgmt connector gets first update only in mode_valid hook and then
2919          * the connector sink is set to either fake or physical sink depends on link status.
2920          * Skip if already done during boot.
2921          */
2922         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
2923                         && aconnector->dc_em_sink) {
2924
2925                 /*
2926                  * For S3 resume with headless use eml_sink to fake stream
2927                  * because on resume connector->sink is set to NULL
2928                  */
2929                 mutex_lock(&dev->mode_config.mutex);
2930
2931                 if (sink) {
2932                         if (aconnector->dc_sink) {
2933                                 amdgpu_dm_update_freesync_caps(connector, NULL);
2934                                 /*
2935                                  * retain and release below are used to
2936                                  * bump up refcount for sink because the link doesn't point
2937                                  * to it anymore after disconnect, so on next crtc to connector
2938                                  * reshuffle by UMD we will get into unwanted dc_sink release
2939                                  */
2940                                 dc_sink_release(aconnector->dc_sink);
2941                         }
2942                         aconnector->dc_sink = sink;
2943                         dc_sink_retain(aconnector->dc_sink);
2944                         amdgpu_dm_update_freesync_caps(connector,
2945                                         aconnector->edid);
2946                 } else {
2947                         amdgpu_dm_update_freesync_caps(connector, NULL);
2948                         if (!aconnector->dc_sink) {
2949                                 aconnector->dc_sink = aconnector->dc_em_sink;
2950                                 dc_sink_retain(aconnector->dc_sink);
2951                         }
2952                 }
2953
2954                 mutex_unlock(&dev->mode_config.mutex);
2955
2956                 if (sink)
2957                         dc_sink_release(sink);
2958                 return;
2959         }
2960
2961         /*
2962          * TODO: temporary guard to look for proper fix
2963          * if this sink is MST sink, we should not do anything
2964          */
2965         if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2966                 dc_sink_release(sink);
2967                 return;
2968         }
2969
2970         if (aconnector->dc_sink == sink) {
2971                 /*
2972                  * We got a DP short pulse (Link Loss, DP CTS, etc...).
2973                  * Do nothing!!
2974                  */
2975                 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
2976                                 aconnector->connector_id);
2977                 if (sink)
2978                         dc_sink_release(sink);
2979                 return;
2980         }
2981
2982         DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
2983                 aconnector->connector_id, aconnector->dc_sink, sink);
2984
2985         mutex_lock(&dev->mode_config.mutex);
2986
2987         /*
2988          * 1. Update status of the drm connector
2989          * 2. Send an event and let userspace tell us what to do
2990          */
2991         if (sink) {
2992                 /*
2993                  * TODO: check if we still need the S3 mode update workaround.
2994                  * If yes, put it here.
2995                  */
2996                 if (aconnector->dc_sink) {
2997                         amdgpu_dm_update_freesync_caps(connector, NULL);
2998                         dc_sink_release(aconnector->dc_sink);
2999                 }
3000
3001                 aconnector->dc_sink = sink;
3002                 dc_sink_retain(aconnector->dc_sink);
3003                 if (sink->dc_edid.length == 0) {
3004                         aconnector->edid = NULL;
3005                         if (aconnector->dc_link->aux_mode) {
3006                                 drm_dp_cec_unset_edid(
3007                                         &aconnector->dm_dp_aux.aux);
3008                         }
3009                 } else {
3010                         aconnector->edid =
3011                                 (struct edid *)sink->dc_edid.raw_edid;
3012
3013                         if (aconnector->dc_link->aux_mode)
3014                                 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
3015                                                     aconnector->edid);
3016                 }
3017
3018                 drm_connector_update_edid_property(connector, aconnector->edid);
3019                 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
3020                 update_connector_ext_caps(aconnector);
3021         } else {
3022                 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
3023                 amdgpu_dm_update_freesync_caps(connector, NULL);
3024                 drm_connector_update_edid_property(connector, NULL);
3025                 aconnector->num_modes = 0;
3026                 dc_sink_release(aconnector->dc_sink);
3027                 aconnector->dc_sink = NULL;
3028                 aconnector->edid = NULL;
3029 #ifdef CONFIG_DRM_AMD_DC_HDCP
3030                 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
3031                 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
3032                         connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
3033 #endif
3034         }
3035
3036         mutex_unlock(&dev->mode_config.mutex);
3037
3038         update_subconnector_property(aconnector);
3039
3040         if (sink)
3041                 dc_sink_release(sink);
3042 }
3043
3044 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)
3045 {
3046         struct drm_connector *connector = &aconnector->base;
3047         struct drm_device *dev = connector->dev;
3048         enum dc_connection_type new_connection_type = dc_connection_none;
3049         struct amdgpu_device *adev = drm_to_adev(dev);
3050 #ifdef CONFIG_DRM_AMD_DC_HDCP
3051         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
3052 #endif
3053         bool ret = false;
3054
3055         if (adev->dm.disable_hpd_irq)
3056                 return;
3057
3058         /*
3059          * In case of failure or MST no need to update connector status or notify the OS
3060          * since (for MST case) MST does this in its own context.
3061          */
3062         mutex_lock(&aconnector->hpd_lock);
3063
3064 #ifdef CONFIG_DRM_AMD_DC_HDCP
3065         if (adev->dm.hdcp_workqueue) {
3066                 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
3067                 dm_con_state->update_hdcp = true;
3068         }
3069 #endif
3070         if (aconnector->fake_enable)
3071                 aconnector->fake_enable = false;
3072
3073         if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
3074                 DRM_ERROR("KMS: Failed to detect connector\n");
3075
3076         if (aconnector->base.force && new_connection_type == dc_connection_none) {
3077                 emulated_link_detect(aconnector->dc_link);
3078
3079                 drm_modeset_lock_all(dev);
3080                 dm_restore_drm_connector_state(dev, connector);
3081                 drm_modeset_unlock_all(dev);
3082
3083                 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3084                         drm_kms_helper_connector_hotplug_event(connector);
3085         } else {
3086                 mutex_lock(&adev->dm.dc_lock);
3087                 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3088                 mutex_unlock(&adev->dm.dc_lock);
3089                 if (ret) {
3090                         amdgpu_dm_update_connector_after_detect(aconnector);
3091
3092                         drm_modeset_lock_all(dev);
3093                         dm_restore_drm_connector_state(dev, connector);
3094                         drm_modeset_unlock_all(dev);
3095
3096                         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3097                                 drm_kms_helper_connector_hotplug_event(connector);
3098                 }
3099         }
3100         mutex_unlock(&aconnector->hpd_lock);
3101
3102 }
3103
3104 static void handle_hpd_irq(void *param)
3105 {
3106         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3107
3108         handle_hpd_irq_helper(aconnector);
3109
3110 }
3111
3112 static void dm_handle_mst_sideband_msg(struct amdgpu_dm_connector *aconnector)
3113 {
3114         uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
3115         uint8_t dret;
3116         bool new_irq_handled = false;
3117         int dpcd_addr;
3118         int dpcd_bytes_to_read;
3119
3120         const int max_process_count = 30;
3121         int process_count = 0;
3122
3123         const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
3124
3125         if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
3126                 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
3127                 /* DPCD 0x200 - 0x201 for downstream IRQ */
3128                 dpcd_addr = DP_SINK_COUNT;
3129         } else {
3130                 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
3131                 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
3132                 dpcd_addr = DP_SINK_COUNT_ESI;
3133         }
3134
3135         dret = drm_dp_dpcd_read(
3136                 &aconnector->dm_dp_aux.aux,
3137                 dpcd_addr,
3138                 esi,
3139                 dpcd_bytes_to_read);
3140
3141         while (dret == dpcd_bytes_to_read &&
3142                 process_count < max_process_count) {
3143                 uint8_t retry;
3144                 dret = 0;
3145
3146                 process_count++;
3147
3148                 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3149                 /* handle HPD short pulse irq */
3150                 if (aconnector->mst_mgr.mst_state)
3151                         drm_dp_mst_hpd_irq(
3152                                 &aconnector->mst_mgr,
3153                                 esi,
3154                                 &new_irq_handled);
3155
3156                 if (new_irq_handled) {
3157                         /* ACK at DPCD to notify down stream */
3158                         const int ack_dpcd_bytes_to_write =
3159                                 dpcd_bytes_to_read - 1;
3160
3161                         for (retry = 0; retry < 3; retry++) {
3162                                 uint8_t wret;
3163
3164                                 wret = drm_dp_dpcd_write(
3165                                         &aconnector->dm_dp_aux.aux,
3166                                         dpcd_addr + 1,
3167                                         &esi[1],
3168                                         ack_dpcd_bytes_to_write);
3169                                 if (wret == ack_dpcd_bytes_to_write)
3170                                         break;
3171                         }
3172
3173                         /* check if there is new irq to be handled */
3174                         dret = drm_dp_dpcd_read(
3175                                 &aconnector->dm_dp_aux.aux,
3176                                 dpcd_addr,
3177                                 esi,
3178                                 dpcd_bytes_to_read);
3179
3180                         new_irq_handled = false;
3181                 } else {
3182                         break;
3183                 }
3184         }
3185
3186         if (process_count == max_process_count)
3187                 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
3188 }
3189
3190 static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq,
3191                                                         union hpd_irq_data hpd_irq_data)
3192 {
3193         struct hpd_rx_irq_offload_work *offload_work =
3194                                 kzalloc(sizeof(*offload_work), GFP_KERNEL);
3195
3196         if (!offload_work) {
3197                 DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n");
3198                 return;
3199         }
3200
3201         INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work);
3202         offload_work->data = hpd_irq_data;
3203         offload_work->offload_wq = offload_wq;
3204
3205         queue_work(offload_wq->wq, &offload_work->work);
3206         DRM_DEBUG_KMS("queue work to handle hpd_rx offload work");
3207 }
3208
3209 static void handle_hpd_rx_irq(void *param)
3210 {
3211         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3212         struct drm_connector *connector = &aconnector->base;
3213         struct drm_device *dev = connector->dev;
3214         struct dc_link *dc_link = aconnector->dc_link;
3215         bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
3216         bool result = false;
3217         enum dc_connection_type new_connection_type = dc_connection_none;
3218         struct amdgpu_device *adev = drm_to_adev(dev);
3219         union hpd_irq_data hpd_irq_data;
3220         bool link_loss = false;
3221         bool has_left_work = false;
3222         int idx = aconnector->base.index;
3223         struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx];
3224
3225         memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
3226
3227         if (adev->dm.disable_hpd_irq)
3228                 return;
3229
3230         /*
3231          * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
3232          * conflict, after implement i2c helper, this mutex should be
3233          * retired.
3234          */
3235         mutex_lock(&aconnector->hpd_lock);
3236
3237         result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data,
3238                                                 &link_loss, true, &has_left_work);
3239
3240         if (!has_left_work)
3241                 goto out;
3242
3243         if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3244                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3245                 goto out;
3246         }
3247
3248         if (dc_link_dp_allow_hpd_rx_irq(dc_link)) {
3249                 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
3250                         hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
3251                         dm_handle_mst_sideband_msg(aconnector);
3252                         goto out;
3253                 }
3254
3255                 if (link_loss) {
3256                         bool skip = false;
3257
3258                         spin_lock(&offload_wq->offload_lock);
3259                         skip = offload_wq->is_handling_link_loss;
3260
3261                         if (!skip)
3262                                 offload_wq->is_handling_link_loss = true;
3263
3264                         spin_unlock(&offload_wq->offload_lock);
3265
3266                         if (!skip)
3267                                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3268
3269                         goto out;
3270                 }
3271         }
3272
3273 out:
3274         if (result && !is_mst_root_connector) {
3275                 /* Downstream Port status changed. */
3276                 if (!dc_link_detect_sink(dc_link, &new_connection_type))
3277                         DRM_ERROR("KMS: Failed to detect connector\n");
3278
3279                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3280                         emulated_link_detect(dc_link);
3281
3282                         if (aconnector->fake_enable)
3283                                 aconnector->fake_enable = false;
3284
3285                         amdgpu_dm_update_connector_after_detect(aconnector);
3286
3287
3288                         drm_modeset_lock_all(dev);
3289                         dm_restore_drm_connector_state(dev, connector);
3290                         drm_modeset_unlock_all(dev);
3291
3292                         drm_kms_helper_connector_hotplug_event(connector);
3293                 } else {
3294                         bool ret = false;
3295
3296                         mutex_lock(&adev->dm.dc_lock);
3297                         ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX);
3298                         mutex_unlock(&adev->dm.dc_lock);
3299
3300                         if (ret) {
3301                                 if (aconnector->fake_enable)
3302                                         aconnector->fake_enable = false;
3303
3304                                 amdgpu_dm_update_connector_after_detect(aconnector);
3305
3306                                 drm_modeset_lock_all(dev);
3307                                 dm_restore_drm_connector_state(dev, connector);
3308                                 drm_modeset_unlock_all(dev);
3309
3310                                 drm_kms_helper_connector_hotplug_event(connector);
3311                         }
3312                 }
3313         }
3314 #ifdef CONFIG_DRM_AMD_DC_HDCP
3315         if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
3316                 if (adev->dm.hdcp_workqueue)
3317                         hdcp_handle_cpirq(adev->dm.hdcp_workqueue,  aconnector->base.index);
3318         }
3319 #endif
3320
3321         if (dc_link->type != dc_connection_mst_branch)
3322                 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
3323
3324         mutex_unlock(&aconnector->hpd_lock);
3325 }
3326
3327 static void register_hpd_handlers(struct amdgpu_device *adev)
3328 {
3329         struct drm_device *dev = adev_to_drm(adev);
3330         struct drm_connector *connector;
3331         struct amdgpu_dm_connector *aconnector;
3332         const struct dc_link *dc_link;
3333         struct dc_interrupt_params int_params = {0};
3334
3335         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3336         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3337
3338         list_for_each_entry(connector,
3339                         &dev->mode_config.connector_list, head) {
3340
3341                 aconnector = to_amdgpu_dm_connector(connector);
3342                 dc_link = aconnector->dc_link;
3343
3344                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
3345                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3346                         int_params.irq_source = dc_link->irq_source_hpd;
3347
3348                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
3349                                         handle_hpd_irq,
3350                                         (void *) aconnector);
3351                 }
3352
3353                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
3354
3355                         /* Also register for DP short pulse (hpd_rx). */
3356                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3357                         int_params.irq_source = dc_link->irq_source_hpd_rx;
3358
3359                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
3360                                         handle_hpd_rx_irq,
3361                                         (void *) aconnector);
3362
3363                         if (adev->dm.hpd_rx_offload_wq)
3364                                 adev->dm.hpd_rx_offload_wq[connector->index].aconnector =
3365                                         aconnector;
3366                 }
3367         }
3368 }
3369
3370 #if defined(CONFIG_DRM_AMD_DC_SI)
3371 /* Register IRQ sources and initialize IRQ callbacks */
3372 static int dce60_register_irq_handlers(struct amdgpu_device *adev)
3373 {
3374         struct dc *dc = adev->dm.dc;
3375         struct common_irq_params *c_irq_params;
3376         struct dc_interrupt_params int_params = {0};
3377         int r;
3378         int i;
3379         unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3380
3381         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3382         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3383
3384         /*
3385          * Actions of amdgpu_irq_add_id():
3386          * 1. Register a set() function with base driver.
3387          *    Base driver will call set() function to enable/disable an
3388          *    interrupt in DC hardware.
3389          * 2. Register amdgpu_dm_irq_handler().
3390          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3391          *    coming from DC hardware.
3392          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3393          *    for acknowledging and handling. */
3394
3395         /* Use VBLANK interrupt */
3396         for (i = 0; i < adev->mode_info.num_crtc; i++) {
3397                 r = amdgpu_irq_add_id(adev, client_id, i+1 , &adev->crtc_irq);
3398                 if (r) {
3399                         DRM_ERROR("Failed to add crtc irq id!\n");
3400                         return r;
3401                 }
3402
3403                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3404                 int_params.irq_source =
3405                         dc_interrupt_to_irq_source(dc, i+1 , 0);
3406
3407                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3408
3409                 c_irq_params->adev = adev;
3410                 c_irq_params->irq_src = int_params.irq_source;
3411
3412                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3413                                 dm_crtc_high_irq, c_irq_params);
3414         }
3415
3416         /* Use GRPH_PFLIP interrupt */
3417         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3418                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3419                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3420                 if (r) {
3421                         DRM_ERROR("Failed to add page flip irq id!\n");
3422                         return r;
3423                 }
3424
3425                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3426                 int_params.irq_source =
3427                         dc_interrupt_to_irq_source(dc, i, 0);
3428
3429                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3430
3431                 c_irq_params->adev = adev;
3432                 c_irq_params->irq_src = int_params.irq_source;
3433
3434                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3435                                 dm_pflip_high_irq, c_irq_params);
3436
3437         }
3438
3439         /* HPD */
3440         r = amdgpu_irq_add_id(adev, client_id,
3441                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3442         if (r) {
3443                 DRM_ERROR("Failed to add hpd irq id!\n");
3444                 return r;
3445         }
3446
3447         register_hpd_handlers(adev);
3448
3449         return 0;
3450 }
3451 #endif
3452
3453 /* Register IRQ sources and initialize IRQ callbacks */
3454 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
3455 {
3456         struct dc *dc = adev->dm.dc;
3457         struct common_irq_params *c_irq_params;
3458         struct dc_interrupt_params int_params = {0};
3459         int r;
3460         int i;
3461         unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3462
3463         if (adev->family >= AMDGPU_FAMILY_AI)
3464                 client_id = SOC15_IH_CLIENTID_DCE;
3465
3466         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3467         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3468
3469         /*
3470          * Actions of amdgpu_irq_add_id():
3471          * 1. Register a set() function with base driver.
3472          *    Base driver will call set() function to enable/disable an
3473          *    interrupt in DC hardware.
3474          * 2. Register amdgpu_dm_irq_handler().
3475          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3476          *    coming from DC hardware.
3477          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3478          *    for acknowledging and handling. */
3479
3480         /* Use VBLANK interrupt */
3481         for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
3482                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
3483                 if (r) {
3484                         DRM_ERROR("Failed to add crtc irq id!\n");
3485                         return r;
3486                 }
3487
3488                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3489                 int_params.irq_source =
3490                         dc_interrupt_to_irq_source(dc, i, 0);
3491
3492                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3493
3494                 c_irq_params->adev = adev;
3495                 c_irq_params->irq_src = int_params.irq_source;
3496
3497                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3498                                 dm_crtc_high_irq, c_irq_params);
3499         }
3500
3501         /* Use VUPDATE interrupt */
3502         for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
3503                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
3504                 if (r) {
3505                         DRM_ERROR("Failed to add vupdate irq id!\n");
3506                         return r;
3507                 }
3508
3509                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3510                 int_params.irq_source =
3511                         dc_interrupt_to_irq_source(dc, i, 0);
3512
3513                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3514
3515                 c_irq_params->adev = adev;
3516                 c_irq_params->irq_src = int_params.irq_source;
3517
3518                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3519                                 dm_vupdate_high_irq, c_irq_params);
3520         }
3521
3522         /* Use GRPH_PFLIP interrupt */
3523         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3524                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3525                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3526                 if (r) {
3527                         DRM_ERROR("Failed to add page flip irq id!\n");
3528                         return r;
3529                 }
3530
3531                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3532                 int_params.irq_source =
3533                         dc_interrupt_to_irq_source(dc, i, 0);
3534
3535                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3536
3537                 c_irq_params->adev = adev;
3538                 c_irq_params->irq_src = int_params.irq_source;
3539
3540                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3541                                 dm_pflip_high_irq, c_irq_params);
3542
3543         }
3544
3545         /* HPD */
3546         r = amdgpu_irq_add_id(adev, client_id,
3547                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3548         if (r) {
3549                 DRM_ERROR("Failed to add hpd irq id!\n");
3550                 return r;
3551         }
3552
3553         register_hpd_handlers(adev);
3554
3555         return 0;
3556 }
3557
3558 /* Register IRQ sources and initialize IRQ callbacks */
3559 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
3560 {
3561         struct dc *dc = adev->dm.dc;
3562         struct common_irq_params *c_irq_params;
3563         struct dc_interrupt_params int_params = {0};
3564         int r;
3565         int i;
3566 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3567         static const unsigned int vrtl_int_srcid[] = {
3568                 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL,
3569                 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL,
3570                 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL,
3571                 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL,
3572                 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL,
3573                 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL
3574         };
3575 #endif
3576
3577         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3578         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3579
3580         /*
3581          * Actions of amdgpu_irq_add_id():
3582          * 1. Register a set() function with base driver.
3583          *    Base driver will call set() function to enable/disable an
3584          *    interrupt in DC hardware.
3585          * 2. Register amdgpu_dm_irq_handler().
3586          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3587          *    coming from DC hardware.
3588          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3589          *    for acknowledging and handling.
3590          */
3591
3592         /* Use VSTARTUP interrupt */
3593         for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
3594                         i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
3595                         i++) {
3596                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
3597
3598                 if (r) {
3599                         DRM_ERROR("Failed to add crtc irq id!\n");
3600                         return r;
3601                 }
3602
3603                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3604                 int_params.irq_source =
3605                         dc_interrupt_to_irq_source(dc, i, 0);
3606
3607                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3608
3609                 c_irq_params->adev = adev;
3610                 c_irq_params->irq_src = int_params.irq_source;
3611
3612                 amdgpu_dm_irq_register_interrupt(
3613                         adev, &int_params, dm_crtc_high_irq, c_irq_params);
3614         }
3615
3616         /* Use otg vertical line interrupt */
3617 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3618         for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) {
3619                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE,
3620                                 vrtl_int_srcid[i], &adev->vline0_irq);
3621
3622                 if (r) {
3623                         DRM_ERROR("Failed to add vline0 irq id!\n");
3624                         return r;
3625                 }
3626
3627                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3628                 int_params.irq_source =
3629                         dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0);
3630
3631                 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) {
3632                         DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]);
3633                         break;
3634                 }
3635
3636                 c_irq_params = &adev->dm.vline0_params[int_params.irq_source
3637                                         - DC_IRQ_SOURCE_DC1_VLINE0];
3638
3639                 c_irq_params->adev = adev;
3640                 c_irq_params->irq_src = int_params.irq_source;
3641
3642                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3643                                 dm_dcn_vertical_interrupt0_high_irq, c_irq_params);
3644         }
3645 #endif
3646
3647         /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
3648          * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
3649          * to trigger at end of each vblank, regardless of state of the lock,
3650          * matching DCE behaviour.
3651          */
3652         for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
3653              i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
3654              i++) {
3655                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
3656
3657                 if (r) {
3658                         DRM_ERROR("Failed to add vupdate irq id!\n");
3659                         return r;
3660                 }
3661
3662                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3663                 int_params.irq_source =
3664                         dc_interrupt_to_irq_source(dc, i, 0);
3665
3666                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3667
3668                 c_irq_params->adev = adev;
3669                 c_irq_params->irq_src = int_params.irq_source;
3670
3671                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3672                                 dm_vupdate_high_irq, c_irq_params);
3673         }
3674
3675         /* Use GRPH_PFLIP interrupt */
3676         for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
3677                         i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1;
3678                         i++) {
3679                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
3680                 if (r) {
3681                         DRM_ERROR("Failed to add page flip irq id!\n");
3682                         return r;
3683                 }
3684
3685                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3686                 int_params.irq_source =
3687                         dc_interrupt_to_irq_source(dc, i, 0);
3688
3689                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3690
3691                 c_irq_params->adev = adev;
3692                 c_irq_params->irq_src = int_params.irq_source;
3693
3694                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3695                                 dm_pflip_high_irq, c_irq_params);
3696
3697         }
3698
3699         /* HPD */
3700         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
3701                         &adev->hpd_irq);
3702         if (r) {
3703                 DRM_ERROR("Failed to add hpd irq id!\n");
3704                 return r;
3705         }
3706
3707         register_hpd_handlers(adev);
3708
3709         return 0;
3710 }
3711 /* Register Outbox IRQ sources and initialize IRQ callbacks */
3712 static int register_outbox_irq_handlers(struct amdgpu_device *adev)
3713 {
3714         struct dc *dc = adev->dm.dc;
3715         struct common_irq_params *c_irq_params;
3716         struct dc_interrupt_params int_params = {0};
3717         int r, i;
3718
3719         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3720         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3721
3722         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT,
3723                         &adev->dmub_outbox_irq);
3724         if (r) {
3725                 DRM_ERROR("Failed to add outbox irq id!\n");
3726                 return r;
3727         }
3728
3729         if (dc->ctx->dmub_srv) {
3730                 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT;
3731                 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3732                 int_params.irq_source =
3733                 dc_interrupt_to_irq_source(dc, i, 0);
3734
3735                 c_irq_params = &adev->dm.dmub_outbox_params[0];
3736
3737                 c_irq_params->adev = adev;
3738                 c_irq_params->irq_src = int_params.irq_source;
3739
3740                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3741                                 dm_dmub_outbox1_low_irq, c_irq_params);
3742         }
3743
3744         return 0;
3745 }
3746
3747 /*
3748  * Acquires the lock for the atomic state object and returns
3749  * the new atomic state.
3750  *
3751  * This should only be called during atomic check.
3752  */
3753 int dm_atomic_get_state(struct drm_atomic_state *state,
3754                         struct dm_atomic_state **dm_state)
3755 {
3756         struct drm_device *dev = state->dev;
3757         struct amdgpu_device *adev = drm_to_adev(dev);
3758         struct amdgpu_display_manager *dm = &adev->dm;
3759         struct drm_private_state *priv_state;
3760
3761         if (*dm_state)
3762                 return 0;
3763
3764         priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
3765         if (IS_ERR(priv_state))
3766                 return PTR_ERR(priv_state);
3767
3768         *dm_state = to_dm_atomic_state(priv_state);
3769
3770         return 0;
3771 }
3772
3773 static struct dm_atomic_state *
3774 dm_atomic_get_new_state(struct drm_atomic_state *state)
3775 {
3776         struct drm_device *dev = state->dev;
3777         struct amdgpu_device *adev = drm_to_adev(dev);
3778         struct amdgpu_display_manager *dm = &adev->dm;
3779         struct drm_private_obj *obj;
3780         struct drm_private_state *new_obj_state;
3781         int i;
3782
3783         for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
3784                 if (obj->funcs == dm->atomic_obj.funcs)
3785                         return to_dm_atomic_state(new_obj_state);
3786         }
3787
3788         return NULL;
3789 }
3790
3791 static struct drm_private_state *
3792 dm_atomic_duplicate_state(struct drm_private_obj *obj)
3793 {
3794         struct dm_atomic_state *old_state, *new_state;
3795
3796         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
3797         if (!new_state)
3798                 return NULL;
3799
3800         __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
3801
3802         old_state = to_dm_atomic_state(obj->state);
3803
3804         if (old_state && old_state->context)
3805                 new_state->context = dc_copy_state(old_state->context);
3806
3807         if (!new_state->context) {
3808                 kfree(new_state);
3809                 return NULL;
3810         }
3811
3812         return &new_state->base;
3813 }
3814
3815 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
3816                                     struct drm_private_state *state)
3817 {
3818         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
3819
3820         if (dm_state && dm_state->context)
3821                 dc_release_state(dm_state->context);
3822
3823         kfree(dm_state);
3824 }
3825
3826 static struct drm_private_state_funcs dm_atomic_state_funcs = {
3827         .atomic_duplicate_state = dm_atomic_duplicate_state,
3828         .atomic_destroy_state = dm_atomic_destroy_state,
3829 };
3830
3831 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
3832 {
3833         struct dm_atomic_state *state;
3834         int r;
3835
3836         adev->mode_info.mode_config_initialized = true;
3837
3838         adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
3839         adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
3840
3841         adev_to_drm(adev)->mode_config.max_width = 16384;
3842         adev_to_drm(adev)->mode_config.max_height = 16384;
3843
3844         adev_to_drm(adev)->mode_config.preferred_depth = 24;
3845         if (adev->asic_type == CHIP_HAWAII)
3846                 /* disable prefer shadow for now due to hibernation issues */
3847                 adev_to_drm(adev)->mode_config.prefer_shadow = 0;
3848         else
3849                 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
3850         /* indicates support for immediate flip */
3851         adev_to_drm(adev)->mode_config.async_page_flip = true;
3852
3853         state = kzalloc(sizeof(*state), GFP_KERNEL);
3854         if (!state)
3855                 return -ENOMEM;
3856
3857         state->context = dc_create_state(adev->dm.dc);
3858         if (!state->context) {
3859                 kfree(state);
3860                 return -ENOMEM;
3861         }
3862
3863         dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
3864
3865         drm_atomic_private_obj_init(adev_to_drm(adev),
3866                                     &adev->dm.atomic_obj,
3867                                     &state->base,
3868                                     &dm_atomic_state_funcs);
3869
3870         r = amdgpu_display_modeset_create_props(adev);
3871         if (r) {
3872                 dc_release_state(state->context);
3873                 kfree(state);
3874                 return r;
3875         }
3876
3877         r = amdgpu_dm_audio_init(adev);
3878         if (r) {
3879                 dc_release_state(state->context);
3880                 kfree(state);
3881                 return r;
3882         }
3883
3884         return 0;
3885 }
3886
3887 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
3888 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
3889 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
3890
3891 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
3892                                             int bl_idx)
3893 {
3894 #if defined(CONFIG_ACPI)
3895         struct amdgpu_dm_backlight_caps caps;
3896
3897         memset(&caps, 0, sizeof(caps));
3898
3899         if (dm->backlight_caps[bl_idx].caps_valid)
3900                 return;
3901
3902         amdgpu_acpi_get_backlight_caps(&caps);
3903         if (caps.caps_valid) {
3904                 dm->backlight_caps[bl_idx].caps_valid = true;
3905                 if (caps.aux_support)
3906                         return;
3907                 dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal;
3908                 dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal;
3909         } else {
3910                 dm->backlight_caps[bl_idx].min_input_signal =
3911                                 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
3912                 dm->backlight_caps[bl_idx].max_input_signal =
3913                                 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
3914         }
3915 #else
3916         if (dm->backlight_caps[bl_idx].aux_support)
3917                 return;
3918
3919         dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
3920         dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
3921 #endif
3922 }
3923
3924 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
3925                                 unsigned *min, unsigned *max)
3926 {
3927         if (!caps)
3928                 return 0;
3929
3930         if (caps->aux_support) {
3931                 // Firmware limits are in nits, DC API wants millinits.
3932                 *max = 1000 * caps->aux_max_input_signal;
3933                 *min = 1000 * caps->aux_min_input_signal;
3934         } else {
3935                 // Firmware limits are 8-bit, PWM control is 16-bit.
3936                 *max = 0x101 * caps->max_input_signal;
3937                 *min = 0x101 * caps->min_input_signal;
3938         }
3939         return 1;
3940 }
3941
3942 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
3943                                         uint32_t brightness)
3944 {
3945         unsigned min, max;
3946
3947         if (!get_brightness_range(caps, &min, &max))
3948                 return brightness;
3949
3950         // Rescale 0..255 to min..max
3951         return min + DIV_ROUND_CLOSEST((max - min) * brightness,
3952                                        AMDGPU_MAX_BL_LEVEL);
3953 }
3954
3955 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
3956                                       uint32_t brightness)
3957 {
3958         unsigned min, max;
3959
3960         if (!get_brightness_range(caps, &min, &max))
3961                 return brightness;
3962
3963         if (brightness < min)
3964                 return 0;
3965         // Rescale min..max to 0..255
3966         return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),
3967                                  max - min);
3968 }
3969
3970 static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
3971                                          int bl_idx,
3972                                          u32 user_brightness)
3973 {
3974         struct amdgpu_dm_backlight_caps caps;
3975         struct dc_link *link;
3976         u32 brightness;
3977         bool rc;
3978
3979         amdgpu_dm_update_backlight_caps(dm, bl_idx);
3980         caps = dm->backlight_caps[bl_idx];
3981
3982         dm->brightness[bl_idx] = user_brightness;
3983         /* update scratch register */
3984         if (bl_idx == 0)
3985                 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]);
3986         brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]);
3987         link = (struct dc_link *)dm->backlight_link[bl_idx];
3988
3989         /* Change brightness based on AUX property */
3990         if (caps.aux_support) {
3991                 rc = dc_link_set_backlight_level_nits(link, true, brightness,
3992                                                       AUX_BL_DEFAULT_TRANSITION_TIME_MS);
3993                 if (!rc)
3994                         DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx);
3995         } else {
3996                 rc = dc_link_set_backlight_level(link, brightness, 0);
3997                 if (!rc)
3998                         DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx);
3999         }
4000
4001         if (rc)
4002                 dm->actual_brightness[bl_idx] = user_brightness;
4003 }
4004
4005 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
4006 {
4007         struct amdgpu_display_manager *dm = bl_get_data(bd);
4008         int i;
4009
4010         for (i = 0; i < dm->num_of_edps; i++) {
4011                 if (bd == dm->backlight_dev[i])
4012                         break;
4013         }
4014         if (i >= AMDGPU_DM_MAX_NUM_EDP)
4015                 i = 0;
4016         amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness);
4017
4018         return 0;
4019 }
4020
4021 static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm,
4022                                          int bl_idx)
4023 {
4024         struct amdgpu_dm_backlight_caps caps;
4025         struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx];
4026
4027         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4028         caps = dm->backlight_caps[bl_idx];
4029
4030         if (caps.aux_support) {
4031                 u32 avg, peak;
4032                 bool rc;
4033
4034                 rc = dc_link_get_backlight_level_nits(link, &avg, &peak);
4035                 if (!rc)
4036                         return dm->brightness[bl_idx];
4037                 return convert_brightness_to_user(&caps, avg);
4038         } else {
4039                 int ret = dc_link_get_backlight_level(link);
4040
4041                 if (ret == DC_ERROR_UNEXPECTED)
4042                         return dm->brightness[bl_idx];
4043                 return convert_brightness_to_user(&caps, ret);
4044         }
4045 }
4046
4047 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
4048 {
4049         struct amdgpu_display_manager *dm = bl_get_data(bd);
4050         int i;
4051
4052         for (i = 0; i < dm->num_of_edps; i++) {
4053                 if (bd == dm->backlight_dev[i])
4054                         break;
4055         }
4056         if (i >= AMDGPU_DM_MAX_NUM_EDP)
4057                 i = 0;
4058         return amdgpu_dm_backlight_get_level(dm, i);
4059 }
4060
4061 static const struct backlight_ops amdgpu_dm_backlight_ops = {
4062         .options = BL_CORE_SUSPENDRESUME,
4063         .get_brightness = amdgpu_dm_backlight_get_brightness,
4064         .update_status  = amdgpu_dm_backlight_update_status,
4065 };
4066
4067 static void
4068 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
4069 {
4070         char bl_name[16];
4071         struct backlight_properties props = { 0 };
4072
4073         amdgpu_dm_update_backlight_caps(dm, dm->num_of_edps);
4074         dm->brightness[dm->num_of_edps] = AMDGPU_MAX_BL_LEVEL;
4075
4076         if (!acpi_video_backlight_use_native()) {
4077                 drm_info(adev_to_drm(dm->adev), "Skipping amdgpu DM backlight registration\n");
4078                 /* Try registering an ACPI video backlight device instead. */
4079                 acpi_video_register_backlight();
4080                 return;
4081         }
4082
4083         props.max_brightness = AMDGPU_MAX_BL_LEVEL;
4084         props.brightness = AMDGPU_MAX_BL_LEVEL;
4085         props.type = BACKLIGHT_RAW;
4086
4087         snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
4088                  adev_to_drm(dm->adev)->primary->index + dm->num_of_edps);
4089
4090         dm->backlight_dev[dm->num_of_edps] = backlight_device_register(bl_name,
4091                                                                        adev_to_drm(dm->adev)->dev,
4092                                                                        dm,
4093                                                                        &amdgpu_dm_backlight_ops,
4094                                                                        &props);
4095
4096         if (IS_ERR(dm->backlight_dev[dm->num_of_edps]))
4097                 DRM_ERROR("DM: Backlight registration failed!\n");
4098         else
4099                 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4100 }
4101
4102 static int initialize_plane(struct amdgpu_display_manager *dm,
4103                             struct amdgpu_mode_info *mode_info, int plane_id,
4104                             enum drm_plane_type plane_type,
4105                             const struct dc_plane_cap *plane_cap)
4106 {
4107         struct drm_plane *plane;
4108         unsigned long possible_crtcs;
4109         int ret = 0;
4110
4111         plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
4112         if (!plane) {
4113                 DRM_ERROR("KMS: Failed to allocate plane\n");
4114                 return -ENOMEM;
4115         }
4116         plane->type = plane_type;
4117
4118         /*
4119          * HACK: IGT tests expect that the primary plane for a CRTC
4120          * can only have one possible CRTC. Only expose support for
4121          * any CRTC if they're not going to be used as a primary plane
4122          * for a CRTC - like overlay or underlay planes.
4123          */
4124         possible_crtcs = 1 << plane_id;
4125         if (plane_id >= dm->dc->caps.max_streams)
4126                 possible_crtcs = 0xff;
4127
4128         ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
4129
4130         if (ret) {
4131                 DRM_ERROR("KMS: Failed to initialize plane\n");
4132                 kfree(plane);
4133                 return ret;
4134         }
4135
4136         if (mode_info)
4137                 mode_info->planes[plane_id] = plane;
4138
4139         return ret;
4140 }
4141
4142
4143 static void register_backlight_device(struct amdgpu_display_manager *dm,
4144                                       struct dc_link *link)
4145 {
4146         if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
4147             link->type != dc_connection_none) {
4148                 /*
4149                  * Event if registration failed, we should continue with
4150                  * DM initialization because not having a backlight control
4151                  * is better then a black screen.
4152                  */
4153                 if (!dm->backlight_dev[dm->num_of_edps])
4154                         amdgpu_dm_register_backlight_device(dm);
4155
4156                 if (dm->backlight_dev[dm->num_of_edps]) {
4157                         dm->backlight_link[dm->num_of_edps] = link;
4158                         dm->num_of_edps++;
4159                 }
4160         }
4161 }
4162
4163 static void amdgpu_set_panel_orientation(struct drm_connector *connector);
4164
4165 /*
4166  * In this architecture, the association
4167  * connector -> encoder -> crtc
4168  * id not really requried. The crtc and connector will hold the
4169  * display_index as an abstraction to use with DAL component
4170  *
4171  * Returns 0 on success
4172  */
4173 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4174 {
4175         struct amdgpu_display_manager *dm = &adev->dm;
4176         int32_t i;
4177         struct amdgpu_dm_connector *aconnector = NULL;
4178         struct amdgpu_encoder *aencoder = NULL;
4179         struct amdgpu_mode_info *mode_info = &adev->mode_info;
4180         uint32_t link_cnt;
4181         int32_t primary_planes;
4182         enum dc_connection_type new_connection_type = dc_connection_none;
4183         const struct dc_plane_cap *plane;
4184         bool psr_feature_enabled = false;
4185
4186         dm->display_indexes_num = dm->dc->caps.max_streams;
4187         /* Update the actual used number of crtc */
4188         adev->mode_info.num_crtc = adev->dm.display_indexes_num;
4189
4190         link_cnt = dm->dc->caps.max_links;
4191         if (amdgpu_dm_mode_config_init(dm->adev)) {
4192                 DRM_ERROR("DM: Failed to initialize mode config\n");
4193                 return -EINVAL;
4194         }
4195
4196         /* There is one primary plane per CRTC */
4197         primary_planes = dm->dc->caps.max_streams;
4198         ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
4199
4200         /*
4201          * Initialize primary planes, implicit planes for legacy IOCTLS.
4202          * Order is reversed to match iteration order in atomic check.
4203          */
4204         for (i = (primary_planes - 1); i >= 0; i--) {
4205                 plane = &dm->dc->caps.planes[i];
4206
4207                 if (initialize_plane(dm, mode_info, i,
4208                                      DRM_PLANE_TYPE_PRIMARY, plane)) {
4209                         DRM_ERROR("KMS: Failed to initialize primary plane\n");
4210                         goto fail;
4211                 }
4212         }
4213
4214         /*
4215          * Initialize overlay planes, index starting after primary planes.
4216          * These planes have a higher DRM index than the primary planes since
4217          * they should be considered as having a higher z-order.
4218          * Order is reversed to match iteration order in atomic check.
4219          *
4220          * Only support DCN for now, and only expose one so we don't encourage
4221          * userspace to use up all the pipes.
4222          */
4223         for (i = 0; i < dm->dc->caps.max_planes; ++i) {
4224                 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
4225
4226                 /* Do not create overlay if MPO disabled */
4227                 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO)
4228                         break;
4229
4230                 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
4231                         continue;
4232
4233                 if (!plane->blends_with_above || !plane->blends_with_below)
4234                         continue;
4235
4236                 if (!plane->pixel_format_support.argb8888)
4237                         continue;
4238
4239                 if (initialize_plane(dm, NULL, primary_planes + i,
4240                                      DRM_PLANE_TYPE_OVERLAY, plane)) {
4241                         DRM_ERROR("KMS: Failed to initialize overlay plane\n");
4242                         goto fail;
4243                 }
4244
4245                 /* Only create one overlay plane. */
4246                 break;
4247         }
4248
4249         for (i = 0; i < dm->dc->caps.max_streams; i++)
4250                 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
4251                         DRM_ERROR("KMS: Failed to initialize crtc\n");
4252                         goto fail;
4253                 }
4254
4255         /* Use Outbox interrupt */
4256         switch (adev->ip_versions[DCE_HWIP][0]) {
4257         case IP_VERSION(3, 0, 0):
4258         case IP_VERSION(3, 1, 2):
4259         case IP_VERSION(3, 1, 3):
4260         case IP_VERSION(3, 1, 4):
4261         case IP_VERSION(3, 1, 5):
4262         case IP_VERSION(3, 1, 6):
4263         case IP_VERSION(3, 2, 0):
4264         case IP_VERSION(3, 2, 1):
4265         case IP_VERSION(2, 1, 0):
4266                 if (register_outbox_irq_handlers(dm->adev)) {
4267                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4268                         goto fail;
4269                 }
4270                 break;
4271         default:
4272                 DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",
4273                               adev->ip_versions[DCE_HWIP][0]);
4274         }
4275
4276         /* Determine whether to enable PSR support by default. */
4277         if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) {
4278                 switch (adev->ip_versions[DCE_HWIP][0]) {
4279                 case IP_VERSION(3, 1, 2):
4280                 case IP_VERSION(3, 1, 3):
4281                 case IP_VERSION(3, 1, 4):
4282                 case IP_VERSION(3, 1, 5):
4283                 case IP_VERSION(3, 1, 6):
4284                 case IP_VERSION(3, 2, 0):
4285                 case IP_VERSION(3, 2, 1):
4286                         psr_feature_enabled = true;
4287                         break;
4288                 default:
4289                         psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK;
4290                         break;
4291                 }
4292         }
4293
4294         /* loops over all connectors on the board */
4295         for (i = 0; i < link_cnt; i++) {
4296                 struct dc_link *link = NULL;
4297
4298                 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
4299                         DRM_ERROR(
4300                                 "KMS: Cannot support more than %d display indexes\n",
4301                                         AMDGPU_DM_MAX_DISPLAY_INDEX);
4302                         continue;
4303                 }
4304
4305                 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
4306                 if (!aconnector)
4307                         goto fail;
4308
4309                 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
4310                 if (!aencoder)
4311                         goto fail;
4312
4313                 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
4314                         DRM_ERROR("KMS: Failed to initialize encoder\n");
4315                         goto fail;
4316                 }
4317
4318                 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
4319                         DRM_ERROR("KMS: Failed to initialize connector\n");
4320                         goto fail;
4321                 }
4322
4323                 link = dc_get_link_at_index(dm->dc, i);
4324
4325                 if (!dc_link_detect_sink(link, &new_connection_type))
4326                         DRM_ERROR("KMS: Failed to detect connector\n");
4327
4328                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
4329                         emulated_link_detect(link);
4330                         amdgpu_dm_update_connector_after_detect(aconnector);
4331                 } else {
4332                         bool ret = false;
4333
4334                         mutex_lock(&dm->dc_lock);
4335                         ret = dc_link_detect(link, DETECT_REASON_BOOT);
4336                         mutex_unlock(&dm->dc_lock);
4337
4338                         if (ret) {
4339                                 amdgpu_dm_update_connector_after_detect(aconnector);
4340                                 register_backlight_device(dm, link);
4341
4342                                 if (dm->num_of_edps)
4343                                         update_connector_ext_caps(aconnector);
4344
4345                                 if (psr_feature_enabled)
4346                                         amdgpu_dm_set_psr_caps(link);
4347
4348                                 /* TODO: Fix vblank control helpers to delay PSR entry to allow this when
4349                                  * PSR is also supported.
4350                                  */
4351                                 if (link->psr_settings.psr_feature_enabled)
4352                                         adev_to_drm(adev)->vblank_disable_immediate = false;
4353                         }
4354                 }
4355                 amdgpu_set_panel_orientation(&aconnector->base);
4356         }
4357
4358         /* If we didn't find a panel, notify the acpi video detection */
4359         if (dm->adev->flags & AMD_IS_APU && dm->num_of_edps == 0)
4360                 acpi_video_report_nolcd();
4361
4362         /* Software is initialized. Now we can register interrupt handlers. */
4363         switch (adev->asic_type) {
4364 #if defined(CONFIG_DRM_AMD_DC_SI)
4365         case CHIP_TAHITI:
4366         case CHIP_PITCAIRN:
4367         case CHIP_VERDE:
4368         case CHIP_OLAND:
4369                 if (dce60_register_irq_handlers(dm->adev)) {
4370                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4371                         goto fail;
4372                 }
4373                 break;
4374 #endif
4375         case CHIP_BONAIRE:
4376         case CHIP_HAWAII:
4377         case CHIP_KAVERI:
4378         case CHIP_KABINI:
4379         case CHIP_MULLINS:
4380         case CHIP_TONGA:
4381         case CHIP_FIJI:
4382         case CHIP_CARRIZO:
4383         case CHIP_STONEY:
4384         case CHIP_POLARIS11:
4385         case CHIP_POLARIS10:
4386         case CHIP_POLARIS12:
4387         case CHIP_VEGAM:
4388         case CHIP_VEGA10:
4389         case CHIP_VEGA12:
4390         case CHIP_VEGA20:
4391                 if (dce110_register_irq_handlers(dm->adev)) {
4392                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4393                         goto fail;
4394                 }
4395                 break;
4396         default:
4397                 switch (adev->ip_versions[DCE_HWIP][0]) {
4398                 case IP_VERSION(1, 0, 0):
4399                 case IP_VERSION(1, 0, 1):
4400                 case IP_VERSION(2, 0, 2):
4401                 case IP_VERSION(2, 0, 3):
4402                 case IP_VERSION(2, 0, 0):
4403                 case IP_VERSION(2, 1, 0):
4404                 case IP_VERSION(3, 0, 0):
4405                 case IP_VERSION(3, 0, 2):
4406                 case IP_VERSION(3, 0, 3):
4407                 case IP_VERSION(3, 0, 1):
4408                 case IP_VERSION(3, 1, 2):
4409                 case IP_VERSION(3, 1, 3):
4410                 case IP_VERSION(3, 1, 4):
4411                 case IP_VERSION(3, 1, 5):
4412                 case IP_VERSION(3, 1, 6):
4413                 case IP_VERSION(3, 2, 0):
4414                 case IP_VERSION(3, 2, 1):
4415                         if (dcn10_register_irq_handlers(dm->adev)) {
4416                                 DRM_ERROR("DM: Failed to initialize IRQ\n");
4417                                 goto fail;
4418                         }
4419                         break;
4420                 default:
4421                         DRM_ERROR("Unsupported DCE IP versions: 0x%X\n",
4422                                         adev->ip_versions[DCE_HWIP][0]);
4423                         goto fail;
4424                 }
4425                 break;
4426         }
4427
4428         return 0;
4429 fail:
4430         kfree(aencoder);
4431         kfree(aconnector);
4432
4433         return -EINVAL;
4434 }
4435
4436 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4437 {
4438         drm_atomic_private_obj_fini(&dm->atomic_obj);
4439         return;
4440 }
4441
4442 /******************************************************************************
4443  * amdgpu_display_funcs functions
4444  *****************************************************************************/
4445
4446 /*
4447  * dm_bandwidth_update - program display watermarks
4448  *
4449  * @adev: amdgpu_device pointer
4450  *
4451  * Calculate and program the display watermarks and line buffer allocation.
4452  */
4453 static void dm_bandwidth_update(struct amdgpu_device *adev)
4454 {
4455         /* TODO: implement later */
4456 }
4457
4458 static const struct amdgpu_display_funcs dm_display_funcs = {
4459         .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
4460         .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
4461         .backlight_set_level = NULL, /* never called for DC */
4462         .backlight_get_level = NULL, /* never called for DC */
4463         .hpd_sense = NULL,/* called unconditionally */
4464         .hpd_set_polarity = NULL, /* called unconditionally */
4465         .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4466         .page_flip_get_scanoutpos =
4467                 dm_crtc_get_scanoutpos,/* called unconditionally */
4468         .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
4469         .add_connector = NULL, /* VBIOS parsing. DAL does it. */
4470 };
4471
4472 #if defined(CONFIG_DEBUG_KERNEL_DC)
4473
4474 static ssize_t s3_debug_store(struct device *device,
4475                               struct device_attribute *attr,
4476                               const char *buf,
4477                               size_t count)
4478 {
4479         int ret;
4480         int s3_state;
4481         struct drm_device *drm_dev = dev_get_drvdata(device);
4482         struct amdgpu_device *adev = drm_to_adev(drm_dev);
4483
4484         ret = kstrtoint(buf, 0, &s3_state);
4485
4486         if (ret == 0) {
4487                 if (s3_state) {
4488                         dm_resume(adev);
4489                         drm_kms_helper_hotplug_event(adev_to_drm(adev));
4490                 } else
4491                         dm_suspend(adev);
4492         }
4493
4494         return ret == 0 ? count : 0;
4495 }
4496
4497 DEVICE_ATTR_WO(s3_debug);
4498
4499 #endif
4500
4501 static int dm_early_init(void *handle)
4502 {
4503         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4504
4505         switch (adev->asic_type) {
4506 #if defined(CONFIG_DRM_AMD_DC_SI)
4507         case CHIP_TAHITI:
4508         case CHIP_PITCAIRN:
4509         case CHIP_VERDE:
4510                 adev->mode_info.num_crtc = 6;
4511                 adev->mode_info.num_hpd = 6;
4512                 adev->mode_info.num_dig = 6;
4513                 break;
4514         case CHIP_OLAND:
4515                 adev->mode_info.num_crtc = 2;
4516                 adev->mode_info.num_hpd = 2;
4517                 adev->mode_info.num_dig = 2;
4518                 break;
4519 #endif
4520         case CHIP_BONAIRE:
4521         case CHIP_HAWAII:
4522                 adev->mode_info.num_crtc = 6;
4523                 adev->mode_info.num_hpd = 6;
4524                 adev->mode_info.num_dig = 6;
4525                 break;
4526         case CHIP_KAVERI:
4527                 adev->mode_info.num_crtc = 4;
4528                 adev->mode_info.num_hpd = 6;
4529                 adev->mode_info.num_dig = 7;
4530                 break;
4531         case CHIP_KABINI:
4532         case CHIP_MULLINS:
4533                 adev->mode_info.num_crtc = 2;
4534                 adev->mode_info.num_hpd = 6;
4535                 adev->mode_info.num_dig = 6;
4536                 break;
4537         case CHIP_FIJI:
4538         case CHIP_TONGA:
4539                 adev->mode_info.num_crtc = 6;
4540                 adev->mode_info.num_hpd = 6;
4541                 adev->mode_info.num_dig = 7;
4542                 break;
4543         case CHIP_CARRIZO:
4544                 adev->mode_info.num_crtc = 3;
4545                 adev->mode_info.num_hpd = 6;
4546                 adev->mode_info.num_dig = 9;
4547                 break;
4548         case CHIP_STONEY:
4549                 adev->mode_info.num_crtc = 2;
4550                 adev->mode_info.num_hpd = 6;
4551                 adev->mode_info.num_dig = 9;
4552                 break;
4553         case CHIP_POLARIS11:
4554         case CHIP_POLARIS12:
4555                 adev->mode_info.num_crtc = 5;
4556                 adev->mode_info.num_hpd = 5;
4557                 adev->mode_info.num_dig = 5;
4558                 break;
4559         case CHIP_POLARIS10:
4560         case CHIP_VEGAM:
4561                 adev->mode_info.num_crtc = 6;
4562                 adev->mode_info.num_hpd = 6;
4563                 adev->mode_info.num_dig = 6;
4564                 break;
4565         case CHIP_VEGA10:
4566         case CHIP_VEGA12:
4567         case CHIP_VEGA20:
4568                 adev->mode_info.num_crtc = 6;
4569                 adev->mode_info.num_hpd = 6;
4570                 adev->mode_info.num_dig = 6;
4571                 break;
4572         default:
4573
4574                 switch (adev->ip_versions[DCE_HWIP][0]) {
4575                 case IP_VERSION(2, 0, 2):
4576                 case IP_VERSION(3, 0, 0):
4577                         adev->mode_info.num_crtc = 6;
4578                         adev->mode_info.num_hpd = 6;
4579                         adev->mode_info.num_dig = 6;
4580                         break;
4581                 case IP_VERSION(2, 0, 0):
4582                 case IP_VERSION(3, 0, 2):
4583                         adev->mode_info.num_crtc = 5;
4584                         adev->mode_info.num_hpd = 5;
4585                         adev->mode_info.num_dig = 5;
4586                         break;
4587                 case IP_VERSION(2, 0, 3):
4588                 case IP_VERSION(3, 0, 3):
4589                         adev->mode_info.num_crtc = 2;
4590                         adev->mode_info.num_hpd = 2;
4591                         adev->mode_info.num_dig = 2;
4592                         break;
4593                 case IP_VERSION(1, 0, 0):
4594                 case IP_VERSION(1, 0, 1):
4595                 case IP_VERSION(3, 0, 1):
4596                 case IP_VERSION(2, 1, 0):
4597                 case IP_VERSION(3, 1, 2):
4598                 case IP_VERSION(3, 1, 3):
4599                 case IP_VERSION(3, 1, 4):
4600                 case IP_VERSION(3, 1, 5):
4601                 case IP_VERSION(3, 1, 6):
4602                 case IP_VERSION(3, 2, 0):
4603                 case IP_VERSION(3, 2, 1):
4604                         adev->mode_info.num_crtc = 4;
4605                         adev->mode_info.num_hpd = 4;
4606                         adev->mode_info.num_dig = 4;
4607                         break;
4608                 default:
4609                         DRM_ERROR("Unsupported DCE IP versions: 0x%x\n",
4610                                         adev->ip_versions[DCE_HWIP][0]);
4611                         return -EINVAL;
4612                 }
4613                 break;
4614         }
4615
4616         amdgpu_dm_set_irq_funcs(adev);
4617
4618         if (adev->mode_info.funcs == NULL)
4619                 adev->mode_info.funcs = &dm_display_funcs;
4620
4621         /*
4622          * Note: Do NOT change adev->audio_endpt_rreg and
4623          * adev->audio_endpt_wreg because they are initialised in
4624          * amdgpu_device_init()
4625          */
4626 #if defined(CONFIG_DEBUG_KERNEL_DC)
4627         device_create_file(
4628                 adev_to_drm(adev)->dev,
4629                 &dev_attr_s3_debug);
4630 #endif
4631         adev->dc_enabled = true;
4632
4633         return 0;
4634 }
4635
4636 static bool modereset_required(struct drm_crtc_state *crtc_state)
4637 {
4638         return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
4639 }
4640
4641 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
4642 {
4643         drm_encoder_cleanup(encoder);
4644         kfree(encoder);
4645 }
4646
4647 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
4648         .destroy = amdgpu_dm_encoder_destroy,
4649 };
4650
4651 static int
4652 fill_plane_color_attributes(const struct drm_plane_state *plane_state,
4653                             const enum surface_pixel_format format,
4654                             enum dc_color_space *color_space)
4655 {
4656         bool full_range;
4657
4658         *color_space = COLOR_SPACE_SRGB;
4659
4660         /* DRM color properties only affect non-RGB formats. */
4661         if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
4662                 return 0;
4663
4664         full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
4665
4666         switch (plane_state->color_encoding) {
4667         case DRM_COLOR_YCBCR_BT601:
4668                 if (full_range)
4669                         *color_space = COLOR_SPACE_YCBCR601;
4670                 else
4671                         *color_space = COLOR_SPACE_YCBCR601_LIMITED;
4672                 break;
4673
4674         case DRM_COLOR_YCBCR_BT709:
4675                 if (full_range)
4676                         *color_space = COLOR_SPACE_YCBCR709;
4677                 else
4678                         *color_space = COLOR_SPACE_YCBCR709_LIMITED;
4679                 break;
4680
4681         case DRM_COLOR_YCBCR_BT2020:
4682                 if (full_range)
4683                         *color_space = COLOR_SPACE_2020_YCBCR;
4684                 else
4685                         return -EINVAL;
4686                 break;
4687
4688         default:
4689                 return -EINVAL;
4690         }
4691
4692         return 0;
4693 }
4694
4695 static int
4696 fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
4697                             const struct drm_plane_state *plane_state,
4698                             const uint64_t tiling_flags,
4699                             struct dc_plane_info *plane_info,
4700                             struct dc_plane_address *address,
4701                             bool tmz_surface,
4702                             bool force_disable_dcc)
4703 {
4704         const struct drm_framebuffer *fb = plane_state->fb;
4705         const struct amdgpu_framebuffer *afb =
4706                 to_amdgpu_framebuffer(plane_state->fb);
4707         int ret;
4708
4709         memset(plane_info, 0, sizeof(*plane_info));
4710
4711         switch (fb->format->format) {
4712         case DRM_FORMAT_C8:
4713                 plane_info->format =
4714                         SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
4715                 break;
4716         case DRM_FORMAT_RGB565:
4717                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
4718                 break;
4719         case DRM_FORMAT_XRGB8888:
4720         case DRM_FORMAT_ARGB8888:
4721                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
4722                 break;
4723         case DRM_FORMAT_XRGB2101010:
4724         case DRM_FORMAT_ARGB2101010:
4725                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
4726                 break;
4727         case DRM_FORMAT_XBGR2101010:
4728         case DRM_FORMAT_ABGR2101010:
4729                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
4730                 break;
4731         case DRM_FORMAT_XBGR8888:
4732         case DRM_FORMAT_ABGR8888:
4733                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
4734                 break;
4735         case DRM_FORMAT_NV21:
4736                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
4737                 break;
4738         case DRM_FORMAT_NV12:
4739                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
4740                 break;
4741         case DRM_FORMAT_P010:
4742                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb;
4743                 break;
4744         case DRM_FORMAT_XRGB16161616F:
4745         case DRM_FORMAT_ARGB16161616F:
4746                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F;
4747                 break;
4748         case DRM_FORMAT_XBGR16161616F:
4749         case DRM_FORMAT_ABGR16161616F:
4750                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;
4751                 break;
4752         case DRM_FORMAT_XRGB16161616:
4753         case DRM_FORMAT_ARGB16161616:
4754                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616;
4755                 break;
4756         case DRM_FORMAT_XBGR16161616:
4757         case DRM_FORMAT_ABGR16161616:
4758                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616;
4759                 break;
4760         default:
4761                 DRM_ERROR(
4762                         "Unsupported screen format %p4cc\n",
4763                         &fb->format->format);
4764                 return -EINVAL;
4765         }
4766
4767         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
4768         case DRM_MODE_ROTATE_0:
4769                 plane_info->rotation = ROTATION_ANGLE_0;
4770                 break;
4771         case DRM_MODE_ROTATE_90:
4772                 plane_info->rotation = ROTATION_ANGLE_90;
4773                 break;
4774         case DRM_MODE_ROTATE_180:
4775                 plane_info->rotation = ROTATION_ANGLE_180;
4776                 break;
4777         case DRM_MODE_ROTATE_270:
4778                 plane_info->rotation = ROTATION_ANGLE_270;
4779                 break;
4780         default:
4781                 plane_info->rotation = ROTATION_ANGLE_0;
4782                 break;
4783         }
4784
4785
4786         plane_info->visible = true;
4787         plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
4788
4789         plane_info->layer_index = plane_state->normalized_zpos;
4790
4791         ret = fill_plane_color_attributes(plane_state, plane_info->format,
4792                                           &plane_info->color_space);
4793         if (ret)
4794                 return ret;
4795
4796         ret = fill_plane_buffer_attributes(adev, afb, plane_info->format,
4797                                            plane_info->rotation, tiling_flags,
4798                                            &plane_info->tiling_info,
4799                                            &plane_info->plane_size,
4800                                            &plane_info->dcc, address,
4801                                            tmz_surface, force_disable_dcc);
4802         if (ret)
4803                 return ret;
4804
4805         fill_blending_from_plane_state(
4806                 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha,
4807                 &plane_info->global_alpha, &plane_info->global_alpha_value);
4808
4809         return 0;
4810 }
4811
4812 static int fill_dc_plane_attributes(struct amdgpu_device *adev,
4813                                     struct dc_plane_state *dc_plane_state,
4814                                     struct drm_plane_state *plane_state,
4815                                     struct drm_crtc_state *crtc_state)
4816 {
4817         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
4818         struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb;
4819         struct dc_scaling_info scaling_info;
4820         struct dc_plane_info plane_info;
4821         int ret;
4822         bool force_disable_dcc = false;
4823
4824         ret = fill_dc_scaling_info(adev, plane_state, &scaling_info);
4825         if (ret)
4826                 return ret;
4827
4828         dc_plane_state->src_rect = scaling_info.src_rect;
4829         dc_plane_state->dst_rect = scaling_info.dst_rect;
4830         dc_plane_state->clip_rect = scaling_info.clip_rect;
4831         dc_plane_state->scaling_quality = scaling_info.scaling_quality;
4832
4833         force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
4834         ret = fill_dc_plane_info_and_addr(adev, plane_state,
4835                                           afb->tiling_flags,
4836                                           &plane_info,
4837                                           &dc_plane_state->address,
4838                                           afb->tmz_surface,
4839                                           force_disable_dcc);
4840         if (ret)
4841                 return ret;
4842
4843         dc_plane_state->format = plane_info.format;
4844         dc_plane_state->color_space = plane_info.color_space;
4845         dc_plane_state->format = plane_info.format;
4846         dc_plane_state->plane_size = plane_info.plane_size;
4847         dc_plane_state->rotation = plane_info.rotation;
4848         dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
4849         dc_plane_state->stereo_format = plane_info.stereo_format;
4850         dc_plane_state->tiling_info = plane_info.tiling_info;
4851         dc_plane_state->visible = plane_info.visible;
4852         dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
4853         dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha;
4854         dc_plane_state->global_alpha = plane_info.global_alpha;
4855         dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
4856         dc_plane_state->dcc = plane_info.dcc;
4857         dc_plane_state->layer_index = plane_info.layer_index;
4858         dc_plane_state->flip_int_enabled = true;
4859
4860         /*
4861          * Always set input transfer function, since plane state is refreshed
4862          * every time.
4863          */
4864         ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
4865         if (ret)
4866                 return ret;
4867
4868         return 0;
4869 }
4870
4871 static inline void fill_dc_dirty_rect(struct drm_plane *plane,
4872                                       struct rect *dirty_rect, int32_t x,
4873                                       int32_t y, int32_t width, int32_t height,
4874                                       int *i, bool ffu)
4875 {
4876         if (*i > DC_MAX_DIRTY_RECTS)
4877                 return;
4878
4879         if (*i == DC_MAX_DIRTY_RECTS)
4880                 goto out;
4881
4882         dirty_rect->x = x;
4883         dirty_rect->y = y;
4884         dirty_rect->width = width;
4885         dirty_rect->height = height;
4886
4887         if (ffu)
4888                 drm_dbg(plane->dev,
4889                         "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n",
4890                         plane->base.id, width, height);
4891         else
4892                 drm_dbg(plane->dev,
4893                         "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)",
4894                         plane->base.id, x, y, width, height);
4895
4896 out:
4897         (*i)++;
4898 }
4899
4900 /**
4901  * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates
4902  *
4903  * @plane: DRM plane containing dirty regions that need to be flushed to the eDP
4904  *         remote fb
4905  * @old_plane_state: Old state of @plane
4906  * @new_plane_state: New state of @plane
4907  * @crtc_state: New state of CRTC connected to the @plane
4908  * @flip_addrs: DC flip tracking struct, which also tracts dirty rects
4909  *
4910  * For PSR SU, DC informs the DMUB uController of dirty rectangle regions
4911  * (referred to as "damage clips" in DRM nomenclature) that require updating on
4912  * the eDP remote buffer. The responsibility of specifying the dirty regions is
4913  * amdgpu_dm's.
4914  *
4915  * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the
4916  * plane with regions that require flushing to the eDP remote buffer. In
4917  * addition, certain use cases - such as cursor and multi-plane overlay (MPO) -
4918  * implicitly provide damage clips without any client support via the plane
4919  * bounds.
4920  */
4921 static void fill_dc_dirty_rects(struct drm_plane *plane,
4922                                 struct drm_plane_state *old_plane_state,
4923                                 struct drm_plane_state *new_plane_state,
4924                                 struct drm_crtc_state *crtc_state,
4925                                 struct dc_flip_addrs *flip_addrs)
4926 {
4927         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
4928         struct rect *dirty_rects = flip_addrs->dirty_rects;
4929         uint32_t num_clips;
4930         struct drm_mode_rect *clips;
4931         bool bb_changed;
4932         bool fb_changed;
4933         uint32_t i = 0;
4934
4935         /*
4936          * Cursor plane has it's own dirty rect update interface. See
4937          * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data
4938          */
4939         if (plane->type == DRM_PLANE_TYPE_CURSOR)
4940                 return;
4941
4942         num_clips = drm_plane_get_damage_clips_count(new_plane_state);
4943         clips = drm_plane_get_damage_clips(new_plane_state);
4944
4945         if (!dm_crtc_state->mpo_requested) {
4946                 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS)
4947                         goto ffu;
4948
4949                 for (; flip_addrs->dirty_rect_count < num_clips; clips++)
4950                         fill_dc_dirty_rect(new_plane_state->plane,
4951                                            &dirty_rects[i], clips->x1,
4952                                            clips->y1, clips->x2 - clips->x1,
4953                                            clips->y2 - clips->y1,
4954                                            &flip_addrs->dirty_rect_count,
4955                                            false);
4956                 return;
4957         }
4958
4959         /*
4960          * MPO is requested. Add entire plane bounding box to dirty rects if
4961          * flipped to or damaged.
4962          *
4963          * If plane is moved or resized, also add old bounding box to dirty
4964          * rects.
4965          */
4966         fb_changed = old_plane_state->fb->base.id !=
4967                      new_plane_state->fb->base.id;
4968         bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x ||
4969                       old_plane_state->crtc_y != new_plane_state->crtc_y ||
4970                       old_plane_state->crtc_w != new_plane_state->crtc_w ||
4971                       old_plane_state->crtc_h != new_plane_state->crtc_h);
4972
4973         drm_dbg(plane->dev,
4974                 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n",
4975                 new_plane_state->plane->base.id,
4976                 bb_changed, fb_changed, num_clips);
4977
4978         if (bb_changed) {
4979                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
4980                                    new_plane_state->crtc_x,
4981                                    new_plane_state->crtc_y,
4982                                    new_plane_state->crtc_w,
4983                                    new_plane_state->crtc_h, &i, false);
4984
4985                 /* Add old plane bounding-box if plane is moved or resized */
4986                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
4987                                    old_plane_state->crtc_x,
4988                                    old_plane_state->crtc_y,
4989                                    old_plane_state->crtc_w,
4990                                    old_plane_state->crtc_h, &i, false);
4991         }
4992
4993         if (num_clips) {
4994                 for (; i < num_clips; clips++)
4995                         fill_dc_dirty_rect(new_plane_state->plane,
4996                                            &dirty_rects[i], clips->x1,
4997                                            clips->y1, clips->x2 - clips->x1,
4998                                            clips->y2 - clips->y1, &i, false);
4999         } else if (fb_changed && !bb_changed) {
5000                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5001                                    new_plane_state->crtc_x,
5002                                    new_plane_state->crtc_y,
5003                                    new_plane_state->crtc_w,
5004                                    new_plane_state->crtc_h, &i, false);
5005         }
5006
5007         if (i > DC_MAX_DIRTY_RECTS)
5008                 goto ffu;
5009
5010         flip_addrs->dirty_rect_count = i;
5011         return;
5012
5013 ffu:
5014         fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0,
5015                            dm_crtc_state->base.mode.crtc_hdisplay,
5016                            dm_crtc_state->base.mode.crtc_vdisplay,
5017                            &flip_addrs->dirty_rect_count, true);
5018 }
5019
5020 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
5021                                            const struct dm_connector_state *dm_state,
5022                                            struct dc_stream_state *stream)
5023 {
5024         enum amdgpu_rmx_type rmx_type;
5025
5026         struct rect src = { 0 }; /* viewport in composition space*/
5027         struct rect dst = { 0 }; /* stream addressable area */
5028
5029         /* no mode. nothing to be done */
5030         if (!mode)
5031                 return;
5032
5033         /* Full screen scaling by default */
5034         src.width = mode->hdisplay;
5035         src.height = mode->vdisplay;
5036         dst.width = stream->timing.h_addressable;
5037         dst.height = stream->timing.v_addressable;
5038
5039         if (dm_state) {
5040                 rmx_type = dm_state->scaling;
5041                 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
5042                         if (src.width * dst.height <
5043                                         src.height * dst.width) {
5044                                 /* height needs less upscaling/more downscaling */
5045                                 dst.width = src.width *
5046                                                 dst.height / src.height;
5047                         } else {
5048                                 /* width needs less upscaling/more downscaling */
5049                                 dst.height = src.height *
5050                                                 dst.width / src.width;
5051                         }
5052                 } else if (rmx_type == RMX_CENTER) {
5053                         dst = src;
5054                 }
5055
5056                 dst.x = (stream->timing.h_addressable - dst.width) / 2;
5057                 dst.y = (stream->timing.v_addressable - dst.height) / 2;
5058
5059                 if (dm_state->underscan_enable) {
5060                         dst.x += dm_state->underscan_hborder / 2;
5061                         dst.y += dm_state->underscan_vborder / 2;
5062                         dst.width -= dm_state->underscan_hborder;
5063                         dst.height -= dm_state->underscan_vborder;
5064                 }
5065         }
5066
5067         stream->src = src;
5068         stream->dst = dst;
5069
5070         DRM_DEBUG_KMS("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",
5071                       dst.x, dst.y, dst.width, dst.height);
5072
5073 }
5074
5075 static enum dc_color_depth
5076 convert_color_depth_from_display_info(const struct drm_connector *connector,
5077                                       bool is_y420, int requested_bpc)
5078 {
5079         uint8_t bpc;
5080
5081         if (is_y420) {
5082                 bpc = 8;
5083
5084                 /* Cap display bpc based on HDMI 2.0 HF-VSDB */
5085                 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)
5086                         bpc = 16;
5087                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
5088                         bpc = 12;
5089                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
5090                         bpc = 10;
5091         } else {
5092                 bpc = (uint8_t)connector->display_info.bpc;
5093                 /* Assume 8 bpc by default if no bpc is specified. */
5094                 bpc = bpc ? bpc : 8;
5095         }
5096
5097         if (requested_bpc > 0) {
5098                 /*
5099                  * Cap display bpc based on the user requested value.
5100                  *
5101                  * The value for state->max_bpc may not correctly updated
5102                  * depending on when the connector gets added to the state
5103                  * or if this was called outside of atomic check, so it
5104                  * can't be used directly.
5105                  */
5106                 bpc = min_t(u8, bpc, requested_bpc);
5107
5108                 /* Round down to the nearest even number. */
5109                 bpc = bpc - (bpc & 1);
5110         }
5111
5112         switch (bpc) {
5113         case 0:
5114                 /*
5115                  * Temporary Work around, DRM doesn't parse color depth for
5116                  * EDID revision before 1.4
5117                  * TODO: Fix edid parsing
5118                  */
5119                 return COLOR_DEPTH_888;
5120         case 6:
5121                 return COLOR_DEPTH_666;
5122         case 8:
5123                 return COLOR_DEPTH_888;
5124         case 10:
5125                 return COLOR_DEPTH_101010;
5126         case 12:
5127                 return COLOR_DEPTH_121212;
5128         case 14:
5129                 return COLOR_DEPTH_141414;
5130         case 16:
5131                 return COLOR_DEPTH_161616;
5132         default:
5133                 return COLOR_DEPTH_UNDEFINED;
5134         }
5135 }
5136
5137 static enum dc_aspect_ratio
5138 get_aspect_ratio(const struct drm_display_mode *mode_in)
5139 {
5140         /* 1-1 mapping, since both enums follow the HDMI spec. */
5141         return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
5142 }
5143
5144 static enum dc_color_space
5145 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
5146 {
5147         enum dc_color_space color_space = COLOR_SPACE_SRGB;
5148
5149         switch (dc_crtc_timing->pixel_encoding) {
5150         case PIXEL_ENCODING_YCBCR422:
5151         case PIXEL_ENCODING_YCBCR444:
5152         case PIXEL_ENCODING_YCBCR420:
5153         {
5154                 /*
5155                  * 27030khz is the separation point between HDTV and SDTV
5156                  * according to HDMI spec, we use YCbCr709 and YCbCr601
5157                  * respectively
5158                  */
5159                 if (dc_crtc_timing->pix_clk_100hz > 270300) {
5160                         if (dc_crtc_timing->flags.Y_ONLY)
5161                                 color_space =
5162                                         COLOR_SPACE_YCBCR709_LIMITED;
5163                         else
5164                                 color_space = COLOR_SPACE_YCBCR709;
5165                 } else {
5166                         if (dc_crtc_timing->flags.Y_ONLY)
5167                                 color_space =
5168                                         COLOR_SPACE_YCBCR601_LIMITED;
5169                         else
5170                                 color_space = COLOR_SPACE_YCBCR601;
5171                 }
5172
5173         }
5174         break;
5175         case PIXEL_ENCODING_RGB:
5176                 color_space = COLOR_SPACE_SRGB;
5177                 break;
5178
5179         default:
5180                 WARN_ON(1);
5181                 break;
5182         }
5183
5184         return color_space;
5185 }
5186
5187 static bool adjust_colour_depth_from_display_info(
5188         struct dc_crtc_timing *timing_out,
5189         const struct drm_display_info *info)
5190 {
5191         enum dc_color_depth depth = timing_out->display_color_depth;
5192         int normalized_clk;
5193         do {
5194                 normalized_clk = timing_out->pix_clk_100hz / 10;
5195                 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
5196                 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
5197                         normalized_clk /= 2;
5198                 /* Adjusting pix clock following on HDMI spec based on colour depth */
5199                 switch (depth) {
5200                 case COLOR_DEPTH_888:
5201                         break;
5202                 case COLOR_DEPTH_101010:
5203                         normalized_clk = (normalized_clk * 30) / 24;
5204                         break;
5205                 case COLOR_DEPTH_121212:
5206                         normalized_clk = (normalized_clk * 36) / 24;
5207                         break;
5208                 case COLOR_DEPTH_161616:
5209                         normalized_clk = (normalized_clk * 48) / 24;
5210                         break;
5211                 default:
5212                         /* The above depths are the only ones valid for HDMI. */
5213                         return false;
5214                 }
5215                 if (normalized_clk <= info->max_tmds_clock) {
5216                         timing_out->display_color_depth = depth;
5217                         return true;
5218                 }
5219         } while (--depth > COLOR_DEPTH_666);
5220         return false;
5221 }
5222
5223 static void fill_stream_properties_from_drm_display_mode(
5224         struct dc_stream_state *stream,
5225         const struct drm_display_mode *mode_in,
5226         const struct drm_connector *connector,
5227         const struct drm_connector_state *connector_state,
5228         const struct dc_stream_state *old_stream,
5229         int requested_bpc)
5230 {
5231         struct dc_crtc_timing *timing_out = &stream->timing;
5232         const struct drm_display_info *info = &connector->display_info;
5233         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5234         struct hdmi_vendor_infoframe hv_frame;
5235         struct hdmi_avi_infoframe avi_frame;
5236
5237         memset(&hv_frame, 0, sizeof(hv_frame));
5238         memset(&avi_frame, 0, sizeof(avi_frame));
5239
5240         timing_out->h_border_left = 0;
5241         timing_out->h_border_right = 0;
5242         timing_out->v_border_top = 0;
5243         timing_out->v_border_bottom = 0;
5244         /* TODO: un-hardcode */
5245         if (drm_mode_is_420_only(info, mode_in)
5246                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5247                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5248         else if (drm_mode_is_420_also(info, mode_in)
5249                         && aconnector->force_yuv420_output)
5250                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5251         else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444)
5252                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5253                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
5254         else
5255                 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
5256
5257         timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
5258         timing_out->display_color_depth = convert_color_depth_from_display_info(
5259                 connector,
5260                 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420),
5261                 requested_bpc);
5262         timing_out->scan_type = SCANNING_TYPE_NODATA;
5263         timing_out->hdmi_vic = 0;
5264
5265         if (old_stream) {
5266                 timing_out->vic = old_stream->timing.vic;
5267                 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
5268                 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
5269         } else {
5270                 timing_out->vic = drm_match_cea_mode(mode_in);
5271                 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
5272                         timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
5273                 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
5274                         timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
5275         }
5276
5277         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5278                 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
5279                 timing_out->vic = avi_frame.video_code;
5280                 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
5281                 timing_out->hdmi_vic = hv_frame.vic;
5282         }
5283
5284         if (is_freesync_video_mode(mode_in, aconnector)) {
5285                 timing_out->h_addressable = mode_in->hdisplay;
5286                 timing_out->h_total = mode_in->htotal;
5287                 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start;
5288                 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay;
5289                 timing_out->v_total = mode_in->vtotal;
5290                 timing_out->v_addressable = mode_in->vdisplay;
5291                 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay;
5292                 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start;
5293                 timing_out->pix_clk_100hz = mode_in->clock * 10;
5294         } else {
5295                 timing_out->h_addressable = mode_in->crtc_hdisplay;
5296                 timing_out->h_total = mode_in->crtc_htotal;
5297                 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
5298                 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
5299                 timing_out->v_total = mode_in->crtc_vtotal;
5300                 timing_out->v_addressable = mode_in->crtc_vdisplay;
5301                 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
5302                 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
5303                 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
5304         }
5305
5306         timing_out->aspect_ratio = get_aspect_ratio(mode_in);
5307
5308         stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
5309         stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
5310         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5311                 if (!adjust_colour_depth_from_display_info(timing_out, info) &&
5312                     drm_mode_is_420_also(info, mode_in) &&
5313                     timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
5314                         timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5315                         adjust_colour_depth_from_display_info(timing_out, info);
5316                 }
5317         }
5318
5319         stream->output_color_space = get_output_color_space(timing_out);
5320 }
5321
5322 static void fill_audio_info(struct audio_info *audio_info,
5323                             const struct drm_connector *drm_connector,
5324                             const struct dc_sink *dc_sink)
5325 {
5326         int i = 0;
5327         int cea_revision = 0;
5328         const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
5329
5330         audio_info->manufacture_id = edid_caps->manufacturer_id;
5331         audio_info->product_id = edid_caps->product_id;
5332
5333         cea_revision = drm_connector->display_info.cea_rev;
5334
5335         strscpy(audio_info->display_name,
5336                 edid_caps->display_name,
5337                 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
5338
5339         if (cea_revision >= 3) {
5340                 audio_info->mode_count = edid_caps->audio_mode_count;
5341
5342                 for (i = 0; i < audio_info->mode_count; ++i) {
5343                         audio_info->modes[i].format_code =
5344                                         (enum audio_format_code)
5345                                         (edid_caps->audio_modes[i].format_code);
5346                         audio_info->modes[i].channel_count =
5347                                         edid_caps->audio_modes[i].channel_count;
5348                         audio_info->modes[i].sample_rates.all =
5349                                         edid_caps->audio_modes[i].sample_rate;
5350                         audio_info->modes[i].sample_size =
5351                                         edid_caps->audio_modes[i].sample_size;
5352                 }
5353         }
5354
5355         audio_info->flags.all = edid_caps->speaker_flags;
5356
5357         /* TODO: We only check for the progressive mode, check for interlace mode too */
5358         if (drm_connector->latency_present[0]) {
5359                 audio_info->video_latency = drm_connector->video_latency[0];
5360                 audio_info->audio_latency = drm_connector->audio_latency[0];
5361         }
5362
5363         /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
5364
5365 }
5366
5367 static void
5368 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
5369                                       struct drm_display_mode *dst_mode)
5370 {
5371         dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
5372         dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
5373         dst_mode->crtc_clock = src_mode->crtc_clock;
5374         dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
5375         dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
5376         dst_mode->crtc_hsync_start =  src_mode->crtc_hsync_start;
5377         dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
5378         dst_mode->crtc_htotal = src_mode->crtc_htotal;
5379         dst_mode->crtc_hskew = src_mode->crtc_hskew;
5380         dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
5381         dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
5382         dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
5383         dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
5384         dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
5385 }
5386
5387 static void
5388 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
5389                                         const struct drm_display_mode *native_mode,
5390                                         bool scale_enabled)
5391 {
5392         if (scale_enabled) {
5393                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5394         } else if (native_mode->clock == drm_mode->clock &&
5395                         native_mode->htotal == drm_mode->htotal &&
5396                         native_mode->vtotal == drm_mode->vtotal) {
5397                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5398         } else {
5399                 /* no scaling nor amdgpu inserted, no need to patch */
5400         }
5401 }
5402
5403 static struct dc_sink *
5404 create_fake_sink(struct amdgpu_dm_connector *aconnector)
5405 {
5406         struct dc_sink_init_data sink_init_data = { 0 };
5407         struct dc_sink *sink = NULL;
5408         sink_init_data.link = aconnector->dc_link;
5409         sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
5410
5411         sink = dc_sink_create(&sink_init_data);
5412         if (!sink) {
5413                 DRM_ERROR("Failed to create sink!\n");
5414                 return NULL;
5415         }
5416         sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
5417
5418         return sink;
5419 }
5420
5421 static void set_multisync_trigger_params(
5422                 struct dc_stream_state *stream)
5423 {
5424         struct dc_stream_state *master = NULL;
5425
5426         if (stream->triggered_crtc_reset.enabled) {
5427                 master = stream->triggered_crtc_reset.event_source;
5428                 stream->triggered_crtc_reset.event =
5429                         master->timing.flags.VSYNC_POSITIVE_POLARITY ?
5430                         CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING;
5431                 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL;
5432         }
5433 }
5434
5435 static void set_master_stream(struct dc_stream_state *stream_set[],
5436                               int stream_count)
5437 {
5438         int j, highest_rfr = 0, master_stream = 0;
5439
5440         for (j = 0;  j < stream_count; j++) {
5441                 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
5442                         int refresh_rate = 0;
5443
5444                         refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
5445                                 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
5446                         if (refresh_rate > highest_rfr) {
5447                                 highest_rfr = refresh_rate;
5448                                 master_stream = j;
5449                         }
5450                 }
5451         }
5452         for (j = 0;  j < stream_count; j++) {
5453                 if (stream_set[j])
5454                         stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
5455         }
5456 }
5457
5458 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
5459 {
5460         int i = 0;
5461         struct dc_stream_state *stream;
5462
5463         if (context->stream_count < 2)
5464                 return;
5465         for (i = 0; i < context->stream_count ; i++) {
5466                 if (!context->streams[i])
5467                         continue;
5468                 /*
5469                  * TODO: add a function to read AMD VSDB bits and set
5470                  * crtc_sync_master.multi_sync_enabled flag
5471                  * For now it's set to false
5472                  */
5473         }
5474
5475         set_master_stream(context->streams, context->stream_count);
5476
5477         for (i = 0; i < context->stream_count ; i++) {
5478                 stream = context->streams[i];
5479
5480                 if (!stream)
5481                         continue;
5482
5483                 set_multisync_trigger_params(stream);
5484         }
5485 }
5486
5487 /**
5488  * DOC: FreeSync Video
5489  *
5490  * When a userspace application wants to play a video, the content follows a
5491  * standard format definition that usually specifies the FPS for that format.
5492  * The below list illustrates some video format and the expected FPS,
5493  * respectively:
5494  *
5495  * - TV/NTSC (23.976 FPS)
5496  * - Cinema (24 FPS)
5497  * - TV/PAL (25 FPS)
5498  * - TV/NTSC (29.97 FPS)
5499  * - TV/NTSC (30 FPS)
5500  * - Cinema HFR (48 FPS)
5501  * - TV/PAL (50 FPS)
5502  * - Commonly used (60 FPS)
5503  * - Multiples of 24 (48,72,96 FPS)
5504  *
5505  * The list of standards video format is not huge and can be added to the
5506  * connector modeset list beforehand. With that, userspace can leverage
5507  * FreeSync to extends the front porch in order to attain the target refresh
5508  * rate. Such a switch will happen seamlessly, without screen blanking or
5509  * reprogramming of the output in any other way. If the userspace requests a
5510  * modesetting change compatible with FreeSync modes that only differ in the
5511  * refresh rate, DC will skip the full update and avoid blink during the
5512  * transition. For example, the video player can change the modesetting from
5513  * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without
5514  * causing any display blink. This same concept can be applied to a mode
5515  * setting change.
5516  */
5517 static struct drm_display_mode *
5518 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
5519                 bool use_probed_modes)
5520 {
5521         struct drm_display_mode *m, *m_pref = NULL;
5522         u16 current_refresh, highest_refresh;
5523         struct list_head *list_head = use_probed_modes ?
5524                 &aconnector->base.probed_modes :
5525                 &aconnector->base.modes;
5526
5527         if (aconnector->freesync_vid_base.clock != 0)
5528                 return &aconnector->freesync_vid_base;
5529
5530         /* Find the preferred mode */
5531         list_for_each_entry (m, list_head, head) {
5532                 if (m->type & DRM_MODE_TYPE_PREFERRED) {
5533                         m_pref = m;
5534                         break;
5535                 }
5536         }
5537
5538         if (!m_pref) {
5539                 /* Probably an EDID with no preferred mode. Fallback to first entry */
5540                 m_pref = list_first_entry_or_null(
5541                                 &aconnector->base.modes, struct drm_display_mode, head);
5542                 if (!m_pref) {
5543                         DRM_DEBUG_DRIVER("No preferred mode found in EDID\n");
5544                         return NULL;
5545                 }
5546         }
5547
5548         highest_refresh = drm_mode_vrefresh(m_pref);
5549
5550         /*
5551          * Find the mode with highest refresh rate with same resolution.
5552          * For some monitors, preferred mode is not the mode with highest
5553          * supported refresh rate.
5554          */
5555         list_for_each_entry (m, list_head, head) {
5556                 current_refresh  = drm_mode_vrefresh(m);
5557
5558                 if (m->hdisplay == m_pref->hdisplay &&
5559                     m->vdisplay == m_pref->vdisplay &&
5560                     highest_refresh < current_refresh) {
5561                         highest_refresh = current_refresh;
5562                         m_pref = m;
5563                 }
5564         }
5565
5566         drm_mode_copy(&aconnector->freesync_vid_base, m_pref);
5567         return m_pref;
5568 }
5569
5570 static bool is_freesync_video_mode(const struct drm_display_mode *mode,
5571                 struct amdgpu_dm_connector *aconnector)
5572 {
5573         struct drm_display_mode *high_mode;
5574         int timing_diff;
5575
5576         high_mode = get_highest_refresh_rate_mode(aconnector, false);
5577         if (!high_mode || !mode)
5578                 return false;
5579
5580         timing_diff = high_mode->vtotal - mode->vtotal;
5581
5582         if (high_mode->clock == 0 || high_mode->clock != mode->clock ||
5583             high_mode->hdisplay != mode->hdisplay ||
5584             high_mode->vdisplay != mode->vdisplay ||
5585             high_mode->hsync_start != mode->hsync_start ||
5586             high_mode->hsync_end != mode->hsync_end ||
5587             high_mode->htotal != mode->htotal ||
5588             high_mode->hskew != mode->hskew ||
5589             high_mode->vscan != mode->vscan ||
5590             high_mode->vsync_start - mode->vsync_start != timing_diff ||
5591             high_mode->vsync_end - mode->vsync_end != timing_diff)
5592                 return false;
5593         else
5594                 return true;
5595 }
5596
5597 #if defined(CONFIG_DRM_AMD_DC_DCN)
5598 static void update_dsc_caps(struct amdgpu_dm_connector *aconnector,
5599                             struct dc_sink *sink, struct dc_stream_state *stream,
5600                             struct dsc_dec_dpcd_caps *dsc_caps)
5601 {
5602         stream->timing.flags.DSC = 0;
5603         dsc_caps->is_dsc_supported = false;
5604
5605         if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
5606             sink->sink_signal == SIGNAL_TYPE_EDP)) {
5607                 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE ||
5608                         sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
5609                         dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
5610                                 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
5611                                 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
5612                                 dsc_caps);
5613         }
5614 }
5615
5616
5617 static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
5618                                     struct dc_sink *sink, struct dc_stream_state *stream,
5619                                     struct dsc_dec_dpcd_caps *dsc_caps,
5620                                     uint32_t max_dsc_target_bpp_limit_override)
5621 {
5622         const struct dc_link_settings *verified_link_cap = NULL;
5623         uint32_t link_bw_in_kbps;
5624         uint32_t edp_min_bpp_x16, edp_max_bpp_x16;
5625         struct dc *dc = sink->ctx->dc;
5626         struct dc_dsc_bw_range bw_range = {0};
5627         struct dc_dsc_config dsc_cfg = {0};
5628
5629         verified_link_cap = dc_link_get_link_cap(stream->link);
5630         link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap);
5631         edp_min_bpp_x16 = 8 * 16;
5632         edp_max_bpp_x16 = 8 * 16;
5633
5634         if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel)
5635                 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel;
5636
5637         if (edp_max_bpp_x16 < edp_min_bpp_x16)
5638                 edp_min_bpp_x16 = edp_max_bpp_x16;
5639
5640         if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0],
5641                                 dc->debug.dsc_min_slice_height_override,
5642                                 edp_min_bpp_x16, edp_max_bpp_x16,
5643                                 dsc_caps,
5644                                 &stream->timing,
5645                                 &bw_range)) {
5646
5647                 if (bw_range.max_kbps < link_bw_in_kbps) {
5648                         if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5649                                         dsc_caps,
5650                                         dc->debug.dsc_min_slice_height_override,
5651                                         max_dsc_target_bpp_limit_override,
5652                                         0,
5653                                         &stream->timing,
5654                                         &dsc_cfg)) {
5655                                 stream->timing.dsc_cfg = dsc_cfg;
5656                                 stream->timing.flags.DSC = 1;
5657                                 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16;
5658                         }
5659                         return;
5660                 }
5661         }
5662
5663         if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5664                                 dsc_caps,
5665                                 dc->debug.dsc_min_slice_height_override,
5666                                 max_dsc_target_bpp_limit_override,
5667                                 link_bw_in_kbps,
5668                                 &stream->timing,
5669                                 &dsc_cfg)) {
5670                 stream->timing.dsc_cfg = dsc_cfg;
5671                 stream->timing.flags.DSC = 1;
5672         }
5673 }
5674
5675
5676 static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
5677                                         struct dc_sink *sink, struct dc_stream_state *stream,
5678                                         struct dsc_dec_dpcd_caps *dsc_caps)
5679 {
5680         struct drm_connector *drm_connector = &aconnector->base;
5681         uint32_t link_bandwidth_kbps;
5682         struct dc *dc = sink->ctx->dc;
5683         uint32_t max_supported_bw_in_kbps, timing_bw_in_kbps;
5684         uint32_t dsc_max_supported_bw_in_kbps;
5685         uint32_t max_dsc_target_bpp_limit_override =
5686                 drm_connector->display_info.max_dsc_bpp;
5687
5688         link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
5689                                                         dc_link_get_link_cap(aconnector->dc_link));
5690
5691         /* Set DSC policy according to dsc_clock_en */
5692         dc_dsc_policy_set_enable_dsc_when_not_needed(
5693                 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);
5694
5695         if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP &&
5696             !aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&
5697             dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
5698
5699                 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);
5700
5701         } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
5702                 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
5703                         if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5704                                                 dsc_caps,
5705                                                 aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override,
5706                                                 max_dsc_target_bpp_limit_override,
5707                                                 link_bandwidth_kbps,
5708                                                 &stream->timing,
5709                                                 &stream->timing.dsc_cfg)) {
5710                                 stream->timing.flags.DSC = 1;
5711                                 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name);
5712                         }
5713                 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
5714                         timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
5715                         max_supported_bw_in_kbps = link_bandwidth_kbps;
5716                         dsc_max_supported_bw_in_kbps = link_bandwidth_kbps;
5717
5718                         if (timing_bw_in_kbps > max_supported_bw_in_kbps &&
5719                                         max_supported_bw_in_kbps > 0 &&
5720                                         dsc_max_supported_bw_in_kbps > 0)
5721                                 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5722                                                 dsc_caps,
5723                                                 aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override,
5724                                                 max_dsc_target_bpp_limit_override,
5725                                                 dsc_max_supported_bw_in_kbps,
5726                                                 &stream->timing,
5727                                                 &stream->timing.dsc_cfg)) {
5728                                         stream->timing.flags.DSC = 1;
5729                                         DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n",
5730                                                                          __func__, drm_connector->name);
5731                                 }
5732                 }
5733         }
5734
5735         /* Overwrite the stream flag if DSC is enabled through debugfs */
5736         if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
5737                 stream->timing.flags.DSC = 1;
5738
5739         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
5740                 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
5741
5742         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
5743                 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
5744
5745         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
5746                 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
5747 }
5748 #endif /* CONFIG_DRM_AMD_DC_DCN */
5749
5750 static struct dc_stream_state *
5751 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
5752                        const struct drm_display_mode *drm_mode,
5753                        const struct dm_connector_state *dm_state,
5754                        const struct dc_stream_state *old_stream,
5755                        int requested_bpc)
5756 {
5757         struct drm_display_mode *preferred_mode = NULL;
5758         struct drm_connector *drm_connector;
5759         const struct drm_connector_state *con_state =
5760                 dm_state ? &dm_state->base : NULL;
5761         struct dc_stream_state *stream = NULL;
5762         struct drm_display_mode mode;
5763         struct drm_display_mode saved_mode;
5764         struct drm_display_mode *freesync_mode = NULL;
5765         bool native_mode_found = false;
5766         bool recalculate_timing = false;
5767         bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
5768         int mode_refresh;
5769         int preferred_refresh = 0;
5770         enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN;
5771 #if defined(CONFIG_DRM_AMD_DC_DCN)
5772         struct dsc_dec_dpcd_caps dsc_caps;
5773 #endif
5774
5775         struct dc_sink *sink = NULL;
5776
5777         drm_mode_init(&mode, drm_mode);
5778         memset(&saved_mode, 0, sizeof(saved_mode));
5779
5780         if (aconnector == NULL) {
5781                 DRM_ERROR("aconnector is NULL!\n");
5782                 return stream;
5783         }
5784
5785         drm_connector = &aconnector->base;
5786
5787         if (!aconnector->dc_sink) {
5788                 sink = create_fake_sink(aconnector);
5789                 if (!sink)
5790                         return stream;
5791         } else {
5792                 sink = aconnector->dc_sink;
5793                 dc_sink_retain(sink);
5794         }
5795
5796         stream = dc_create_stream_for_sink(sink);
5797
5798         if (stream == NULL) {
5799                 DRM_ERROR("Failed to create stream for sink!\n");
5800                 goto finish;
5801         }
5802
5803         stream->dm_stream_context = aconnector;
5804
5805         stream->timing.flags.LTE_340MCSC_SCRAMBLE =
5806                 drm_connector->display_info.hdmi.scdc.scrambling.low_rates;
5807
5808         list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
5809                 /* Search for preferred mode */
5810                 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
5811                         native_mode_found = true;
5812                         break;
5813                 }
5814         }
5815         if (!native_mode_found)
5816                 preferred_mode = list_first_entry_or_null(
5817                                 &aconnector->base.modes,
5818                                 struct drm_display_mode,
5819                                 head);
5820
5821         mode_refresh = drm_mode_vrefresh(&mode);
5822
5823         if (preferred_mode == NULL) {
5824                 /*
5825                  * This may not be an error, the use case is when we have no
5826                  * usermode calls to reset and set mode upon hotplug. In this
5827                  * case, we call set mode ourselves to restore the previous mode
5828                  * and the modelist may not be filled in in time.
5829                  */
5830                 DRM_DEBUG_DRIVER("No preferred mode found\n");
5831         } else {
5832                 recalculate_timing = amdgpu_freesync_vid_mode &&
5833                                  is_freesync_video_mode(&mode, aconnector);
5834                 if (recalculate_timing) {
5835                         freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
5836                         drm_mode_copy(&saved_mode, &mode);
5837                         drm_mode_copy(&mode, freesync_mode);
5838                 } else {
5839                         decide_crtc_timing_for_drm_display_mode(
5840                                         &mode, preferred_mode, scale);
5841
5842                         preferred_refresh = drm_mode_vrefresh(preferred_mode);
5843                 }
5844         }
5845
5846         if (recalculate_timing)
5847                 drm_mode_set_crtcinfo(&saved_mode, 0);
5848         else if (!dm_state)
5849                 drm_mode_set_crtcinfo(&mode, 0);
5850
5851         /*
5852         * If scaling is enabled and refresh rate didn't change
5853         * we copy the vic and polarities of the old timings
5854         */
5855         if (!scale || mode_refresh != preferred_refresh)
5856                 fill_stream_properties_from_drm_display_mode(
5857                         stream, &mode, &aconnector->base, con_state, NULL,
5858                         requested_bpc);
5859         else
5860                 fill_stream_properties_from_drm_display_mode(
5861                         stream, &mode, &aconnector->base, con_state, old_stream,
5862                         requested_bpc);
5863
5864 #if defined(CONFIG_DRM_AMD_DC_DCN)
5865         /* SST DSC determination policy */
5866         update_dsc_caps(aconnector, sink, stream, &dsc_caps);
5867         if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported)
5868                 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps);
5869 #endif
5870
5871         update_stream_scaling_settings(&mode, dm_state, stream);
5872
5873         fill_audio_info(
5874                 &stream->audio_info,
5875                 drm_connector,
5876                 sink);
5877
5878         update_stream_signal(stream, sink);
5879
5880         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5881                 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);
5882
5883         if (stream->link->psr_settings.psr_feature_enabled) {
5884                 //
5885                 // should decide stream support vsc sdp colorimetry capability
5886                 // before building vsc info packet
5887                 //
5888                 stream->use_vsc_sdp_for_colorimetry = false;
5889                 if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
5890                         stream->use_vsc_sdp_for_colorimetry =
5891                                 aconnector->dc_sink->is_vsc_sdp_colorimetry_supported;
5892                 } else {
5893                         if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
5894                                 stream->use_vsc_sdp_for_colorimetry = true;
5895                 }
5896                 if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22)
5897                         tf = TRANSFER_FUNC_GAMMA_22;
5898                 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);
5899                 aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
5900
5901         }
5902 finish:
5903         dc_sink_release(sink);
5904
5905         return stream;
5906 }
5907
5908 static enum drm_connector_status
5909 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
5910 {
5911         bool connected;
5912         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5913
5914         /*
5915          * Notes:
5916          * 1. This interface is NOT called in context of HPD irq.
5917          * 2. This interface *is called* in context of user-mode ioctl. Which
5918          * makes it a bad place for *any* MST-related activity.
5919          */
5920
5921         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
5922             !aconnector->fake_enable)
5923                 connected = (aconnector->dc_sink != NULL);
5924         else
5925                 connected = (aconnector->base.force == DRM_FORCE_ON ||
5926                                 aconnector->base.force == DRM_FORCE_ON_DIGITAL);
5927
5928         update_subconnector_property(aconnector);
5929
5930         return (connected ? connector_status_connected :
5931                         connector_status_disconnected);
5932 }
5933
5934 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
5935                                             struct drm_connector_state *connector_state,
5936                                             struct drm_property *property,
5937                                             uint64_t val)
5938 {
5939         struct drm_device *dev = connector->dev;
5940         struct amdgpu_device *adev = drm_to_adev(dev);
5941         struct dm_connector_state *dm_old_state =
5942                 to_dm_connector_state(connector->state);
5943         struct dm_connector_state *dm_new_state =
5944                 to_dm_connector_state(connector_state);
5945
5946         int ret = -EINVAL;
5947
5948         if (property == dev->mode_config.scaling_mode_property) {
5949                 enum amdgpu_rmx_type rmx_type;
5950
5951                 switch (val) {
5952                 case DRM_MODE_SCALE_CENTER:
5953                         rmx_type = RMX_CENTER;
5954                         break;
5955                 case DRM_MODE_SCALE_ASPECT:
5956                         rmx_type = RMX_ASPECT;
5957                         break;
5958                 case DRM_MODE_SCALE_FULLSCREEN:
5959                         rmx_type = RMX_FULL;
5960                         break;
5961                 case DRM_MODE_SCALE_NONE:
5962                 default:
5963                         rmx_type = RMX_OFF;
5964                         break;
5965                 }
5966
5967                 if (dm_old_state->scaling == rmx_type)
5968                         return 0;
5969
5970                 dm_new_state->scaling = rmx_type;
5971                 ret = 0;
5972         } else if (property == adev->mode_info.underscan_hborder_property) {
5973                 dm_new_state->underscan_hborder = val;
5974                 ret = 0;
5975         } else if (property == adev->mode_info.underscan_vborder_property) {
5976                 dm_new_state->underscan_vborder = val;
5977                 ret = 0;
5978         } else if (property == adev->mode_info.underscan_property) {
5979                 dm_new_state->underscan_enable = val;
5980                 ret = 0;
5981         } else if (property == adev->mode_info.abm_level_property) {
5982                 dm_new_state->abm_level = val;
5983                 ret = 0;
5984         }
5985
5986         return ret;
5987 }
5988
5989 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
5990                                             const struct drm_connector_state *state,
5991                                             struct drm_property *property,
5992                                             uint64_t *val)
5993 {
5994         struct drm_device *dev = connector->dev;
5995         struct amdgpu_device *adev = drm_to_adev(dev);
5996         struct dm_connector_state *dm_state =
5997                 to_dm_connector_state(state);
5998         int ret = -EINVAL;
5999
6000         if (property == dev->mode_config.scaling_mode_property) {
6001                 switch (dm_state->scaling) {
6002                 case RMX_CENTER:
6003                         *val = DRM_MODE_SCALE_CENTER;
6004                         break;
6005                 case RMX_ASPECT:
6006                         *val = DRM_MODE_SCALE_ASPECT;
6007                         break;
6008                 case RMX_FULL:
6009                         *val = DRM_MODE_SCALE_FULLSCREEN;
6010                         break;
6011                 case RMX_OFF:
6012                 default:
6013                         *val = DRM_MODE_SCALE_NONE;
6014                         break;
6015                 }
6016                 ret = 0;
6017         } else if (property == adev->mode_info.underscan_hborder_property) {
6018                 *val = dm_state->underscan_hborder;
6019                 ret = 0;
6020         } else if (property == adev->mode_info.underscan_vborder_property) {
6021                 *val = dm_state->underscan_vborder;
6022                 ret = 0;
6023         } else if (property == adev->mode_info.underscan_property) {
6024                 *val = dm_state->underscan_enable;
6025                 ret = 0;
6026         } else if (property == adev->mode_info.abm_level_property) {
6027                 *val = dm_state->abm_level;
6028                 ret = 0;
6029         }
6030
6031         return ret;
6032 }
6033
6034 static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
6035 {
6036         struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
6037
6038         drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
6039 }
6040
6041 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
6042 {
6043         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6044         const struct dc_link *link = aconnector->dc_link;
6045         struct amdgpu_device *adev = drm_to_adev(connector->dev);
6046         struct amdgpu_display_manager *dm = &adev->dm;
6047         int i;
6048
6049         /*
6050          * Call only if mst_mgr was initialized before since it's not done
6051          * for all connector types.
6052          */
6053         if (aconnector->mst_mgr.dev)
6054                 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);
6055
6056 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
6057         defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
6058         for (i = 0; i < dm->num_of_edps; i++) {
6059                 if ((link == dm->backlight_link[i]) && dm->backlight_dev[i]) {
6060                         backlight_device_unregister(dm->backlight_dev[i]);
6061                         dm->backlight_dev[i] = NULL;
6062                 }
6063         }
6064 #endif
6065
6066         if (aconnector->dc_em_sink)
6067                 dc_sink_release(aconnector->dc_em_sink);
6068         aconnector->dc_em_sink = NULL;
6069         if (aconnector->dc_sink)
6070                 dc_sink_release(aconnector->dc_sink);
6071         aconnector->dc_sink = NULL;
6072
6073         drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
6074         drm_connector_unregister(connector);
6075         drm_connector_cleanup(connector);
6076         if (aconnector->i2c) {
6077                 i2c_del_adapter(&aconnector->i2c->base);
6078                 kfree(aconnector->i2c);
6079         }
6080         kfree(aconnector->dm_dp_aux.aux.name);
6081
6082         kfree(connector);
6083 }
6084
6085 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
6086 {
6087         struct dm_connector_state *state =
6088                 to_dm_connector_state(connector->state);
6089
6090         if (connector->state)
6091                 __drm_atomic_helper_connector_destroy_state(connector->state);
6092
6093         kfree(state);
6094
6095         state = kzalloc(sizeof(*state), GFP_KERNEL);
6096
6097         if (state) {
6098                 state->scaling = RMX_OFF;
6099                 state->underscan_enable = false;
6100                 state->underscan_hborder = 0;
6101                 state->underscan_vborder = 0;
6102                 state->base.max_requested_bpc = 8;
6103                 state->vcpi_slots = 0;
6104                 state->pbn = 0;
6105
6106                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
6107                         state->abm_level = amdgpu_dm_abm_level;
6108
6109                 __drm_atomic_helper_connector_reset(connector, &state->base);
6110         }
6111 }
6112
6113 struct drm_connector_state *
6114 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
6115 {
6116         struct dm_connector_state *state =
6117                 to_dm_connector_state(connector->state);
6118
6119         struct dm_connector_state *new_state =
6120                         kmemdup(state, sizeof(*state), GFP_KERNEL);
6121
6122         if (!new_state)
6123                 return NULL;
6124
6125         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
6126
6127         new_state->freesync_capable = state->freesync_capable;
6128         new_state->abm_level = state->abm_level;
6129         new_state->scaling = state->scaling;
6130         new_state->underscan_enable = state->underscan_enable;
6131         new_state->underscan_hborder = state->underscan_hborder;
6132         new_state->underscan_vborder = state->underscan_vborder;
6133         new_state->vcpi_slots = state->vcpi_slots;
6134         new_state->pbn = state->pbn;
6135         return &new_state->base;
6136 }
6137
6138 static int
6139 amdgpu_dm_connector_late_register(struct drm_connector *connector)
6140 {
6141         struct amdgpu_dm_connector *amdgpu_dm_connector =
6142                 to_amdgpu_dm_connector(connector);
6143         int r;
6144
6145         if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
6146             (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
6147                 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
6148                 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
6149                 if (r)
6150                         return r;
6151         }
6152
6153 #if defined(CONFIG_DEBUG_FS)
6154         connector_debugfs_init(amdgpu_dm_connector);
6155 #endif
6156
6157         return 0;
6158 }
6159
6160 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
6161         .reset = amdgpu_dm_connector_funcs_reset,
6162         .detect = amdgpu_dm_connector_detect,
6163         .fill_modes = drm_helper_probe_single_connector_modes,
6164         .destroy = amdgpu_dm_connector_destroy,
6165         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
6166         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6167         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
6168         .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
6169         .late_register = amdgpu_dm_connector_late_register,
6170         .early_unregister = amdgpu_dm_connector_unregister
6171 };
6172
6173 static int get_modes(struct drm_connector *connector)
6174 {
6175         return amdgpu_dm_connector_get_modes(connector);
6176 }
6177
6178 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
6179 {
6180         struct dc_sink_init_data init_params = {
6181                         .link = aconnector->dc_link,
6182                         .sink_signal = SIGNAL_TYPE_VIRTUAL
6183         };
6184         struct edid *edid;
6185
6186         if (!aconnector->base.edid_blob_ptr) {
6187                 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
6188                                 aconnector->base.name);
6189
6190                 aconnector->base.force = DRM_FORCE_OFF;
6191                 return;
6192         }
6193
6194         edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
6195
6196         aconnector->edid = edid;
6197
6198         aconnector->dc_em_sink = dc_link_add_remote_sink(
6199                 aconnector->dc_link,
6200                 (uint8_t *)edid,
6201                 (edid->extensions + 1) * EDID_LENGTH,
6202                 &init_params);
6203
6204         if (aconnector->base.force == DRM_FORCE_ON) {
6205                 aconnector->dc_sink = aconnector->dc_link->local_sink ?
6206                 aconnector->dc_link->local_sink :
6207                 aconnector->dc_em_sink;
6208                 dc_sink_retain(aconnector->dc_sink);
6209         }
6210 }
6211
6212 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
6213 {
6214         struct dc_link *link = (struct dc_link *)aconnector->dc_link;
6215
6216         /*
6217          * In case of headless boot with force on for DP managed connector
6218          * Those settings have to be != 0 to get initial modeset
6219          */
6220         if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
6221                 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
6222                 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
6223         }
6224
6225         create_eml_sink(aconnector);
6226 }
6227
6228 static enum dc_status dm_validate_stream_and_context(struct dc *dc,
6229                                                 struct dc_stream_state *stream)
6230 {
6231         enum dc_status dc_result = DC_ERROR_UNEXPECTED;
6232         struct dc_plane_state *dc_plane_state = NULL;
6233         struct dc_state *dc_state = NULL;
6234
6235         if (!stream)
6236                 goto cleanup;
6237
6238         dc_plane_state = dc_create_plane_state(dc);
6239         if (!dc_plane_state)
6240                 goto cleanup;
6241
6242         dc_state = dc_create_state(dc);
6243         if (!dc_state)
6244                 goto cleanup;
6245
6246         /* populate stream to plane */
6247         dc_plane_state->src_rect.height  = stream->src.height;
6248         dc_plane_state->src_rect.width   = stream->src.width;
6249         dc_plane_state->dst_rect.height  = stream->src.height;
6250         dc_plane_state->dst_rect.width   = stream->src.width;
6251         dc_plane_state->clip_rect.height = stream->src.height;
6252         dc_plane_state->clip_rect.width  = stream->src.width;
6253         dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256;
6254         dc_plane_state->plane_size.surface_size.height = stream->src.height;
6255         dc_plane_state->plane_size.surface_size.width  = stream->src.width;
6256         dc_plane_state->plane_size.chroma_size.height  = stream->src.height;
6257         dc_plane_state->plane_size.chroma_size.width   = stream->src.width;
6258         dc_plane_state->tiling_info.gfx9.swizzle =  DC_SW_UNKNOWN;
6259         dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
6260         dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN;
6261         dc_plane_state->rotation = ROTATION_ANGLE_0;
6262         dc_plane_state->is_tiling_rotated = false;
6263         dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL;
6264
6265         dc_result = dc_validate_stream(dc, stream);
6266         if (dc_result == DC_OK)
6267                 dc_result = dc_validate_plane(dc, dc_plane_state);
6268
6269         if (dc_result == DC_OK)
6270                 dc_result = dc_add_stream_to_ctx(dc, dc_state, stream);
6271
6272         if (dc_result == DC_OK && !dc_add_plane_to_context(
6273                                                 dc,
6274                                                 stream,
6275                                                 dc_plane_state,
6276                                                 dc_state))
6277                 dc_result = DC_FAIL_ATTACH_SURFACES;
6278
6279         if (dc_result == DC_OK)
6280                 dc_result = dc_validate_global_state(dc, dc_state, true);
6281
6282 cleanup:
6283         if (dc_state)
6284                 dc_release_state(dc_state);
6285
6286         if (dc_plane_state)
6287                 dc_plane_state_release(dc_plane_state);
6288
6289         return dc_result;
6290 }
6291
6292 struct dc_stream_state *
6293 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6294                                 const struct drm_display_mode *drm_mode,
6295                                 const struct dm_connector_state *dm_state,
6296                                 const struct dc_stream_state *old_stream)
6297 {
6298         struct drm_connector *connector = &aconnector->base;
6299         struct amdgpu_device *adev = drm_to_adev(connector->dev);
6300         struct dc_stream_state *stream;
6301         const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL;
6302         int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8;
6303         enum dc_status dc_result = DC_OK;
6304
6305         do {
6306                 stream = create_stream_for_sink(aconnector, drm_mode,
6307                                                 dm_state, old_stream,
6308                                                 requested_bpc);
6309                 if (stream == NULL) {
6310                         DRM_ERROR("Failed to create stream for sink!\n");
6311                         break;
6312                 }
6313
6314                 dc_result = dc_validate_stream(adev->dm.dc, stream);
6315                 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
6316                         dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream);
6317
6318                 if (dc_result == DC_OK)
6319                         dc_result = dm_validate_stream_and_context(adev->dm.dc, stream);
6320
6321                 if (dc_result != DC_OK) {
6322                         DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",
6323                                       drm_mode->hdisplay,
6324                                       drm_mode->vdisplay,
6325                                       drm_mode->clock,
6326                                       dc_result,
6327                                       dc_status_to_str(dc_result));
6328
6329                         dc_stream_release(stream);
6330                         stream = NULL;
6331                         requested_bpc -= 2; /* lower bpc to retry validation */
6332                 }
6333
6334         } while (stream == NULL && requested_bpc >= 6);
6335
6336         if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) {
6337                 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n");
6338
6339                 aconnector->force_yuv420_output = true;
6340                 stream = create_validate_stream_for_sink(aconnector, drm_mode,
6341                                                 dm_state, old_stream);
6342                 aconnector->force_yuv420_output = false;
6343         }
6344
6345         return stream;
6346 }
6347
6348 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
6349                                    struct drm_display_mode *mode)
6350 {
6351         int result = MODE_ERROR;
6352         struct dc_sink *dc_sink;
6353         /* TODO: Unhardcode stream count */
6354         struct dc_stream_state *stream;
6355         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6356
6357         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
6358                         (mode->flags & DRM_MODE_FLAG_DBLSCAN))
6359                 return result;
6360
6361         /*
6362          * Only run this the first time mode_valid is called to initilialize
6363          * EDID mgmt
6364          */
6365         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
6366                 !aconnector->dc_em_sink)
6367                 handle_edid_mgmt(aconnector);
6368
6369         dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
6370
6371         if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL &&
6372                                 aconnector->base.force != DRM_FORCE_ON) {
6373                 DRM_ERROR("dc_sink is NULL!\n");
6374                 goto fail;
6375         }
6376
6377         stream = create_validate_stream_for_sink(aconnector, mode, NULL, NULL);
6378         if (stream) {
6379                 dc_stream_release(stream);
6380                 result = MODE_OK;
6381         }
6382
6383 fail:
6384         /* TODO: error handling*/
6385         return result;
6386 }
6387
6388 static int fill_hdr_info_packet(const struct drm_connector_state *state,
6389                                 struct dc_info_packet *out)
6390 {
6391         struct hdmi_drm_infoframe frame;
6392         unsigned char buf[30]; /* 26 + 4 */
6393         ssize_t len;
6394         int ret, i;
6395
6396         memset(out, 0, sizeof(*out));
6397
6398         if (!state->hdr_output_metadata)
6399                 return 0;
6400
6401         ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
6402         if (ret)
6403                 return ret;
6404
6405         len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
6406         if (len < 0)
6407                 return (int)len;
6408
6409         /* Static metadata is a fixed 26 bytes + 4 byte header. */
6410         if (len != 30)
6411                 return -EINVAL;
6412
6413         /* Prepare the infopacket for DC. */
6414         switch (state->connector->connector_type) {
6415         case DRM_MODE_CONNECTOR_HDMIA:
6416                 out->hb0 = 0x87; /* type */
6417                 out->hb1 = 0x01; /* version */
6418                 out->hb2 = 0x1A; /* length */
6419                 out->sb[0] = buf[3]; /* checksum */
6420                 i = 1;
6421                 break;
6422
6423         case DRM_MODE_CONNECTOR_DisplayPort:
6424         case DRM_MODE_CONNECTOR_eDP:
6425                 out->hb0 = 0x00; /* sdp id, zero */
6426                 out->hb1 = 0x87; /* type */
6427                 out->hb2 = 0x1D; /* payload len - 1 */
6428                 out->hb3 = (0x13 << 2); /* sdp version */
6429                 out->sb[0] = 0x01; /* version */
6430                 out->sb[1] = 0x1A; /* length */
6431                 i = 2;
6432                 break;
6433
6434         default:
6435                 return -EINVAL;
6436         }
6437
6438         memcpy(&out->sb[i], &buf[4], 26);
6439         out->valid = true;
6440
6441         print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
6442                        sizeof(out->sb), false);
6443
6444         return 0;
6445 }
6446
6447 static int
6448 amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
6449                                  struct drm_atomic_state *state)
6450 {
6451         struct drm_connector_state *new_con_state =
6452                 drm_atomic_get_new_connector_state(state, conn);
6453         struct drm_connector_state *old_con_state =
6454                 drm_atomic_get_old_connector_state(state, conn);
6455         struct drm_crtc *crtc = new_con_state->crtc;
6456         struct drm_crtc_state *new_crtc_state;
6457         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn);
6458         int ret;
6459
6460         trace_amdgpu_dm_connector_atomic_check(new_con_state);
6461
6462         if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
6463                 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr);
6464                 if (ret < 0)
6465                         return ret;
6466         }
6467
6468         if (!crtc)
6469                 return 0;
6470
6471         if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) {
6472                 struct dc_info_packet hdr_infopacket;
6473
6474                 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
6475                 if (ret)
6476                         return ret;
6477
6478                 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6479                 if (IS_ERR(new_crtc_state))
6480                         return PTR_ERR(new_crtc_state);
6481
6482                 /*
6483                  * DC considers the stream backends changed if the
6484                  * static metadata changes. Forcing the modeset also
6485                  * gives a simple way for userspace to switch from
6486                  * 8bpc to 10bpc when setting the metadata to enter
6487                  * or exit HDR.
6488                  *
6489                  * Changing the static metadata after it's been
6490                  * set is permissible, however. So only force a
6491                  * modeset if we're entering or exiting HDR.
6492                  */
6493                 new_crtc_state->mode_changed =
6494                         !old_con_state->hdr_output_metadata ||
6495                         !new_con_state->hdr_output_metadata;
6496         }
6497
6498         return 0;
6499 }
6500
6501 static const struct drm_connector_helper_funcs
6502 amdgpu_dm_connector_helper_funcs = {
6503         /*
6504          * If hotplugging a second bigger display in FB Con mode, bigger resolution
6505          * modes will be filtered by drm_mode_validate_size(), and those modes
6506          * are missing after user start lightdm. So we need to renew modes list.
6507          * in get_modes call back, not just return the modes count
6508          */
6509         .get_modes = get_modes,
6510         .mode_valid = amdgpu_dm_connector_mode_valid,
6511         .atomic_check = amdgpu_dm_connector_atomic_check,
6512 };
6513
6514 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
6515 {
6516
6517 }
6518
6519 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth)
6520 {
6521         switch (display_color_depth) {
6522         case COLOR_DEPTH_666:
6523                 return 6;
6524         case COLOR_DEPTH_888:
6525                 return 8;
6526         case COLOR_DEPTH_101010:
6527                 return 10;
6528         case COLOR_DEPTH_121212:
6529                 return 12;
6530         case COLOR_DEPTH_141414:
6531                 return 14;
6532         case COLOR_DEPTH_161616:
6533                 return 16;
6534         default:
6535                 break;
6536         }
6537         return 0;
6538 }
6539
6540 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
6541                                           struct drm_crtc_state *crtc_state,
6542                                           struct drm_connector_state *conn_state)
6543 {
6544         struct drm_atomic_state *state = crtc_state->state;
6545         struct drm_connector *connector = conn_state->connector;
6546         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6547         struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state);
6548         const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
6549         struct drm_dp_mst_topology_mgr *mst_mgr;
6550         struct drm_dp_mst_port *mst_port;
6551         struct drm_dp_mst_topology_state *mst_state;
6552         enum dc_color_depth color_depth;
6553         int clock, bpp = 0;
6554         bool is_y420 = false;
6555
6556         if (!aconnector->port || !aconnector->dc_sink)
6557                 return 0;
6558
6559         mst_port = aconnector->port;
6560         mst_mgr = &aconnector->mst_port->mst_mgr;
6561
6562         if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
6563                 return 0;
6564
6565         mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr);
6566         if (IS_ERR(mst_state))
6567                 return PTR_ERR(mst_state);
6568
6569         if (!mst_state->pbn_div)
6570                 mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_port->dc_link);
6571
6572         if (!state->duplicated) {
6573                 int max_bpc = conn_state->max_requested_bpc;
6574                 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
6575                           aconnector->force_yuv420_output;
6576                 color_depth = convert_color_depth_from_display_info(connector,
6577                                                                     is_y420,
6578                                                                     max_bpc);
6579                 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
6580                 clock = adjusted_mode->clock;
6581                 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
6582         }
6583
6584         dm_new_connector_state->vcpi_slots =
6585                 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port,
6586                                               dm_new_connector_state->pbn);
6587         if (dm_new_connector_state->vcpi_slots < 0) {
6588                 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
6589                 return dm_new_connector_state->vcpi_slots;
6590         }
6591         return 0;
6592 }
6593
6594 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
6595         .disable = dm_encoder_helper_disable,
6596         .atomic_check = dm_encoder_helper_atomic_check
6597 };
6598
6599 #if defined(CONFIG_DRM_AMD_DC_DCN)
6600 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
6601                                             struct dc_state *dc_state,
6602                                             struct dsc_mst_fairness_vars *vars)
6603 {
6604         struct dc_stream_state *stream = NULL;
6605         struct drm_connector *connector;
6606         struct drm_connector_state *new_con_state;
6607         struct amdgpu_dm_connector *aconnector;
6608         struct dm_connector_state *dm_conn_state;
6609         int i, j, ret;
6610         int vcpi, pbn_div, pbn, slot_num = 0;
6611
6612         for_each_new_connector_in_state(state, connector, new_con_state, i) {
6613
6614                 aconnector = to_amdgpu_dm_connector(connector);
6615
6616                 if (!aconnector->port)
6617                         continue;
6618
6619                 if (!new_con_state || !new_con_state->crtc)
6620                         continue;
6621
6622                 dm_conn_state = to_dm_connector_state(new_con_state);
6623
6624                 for (j = 0; j < dc_state->stream_count; j++) {
6625                         stream = dc_state->streams[j];
6626                         if (!stream)
6627                                 continue;
6628
6629                         if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector)
6630                                 break;
6631
6632                         stream = NULL;
6633                 }
6634
6635                 if (!stream)
6636                         continue;
6637
6638                 pbn_div = dm_mst_get_pbn_divider(stream->link);
6639                 /* pbn is calculated by compute_mst_dsc_configs_for_state*/
6640                 for (j = 0; j < dc_state->stream_count; j++) {
6641                         if (vars[j].aconnector == aconnector) {
6642                                 pbn = vars[j].pbn;
6643                                 break;
6644                         }
6645                 }
6646
6647                 if (j == dc_state->stream_count)
6648                         continue;
6649
6650                 slot_num = DIV_ROUND_UP(pbn, pbn_div);
6651
6652                 if (stream->timing.flags.DSC != 1) {
6653                         dm_conn_state->pbn = pbn;
6654                         dm_conn_state->vcpi_slots = slot_num;
6655
6656                         ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->port,
6657                                                            dm_conn_state->pbn, false);
6658                         if (ret < 0)
6659                                 return ret;
6660
6661                         continue;
6662                 }
6663
6664                 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->port, pbn, true);
6665                 if (vcpi < 0)
6666                         return vcpi;
6667
6668                 dm_conn_state->pbn = pbn;
6669                 dm_conn_state->vcpi_slots = vcpi;
6670         }
6671         return 0;
6672 }
6673 #endif
6674
6675 static int to_drm_connector_type(enum signal_type st)
6676 {
6677         switch (st) {
6678         case SIGNAL_TYPE_HDMI_TYPE_A:
6679                 return DRM_MODE_CONNECTOR_HDMIA;
6680         case SIGNAL_TYPE_EDP:
6681                 return DRM_MODE_CONNECTOR_eDP;
6682         case SIGNAL_TYPE_LVDS:
6683                 return DRM_MODE_CONNECTOR_LVDS;
6684         case SIGNAL_TYPE_RGB:
6685                 return DRM_MODE_CONNECTOR_VGA;
6686         case SIGNAL_TYPE_DISPLAY_PORT:
6687         case SIGNAL_TYPE_DISPLAY_PORT_MST:
6688                 return DRM_MODE_CONNECTOR_DisplayPort;
6689         case SIGNAL_TYPE_DVI_DUAL_LINK:
6690         case SIGNAL_TYPE_DVI_SINGLE_LINK:
6691                 return DRM_MODE_CONNECTOR_DVID;
6692         case SIGNAL_TYPE_VIRTUAL:
6693                 return DRM_MODE_CONNECTOR_VIRTUAL;
6694
6695         default:
6696                 return DRM_MODE_CONNECTOR_Unknown;
6697         }
6698 }
6699
6700 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
6701 {
6702         struct drm_encoder *encoder;
6703
6704         /* There is only one encoder per connector */
6705         drm_connector_for_each_possible_encoder(connector, encoder)
6706                 return encoder;
6707
6708         return NULL;
6709 }
6710
6711 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
6712 {
6713         struct drm_encoder *encoder;
6714         struct amdgpu_encoder *amdgpu_encoder;
6715
6716         encoder = amdgpu_dm_connector_to_encoder(connector);
6717
6718         if (encoder == NULL)
6719                 return;
6720
6721         amdgpu_encoder = to_amdgpu_encoder(encoder);
6722
6723         amdgpu_encoder->native_mode.clock = 0;
6724
6725         if (!list_empty(&connector->probed_modes)) {
6726                 struct drm_display_mode *preferred_mode = NULL;
6727
6728                 list_for_each_entry(preferred_mode,
6729                                     &connector->probed_modes,
6730                                     head) {
6731                         if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
6732                                 amdgpu_encoder->native_mode = *preferred_mode;
6733
6734                         break;
6735                 }
6736
6737         }
6738 }
6739
6740 static struct drm_display_mode *
6741 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
6742                              char *name,
6743                              int hdisplay, int vdisplay)
6744 {
6745         struct drm_device *dev = encoder->dev;
6746         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
6747         struct drm_display_mode *mode = NULL;
6748         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
6749
6750         mode = drm_mode_duplicate(dev, native_mode);
6751
6752         if (mode == NULL)
6753                 return NULL;
6754
6755         mode->hdisplay = hdisplay;
6756         mode->vdisplay = vdisplay;
6757         mode->type &= ~DRM_MODE_TYPE_PREFERRED;
6758         strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
6759
6760         return mode;
6761
6762 }
6763
6764 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
6765                                                  struct drm_connector *connector)
6766 {
6767         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
6768         struct drm_display_mode *mode = NULL;
6769         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
6770         struct amdgpu_dm_connector *amdgpu_dm_connector =
6771                                 to_amdgpu_dm_connector(connector);
6772         int i;
6773         int n;
6774         struct mode_size {
6775                 char name[DRM_DISPLAY_MODE_LEN];
6776                 int w;
6777                 int h;
6778         } common_modes[] = {
6779                 {  "640x480",  640,  480},
6780                 {  "800x600",  800,  600},
6781                 { "1024x768", 1024,  768},
6782                 { "1280x720", 1280,  720},
6783                 { "1280x800", 1280,  800},
6784                 {"1280x1024", 1280, 1024},
6785                 { "1440x900", 1440,  900},
6786                 {"1680x1050", 1680, 1050},
6787                 {"1600x1200", 1600, 1200},
6788                 {"1920x1080", 1920, 1080},
6789                 {"1920x1200", 1920, 1200}
6790         };
6791
6792         n = ARRAY_SIZE(common_modes);
6793
6794         for (i = 0; i < n; i++) {
6795                 struct drm_display_mode *curmode = NULL;
6796                 bool mode_existed = false;
6797
6798                 if (common_modes[i].w > native_mode->hdisplay ||
6799                     common_modes[i].h > native_mode->vdisplay ||
6800                    (common_modes[i].w == native_mode->hdisplay &&
6801                     common_modes[i].h == native_mode->vdisplay))
6802                         continue;
6803
6804                 list_for_each_entry(curmode, &connector->probed_modes, head) {
6805                         if (common_modes[i].w == curmode->hdisplay &&
6806                             common_modes[i].h == curmode->vdisplay) {
6807                                 mode_existed = true;
6808                                 break;
6809                         }
6810                 }
6811
6812                 if (mode_existed)
6813                         continue;
6814
6815                 mode = amdgpu_dm_create_common_mode(encoder,
6816                                 common_modes[i].name, common_modes[i].w,
6817                                 common_modes[i].h);
6818                 if (!mode)
6819                         continue;
6820
6821                 drm_mode_probed_add(connector, mode);
6822                 amdgpu_dm_connector->num_modes++;
6823         }
6824 }
6825
6826 static void amdgpu_set_panel_orientation(struct drm_connector *connector)
6827 {
6828         struct drm_encoder *encoder;
6829         struct amdgpu_encoder *amdgpu_encoder;
6830         const struct drm_display_mode *native_mode;
6831
6832         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
6833             connector->connector_type != DRM_MODE_CONNECTOR_LVDS)
6834                 return;
6835
6836         mutex_lock(&connector->dev->mode_config.mutex);
6837         amdgpu_dm_connector_get_modes(connector);
6838         mutex_unlock(&connector->dev->mode_config.mutex);
6839
6840         encoder = amdgpu_dm_connector_to_encoder(connector);
6841         if (!encoder)
6842                 return;
6843
6844         amdgpu_encoder = to_amdgpu_encoder(encoder);
6845
6846         native_mode = &amdgpu_encoder->native_mode;
6847         if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0)
6848                 return;
6849
6850         drm_connector_set_panel_orientation_with_quirk(connector,
6851                                                        DRM_MODE_PANEL_ORIENTATION_UNKNOWN,
6852                                                        native_mode->hdisplay,
6853                                                        native_mode->vdisplay);
6854 }
6855
6856 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
6857                                               struct edid *edid)
6858 {
6859         struct amdgpu_dm_connector *amdgpu_dm_connector =
6860                         to_amdgpu_dm_connector(connector);
6861
6862         if (edid) {
6863                 /* empty probed_modes */
6864                 INIT_LIST_HEAD(&connector->probed_modes);
6865                 amdgpu_dm_connector->num_modes =
6866                                 drm_add_edid_modes(connector, edid);
6867
6868                 /* sorting the probed modes before calling function
6869                  * amdgpu_dm_get_native_mode() since EDID can have
6870                  * more than one preferred mode. The modes that are
6871                  * later in the probed mode list could be of higher
6872                  * and preferred resolution. For example, 3840x2160
6873                  * resolution in base EDID preferred timing and 4096x2160
6874                  * preferred resolution in DID extension block later.
6875                  */
6876                 drm_mode_sort(&connector->probed_modes);
6877                 amdgpu_dm_get_native_mode(connector);
6878
6879                 /* Freesync capabilities are reset by calling
6880                  * drm_add_edid_modes() and need to be
6881                  * restored here.
6882                  */
6883                 amdgpu_dm_update_freesync_caps(connector, edid);
6884         } else {
6885                 amdgpu_dm_connector->num_modes = 0;
6886         }
6887 }
6888
6889 static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector,
6890                               struct drm_display_mode *mode)
6891 {
6892         struct drm_display_mode *m;
6893
6894         list_for_each_entry (m, &aconnector->base.probed_modes, head) {
6895                 if (drm_mode_equal(m, mode))
6896                         return true;
6897         }
6898
6899         return false;
6900 }
6901
6902 static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)
6903 {
6904         const struct drm_display_mode *m;
6905         struct drm_display_mode *new_mode;
6906         uint i;
6907         uint32_t new_modes_count = 0;
6908
6909         /* Standard FPS values
6910          *
6911          * 23.976       - TV/NTSC
6912          * 24           - Cinema
6913          * 25           - TV/PAL
6914          * 29.97        - TV/NTSC
6915          * 30           - TV/NTSC
6916          * 48           - Cinema HFR
6917          * 50           - TV/PAL
6918          * 60           - Commonly used
6919          * 48,72,96,120 - Multiples of 24
6920          */
6921         static const uint32_t common_rates[] = {
6922                 23976, 24000, 25000, 29970, 30000,
6923                 48000, 50000, 60000, 72000, 96000, 120000
6924         };
6925
6926         /*
6927          * Find mode with highest refresh rate with the same resolution
6928          * as the preferred mode. Some monitors report a preferred mode
6929          * with lower resolution than the highest refresh rate supported.
6930          */
6931
6932         m = get_highest_refresh_rate_mode(aconnector, true);
6933         if (!m)
6934                 return 0;
6935
6936         for (i = 0; i < ARRAY_SIZE(common_rates); i++) {
6937                 uint64_t target_vtotal, target_vtotal_diff;
6938                 uint64_t num, den;
6939
6940                 if (drm_mode_vrefresh(m) * 1000 < common_rates[i])
6941                         continue;
6942
6943                 if (common_rates[i] < aconnector->min_vfreq * 1000 ||
6944                     common_rates[i] > aconnector->max_vfreq * 1000)
6945                         continue;
6946
6947                 num = (unsigned long long)m->clock * 1000 * 1000;
6948                 den = common_rates[i] * (unsigned long long)m->htotal;
6949                 target_vtotal = div_u64(num, den);
6950                 target_vtotal_diff = target_vtotal - m->vtotal;
6951
6952                 /* Check for illegal modes */
6953                 if (m->vsync_start + target_vtotal_diff < m->vdisplay ||
6954                     m->vsync_end + target_vtotal_diff < m->vsync_start ||
6955                     m->vtotal + target_vtotal_diff < m->vsync_end)
6956                         continue;
6957
6958                 new_mode = drm_mode_duplicate(aconnector->base.dev, m);
6959                 if (!new_mode)
6960                         goto out;
6961
6962                 new_mode->vtotal += (u16)target_vtotal_diff;
6963                 new_mode->vsync_start += (u16)target_vtotal_diff;
6964                 new_mode->vsync_end += (u16)target_vtotal_diff;
6965                 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
6966                 new_mode->type |= DRM_MODE_TYPE_DRIVER;
6967
6968                 if (!is_duplicate_mode(aconnector, new_mode)) {
6969                         drm_mode_probed_add(&aconnector->base, new_mode);
6970                         new_modes_count += 1;
6971                 } else
6972                         drm_mode_destroy(aconnector->base.dev, new_mode);
6973         }
6974  out:
6975         return new_modes_count;
6976 }
6977
6978 static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector,
6979                                                    struct edid *edid)
6980 {
6981         struct amdgpu_dm_connector *amdgpu_dm_connector =
6982                 to_amdgpu_dm_connector(connector);
6983
6984         if (!(amdgpu_freesync_vid_mode && edid))
6985                 return;
6986
6987         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
6988                 amdgpu_dm_connector->num_modes +=
6989                         add_fs_modes(amdgpu_dm_connector);
6990 }
6991
6992 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
6993 {
6994         struct amdgpu_dm_connector *amdgpu_dm_connector =
6995                         to_amdgpu_dm_connector(connector);
6996         struct drm_encoder *encoder;
6997         struct edid *edid = amdgpu_dm_connector->edid;
6998
6999         encoder = amdgpu_dm_connector_to_encoder(connector);
7000
7001         if (!drm_edid_is_valid(edid)) {
7002                 amdgpu_dm_connector->num_modes =
7003                                 drm_add_modes_noedid(connector, 640, 480);
7004         } else {
7005                 amdgpu_dm_connector_ddc_get_modes(connector, edid);
7006                 amdgpu_dm_connector_add_common_modes(encoder, connector);
7007                 amdgpu_dm_connector_add_freesync_modes(connector, edid);
7008         }
7009         amdgpu_dm_fbc_init(connector);
7010
7011         return amdgpu_dm_connector->num_modes;
7012 }
7013
7014 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
7015                                      struct amdgpu_dm_connector *aconnector,
7016                                      int connector_type,
7017                                      struct dc_link *link,
7018                                      int link_index)
7019 {
7020         struct amdgpu_device *adev = drm_to_adev(dm->ddev);
7021
7022         /*
7023          * Some of the properties below require access to state, like bpc.
7024          * Allocate some default initial connector state with our reset helper.
7025          */
7026         if (aconnector->base.funcs->reset)
7027                 aconnector->base.funcs->reset(&aconnector->base);
7028
7029         aconnector->connector_id = link_index;
7030         aconnector->dc_link = link;
7031         aconnector->base.interlace_allowed = false;
7032         aconnector->base.doublescan_allowed = false;
7033         aconnector->base.stereo_allowed = false;
7034         aconnector->base.dpms = DRM_MODE_DPMS_OFF;
7035         aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
7036         aconnector->audio_inst = -1;
7037         mutex_init(&aconnector->hpd_lock);
7038
7039         /*
7040          * configure support HPD hot plug connector_>polled default value is 0
7041          * which means HPD hot plug not supported
7042          */
7043         switch (connector_type) {
7044         case DRM_MODE_CONNECTOR_HDMIA:
7045                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7046                 aconnector->base.ycbcr_420_allowed =
7047                         link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
7048                 break;
7049         case DRM_MODE_CONNECTOR_DisplayPort:
7050                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7051                 link->link_enc = link_enc_cfg_get_link_enc(link);
7052                 ASSERT(link->link_enc);
7053                 if (link->link_enc)
7054                         aconnector->base.ycbcr_420_allowed =
7055                         link->link_enc->features.dp_ycbcr420_supported ? true : false;
7056                 break;
7057         case DRM_MODE_CONNECTOR_DVID:
7058                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7059                 break;
7060         default:
7061                 break;
7062         }
7063
7064         drm_object_attach_property(&aconnector->base.base,
7065                                 dm->ddev->mode_config.scaling_mode_property,
7066                                 DRM_MODE_SCALE_NONE);
7067
7068         drm_object_attach_property(&aconnector->base.base,
7069                                 adev->mode_info.underscan_property,
7070                                 UNDERSCAN_OFF);
7071         drm_object_attach_property(&aconnector->base.base,
7072                                 adev->mode_info.underscan_hborder_property,
7073                                 0);
7074         drm_object_attach_property(&aconnector->base.base,
7075                                 adev->mode_info.underscan_vborder_property,
7076                                 0);
7077
7078         if (!aconnector->mst_port)
7079                 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
7080
7081         /* This defaults to the max in the range, but we want 8bpc for non-edp. */
7082         aconnector->base.state->max_bpc = (connector_type == DRM_MODE_CONNECTOR_eDP) ? 16 : 8;
7083         aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
7084
7085         if (connector_type == DRM_MODE_CONNECTOR_eDP &&
7086             (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) {
7087                 drm_object_attach_property(&aconnector->base.base,
7088                                 adev->mode_info.abm_level_property, 0);
7089         }
7090
7091         if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
7092             connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
7093             connector_type == DRM_MODE_CONNECTOR_eDP) {
7094                 drm_connector_attach_hdr_output_metadata_property(&aconnector->base);
7095
7096                 if (!aconnector->mst_port)
7097                         drm_connector_attach_vrr_capable_property(&aconnector->base);
7098
7099 #ifdef CONFIG_DRM_AMD_DC_HDCP
7100                 if (adev->dm.hdcp_workqueue)
7101                         drm_connector_attach_content_protection_property(&aconnector->base, true);
7102 #endif
7103         }
7104 }
7105
7106 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
7107                               struct i2c_msg *msgs, int num)
7108 {
7109         struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
7110         struct ddc_service *ddc_service = i2c->ddc_service;
7111         struct i2c_command cmd;
7112         int i;
7113         int result = -EIO;
7114
7115         cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
7116
7117         if (!cmd.payloads)
7118                 return result;
7119
7120         cmd.number_of_payloads = num;
7121         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
7122         cmd.speed = 100;
7123
7124         for (i = 0; i < num; i++) {
7125                 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
7126                 cmd.payloads[i].address = msgs[i].addr;
7127                 cmd.payloads[i].length = msgs[i].len;
7128                 cmd.payloads[i].data = msgs[i].buf;
7129         }
7130
7131         if (dc_submit_i2c(
7132                         ddc_service->ctx->dc,
7133                         ddc_service->link->link_index,
7134                         &cmd))
7135                 result = num;
7136
7137         kfree(cmd.payloads);
7138         return result;
7139 }
7140
7141 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
7142 {
7143         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
7144 }
7145
7146 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
7147         .master_xfer = amdgpu_dm_i2c_xfer,
7148         .functionality = amdgpu_dm_i2c_func,
7149 };
7150
7151 static struct amdgpu_i2c_adapter *
7152 create_i2c(struct ddc_service *ddc_service,
7153            int link_index,
7154            int *res)
7155 {
7156         struct amdgpu_device *adev = ddc_service->ctx->driver_context;
7157         struct amdgpu_i2c_adapter *i2c;
7158
7159         i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
7160         if (!i2c)
7161                 return NULL;
7162         i2c->base.owner = THIS_MODULE;
7163         i2c->base.class = I2C_CLASS_DDC;
7164         i2c->base.dev.parent = &adev->pdev->dev;
7165         i2c->base.algo = &amdgpu_dm_i2c_algo;
7166         snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
7167         i2c_set_adapdata(&i2c->base, i2c);
7168         i2c->ddc_service = ddc_service;
7169
7170         return i2c;
7171 }
7172
7173
7174 /*
7175  * Note: this function assumes that dc_link_detect() was called for the
7176  * dc_link which will be represented by this aconnector.
7177  */
7178 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
7179                                     struct amdgpu_dm_connector *aconnector,
7180                                     uint32_t link_index,
7181                                     struct amdgpu_encoder *aencoder)
7182 {
7183         int res = 0;
7184         int connector_type;
7185         struct dc *dc = dm->dc;
7186         struct dc_link *link = dc_get_link_at_index(dc, link_index);
7187         struct amdgpu_i2c_adapter *i2c;
7188
7189         link->priv = aconnector;
7190
7191         DRM_DEBUG_DRIVER("%s()\n", __func__);
7192
7193         i2c = create_i2c(link->ddc, link->link_index, &res);
7194         if (!i2c) {
7195                 DRM_ERROR("Failed to create i2c adapter data\n");
7196                 return -ENOMEM;
7197         }
7198
7199         aconnector->i2c = i2c;
7200         res = i2c_add_adapter(&i2c->base);
7201
7202         if (res) {
7203                 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
7204                 goto out_free;
7205         }
7206
7207         connector_type = to_drm_connector_type(link->connector_signal);
7208
7209         res = drm_connector_init_with_ddc(
7210                         dm->ddev,
7211                         &aconnector->base,
7212                         &amdgpu_dm_connector_funcs,
7213                         connector_type,
7214                         &i2c->base);
7215
7216         if (res) {
7217                 DRM_ERROR("connector_init failed\n");
7218                 aconnector->connector_id = -1;
7219                 goto out_free;
7220         }
7221
7222         drm_connector_helper_add(
7223                         &aconnector->base,
7224                         &amdgpu_dm_connector_helper_funcs);
7225
7226         amdgpu_dm_connector_init_helper(
7227                 dm,
7228                 aconnector,
7229                 connector_type,
7230                 link,
7231                 link_index);
7232
7233         drm_connector_attach_encoder(
7234                 &aconnector->base, &aencoder->base);
7235
7236         if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
7237                 || connector_type == DRM_MODE_CONNECTOR_eDP)
7238                 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);
7239
7240 out_free:
7241         if (res) {
7242                 kfree(i2c);
7243                 aconnector->i2c = NULL;
7244         }
7245         return res;
7246 }
7247
7248 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
7249 {
7250         switch (adev->mode_info.num_crtc) {
7251         case 1:
7252                 return 0x1;
7253         case 2:
7254                 return 0x3;
7255         case 3:
7256                 return 0x7;
7257         case 4:
7258                 return 0xf;
7259         case 5:
7260                 return 0x1f;
7261         case 6:
7262         default:
7263                 return 0x3f;
7264         }
7265 }
7266
7267 static int amdgpu_dm_encoder_init(struct drm_device *dev,
7268                                   struct amdgpu_encoder *aencoder,
7269                                   uint32_t link_index)
7270 {
7271         struct amdgpu_device *adev = drm_to_adev(dev);
7272
7273         int res = drm_encoder_init(dev,
7274                                    &aencoder->base,
7275                                    &amdgpu_dm_encoder_funcs,
7276                                    DRM_MODE_ENCODER_TMDS,
7277                                    NULL);
7278
7279         aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
7280
7281         if (!res)
7282                 aencoder->encoder_id = link_index;
7283         else
7284                 aencoder->encoder_id = -1;
7285
7286         drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
7287
7288         return res;
7289 }
7290
7291 static void manage_dm_interrupts(struct amdgpu_device *adev,
7292                                  struct amdgpu_crtc *acrtc,
7293                                  bool enable)
7294 {
7295         /*
7296          * We have no guarantee that the frontend index maps to the same
7297          * backend index - some even map to more than one.
7298          *
7299          * TODO: Use a different interrupt or check DC itself for the mapping.
7300          */
7301         int irq_type =
7302                 amdgpu_display_crtc_idx_to_irq_type(
7303                         adev,
7304                         acrtc->crtc_id);
7305
7306         if (enable) {
7307                 drm_crtc_vblank_on(&acrtc->base);
7308                 amdgpu_irq_get(
7309                         adev,
7310                         &adev->pageflip_irq,
7311                         irq_type);
7312 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7313                 amdgpu_irq_get(
7314                         adev,
7315                         &adev->vline0_irq,
7316                         irq_type);
7317 #endif
7318         } else {
7319 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7320                 amdgpu_irq_put(
7321                         adev,
7322                         &adev->vline0_irq,
7323                         irq_type);
7324 #endif
7325                 amdgpu_irq_put(
7326                         adev,
7327                         &adev->pageflip_irq,
7328                         irq_type);
7329                 drm_crtc_vblank_off(&acrtc->base);
7330         }
7331 }
7332
7333 static void dm_update_pflip_irq_state(struct amdgpu_device *adev,
7334                                       struct amdgpu_crtc *acrtc)
7335 {
7336         int irq_type =
7337                 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
7338
7339         /**
7340          * This reads the current state for the IRQ and force reapplies
7341          * the setting to hardware.
7342          */
7343         amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type);
7344 }
7345
7346 static bool
7347 is_scaling_state_different(const struct dm_connector_state *dm_state,
7348                            const struct dm_connector_state *old_dm_state)
7349 {
7350         if (dm_state->scaling != old_dm_state->scaling)
7351                 return true;
7352         if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
7353                 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
7354                         return true;
7355         } else  if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
7356                 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
7357                         return true;
7358         } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
7359                    dm_state->underscan_vborder != old_dm_state->underscan_vborder)
7360                 return true;
7361         return false;
7362 }
7363
7364 #ifdef CONFIG_DRM_AMD_DC_HDCP
7365 static bool is_content_protection_different(struct drm_connector_state *state,
7366                                             const struct drm_connector_state *old_state,
7367                                             const struct drm_connector *connector, struct hdcp_workqueue *hdcp_w)
7368 {
7369         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7370         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
7371
7372         /* Handle: Type0/1 change */
7373         if (old_state->hdcp_content_type != state->hdcp_content_type &&
7374             state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
7375                 state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7376                 return true;
7377         }
7378
7379         /* CP is being re enabled, ignore this
7380          *
7381          * Handles:     ENABLED -> DESIRED
7382          */
7383         if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
7384             state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7385                 state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
7386                 return false;
7387         }
7388
7389         /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED
7390          *
7391          * Handles:     UNDESIRED -> ENABLED
7392          */
7393         if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
7394             state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
7395                 state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7396
7397         /* Stream removed and re-enabled
7398          *
7399          * Can sometimes overlap with the HPD case,
7400          * thus set update_hdcp to false to avoid
7401          * setting HDCP multiple times.
7402          *
7403          * Handles:     DESIRED -> DESIRED (Special case)
7404          */
7405         if (!(old_state->crtc && old_state->crtc->enabled) &&
7406                 state->crtc && state->crtc->enabled &&
7407                 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7408                 dm_con_state->update_hdcp = false;
7409                 return true;
7410         }
7411
7412         /* Hot-plug, headless s3, dpms
7413          *
7414          * Only start HDCP if the display is connected/enabled.
7415          * update_hdcp flag will be set to false until the next
7416          * HPD comes in.
7417          *
7418          * Handles:     DESIRED -> DESIRED (Special case)
7419          */
7420         if (dm_con_state->update_hdcp && state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
7421             connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
7422                 dm_con_state->update_hdcp = false;
7423                 return true;
7424         }
7425
7426         /*
7427          * Handles:     UNDESIRED -> UNDESIRED
7428          *              DESIRED -> DESIRED
7429          *              ENABLED -> ENABLED
7430          */
7431         if (old_state->content_protection == state->content_protection)
7432                 return false;
7433
7434         /*
7435          * Handles:     UNDESIRED -> DESIRED
7436          *              DESIRED -> UNDESIRED
7437          *              ENABLED -> UNDESIRED
7438          */
7439         if (state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED)
7440                 return true;
7441
7442         /*
7443          * Handles:     DESIRED -> ENABLED
7444          */
7445         return false;
7446 }
7447
7448 #endif
7449 static void remove_stream(struct amdgpu_device *adev,
7450                           struct amdgpu_crtc *acrtc,
7451                           struct dc_stream_state *stream)
7452 {
7453         /* this is the update mode case */
7454
7455         acrtc->otg_inst = -1;
7456         acrtc->enabled = false;
7457 }
7458
7459 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
7460 {
7461
7462         assert_spin_locked(&acrtc->base.dev->event_lock);
7463         WARN_ON(acrtc->event);
7464
7465         acrtc->event = acrtc->base.state->event;
7466
7467         /* Set the flip status */
7468         acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
7469
7470         /* Mark this event as consumed */
7471         acrtc->base.state->event = NULL;
7472
7473         DC_LOG_PFLIP("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
7474                      acrtc->crtc_id);
7475 }
7476
7477 static void update_freesync_state_on_stream(
7478         struct amdgpu_display_manager *dm,
7479         struct dm_crtc_state *new_crtc_state,
7480         struct dc_stream_state *new_stream,
7481         struct dc_plane_state *surface,
7482         u32 flip_timestamp_in_us)
7483 {
7484         struct mod_vrr_params vrr_params;
7485         struct dc_info_packet vrr_infopacket = {0};
7486         struct amdgpu_device *adev = dm->adev;
7487         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7488         unsigned long flags;
7489         bool pack_sdp_v1_3 = false;
7490
7491         if (!new_stream)
7492                 return;
7493
7494         /*
7495          * TODO: Determine why min/max totals and vrefresh can be 0 here.
7496          * For now it's sufficient to just guard against these conditions.
7497          */
7498
7499         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7500                 return;
7501
7502         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7503         vrr_params = acrtc->dm_irq_params.vrr_params;
7504
7505         if (surface) {
7506                 mod_freesync_handle_preflip(
7507                         dm->freesync_module,
7508                         surface,
7509                         new_stream,
7510                         flip_timestamp_in_us,
7511                         &vrr_params);
7512
7513                 if (adev->family < AMDGPU_FAMILY_AI &&
7514                     amdgpu_dm_vrr_active(new_crtc_state)) {
7515                         mod_freesync_handle_v_update(dm->freesync_module,
7516                                                      new_stream, &vrr_params);
7517
7518                         /* Need to call this before the frame ends. */
7519                         dc_stream_adjust_vmin_vmax(dm->dc,
7520                                                    new_crtc_state->stream,
7521                                                    &vrr_params.adjust);
7522                 }
7523         }
7524
7525         mod_freesync_build_vrr_infopacket(
7526                 dm->freesync_module,
7527                 new_stream,
7528                 &vrr_params,
7529                 PACKET_TYPE_VRR,
7530                 TRANSFER_FUNC_UNKNOWN,
7531                 &vrr_infopacket,
7532                 pack_sdp_v1_3);
7533
7534         new_crtc_state->freesync_vrr_info_changed |=
7535                 (memcmp(&new_crtc_state->vrr_infopacket,
7536                         &vrr_infopacket,
7537                         sizeof(vrr_infopacket)) != 0);
7538
7539         acrtc->dm_irq_params.vrr_params = vrr_params;
7540         new_crtc_state->vrr_infopacket = vrr_infopacket;
7541
7542         new_stream->vrr_infopacket = vrr_infopacket;
7543
7544         if (new_crtc_state->freesync_vrr_info_changed)
7545                 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
7546                               new_crtc_state->base.crtc->base.id,
7547                               (int)new_crtc_state->base.vrr_enabled,
7548                               (int)vrr_params.state);
7549
7550         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7551 }
7552
7553 static void update_stream_irq_parameters(
7554         struct amdgpu_display_manager *dm,
7555         struct dm_crtc_state *new_crtc_state)
7556 {
7557         struct dc_stream_state *new_stream = new_crtc_state->stream;
7558         struct mod_vrr_params vrr_params;
7559         struct mod_freesync_config config = new_crtc_state->freesync_config;
7560         struct amdgpu_device *adev = dm->adev;
7561         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7562         unsigned long flags;
7563
7564         if (!new_stream)
7565                 return;
7566
7567         /*
7568          * TODO: Determine why min/max totals and vrefresh can be 0 here.
7569          * For now it's sufficient to just guard against these conditions.
7570          */
7571         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7572                 return;
7573
7574         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7575         vrr_params = acrtc->dm_irq_params.vrr_params;
7576
7577         if (new_crtc_state->vrr_supported &&
7578             config.min_refresh_in_uhz &&
7579             config.max_refresh_in_uhz) {
7580                 /*
7581                  * if freesync compatible mode was set, config.state will be set
7582                  * in atomic check
7583                  */
7584                 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz &&
7585                     (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) ||
7586                      new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) {
7587                         vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz;
7588                         vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz;
7589                         vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz;
7590                         vrr_params.state = VRR_STATE_ACTIVE_FIXED;
7591                 } else {
7592                         config.state = new_crtc_state->base.vrr_enabled ?
7593                                                      VRR_STATE_ACTIVE_VARIABLE :
7594                                                      VRR_STATE_INACTIVE;
7595                 }
7596         } else {
7597                 config.state = VRR_STATE_UNSUPPORTED;
7598         }
7599
7600         mod_freesync_build_vrr_params(dm->freesync_module,
7601                                       new_stream,
7602                                       &config, &vrr_params);
7603
7604         new_crtc_state->freesync_config = config;
7605         /* Copy state for access from DM IRQ handler */
7606         acrtc->dm_irq_params.freesync_config = config;
7607         acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes;
7608         acrtc->dm_irq_params.vrr_params = vrr_params;
7609         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7610 }
7611
7612 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
7613                                             struct dm_crtc_state *new_state)
7614 {
7615         bool old_vrr_active = amdgpu_dm_vrr_active(old_state);
7616         bool new_vrr_active = amdgpu_dm_vrr_active(new_state);
7617
7618         if (!old_vrr_active && new_vrr_active) {
7619                 /* Transition VRR inactive -> active:
7620                  * While VRR is active, we must not disable vblank irq, as a
7621                  * reenable after disable would compute bogus vblank/pflip
7622                  * timestamps if it likely happened inside display front-porch.
7623                  *
7624                  * We also need vupdate irq for the actual core vblank handling
7625                  * at end of vblank.
7626                  */
7627                 WARN_ON(dm_set_vupdate_irq(new_state->base.crtc, true) != 0);
7628                 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0);
7629                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
7630                                  __func__, new_state->base.crtc->base.id);
7631         } else if (old_vrr_active && !new_vrr_active) {
7632                 /* Transition VRR active -> inactive:
7633                  * Allow vblank irq disable again for fixed refresh rate.
7634                  */
7635                 WARN_ON(dm_set_vupdate_irq(new_state->base.crtc, false) != 0);
7636                 drm_crtc_vblank_put(new_state->base.crtc);
7637                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
7638                                  __func__, new_state->base.crtc->base.id);
7639         }
7640 }
7641
7642 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
7643 {
7644         struct drm_plane *plane;
7645         struct drm_plane_state *old_plane_state;
7646         int i;
7647
7648         /*
7649          * TODO: Make this per-stream so we don't issue redundant updates for
7650          * commits with multiple streams.
7651          */
7652         for_each_old_plane_in_state(state, plane, old_plane_state, i)
7653                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
7654                         handle_cursor_update(plane, old_plane_state);
7655 }
7656
7657 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
7658                                     struct dc_state *dc_state,
7659                                     struct drm_device *dev,
7660                                     struct amdgpu_display_manager *dm,
7661                                     struct drm_crtc *pcrtc,
7662                                     bool wait_for_vblank)
7663 {
7664         uint32_t i;
7665         uint64_t timestamp_ns;
7666         struct drm_plane *plane;
7667         struct drm_plane_state *old_plane_state, *new_plane_state;
7668         struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
7669         struct drm_crtc_state *new_pcrtc_state =
7670                         drm_atomic_get_new_crtc_state(state, pcrtc);
7671         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
7672         struct dm_crtc_state *dm_old_crtc_state =
7673                         to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
7674         int planes_count = 0, vpos, hpos;
7675         unsigned long flags;
7676         uint32_t target_vblank, last_flip_vblank;
7677         bool vrr_active = amdgpu_dm_vrr_active(acrtc_state);
7678         bool cursor_update = false;
7679         bool pflip_present = false;
7680         struct {
7681                 struct dc_surface_update surface_updates[MAX_SURFACES];
7682                 struct dc_plane_info plane_infos[MAX_SURFACES];
7683                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
7684                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
7685                 struct dc_stream_update stream_update;
7686         } *bundle;
7687
7688         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
7689
7690         if (!bundle) {
7691                 dm_error("Failed to allocate update bundle\n");
7692                 goto cleanup;
7693         }
7694
7695         /*
7696          * Disable the cursor first if we're disabling all the planes.
7697          * It'll remain on the screen after the planes are re-enabled
7698          * if we don't.
7699          */
7700         if (acrtc_state->active_planes == 0)
7701                 amdgpu_dm_commit_cursors(state);
7702
7703         /* update planes when needed */
7704         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
7705                 struct drm_crtc *crtc = new_plane_state->crtc;
7706                 struct drm_crtc_state *new_crtc_state;
7707                 struct drm_framebuffer *fb = new_plane_state->fb;
7708                 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb;
7709                 bool plane_needs_flip;
7710                 struct dc_plane_state *dc_plane;
7711                 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
7712
7713                 /* Cursor plane is handled after stream updates */
7714                 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
7715                         if ((fb && crtc == pcrtc) ||
7716                             (old_plane_state->fb && old_plane_state->crtc == pcrtc))
7717                                 cursor_update = true;
7718
7719                         continue;
7720                 }
7721
7722                 if (!fb || !crtc || pcrtc != crtc)
7723                         continue;
7724
7725                 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
7726                 if (!new_crtc_state->active)
7727                         continue;
7728
7729                 dc_plane = dm_new_plane_state->dc_state;
7730
7731                 bundle->surface_updates[planes_count].surface = dc_plane;
7732                 if (new_pcrtc_state->color_mgmt_changed) {
7733                         bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
7734                         bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
7735                         bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;
7736                 }
7737
7738                 fill_dc_scaling_info(dm->adev, new_plane_state,
7739                                      &bundle->scaling_infos[planes_count]);
7740
7741                 bundle->surface_updates[planes_count].scaling_info =
7742                         &bundle->scaling_infos[planes_count];
7743
7744                 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
7745
7746                 pflip_present = pflip_present || plane_needs_flip;
7747
7748                 if (!plane_needs_flip) {
7749                         planes_count += 1;
7750                         continue;
7751                 }
7752
7753                 fill_dc_plane_info_and_addr(
7754                         dm->adev, new_plane_state,
7755                         afb->tiling_flags,
7756                         &bundle->plane_infos[planes_count],
7757                         &bundle->flip_addrs[planes_count].address,
7758                         afb->tmz_surface, false);
7759
7760                 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n",
7761                                  new_plane_state->plane->index,
7762                                  bundle->plane_infos[planes_count].dcc.enable);
7763
7764                 bundle->surface_updates[planes_count].plane_info =
7765                         &bundle->plane_infos[planes_count];
7766
7767                 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled)
7768                         fill_dc_dirty_rects(plane, old_plane_state,
7769                                             new_plane_state, new_crtc_state,
7770                                             &bundle->flip_addrs[planes_count]);
7771
7772                 /*
7773                  * Only allow immediate flips for fast updates that don't
7774                  * change FB pitch, DCC state, rotation or mirroing.
7775                  */
7776                 bundle->flip_addrs[planes_count].flip_immediate =
7777                         crtc->state->async_flip &&
7778                         acrtc_state->update_type == UPDATE_TYPE_FAST;
7779
7780                 timestamp_ns = ktime_get_ns();
7781                 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
7782                 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
7783                 bundle->surface_updates[planes_count].surface = dc_plane;
7784
7785                 if (!bundle->surface_updates[planes_count].surface) {
7786                         DRM_ERROR("No surface for CRTC: id=%d\n",
7787                                         acrtc_attach->crtc_id);
7788                         continue;
7789                 }
7790
7791                 if (plane == pcrtc->primary)
7792                         update_freesync_state_on_stream(
7793                                 dm,
7794                                 acrtc_state,
7795                                 acrtc_state->stream,
7796                                 dc_plane,
7797                                 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
7798
7799                 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n",
7800                                  __func__,
7801                                  bundle->flip_addrs[planes_count].address.grph.addr.high_part,
7802                                  bundle->flip_addrs[planes_count].address.grph.addr.low_part);
7803
7804                 planes_count += 1;
7805
7806         }
7807
7808         if (pflip_present) {
7809                 if (!vrr_active) {
7810                         /* Use old throttling in non-vrr fixed refresh rate mode
7811                          * to keep flip scheduling based on target vblank counts
7812                          * working in a backwards compatible way, e.g., for
7813                          * clients using the GLX_OML_sync_control extension or
7814                          * DRI3/Present extension with defined target_msc.
7815                          */
7816                         last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);
7817                 }
7818                 else {
7819                         /* For variable refresh rate mode only:
7820                          * Get vblank of last completed flip to avoid > 1 vrr
7821                          * flips per video frame by use of throttling, but allow
7822                          * flip programming anywhere in the possibly large
7823                          * variable vrr vblank interval for fine-grained flip
7824                          * timing control and more opportunity to avoid stutter
7825                          * on late submission of flips.
7826                          */
7827                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
7828                         last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank;
7829                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
7830                 }
7831
7832                 target_vblank = last_flip_vblank + wait_for_vblank;
7833
7834                 /*
7835                  * Wait until we're out of the vertical blank period before the one
7836                  * targeted by the flip
7837                  */
7838                 while ((acrtc_attach->enabled &&
7839                         (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
7840                                                             0, &vpos, &hpos, NULL,
7841                                                             NULL, &pcrtc->hwmode)
7842                          & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
7843                         (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
7844                         (int)(target_vblank -
7845                           amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) {
7846                         usleep_range(1000, 1100);
7847                 }
7848
7849                 /**
7850                  * Prepare the flip event for the pageflip interrupt to handle.
7851                  *
7852                  * This only works in the case where we've already turned on the
7853                  * appropriate hardware blocks (eg. HUBP) so in the transition case
7854                  * from 0 -> n planes we have to skip a hardware generated event
7855                  * and rely on sending it from software.
7856                  */
7857                 if (acrtc_attach->base.state->event &&
7858                     acrtc_state->active_planes > 0) {
7859                         drm_crtc_vblank_get(pcrtc);
7860
7861                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
7862
7863                         WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
7864                         prepare_flip_isr(acrtc_attach);
7865
7866                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
7867                 }
7868
7869                 if (acrtc_state->stream) {
7870                         if (acrtc_state->freesync_vrr_info_changed)
7871                                 bundle->stream_update.vrr_infopacket =
7872                                         &acrtc_state->stream->vrr_infopacket;
7873                 }
7874         } else if (cursor_update && acrtc_state->active_planes > 0 &&
7875                    acrtc_attach->base.state->event) {
7876                 drm_crtc_vblank_get(pcrtc);
7877
7878                 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
7879
7880                 acrtc_attach->event = acrtc_attach->base.state->event;
7881                 acrtc_attach->base.state->event = NULL;
7882
7883                 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
7884         }
7885
7886         /* Update the planes if changed or disable if we don't have any. */
7887         if ((planes_count || acrtc_state->active_planes == 0) &&
7888                 acrtc_state->stream) {
7889                 /*
7890                  * If PSR or idle optimizations are enabled then flush out
7891                  * any pending work before hardware programming.
7892                  */
7893                 if (dm->vblank_control_workqueue)
7894                         flush_workqueue(dm->vblank_control_workqueue);
7895
7896                 bundle->stream_update.stream = acrtc_state->stream;
7897                 if (new_pcrtc_state->mode_changed) {
7898                         bundle->stream_update.src = acrtc_state->stream->src;
7899                         bundle->stream_update.dst = acrtc_state->stream->dst;
7900                 }
7901
7902                 if (new_pcrtc_state->color_mgmt_changed) {
7903                         /*
7904                          * TODO: This isn't fully correct since we've actually
7905                          * already modified the stream in place.
7906                          */
7907                         bundle->stream_update.gamut_remap =
7908                                 &acrtc_state->stream->gamut_remap_matrix;
7909                         bundle->stream_update.output_csc_transform =
7910                                 &acrtc_state->stream->csc_color_matrix;
7911                         bundle->stream_update.out_transfer_func =
7912                                 acrtc_state->stream->out_transfer_func;
7913                 }
7914
7915                 acrtc_state->stream->abm_level = acrtc_state->abm_level;
7916                 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
7917                         bundle->stream_update.abm_level = &acrtc_state->abm_level;
7918
7919                 /*
7920                  * If FreeSync state on the stream has changed then we need to
7921                  * re-adjust the min/max bounds now that DC doesn't handle this
7922                  * as part of commit.
7923                  */
7924                 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) {
7925                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
7926                         dc_stream_adjust_vmin_vmax(
7927                                 dm->dc, acrtc_state->stream,
7928                                 &acrtc_attach->dm_irq_params.vrr_params.adjust);
7929                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
7930                 }
7931                 mutex_lock(&dm->dc_lock);
7932                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
7933                                 acrtc_state->stream->link->psr_settings.psr_allow_active)
7934                         amdgpu_dm_psr_disable(acrtc_state->stream);
7935
7936                 dc_commit_updates_for_stream(dm->dc,
7937                                                      bundle->surface_updates,
7938                                                      planes_count,
7939                                                      acrtc_state->stream,
7940                                                      &bundle->stream_update,
7941                                                      dc_state);
7942
7943                 /**
7944                  * Enable or disable the interrupts on the backend.
7945                  *
7946                  * Most pipes are put into power gating when unused.
7947                  *
7948                  * When power gating is enabled on a pipe we lose the
7949                  * interrupt enablement state when power gating is disabled.
7950                  *
7951                  * So we need to update the IRQ control state in hardware
7952                  * whenever the pipe turns on (since it could be previously
7953                  * power gated) or off (since some pipes can't be power gated
7954                  * on some ASICs).
7955                  */
7956                 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes)
7957                         dm_update_pflip_irq_state(drm_to_adev(dev),
7958                                                   acrtc_attach);
7959
7960                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
7961                                 acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
7962                                 !acrtc_state->stream->link->psr_settings.psr_feature_enabled)
7963                         amdgpu_dm_link_setup_psr(acrtc_state->stream);
7964
7965                 /* Decrement skip count when PSR is enabled and we're doing fast updates. */
7966                 if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
7967                     acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
7968                         struct amdgpu_dm_connector *aconn =
7969                                 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
7970
7971                         if (aconn->psr_skip_count > 0)
7972                                 aconn->psr_skip_count--;
7973
7974                         /* Allow PSR when skip count is 0. */
7975                         acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count;
7976
7977                         /*
7978                          * If sink supports PSR SU, there is no need to rely on
7979                          * a vblank event disable request to enable PSR. PSR SU
7980                          * can be enabled immediately once OS demonstrates an
7981                          * adequate number of fast atomic commits to notify KMD
7982                          * of update events. See `vblank_control_worker()`.
7983                          */
7984                         if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
7985                             acrtc_attach->dm_irq_params.allow_psr_entry &&
7986 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
7987                             !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
7988 #endif
7989                             !acrtc_state->stream->link->psr_settings.psr_allow_active)
7990                                 amdgpu_dm_psr_enable(acrtc_state->stream);
7991                 } else {
7992                         acrtc_attach->dm_irq_params.allow_psr_entry = false;
7993                 }
7994
7995                 mutex_unlock(&dm->dc_lock);
7996         }
7997
7998         /*
7999          * Update cursor state *after* programming all the planes.
8000          * This avoids redundant programming in the case where we're going
8001          * to be disabling a single plane - those pipes are being disabled.
8002          */
8003         if (acrtc_state->active_planes)
8004                 amdgpu_dm_commit_cursors(state);
8005
8006 cleanup:
8007         kfree(bundle);
8008 }
8009
8010 static void amdgpu_dm_commit_audio(struct drm_device *dev,
8011                                    struct drm_atomic_state *state)
8012 {
8013         struct amdgpu_device *adev = drm_to_adev(dev);
8014         struct amdgpu_dm_connector *aconnector;
8015         struct drm_connector *connector;
8016         struct drm_connector_state *old_con_state, *new_con_state;
8017         struct drm_crtc_state *new_crtc_state;
8018         struct dm_crtc_state *new_dm_crtc_state;
8019         const struct dc_stream_status *status;
8020         int i, inst;
8021
8022         /* Notify device removals. */
8023         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8024                 if (old_con_state->crtc != new_con_state->crtc) {
8025                         /* CRTC changes require notification. */
8026                         goto notify;
8027                 }
8028
8029                 if (!new_con_state->crtc)
8030                         continue;
8031
8032                 new_crtc_state = drm_atomic_get_new_crtc_state(
8033                         state, new_con_state->crtc);
8034
8035                 if (!new_crtc_state)
8036                         continue;
8037
8038                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8039                         continue;
8040
8041         notify:
8042                 aconnector = to_amdgpu_dm_connector(connector);
8043
8044                 mutex_lock(&adev->dm.audio_lock);
8045                 inst = aconnector->audio_inst;
8046                 aconnector->audio_inst = -1;
8047                 mutex_unlock(&adev->dm.audio_lock);
8048
8049                 amdgpu_dm_audio_eld_notify(adev, inst);
8050         }
8051
8052         /* Notify audio device additions. */
8053         for_each_new_connector_in_state(state, connector, new_con_state, i) {
8054                 if (!new_con_state->crtc)
8055                         continue;
8056
8057                 new_crtc_state = drm_atomic_get_new_crtc_state(
8058                         state, new_con_state->crtc);
8059
8060                 if (!new_crtc_state)
8061                         continue;
8062
8063                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8064                         continue;
8065
8066                 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
8067                 if (!new_dm_crtc_state->stream)
8068                         continue;
8069
8070                 status = dc_stream_get_status(new_dm_crtc_state->stream);
8071                 if (!status)
8072                         continue;
8073
8074                 aconnector = to_amdgpu_dm_connector(connector);
8075
8076                 mutex_lock(&adev->dm.audio_lock);
8077                 inst = status->audio_inst;
8078                 aconnector->audio_inst = inst;
8079                 mutex_unlock(&adev->dm.audio_lock);
8080
8081                 amdgpu_dm_audio_eld_notify(adev, inst);
8082         }
8083 }
8084
8085 /*
8086  * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
8087  * @crtc_state: the DRM CRTC state
8088  * @stream_state: the DC stream state.
8089  *
8090  * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
8091  * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
8092  */
8093 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
8094                                                 struct dc_stream_state *stream_state)
8095 {
8096         stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
8097 }
8098
8099 /**
8100  * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
8101  * @state: The atomic state to commit
8102  *
8103  * This will tell DC to commit the constructed DC state from atomic_check,
8104  * programming the hardware. Any failures here implies a hardware failure, since
8105  * atomic check should have filtered anything non-kosher.
8106  */
8107 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
8108 {
8109         struct drm_device *dev = state->dev;
8110         struct amdgpu_device *adev = drm_to_adev(dev);
8111         struct amdgpu_display_manager *dm = &adev->dm;
8112         struct dm_atomic_state *dm_state;
8113         struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
8114         uint32_t i, j;
8115         struct drm_crtc *crtc;
8116         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8117         unsigned long flags;
8118         bool wait_for_vblank = true;
8119         struct drm_connector *connector;
8120         struct drm_connector_state *old_con_state, *new_con_state;
8121         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8122         int crtc_disable_count = 0;
8123         bool mode_set_reset_required = false;
8124         int r;
8125
8126         trace_amdgpu_dm_atomic_commit_tail_begin(state);
8127
8128         r = drm_atomic_helper_wait_for_fences(dev, state, false);
8129         if (unlikely(r))
8130                 DRM_ERROR("Waiting for fences timed out!");
8131
8132         drm_atomic_helper_update_legacy_modeset_state(dev, state);
8133         drm_dp_mst_atomic_wait_for_dependencies(state);
8134
8135         dm_state = dm_atomic_get_new_state(state);
8136         if (dm_state && dm_state->context) {
8137                 dc_state = dm_state->context;
8138         } else {
8139                 /* No state changes, retain current state. */
8140                 dc_state_temp = dc_create_state(dm->dc);
8141                 ASSERT(dc_state_temp);
8142                 dc_state = dc_state_temp;
8143                 dc_resource_state_copy_construct_current(dm->dc, dc_state);
8144         }
8145
8146         for_each_oldnew_crtc_in_state (state, crtc, old_crtc_state,
8147                                        new_crtc_state, i) {
8148                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8149
8150                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8151
8152                 if (old_crtc_state->active &&
8153                     (!new_crtc_state->active ||
8154                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8155                         manage_dm_interrupts(adev, acrtc, false);
8156                         dc_stream_release(dm_old_crtc_state->stream);
8157                 }
8158         }
8159
8160         drm_atomic_helper_calc_timestamping_constants(state);
8161
8162         /* update changed items */
8163         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8164                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8165
8166                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8167                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8168
8169                 drm_dbg_state(state->dev,
8170                         "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
8171                         "planes_changed:%d, mode_changed:%d,active_changed:%d,"
8172                         "connectors_changed:%d\n",
8173                         acrtc->crtc_id,
8174                         new_crtc_state->enable,
8175                         new_crtc_state->active,
8176                         new_crtc_state->planes_changed,
8177                         new_crtc_state->mode_changed,
8178                         new_crtc_state->active_changed,
8179                         new_crtc_state->connectors_changed);
8180
8181                 /* Disable cursor if disabling crtc */
8182                 if (old_crtc_state->active && !new_crtc_state->active) {
8183                         struct dc_cursor_position position;
8184
8185                         memset(&position, 0, sizeof(position));
8186                         mutex_lock(&dm->dc_lock);
8187                         dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position);
8188                         mutex_unlock(&dm->dc_lock);
8189                 }
8190
8191                 /* Copy all transient state flags into dc state */
8192                 if (dm_new_crtc_state->stream) {
8193                         amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
8194                                                             dm_new_crtc_state->stream);
8195                 }
8196
8197                 /* handles headless hotplug case, updating new_state and
8198                  * aconnector as needed
8199                  */
8200
8201                 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
8202
8203                         DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
8204
8205                         if (!dm_new_crtc_state->stream) {
8206                                 /*
8207                                  * this could happen because of issues with
8208                                  * userspace notifications delivery.
8209                                  * In this case userspace tries to set mode on
8210                                  * display which is disconnected in fact.
8211                                  * dc_sink is NULL in this case on aconnector.
8212                                  * We expect reset mode will come soon.
8213                                  *
8214                                  * This can also happen when unplug is done
8215                                  * during resume sequence ended
8216                                  *
8217                                  * In this case, we want to pretend we still
8218                                  * have a sink to keep the pipe running so that
8219                                  * hw state is consistent with the sw state
8220                                  */
8221                                 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
8222                                                 __func__, acrtc->base.base.id);
8223                                 continue;
8224                         }
8225
8226                         if (dm_old_crtc_state->stream)
8227                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8228
8229                         pm_runtime_get_noresume(dev->dev);
8230
8231                         acrtc->enabled = true;
8232                         acrtc->hw_mode = new_crtc_state->mode;
8233                         crtc->hwmode = new_crtc_state->mode;
8234                         mode_set_reset_required = true;
8235                 } else if (modereset_required(new_crtc_state)) {
8236                         DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
8237                         /* i.e. reset mode */
8238                         if (dm_old_crtc_state->stream)
8239                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8240
8241                         mode_set_reset_required = true;
8242                 }
8243         } /* for_each_crtc_in_state() */
8244
8245         if (dc_state) {
8246                 /* if there mode set or reset, disable eDP PSR */
8247                 if (mode_set_reset_required) {
8248                         if (dm->vblank_control_workqueue)
8249                                 flush_workqueue(dm->vblank_control_workqueue);
8250
8251                         amdgpu_dm_psr_disable_all(dm);
8252                 }
8253
8254                 dm_enable_per_frame_crtc_master_sync(dc_state);
8255                 mutex_lock(&dm->dc_lock);
8256                 WARN_ON(!dc_commit_state(dm->dc, dc_state));
8257
8258                 /* Allow idle optimization when vblank count is 0 for display off */
8259                 if (dm->active_vblank_irq_count == 0)
8260                         dc_allow_idle_optimizations(dm->dc, true);
8261                 mutex_unlock(&dm->dc_lock);
8262         }
8263
8264         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8265                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8266
8267                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8268
8269                 if (dm_new_crtc_state->stream != NULL) {
8270                         const struct dc_stream_status *status =
8271                                         dc_stream_get_status(dm_new_crtc_state->stream);
8272
8273                         if (!status)
8274                                 status = dc_stream_get_status_from_state(dc_state,
8275                                                                          dm_new_crtc_state->stream);
8276                         if (!status)
8277                                 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
8278                         else
8279                                 acrtc->otg_inst = status->primary_otg_inst;
8280                 }
8281         }
8282 #ifdef CONFIG_DRM_AMD_DC_HDCP
8283         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8284                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8285                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8286                 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8287
8288                 new_crtc_state = NULL;
8289
8290                 if (acrtc)
8291                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8292
8293                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8294
8295                 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
8296                     connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
8297                         hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
8298                         new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
8299                         dm_new_con_state->update_hdcp = true;
8300                         continue;
8301                 }
8302
8303                 if (is_content_protection_different(new_con_state, old_con_state, connector, adev->dm.hdcp_workqueue))
8304                         hdcp_update_display(
8305                                 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
8306                                 new_con_state->hdcp_content_type,
8307                                 new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED);
8308         }
8309 #endif
8310
8311         /* Handle connector state changes */
8312         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8313                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8314                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
8315                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8316                 struct dc_surface_update dummy_updates[MAX_SURFACES];
8317                 struct dc_stream_update stream_update;
8318                 struct dc_info_packet hdr_packet;
8319                 struct dc_stream_status *status = NULL;
8320                 bool abm_changed, hdr_changed, scaling_changed;
8321
8322                 memset(&dummy_updates, 0, sizeof(dummy_updates));
8323                 memset(&stream_update, 0, sizeof(stream_update));
8324
8325                 if (acrtc) {
8326                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8327                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8328                 }
8329
8330                 /* Skip any modesets/resets */
8331                 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
8332                         continue;
8333
8334                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8335                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8336
8337                 scaling_changed = is_scaling_state_different(dm_new_con_state,
8338                                                              dm_old_con_state);
8339
8340                 abm_changed = dm_new_crtc_state->abm_level !=
8341                               dm_old_crtc_state->abm_level;
8342
8343                 hdr_changed =
8344                         !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state);
8345
8346                 if (!scaling_changed && !abm_changed && !hdr_changed)
8347                         continue;
8348
8349                 stream_update.stream = dm_new_crtc_state->stream;
8350                 if (scaling_changed) {
8351                         update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
8352                                         dm_new_con_state, dm_new_crtc_state->stream);
8353
8354                         stream_update.src = dm_new_crtc_state->stream->src;
8355                         stream_update.dst = dm_new_crtc_state->stream->dst;
8356                 }
8357
8358                 if (abm_changed) {
8359                         dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
8360
8361                         stream_update.abm_level = &dm_new_crtc_state->abm_level;
8362                 }
8363
8364                 if (hdr_changed) {
8365                         fill_hdr_info_packet(new_con_state, &hdr_packet);
8366                         stream_update.hdr_static_metadata = &hdr_packet;
8367                 }
8368
8369                 status = dc_stream_get_status(dm_new_crtc_state->stream);
8370
8371                 if (WARN_ON(!status))
8372                         continue;
8373
8374                 WARN_ON(!status->plane_count);
8375
8376                 /*
8377                  * TODO: DC refuses to perform stream updates without a dc_surface_update.
8378                  * Here we create an empty update on each plane.
8379                  * To fix this, DC should permit updating only stream properties.
8380                  */
8381                 for (j = 0; j < status->plane_count; j++)
8382                         dummy_updates[j].surface = status->plane_states[0];
8383
8384
8385                 mutex_lock(&dm->dc_lock);
8386                 dc_commit_updates_for_stream(dm->dc,
8387                                                      dummy_updates,
8388                                                      status->plane_count,
8389                                                      dm_new_crtc_state->stream,
8390                                                      &stream_update,
8391                                                      dc_state);
8392                 mutex_unlock(&dm->dc_lock);
8393         }
8394
8395         /**
8396          * Enable interrupts for CRTCs that are newly enabled or went through
8397          * a modeset. It was intentionally deferred until after the front end
8398          * state was modified to wait until the OTG was on and so the IRQ
8399          * handlers didn't access stale or invalid state.
8400          */
8401         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8402                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8403 #ifdef CONFIG_DEBUG_FS
8404                 enum amdgpu_dm_pipe_crc_source cur_crc_src;
8405 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
8406                 struct crc_rd_work *crc_rd_wrk;
8407 #endif
8408 #endif
8409                 /* Count number of newly disabled CRTCs for dropping PM refs later. */
8410                 if (old_crtc_state->active && !new_crtc_state->active)
8411                         crtc_disable_count++;
8412
8413                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8414                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8415
8416                 /* For freesync config update on crtc state and params for irq */
8417                 update_stream_irq_parameters(dm, dm_new_crtc_state);
8418
8419 #ifdef CONFIG_DEBUG_FS
8420 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
8421                 crc_rd_wrk = dm->crc_rd_wrk;
8422 #endif
8423                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8424                 cur_crc_src = acrtc->dm_irq_params.crc_src;
8425                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8426 #endif
8427
8428                 if (new_crtc_state->active &&
8429                     (!old_crtc_state->active ||
8430                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8431                         dc_stream_retain(dm_new_crtc_state->stream);
8432                         acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
8433                         manage_dm_interrupts(adev, acrtc, true);
8434                 }
8435                 /* Handle vrr on->off / off->on transitions */
8436                 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state);
8437
8438 #ifdef CONFIG_DEBUG_FS
8439                 if (new_crtc_state->active &&
8440                     (!old_crtc_state->active ||
8441                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8442                         /**
8443                          * Frontend may have changed so reapply the CRC capture
8444                          * settings for the stream.
8445                          */
8446                         if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
8447 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
8448                                 if (amdgpu_dm_crc_window_is_activated(crtc)) {
8449                                         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8450                                         acrtc->dm_irq_params.window_param.update_win = true;
8451                                         acrtc->dm_irq_params.window_param.skip_frame_cnt = 2;
8452                                         spin_lock_irq(&crc_rd_wrk->crc_rd_work_lock);
8453                                         crc_rd_wrk->crtc = crtc;
8454                                         spin_unlock_irq(&crc_rd_wrk->crc_rd_work_lock);
8455                                         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8456                                 }
8457 #endif
8458                                 if (amdgpu_dm_crtc_configure_crc_source(
8459                                         crtc, dm_new_crtc_state, cur_crc_src))
8460                                         DRM_DEBUG_DRIVER("Failed to configure crc source");
8461                         }
8462                 }
8463 #endif
8464         }
8465
8466         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
8467                 if (new_crtc_state->async_flip)
8468                         wait_for_vblank = false;
8469
8470         /* update planes when needed per crtc*/
8471         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
8472                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8473
8474                 if (dm_new_crtc_state->stream)
8475                         amdgpu_dm_commit_planes(state, dc_state, dev,
8476                                                 dm, crtc, wait_for_vblank);
8477         }
8478
8479         /* Update audio instances for each connector. */
8480         amdgpu_dm_commit_audio(dev, state);
8481
8482         /* restore the backlight level */
8483         for (i = 0; i < dm->num_of_edps; i++) {
8484                 if (dm->backlight_dev[i] &&
8485                     (dm->actual_brightness[i] != dm->brightness[i]))
8486                         amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
8487         }
8488
8489         /*
8490          * send vblank event on all events not handled in flip and
8491          * mark consumed event for drm_atomic_helper_commit_hw_done
8492          */
8493         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8494         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8495
8496                 if (new_crtc_state->event)
8497                         drm_send_event_locked(dev, &new_crtc_state->event->base);
8498
8499                 new_crtc_state->event = NULL;
8500         }
8501         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8502
8503         /* Signal HW programming completion */
8504         drm_atomic_helper_commit_hw_done(state);
8505
8506         if (wait_for_vblank)
8507                 drm_atomic_helper_wait_for_flip_done(dev, state);
8508
8509         drm_atomic_helper_cleanup_planes(dev, state);
8510
8511         /* return the stolen vga memory back to VRAM */
8512         if (!adev->mman.keep_stolen_vga_memory)
8513                 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
8514         amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
8515
8516         /*
8517          * Finally, drop a runtime PM reference for each newly disabled CRTC,
8518          * so we can put the GPU into runtime suspend if we're not driving any
8519          * displays anymore
8520          */
8521         for (i = 0; i < crtc_disable_count; i++)
8522                 pm_runtime_put_autosuspend(dev->dev);
8523         pm_runtime_mark_last_busy(dev->dev);
8524
8525         if (dc_state_temp)
8526                 dc_release_state(dc_state_temp);
8527 }
8528
8529 static int dm_force_atomic_commit(struct drm_connector *connector)
8530 {
8531         int ret = 0;
8532         struct drm_device *ddev = connector->dev;
8533         struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
8534         struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
8535         struct drm_plane *plane = disconnected_acrtc->base.primary;
8536         struct drm_connector_state *conn_state;
8537         struct drm_crtc_state *crtc_state;
8538         struct drm_plane_state *plane_state;
8539
8540         if (!state)
8541                 return -ENOMEM;
8542
8543         state->acquire_ctx = ddev->mode_config.acquire_ctx;
8544
8545         /* Construct an atomic state to restore previous display setting */
8546
8547         /*
8548          * Attach connectors to drm_atomic_state
8549          */
8550         conn_state = drm_atomic_get_connector_state(state, connector);
8551
8552         ret = PTR_ERR_OR_ZERO(conn_state);
8553         if (ret)
8554                 goto out;
8555
8556         /* Attach crtc to drm_atomic_state*/
8557         crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
8558
8559         ret = PTR_ERR_OR_ZERO(crtc_state);
8560         if (ret)
8561                 goto out;
8562
8563         /* force a restore */
8564         crtc_state->mode_changed = true;
8565
8566         /* Attach plane to drm_atomic_state */
8567         plane_state = drm_atomic_get_plane_state(state, plane);
8568
8569         ret = PTR_ERR_OR_ZERO(plane_state);
8570         if (ret)
8571                 goto out;
8572
8573         /* Call commit internally with the state we just constructed */
8574         ret = drm_atomic_commit(state);
8575
8576 out:
8577         drm_atomic_state_put(state);
8578         if (ret)
8579                 DRM_ERROR("Restoring old state failed with %i\n", ret);
8580
8581         return ret;
8582 }
8583
8584 /*
8585  * This function handles all cases when set mode does not come upon hotplug.
8586  * This includes when a display is unplugged then plugged back into the
8587  * same port and when running without usermode desktop manager supprot
8588  */
8589 void dm_restore_drm_connector_state(struct drm_device *dev,
8590                                     struct drm_connector *connector)
8591 {
8592         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8593         struct amdgpu_crtc *disconnected_acrtc;
8594         struct dm_crtc_state *acrtc_state;
8595
8596         if (!aconnector->dc_sink || !connector->state || !connector->encoder)
8597                 return;
8598
8599         disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
8600         if (!disconnected_acrtc)
8601                 return;
8602
8603         acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
8604         if (!acrtc_state->stream)
8605                 return;
8606
8607         /*
8608          * If the previous sink is not released and different from the current,
8609          * we deduce we are in a state where we can not rely on usermode call
8610          * to turn on the display, so we do it here
8611          */
8612         if (acrtc_state->stream->sink != aconnector->dc_sink)
8613                 dm_force_atomic_commit(&aconnector->base);
8614 }
8615
8616 /*
8617  * Grabs all modesetting locks to serialize against any blocking commits,
8618  * Waits for completion of all non blocking commits.
8619  */
8620 static int do_aquire_global_lock(struct drm_device *dev,
8621                                  struct drm_atomic_state *state)
8622 {
8623         struct drm_crtc *crtc;
8624         struct drm_crtc_commit *commit;
8625         long ret;
8626
8627         /*
8628          * Adding all modeset locks to aquire_ctx will
8629          * ensure that when the framework release it the
8630          * extra locks we are locking here will get released to
8631          */
8632         ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
8633         if (ret)
8634                 return ret;
8635
8636         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8637                 spin_lock(&crtc->commit_lock);
8638                 commit = list_first_entry_or_null(&crtc->commit_list,
8639                                 struct drm_crtc_commit, commit_entry);
8640                 if (commit)
8641                         drm_crtc_commit_get(commit);
8642                 spin_unlock(&crtc->commit_lock);
8643
8644                 if (!commit)
8645                         continue;
8646
8647                 /*
8648                  * Make sure all pending HW programming completed and
8649                  * page flips done
8650                  */
8651                 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
8652
8653                 if (ret > 0)
8654                         ret = wait_for_completion_interruptible_timeout(
8655                                         &commit->flip_done, 10*HZ);
8656
8657                 if (ret == 0)
8658                         DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
8659                                   "timed out\n", crtc->base.id, crtc->name);
8660
8661                 drm_crtc_commit_put(commit);
8662         }
8663
8664         return ret < 0 ? ret : 0;
8665 }
8666
8667 static void get_freesync_config_for_crtc(
8668         struct dm_crtc_state *new_crtc_state,
8669         struct dm_connector_state *new_con_state)
8670 {
8671         struct mod_freesync_config config = {0};
8672         struct amdgpu_dm_connector *aconnector =
8673                         to_amdgpu_dm_connector(new_con_state->base.connector);
8674         struct drm_display_mode *mode = &new_crtc_state->base.mode;
8675         int vrefresh = drm_mode_vrefresh(mode);
8676         bool fs_vid_mode = false;
8677
8678         new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
8679                                         vrefresh >= aconnector->min_vfreq &&
8680                                         vrefresh <= aconnector->max_vfreq;
8681
8682         if (new_crtc_state->vrr_supported) {
8683                 new_crtc_state->stream->ignore_msa_timing_param = true;
8684                 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
8685
8686                 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000;
8687                 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000;
8688                 config.vsif_supported = true;
8689                 config.btr = true;
8690
8691                 if (fs_vid_mode) {
8692                         config.state = VRR_STATE_ACTIVE_FIXED;
8693                         config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz;
8694                         goto out;
8695                 } else if (new_crtc_state->base.vrr_enabled) {
8696                         config.state = VRR_STATE_ACTIVE_VARIABLE;
8697                 } else {
8698                         config.state = VRR_STATE_INACTIVE;
8699                 }
8700         }
8701 out:
8702         new_crtc_state->freesync_config = config;
8703 }
8704
8705 static void reset_freesync_config_for_crtc(
8706         struct dm_crtc_state *new_crtc_state)
8707 {
8708         new_crtc_state->vrr_supported = false;
8709
8710         memset(&new_crtc_state->vrr_infopacket, 0,
8711                sizeof(new_crtc_state->vrr_infopacket));
8712 }
8713
8714 static bool
8715 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
8716                                  struct drm_crtc_state *new_crtc_state)
8717 {
8718         const struct drm_display_mode *old_mode, *new_mode;
8719
8720         if (!old_crtc_state || !new_crtc_state)
8721                 return false;
8722
8723         old_mode = &old_crtc_state->mode;
8724         new_mode = &new_crtc_state->mode;
8725
8726         if (old_mode->clock       == new_mode->clock &&
8727             old_mode->hdisplay    == new_mode->hdisplay &&
8728             old_mode->vdisplay    == new_mode->vdisplay &&
8729             old_mode->htotal      == new_mode->htotal &&
8730             old_mode->vtotal      != new_mode->vtotal &&
8731             old_mode->hsync_start == new_mode->hsync_start &&
8732             old_mode->vsync_start != new_mode->vsync_start &&
8733             old_mode->hsync_end   == new_mode->hsync_end &&
8734             old_mode->vsync_end   != new_mode->vsync_end &&
8735             old_mode->hskew       == new_mode->hskew &&
8736             old_mode->vscan       == new_mode->vscan &&
8737             (old_mode->vsync_end - old_mode->vsync_start) ==
8738             (new_mode->vsync_end - new_mode->vsync_start))
8739                 return true;
8740
8741         return false;
8742 }
8743
8744 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) {
8745         uint64_t num, den, res;
8746         struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
8747
8748         dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;
8749
8750         num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000;
8751         den = (unsigned long long)new_crtc_state->mode.htotal *
8752               (unsigned long long)new_crtc_state->mode.vtotal;
8753
8754         res = div_u64(num, den);
8755         dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
8756 }
8757
8758 static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
8759                          struct drm_atomic_state *state,
8760                          struct drm_crtc *crtc,
8761                          struct drm_crtc_state *old_crtc_state,
8762                          struct drm_crtc_state *new_crtc_state,
8763                          bool enable,
8764                          bool *lock_and_validation_needed)
8765 {
8766         struct dm_atomic_state *dm_state = NULL;
8767         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8768         struct dc_stream_state *new_stream;
8769         int ret = 0;
8770
8771         /*
8772          * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
8773          * update changed items
8774          */
8775         struct amdgpu_crtc *acrtc = NULL;
8776         struct amdgpu_dm_connector *aconnector = NULL;
8777         struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
8778         struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
8779
8780         new_stream = NULL;
8781
8782         dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8783         dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8784         acrtc = to_amdgpu_crtc(crtc);
8785         aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
8786
8787         /* TODO This hack should go away */
8788         if (aconnector && enable) {
8789                 /* Make sure fake sink is created in plug-in scenario */
8790                 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
8791                                                             &aconnector->base);
8792                 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
8793                                                             &aconnector->base);
8794
8795                 if (IS_ERR(drm_new_conn_state)) {
8796                         ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
8797                         goto fail;
8798                 }
8799
8800                 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
8801                 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
8802
8803                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8804                         goto skip_modeset;
8805
8806                 new_stream = create_validate_stream_for_sink(aconnector,
8807                                                              &new_crtc_state->mode,
8808                                                              dm_new_conn_state,
8809                                                              dm_old_crtc_state->stream);
8810
8811                 /*
8812                  * we can have no stream on ACTION_SET if a display
8813                  * was disconnected during S3, in this case it is not an
8814                  * error, the OS will be updated after detection, and
8815                  * will do the right thing on next atomic commit
8816                  */
8817
8818                 if (!new_stream) {
8819                         DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
8820                                         __func__, acrtc->base.base.id);
8821                         ret = -ENOMEM;
8822                         goto fail;
8823                 }
8824
8825                 /*
8826                  * TODO: Check VSDB bits to decide whether this should
8827                  * be enabled or not.
8828                  */
8829                 new_stream->triggered_crtc_reset.enabled =
8830                         dm->force_timing_sync;
8831
8832                 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
8833
8834                 ret = fill_hdr_info_packet(drm_new_conn_state,
8835                                            &new_stream->hdr_static_metadata);
8836                 if (ret)
8837                         goto fail;
8838
8839                 /*
8840                  * If we already removed the old stream from the context
8841                  * (and set the new stream to NULL) then we can't reuse
8842                  * the old stream even if the stream and scaling are unchanged.
8843                  * We'll hit the BUG_ON and black screen.
8844                  *
8845                  * TODO: Refactor this function to allow this check to work
8846                  * in all conditions.
8847                  */
8848                 if (amdgpu_freesync_vid_mode &&
8849                     dm_new_crtc_state->stream &&
8850                     is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))
8851                         goto skip_modeset;
8852
8853                 if (dm_new_crtc_state->stream &&
8854                     dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
8855                     dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
8856                         new_crtc_state->mode_changed = false;
8857                         DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
8858                                          new_crtc_state->mode_changed);
8859                 }
8860         }
8861
8862         /* mode_changed flag may get updated above, need to check again */
8863         if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8864                 goto skip_modeset;
8865
8866         drm_dbg_state(state->dev,
8867                 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
8868                 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
8869                 "connectors_changed:%d\n",
8870                 acrtc->crtc_id,
8871                 new_crtc_state->enable,
8872                 new_crtc_state->active,
8873                 new_crtc_state->planes_changed,
8874                 new_crtc_state->mode_changed,
8875                 new_crtc_state->active_changed,
8876                 new_crtc_state->connectors_changed);
8877
8878         /* Remove stream for any changed/disabled CRTC */
8879         if (!enable) {
8880
8881                 if (!dm_old_crtc_state->stream)
8882                         goto skip_modeset;
8883
8884                 if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream &&
8885                     is_timing_unchanged_for_freesync(new_crtc_state,
8886                                                      old_crtc_state)) {
8887                         new_crtc_state->mode_changed = false;
8888                         DRM_DEBUG_DRIVER(
8889                                 "Mode change not required for front porch change, "
8890                                 "setting mode_changed to %d",
8891                                 new_crtc_state->mode_changed);
8892
8893                         set_freesync_fixed_config(dm_new_crtc_state);
8894
8895                         goto skip_modeset;
8896                 } else if (amdgpu_freesync_vid_mode && aconnector &&
8897                            is_freesync_video_mode(&new_crtc_state->mode,
8898                                                   aconnector)) {
8899                         struct drm_display_mode *high_mode;
8900
8901                         high_mode = get_highest_refresh_rate_mode(aconnector, false);
8902                         if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) {
8903                                 set_freesync_fixed_config(dm_new_crtc_state);
8904                         }
8905                 }
8906
8907                 ret = dm_atomic_get_state(state, &dm_state);
8908                 if (ret)
8909                         goto fail;
8910
8911                 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
8912                                 crtc->base.id);
8913
8914                 /* i.e. reset mode */
8915                 if (dc_remove_stream_from_ctx(
8916                                 dm->dc,
8917                                 dm_state->context,
8918                                 dm_old_crtc_state->stream) != DC_OK) {
8919                         ret = -EINVAL;
8920                         goto fail;
8921                 }
8922
8923                 dc_stream_release(dm_old_crtc_state->stream);
8924                 dm_new_crtc_state->stream = NULL;
8925
8926                 reset_freesync_config_for_crtc(dm_new_crtc_state);
8927
8928                 *lock_and_validation_needed = true;
8929
8930         } else {/* Add stream for any updated/enabled CRTC */
8931                 /*
8932                  * Quick fix to prevent NULL pointer on new_stream when
8933                  * added MST connectors not found in existing crtc_state in the chained mode
8934                  * TODO: need to dig out the root cause of that
8935                  */
8936                 if (!aconnector)
8937                         goto skip_modeset;
8938
8939                 if (modereset_required(new_crtc_state))
8940                         goto skip_modeset;
8941
8942                 if (modeset_required(new_crtc_state, new_stream,
8943                                      dm_old_crtc_state->stream)) {
8944
8945                         WARN_ON(dm_new_crtc_state->stream);
8946
8947                         ret = dm_atomic_get_state(state, &dm_state);
8948                         if (ret)
8949                                 goto fail;
8950
8951                         dm_new_crtc_state->stream = new_stream;
8952
8953                         dc_stream_retain(new_stream);
8954
8955                         DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n",
8956                                          crtc->base.id);
8957
8958                         if (dc_add_stream_to_ctx(
8959                                         dm->dc,
8960                                         dm_state->context,
8961                                         dm_new_crtc_state->stream) != DC_OK) {
8962                                 ret = -EINVAL;
8963                                 goto fail;
8964                         }
8965
8966                         *lock_and_validation_needed = true;
8967                 }
8968         }
8969
8970 skip_modeset:
8971         /* Release extra reference */
8972         if (new_stream)
8973                  dc_stream_release(new_stream);
8974
8975         /*
8976          * We want to do dc stream updates that do not require a
8977          * full modeset below.
8978          */
8979         if (!(enable && aconnector && new_crtc_state->active))
8980                 return 0;
8981         /*
8982          * Given above conditions, the dc state cannot be NULL because:
8983          * 1. We're in the process of enabling CRTCs (just been added
8984          *    to the dc context, or already is on the context)
8985          * 2. Has a valid connector attached, and
8986          * 3. Is currently active and enabled.
8987          * => The dc stream state currently exists.
8988          */
8989         BUG_ON(dm_new_crtc_state->stream == NULL);
8990
8991         /* Scaling or underscan settings */
8992         if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) ||
8993                                 drm_atomic_crtc_needs_modeset(new_crtc_state))
8994                 update_stream_scaling_settings(
8995                         &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
8996
8997         /* ABM settings */
8998         dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
8999
9000         /*
9001          * Color management settings. We also update color properties
9002          * when a modeset is needed, to ensure it gets reprogrammed.
9003          */
9004         if (dm_new_crtc_state->base.color_mgmt_changed ||
9005             drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9006                 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
9007                 if (ret)
9008                         goto fail;
9009         }
9010
9011         /* Update Freesync settings. */
9012         get_freesync_config_for_crtc(dm_new_crtc_state,
9013                                      dm_new_conn_state);
9014
9015         return ret;
9016
9017 fail:
9018         if (new_stream)
9019                 dc_stream_release(new_stream);
9020         return ret;
9021 }
9022
9023 static bool should_reset_plane(struct drm_atomic_state *state,
9024                                struct drm_plane *plane,
9025                                struct drm_plane_state *old_plane_state,
9026                                struct drm_plane_state *new_plane_state)
9027 {
9028         struct drm_plane *other;
9029         struct drm_plane_state *old_other_state, *new_other_state;
9030         struct drm_crtc_state *new_crtc_state;
9031         int i;
9032
9033         /*
9034          * TODO: Remove this hack once the checks below are sufficient
9035          * enough to determine when we need to reset all the planes on
9036          * the stream.
9037          */
9038         if (state->allow_modeset)
9039                 return true;
9040
9041         /* Exit early if we know that we're adding or removing the plane. */
9042         if (old_plane_state->crtc != new_plane_state->crtc)
9043                 return true;
9044
9045         /* old crtc == new_crtc == NULL, plane not in context. */
9046         if (!new_plane_state->crtc)
9047                 return false;
9048
9049         new_crtc_state =
9050                 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
9051
9052         if (!new_crtc_state)
9053                 return true;
9054
9055         /* CRTC Degamma changes currently require us to recreate planes. */
9056         if (new_crtc_state->color_mgmt_changed)
9057                 return true;
9058
9059         if (drm_atomic_crtc_needs_modeset(new_crtc_state))
9060                 return true;
9061
9062         /*
9063          * If there are any new primary or overlay planes being added or
9064          * removed then the z-order can potentially change. To ensure
9065          * correct z-order and pipe acquisition the current DC architecture
9066          * requires us to remove and recreate all existing planes.
9067          *
9068          * TODO: Come up with a more elegant solution for this.
9069          */
9070         for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
9071                 struct amdgpu_framebuffer *old_afb, *new_afb;
9072                 if (other->type == DRM_PLANE_TYPE_CURSOR)
9073                         continue;
9074
9075                 if (old_other_state->crtc != new_plane_state->crtc &&
9076                     new_other_state->crtc != new_plane_state->crtc)
9077                         continue;
9078
9079                 if (old_other_state->crtc != new_other_state->crtc)
9080                         return true;
9081
9082                 /* Src/dst size and scaling updates. */
9083                 if (old_other_state->src_w != new_other_state->src_w ||
9084                     old_other_state->src_h != new_other_state->src_h ||
9085                     old_other_state->crtc_w != new_other_state->crtc_w ||
9086                     old_other_state->crtc_h != new_other_state->crtc_h)
9087                         return true;
9088
9089                 /* Rotation / mirroring updates. */
9090                 if (old_other_state->rotation != new_other_state->rotation)
9091                         return true;
9092
9093                 /* Blending updates. */
9094                 if (old_other_state->pixel_blend_mode !=
9095                     new_other_state->pixel_blend_mode)
9096                         return true;
9097
9098                 /* Alpha updates. */
9099                 if (old_other_state->alpha != new_other_state->alpha)
9100                         return true;
9101
9102                 /* Colorspace changes. */
9103                 if (old_other_state->color_range != new_other_state->color_range ||
9104                     old_other_state->color_encoding != new_other_state->color_encoding)
9105                         return true;
9106
9107                 /* Framebuffer checks fall at the end. */
9108                 if (!old_other_state->fb || !new_other_state->fb)
9109                         continue;
9110
9111                 /* Pixel format changes can require bandwidth updates. */
9112                 if (old_other_state->fb->format != new_other_state->fb->format)
9113                         return true;
9114
9115                 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb;
9116                 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb;
9117
9118                 /* Tiling and DCC changes also require bandwidth updates. */
9119                 if (old_afb->tiling_flags != new_afb->tiling_flags ||
9120                     old_afb->base.modifier != new_afb->base.modifier)
9121                         return true;
9122         }
9123
9124         return false;
9125 }
9126
9127 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,
9128                               struct drm_plane_state *new_plane_state,
9129                               struct drm_framebuffer *fb)
9130 {
9131         struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev);
9132         struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
9133         unsigned int pitch;
9134         bool linear;
9135
9136         if (fb->width > new_acrtc->max_cursor_width ||
9137             fb->height > new_acrtc->max_cursor_height) {
9138                 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n",
9139                                  new_plane_state->fb->width,
9140                                  new_plane_state->fb->height);
9141                 return -EINVAL;
9142         }
9143         if (new_plane_state->src_w != fb->width << 16 ||
9144             new_plane_state->src_h != fb->height << 16) {
9145                 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9146                 return -EINVAL;
9147         }
9148
9149         /* Pitch in pixels */
9150         pitch = fb->pitches[0] / fb->format->cpp[0];
9151
9152         if (fb->width != pitch) {
9153                 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d",
9154                                  fb->width, pitch);
9155                 return -EINVAL;
9156         }
9157
9158         switch (pitch) {
9159         case 64:
9160         case 128:
9161         case 256:
9162                 /* FB pitch is supported by cursor plane */
9163                 break;
9164         default:
9165                 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch);
9166                 return -EINVAL;
9167         }
9168
9169         /* Core DRM takes care of checking FB modifiers, so we only need to
9170          * check tiling flags when the FB doesn't have a modifier. */
9171         if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) {
9172                 if (adev->family < AMDGPU_FAMILY_AI) {
9173                         linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &&
9174                                  AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &&
9175                                  AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0;
9176                 } else {
9177                         linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;
9178                 }
9179                 if (!linear) {
9180                         DRM_DEBUG_ATOMIC("Cursor FB not linear");
9181                         return -EINVAL;
9182                 }
9183         }
9184
9185         return 0;
9186 }
9187
9188 static int dm_update_plane_state(struct dc *dc,
9189                                  struct drm_atomic_state *state,
9190                                  struct drm_plane *plane,
9191                                  struct drm_plane_state *old_plane_state,
9192                                  struct drm_plane_state *new_plane_state,
9193                                  bool enable,
9194                                  bool *lock_and_validation_needed)
9195 {
9196
9197         struct dm_atomic_state *dm_state = NULL;
9198         struct drm_crtc *new_plane_crtc, *old_plane_crtc;
9199         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9200         struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
9201         struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
9202         struct amdgpu_crtc *new_acrtc;
9203         bool needs_reset;
9204         int ret = 0;
9205
9206
9207         new_plane_crtc = new_plane_state->crtc;
9208         old_plane_crtc = old_plane_state->crtc;
9209         dm_new_plane_state = to_dm_plane_state(new_plane_state);
9210         dm_old_plane_state = to_dm_plane_state(old_plane_state);
9211
9212         if (plane->type == DRM_PLANE_TYPE_CURSOR) {
9213                 if (!enable || !new_plane_crtc ||
9214                         drm_atomic_plane_disabling(plane->state, new_plane_state))
9215                         return 0;
9216
9217                 new_acrtc = to_amdgpu_crtc(new_plane_crtc);
9218
9219                 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) {
9220                         DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9221                         return -EINVAL;
9222                 }
9223
9224                 if (new_plane_state->fb) {
9225                         ret = dm_check_cursor_fb(new_acrtc, new_plane_state,
9226                                                  new_plane_state->fb);
9227                         if (ret)
9228                                 return ret;
9229                 }
9230
9231                 return 0;
9232         }
9233
9234         needs_reset = should_reset_plane(state, plane, old_plane_state,
9235                                          new_plane_state);
9236
9237         /* Remove any changed/removed planes */
9238         if (!enable) {
9239                 if (!needs_reset)
9240                         return 0;
9241
9242                 if (!old_plane_crtc)
9243                         return 0;
9244
9245                 old_crtc_state = drm_atomic_get_old_crtc_state(
9246                                 state, old_plane_crtc);
9247                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9248
9249                 if (!dm_old_crtc_state->stream)
9250                         return 0;
9251
9252                 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
9253                                 plane->base.id, old_plane_crtc->base.id);
9254
9255                 ret = dm_atomic_get_state(state, &dm_state);
9256                 if (ret)
9257                         return ret;
9258
9259                 if (!dc_remove_plane_from_context(
9260                                 dc,
9261                                 dm_old_crtc_state->stream,
9262                                 dm_old_plane_state->dc_state,
9263                                 dm_state->context)) {
9264
9265                         return -EINVAL;
9266                 }
9267
9268
9269                 dc_plane_state_release(dm_old_plane_state->dc_state);
9270                 dm_new_plane_state->dc_state = NULL;
9271
9272                 *lock_and_validation_needed = true;
9273
9274         } else { /* Add new planes */
9275                 struct dc_plane_state *dc_new_plane_state;
9276
9277                 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
9278                         return 0;
9279
9280                 if (!new_plane_crtc)
9281                         return 0;
9282
9283                 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
9284                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9285
9286                 if (!dm_new_crtc_state->stream)
9287                         return 0;
9288
9289                 if (!needs_reset)
9290                         return 0;
9291
9292                 ret = dm_plane_helper_check_state(new_plane_state, new_crtc_state);
9293                 if (ret)
9294                         return ret;
9295
9296                 WARN_ON(dm_new_plane_state->dc_state);
9297
9298                 dc_new_plane_state = dc_create_plane_state(dc);
9299                 if (!dc_new_plane_state)
9300                         return -ENOMEM;
9301
9302                 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n",
9303                                  plane->base.id, new_plane_crtc->base.id);
9304
9305                 ret = fill_dc_plane_attributes(
9306                         drm_to_adev(new_plane_crtc->dev),
9307                         dc_new_plane_state,
9308                         new_plane_state,
9309                         new_crtc_state);
9310                 if (ret) {
9311                         dc_plane_state_release(dc_new_plane_state);
9312                         return ret;
9313                 }
9314
9315                 ret = dm_atomic_get_state(state, &dm_state);
9316                 if (ret) {
9317                         dc_plane_state_release(dc_new_plane_state);
9318                         return ret;
9319                 }
9320
9321                 /*
9322                  * Any atomic check errors that occur after this will
9323                  * not need a release. The plane state will be attached
9324                  * to the stream, and therefore part of the atomic
9325                  * state. It'll be released when the atomic state is
9326                  * cleaned.
9327                  */
9328                 if (!dc_add_plane_to_context(
9329                                 dc,
9330                                 dm_new_crtc_state->stream,
9331                                 dc_new_plane_state,
9332                                 dm_state->context)) {
9333
9334                         dc_plane_state_release(dc_new_plane_state);
9335                         return -EINVAL;
9336                 }
9337
9338                 dm_new_plane_state->dc_state = dc_new_plane_state;
9339
9340                 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY);
9341
9342                 /* Tell DC to do a full surface update every time there
9343                  * is a plane change. Inefficient, but works for now.
9344                  */
9345                 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
9346
9347                 *lock_and_validation_needed = true;
9348         }
9349
9350
9351         return ret;
9352 }
9353
9354 static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state,
9355                                        int *src_w, int *src_h)
9356 {
9357         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
9358         case DRM_MODE_ROTATE_90:
9359         case DRM_MODE_ROTATE_270:
9360                 *src_w = plane_state->src_h >> 16;
9361                 *src_h = plane_state->src_w >> 16;
9362                 break;
9363         case DRM_MODE_ROTATE_0:
9364         case DRM_MODE_ROTATE_180:
9365         default:
9366                 *src_w = plane_state->src_w >> 16;
9367                 *src_h = plane_state->src_h >> 16;
9368                 break;
9369         }
9370 }
9371
9372 static int dm_check_crtc_cursor(struct drm_atomic_state *state,
9373                                 struct drm_crtc *crtc,
9374                                 struct drm_crtc_state *new_crtc_state)
9375 {
9376         struct drm_plane *cursor = crtc->cursor, *underlying;
9377         struct drm_plane_state *new_cursor_state, *new_underlying_state;
9378         int i;
9379         int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h;
9380         int cursor_src_w, cursor_src_h;
9381         int underlying_src_w, underlying_src_h;
9382
9383         /* On DCE and DCN there is no dedicated hardware cursor plane. We get a
9384          * cursor per pipe but it's going to inherit the scaling and
9385          * positioning from the underlying pipe. Check the cursor plane's
9386          * blending properties match the underlying planes'. */
9387
9388         new_cursor_state = drm_atomic_get_new_plane_state(state, cursor);
9389         if (!new_cursor_state || !new_cursor_state->fb) {
9390                 return 0;
9391         }
9392
9393         dm_get_oriented_plane_size(new_cursor_state, &cursor_src_w, &cursor_src_h);
9394         cursor_scale_w = new_cursor_state->crtc_w * 1000 / cursor_src_w;
9395         cursor_scale_h = new_cursor_state->crtc_h * 1000 / cursor_src_h;
9396
9397         for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) {
9398                 /* Narrow down to non-cursor planes on the same CRTC as the cursor */
9399                 if (new_underlying_state->crtc != crtc || underlying == crtc->cursor)
9400                         continue;
9401
9402                 /* Ignore disabled planes */
9403                 if (!new_underlying_state->fb)
9404                         continue;
9405
9406                 dm_get_oriented_plane_size(new_underlying_state,
9407                                            &underlying_src_w, &underlying_src_h);
9408                 underlying_scale_w = new_underlying_state->crtc_w * 1000 / underlying_src_w;
9409                 underlying_scale_h = new_underlying_state->crtc_h * 1000 / underlying_src_h;
9410
9411                 if (cursor_scale_w != underlying_scale_w ||
9412                     cursor_scale_h != underlying_scale_h) {
9413                         drm_dbg_atomic(crtc->dev,
9414                                        "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n",
9415                                        cursor->base.id, cursor->name, underlying->base.id, underlying->name);
9416                         return -EINVAL;
9417                 }
9418
9419                 /* If this plane covers the whole CRTC, no need to check planes underneath */
9420                 if (new_underlying_state->crtc_x <= 0 &&
9421                     new_underlying_state->crtc_y <= 0 &&
9422                     new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay &&
9423                     new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay)
9424                         break;
9425         }
9426
9427         return 0;
9428 }
9429
9430 #if defined(CONFIG_DRM_AMD_DC_DCN)
9431 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
9432 {
9433         struct drm_connector *connector;
9434         struct drm_connector_state *conn_state, *old_conn_state;
9435         struct amdgpu_dm_connector *aconnector = NULL;
9436         int i;
9437         for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) {
9438                 if (!conn_state->crtc)
9439                         conn_state = old_conn_state;
9440
9441                 if (conn_state->crtc != crtc)
9442                         continue;
9443
9444                 aconnector = to_amdgpu_dm_connector(connector);
9445                 if (!aconnector->port || !aconnector->mst_port)
9446                         aconnector = NULL;
9447                 else
9448                         break;
9449         }
9450
9451         if (!aconnector)
9452                 return 0;
9453
9454         return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_port->mst_mgr);
9455 }
9456 #endif
9457
9458 /**
9459  * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
9460  *
9461  * @dev: The DRM device
9462  * @state: The atomic state to commit
9463  *
9464  * Validate that the given atomic state is programmable by DC into hardware.
9465  * This involves constructing a &struct dc_state reflecting the new hardware
9466  * state we wish to commit, then querying DC to see if it is programmable. It's
9467  * important not to modify the existing DC state. Otherwise, atomic_check
9468  * may unexpectedly commit hardware changes.
9469  *
9470  * When validating the DC state, it's important that the right locks are
9471  * acquired. For full updates case which removes/adds/updates streams on one
9472  * CRTC while flipping on another CRTC, acquiring global lock will guarantee
9473  * that any such full update commit will wait for completion of any outstanding
9474  * flip using DRMs synchronization events.
9475  *
9476  * Note that DM adds the affected connectors for all CRTCs in state, when that
9477  * might not seem necessary. This is because DC stream creation requires the
9478  * DC sink, which is tied to the DRM connector state. Cleaning this up should
9479  * be possible but non-trivial - a possible TODO item.
9480  *
9481  * Return: -Error code if validation failed.
9482  */
9483 static int amdgpu_dm_atomic_check(struct drm_device *dev,
9484                                   struct drm_atomic_state *state)
9485 {
9486         struct amdgpu_device *adev = drm_to_adev(dev);
9487         struct dm_atomic_state *dm_state = NULL;
9488         struct dc *dc = adev->dm.dc;
9489         struct drm_connector *connector;
9490         struct drm_connector_state *old_con_state, *new_con_state;
9491         struct drm_crtc *crtc;
9492         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9493         struct drm_plane *plane;
9494         struct drm_plane_state *old_plane_state, *new_plane_state;
9495         enum dc_status status;
9496         int ret, i;
9497         bool lock_and_validation_needed = false;
9498         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9499 #if defined(CONFIG_DRM_AMD_DC_DCN)
9500         struct dsc_mst_fairness_vars vars[MAX_PIPES];
9501 #endif
9502
9503         trace_amdgpu_dm_atomic_check_begin(state);
9504
9505         ret = drm_atomic_helper_check_modeset(dev, state);
9506         if (ret) {
9507                 DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n");
9508                 goto fail;
9509         }
9510
9511         /* Check connector changes */
9512         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9513                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
9514                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9515
9516                 /* Skip connectors that are disabled or part of modeset already. */
9517                 if (!new_con_state->crtc)
9518                         continue;
9519
9520                 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc);
9521                 if (IS_ERR(new_crtc_state)) {
9522                         DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n");
9523                         ret = PTR_ERR(new_crtc_state);
9524                         goto fail;
9525                 }
9526
9527                 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level ||
9528                     dm_old_con_state->scaling != dm_new_con_state->scaling)
9529                         new_crtc_state->connectors_changed = true;
9530         }
9531
9532 #if defined(CONFIG_DRM_AMD_DC_DCN)
9533         if (dc_resource_is_dsc_encoding_supported(dc)) {
9534                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9535                         if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9536                                 ret = add_affected_mst_dsc_crtcs(state, crtc);
9537                                 if (ret) {
9538                                         DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n");
9539                                         goto fail;
9540                                 }
9541                         }
9542                 }
9543         }
9544 #endif
9545         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9546                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9547
9548                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
9549                     !new_crtc_state->color_mgmt_changed &&
9550                     old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled &&
9551                         dm_old_crtc_state->dsc_force_changed == false)
9552                         continue;
9553
9554                 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state);
9555                 if (ret) {
9556                         DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n");
9557                         goto fail;
9558                 }
9559
9560                 if (!new_crtc_state->enable)
9561                         continue;
9562
9563                 ret = drm_atomic_add_affected_connectors(state, crtc);
9564                 if (ret) {
9565                         DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n");
9566                         goto fail;
9567                 }
9568
9569                 ret = drm_atomic_add_affected_planes(state, crtc);
9570                 if (ret) {
9571                         DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n");
9572                         goto fail;
9573                 }
9574
9575                 if (dm_old_crtc_state->dsc_force_changed)
9576                         new_crtc_state->mode_changed = true;
9577         }
9578
9579         /*
9580          * Add all primary and overlay planes on the CRTC to the state
9581          * whenever a plane is enabled to maintain correct z-ordering
9582          * and to enable fast surface updates.
9583          */
9584         drm_for_each_crtc(crtc, dev) {
9585                 bool modified = false;
9586
9587                 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
9588                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
9589                                 continue;
9590
9591                         if (new_plane_state->crtc == crtc ||
9592                             old_plane_state->crtc == crtc) {
9593                                 modified = true;
9594                                 break;
9595                         }
9596                 }
9597
9598                 if (!modified)
9599                         continue;
9600
9601                 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
9602                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
9603                                 continue;
9604
9605                         new_plane_state =
9606                                 drm_atomic_get_plane_state(state, plane);
9607
9608                         if (IS_ERR(new_plane_state)) {
9609                                 ret = PTR_ERR(new_plane_state);
9610                                 DRM_DEBUG_DRIVER("new_plane_state is BAD\n");
9611                                 goto fail;
9612                         }
9613                 }
9614         }
9615
9616         /*
9617          * DC consults the zpos (layer_index in DC terminology) to determine the
9618          * hw plane on which to enable the hw cursor (see
9619          * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in
9620          * atomic state, so call drm helper to normalize zpos.
9621          */
9622         drm_atomic_normalize_zpos(dev, state);
9623
9624         /* Remove exiting planes if they are modified */
9625         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
9626                 ret = dm_update_plane_state(dc, state, plane,
9627                                             old_plane_state,
9628                                             new_plane_state,
9629                                             false,
9630                                             &lock_and_validation_needed);
9631                 if (ret) {
9632                         DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
9633                         goto fail;
9634                 }
9635         }
9636
9637         /* Disable all crtcs which require disable */
9638         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9639                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
9640                                            old_crtc_state,
9641                                            new_crtc_state,
9642                                            false,
9643                                            &lock_and_validation_needed);
9644                 if (ret) {
9645                         DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n");
9646                         goto fail;
9647                 }
9648         }
9649
9650         /* Enable all crtcs which require enable */
9651         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9652                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
9653                                            old_crtc_state,
9654                                            new_crtc_state,
9655                                            true,
9656                                            &lock_and_validation_needed);
9657                 if (ret) {
9658                         DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n");
9659                         goto fail;
9660                 }
9661         }
9662
9663         /* Add new/modified planes */
9664         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
9665                 ret = dm_update_plane_state(dc, state, plane,
9666                                             old_plane_state,
9667                                             new_plane_state,
9668                                             true,
9669                                             &lock_and_validation_needed);
9670                 if (ret) {
9671                         DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
9672                         goto fail;
9673                 }
9674         }
9675
9676 #if defined(CONFIG_DRM_AMD_DC_DCN)
9677         if (dc_resource_is_dsc_encoding_supported(dc)) {
9678                 ret = pre_validate_dsc(state, &dm_state, vars);
9679                 if (ret != 0)
9680                         goto fail;
9681         }
9682 #endif
9683
9684         /* Run this here since we want to validate the streams we created */
9685         ret = drm_atomic_helper_check_planes(dev, state);
9686         if (ret) {
9687                 DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n");
9688                 goto fail;
9689         }
9690
9691         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
9692                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9693                 if (dm_new_crtc_state->mpo_requested)
9694                         DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc);
9695         }
9696
9697         /* Check cursor planes scaling */
9698         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
9699                 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state);
9700                 if (ret) {
9701                         DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n");
9702                         goto fail;
9703                 }
9704         }
9705
9706         if (state->legacy_cursor_update) {
9707                 /*
9708                  * This is a fast cursor update coming from the plane update
9709                  * helper, check if it can be done asynchronously for better
9710                  * performance.
9711                  */
9712                 state->async_update =
9713                         !drm_atomic_helper_async_check(dev, state);
9714
9715                 /*
9716                  * Skip the remaining global validation if this is an async
9717                  * update. Cursor updates can be done without affecting
9718                  * state or bandwidth calcs and this avoids the performance
9719                  * penalty of locking the private state object and
9720                  * allocating a new dc_state.
9721                  */
9722                 if (state->async_update)
9723                         return 0;
9724         }
9725
9726         /* Check scaling and underscan changes*/
9727         /* TODO Removed scaling changes validation due to inability to commit
9728          * new stream into context w\o causing full reset. Need to
9729          * decide how to handle.
9730          */
9731         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9732                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
9733                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9734                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
9735
9736                 /* Skip any modesets/resets */
9737                 if (!acrtc || drm_atomic_crtc_needs_modeset(
9738                                 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
9739                         continue;
9740
9741                 /* Skip any thing not scale or underscan changes */
9742                 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
9743                         continue;
9744
9745                 lock_and_validation_needed = true;
9746         }
9747
9748         /**
9749          * Streams and planes are reset when there are changes that affect
9750          * bandwidth. Anything that affects bandwidth needs to go through
9751          * DC global validation to ensure that the configuration can be applied
9752          * to hardware.
9753          *
9754          * We have to currently stall out here in atomic_check for outstanding
9755          * commits to finish in this case because our IRQ handlers reference
9756          * DRM state directly - we can end up disabling interrupts too early
9757          * if we don't.
9758          *
9759          * TODO: Remove this stall and drop DM state private objects.
9760          */
9761         if (lock_and_validation_needed) {
9762                 ret = dm_atomic_get_state(state, &dm_state);
9763                 if (ret) {
9764                         DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n");
9765                         goto fail;
9766                 }
9767
9768                 ret = do_aquire_global_lock(dev, state);
9769                 if (ret) {
9770                         DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n");
9771                         goto fail;
9772                 }
9773
9774 #if defined(CONFIG_DRM_AMD_DC_DCN)
9775                 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars);
9776                 if (ret) {
9777                         DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n");
9778                         goto fail;
9779                 }
9780
9781                 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars);
9782                 if (ret) {
9783                         DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n");
9784                         goto fail;
9785                 }
9786 #endif
9787
9788                 /*
9789                  * Perform validation of MST topology in the state:
9790                  * We need to perform MST atomic check before calling
9791                  * dc_validate_global_state(), or there is a chance
9792                  * to get stuck in an infinite loop and hang eventually.
9793                  */
9794                 ret = drm_dp_mst_atomic_check(state);
9795                 if (ret) {
9796                         DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n");
9797                         goto fail;
9798                 }
9799                 status = dc_validate_global_state(dc, dm_state->context, true);
9800                 if (status != DC_OK) {
9801                         DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)",
9802                                        dc_status_to_str(status), status);
9803                         ret = -EINVAL;
9804                         goto fail;
9805                 }
9806         } else {
9807                 /*
9808                  * The commit is a fast update. Fast updates shouldn't change
9809                  * the DC context, affect global validation, and can have their
9810                  * commit work done in parallel with other commits not touching
9811                  * the same resource. If we have a new DC context as part of
9812                  * the DM atomic state from validation we need to free it and
9813                  * retain the existing one instead.
9814                  *
9815                  * Furthermore, since the DM atomic state only contains the DC
9816                  * context and can safely be annulled, we can free the state
9817                  * and clear the associated private object now to free
9818                  * some memory and avoid a possible use-after-free later.
9819                  */
9820
9821                 for (i = 0; i < state->num_private_objs; i++) {
9822                         struct drm_private_obj *obj = state->private_objs[i].ptr;
9823
9824                         if (obj->funcs == adev->dm.atomic_obj.funcs) {
9825                                 int j = state->num_private_objs-1;
9826
9827                                 dm_atomic_destroy_state(obj,
9828                                                 state->private_objs[i].state);
9829
9830                                 /* If i is not at the end of the array then the
9831                                  * last element needs to be moved to where i was
9832                                  * before the array can safely be truncated.
9833                                  */
9834                                 if (i != j)
9835                                         state->private_objs[i] =
9836                                                 state->private_objs[j];
9837
9838                                 state->private_objs[j].ptr = NULL;
9839                                 state->private_objs[j].state = NULL;
9840                                 state->private_objs[j].old_state = NULL;
9841                                 state->private_objs[j].new_state = NULL;
9842
9843                                 state->num_private_objs = j;
9844                                 break;
9845                         }
9846                 }
9847         }
9848
9849         /* Store the overall update type for use later in atomic check. */
9850         for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
9851                 struct dm_crtc_state *dm_new_crtc_state =
9852                         to_dm_crtc_state(new_crtc_state);
9853
9854                 dm_new_crtc_state->update_type = lock_and_validation_needed ?
9855                                                          UPDATE_TYPE_FULL :
9856                                                          UPDATE_TYPE_FAST;
9857         }
9858
9859         /* Must be success */
9860         WARN_ON(ret);
9861
9862         trace_amdgpu_dm_atomic_check_finish(state, ret);
9863
9864         return ret;
9865
9866 fail:
9867         if (ret == -EDEADLK)
9868                 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
9869         else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
9870                 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
9871         else
9872                 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
9873
9874         trace_amdgpu_dm_atomic_check_finish(state, ret);
9875
9876         return ret;
9877 }
9878
9879 static bool is_dp_capable_without_timing_msa(struct dc *dc,
9880                                              struct amdgpu_dm_connector *amdgpu_dm_connector)
9881 {
9882         uint8_t dpcd_data;
9883         bool capable = false;
9884
9885         if (amdgpu_dm_connector->dc_link &&
9886                 dm_helpers_dp_read_dpcd(
9887                                 NULL,
9888                                 amdgpu_dm_connector->dc_link,
9889                                 DP_DOWN_STREAM_PORT_COUNT,
9890                                 &dpcd_data,
9891                                 sizeof(dpcd_data))) {
9892                 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
9893         }
9894
9895         return capable;
9896 }
9897
9898 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,
9899                 unsigned int offset,
9900                 unsigned int total_length,
9901                 uint8_t *data,
9902                 unsigned int length,
9903                 struct amdgpu_hdmi_vsdb_info *vsdb)
9904 {
9905         bool res;
9906         union dmub_rb_cmd cmd;
9907         struct dmub_cmd_send_edid_cea *input;
9908         struct dmub_cmd_edid_cea_output *output;
9909
9910         if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES)
9911                 return false;
9912
9913         memset(&cmd, 0, sizeof(cmd));
9914
9915         input = &cmd.edid_cea.data.input;
9916
9917         cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA;
9918         cmd.edid_cea.header.sub_type = 0;
9919         cmd.edid_cea.header.payload_bytes =
9920                 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header);
9921         input->offset = offset;
9922         input->length = length;
9923         input->cea_total_length = total_length;
9924         memcpy(input->payload, data, length);
9925
9926         res = dc_dmub_srv_cmd_with_reply_data(dm->dc->ctx->dmub_srv, &cmd);
9927         if (!res) {
9928                 DRM_ERROR("EDID CEA parser failed\n");
9929                 return false;
9930         }
9931
9932         output = &cmd.edid_cea.data.output;
9933
9934         if (output->type == DMUB_CMD__EDID_CEA_ACK) {
9935                 if (!output->ack.success) {
9936                         DRM_ERROR("EDID CEA ack failed at offset %d\n",
9937                                         output->ack.offset);
9938                 }
9939         } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) {
9940                 if (!output->amd_vsdb.vsdb_found)
9941                         return false;
9942
9943                 vsdb->freesync_supported = output->amd_vsdb.freesync_supported;
9944                 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version;
9945                 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate;
9946                 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate;
9947         } else {
9948                 DRM_WARN("Unknown EDID CEA parser results\n");
9949                 return false;
9950         }
9951
9952         return true;
9953 }
9954
9955 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm,
9956                 uint8_t *edid_ext, int len,
9957                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
9958 {
9959         int i;
9960
9961         /* send extension block to DMCU for parsing */
9962         for (i = 0; i < len; i += 8) {
9963                 bool res;
9964                 int offset;
9965
9966                 /* send 8 bytes a time */
9967                 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8))
9968                         return false;
9969
9970                 if (i+8 == len) {
9971                         /* EDID block sent completed, expect result */
9972                         int version, min_rate, max_rate;
9973
9974                         res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate);
9975                         if (res) {
9976                                 /* amd vsdb found */
9977                                 vsdb_info->freesync_supported = 1;
9978                                 vsdb_info->amd_vsdb_version = version;
9979                                 vsdb_info->min_refresh_rate_hz = min_rate;
9980                                 vsdb_info->max_refresh_rate_hz = max_rate;
9981                                 return true;
9982                         }
9983                         /* not amd vsdb */
9984                         return false;
9985                 }
9986
9987                 /* check for ack*/
9988                 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset);
9989                 if (!res)
9990                         return false;
9991         }
9992
9993         return false;
9994 }
9995
9996 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm,
9997                 uint8_t *edid_ext, int len,
9998                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
9999 {
10000         int i;
10001
10002         /* send extension block to DMCU for parsing */
10003         for (i = 0; i < len; i += 8) {
10004                 /* send 8 bytes a time */
10005                 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info))
10006                         return false;
10007         }
10008
10009         return vsdb_info->freesync_supported;
10010 }
10011
10012 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
10013                 uint8_t *edid_ext, int len,
10014                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10015 {
10016         struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
10017
10018         if (adev->dm.dmub_srv)
10019                 return parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info);
10020         else
10021                 return parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info);
10022 }
10023
10024 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
10025                 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
10026 {
10027         uint8_t *edid_ext = NULL;
10028         int i;
10029         bool valid_vsdb_found = false;
10030
10031         /*----- drm_find_cea_extension() -----*/
10032         /* No EDID or EDID extensions */
10033         if (edid == NULL || edid->extensions == 0)
10034                 return -ENODEV;
10035
10036         /* Find CEA extension */
10037         for (i = 0; i < edid->extensions; i++) {
10038                 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1);
10039                 if (edid_ext[0] == CEA_EXT)
10040                         break;
10041         }
10042
10043         if (i == edid->extensions)
10044                 return -ENODEV;
10045
10046         /*----- cea_db_offsets() -----*/
10047         if (edid_ext[0] != CEA_EXT)
10048                 return -ENODEV;
10049
10050         valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info);
10051
10052         return valid_vsdb_found ? i : -ENODEV;
10053 }
10054
10055 /**
10056  * amdgpu_dm_update_freesync_caps - Update Freesync capabilities
10057  *
10058  * @connector: Connector to query.
10059  * @edid: EDID from monitor
10060  *
10061  * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep
10062  * track of some of the display information in the internal data struct used by
10063  * amdgpu_dm. This function checks which type of connector we need to set the
10064  * FreeSync parameters.
10065  */
10066 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
10067                                     struct edid *edid)
10068 {
10069         int i = 0;
10070         struct detailed_timing *timing;
10071         struct detailed_non_pixel *data;
10072         struct detailed_data_monitor_range *range;
10073         struct amdgpu_dm_connector *amdgpu_dm_connector =
10074                         to_amdgpu_dm_connector(connector);
10075         struct dm_connector_state *dm_con_state = NULL;
10076         struct dc_sink *sink;
10077
10078         struct drm_device *dev = connector->dev;
10079         struct amdgpu_device *adev = drm_to_adev(dev);
10080         struct amdgpu_hdmi_vsdb_info vsdb_info = {0};
10081         bool freesync_capable = false;
10082
10083         if (!connector->state) {
10084                 DRM_ERROR("%s - Connector has no state", __func__);
10085                 goto update;
10086         }
10087
10088         sink = amdgpu_dm_connector->dc_sink ?
10089                 amdgpu_dm_connector->dc_sink :
10090                 amdgpu_dm_connector->dc_em_sink;
10091
10092         if (!edid || !sink) {
10093                 dm_con_state = to_dm_connector_state(connector->state);
10094
10095                 amdgpu_dm_connector->min_vfreq = 0;
10096                 amdgpu_dm_connector->max_vfreq = 0;
10097                 amdgpu_dm_connector->pixel_clock_mhz = 0;
10098                 connector->display_info.monitor_range.min_vfreq = 0;
10099                 connector->display_info.monitor_range.max_vfreq = 0;
10100                 freesync_capable = false;
10101
10102                 goto update;
10103         }
10104
10105         dm_con_state = to_dm_connector_state(connector->state);
10106
10107         if (!adev->dm.freesync_module)
10108                 goto update;
10109
10110         if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
10111                 || sink->sink_signal == SIGNAL_TYPE_EDP) {
10112                 bool edid_check_required = false;
10113
10114                 if (edid) {
10115                         edid_check_required = is_dp_capable_without_timing_msa(
10116                                                 adev->dm.dc,
10117                                                 amdgpu_dm_connector);
10118                 }
10119
10120                 if (edid_check_required == true && (edid->version > 1 ||
10121                    (edid->version == 1 && edid->revision > 1))) {
10122                         for (i = 0; i < 4; i++) {
10123
10124                                 timing  = &edid->detailed_timings[i];
10125                                 data    = &timing->data.other_data;
10126                                 range   = &data->data.range;
10127                                 /*
10128                                  * Check if monitor has continuous frequency mode
10129                                  */
10130                                 if (data->type != EDID_DETAIL_MONITOR_RANGE)
10131                                         continue;
10132                                 /*
10133                                  * Check for flag range limits only. If flag == 1 then
10134                                  * no additional timing information provided.
10135                                  * Default GTF, GTF Secondary curve and CVT are not
10136                                  * supported
10137                                  */
10138                                 if (range->flags != 1)
10139                                         continue;
10140
10141                                 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
10142                                 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
10143                                 amdgpu_dm_connector->pixel_clock_mhz =
10144                                         range->pixel_clock_mhz * 10;
10145
10146                                 connector->display_info.monitor_range.min_vfreq = range->min_vfreq;
10147                                 connector->display_info.monitor_range.max_vfreq = range->max_vfreq;
10148
10149                                 break;
10150                         }
10151
10152                         if (amdgpu_dm_connector->max_vfreq -
10153                             amdgpu_dm_connector->min_vfreq > 10) {
10154
10155                                 freesync_capable = true;
10156                         }
10157                 }
10158         } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
10159                 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10160                 if (i >= 0 && vsdb_info.freesync_supported) {
10161                         timing  = &edid->detailed_timings[i];
10162                         data    = &timing->data.other_data;
10163
10164                         amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10165                         amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10166                         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10167                                 freesync_capable = true;
10168
10169                         connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10170                         connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10171                 }
10172         }
10173
10174 update:
10175         if (dm_con_state)
10176                 dm_con_state->freesync_capable = freesync_capable;
10177
10178         if (connector->vrr_capable_property)
10179                 drm_connector_set_vrr_capable_property(connector,
10180                                                        freesync_capable);
10181 }
10182
10183 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
10184 {
10185         struct amdgpu_device *adev = drm_to_adev(dev);
10186         struct dc *dc = adev->dm.dc;
10187         int i;
10188
10189         mutex_lock(&adev->dm.dc_lock);
10190         if (dc->current_state) {
10191                 for (i = 0; i < dc->current_state->stream_count; ++i)
10192                         dc->current_state->streams[i]
10193                                 ->triggered_crtc_reset.enabled =
10194                                 adev->dm.force_timing_sync;
10195
10196                 dm_enable_per_frame_crtc_master_sync(dc->current_state);
10197                 dc_trigger_sync(dc, dc->current_state);
10198         }
10199         mutex_unlock(&adev->dm.dc_lock);
10200 }
10201
10202 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
10203                        uint32_t value, const char *func_name)
10204 {
10205 #ifdef DM_CHECK_ADDR_0
10206         if (address == 0) {
10207                 DC_ERR("invalid register write. address = 0");
10208                 return;
10209         }
10210 #endif
10211         cgs_write_register(ctx->cgs_device, address, value);
10212         trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
10213 }
10214
10215 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
10216                           const char *func_name)
10217 {
10218         uint32_t value;
10219 #ifdef DM_CHECK_ADDR_0
10220         if (address == 0) {
10221                 DC_ERR("invalid register read; address = 0\n");
10222                 return 0;
10223         }
10224 #endif
10225
10226         if (ctx->dmub_srv &&
10227             ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
10228             !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
10229                 ASSERT(false);
10230                 return 0;
10231         }
10232
10233         value = cgs_read_register(ctx->cgs_device, address);
10234
10235         trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
10236
10237         return value;
10238 }
10239
10240 int amdgpu_dm_process_dmub_aux_transfer_sync(
10241                 struct dc_context *ctx,
10242                 unsigned int link_index,
10243                 struct aux_payload *payload,
10244                 enum aux_return_code_type *operation_result)
10245 {
10246         struct amdgpu_device *adev = ctx->driver_context;
10247         struct dmub_notification *p_notify = adev->dm.dmub_notify;
10248         int ret = -1;
10249
10250         mutex_lock(&adev->dm.dpia_aux_lock);
10251         if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) {
10252                 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE;
10253                 goto out;
10254         }
10255
10256         if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10257                 DRM_ERROR("wait_for_completion_timeout timeout!");
10258                 *operation_result = AUX_RET_ERROR_TIMEOUT;
10259                 goto out;
10260         }
10261
10262         if (p_notify->result != AUX_RET_SUCCESS) {
10263                 /*
10264                  * Transient states before tunneling is enabled could
10265                  * lead to this error. We can ignore this for now.
10266                  */
10267                 if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) {
10268                         DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n",
10269                                         payload->address, payload->length,
10270                                         p_notify->result);
10271                 }
10272                 *operation_result = AUX_RET_ERROR_INVALID_REPLY;
10273                 goto out;
10274         }
10275
10276
10277         payload->reply[0] = adev->dm.dmub_notify->aux_reply.command;
10278         if (!payload->write && p_notify->aux_reply.length &&
10279                         (payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) {
10280
10281                 if (payload->length != p_notify->aux_reply.length) {
10282                         DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n",
10283                                 p_notify->aux_reply.length,
10284                                         payload->address, payload->length);
10285                         *operation_result = AUX_RET_ERROR_INVALID_REPLY;
10286                         goto out;
10287                 }
10288
10289                 memcpy(payload->data, p_notify->aux_reply.data,
10290                                 p_notify->aux_reply.length);
10291         }
10292
10293         /* success */
10294         ret = p_notify->aux_reply.length;
10295         *operation_result = p_notify->result;
10296 out:
10297         mutex_unlock(&adev->dm.dpia_aux_lock);
10298         return ret;
10299 }
10300
10301 int amdgpu_dm_process_dmub_set_config_sync(
10302                 struct dc_context *ctx,
10303                 unsigned int link_index,
10304                 struct set_config_cmd_payload *payload,
10305                 enum set_config_status *operation_result)
10306 {
10307         struct amdgpu_device *adev = ctx->driver_context;
10308         bool is_cmd_complete;
10309         int ret;
10310
10311         mutex_lock(&adev->dm.dpia_aux_lock);
10312         is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc,
10313                         link_index, payload, adev->dm.dmub_notify);
10314
10315         if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10316                 ret = 0;
10317                 *operation_result = adev->dm.dmub_notify->sc_status;
10318         } else {
10319                 DRM_ERROR("wait_for_completion_timeout timeout!");
10320                 ret = -1;
10321                 *operation_result = SET_CONFIG_UNKNOWN_ERROR;
10322         }
10323
10324         mutex_unlock(&adev->dm.dpia_aux_lock);
10325         return ret;
10326 }
10327
10328 /*
10329  * Check whether seamless boot is supported.
10330  *
10331  * So far we only support seamless boot on CHIP_VANGOGH.
10332  * If everything goes well, we may consider expanding
10333  * seamless boot to other ASICs.
10334  */
10335 bool check_seamless_boot_capability(struct amdgpu_device *adev)
10336 {
10337         switch (adev->ip_versions[DCE_HWIP][0]) {
10338         case IP_VERSION(3, 0, 1):
10339                 if (!adev->mman.keep_stolen_vga_memory)
10340                         return true;
10341                 break;
10342         default:
10343                 break;
10344         }
10345
10346         return false;
10347 }