1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <linux/ratelimit.h>
26 #include <linux/printk.h>
27 #include <linux/slab.h>
28 #include <linux/list.h>
29 #include <linux/types.h>
30 #include <linux/bitops.h>
31 #include <linux/sched.h>
33 #include "kfd_device_queue_manager.h"
34 #include "kfd_mqd_manager.h"
36 #include "kfd_kernel_queue.h"
37 #include "amdgpu_amdkfd.h"
38 #include "mes_api_def.h"
39 #include "kfd_debug.h"
41 /* Size of the per-pipe EOP queue */
42 #define CIK_HPD_EOP_BYTES_LOG2 11
43 #define CIK_HPD_EOP_BYTES (1U << CIK_HPD_EOP_BYTES_LOG2)
45 static int set_pasid_vmid_mapping(struct device_queue_manager *dqm,
46 u32 pasid, unsigned int vmid);
48 static int execute_queues_cpsch(struct device_queue_manager *dqm,
49 enum kfd_unmap_queues_filter filter,
50 uint32_t filter_param,
51 uint32_t grace_period);
52 static int unmap_queues_cpsch(struct device_queue_manager *dqm,
53 enum kfd_unmap_queues_filter filter,
54 uint32_t filter_param,
55 uint32_t grace_period,
58 static int map_queues_cpsch(struct device_queue_manager *dqm);
60 static void deallocate_sdma_queue(struct device_queue_manager *dqm,
63 static inline void deallocate_hqd(struct device_queue_manager *dqm,
65 static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q);
66 static int allocate_sdma_queue(struct device_queue_manager *dqm,
67 struct queue *q, const uint32_t *restore_sdma_id);
68 static void kfd_process_hw_exception(struct work_struct *work);
71 enum KFD_MQD_TYPE get_mqd_type_from_queue_type(enum kfd_queue_type type)
73 if (type == KFD_QUEUE_TYPE_SDMA || type == KFD_QUEUE_TYPE_SDMA_XGMI)
74 return KFD_MQD_TYPE_SDMA;
75 return KFD_MQD_TYPE_CP;
78 static bool is_pipe_enabled(struct device_queue_manager *dqm, int mec, int pipe)
81 int pipe_offset = (mec * dqm->dev->kfd->shared_resources.num_pipe_per_mec
82 + pipe) * dqm->dev->kfd->shared_resources.num_queue_per_pipe;
84 /* queue is available for KFD usage if bit is 1 */
85 for (i = 0; i < dqm->dev->kfd->shared_resources.num_queue_per_pipe; ++i)
86 if (test_bit(pipe_offset + i,
87 dqm->dev->kfd->shared_resources.cp_queue_bitmap))
92 unsigned int get_cp_queues_num(struct device_queue_manager *dqm)
94 return bitmap_weight(dqm->dev->kfd->shared_resources.cp_queue_bitmap,
98 unsigned int get_queues_per_pipe(struct device_queue_manager *dqm)
100 return dqm->dev->kfd->shared_resources.num_queue_per_pipe;
103 unsigned int get_pipes_per_mec(struct device_queue_manager *dqm)
105 return dqm->dev->kfd->shared_resources.num_pipe_per_mec;
108 static unsigned int get_num_all_sdma_engines(struct device_queue_manager *dqm)
110 return kfd_get_num_sdma_engines(dqm->dev) +
111 kfd_get_num_xgmi_sdma_engines(dqm->dev);
114 unsigned int get_num_sdma_queues(struct device_queue_manager *dqm)
116 return kfd_get_num_sdma_engines(dqm->dev) *
117 dqm->dev->kfd->device_info.num_sdma_queues_per_engine;
120 unsigned int get_num_xgmi_sdma_queues(struct device_queue_manager *dqm)
122 return kfd_get_num_xgmi_sdma_engines(dqm->dev) *
123 dqm->dev->kfd->device_info.num_sdma_queues_per_engine;
126 static void init_sdma_bitmaps(struct device_queue_manager *dqm)
128 bitmap_zero(dqm->sdma_bitmap, KFD_MAX_SDMA_QUEUES);
129 bitmap_set(dqm->sdma_bitmap, 0, get_num_sdma_queues(dqm));
131 bitmap_zero(dqm->xgmi_sdma_bitmap, KFD_MAX_SDMA_QUEUES);
132 bitmap_set(dqm->xgmi_sdma_bitmap, 0, get_num_xgmi_sdma_queues(dqm));
134 /* Mask out the reserved queues */
135 bitmap_andnot(dqm->sdma_bitmap, dqm->sdma_bitmap,
136 dqm->dev->kfd->device_info.reserved_sdma_queues_bitmap,
137 KFD_MAX_SDMA_QUEUES);
140 void program_sh_mem_settings(struct device_queue_manager *dqm,
141 struct qcm_process_device *qpd)
143 uint32_t xcc_mask = dqm->dev->xcc_mask;
146 for_each_inst(xcc_id, xcc_mask)
147 dqm->dev->kfd2kgd->program_sh_mem_settings(
148 dqm->dev->adev, qpd->vmid, qpd->sh_mem_config,
149 qpd->sh_mem_ape1_base, qpd->sh_mem_ape1_limit,
150 qpd->sh_mem_bases, xcc_id);
153 static void kfd_hws_hang(struct device_queue_manager *dqm)
156 * Issue a GPU reset if HWS is unresponsive
158 dqm->is_hws_hang = true;
160 /* It's possible we're detecting a HWS hang in the
161 * middle of a GPU reset. No need to schedule another
162 * reset in this case.
164 if (!dqm->is_resetting)
165 schedule_work(&dqm->hw_exception_work);
168 static int convert_to_mes_queue_type(int queue_type)
172 switch (queue_type) {
173 case KFD_QUEUE_TYPE_COMPUTE:
174 mes_queue_type = MES_QUEUE_TYPE_COMPUTE;
176 case KFD_QUEUE_TYPE_SDMA:
177 mes_queue_type = MES_QUEUE_TYPE_SDMA;
180 WARN(1, "Invalid queue type %d", queue_type);
181 mes_queue_type = -EINVAL;
185 return mes_queue_type;
188 static int add_queue_mes(struct device_queue_manager *dqm, struct queue *q,
189 struct qcm_process_device *qpd)
191 struct amdgpu_device *adev = (struct amdgpu_device *)dqm->dev->adev;
192 struct kfd_process_device *pdd = qpd_to_pdd(qpd);
193 struct mes_add_queue_input queue_input;
195 uint64_t wptr_addr_off;
197 if (dqm->is_hws_hang)
200 memset(&queue_input, 0x0, sizeof(struct mes_add_queue_input));
201 queue_input.process_id = qpd->pqm->process->pasid;
202 queue_input.page_table_base_addr = qpd->page_table_base;
203 queue_input.process_va_start = 0;
204 queue_input.process_va_end = adev->vm_manager.max_pfn - 1;
205 /* MES unit for quantum is 100ns */
206 queue_input.process_quantum = KFD_MES_PROCESS_QUANTUM; /* Equivalent to 10ms. */
207 queue_input.process_context_addr = pdd->proc_ctx_gpu_addr;
208 queue_input.gang_quantum = KFD_MES_GANG_QUANTUM; /* Equivalent to 1ms */
209 queue_input.gang_context_addr = q->gang_ctx_gpu_addr;
210 queue_input.inprocess_gang_priority = q->properties.priority;
211 queue_input.gang_global_priority_level =
212 AMDGPU_MES_PRIORITY_LEVEL_NORMAL;
213 queue_input.doorbell_offset = q->properties.doorbell_off;
214 queue_input.mqd_addr = q->gart_mqd_addr;
215 queue_input.wptr_addr = (uint64_t)q->properties.write_ptr;
218 wptr_addr_off = (uint64_t)q->properties.write_ptr & (PAGE_SIZE - 1);
219 queue_input.wptr_mc_addr = ((uint64_t)q->wptr_bo->tbo.resource->start << PAGE_SHIFT) + wptr_addr_off;
222 queue_input.is_kfd_process = 1;
223 queue_input.is_aql_queue = (q->properties.format == KFD_QUEUE_FORMAT_AQL);
224 queue_input.queue_size = q->properties.queue_size >> 2;
226 queue_input.paging = false;
227 queue_input.tba_addr = qpd->tba_addr;
228 queue_input.tma_addr = qpd->tma_addr;
229 queue_input.trap_en = KFD_GC_VERSION(q->device) < IP_VERSION(11, 0, 0) ||
230 KFD_GC_VERSION(q->device) > IP_VERSION(11, 0, 3);
231 queue_input.skip_process_ctx_clear = qpd->pqm->process->debug_trap_enabled;
233 queue_type = convert_to_mes_queue_type(q->properties.type);
234 if (queue_type < 0) {
235 pr_err("Queue type not supported with MES, queue:%d\n",
239 queue_input.queue_type = (uint32_t)queue_type;
242 queue_input.gws_base = 0;
243 queue_input.gws_size = qpd->num_gws;
246 amdgpu_mes_lock(&adev->mes);
247 r = adev->mes.funcs->add_hw_queue(&adev->mes, &queue_input);
248 amdgpu_mes_unlock(&adev->mes);
250 pr_err("failed to add hardware queue to MES, doorbell=0x%x\n",
251 q->properties.doorbell_off);
252 pr_err("MES might be in unrecoverable state, issue a GPU reset\n");
259 static int remove_queue_mes(struct device_queue_manager *dqm, struct queue *q,
260 struct qcm_process_device *qpd)
262 struct amdgpu_device *adev = (struct amdgpu_device *)dqm->dev->adev;
264 struct mes_remove_queue_input queue_input;
266 if (dqm->is_hws_hang)
269 memset(&queue_input, 0x0, sizeof(struct mes_remove_queue_input));
270 queue_input.doorbell_offset = q->properties.doorbell_off;
271 queue_input.gang_context_addr = q->gang_ctx_gpu_addr;
273 amdgpu_mes_lock(&adev->mes);
274 r = adev->mes.funcs->remove_hw_queue(&adev->mes, &queue_input);
275 amdgpu_mes_unlock(&adev->mes);
278 pr_err("failed to remove hardware queue from MES, doorbell=0x%x\n",
279 q->properties.doorbell_off);
280 pr_err("MES might be in unrecoverable state, issue a GPU reset\n");
287 static int remove_all_queues_mes(struct device_queue_manager *dqm)
289 struct device_process_node *cur;
290 struct qcm_process_device *qpd;
294 list_for_each_entry(cur, &dqm->queues, list) {
296 list_for_each_entry(q, &qpd->queues_list, list) {
297 if (q->properties.is_active) {
298 retval = remove_queue_mes(dqm, q, qpd);
300 pr_err("%s: Failed to remove queue %d for dev %d",
302 q->properties.queue_id,
313 static void increment_queue_count(struct device_queue_manager *dqm,
314 struct qcm_process_device *qpd,
317 dqm->active_queue_count++;
318 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
319 q->properties.type == KFD_QUEUE_TYPE_DIQ)
320 dqm->active_cp_queue_count++;
322 if (q->properties.is_gws) {
323 dqm->gws_queue_count++;
324 qpd->mapped_gws_queue = true;
328 static void decrement_queue_count(struct device_queue_manager *dqm,
329 struct qcm_process_device *qpd,
332 dqm->active_queue_count--;
333 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
334 q->properties.type == KFD_QUEUE_TYPE_DIQ)
335 dqm->active_cp_queue_count--;
337 if (q->properties.is_gws) {
338 dqm->gws_queue_count--;
339 qpd->mapped_gws_queue = false;
344 * Allocate a doorbell ID to this queue.
345 * If doorbell_id is passed in, make sure requested ID is valid then allocate it.
347 static int allocate_doorbell(struct qcm_process_device *qpd,
349 uint32_t const *restore_id)
351 struct kfd_node *dev = qpd->dqm->dev;
353 if (!KFD_IS_SOC15(dev)) {
354 /* On pre-SOC15 chips we need to use the queue ID to
355 * preserve the user mode ABI.
358 if (restore_id && *restore_id != q->properties.queue_id)
361 q->doorbell_id = q->properties.queue_id;
362 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
363 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
364 /* For SDMA queues on SOC15 with 8-byte doorbell, use static
365 * doorbell assignments based on the engine and queue id.
366 * The doobell index distance between RLC (2*i) and (2*i+1)
367 * for a SDMA engine is 512.
370 uint32_t *idx_offset = dev->kfd->shared_resources.sdma_doorbell_idx;
373 * q->properties.sdma_engine_id corresponds to the virtual
374 * sdma engine number. However, for doorbell allocation,
375 * we need the physical sdma engine id in order to get the
376 * correct doorbell offset.
378 uint32_t valid_id = idx_offset[qpd->dqm->dev->node_id *
379 get_num_all_sdma_engines(qpd->dqm) +
380 q->properties.sdma_engine_id]
381 + (q->properties.sdma_queue_id & 1)
382 * KFD_QUEUE_DOORBELL_MIRROR_OFFSET
383 + (q->properties.sdma_queue_id >> 1);
385 if (restore_id && *restore_id != valid_id)
387 q->doorbell_id = valid_id;
389 /* For CP queues on SOC15 */
391 /* make sure that ID is free */
392 if (__test_and_set_bit(*restore_id, qpd->doorbell_bitmap))
395 q->doorbell_id = *restore_id;
397 /* or reserve a free doorbell ID */
400 found = find_first_zero_bit(qpd->doorbell_bitmap,
401 KFD_MAX_NUM_OF_QUEUES_PER_PROCESS);
402 if (found >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) {
403 pr_debug("No doorbells available");
406 set_bit(found, qpd->doorbell_bitmap);
407 q->doorbell_id = found;
411 q->properties.doorbell_off =
412 kfd_get_doorbell_dw_offset_in_bar(dev->kfd, qpd_to_pdd(qpd),
417 static void deallocate_doorbell(struct qcm_process_device *qpd,
421 struct kfd_node *dev = qpd->dqm->dev;
423 if (!KFD_IS_SOC15(dev) ||
424 q->properties.type == KFD_QUEUE_TYPE_SDMA ||
425 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
428 old = test_and_clear_bit(q->doorbell_id, qpd->doorbell_bitmap);
432 static void program_trap_handler_settings(struct device_queue_manager *dqm,
433 struct qcm_process_device *qpd)
435 uint32_t xcc_mask = dqm->dev->xcc_mask;
438 if (dqm->dev->kfd2kgd->program_trap_handler_settings)
439 for_each_inst(xcc_id, xcc_mask)
440 dqm->dev->kfd2kgd->program_trap_handler_settings(
441 dqm->dev->adev, qpd->vmid, qpd->tba_addr,
442 qpd->tma_addr, xcc_id);
445 static int allocate_vmid(struct device_queue_manager *dqm,
446 struct qcm_process_device *qpd,
449 int allocated_vmid = -1, i;
451 for (i = dqm->dev->vm_info.first_vmid_kfd;
452 i <= dqm->dev->vm_info.last_vmid_kfd; i++) {
453 if (!dqm->vmid_pasid[i]) {
459 if (allocated_vmid < 0) {
460 pr_err("no more vmid to allocate\n");
464 pr_debug("vmid allocated: %d\n", allocated_vmid);
466 dqm->vmid_pasid[allocated_vmid] = q->process->pasid;
468 set_pasid_vmid_mapping(dqm, q->process->pasid, allocated_vmid);
470 qpd->vmid = allocated_vmid;
471 q->properties.vmid = allocated_vmid;
473 program_sh_mem_settings(dqm, qpd);
475 if (KFD_IS_SOC15(dqm->dev) && dqm->dev->kfd->cwsr_enabled)
476 program_trap_handler_settings(dqm, qpd);
478 /* qpd->page_table_base is set earlier when register_process()
479 * is called, i.e. when the first queue is created.
481 dqm->dev->kfd2kgd->set_vm_context_page_table_base(dqm->dev->adev,
483 qpd->page_table_base);
484 /* invalidate the VM context after pasid and vmid mapping is set up */
485 kfd_flush_tlb(qpd_to_pdd(qpd), TLB_FLUSH_LEGACY);
487 if (dqm->dev->kfd2kgd->set_scratch_backing_va)
488 dqm->dev->kfd2kgd->set_scratch_backing_va(dqm->dev->adev,
489 qpd->sh_hidden_private_base, qpd->vmid);
494 static int flush_texture_cache_nocpsch(struct kfd_node *kdev,
495 struct qcm_process_device *qpd)
497 const struct packet_manager_funcs *pmf = qpd->dqm->packet_mgr.pmf;
503 ret = pmf->release_mem(qpd->ib_base, (uint32_t *)qpd->ib_kaddr);
507 return amdgpu_amdkfd_submit_ib(kdev->adev, KGD_ENGINE_MEC1, qpd->vmid,
508 qpd->ib_base, (uint32_t *)qpd->ib_kaddr,
509 pmf->release_mem_size / sizeof(uint32_t));
512 static void deallocate_vmid(struct device_queue_manager *dqm,
513 struct qcm_process_device *qpd,
516 /* On GFX v7, CP doesn't flush TC at dequeue */
517 if (q->device->adev->asic_type == CHIP_HAWAII)
518 if (flush_texture_cache_nocpsch(q->device, qpd))
519 pr_err("Failed to flush TC\n");
521 kfd_flush_tlb(qpd_to_pdd(qpd), TLB_FLUSH_LEGACY);
523 /* Release the vmid mapping */
524 set_pasid_vmid_mapping(dqm, 0, qpd->vmid);
525 dqm->vmid_pasid[qpd->vmid] = 0;
528 q->properties.vmid = 0;
531 static int create_queue_nocpsch(struct device_queue_manager *dqm,
533 struct qcm_process_device *qpd,
534 const struct kfd_criu_queue_priv_data *qd,
535 const void *restore_mqd, const void *restore_ctl_stack)
537 struct mqd_manager *mqd_mgr;
542 if (dqm->total_queue_count >= max_num_of_queues_per_device) {
543 pr_warn("Can't create new usermode queue because %d queues were already created\n",
544 dqm->total_queue_count);
549 if (list_empty(&qpd->queues_list)) {
550 retval = allocate_vmid(dqm, qpd, q);
554 q->properties.vmid = qpd->vmid;
556 * Eviction state logic: mark all queues as evicted, even ones
557 * not currently active. Restoring inactive queues later only
558 * updates the is_evicted flag but is a no-op otherwise.
560 q->properties.is_evicted = !!qpd->evicted;
562 q->properties.tba_addr = qpd->tba_addr;
563 q->properties.tma_addr = qpd->tma_addr;
565 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
566 q->properties.type)];
567 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) {
568 retval = allocate_hqd(dqm, q);
570 goto deallocate_vmid;
571 pr_debug("Loading mqd to hqd on pipe %d, queue %d\n",
573 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
574 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
575 retval = allocate_sdma_queue(dqm, q, qd ? &qd->sdma_id : NULL);
577 goto deallocate_vmid;
578 dqm->asic_ops.init_sdma_vm(dqm, q, qpd);
581 retval = allocate_doorbell(qpd, q, qd ? &qd->doorbell_id : NULL);
583 goto out_deallocate_hqd;
585 /* Temporarily release dqm lock to avoid a circular lock dependency */
587 q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties);
590 if (!q->mqd_mem_obj) {
592 goto out_deallocate_doorbell;
596 mqd_mgr->restore_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, &q->gart_mqd_addr,
597 &q->properties, restore_mqd, restore_ctl_stack,
600 mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj,
601 &q->gart_mqd_addr, &q->properties);
603 if (q->properties.is_active) {
604 if (!dqm->sched_running) {
605 WARN_ONCE(1, "Load non-HWS mqd while stopped\n");
606 goto add_queue_to_list;
609 if (WARN(q->process->mm != current->mm,
610 "should only run in user thread"))
613 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe,
614 q->queue, &q->properties, current->mm);
620 list_add(&q->list, &qpd->queues_list);
622 if (q->properties.is_active)
623 increment_queue_count(dqm, qpd, q);
626 * Unconditionally increment this counter, regardless of the queue's
627 * type or whether the queue is active.
629 dqm->total_queue_count++;
630 pr_debug("Total of %d queues are accountable so far\n",
631 dqm->total_queue_count);
635 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
636 out_deallocate_doorbell:
637 deallocate_doorbell(qpd, q);
639 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE)
640 deallocate_hqd(dqm, q);
641 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
642 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
643 deallocate_sdma_queue(dqm, q);
645 if (list_empty(&qpd->queues_list))
646 deallocate_vmid(dqm, qpd, q);
652 static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q)
659 for (pipe = dqm->next_pipe_to_allocate, i = 0;
660 i < get_pipes_per_mec(dqm);
661 pipe = ((pipe + 1) % get_pipes_per_mec(dqm)), ++i) {
663 if (!is_pipe_enabled(dqm, 0, pipe))
666 if (dqm->allocated_queues[pipe] != 0) {
667 bit = ffs(dqm->allocated_queues[pipe]) - 1;
668 dqm->allocated_queues[pipe] &= ~(1 << bit);
679 pr_debug("hqd slot - pipe %d, queue %d\n", q->pipe, q->queue);
680 /* horizontal hqd allocation */
681 dqm->next_pipe_to_allocate = (pipe + 1) % get_pipes_per_mec(dqm);
686 static inline void deallocate_hqd(struct device_queue_manager *dqm,
689 dqm->allocated_queues[q->pipe] |= (1 << q->queue);
692 #define SQ_IND_CMD_CMD_KILL 0x00000003
693 #define SQ_IND_CMD_MODE_BROADCAST 0x00000001
695 static int dbgdev_wave_reset_wavefronts(struct kfd_node *dev, struct kfd_process *p)
699 uint16_t queried_pasid;
700 union SQ_CMD_BITS reg_sq_cmd;
701 union GRBM_GFX_INDEX_BITS reg_gfx_index;
702 struct kfd_process_device *pdd;
703 int first_vmid_to_scan = dev->vm_info.first_vmid_kfd;
704 int last_vmid_to_scan = dev->vm_info.last_vmid_kfd;
705 uint32_t xcc_mask = dev->xcc_mask;
708 reg_sq_cmd.u32All = 0;
709 reg_gfx_index.u32All = 0;
711 pr_debug("Killing all process wavefronts\n");
713 if (!dev->kfd2kgd->get_atc_vmid_pasid_mapping_info) {
714 pr_err("no vmid pasid mapping supported \n");
718 /* Scan all registers in the range ATC_VMID8_PASID_MAPPING ..
719 * ATC_VMID15_PASID_MAPPING
720 * to check which VMID the current process is mapped to.
723 for (vmid = first_vmid_to_scan; vmid <= last_vmid_to_scan; vmid++) {
724 status = dev->kfd2kgd->get_atc_vmid_pasid_mapping_info
725 (dev->adev, vmid, &queried_pasid);
727 if (status && queried_pasid == p->pasid) {
728 pr_debug("Killing wave fronts of vmid %d and pasid 0x%x\n",
734 if (vmid > last_vmid_to_scan) {
735 pr_err("Didn't find vmid for pasid 0x%x\n", p->pasid);
739 /* taking the VMID for that process on the safe way using PDD */
740 pdd = kfd_get_process_device_data(dev, p);
744 reg_gfx_index.bits.sh_broadcast_writes = 1;
745 reg_gfx_index.bits.se_broadcast_writes = 1;
746 reg_gfx_index.bits.instance_broadcast_writes = 1;
747 reg_sq_cmd.bits.mode = SQ_IND_CMD_MODE_BROADCAST;
748 reg_sq_cmd.bits.cmd = SQ_IND_CMD_CMD_KILL;
749 reg_sq_cmd.bits.vm_id = vmid;
751 for_each_inst(xcc_id, xcc_mask)
752 dev->kfd2kgd->wave_control_execute(
753 dev->adev, reg_gfx_index.u32All,
754 reg_sq_cmd.u32All, xcc_id);
759 /* Access to DQM has to be locked before calling destroy_queue_nocpsch_locked
760 * to avoid asynchronized access
762 static int destroy_queue_nocpsch_locked(struct device_queue_manager *dqm,
763 struct qcm_process_device *qpd,
767 struct mqd_manager *mqd_mgr;
769 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
770 q->properties.type)];
772 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE)
773 deallocate_hqd(dqm, q);
774 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
775 deallocate_sdma_queue(dqm, q);
776 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
777 deallocate_sdma_queue(dqm, q);
779 pr_debug("q->properties.type %d is invalid\n",
783 dqm->total_queue_count--;
785 deallocate_doorbell(qpd, q);
787 if (!dqm->sched_running) {
788 WARN_ONCE(1, "Destroy non-HWS queue while stopped\n");
792 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd,
793 KFD_PREEMPT_TYPE_WAVEFRONT_RESET,
794 KFD_UNMAP_LATENCY_MS,
796 if (retval == -ETIME)
797 qpd->reset_wavefronts = true;
800 if (list_empty(&qpd->queues_list)) {
801 if (qpd->reset_wavefronts) {
802 pr_warn("Resetting wave fronts (nocpsch) on dev %p\n",
804 /* dbgdev_wave_reset_wavefronts has to be called before
805 * deallocate_vmid(), i.e. when vmid is still in use.
807 dbgdev_wave_reset_wavefronts(dqm->dev,
809 qpd->reset_wavefronts = false;
812 deallocate_vmid(dqm, qpd, q);
815 if (q->properties.is_active)
816 decrement_queue_count(dqm, qpd, q);
821 static int destroy_queue_nocpsch(struct device_queue_manager *dqm,
822 struct qcm_process_device *qpd,
826 uint64_t sdma_val = 0;
827 struct kfd_process_device *pdd = qpd_to_pdd(qpd);
828 struct mqd_manager *mqd_mgr =
829 dqm->mqd_mgrs[get_mqd_type_from_queue_type(q->properties.type)];
831 /* Get the SDMA queue stats */
832 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) ||
833 (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) {
834 retval = read_sdma_queue_counter((uint64_t __user *)q->properties.read_ptr,
837 pr_err("Failed to read SDMA queue counter for queue: %d\n",
838 q->properties.queue_id);
842 retval = destroy_queue_nocpsch_locked(dqm, qpd, q);
844 pdd->sdma_past_activity_counter += sdma_val;
847 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
852 static int update_queue(struct device_queue_manager *dqm, struct queue *q,
853 struct mqd_update_info *minfo)
856 struct mqd_manager *mqd_mgr;
857 struct kfd_process_device *pdd;
858 bool prev_active = false;
861 pdd = kfd_get_process_device_data(q->device, q->process);
866 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
867 q->properties.type)];
869 /* Save previous activity state for counters */
870 prev_active = q->properties.is_active;
872 /* Make sure the queue is unmapped before updating the MQD */
873 if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) {
874 if (!dqm->dev->kfd->shared_resources.enable_mes)
875 retval = unmap_queues_cpsch(dqm,
876 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD, false);
877 else if (prev_active)
878 retval = remove_queue_mes(dqm, q, &pdd->qpd);
881 pr_err("unmap queue failed\n");
884 } else if (prev_active &&
885 (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
886 q->properties.type == KFD_QUEUE_TYPE_SDMA ||
887 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) {
889 if (!dqm->sched_running) {
890 WARN_ONCE(1, "Update non-HWS queue while stopped\n");
894 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd,
895 (dqm->dev->kfd->cwsr_enabled ?
896 KFD_PREEMPT_TYPE_WAVEFRONT_SAVE :
897 KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN),
898 KFD_UNMAP_LATENCY_MS, q->pipe, q->queue);
900 pr_err("destroy mqd failed\n");
905 mqd_mgr->update_mqd(mqd_mgr, q->mqd, &q->properties, minfo);
908 * check active state vs. the previous state and modify
909 * counter accordingly. map_queues_cpsch uses the
910 * dqm->active_queue_count to determine whether a new runlist must be
913 if (q->properties.is_active && !prev_active) {
914 increment_queue_count(dqm, &pdd->qpd, q);
915 } else if (!q->properties.is_active && prev_active) {
916 decrement_queue_count(dqm, &pdd->qpd, q);
917 } else if (q->gws && !q->properties.is_gws) {
918 if (q->properties.is_active) {
919 dqm->gws_queue_count++;
920 pdd->qpd.mapped_gws_queue = true;
922 q->properties.is_gws = true;
923 } else if (!q->gws && q->properties.is_gws) {
924 if (q->properties.is_active) {
925 dqm->gws_queue_count--;
926 pdd->qpd.mapped_gws_queue = false;
928 q->properties.is_gws = false;
931 if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) {
932 if (!dqm->dev->kfd->shared_resources.enable_mes)
933 retval = map_queues_cpsch(dqm);
934 else if (q->properties.is_active)
935 retval = add_queue_mes(dqm, q, &pdd->qpd);
936 } else if (q->properties.is_active &&
937 (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
938 q->properties.type == KFD_QUEUE_TYPE_SDMA ||
939 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) {
940 if (WARN(q->process->mm != current->mm,
941 "should only run in user thread"))
944 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd,
946 &q->properties, current->mm);
954 /* suspend_single_queue does not lock the dqm like the
955 * evict_process_queues_cpsch or evict_process_queues_nocpsch. You should
956 * lock the dqm before calling, and unlock after calling.
958 * The reason we don't lock the dqm is because this function may be
959 * called on multiple queues in a loop, so rather than locking/unlocking
960 * multiple times, we will just keep the dqm locked for all of the calls.
962 static int suspend_single_queue(struct device_queue_manager *dqm,
963 struct kfd_process_device *pdd,
968 if (q->properties.is_suspended)
971 pr_debug("Suspending PASID %u queue [%i]\n",
973 q->properties.queue_id);
975 is_new = q->properties.exception_status & KFD_EC_MASK(EC_QUEUE_NEW);
977 if (is_new || q->properties.is_being_destroyed) {
978 pr_debug("Suspend: skip %s queue id %i\n",
979 is_new ? "new" : "destroyed",
980 q->properties.queue_id);
984 q->properties.is_suspended = true;
985 if (q->properties.is_active) {
986 if (dqm->dev->kfd->shared_resources.enable_mes) {
987 int r = remove_queue_mes(dqm, q, &pdd->qpd);
993 decrement_queue_count(dqm, &pdd->qpd, q);
994 q->properties.is_active = false;
1000 /* resume_single_queue does not lock the dqm like the functions
1001 * restore_process_queues_cpsch or restore_process_queues_nocpsch. You should
1002 * lock the dqm before calling, and unlock after calling.
1004 * The reason we don't lock the dqm is because this function may be
1005 * called on multiple queues in a loop, so rather than locking/unlocking
1006 * multiple times, we will just keep the dqm locked for all of the calls.
1008 static int resume_single_queue(struct device_queue_manager *dqm,
1009 struct qcm_process_device *qpd,
1012 struct kfd_process_device *pdd;
1014 if (!q->properties.is_suspended)
1017 pdd = qpd_to_pdd(qpd);
1019 pr_debug("Restoring from suspend PASID %u queue [%i]\n",
1020 pdd->process->pasid,
1021 q->properties.queue_id);
1023 q->properties.is_suspended = false;
1025 if (QUEUE_IS_ACTIVE(q->properties)) {
1026 if (dqm->dev->kfd->shared_resources.enable_mes) {
1027 int r = add_queue_mes(dqm, q, &pdd->qpd);
1033 q->properties.is_active = true;
1034 increment_queue_count(dqm, qpd, q);
1040 static int evict_process_queues_nocpsch(struct device_queue_manager *dqm,
1041 struct qcm_process_device *qpd)
1044 struct mqd_manager *mqd_mgr;
1045 struct kfd_process_device *pdd;
1046 int retval, ret = 0;
1049 if (qpd->evicted++ > 0) /* already evicted, do nothing */
1052 pdd = qpd_to_pdd(qpd);
1053 pr_debug_ratelimited("Evicting PASID 0x%x queues\n",
1054 pdd->process->pasid);
1056 pdd->last_evict_timestamp = get_jiffies_64();
1057 /* Mark all queues as evicted. Deactivate all active queues on
1060 list_for_each_entry(q, &qpd->queues_list, list) {
1061 q->properties.is_evicted = true;
1062 if (!q->properties.is_active)
1065 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
1066 q->properties.type)];
1067 q->properties.is_active = false;
1068 decrement_queue_count(dqm, qpd, q);
1070 if (WARN_ONCE(!dqm->sched_running, "Evict when stopped\n"))
1073 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd,
1074 (dqm->dev->kfd->cwsr_enabled ?
1075 KFD_PREEMPT_TYPE_WAVEFRONT_SAVE :
1076 KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN),
1077 KFD_UNMAP_LATENCY_MS, q->pipe, q->queue);
1079 /* Return the first error, but keep going to
1080 * maintain a consistent eviction state
1090 static int evict_process_queues_cpsch(struct device_queue_manager *dqm,
1091 struct qcm_process_device *qpd)
1094 struct kfd_process_device *pdd;
1098 if (qpd->evicted++ > 0) /* already evicted, do nothing */
1101 pdd = qpd_to_pdd(qpd);
1103 /* The debugger creates processes that temporarily have not acquired
1104 * all VMs for all devices and has no VMs itself.
1105 * Skip queue eviction on process eviction.
1110 pr_debug_ratelimited("Evicting PASID 0x%x queues\n",
1111 pdd->process->pasid);
1113 /* Mark all queues as evicted. Deactivate all active queues on
1116 list_for_each_entry(q, &qpd->queues_list, list) {
1117 q->properties.is_evicted = true;
1118 if (!q->properties.is_active)
1121 q->properties.is_active = false;
1122 decrement_queue_count(dqm, qpd, q);
1124 if (dqm->dev->kfd->shared_resources.enable_mes) {
1125 retval = remove_queue_mes(dqm, q, qpd);
1127 pr_err("Failed to evict queue %d\n",
1128 q->properties.queue_id);
1133 pdd->last_evict_timestamp = get_jiffies_64();
1134 if (!dqm->dev->kfd->shared_resources.enable_mes)
1135 retval = execute_queues_cpsch(dqm,
1137 KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES :
1138 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0,
1139 USE_DEFAULT_GRACE_PERIOD);
1146 static int restore_process_queues_nocpsch(struct device_queue_manager *dqm,
1147 struct qcm_process_device *qpd)
1149 struct mm_struct *mm = NULL;
1151 struct mqd_manager *mqd_mgr;
1152 struct kfd_process_device *pdd;
1154 uint64_t eviction_duration;
1155 int retval, ret = 0;
1157 pdd = qpd_to_pdd(qpd);
1158 /* Retrieve PD base */
1159 pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv);
1162 if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */
1164 if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */
1169 pr_debug_ratelimited("Restoring PASID 0x%x queues\n",
1170 pdd->process->pasid);
1172 /* Update PD Base in QPD */
1173 qpd->page_table_base = pd_base;
1174 pr_debug("Updated PD address to 0x%llx\n", pd_base);
1176 if (!list_empty(&qpd->queues_list)) {
1177 dqm->dev->kfd2kgd->set_vm_context_page_table_base(
1180 qpd->page_table_base);
1181 kfd_flush_tlb(pdd, TLB_FLUSH_LEGACY);
1184 /* Take a safe reference to the mm_struct, which may otherwise
1185 * disappear even while the kfd_process is still referenced.
1187 mm = get_task_mm(pdd->process->lead_thread);
1193 /* Remove the eviction flags. Activate queues that are not
1194 * inactive for other reasons.
1196 list_for_each_entry(q, &qpd->queues_list, list) {
1197 q->properties.is_evicted = false;
1198 if (!QUEUE_IS_ACTIVE(q->properties))
1201 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
1202 q->properties.type)];
1203 q->properties.is_active = true;
1204 increment_queue_count(dqm, qpd, q);
1206 if (WARN_ONCE(!dqm->sched_running, "Restore when stopped\n"))
1209 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe,
1210 q->queue, &q->properties, mm);
1212 /* Return the first error, but keep going to
1213 * maintain a consistent eviction state
1218 eviction_duration = get_jiffies_64() - pdd->last_evict_timestamp;
1219 atomic64_add(eviction_duration, &pdd->evict_duration_counter);
1227 static int restore_process_queues_cpsch(struct device_queue_manager *dqm,
1228 struct qcm_process_device *qpd)
1231 struct kfd_process_device *pdd;
1232 uint64_t eviction_duration;
1235 pdd = qpd_to_pdd(qpd);
1238 if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */
1240 if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */
1245 /* The debugger creates processes that temporarily have not acquired
1246 * all VMs for all devices and has no VMs itself.
1247 * Skip queue restore on process restore.
1250 goto vm_not_acquired;
1252 pr_debug_ratelimited("Restoring PASID 0x%x queues\n",
1253 pdd->process->pasid);
1255 /* Update PD Base in QPD */
1256 qpd->page_table_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv);
1257 pr_debug("Updated PD address to 0x%llx\n", qpd->page_table_base);
1259 /* activate all active queues on the qpd */
1260 list_for_each_entry(q, &qpd->queues_list, list) {
1261 q->properties.is_evicted = false;
1262 if (!QUEUE_IS_ACTIVE(q->properties))
1265 q->properties.is_active = true;
1266 increment_queue_count(dqm, &pdd->qpd, q);
1268 if (dqm->dev->kfd->shared_resources.enable_mes) {
1269 retval = add_queue_mes(dqm, q, qpd);
1271 pr_err("Failed to restore queue %d\n",
1272 q->properties.queue_id);
1277 if (!dqm->dev->kfd->shared_resources.enable_mes)
1278 retval = execute_queues_cpsch(dqm,
1279 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD);
1280 eviction_duration = get_jiffies_64() - pdd->last_evict_timestamp;
1281 atomic64_add(eviction_duration, &pdd->evict_duration_counter);
1289 static int register_process(struct device_queue_manager *dqm,
1290 struct qcm_process_device *qpd)
1292 struct device_process_node *n;
1293 struct kfd_process_device *pdd;
1297 n = kzalloc(sizeof(*n), GFP_KERNEL);
1303 pdd = qpd_to_pdd(qpd);
1304 /* Retrieve PD base */
1305 pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv);
1308 list_add(&n->list, &dqm->queues);
1310 /* Update PD Base in QPD */
1311 qpd->page_table_base = pd_base;
1312 pr_debug("Updated PD address to 0x%llx\n", pd_base);
1314 retval = dqm->asic_ops.update_qpd(dqm, qpd);
1316 dqm->processes_count++;
1320 /* Outside the DQM lock because under the DQM lock we can't do
1321 * reclaim or take other locks that others hold while reclaiming.
1323 kfd_inc_compute_active(dqm->dev);
1328 static int unregister_process(struct device_queue_manager *dqm,
1329 struct qcm_process_device *qpd)
1332 struct device_process_node *cur, *next;
1334 pr_debug("qpd->queues_list is %s\n",
1335 list_empty(&qpd->queues_list) ? "empty" : "not empty");
1340 list_for_each_entry_safe(cur, next, &dqm->queues, list) {
1341 if (qpd == cur->qpd) {
1342 list_del(&cur->list);
1344 dqm->processes_count--;
1348 /* qpd not found in dqm list */
1353 /* Outside the DQM lock because under the DQM lock we can't do
1354 * reclaim or take other locks that others hold while reclaiming.
1357 kfd_dec_compute_active(dqm->dev);
1363 set_pasid_vmid_mapping(struct device_queue_manager *dqm, u32 pasid,
1366 uint32_t xcc_mask = dqm->dev->xcc_mask;
1369 for_each_inst(xcc_id, xcc_mask) {
1370 ret = dqm->dev->kfd2kgd->set_pasid_vmid_mapping(
1371 dqm->dev->adev, pasid, vmid, xcc_id);
1379 static void init_interrupts(struct device_queue_manager *dqm)
1381 uint32_t xcc_mask = dqm->dev->xcc_mask;
1382 unsigned int i, xcc_id;
1384 for_each_inst(xcc_id, xcc_mask) {
1385 for (i = 0 ; i < get_pipes_per_mec(dqm) ; i++) {
1386 if (is_pipe_enabled(dqm, 0, i)) {
1387 dqm->dev->kfd2kgd->init_interrupts(
1388 dqm->dev->adev, i, xcc_id);
1394 static int initialize_nocpsch(struct device_queue_manager *dqm)
1398 pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm));
1400 dqm->allocated_queues = kcalloc(get_pipes_per_mec(dqm),
1401 sizeof(unsigned int), GFP_KERNEL);
1402 if (!dqm->allocated_queues)
1405 mutex_init(&dqm->lock_hidden);
1406 INIT_LIST_HEAD(&dqm->queues);
1407 dqm->active_queue_count = dqm->next_pipe_to_allocate = 0;
1408 dqm->active_cp_queue_count = 0;
1409 dqm->gws_queue_count = 0;
1411 for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) {
1412 int pipe_offset = pipe * get_queues_per_pipe(dqm);
1414 for (queue = 0; queue < get_queues_per_pipe(dqm); queue++)
1415 if (test_bit(pipe_offset + queue,
1416 dqm->dev->kfd->shared_resources.cp_queue_bitmap))
1417 dqm->allocated_queues[pipe] |= 1 << queue;
1420 memset(dqm->vmid_pasid, 0, sizeof(dqm->vmid_pasid));
1422 init_sdma_bitmaps(dqm);
1427 static void uninitialize(struct device_queue_manager *dqm)
1431 WARN_ON(dqm->active_queue_count > 0 || dqm->processes_count > 0);
1433 kfree(dqm->allocated_queues);
1434 for (i = 0 ; i < KFD_MQD_TYPE_MAX ; i++)
1435 kfree(dqm->mqd_mgrs[i]);
1436 mutex_destroy(&dqm->lock_hidden);
1439 static int start_nocpsch(struct device_queue_manager *dqm)
1443 pr_info("SW scheduler is used");
1444 init_interrupts(dqm);
1446 if (dqm->dev->adev->asic_type == CHIP_HAWAII)
1447 r = pm_init(&dqm->packet_mgr, dqm);
1449 dqm->sched_running = true;
1454 static int stop_nocpsch(struct device_queue_manager *dqm)
1457 if (!dqm->sched_running) {
1462 if (dqm->dev->adev->asic_type == CHIP_HAWAII)
1463 pm_uninit(&dqm->packet_mgr, false);
1464 dqm->sched_running = false;
1470 static void pre_reset(struct device_queue_manager *dqm)
1473 dqm->is_resetting = true;
1477 static int allocate_sdma_queue(struct device_queue_manager *dqm,
1478 struct queue *q, const uint32_t *restore_sdma_id)
1482 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
1483 if (bitmap_empty(dqm->sdma_bitmap, KFD_MAX_SDMA_QUEUES)) {
1484 pr_err("No more SDMA queue to allocate\n");
1488 if (restore_sdma_id) {
1489 /* Re-use existing sdma_id */
1490 if (!test_bit(*restore_sdma_id, dqm->sdma_bitmap)) {
1491 pr_err("SDMA queue already in use\n");
1494 clear_bit(*restore_sdma_id, dqm->sdma_bitmap);
1495 q->sdma_id = *restore_sdma_id;
1497 /* Find first available sdma_id */
1498 bit = find_first_bit(dqm->sdma_bitmap,
1499 get_num_sdma_queues(dqm));
1500 clear_bit(bit, dqm->sdma_bitmap);
1504 q->properties.sdma_engine_id =
1505 q->sdma_id % kfd_get_num_sdma_engines(dqm->dev);
1506 q->properties.sdma_queue_id = q->sdma_id /
1507 kfd_get_num_sdma_engines(dqm->dev);
1508 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
1509 if (bitmap_empty(dqm->xgmi_sdma_bitmap, KFD_MAX_SDMA_QUEUES)) {
1510 pr_err("No more XGMI SDMA queue to allocate\n");
1513 if (restore_sdma_id) {
1514 /* Re-use existing sdma_id */
1515 if (!test_bit(*restore_sdma_id, dqm->xgmi_sdma_bitmap)) {
1516 pr_err("SDMA queue already in use\n");
1519 clear_bit(*restore_sdma_id, dqm->xgmi_sdma_bitmap);
1520 q->sdma_id = *restore_sdma_id;
1522 bit = find_first_bit(dqm->xgmi_sdma_bitmap,
1523 get_num_xgmi_sdma_queues(dqm));
1524 clear_bit(bit, dqm->xgmi_sdma_bitmap);
1527 /* sdma_engine_id is sdma id including
1528 * both PCIe-optimized SDMAs and XGMI-
1529 * optimized SDMAs. The calculation below
1530 * assumes the first N engines are always
1531 * PCIe-optimized ones
1533 q->properties.sdma_engine_id =
1534 kfd_get_num_sdma_engines(dqm->dev) +
1535 q->sdma_id % kfd_get_num_xgmi_sdma_engines(dqm->dev);
1536 q->properties.sdma_queue_id = q->sdma_id /
1537 kfd_get_num_xgmi_sdma_engines(dqm->dev);
1540 pr_debug("SDMA engine id: %d\n", q->properties.sdma_engine_id);
1541 pr_debug("SDMA queue id: %d\n", q->properties.sdma_queue_id);
1546 static void deallocate_sdma_queue(struct device_queue_manager *dqm,
1549 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
1550 if (q->sdma_id >= get_num_sdma_queues(dqm))
1552 set_bit(q->sdma_id, dqm->sdma_bitmap);
1553 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
1554 if (q->sdma_id >= get_num_xgmi_sdma_queues(dqm))
1556 set_bit(q->sdma_id, dqm->xgmi_sdma_bitmap);
1561 * Device Queue Manager implementation for cp scheduler
1564 static int set_sched_resources(struct device_queue_manager *dqm)
1567 struct scheduling_resources res;
1569 res.vmid_mask = dqm->dev->compute_vmid_bitmap;
1572 for (i = 0; i < KGD_MAX_QUEUES; ++i) {
1573 mec = (i / dqm->dev->kfd->shared_resources.num_queue_per_pipe)
1574 / dqm->dev->kfd->shared_resources.num_pipe_per_mec;
1576 if (!test_bit(i, dqm->dev->kfd->shared_resources.cp_queue_bitmap))
1579 /* only acquire queues from the first MEC */
1583 /* This situation may be hit in the future if a new HW
1584 * generation exposes more than 64 queues. If so, the
1585 * definition of res.queue_mask needs updating
1587 if (WARN_ON(i >= (sizeof(res.queue_mask)*8))) {
1588 pr_err("Invalid queue enabled by amdgpu: %d\n", i);
1592 res.queue_mask |= 1ull
1593 << amdgpu_queue_mask_bit_to_set_resource_bit(
1596 res.gws_mask = ~0ull;
1597 res.oac_mask = res.gds_heap_base = res.gds_heap_size = 0;
1599 pr_debug("Scheduling resources:\n"
1600 "vmid mask: 0x%8X\n"
1601 "queue mask: 0x%8llX\n",
1602 res.vmid_mask, res.queue_mask);
1604 return pm_send_set_resources(&dqm->packet_mgr, &res);
1607 static int initialize_cpsch(struct device_queue_manager *dqm)
1609 pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm));
1611 mutex_init(&dqm->lock_hidden);
1612 INIT_LIST_HEAD(&dqm->queues);
1613 dqm->active_queue_count = dqm->processes_count = 0;
1614 dqm->active_cp_queue_count = 0;
1615 dqm->gws_queue_count = 0;
1616 dqm->active_runlist = false;
1617 INIT_WORK(&dqm->hw_exception_work, kfd_process_hw_exception);
1618 dqm->trap_debug_vmid = 0;
1620 init_sdma_bitmaps(dqm);
1622 if (dqm->dev->kfd2kgd->get_iq_wait_times)
1623 dqm->dev->kfd2kgd->get_iq_wait_times(dqm->dev->adev,
1628 static int start_cpsch(struct device_queue_manager *dqm)
1636 if (!dqm->dev->kfd->shared_resources.enable_mes) {
1637 retval = pm_init(&dqm->packet_mgr, dqm);
1639 goto fail_packet_manager_init;
1641 retval = set_sched_resources(dqm);
1643 goto fail_set_sched_resources;
1645 pr_debug("Allocating fence memory\n");
1647 /* allocate fence memory on the gart */
1648 retval = kfd_gtt_sa_allocate(dqm->dev, sizeof(*dqm->fence_addr),
1652 goto fail_allocate_vidmem;
1654 dqm->fence_addr = (uint64_t *)dqm->fence_mem->cpu_ptr;
1655 dqm->fence_gpu_addr = dqm->fence_mem->gpu_addr;
1657 init_interrupts(dqm);
1659 /* clear hang status when driver try to start the hw scheduler */
1660 dqm->is_hws_hang = false;
1661 dqm->is_resetting = false;
1662 dqm->sched_running = true;
1664 if (!dqm->dev->kfd->shared_resources.enable_mes)
1665 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD);
1669 fail_allocate_vidmem:
1670 fail_set_sched_resources:
1671 if (!dqm->dev->kfd->shared_resources.enable_mes)
1672 pm_uninit(&dqm->packet_mgr, false);
1673 fail_packet_manager_init:
1678 static int stop_cpsch(struct device_queue_manager *dqm)
1683 if (!dqm->sched_running) {
1688 if (!dqm->is_hws_hang) {
1689 if (!dqm->dev->kfd->shared_resources.enable_mes)
1690 unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD, false);
1692 remove_all_queues_mes(dqm);
1695 hanging = dqm->is_hws_hang || dqm->is_resetting;
1696 dqm->sched_running = false;
1698 if (!dqm->dev->kfd->shared_resources.enable_mes)
1699 pm_release_ib(&dqm->packet_mgr);
1701 kfd_gtt_sa_free(dqm->dev, dqm->fence_mem);
1702 if (!dqm->dev->kfd->shared_resources.enable_mes)
1703 pm_uninit(&dqm->packet_mgr, hanging);
1709 static int create_kernel_queue_cpsch(struct device_queue_manager *dqm,
1710 struct kernel_queue *kq,
1711 struct qcm_process_device *qpd)
1714 if (dqm->total_queue_count >= max_num_of_queues_per_device) {
1715 pr_warn("Can't create new kernel queue because %d queues were already created\n",
1716 dqm->total_queue_count);
1722 * Unconditionally increment this counter, regardless of the queue's
1723 * type or whether the queue is active.
1725 dqm->total_queue_count++;
1726 pr_debug("Total of %d queues are accountable so far\n",
1727 dqm->total_queue_count);
1729 list_add(&kq->list, &qpd->priv_queue_list);
1730 increment_queue_count(dqm, qpd, kq->queue);
1731 qpd->is_debug = true;
1732 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0,
1733 USE_DEFAULT_GRACE_PERIOD);
1739 static void destroy_kernel_queue_cpsch(struct device_queue_manager *dqm,
1740 struct kernel_queue *kq,
1741 struct qcm_process_device *qpd)
1744 list_del(&kq->list);
1745 decrement_queue_count(dqm, qpd, kq->queue);
1746 qpd->is_debug = false;
1747 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0,
1748 USE_DEFAULT_GRACE_PERIOD);
1750 * Unconditionally decrement this counter, regardless of the queue's
1753 dqm->total_queue_count--;
1754 pr_debug("Total of %d queues are accountable so far\n",
1755 dqm->total_queue_count);
1759 static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q,
1760 struct qcm_process_device *qpd,
1761 const struct kfd_criu_queue_priv_data *qd,
1762 const void *restore_mqd, const void *restore_ctl_stack)
1765 struct mqd_manager *mqd_mgr;
1767 if (dqm->total_queue_count >= max_num_of_queues_per_device) {
1768 pr_warn("Can't create new usermode queue because %d queues were already created\n",
1769 dqm->total_queue_count);
1774 if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
1775 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
1777 retval = allocate_sdma_queue(dqm, q, qd ? &qd->sdma_id : NULL);
1783 retval = allocate_doorbell(qpd, q, qd ? &qd->doorbell_id : NULL);
1785 goto out_deallocate_sdma_queue;
1787 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
1788 q->properties.type)];
1790 if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
1791 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
1792 dqm->asic_ops.init_sdma_vm(dqm, q, qpd);
1793 q->properties.tba_addr = qpd->tba_addr;
1794 q->properties.tma_addr = qpd->tma_addr;
1795 q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties);
1796 if (!q->mqd_mem_obj) {
1798 goto out_deallocate_doorbell;
1803 * Eviction state logic: mark all queues as evicted, even ones
1804 * not currently active. Restoring inactive queues later only
1805 * updates the is_evicted flag but is a no-op otherwise.
1807 q->properties.is_evicted = !!qpd->evicted;
1808 q->properties.is_dbg_wa = qpd->pqm->process->debug_trap_enabled &&
1809 KFD_GC_VERSION(q->device) >= IP_VERSION(11, 0, 0) &&
1810 KFD_GC_VERSION(q->device) <= IP_VERSION(11, 0, 3);
1813 mqd_mgr->restore_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, &q->gart_mqd_addr,
1814 &q->properties, restore_mqd, restore_ctl_stack,
1815 qd->ctl_stack_size);
1817 mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj,
1818 &q->gart_mqd_addr, &q->properties);
1820 list_add(&q->list, &qpd->queues_list);
1823 if (q->properties.is_active) {
1824 increment_queue_count(dqm, qpd, q);
1826 if (!dqm->dev->kfd->shared_resources.enable_mes)
1827 retval = execute_queues_cpsch(dqm,
1828 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD);
1830 retval = add_queue_mes(dqm, q, qpd);
1836 * Unconditionally increment this counter, regardless of the queue's
1837 * type or whether the queue is active.
1839 dqm->total_queue_count++;
1841 pr_debug("Total of %d queues are accountable so far\n",
1842 dqm->total_queue_count);
1850 if (q->properties.is_active)
1851 decrement_queue_count(dqm, qpd, q);
1852 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
1854 out_deallocate_doorbell:
1855 deallocate_doorbell(qpd, q);
1856 out_deallocate_sdma_queue:
1857 if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
1858 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
1860 deallocate_sdma_queue(dqm, q);
1867 int amdkfd_fence_wait_timeout(uint64_t *fence_addr,
1868 uint64_t fence_value,
1869 unsigned int timeout_ms)
1871 unsigned long end_jiffies = msecs_to_jiffies(timeout_ms) + jiffies;
1873 while (*fence_addr != fence_value) {
1874 if (time_after(jiffies, end_jiffies)) {
1875 pr_err("qcm fence wait loop timeout expired\n");
1876 /* In HWS case, this is used to halt the driver thread
1877 * in order not to mess up CP states before doing
1878 * scandumps for FW debugging.
1880 while (halt_if_hws_hang)
1891 /* dqm->lock mutex has to be locked before calling this function */
1892 static int map_queues_cpsch(struct device_queue_manager *dqm)
1896 if (!dqm->sched_running)
1898 if (dqm->active_queue_count <= 0 || dqm->processes_count <= 0)
1900 if (dqm->active_runlist)
1903 retval = pm_send_runlist(&dqm->packet_mgr, &dqm->queues);
1904 pr_debug("%s sent runlist\n", __func__);
1906 pr_err("failed to execute runlist\n");
1909 dqm->active_runlist = true;
1914 /* dqm->lock mutex has to be locked before calling this function */
1915 static int unmap_queues_cpsch(struct device_queue_manager *dqm,
1916 enum kfd_unmap_queues_filter filter,
1917 uint32_t filter_param,
1918 uint32_t grace_period,
1922 struct mqd_manager *mqd_mgr;
1924 if (!dqm->sched_running)
1926 if (dqm->is_hws_hang || dqm->is_resetting)
1928 if (!dqm->active_runlist)
1931 if (grace_period != USE_DEFAULT_GRACE_PERIOD) {
1932 retval = pm_update_grace_period(&dqm->packet_mgr, grace_period);
1937 retval = pm_send_unmap_queue(&dqm->packet_mgr, filter, filter_param, reset);
1941 *dqm->fence_addr = KFD_FENCE_INIT;
1942 pm_send_query_status(&dqm->packet_mgr, dqm->fence_gpu_addr,
1943 KFD_FENCE_COMPLETED);
1944 /* should be timed out */
1945 retval = amdkfd_fence_wait_timeout(dqm->fence_addr, KFD_FENCE_COMPLETED,
1946 queue_preemption_timeout_ms);
1948 pr_err("The cp might be in an unrecoverable state due to an unsuccessful queues preemption\n");
1953 /* In the current MEC firmware implementation, if compute queue
1954 * doesn't response to the preemption request in time, HIQ will
1955 * abandon the unmap request without returning any timeout error
1956 * to driver. Instead, MEC firmware will log the doorbell of the
1957 * unresponding compute queue to HIQ.MQD.queue_doorbell_id fields.
1958 * To make sure the queue unmap was successful, driver need to
1959 * check those fields
1961 mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ];
1962 if (mqd_mgr->read_doorbell_id(dqm->packet_mgr.priv_queue->queue->mqd)) {
1963 pr_err("HIQ MQD's queue_doorbell_id0 is not 0, Queue preemption time out\n");
1964 while (halt_if_hws_hang)
1969 /* We need to reset the grace period value for this device */
1970 if (grace_period != USE_DEFAULT_GRACE_PERIOD) {
1971 if (pm_update_grace_period(&dqm->packet_mgr,
1972 USE_DEFAULT_GRACE_PERIOD))
1973 pr_err("Failed to reset grace period\n");
1976 pm_release_ib(&dqm->packet_mgr);
1977 dqm->active_runlist = false;
1982 /* only for compute queue */
1983 static int reset_queues_cpsch(struct device_queue_manager *dqm,
1990 retval = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_BY_PASID,
1991 pasid, USE_DEFAULT_GRACE_PERIOD, true);
1997 /* dqm->lock mutex has to be locked before calling this function */
1998 static int execute_queues_cpsch(struct device_queue_manager *dqm,
1999 enum kfd_unmap_queues_filter filter,
2000 uint32_t filter_param,
2001 uint32_t grace_period)
2005 if (dqm->is_hws_hang)
2007 retval = unmap_queues_cpsch(dqm, filter, filter_param, grace_period, false);
2011 return map_queues_cpsch(dqm);
2014 static int wait_on_destroy_queue(struct device_queue_manager *dqm,
2017 struct kfd_process_device *pdd = kfd_get_process_device_data(q->device,
2021 if (pdd->qpd.is_debug)
2024 q->properties.is_being_destroyed = true;
2026 if (pdd->process->debug_trap_enabled && q->properties.is_suspended) {
2028 mutex_unlock(&q->process->mutex);
2029 ret = wait_event_interruptible(dqm->destroy_wait,
2030 !q->properties.is_suspended);
2032 mutex_lock(&q->process->mutex);
2039 static int destroy_queue_cpsch(struct device_queue_manager *dqm,
2040 struct qcm_process_device *qpd,
2044 struct mqd_manager *mqd_mgr;
2045 uint64_t sdma_val = 0;
2046 struct kfd_process_device *pdd = qpd_to_pdd(qpd);
2048 /* Get the SDMA queue stats */
2049 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) ||
2050 (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) {
2051 retval = read_sdma_queue_counter((uint64_t __user *)q->properties.read_ptr,
2054 pr_err("Failed to read SDMA queue counter for queue: %d\n",
2055 q->properties.queue_id);
2058 /* remove queue from list to prevent rescheduling after preemption */
2061 retval = wait_on_destroy_queue(dqm, q);
2068 if (qpd->is_debug) {
2070 * error, currently we do not allow to destroy a queue
2071 * of a currently debugged process
2074 goto failed_try_destroy_debugged_queue;
2078 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
2079 q->properties.type)];
2081 deallocate_doorbell(qpd, q);
2083 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) ||
2084 (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) {
2085 deallocate_sdma_queue(dqm, q);
2086 pdd->sdma_past_activity_counter += sdma_val;
2091 if (q->properties.is_active) {
2092 decrement_queue_count(dqm, qpd, q);
2093 if (!dqm->dev->kfd->shared_resources.enable_mes) {
2094 retval = execute_queues_cpsch(dqm,
2095 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0,
2096 USE_DEFAULT_GRACE_PERIOD);
2097 if (retval == -ETIME)
2098 qpd->reset_wavefronts = true;
2100 retval = remove_queue_mes(dqm, q, qpd);
2105 * Unconditionally decrement this counter, regardless of the queue's
2108 dqm->total_queue_count--;
2109 pr_debug("Total of %d queues are accountable so far\n",
2110 dqm->total_queue_count);
2115 * Do free_mqd and raise delete event after dqm_unlock(dqm) to avoid
2118 kfd_dbg_ev_raise(KFD_EC_MASK(EC_DEVICE_QUEUE_DELETE),
2119 qpd->pqm->process, q->device,
2120 -1, false, NULL, 0);
2122 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
2126 failed_try_destroy_debugged_queue:
2133 * Low bits must be 0000/FFFF as required by HW, high bits must be 0 to
2134 * stay in user mode.
2136 #define APE1_FIXED_BITS_MASK 0xFFFF80000000FFFFULL
2137 /* APE1 limit is inclusive and 64K aligned. */
2138 #define APE1_LIMIT_ALIGNMENT 0xFFFF
2140 static bool set_cache_memory_policy(struct device_queue_manager *dqm,
2141 struct qcm_process_device *qpd,
2142 enum cache_policy default_policy,
2143 enum cache_policy alternate_policy,
2144 void __user *alternate_aperture_base,
2145 uint64_t alternate_aperture_size)
2149 if (!dqm->asic_ops.set_cache_memory_policy)
2154 if (alternate_aperture_size == 0) {
2155 /* base > limit disables APE1 */
2156 qpd->sh_mem_ape1_base = 1;
2157 qpd->sh_mem_ape1_limit = 0;
2160 * In FSA64, APE1_Base[63:0] = { 16{SH_MEM_APE1_BASE[31]},
2161 * SH_MEM_APE1_BASE[31:0], 0x0000 }
2162 * APE1_Limit[63:0] = { 16{SH_MEM_APE1_LIMIT[31]},
2163 * SH_MEM_APE1_LIMIT[31:0], 0xFFFF }
2164 * Verify that the base and size parameters can be
2165 * represented in this format and convert them.
2166 * Additionally restrict APE1 to user-mode addresses.
2169 uint64_t base = (uintptr_t)alternate_aperture_base;
2170 uint64_t limit = base + alternate_aperture_size - 1;
2172 if (limit <= base || (base & APE1_FIXED_BITS_MASK) != 0 ||
2173 (limit & APE1_FIXED_BITS_MASK) != APE1_LIMIT_ALIGNMENT) {
2178 qpd->sh_mem_ape1_base = base >> 16;
2179 qpd->sh_mem_ape1_limit = limit >> 16;
2182 retval = dqm->asic_ops.set_cache_memory_policy(
2187 alternate_aperture_base,
2188 alternate_aperture_size);
2190 if ((dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) && (qpd->vmid != 0))
2191 program_sh_mem_settings(dqm, qpd);
2193 pr_debug("sh_mem_config: 0x%x, ape1_base: 0x%x, ape1_limit: 0x%x\n",
2194 qpd->sh_mem_config, qpd->sh_mem_ape1_base,
2195 qpd->sh_mem_ape1_limit);
2202 static int process_termination_nocpsch(struct device_queue_manager *dqm,
2203 struct qcm_process_device *qpd)
2206 struct device_process_node *cur, *next_dpn;
2212 /* Clear all user mode queues */
2213 while (!list_empty(&qpd->queues_list)) {
2214 struct mqd_manager *mqd_mgr;
2217 q = list_first_entry(&qpd->queues_list, struct queue, list);
2218 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
2219 q->properties.type)];
2220 ret = destroy_queue_nocpsch_locked(dqm, qpd, q);
2224 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
2228 /* Unregister process */
2229 list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) {
2230 if (qpd == cur->qpd) {
2231 list_del(&cur->list);
2233 dqm->processes_count--;
2241 /* Outside the DQM lock because under the DQM lock we can't do
2242 * reclaim or take other locks that others hold while reclaiming.
2245 kfd_dec_compute_active(dqm->dev);
2250 static int get_wave_state(struct device_queue_manager *dqm,
2252 void __user *ctl_stack,
2253 u32 *ctl_stack_used_size,
2254 u32 *save_area_used_size)
2256 struct mqd_manager *mqd_mgr;
2260 mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_CP];
2262 if (q->properties.type != KFD_QUEUE_TYPE_COMPUTE ||
2263 q->properties.is_active || !q->device->kfd->cwsr_enabled ||
2264 !mqd_mgr->get_wave_state) {
2272 * get_wave_state is outside the dqm lock to prevent circular locking
2273 * and the queue should be protected against destruction by the process
2276 return mqd_mgr->get_wave_state(mqd_mgr, q->mqd, &q->properties,
2277 ctl_stack, ctl_stack_used_size, save_area_used_size);
2280 static void get_queue_checkpoint_info(struct device_queue_manager *dqm,
2281 const struct queue *q,
2283 u32 *ctl_stack_size)
2285 struct mqd_manager *mqd_mgr;
2286 enum KFD_MQD_TYPE mqd_type =
2287 get_mqd_type_from_queue_type(q->properties.type);
2290 mqd_mgr = dqm->mqd_mgrs[mqd_type];
2291 *mqd_size = mqd_mgr->mqd_size;
2292 *ctl_stack_size = 0;
2294 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE && mqd_mgr->get_checkpoint_info)
2295 mqd_mgr->get_checkpoint_info(mqd_mgr, q->mqd, ctl_stack_size);
2300 static int checkpoint_mqd(struct device_queue_manager *dqm,
2301 const struct queue *q,
2305 struct mqd_manager *mqd_mgr;
2307 enum KFD_MQD_TYPE mqd_type =
2308 get_mqd_type_from_queue_type(q->properties.type);
2312 if (q->properties.is_active || !q->device->kfd->cwsr_enabled) {
2317 mqd_mgr = dqm->mqd_mgrs[mqd_type];
2318 if (!mqd_mgr->checkpoint_mqd) {
2323 mqd_mgr->checkpoint_mqd(mqd_mgr, q->mqd, mqd, ctl_stack);
2330 static int process_termination_cpsch(struct device_queue_manager *dqm,
2331 struct qcm_process_device *qpd)
2335 struct kernel_queue *kq, *kq_next;
2336 struct mqd_manager *mqd_mgr;
2337 struct device_process_node *cur, *next_dpn;
2338 enum kfd_unmap_queues_filter filter =
2339 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES;
2346 /* Clean all kernel queues */
2347 list_for_each_entry_safe(kq, kq_next, &qpd->priv_queue_list, list) {
2348 list_del(&kq->list);
2349 decrement_queue_count(dqm, qpd, kq->queue);
2350 qpd->is_debug = false;
2351 dqm->total_queue_count--;
2352 filter = KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES;
2355 /* Clear all user mode queues */
2356 list_for_each_entry(q, &qpd->queues_list, list) {
2357 if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
2358 deallocate_sdma_queue(dqm, q);
2359 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
2360 deallocate_sdma_queue(dqm, q);
2362 if (q->properties.is_active) {
2363 decrement_queue_count(dqm, qpd, q);
2365 if (dqm->dev->kfd->shared_resources.enable_mes) {
2366 retval = remove_queue_mes(dqm, q, qpd);
2368 pr_err("Failed to remove queue %d\n",
2369 q->properties.queue_id);
2373 dqm->total_queue_count--;
2376 /* Unregister process */
2377 list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) {
2378 if (qpd == cur->qpd) {
2379 list_del(&cur->list);
2381 dqm->processes_count--;
2387 if (!dqm->dev->kfd->shared_resources.enable_mes)
2388 retval = execute_queues_cpsch(dqm, filter, 0, USE_DEFAULT_GRACE_PERIOD);
2390 if ((!dqm->is_hws_hang) && (retval || qpd->reset_wavefronts)) {
2391 pr_warn("Resetting wave fronts (cpsch) on dev %p\n", dqm->dev);
2392 dbgdev_wave_reset_wavefronts(dqm->dev, qpd->pqm->process);
2393 qpd->reset_wavefronts = false;
2396 /* Lastly, free mqd resources.
2397 * Do free_mqd() after dqm_unlock to avoid circular locking.
2399 while (!list_empty(&qpd->queues_list)) {
2400 q = list_first_entry(&qpd->queues_list, struct queue, list);
2401 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
2402 q->properties.type)];
2406 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
2411 /* Outside the DQM lock because under the DQM lock we can't do
2412 * reclaim or take other locks that others hold while reclaiming.
2415 kfd_dec_compute_active(dqm->dev);
2420 static int init_mqd_managers(struct device_queue_manager *dqm)
2423 struct mqd_manager *mqd_mgr;
2425 for (i = 0; i < KFD_MQD_TYPE_MAX; i++) {
2426 mqd_mgr = dqm->asic_ops.mqd_manager_init(i, dqm->dev);
2428 pr_err("mqd manager [%d] initialization failed\n", i);
2431 dqm->mqd_mgrs[i] = mqd_mgr;
2437 for (j = 0; j < i; j++) {
2438 kfree(dqm->mqd_mgrs[j]);
2439 dqm->mqd_mgrs[j] = NULL;
2445 /* Allocate one hiq mqd (HWS) and all SDMA mqd in a continuous trunk*/
2446 static int allocate_hiq_sdma_mqd(struct device_queue_manager *dqm)
2449 struct kfd_node *dev = dqm->dev;
2450 struct kfd_mem_obj *mem_obj = &dqm->hiq_sdma_mqd;
2451 uint32_t size = dqm->mqd_mgrs[KFD_MQD_TYPE_SDMA]->mqd_size *
2452 get_num_all_sdma_engines(dqm) *
2453 dev->kfd->device_info.num_sdma_queues_per_engine +
2454 (dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]->mqd_size *
2455 NUM_XCC(dqm->dev->xcc_mask));
2457 retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev, size,
2458 &(mem_obj->gtt_mem), &(mem_obj->gpu_addr),
2459 (void *)&(mem_obj->cpu_ptr), false);
2464 struct device_queue_manager *device_queue_manager_init(struct kfd_node *dev)
2466 struct device_queue_manager *dqm;
2468 pr_debug("Loading device queue manager\n");
2470 dqm = kzalloc(sizeof(*dqm), GFP_KERNEL);
2474 switch (dev->adev->asic_type) {
2475 /* HWS is not available on Hawaii. */
2477 /* HWS depends on CWSR for timely dequeue. CWSR is not
2478 * available on Tonga.
2480 * FIXME: This argument also applies to Kaveri.
2483 dqm->sched_policy = KFD_SCHED_POLICY_NO_HWS;
2486 dqm->sched_policy = sched_policy;
2491 switch (dqm->sched_policy) {
2492 case KFD_SCHED_POLICY_HWS:
2493 case KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION:
2494 /* initialize dqm for cp scheduling */
2495 dqm->ops.create_queue = create_queue_cpsch;
2496 dqm->ops.initialize = initialize_cpsch;
2497 dqm->ops.start = start_cpsch;
2498 dqm->ops.stop = stop_cpsch;
2499 dqm->ops.pre_reset = pre_reset;
2500 dqm->ops.destroy_queue = destroy_queue_cpsch;
2501 dqm->ops.update_queue = update_queue;
2502 dqm->ops.register_process = register_process;
2503 dqm->ops.unregister_process = unregister_process;
2504 dqm->ops.uninitialize = uninitialize;
2505 dqm->ops.create_kernel_queue = create_kernel_queue_cpsch;
2506 dqm->ops.destroy_kernel_queue = destroy_kernel_queue_cpsch;
2507 dqm->ops.set_cache_memory_policy = set_cache_memory_policy;
2508 dqm->ops.process_termination = process_termination_cpsch;
2509 dqm->ops.evict_process_queues = evict_process_queues_cpsch;
2510 dqm->ops.restore_process_queues = restore_process_queues_cpsch;
2511 dqm->ops.get_wave_state = get_wave_state;
2512 dqm->ops.reset_queues = reset_queues_cpsch;
2513 dqm->ops.get_queue_checkpoint_info = get_queue_checkpoint_info;
2514 dqm->ops.checkpoint_mqd = checkpoint_mqd;
2516 case KFD_SCHED_POLICY_NO_HWS:
2517 /* initialize dqm for no cp scheduling */
2518 dqm->ops.start = start_nocpsch;
2519 dqm->ops.stop = stop_nocpsch;
2520 dqm->ops.pre_reset = pre_reset;
2521 dqm->ops.create_queue = create_queue_nocpsch;
2522 dqm->ops.destroy_queue = destroy_queue_nocpsch;
2523 dqm->ops.update_queue = update_queue;
2524 dqm->ops.register_process = register_process;
2525 dqm->ops.unregister_process = unregister_process;
2526 dqm->ops.initialize = initialize_nocpsch;
2527 dqm->ops.uninitialize = uninitialize;
2528 dqm->ops.set_cache_memory_policy = set_cache_memory_policy;
2529 dqm->ops.process_termination = process_termination_nocpsch;
2530 dqm->ops.evict_process_queues = evict_process_queues_nocpsch;
2531 dqm->ops.restore_process_queues =
2532 restore_process_queues_nocpsch;
2533 dqm->ops.get_wave_state = get_wave_state;
2534 dqm->ops.get_queue_checkpoint_info = get_queue_checkpoint_info;
2535 dqm->ops.checkpoint_mqd = checkpoint_mqd;
2538 pr_err("Invalid scheduling policy %d\n", dqm->sched_policy);
2542 switch (dev->adev->asic_type) {
2544 device_queue_manager_init_vi(&dqm->asic_ops);
2548 device_queue_manager_init_cik(&dqm->asic_ops);
2552 device_queue_manager_init_cik_hawaii(&dqm->asic_ops);
2557 case CHIP_POLARIS10:
2558 case CHIP_POLARIS11:
2559 case CHIP_POLARIS12:
2561 device_queue_manager_init_vi_tonga(&dqm->asic_ops);
2565 if (KFD_GC_VERSION(dev) >= IP_VERSION(11, 0, 0))
2566 device_queue_manager_init_v11(&dqm->asic_ops);
2567 else if (KFD_GC_VERSION(dev) >= IP_VERSION(10, 1, 1))
2568 device_queue_manager_init_v10_navi10(&dqm->asic_ops);
2569 else if (KFD_GC_VERSION(dev) >= IP_VERSION(9, 0, 1))
2570 device_queue_manager_init_v9(&dqm->asic_ops);
2572 WARN(1, "Unexpected ASIC family %u",
2573 dev->adev->asic_type);
2578 if (init_mqd_managers(dqm))
2581 if (!dev->kfd->shared_resources.enable_mes && allocate_hiq_sdma_mqd(dqm)) {
2582 pr_err("Failed to allocate hiq sdma mqd trunk buffer\n");
2586 if (!dqm->ops.initialize(dqm)) {
2587 init_waitqueue_head(&dqm->destroy_wait);
2596 static void deallocate_hiq_sdma_mqd(struct kfd_node *dev,
2597 struct kfd_mem_obj *mqd)
2599 WARN(!mqd, "No hiq sdma mqd trunk to free");
2601 amdgpu_amdkfd_free_gtt_mem(dev->adev, mqd->gtt_mem);
2604 void device_queue_manager_uninit(struct device_queue_manager *dqm)
2607 dqm->ops.uninitialize(dqm);
2608 if (!dqm->dev->kfd->shared_resources.enable_mes)
2609 deallocate_hiq_sdma_mqd(dqm->dev, &dqm->hiq_sdma_mqd);
2613 int kfd_dqm_evict_pasid(struct device_queue_manager *dqm, u32 pasid)
2615 struct kfd_process_device *pdd;
2616 struct kfd_process *p = kfd_lookup_process_by_pasid(pasid);
2621 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid);
2622 pdd = kfd_get_process_device_data(dqm->dev, p);
2624 ret = dqm->ops.evict_process_queues(dqm, &pdd->qpd);
2625 kfd_unref_process(p);
2630 static void kfd_process_hw_exception(struct work_struct *work)
2632 struct device_queue_manager *dqm = container_of(work,
2633 struct device_queue_manager, hw_exception_work);
2634 amdgpu_amdkfd_gpu_reset(dqm->dev->adev);
2637 int reserve_debug_trap_vmid(struct device_queue_manager *dqm,
2638 struct qcm_process_device *qpd)
2641 int updated_vmid_mask;
2643 if (dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) {
2644 pr_err("Unsupported on sched_policy: %i\n", dqm->sched_policy);
2650 if (dqm->trap_debug_vmid != 0) {
2651 pr_err("Trap debug id already reserved\n");
2656 r = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0,
2657 USE_DEFAULT_GRACE_PERIOD, false);
2661 updated_vmid_mask = dqm->dev->kfd->shared_resources.compute_vmid_bitmap;
2662 updated_vmid_mask &= ~(1 << dqm->dev->vm_info.last_vmid_kfd);
2664 dqm->dev->kfd->shared_resources.compute_vmid_bitmap = updated_vmid_mask;
2665 dqm->trap_debug_vmid = dqm->dev->vm_info.last_vmid_kfd;
2666 r = set_sched_resources(dqm);
2670 r = map_queues_cpsch(dqm);
2674 pr_debug("Reserved VMID for trap debug: %i\n", dqm->trap_debug_vmid);
2682 * Releases vmid for the trap debugger
2684 int release_debug_trap_vmid(struct device_queue_manager *dqm,
2685 struct qcm_process_device *qpd)
2688 int updated_vmid_mask;
2689 uint32_t trap_debug_vmid;
2691 if (dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) {
2692 pr_err("Unsupported on sched_policy: %i\n", dqm->sched_policy);
2697 trap_debug_vmid = dqm->trap_debug_vmid;
2698 if (dqm->trap_debug_vmid == 0) {
2699 pr_err("Trap debug id is not reserved\n");
2704 r = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0,
2705 USE_DEFAULT_GRACE_PERIOD, false);
2709 updated_vmid_mask = dqm->dev->kfd->shared_resources.compute_vmid_bitmap;
2710 updated_vmid_mask |= (1 << dqm->dev->vm_info.last_vmid_kfd);
2712 dqm->dev->kfd->shared_resources.compute_vmid_bitmap = updated_vmid_mask;
2713 dqm->trap_debug_vmid = 0;
2714 r = set_sched_resources(dqm);
2718 r = map_queues_cpsch(dqm);
2722 pr_debug("Released VMID for trap debug: %i\n", trap_debug_vmid);
2729 #define QUEUE_NOT_FOUND -1
2730 /* invalidate queue operation in array */
2731 static void q_array_invalidate(uint32_t num_queues, uint32_t *queue_ids)
2735 for (i = 0; i < num_queues; i++)
2736 queue_ids[i] |= KFD_DBG_QUEUE_INVALID_MASK;
2739 /* find queue index in array */
2740 static int q_array_get_index(unsigned int queue_id,
2741 uint32_t num_queues,
2742 uint32_t *queue_ids)
2746 for (i = 0; i < num_queues; i++)
2747 if (queue_id == (queue_ids[i] & ~KFD_DBG_QUEUE_INVALID_MASK))
2750 return QUEUE_NOT_FOUND;
2753 struct copy_context_work_handler_workarea {
2754 struct work_struct copy_context_work;
2755 struct kfd_process *p;
2758 static void copy_context_work_handler (struct work_struct *work)
2760 struct copy_context_work_handler_workarea *workarea;
2761 struct mqd_manager *mqd_mgr;
2763 struct mm_struct *mm;
2764 struct kfd_process *p;
2765 uint32_t tmp_ctl_stack_used_size, tmp_save_area_used_size;
2768 workarea = container_of(work,
2769 struct copy_context_work_handler_workarea,
2773 mm = get_task_mm(p->lead_thread);
2779 for (i = 0; i < p->n_pdds; i++) {
2780 struct kfd_process_device *pdd = p->pdds[i];
2781 struct device_queue_manager *dqm = pdd->dev->dqm;
2782 struct qcm_process_device *qpd = &pdd->qpd;
2784 list_for_each_entry(q, &qpd->queues_list, list) {
2785 mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_CP];
2787 /* We ignore the return value from get_wave_state
2789 * i) right now, it always returns 0, and
2790 * ii) if we hit an error, we would continue to the
2791 * next queue anyway.
2793 mqd_mgr->get_wave_state(mqd_mgr,
2796 (void __user *) q->properties.ctx_save_restore_area_address,
2797 &tmp_ctl_stack_used_size,
2798 &tmp_save_area_used_size);
2801 kthread_unuse_mm(mm);
2805 static uint32_t *get_queue_ids(uint32_t num_queues, uint32_t *usr_queue_id_array)
2807 size_t array_size = num_queues * sizeof(uint32_t);
2808 uint32_t *queue_ids = NULL;
2810 if (!usr_queue_id_array)
2813 queue_ids = kzalloc(array_size, GFP_KERNEL);
2815 return ERR_PTR(-ENOMEM);
2817 if (copy_from_user(queue_ids, usr_queue_id_array, array_size))
2818 return ERR_PTR(-EFAULT);
2823 int resume_queues(struct kfd_process *p,
2824 uint32_t num_queues,
2825 uint32_t *usr_queue_id_array)
2827 uint32_t *queue_ids = NULL;
2828 int total_resumed = 0;
2831 if (usr_queue_id_array) {
2832 queue_ids = get_queue_ids(num_queues, usr_queue_id_array);
2834 if (IS_ERR(queue_ids))
2835 return PTR_ERR(queue_ids);
2837 /* mask all queues as invalid. unmask per successful request */
2838 q_array_invalidate(num_queues, queue_ids);
2841 for (i = 0; i < p->n_pdds; i++) {
2842 struct kfd_process_device *pdd = p->pdds[i];
2843 struct device_queue_manager *dqm = pdd->dev->dqm;
2844 struct qcm_process_device *qpd = &pdd->qpd;
2846 int r, per_device_resumed = 0;
2850 /* unmask queues that resume or already resumed as valid */
2851 list_for_each_entry(q, &qpd->queues_list, list) {
2852 int q_idx = QUEUE_NOT_FOUND;
2855 q_idx = q_array_get_index(
2856 q->properties.queue_id,
2860 if (!queue_ids || q_idx != QUEUE_NOT_FOUND) {
2861 int err = resume_single_queue(dqm, &pdd->qpd, q);
2866 ~KFD_DBG_QUEUE_INVALID_MASK;
2869 KFD_DBG_QUEUE_ERROR_MASK;
2874 if (dqm->dev->kfd->shared_resources.enable_mes) {
2875 wake_up_all(&dqm->destroy_wait);
2879 per_device_resumed++;
2884 if (!per_device_resumed) {
2889 r = execute_queues_cpsch(dqm,
2890 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES,
2892 USE_DEFAULT_GRACE_PERIOD);
2894 pr_err("Failed to resume process queues\n");
2896 list_for_each_entry(q, &qpd->queues_list, list) {
2897 int q_idx = q_array_get_index(
2898 q->properties.queue_id,
2902 /* mask queue as error on resume fail */
2903 if (q_idx != QUEUE_NOT_FOUND)
2905 KFD_DBG_QUEUE_ERROR_MASK;
2909 wake_up_all(&dqm->destroy_wait);
2910 total_resumed += per_device_resumed;
2917 if (copy_to_user((void __user *)usr_queue_id_array, queue_ids,
2918 num_queues * sizeof(uint32_t)))
2919 pr_err("copy_to_user failed on queue resume\n");
2924 return total_resumed;
2927 int suspend_queues(struct kfd_process *p,
2928 uint32_t num_queues,
2929 uint32_t grace_period,
2930 uint64_t exception_clear_mask,
2931 uint32_t *usr_queue_id_array)
2933 uint32_t *queue_ids = get_queue_ids(num_queues, usr_queue_id_array);
2934 int total_suspended = 0;
2937 if (IS_ERR(queue_ids))
2938 return PTR_ERR(queue_ids);
2940 /* mask all queues as invalid. umask on successful request */
2941 q_array_invalidate(num_queues, queue_ids);
2943 for (i = 0; i < p->n_pdds; i++) {
2944 struct kfd_process_device *pdd = p->pdds[i];
2945 struct device_queue_manager *dqm = pdd->dev->dqm;
2946 struct qcm_process_device *qpd = &pdd->qpd;
2948 int r, per_device_suspended = 0;
2950 mutex_lock(&p->event_mutex);
2953 /* unmask queues that suspend or already suspended */
2954 list_for_each_entry(q, &qpd->queues_list, list) {
2955 int q_idx = q_array_get_index(q->properties.queue_id,
2959 if (q_idx != QUEUE_NOT_FOUND) {
2960 int err = suspend_single_queue(dqm, pdd, q);
2961 bool is_mes = dqm->dev->kfd->shared_resources.enable_mes;
2964 queue_ids[q_idx] &= ~KFD_DBG_QUEUE_INVALID_MASK;
2965 if (exception_clear_mask && is_mes)
2966 q->properties.exception_status &=
2967 ~exception_clear_mask;
2972 per_device_suspended++;
2973 } else if (err != -EBUSY) {
2975 queue_ids[q_idx] |= KFD_DBG_QUEUE_ERROR_MASK;
2981 if (!per_device_suspended) {
2983 mutex_unlock(&p->event_mutex);
2984 if (total_suspended)
2985 amdgpu_amdkfd_debug_mem_fence(dqm->dev->adev);
2989 r = execute_queues_cpsch(dqm,
2990 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0,
2994 pr_err("Failed to suspend process queues.\n");
2996 total_suspended += per_device_suspended;
2998 list_for_each_entry(q, &qpd->queues_list, list) {
2999 int q_idx = q_array_get_index(q->properties.queue_id,
3000 num_queues, queue_ids);
3002 if (q_idx == QUEUE_NOT_FOUND)
3005 /* mask queue as error on suspend fail */
3007 queue_ids[q_idx] |= KFD_DBG_QUEUE_ERROR_MASK;
3008 else if (exception_clear_mask)
3009 q->properties.exception_status &=
3010 ~exception_clear_mask;
3014 mutex_unlock(&p->event_mutex);
3015 amdgpu_device_flush_hdp(dqm->dev->adev, NULL);
3018 if (total_suspended) {
3019 struct copy_context_work_handler_workarea copy_context_worker;
3022 ©_context_worker.copy_context_work,
3023 copy_context_work_handler);
3025 copy_context_worker.p = p;
3027 schedule_work(©_context_worker.copy_context_work);
3030 flush_work(©_context_worker.copy_context_work);
3031 destroy_work_on_stack(©_context_worker.copy_context_work);
3034 if (copy_to_user((void __user *)usr_queue_id_array, queue_ids,
3035 num_queues * sizeof(uint32_t)))
3036 pr_err("copy_to_user failed on queue suspend\n");
3040 return total_suspended;
3043 static uint32_t set_queue_type_for_user(struct queue_properties *q_props)
3045 switch (q_props->type) {
3046 case KFD_QUEUE_TYPE_COMPUTE:
3047 return q_props->format == KFD_QUEUE_FORMAT_PM4
3048 ? KFD_IOC_QUEUE_TYPE_COMPUTE
3049 : KFD_IOC_QUEUE_TYPE_COMPUTE_AQL;
3050 case KFD_QUEUE_TYPE_SDMA:
3051 return KFD_IOC_QUEUE_TYPE_SDMA;
3052 case KFD_QUEUE_TYPE_SDMA_XGMI:
3053 return KFD_IOC_QUEUE_TYPE_SDMA_XGMI;
3055 WARN_ONCE(true, "queue type not recognized!");
3060 void set_queue_snapshot_entry(struct queue *q,
3061 uint64_t exception_clear_mask,
3062 struct kfd_queue_snapshot_entry *qss_entry)
3064 qss_entry->ring_base_address = q->properties.queue_address;
3065 qss_entry->write_pointer_address = (uint64_t)q->properties.write_ptr;
3066 qss_entry->read_pointer_address = (uint64_t)q->properties.read_ptr;
3067 qss_entry->ctx_save_restore_address =
3068 q->properties.ctx_save_restore_area_address;
3069 qss_entry->ctx_save_restore_area_size =
3070 q->properties.ctx_save_restore_area_size;
3071 qss_entry->exception_status = q->properties.exception_status;
3072 qss_entry->queue_id = q->properties.queue_id;
3073 qss_entry->gpu_id = q->device->id;
3074 qss_entry->ring_size = (uint32_t)q->properties.queue_size;
3075 qss_entry->queue_type = set_queue_type_for_user(&q->properties);
3076 q->properties.exception_status &= ~exception_clear_mask;
3079 int debug_lock_and_unmap(struct device_queue_manager *dqm)
3083 if (dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) {
3084 pr_err("Unsupported on sched_policy: %i\n", dqm->sched_policy);
3088 if (!kfd_dbg_is_per_vmid_supported(dqm->dev))
3093 r = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, 0, false);
3100 int debug_map_and_unlock(struct device_queue_manager *dqm)
3104 if (dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) {
3105 pr_err("Unsupported on sched_policy: %i\n", dqm->sched_policy);
3109 if (!kfd_dbg_is_per_vmid_supported(dqm->dev))
3112 r = map_queues_cpsch(dqm);
3119 int debug_refresh_runlist(struct device_queue_manager *dqm)
3121 int r = debug_lock_and_unmap(dqm);
3126 return debug_map_and_unlock(dqm);
3129 #if defined(CONFIG_DEBUG_FS)
3131 static void seq_reg_dump(struct seq_file *m,
3132 uint32_t (*dump)[2], uint32_t n_regs)
3136 for (i = 0, count = 0; i < n_regs; i++) {
3138 dump[i-1][0] + sizeof(uint32_t) != dump[i][0]) {
3139 seq_printf(m, "%s %08x: %08x",
3141 dump[i][0], dump[i][1]);
3144 seq_printf(m, " %08x", dump[i][1]);
3152 int dqm_debugfs_hqds(struct seq_file *m, void *data)
3154 struct device_queue_manager *dqm = data;
3155 uint32_t xcc_mask = dqm->dev->xcc_mask;
3156 uint32_t (*dump)[2], n_regs;
3159 uint32_t sdma_engine_start;
3161 if (!dqm->sched_running) {
3162 seq_puts(m, " Device is stopped\n");
3166 for_each_inst(xcc_id, xcc_mask) {
3167 r = dqm->dev->kfd2kgd->hqd_dump(dqm->dev->adev,
3169 KFD_CIK_HIQ_QUEUE, &dump,
3174 " Inst %d, HIQ on MEC %d Pipe %d Queue %d\n",
3176 KFD_CIK_HIQ_PIPE / get_pipes_per_mec(dqm) + 1,
3177 KFD_CIK_HIQ_PIPE % get_pipes_per_mec(dqm),
3179 seq_reg_dump(m, dump, n_regs);
3184 for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) {
3185 int pipe_offset = pipe * get_queues_per_pipe(dqm);
3187 for (queue = 0; queue < get_queues_per_pipe(dqm); queue++) {
3188 if (!test_bit(pipe_offset + queue,
3189 dqm->dev->kfd->shared_resources.cp_queue_bitmap))
3192 r = dqm->dev->kfd2kgd->hqd_dump(dqm->dev->adev,
3200 " Inst %d, CP Pipe %d, Queue %d\n",
3201 xcc_id, pipe, queue);
3202 seq_reg_dump(m, dump, n_regs);
3209 sdma_engine_start = dqm->dev->node_id * get_num_all_sdma_engines(dqm);
3210 for (pipe = sdma_engine_start;
3211 pipe < (sdma_engine_start + get_num_all_sdma_engines(dqm));
3214 queue < dqm->dev->kfd->device_info.num_sdma_queues_per_engine;
3216 r = dqm->dev->kfd2kgd->hqd_sdma_dump(
3217 dqm->dev->adev, pipe, queue, &dump, &n_regs);
3221 seq_printf(m, " SDMA Engine %d, RLC %d\n",
3223 seq_reg_dump(m, dump, n_regs);
3232 int dqm_debugfs_hang_hws(struct device_queue_manager *dqm)
3237 r = pm_debugfs_hang_hws(&dqm->packet_mgr);
3242 dqm->active_runlist = true;
3243 r = execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES,
3244 0, USE_DEFAULT_GRACE_PERIOD);