1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <linux/ratelimit.h>
26 #include <linux/printk.h>
27 #include <linux/slab.h>
28 #include <linux/list.h>
29 #include <linux/types.h>
30 #include <linux/bitops.h>
31 #include <linux/sched.h>
33 #include "kfd_device_queue_manager.h"
34 #include "kfd_mqd_manager.h"
36 #include "kfd_kernel_queue.h"
37 #include "amdgpu_amdkfd.h"
38 #include "mes_api_def.h"
39 #include "kfd_debug.h"
41 /* Size of the per-pipe EOP queue */
42 #define CIK_HPD_EOP_BYTES_LOG2 11
43 #define CIK_HPD_EOP_BYTES (1U << CIK_HPD_EOP_BYTES_LOG2)
45 static int set_pasid_vmid_mapping(struct device_queue_manager *dqm,
46 u32 pasid, unsigned int vmid);
48 static int execute_queues_cpsch(struct device_queue_manager *dqm,
49 enum kfd_unmap_queues_filter filter,
50 uint32_t filter_param,
51 uint32_t grace_period);
52 static int unmap_queues_cpsch(struct device_queue_manager *dqm,
53 enum kfd_unmap_queues_filter filter,
54 uint32_t filter_param,
55 uint32_t grace_period,
58 static int map_queues_cpsch(struct device_queue_manager *dqm);
60 static void deallocate_sdma_queue(struct device_queue_manager *dqm,
63 static inline void deallocate_hqd(struct device_queue_manager *dqm,
65 static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q);
66 static int allocate_sdma_queue(struct device_queue_manager *dqm,
67 struct queue *q, const uint32_t *restore_sdma_id);
68 static void kfd_process_hw_exception(struct work_struct *work);
71 enum KFD_MQD_TYPE get_mqd_type_from_queue_type(enum kfd_queue_type type)
73 if (type == KFD_QUEUE_TYPE_SDMA || type == KFD_QUEUE_TYPE_SDMA_XGMI)
74 return KFD_MQD_TYPE_SDMA;
75 return KFD_MQD_TYPE_CP;
78 static bool is_pipe_enabled(struct device_queue_manager *dqm, int mec, int pipe)
81 int pipe_offset = (mec * dqm->dev->kfd->shared_resources.num_pipe_per_mec
82 + pipe) * dqm->dev->kfd->shared_resources.num_queue_per_pipe;
84 /* queue is available for KFD usage if bit is 1 */
85 for (i = 0; i < dqm->dev->kfd->shared_resources.num_queue_per_pipe; ++i)
86 if (test_bit(pipe_offset + i,
87 dqm->dev->kfd->shared_resources.cp_queue_bitmap))
92 unsigned int get_cp_queues_num(struct device_queue_manager *dqm)
94 return bitmap_weight(dqm->dev->kfd->shared_resources.cp_queue_bitmap,
98 unsigned int get_queues_per_pipe(struct device_queue_manager *dqm)
100 return dqm->dev->kfd->shared_resources.num_queue_per_pipe;
103 unsigned int get_pipes_per_mec(struct device_queue_manager *dqm)
105 return dqm->dev->kfd->shared_resources.num_pipe_per_mec;
108 static unsigned int get_num_all_sdma_engines(struct device_queue_manager *dqm)
110 return kfd_get_num_sdma_engines(dqm->dev) +
111 kfd_get_num_xgmi_sdma_engines(dqm->dev);
114 unsigned int get_num_sdma_queues(struct device_queue_manager *dqm)
116 return kfd_get_num_sdma_engines(dqm->dev) *
117 dqm->dev->kfd->device_info.num_sdma_queues_per_engine;
120 unsigned int get_num_xgmi_sdma_queues(struct device_queue_manager *dqm)
122 return kfd_get_num_xgmi_sdma_engines(dqm->dev) *
123 dqm->dev->kfd->device_info.num_sdma_queues_per_engine;
126 static void init_sdma_bitmaps(struct device_queue_manager *dqm)
128 bitmap_zero(dqm->sdma_bitmap, KFD_MAX_SDMA_QUEUES);
129 bitmap_set(dqm->sdma_bitmap, 0, get_num_sdma_queues(dqm));
131 bitmap_zero(dqm->xgmi_sdma_bitmap, KFD_MAX_SDMA_QUEUES);
132 bitmap_set(dqm->xgmi_sdma_bitmap, 0, get_num_xgmi_sdma_queues(dqm));
134 /* Mask out the reserved queues */
135 bitmap_andnot(dqm->sdma_bitmap, dqm->sdma_bitmap,
136 dqm->dev->kfd->device_info.reserved_sdma_queues_bitmap,
137 KFD_MAX_SDMA_QUEUES);
140 void program_sh_mem_settings(struct device_queue_manager *dqm,
141 struct qcm_process_device *qpd)
143 uint32_t xcc_mask = dqm->dev->xcc_mask;
146 for_each_inst(xcc_id, xcc_mask)
147 dqm->dev->kfd2kgd->program_sh_mem_settings(
148 dqm->dev->adev, qpd->vmid, qpd->sh_mem_config,
149 qpd->sh_mem_ape1_base, qpd->sh_mem_ape1_limit,
150 qpd->sh_mem_bases, xcc_id);
153 static void kfd_hws_hang(struct device_queue_manager *dqm)
156 * Issue a GPU reset if HWS is unresponsive
158 dqm->is_hws_hang = true;
160 /* It's possible we're detecting a HWS hang in the
161 * middle of a GPU reset. No need to schedule another
162 * reset in this case.
164 if (!dqm->is_resetting)
165 schedule_work(&dqm->hw_exception_work);
168 static int convert_to_mes_queue_type(int queue_type)
172 switch (queue_type) {
173 case KFD_QUEUE_TYPE_COMPUTE:
174 mes_queue_type = MES_QUEUE_TYPE_COMPUTE;
176 case KFD_QUEUE_TYPE_SDMA:
177 mes_queue_type = MES_QUEUE_TYPE_SDMA;
180 WARN(1, "Invalid queue type %d", queue_type);
181 mes_queue_type = -EINVAL;
185 return mes_queue_type;
188 static int add_queue_mes(struct device_queue_manager *dqm, struct queue *q,
189 struct qcm_process_device *qpd)
191 struct amdgpu_device *adev = (struct amdgpu_device *)dqm->dev->adev;
192 struct kfd_process_device *pdd = qpd_to_pdd(qpd);
193 struct mes_add_queue_input queue_input;
195 uint64_t wptr_addr_off;
197 if (dqm->is_hws_hang)
200 memset(&queue_input, 0x0, sizeof(struct mes_add_queue_input));
201 queue_input.process_id = qpd->pqm->process->pasid;
202 queue_input.page_table_base_addr = qpd->page_table_base;
203 queue_input.process_va_start = 0;
204 queue_input.process_va_end = adev->vm_manager.max_pfn - 1;
205 /* MES unit for quantum is 100ns */
206 queue_input.process_quantum = KFD_MES_PROCESS_QUANTUM; /* Equivalent to 10ms. */
207 queue_input.process_context_addr = pdd->proc_ctx_gpu_addr;
208 queue_input.gang_quantum = KFD_MES_GANG_QUANTUM; /* Equivalent to 1ms */
209 queue_input.gang_context_addr = q->gang_ctx_gpu_addr;
210 queue_input.inprocess_gang_priority = q->properties.priority;
211 queue_input.gang_global_priority_level =
212 AMDGPU_MES_PRIORITY_LEVEL_NORMAL;
213 queue_input.doorbell_offset = q->properties.doorbell_off;
214 queue_input.mqd_addr = q->gart_mqd_addr;
215 queue_input.wptr_addr = (uint64_t)q->properties.write_ptr;
218 wptr_addr_off = (uint64_t)q->properties.write_ptr & (PAGE_SIZE - 1);
219 queue_input.wptr_mc_addr = ((uint64_t)q->wptr_bo->tbo.resource->start << PAGE_SHIFT) + wptr_addr_off;
222 queue_input.is_kfd_process = 1;
223 queue_input.is_aql_queue = (q->properties.format == KFD_QUEUE_FORMAT_AQL);
224 queue_input.queue_size = q->properties.queue_size >> 2;
226 queue_input.paging = false;
227 queue_input.tba_addr = qpd->tba_addr;
228 queue_input.tma_addr = qpd->tma_addr;
229 queue_input.trap_en = !kfd_dbg_has_cwsr_workaround(q->device);
230 queue_input.skip_process_ctx_clear = qpd->pqm->process->debug_trap_enabled;
232 queue_type = convert_to_mes_queue_type(q->properties.type);
233 if (queue_type < 0) {
234 pr_err("Queue type not supported with MES, queue:%d\n",
238 queue_input.queue_type = (uint32_t)queue_type;
241 queue_input.gws_base = 0;
242 queue_input.gws_size = qpd->num_gws;
245 amdgpu_mes_lock(&adev->mes);
246 r = adev->mes.funcs->add_hw_queue(&adev->mes, &queue_input);
247 amdgpu_mes_unlock(&adev->mes);
249 pr_err("failed to add hardware queue to MES, doorbell=0x%x\n",
250 q->properties.doorbell_off);
251 pr_err("MES might be in unrecoverable state, issue a GPU reset\n");
258 static int remove_queue_mes(struct device_queue_manager *dqm, struct queue *q,
259 struct qcm_process_device *qpd)
261 struct amdgpu_device *adev = (struct amdgpu_device *)dqm->dev->adev;
263 struct mes_remove_queue_input queue_input;
265 if (dqm->is_hws_hang)
268 memset(&queue_input, 0x0, sizeof(struct mes_remove_queue_input));
269 queue_input.doorbell_offset = q->properties.doorbell_off;
270 queue_input.gang_context_addr = q->gang_ctx_gpu_addr;
272 amdgpu_mes_lock(&adev->mes);
273 r = adev->mes.funcs->remove_hw_queue(&adev->mes, &queue_input);
274 amdgpu_mes_unlock(&adev->mes);
277 pr_err("failed to remove hardware queue from MES, doorbell=0x%x\n",
278 q->properties.doorbell_off);
279 pr_err("MES might be in unrecoverable state, issue a GPU reset\n");
286 static int remove_all_queues_mes(struct device_queue_manager *dqm)
288 struct device_process_node *cur;
289 struct qcm_process_device *qpd;
293 list_for_each_entry(cur, &dqm->queues, list) {
295 list_for_each_entry(q, &qpd->queues_list, list) {
296 if (q->properties.is_active) {
297 retval = remove_queue_mes(dqm, q, qpd);
299 pr_err("%s: Failed to remove queue %d for dev %d",
301 q->properties.queue_id,
312 static void increment_queue_count(struct device_queue_manager *dqm,
313 struct qcm_process_device *qpd,
316 dqm->active_queue_count++;
317 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
318 q->properties.type == KFD_QUEUE_TYPE_DIQ)
319 dqm->active_cp_queue_count++;
321 if (q->properties.is_gws) {
322 dqm->gws_queue_count++;
323 qpd->mapped_gws_queue = true;
327 static void decrement_queue_count(struct device_queue_manager *dqm,
328 struct qcm_process_device *qpd,
331 dqm->active_queue_count--;
332 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
333 q->properties.type == KFD_QUEUE_TYPE_DIQ)
334 dqm->active_cp_queue_count--;
336 if (q->properties.is_gws) {
337 dqm->gws_queue_count--;
338 qpd->mapped_gws_queue = false;
343 * Allocate a doorbell ID to this queue.
344 * If doorbell_id is passed in, make sure requested ID is valid then allocate it.
346 static int allocate_doorbell(struct qcm_process_device *qpd,
348 uint32_t const *restore_id)
350 struct kfd_node *dev = qpd->dqm->dev;
352 if (!KFD_IS_SOC15(dev)) {
353 /* On pre-SOC15 chips we need to use the queue ID to
354 * preserve the user mode ABI.
357 if (restore_id && *restore_id != q->properties.queue_id)
360 q->doorbell_id = q->properties.queue_id;
361 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
362 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
363 /* For SDMA queues on SOC15 with 8-byte doorbell, use static
364 * doorbell assignments based on the engine and queue id.
365 * The doobell index distance between RLC (2*i) and (2*i+1)
366 * for a SDMA engine is 512.
369 uint32_t *idx_offset = dev->kfd->shared_resources.sdma_doorbell_idx;
372 * q->properties.sdma_engine_id corresponds to the virtual
373 * sdma engine number. However, for doorbell allocation,
374 * we need the physical sdma engine id in order to get the
375 * correct doorbell offset.
377 uint32_t valid_id = idx_offset[qpd->dqm->dev->node_id *
378 get_num_all_sdma_engines(qpd->dqm) +
379 q->properties.sdma_engine_id]
380 + (q->properties.sdma_queue_id & 1)
381 * KFD_QUEUE_DOORBELL_MIRROR_OFFSET
382 + (q->properties.sdma_queue_id >> 1);
384 if (restore_id && *restore_id != valid_id)
386 q->doorbell_id = valid_id;
388 /* For CP queues on SOC15 */
390 /* make sure that ID is free */
391 if (__test_and_set_bit(*restore_id, qpd->doorbell_bitmap))
394 q->doorbell_id = *restore_id;
396 /* or reserve a free doorbell ID */
399 found = find_first_zero_bit(qpd->doorbell_bitmap,
400 KFD_MAX_NUM_OF_QUEUES_PER_PROCESS);
401 if (found >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) {
402 pr_debug("No doorbells available");
405 set_bit(found, qpd->doorbell_bitmap);
406 q->doorbell_id = found;
410 q->properties.doorbell_off =
411 kfd_get_doorbell_dw_offset_in_bar(dev->kfd, qpd_to_pdd(qpd),
416 static void deallocate_doorbell(struct qcm_process_device *qpd,
420 struct kfd_node *dev = qpd->dqm->dev;
422 if (!KFD_IS_SOC15(dev) ||
423 q->properties.type == KFD_QUEUE_TYPE_SDMA ||
424 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
427 old = test_and_clear_bit(q->doorbell_id, qpd->doorbell_bitmap);
431 static void program_trap_handler_settings(struct device_queue_manager *dqm,
432 struct qcm_process_device *qpd)
434 uint32_t xcc_mask = dqm->dev->xcc_mask;
437 if (dqm->dev->kfd2kgd->program_trap_handler_settings)
438 for_each_inst(xcc_id, xcc_mask)
439 dqm->dev->kfd2kgd->program_trap_handler_settings(
440 dqm->dev->adev, qpd->vmid, qpd->tba_addr,
441 qpd->tma_addr, xcc_id);
444 static int allocate_vmid(struct device_queue_manager *dqm,
445 struct qcm_process_device *qpd,
448 int allocated_vmid = -1, i;
450 for (i = dqm->dev->vm_info.first_vmid_kfd;
451 i <= dqm->dev->vm_info.last_vmid_kfd; i++) {
452 if (!dqm->vmid_pasid[i]) {
458 if (allocated_vmid < 0) {
459 pr_err("no more vmid to allocate\n");
463 pr_debug("vmid allocated: %d\n", allocated_vmid);
465 dqm->vmid_pasid[allocated_vmid] = q->process->pasid;
467 set_pasid_vmid_mapping(dqm, q->process->pasid, allocated_vmid);
469 qpd->vmid = allocated_vmid;
470 q->properties.vmid = allocated_vmid;
472 program_sh_mem_settings(dqm, qpd);
474 if (KFD_IS_SOC15(dqm->dev) && dqm->dev->kfd->cwsr_enabled)
475 program_trap_handler_settings(dqm, qpd);
477 /* qpd->page_table_base is set earlier when register_process()
478 * is called, i.e. when the first queue is created.
480 dqm->dev->kfd2kgd->set_vm_context_page_table_base(dqm->dev->adev,
482 qpd->page_table_base);
483 /* invalidate the VM context after pasid and vmid mapping is set up */
484 kfd_flush_tlb(qpd_to_pdd(qpd), TLB_FLUSH_LEGACY);
486 if (dqm->dev->kfd2kgd->set_scratch_backing_va)
487 dqm->dev->kfd2kgd->set_scratch_backing_va(dqm->dev->adev,
488 qpd->sh_hidden_private_base, qpd->vmid);
493 static int flush_texture_cache_nocpsch(struct kfd_node *kdev,
494 struct qcm_process_device *qpd)
496 const struct packet_manager_funcs *pmf = qpd->dqm->packet_mgr.pmf;
502 ret = pmf->release_mem(qpd->ib_base, (uint32_t *)qpd->ib_kaddr);
506 return amdgpu_amdkfd_submit_ib(kdev->adev, KGD_ENGINE_MEC1, qpd->vmid,
507 qpd->ib_base, (uint32_t *)qpd->ib_kaddr,
508 pmf->release_mem_size / sizeof(uint32_t));
511 static void deallocate_vmid(struct device_queue_manager *dqm,
512 struct qcm_process_device *qpd,
515 /* On GFX v7, CP doesn't flush TC at dequeue */
516 if (q->device->adev->asic_type == CHIP_HAWAII)
517 if (flush_texture_cache_nocpsch(q->device, qpd))
518 pr_err("Failed to flush TC\n");
520 kfd_flush_tlb(qpd_to_pdd(qpd), TLB_FLUSH_LEGACY);
522 /* Release the vmid mapping */
523 set_pasid_vmid_mapping(dqm, 0, qpd->vmid);
524 dqm->vmid_pasid[qpd->vmid] = 0;
527 q->properties.vmid = 0;
530 static int create_queue_nocpsch(struct device_queue_manager *dqm,
532 struct qcm_process_device *qpd,
533 const struct kfd_criu_queue_priv_data *qd,
534 const void *restore_mqd, const void *restore_ctl_stack)
536 struct mqd_manager *mqd_mgr;
541 if (dqm->total_queue_count >= max_num_of_queues_per_device) {
542 pr_warn("Can't create new usermode queue because %d queues were already created\n",
543 dqm->total_queue_count);
548 if (list_empty(&qpd->queues_list)) {
549 retval = allocate_vmid(dqm, qpd, q);
553 q->properties.vmid = qpd->vmid;
555 * Eviction state logic: mark all queues as evicted, even ones
556 * not currently active. Restoring inactive queues later only
557 * updates the is_evicted flag but is a no-op otherwise.
559 q->properties.is_evicted = !!qpd->evicted;
561 q->properties.tba_addr = qpd->tba_addr;
562 q->properties.tma_addr = qpd->tma_addr;
564 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
565 q->properties.type)];
566 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) {
567 retval = allocate_hqd(dqm, q);
569 goto deallocate_vmid;
570 pr_debug("Loading mqd to hqd on pipe %d, queue %d\n",
572 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
573 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
574 retval = allocate_sdma_queue(dqm, q, qd ? &qd->sdma_id : NULL);
576 goto deallocate_vmid;
577 dqm->asic_ops.init_sdma_vm(dqm, q, qpd);
580 retval = allocate_doorbell(qpd, q, qd ? &qd->doorbell_id : NULL);
582 goto out_deallocate_hqd;
584 /* Temporarily release dqm lock to avoid a circular lock dependency */
586 q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties);
589 if (!q->mqd_mem_obj) {
591 goto out_deallocate_doorbell;
595 mqd_mgr->restore_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, &q->gart_mqd_addr,
596 &q->properties, restore_mqd, restore_ctl_stack,
599 mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj,
600 &q->gart_mqd_addr, &q->properties);
602 if (q->properties.is_active) {
603 if (!dqm->sched_running) {
604 WARN_ONCE(1, "Load non-HWS mqd while stopped\n");
605 goto add_queue_to_list;
608 if (WARN(q->process->mm != current->mm,
609 "should only run in user thread"))
612 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe,
613 q->queue, &q->properties, current->mm);
619 list_add(&q->list, &qpd->queues_list);
621 if (q->properties.is_active)
622 increment_queue_count(dqm, qpd, q);
625 * Unconditionally increment this counter, regardless of the queue's
626 * type or whether the queue is active.
628 dqm->total_queue_count++;
629 pr_debug("Total of %d queues are accountable so far\n",
630 dqm->total_queue_count);
634 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
635 out_deallocate_doorbell:
636 deallocate_doorbell(qpd, q);
638 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE)
639 deallocate_hqd(dqm, q);
640 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
641 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
642 deallocate_sdma_queue(dqm, q);
644 if (list_empty(&qpd->queues_list))
645 deallocate_vmid(dqm, qpd, q);
651 static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q)
658 for (pipe = dqm->next_pipe_to_allocate, i = 0;
659 i < get_pipes_per_mec(dqm);
660 pipe = ((pipe + 1) % get_pipes_per_mec(dqm)), ++i) {
662 if (!is_pipe_enabled(dqm, 0, pipe))
665 if (dqm->allocated_queues[pipe] != 0) {
666 bit = ffs(dqm->allocated_queues[pipe]) - 1;
667 dqm->allocated_queues[pipe] &= ~(1 << bit);
678 pr_debug("hqd slot - pipe %d, queue %d\n", q->pipe, q->queue);
679 /* horizontal hqd allocation */
680 dqm->next_pipe_to_allocate = (pipe + 1) % get_pipes_per_mec(dqm);
685 static inline void deallocate_hqd(struct device_queue_manager *dqm,
688 dqm->allocated_queues[q->pipe] |= (1 << q->queue);
691 #define SQ_IND_CMD_CMD_KILL 0x00000003
692 #define SQ_IND_CMD_MODE_BROADCAST 0x00000001
694 static int dbgdev_wave_reset_wavefronts(struct kfd_node *dev, struct kfd_process *p)
698 uint16_t queried_pasid;
699 union SQ_CMD_BITS reg_sq_cmd;
700 union GRBM_GFX_INDEX_BITS reg_gfx_index;
701 struct kfd_process_device *pdd;
702 int first_vmid_to_scan = dev->vm_info.first_vmid_kfd;
703 int last_vmid_to_scan = dev->vm_info.last_vmid_kfd;
704 uint32_t xcc_mask = dev->xcc_mask;
707 reg_sq_cmd.u32All = 0;
708 reg_gfx_index.u32All = 0;
710 pr_debug("Killing all process wavefronts\n");
712 if (!dev->kfd2kgd->get_atc_vmid_pasid_mapping_info) {
713 pr_err("no vmid pasid mapping supported \n");
717 /* Scan all registers in the range ATC_VMID8_PASID_MAPPING ..
718 * ATC_VMID15_PASID_MAPPING
719 * to check which VMID the current process is mapped to.
722 for (vmid = first_vmid_to_scan; vmid <= last_vmid_to_scan; vmid++) {
723 status = dev->kfd2kgd->get_atc_vmid_pasid_mapping_info
724 (dev->adev, vmid, &queried_pasid);
726 if (status && queried_pasid == p->pasid) {
727 pr_debug("Killing wave fronts of vmid %d and pasid 0x%x\n",
733 if (vmid > last_vmid_to_scan) {
734 pr_err("Didn't find vmid for pasid 0x%x\n", p->pasid);
738 /* taking the VMID for that process on the safe way using PDD */
739 pdd = kfd_get_process_device_data(dev, p);
743 reg_gfx_index.bits.sh_broadcast_writes = 1;
744 reg_gfx_index.bits.se_broadcast_writes = 1;
745 reg_gfx_index.bits.instance_broadcast_writes = 1;
746 reg_sq_cmd.bits.mode = SQ_IND_CMD_MODE_BROADCAST;
747 reg_sq_cmd.bits.cmd = SQ_IND_CMD_CMD_KILL;
748 reg_sq_cmd.bits.vm_id = vmid;
750 for_each_inst(xcc_id, xcc_mask)
751 dev->kfd2kgd->wave_control_execute(
752 dev->adev, reg_gfx_index.u32All,
753 reg_sq_cmd.u32All, xcc_id);
758 /* Access to DQM has to be locked before calling destroy_queue_nocpsch_locked
759 * to avoid asynchronized access
761 static int destroy_queue_nocpsch_locked(struct device_queue_manager *dqm,
762 struct qcm_process_device *qpd,
766 struct mqd_manager *mqd_mgr;
768 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
769 q->properties.type)];
771 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE)
772 deallocate_hqd(dqm, q);
773 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
774 deallocate_sdma_queue(dqm, q);
775 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
776 deallocate_sdma_queue(dqm, q);
778 pr_debug("q->properties.type %d is invalid\n",
782 dqm->total_queue_count--;
784 deallocate_doorbell(qpd, q);
786 if (!dqm->sched_running) {
787 WARN_ONCE(1, "Destroy non-HWS queue while stopped\n");
791 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd,
792 KFD_PREEMPT_TYPE_WAVEFRONT_RESET,
793 KFD_UNMAP_LATENCY_MS,
795 if (retval == -ETIME)
796 qpd->reset_wavefronts = true;
799 if (list_empty(&qpd->queues_list)) {
800 if (qpd->reset_wavefronts) {
801 pr_warn("Resetting wave fronts (nocpsch) on dev %p\n",
803 /* dbgdev_wave_reset_wavefronts has to be called before
804 * deallocate_vmid(), i.e. when vmid is still in use.
806 dbgdev_wave_reset_wavefronts(dqm->dev,
808 qpd->reset_wavefronts = false;
811 deallocate_vmid(dqm, qpd, q);
814 if (q->properties.is_active)
815 decrement_queue_count(dqm, qpd, q);
820 static int destroy_queue_nocpsch(struct device_queue_manager *dqm,
821 struct qcm_process_device *qpd,
825 uint64_t sdma_val = 0;
826 struct kfd_process_device *pdd = qpd_to_pdd(qpd);
827 struct mqd_manager *mqd_mgr =
828 dqm->mqd_mgrs[get_mqd_type_from_queue_type(q->properties.type)];
830 /* Get the SDMA queue stats */
831 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) ||
832 (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) {
833 retval = read_sdma_queue_counter((uint64_t __user *)q->properties.read_ptr,
836 pr_err("Failed to read SDMA queue counter for queue: %d\n",
837 q->properties.queue_id);
841 retval = destroy_queue_nocpsch_locked(dqm, qpd, q);
843 pdd->sdma_past_activity_counter += sdma_val;
846 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
851 static int update_queue(struct device_queue_manager *dqm, struct queue *q,
852 struct mqd_update_info *minfo)
855 struct mqd_manager *mqd_mgr;
856 struct kfd_process_device *pdd;
857 bool prev_active = false;
860 pdd = kfd_get_process_device_data(q->device, q->process);
865 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
866 q->properties.type)];
868 /* Save previous activity state for counters */
869 prev_active = q->properties.is_active;
871 /* Make sure the queue is unmapped before updating the MQD */
872 if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) {
873 if (!dqm->dev->kfd->shared_resources.enable_mes)
874 retval = unmap_queues_cpsch(dqm,
875 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD, false);
876 else if (prev_active)
877 retval = remove_queue_mes(dqm, q, &pdd->qpd);
880 pr_err("unmap queue failed\n");
883 } else if (prev_active &&
884 (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
885 q->properties.type == KFD_QUEUE_TYPE_SDMA ||
886 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) {
888 if (!dqm->sched_running) {
889 WARN_ONCE(1, "Update non-HWS queue while stopped\n");
893 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd,
894 (dqm->dev->kfd->cwsr_enabled ?
895 KFD_PREEMPT_TYPE_WAVEFRONT_SAVE :
896 KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN),
897 KFD_UNMAP_LATENCY_MS, q->pipe, q->queue);
899 pr_err("destroy mqd failed\n");
904 mqd_mgr->update_mqd(mqd_mgr, q->mqd, &q->properties, minfo);
907 * check active state vs. the previous state and modify
908 * counter accordingly. map_queues_cpsch uses the
909 * dqm->active_queue_count to determine whether a new runlist must be
912 if (q->properties.is_active && !prev_active) {
913 increment_queue_count(dqm, &pdd->qpd, q);
914 } else if (!q->properties.is_active && prev_active) {
915 decrement_queue_count(dqm, &pdd->qpd, q);
916 } else if (q->gws && !q->properties.is_gws) {
917 if (q->properties.is_active) {
918 dqm->gws_queue_count++;
919 pdd->qpd.mapped_gws_queue = true;
921 q->properties.is_gws = true;
922 } else if (!q->gws && q->properties.is_gws) {
923 if (q->properties.is_active) {
924 dqm->gws_queue_count--;
925 pdd->qpd.mapped_gws_queue = false;
927 q->properties.is_gws = false;
930 if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) {
931 if (!dqm->dev->kfd->shared_resources.enable_mes)
932 retval = map_queues_cpsch(dqm);
933 else if (q->properties.is_active)
934 retval = add_queue_mes(dqm, q, &pdd->qpd);
935 } else if (q->properties.is_active &&
936 (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
937 q->properties.type == KFD_QUEUE_TYPE_SDMA ||
938 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) {
939 if (WARN(q->process->mm != current->mm,
940 "should only run in user thread"))
943 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd,
945 &q->properties, current->mm);
953 /* suspend_single_queue does not lock the dqm like the
954 * evict_process_queues_cpsch or evict_process_queues_nocpsch. You should
955 * lock the dqm before calling, and unlock after calling.
957 * The reason we don't lock the dqm is because this function may be
958 * called on multiple queues in a loop, so rather than locking/unlocking
959 * multiple times, we will just keep the dqm locked for all of the calls.
961 static int suspend_single_queue(struct device_queue_manager *dqm,
962 struct kfd_process_device *pdd,
967 if (q->properties.is_suspended)
970 pr_debug("Suspending PASID %u queue [%i]\n",
972 q->properties.queue_id);
974 is_new = q->properties.exception_status & KFD_EC_MASK(EC_QUEUE_NEW);
976 if (is_new || q->properties.is_being_destroyed) {
977 pr_debug("Suspend: skip %s queue id %i\n",
978 is_new ? "new" : "destroyed",
979 q->properties.queue_id);
983 q->properties.is_suspended = true;
984 if (q->properties.is_active) {
985 if (dqm->dev->kfd->shared_resources.enable_mes) {
986 int r = remove_queue_mes(dqm, q, &pdd->qpd);
992 decrement_queue_count(dqm, &pdd->qpd, q);
993 q->properties.is_active = false;
999 /* resume_single_queue does not lock the dqm like the functions
1000 * restore_process_queues_cpsch or restore_process_queues_nocpsch. You should
1001 * lock the dqm before calling, and unlock after calling.
1003 * The reason we don't lock the dqm is because this function may be
1004 * called on multiple queues in a loop, so rather than locking/unlocking
1005 * multiple times, we will just keep the dqm locked for all of the calls.
1007 static int resume_single_queue(struct device_queue_manager *dqm,
1008 struct qcm_process_device *qpd,
1011 struct kfd_process_device *pdd;
1013 if (!q->properties.is_suspended)
1016 pdd = qpd_to_pdd(qpd);
1018 pr_debug("Restoring from suspend PASID %u queue [%i]\n",
1019 pdd->process->pasid,
1020 q->properties.queue_id);
1022 q->properties.is_suspended = false;
1024 if (QUEUE_IS_ACTIVE(q->properties)) {
1025 if (dqm->dev->kfd->shared_resources.enable_mes) {
1026 int r = add_queue_mes(dqm, q, &pdd->qpd);
1032 q->properties.is_active = true;
1033 increment_queue_count(dqm, qpd, q);
1039 static int evict_process_queues_nocpsch(struct device_queue_manager *dqm,
1040 struct qcm_process_device *qpd)
1043 struct mqd_manager *mqd_mgr;
1044 struct kfd_process_device *pdd;
1045 int retval, ret = 0;
1048 if (qpd->evicted++ > 0) /* already evicted, do nothing */
1051 pdd = qpd_to_pdd(qpd);
1052 pr_debug_ratelimited("Evicting PASID 0x%x queues\n",
1053 pdd->process->pasid);
1055 pdd->last_evict_timestamp = get_jiffies_64();
1056 /* Mark all queues as evicted. Deactivate all active queues on
1059 list_for_each_entry(q, &qpd->queues_list, list) {
1060 q->properties.is_evicted = true;
1061 if (!q->properties.is_active)
1064 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
1065 q->properties.type)];
1066 q->properties.is_active = false;
1067 decrement_queue_count(dqm, qpd, q);
1069 if (WARN_ONCE(!dqm->sched_running, "Evict when stopped\n"))
1072 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd,
1073 (dqm->dev->kfd->cwsr_enabled ?
1074 KFD_PREEMPT_TYPE_WAVEFRONT_SAVE :
1075 KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN),
1076 KFD_UNMAP_LATENCY_MS, q->pipe, q->queue);
1078 /* Return the first error, but keep going to
1079 * maintain a consistent eviction state
1089 static int evict_process_queues_cpsch(struct device_queue_manager *dqm,
1090 struct qcm_process_device *qpd)
1093 struct kfd_process_device *pdd;
1097 if (qpd->evicted++ > 0) /* already evicted, do nothing */
1100 pdd = qpd_to_pdd(qpd);
1102 /* The debugger creates processes that temporarily have not acquired
1103 * all VMs for all devices and has no VMs itself.
1104 * Skip queue eviction on process eviction.
1109 pr_debug_ratelimited("Evicting PASID 0x%x queues\n",
1110 pdd->process->pasid);
1112 /* Mark all queues as evicted. Deactivate all active queues on
1115 list_for_each_entry(q, &qpd->queues_list, list) {
1116 q->properties.is_evicted = true;
1117 if (!q->properties.is_active)
1120 q->properties.is_active = false;
1121 decrement_queue_count(dqm, qpd, q);
1123 if (dqm->dev->kfd->shared_resources.enable_mes) {
1124 retval = remove_queue_mes(dqm, q, qpd);
1126 pr_err("Failed to evict queue %d\n",
1127 q->properties.queue_id);
1132 pdd->last_evict_timestamp = get_jiffies_64();
1133 if (!dqm->dev->kfd->shared_resources.enable_mes)
1134 retval = execute_queues_cpsch(dqm,
1136 KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES :
1137 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0,
1138 USE_DEFAULT_GRACE_PERIOD);
1145 static int restore_process_queues_nocpsch(struct device_queue_manager *dqm,
1146 struct qcm_process_device *qpd)
1148 struct mm_struct *mm = NULL;
1150 struct mqd_manager *mqd_mgr;
1151 struct kfd_process_device *pdd;
1153 uint64_t eviction_duration;
1154 int retval, ret = 0;
1156 pdd = qpd_to_pdd(qpd);
1157 /* Retrieve PD base */
1158 pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv);
1161 if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */
1163 if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */
1168 pr_debug_ratelimited("Restoring PASID 0x%x queues\n",
1169 pdd->process->pasid);
1171 /* Update PD Base in QPD */
1172 qpd->page_table_base = pd_base;
1173 pr_debug("Updated PD address to 0x%llx\n", pd_base);
1175 if (!list_empty(&qpd->queues_list)) {
1176 dqm->dev->kfd2kgd->set_vm_context_page_table_base(
1179 qpd->page_table_base);
1180 kfd_flush_tlb(pdd, TLB_FLUSH_LEGACY);
1183 /* Take a safe reference to the mm_struct, which may otherwise
1184 * disappear even while the kfd_process is still referenced.
1186 mm = get_task_mm(pdd->process->lead_thread);
1192 /* Remove the eviction flags. Activate queues that are not
1193 * inactive for other reasons.
1195 list_for_each_entry(q, &qpd->queues_list, list) {
1196 q->properties.is_evicted = false;
1197 if (!QUEUE_IS_ACTIVE(q->properties))
1200 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
1201 q->properties.type)];
1202 q->properties.is_active = true;
1203 increment_queue_count(dqm, qpd, q);
1205 if (WARN_ONCE(!dqm->sched_running, "Restore when stopped\n"))
1208 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe,
1209 q->queue, &q->properties, mm);
1211 /* Return the first error, but keep going to
1212 * maintain a consistent eviction state
1217 eviction_duration = get_jiffies_64() - pdd->last_evict_timestamp;
1218 atomic64_add(eviction_duration, &pdd->evict_duration_counter);
1226 static int restore_process_queues_cpsch(struct device_queue_manager *dqm,
1227 struct qcm_process_device *qpd)
1230 struct kfd_process_device *pdd;
1231 uint64_t eviction_duration;
1234 pdd = qpd_to_pdd(qpd);
1237 if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */
1239 if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */
1244 /* The debugger creates processes that temporarily have not acquired
1245 * all VMs for all devices and has no VMs itself.
1246 * Skip queue restore on process restore.
1249 goto vm_not_acquired;
1251 pr_debug_ratelimited("Restoring PASID 0x%x queues\n",
1252 pdd->process->pasid);
1254 /* Update PD Base in QPD */
1255 qpd->page_table_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv);
1256 pr_debug("Updated PD address to 0x%llx\n", qpd->page_table_base);
1258 /* activate all active queues on the qpd */
1259 list_for_each_entry(q, &qpd->queues_list, list) {
1260 q->properties.is_evicted = false;
1261 if (!QUEUE_IS_ACTIVE(q->properties))
1264 q->properties.is_active = true;
1265 increment_queue_count(dqm, &pdd->qpd, q);
1267 if (dqm->dev->kfd->shared_resources.enable_mes) {
1268 retval = add_queue_mes(dqm, q, qpd);
1270 pr_err("Failed to restore queue %d\n",
1271 q->properties.queue_id);
1276 if (!dqm->dev->kfd->shared_resources.enable_mes)
1277 retval = execute_queues_cpsch(dqm,
1278 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD);
1279 eviction_duration = get_jiffies_64() - pdd->last_evict_timestamp;
1280 atomic64_add(eviction_duration, &pdd->evict_duration_counter);
1288 static int register_process(struct device_queue_manager *dqm,
1289 struct qcm_process_device *qpd)
1291 struct device_process_node *n;
1292 struct kfd_process_device *pdd;
1296 n = kzalloc(sizeof(*n), GFP_KERNEL);
1302 pdd = qpd_to_pdd(qpd);
1303 /* Retrieve PD base */
1304 pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv);
1307 list_add(&n->list, &dqm->queues);
1309 /* Update PD Base in QPD */
1310 qpd->page_table_base = pd_base;
1311 pr_debug("Updated PD address to 0x%llx\n", pd_base);
1313 retval = dqm->asic_ops.update_qpd(dqm, qpd);
1315 dqm->processes_count++;
1319 /* Outside the DQM lock because under the DQM lock we can't do
1320 * reclaim or take other locks that others hold while reclaiming.
1322 kfd_inc_compute_active(dqm->dev);
1327 static int unregister_process(struct device_queue_manager *dqm,
1328 struct qcm_process_device *qpd)
1331 struct device_process_node *cur, *next;
1333 pr_debug("qpd->queues_list is %s\n",
1334 list_empty(&qpd->queues_list) ? "empty" : "not empty");
1339 list_for_each_entry_safe(cur, next, &dqm->queues, list) {
1340 if (qpd == cur->qpd) {
1341 list_del(&cur->list);
1343 dqm->processes_count--;
1347 /* qpd not found in dqm list */
1352 /* Outside the DQM lock because under the DQM lock we can't do
1353 * reclaim or take other locks that others hold while reclaiming.
1356 kfd_dec_compute_active(dqm->dev);
1362 set_pasid_vmid_mapping(struct device_queue_manager *dqm, u32 pasid,
1365 uint32_t xcc_mask = dqm->dev->xcc_mask;
1368 for_each_inst(xcc_id, xcc_mask) {
1369 ret = dqm->dev->kfd2kgd->set_pasid_vmid_mapping(
1370 dqm->dev->adev, pasid, vmid, xcc_id);
1378 static void init_interrupts(struct device_queue_manager *dqm)
1380 uint32_t xcc_mask = dqm->dev->xcc_mask;
1381 unsigned int i, xcc_id;
1383 for_each_inst(xcc_id, xcc_mask) {
1384 for (i = 0 ; i < get_pipes_per_mec(dqm) ; i++) {
1385 if (is_pipe_enabled(dqm, 0, i)) {
1386 dqm->dev->kfd2kgd->init_interrupts(
1387 dqm->dev->adev, i, xcc_id);
1393 static int initialize_nocpsch(struct device_queue_manager *dqm)
1397 pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm));
1399 dqm->allocated_queues = kcalloc(get_pipes_per_mec(dqm),
1400 sizeof(unsigned int), GFP_KERNEL);
1401 if (!dqm->allocated_queues)
1404 mutex_init(&dqm->lock_hidden);
1405 INIT_LIST_HEAD(&dqm->queues);
1406 dqm->active_queue_count = dqm->next_pipe_to_allocate = 0;
1407 dqm->active_cp_queue_count = 0;
1408 dqm->gws_queue_count = 0;
1410 for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) {
1411 int pipe_offset = pipe * get_queues_per_pipe(dqm);
1413 for (queue = 0; queue < get_queues_per_pipe(dqm); queue++)
1414 if (test_bit(pipe_offset + queue,
1415 dqm->dev->kfd->shared_resources.cp_queue_bitmap))
1416 dqm->allocated_queues[pipe] |= 1 << queue;
1419 memset(dqm->vmid_pasid, 0, sizeof(dqm->vmid_pasid));
1421 init_sdma_bitmaps(dqm);
1426 static void uninitialize(struct device_queue_manager *dqm)
1430 WARN_ON(dqm->active_queue_count > 0 || dqm->processes_count > 0);
1432 kfree(dqm->allocated_queues);
1433 for (i = 0 ; i < KFD_MQD_TYPE_MAX ; i++)
1434 kfree(dqm->mqd_mgrs[i]);
1435 mutex_destroy(&dqm->lock_hidden);
1438 static int start_nocpsch(struct device_queue_manager *dqm)
1442 pr_info("SW scheduler is used");
1443 init_interrupts(dqm);
1445 if (dqm->dev->adev->asic_type == CHIP_HAWAII)
1446 r = pm_init(&dqm->packet_mgr, dqm);
1448 dqm->sched_running = true;
1453 static int stop_nocpsch(struct device_queue_manager *dqm)
1456 if (!dqm->sched_running) {
1461 if (dqm->dev->adev->asic_type == CHIP_HAWAII)
1462 pm_uninit(&dqm->packet_mgr, false);
1463 dqm->sched_running = false;
1469 static void pre_reset(struct device_queue_manager *dqm)
1472 dqm->is_resetting = true;
1476 static int allocate_sdma_queue(struct device_queue_manager *dqm,
1477 struct queue *q, const uint32_t *restore_sdma_id)
1481 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
1482 if (bitmap_empty(dqm->sdma_bitmap, KFD_MAX_SDMA_QUEUES)) {
1483 pr_err("No more SDMA queue to allocate\n");
1487 if (restore_sdma_id) {
1488 /* Re-use existing sdma_id */
1489 if (!test_bit(*restore_sdma_id, dqm->sdma_bitmap)) {
1490 pr_err("SDMA queue already in use\n");
1493 clear_bit(*restore_sdma_id, dqm->sdma_bitmap);
1494 q->sdma_id = *restore_sdma_id;
1496 /* Find first available sdma_id */
1497 bit = find_first_bit(dqm->sdma_bitmap,
1498 get_num_sdma_queues(dqm));
1499 clear_bit(bit, dqm->sdma_bitmap);
1503 q->properties.sdma_engine_id =
1504 q->sdma_id % kfd_get_num_sdma_engines(dqm->dev);
1505 q->properties.sdma_queue_id = q->sdma_id /
1506 kfd_get_num_sdma_engines(dqm->dev);
1507 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
1508 if (bitmap_empty(dqm->xgmi_sdma_bitmap, KFD_MAX_SDMA_QUEUES)) {
1509 pr_err("No more XGMI SDMA queue to allocate\n");
1512 if (restore_sdma_id) {
1513 /* Re-use existing sdma_id */
1514 if (!test_bit(*restore_sdma_id, dqm->xgmi_sdma_bitmap)) {
1515 pr_err("SDMA queue already in use\n");
1518 clear_bit(*restore_sdma_id, dqm->xgmi_sdma_bitmap);
1519 q->sdma_id = *restore_sdma_id;
1521 bit = find_first_bit(dqm->xgmi_sdma_bitmap,
1522 get_num_xgmi_sdma_queues(dqm));
1523 clear_bit(bit, dqm->xgmi_sdma_bitmap);
1526 /* sdma_engine_id is sdma id including
1527 * both PCIe-optimized SDMAs and XGMI-
1528 * optimized SDMAs. The calculation below
1529 * assumes the first N engines are always
1530 * PCIe-optimized ones
1532 q->properties.sdma_engine_id =
1533 kfd_get_num_sdma_engines(dqm->dev) +
1534 q->sdma_id % kfd_get_num_xgmi_sdma_engines(dqm->dev);
1535 q->properties.sdma_queue_id = q->sdma_id /
1536 kfd_get_num_xgmi_sdma_engines(dqm->dev);
1539 pr_debug("SDMA engine id: %d\n", q->properties.sdma_engine_id);
1540 pr_debug("SDMA queue id: %d\n", q->properties.sdma_queue_id);
1545 static void deallocate_sdma_queue(struct device_queue_manager *dqm,
1548 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
1549 if (q->sdma_id >= get_num_sdma_queues(dqm))
1551 set_bit(q->sdma_id, dqm->sdma_bitmap);
1552 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
1553 if (q->sdma_id >= get_num_xgmi_sdma_queues(dqm))
1555 set_bit(q->sdma_id, dqm->xgmi_sdma_bitmap);
1560 * Device Queue Manager implementation for cp scheduler
1563 static int set_sched_resources(struct device_queue_manager *dqm)
1566 struct scheduling_resources res;
1568 res.vmid_mask = dqm->dev->compute_vmid_bitmap;
1571 for (i = 0; i < KGD_MAX_QUEUES; ++i) {
1572 mec = (i / dqm->dev->kfd->shared_resources.num_queue_per_pipe)
1573 / dqm->dev->kfd->shared_resources.num_pipe_per_mec;
1575 if (!test_bit(i, dqm->dev->kfd->shared_resources.cp_queue_bitmap))
1578 /* only acquire queues from the first MEC */
1582 /* This situation may be hit in the future if a new HW
1583 * generation exposes more than 64 queues. If so, the
1584 * definition of res.queue_mask needs updating
1586 if (WARN_ON(i >= (sizeof(res.queue_mask)*8))) {
1587 pr_err("Invalid queue enabled by amdgpu: %d\n", i);
1591 res.queue_mask |= 1ull
1592 << amdgpu_queue_mask_bit_to_set_resource_bit(
1595 res.gws_mask = ~0ull;
1596 res.oac_mask = res.gds_heap_base = res.gds_heap_size = 0;
1598 pr_debug("Scheduling resources:\n"
1599 "vmid mask: 0x%8X\n"
1600 "queue mask: 0x%8llX\n",
1601 res.vmid_mask, res.queue_mask);
1603 return pm_send_set_resources(&dqm->packet_mgr, &res);
1606 static int initialize_cpsch(struct device_queue_manager *dqm)
1608 pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm));
1610 mutex_init(&dqm->lock_hidden);
1611 INIT_LIST_HEAD(&dqm->queues);
1612 dqm->active_queue_count = dqm->processes_count = 0;
1613 dqm->active_cp_queue_count = 0;
1614 dqm->gws_queue_count = 0;
1615 dqm->active_runlist = false;
1616 INIT_WORK(&dqm->hw_exception_work, kfd_process_hw_exception);
1617 dqm->trap_debug_vmid = 0;
1619 init_sdma_bitmaps(dqm);
1621 if (dqm->dev->kfd2kgd->get_iq_wait_times)
1622 dqm->dev->kfd2kgd->get_iq_wait_times(dqm->dev->adev,
1627 static int start_cpsch(struct device_queue_manager *dqm)
1635 if (!dqm->dev->kfd->shared_resources.enable_mes) {
1636 retval = pm_init(&dqm->packet_mgr, dqm);
1638 goto fail_packet_manager_init;
1640 retval = set_sched_resources(dqm);
1642 goto fail_set_sched_resources;
1644 pr_debug("Allocating fence memory\n");
1646 /* allocate fence memory on the gart */
1647 retval = kfd_gtt_sa_allocate(dqm->dev, sizeof(*dqm->fence_addr),
1651 goto fail_allocate_vidmem;
1653 dqm->fence_addr = (uint64_t *)dqm->fence_mem->cpu_ptr;
1654 dqm->fence_gpu_addr = dqm->fence_mem->gpu_addr;
1656 init_interrupts(dqm);
1658 /* clear hang status when driver try to start the hw scheduler */
1659 dqm->is_hws_hang = false;
1660 dqm->is_resetting = false;
1661 dqm->sched_running = true;
1663 if (!dqm->dev->kfd->shared_resources.enable_mes)
1664 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD);
1668 fail_allocate_vidmem:
1669 fail_set_sched_resources:
1670 if (!dqm->dev->kfd->shared_resources.enable_mes)
1671 pm_uninit(&dqm->packet_mgr, false);
1672 fail_packet_manager_init:
1677 static int stop_cpsch(struct device_queue_manager *dqm)
1682 if (!dqm->sched_running) {
1687 if (!dqm->is_hws_hang) {
1688 if (!dqm->dev->kfd->shared_resources.enable_mes)
1689 unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD, false);
1691 remove_all_queues_mes(dqm);
1694 hanging = dqm->is_hws_hang || dqm->is_resetting;
1695 dqm->sched_running = false;
1697 if (!dqm->dev->kfd->shared_resources.enable_mes)
1698 pm_release_ib(&dqm->packet_mgr);
1700 kfd_gtt_sa_free(dqm->dev, dqm->fence_mem);
1701 if (!dqm->dev->kfd->shared_resources.enable_mes)
1702 pm_uninit(&dqm->packet_mgr, hanging);
1708 static int create_kernel_queue_cpsch(struct device_queue_manager *dqm,
1709 struct kernel_queue *kq,
1710 struct qcm_process_device *qpd)
1713 if (dqm->total_queue_count >= max_num_of_queues_per_device) {
1714 pr_warn("Can't create new kernel queue because %d queues were already created\n",
1715 dqm->total_queue_count);
1721 * Unconditionally increment this counter, regardless of the queue's
1722 * type or whether the queue is active.
1724 dqm->total_queue_count++;
1725 pr_debug("Total of %d queues are accountable so far\n",
1726 dqm->total_queue_count);
1728 list_add(&kq->list, &qpd->priv_queue_list);
1729 increment_queue_count(dqm, qpd, kq->queue);
1730 qpd->is_debug = true;
1731 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0,
1732 USE_DEFAULT_GRACE_PERIOD);
1738 static void destroy_kernel_queue_cpsch(struct device_queue_manager *dqm,
1739 struct kernel_queue *kq,
1740 struct qcm_process_device *qpd)
1743 list_del(&kq->list);
1744 decrement_queue_count(dqm, qpd, kq->queue);
1745 qpd->is_debug = false;
1746 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0,
1747 USE_DEFAULT_GRACE_PERIOD);
1749 * Unconditionally decrement this counter, regardless of the queue's
1752 dqm->total_queue_count--;
1753 pr_debug("Total of %d queues are accountable so far\n",
1754 dqm->total_queue_count);
1758 static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q,
1759 struct qcm_process_device *qpd,
1760 const struct kfd_criu_queue_priv_data *qd,
1761 const void *restore_mqd, const void *restore_ctl_stack)
1764 struct mqd_manager *mqd_mgr;
1766 if (dqm->total_queue_count >= max_num_of_queues_per_device) {
1767 pr_warn("Can't create new usermode queue because %d queues were already created\n",
1768 dqm->total_queue_count);
1773 if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
1774 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
1776 retval = allocate_sdma_queue(dqm, q, qd ? &qd->sdma_id : NULL);
1782 retval = allocate_doorbell(qpd, q, qd ? &qd->doorbell_id : NULL);
1784 goto out_deallocate_sdma_queue;
1786 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
1787 q->properties.type)];
1789 if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
1790 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
1791 dqm->asic_ops.init_sdma_vm(dqm, q, qpd);
1792 q->properties.tba_addr = qpd->tba_addr;
1793 q->properties.tma_addr = qpd->tma_addr;
1794 q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties);
1795 if (!q->mqd_mem_obj) {
1797 goto out_deallocate_doorbell;
1802 * Eviction state logic: mark all queues as evicted, even ones
1803 * not currently active. Restoring inactive queues later only
1804 * updates the is_evicted flag but is a no-op otherwise.
1806 q->properties.is_evicted = !!qpd->evicted;
1807 q->properties.is_dbg_wa = qpd->pqm->process->debug_trap_enabled &&
1808 kfd_dbg_has_cwsr_workaround(q->device);
1811 mqd_mgr->restore_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, &q->gart_mqd_addr,
1812 &q->properties, restore_mqd, restore_ctl_stack,
1813 qd->ctl_stack_size);
1815 mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj,
1816 &q->gart_mqd_addr, &q->properties);
1818 list_add(&q->list, &qpd->queues_list);
1821 if (q->properties.is_active) {
1822 increment_queue_count(dqm, qpd, q);
1824 if (!dqm->dev->kfd->shared_resources.enable_mes)
1825 retval = execute_queues_cpsch(dqm,
1826 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD);
1828 retval = add_queue_mes(dqm, q, qpd);
1834 * Unconditionally increment this counter, regardless of the queue's
1835 * type or whether the queue is active.
1837 dqm->total_queue_count++;
1839 pr_debug("Total of %d queues are accountable so far\n",
1840 dqm->total_queue_count);
1848 if (q->properties.is_active)
1849 decrement_queue_count(dqm, qpd, q);
1850 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
1852 out_deallocate_doorbell:
1853 deallocate_doorbell(qpd, q);
1854 out_deallocate_sdma_queue:
1855 if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
1856 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
1858 deallocate_sdma_queue(dqm, q);
1865 int amdkfd_fence_wait_timeout(uint64_t *fence_addr,
1866 uint64_t fence_value,
1867 unsigned int timeout_ms)
1869 unsigned long end_jiffies = msecs_to_jiffies(timeout_ms) + jiffies;
1871 while (*fence_addr != fence_value) {
1872 if (time_after(jiffies, end_jiffies)) {
1873 pr_err("qcm fence wait loop timeout expired\n");
1874 /* In HWS case, this is used to halt the driver thread
1875 * in order not to mess up CP states before doing
1876 * scandumps for FW debugging.
1878 while (halt_if_hws_hang)
1889 /* dqm->lock mutex has to be locked before calling this function */
1890 static int map_queues_cpsch(struct device_queue_manager *dqm)
1894 if (!dqm->sched_running)
1896 if (dqm->active_queue_count <= 0 || dqm->processes_count <= 0)
1898 if (dqm->active_runlist)
1901 retval = pm_send_runlist(&dqm->packet_mgr, &dqm->queues);
1902 pr_debug("%s sent runlist\n", __func__);
1904 pr_err("failed to execute runlist\n");
1907 dqm->active_runlist = true;
1912 /* dqm->lock mutex has to be locked before calling this function */
1913 static int unmap_queues_cpsch(struct device_queue_manager *dqm,
1914 enum kfd_unmap_queues_filter filter,
1915 uint32_t filter_param,
1916 uint32_t grace_period,
1920 struct mqd_manager *mqd_mgr;
1922 if (!dqm->sched_running)
1924 if (dqm->is_hws_hang || dqm->is_resetting)
1926 if (!dqm->active_runlist)
1929 if (grace_period != USE_DEFAULT_GRACE_PERIOD) {
1930 retval = pm_update_grace_period(&dqm->packet_mgr, grace_period);
1935 retval = pm_send_unmap_queue(&dqm->packet_mgr, filter, filter_param, reset);
1939 *dqm->fence_addr = KFD_FENCE_INIT;
1940 pm_send_query_status(&dqm->packet_mgr, dqm->fence_gpu_addr,
1941 KFD_FENCE_COMPLETED);
1942 /* should be timed out */
1943 retval = amdkfd_fence_wait_timeout(dqm->fence_addr, KFD_FENCE_COMPLETED,
1944 queue_preemption_timeout_ms);
1946 pr_err("The cp might be in an unrecoverable state due to an unsuccessful queues preemption\n");
1951 /* In the current MEC firmware implementation, if compute queue
1952 * doesn't response to the preemption request in time, HIQ will
1953 * abandon the unmap request without returning any timeout error
1954 * to driver. Instead, MEC firmware will log the doorbell of the
1955 * unresponding compute queue to HIQ.MQD.queue_doorbell_id fields.
1956 * To make sure the queue unmap was successful, driver need to
1957 * check those fields
1959 mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ];
1960 if (mqd_mgr->read_doorbell_id(dqm->packet_mgr.priv_queue->queue->mqd)) {
1961 pr_err("HIQ MQD's queue_doorbell_id0 is not 0, Queue preemption time out\n");
1962 while (halt_if_hws_hang)
1967 /* We need to reset the grace period value for this device */
1968 if (grace_period != USE_DEFAULT_GRACE_PERIOD) {
1969 if (pm_update_grace_period(&dqm->packet_mgr,
1970 USE_DEFAULT_GRACE_PERIOD))
1971 pr_err("Failed to reset grace period\n");
1974 pm_release_ib(&dqm->packet_mgr);
1975 dqm->active_runlist = false;
1980 /* only for compute queue */
1981 static int reset_queues_cpsch(struct device_queue_manager *dqm,
1988 retval = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_BY_PASID,
1989 pasid, USE_DEFAULT_GRACE_PERIOD, true);
1995 /* dqm->lock mutex has to be locked before calling this function */
1996 static int execute_queues_cpsch(struct device_queue_manager *dqm,
1997 enum kfd_unmap_queues_filter filter,
1998 uint32_t filter_param,
1999 uint32_t grace_period)
2003 if (dqm->is_hws_hang)
2005 retval = unmap_queues_cpsch(dqm, filter, filter_param, grace_period, false);
2009 return map_queues_cpsch(dqm);
2012 static int wait_on_destroy_queue(struct device_queue_manager *dqm,
2015 struct kfd_process_device *pdd = kfd_get_process_device_data(q->device,
2019 if (pdd->qpd.is_debug)
2022 q->properties.is_being_destroyed = true;
2024 if (pdd->process->debug_trap_enabled && q->properties.is_suspended) {
2026 mutex_unlock(&q->process->mutex);
2027 ret = wait_event_interruptible(dqm->destroy_wait,
2028 !q->properties.is_suspended);
2030 mutex_lock(&q->process->mutex);
2037 static int destroy_queue_cpsch(struct device_queue_manager *dqm,
2038 struct qcm_process_device *qpd,
2042 struct mqd_manager *mqd_mgr;
2043 uint64_t sdma_val = 0;
2044 struct kfd_process_device *pdd = qpd_to_pdd(qpd);
2046 /* Get the SDMA queue stats */
2047 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) ||
2048 (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) {
2049 retval = read_sdma_queue_counter((uint64_t __user *)q->properties.read_ptr,
2052 pr_err("Failed to read SDMA queue counter for queue: %d\n",
2053 q->properties.queue_id);
2056 /* remove queue from list to prevent rescheduling after preemption */
2059 retval = wait_on_destroy_queue(dqm, q);
2066 if (qpd->is_debug) {
2068 * error, currently we do not allow to destroy a queue
2069 * of a currently debugged process
2072 goto failed_try_destroy_debugged_queue;
2076 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
2077 q->properties.type)];
2079 deallocate_doorbell(qpd, q);
2081 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) ||
2082 (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) {
2083 deallocate_sdma_queue(dqm, q);
2084 pdd->sdma_past_activity_counter += sdma_val;
2089 if (q->properties.is_active) {
2090 decrement_queue_count(dqm, qpd, q);
2091 if (!dqm->dev->kfd->shared_resources.enable_mes) {
2092 retval = execute_queues_cpsch(dqm,
2093 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0,
2094 USE_DEFAULT_GRACE_PERIOD);
2095 if (retval == -ETIME)
2096 qpd->reset_wavefronts = true;
2098 retval = remove_queue_mes(dqm, q, qpd);
2103 * Unconditionally decrement this counter, regardless of the queue's
2106 dqm->total_queue_count--;
2107 pr_debug("Total of %d queues are accountable so far\n",
2108 dqm->total_queue_count);
2113 * Do free_mqd and raise delete event after dqm_unlock(dqm) to avoid
2116 kfd_dbg_ev_raise(KFD_EC_MASK(EC_DEVICE_QUEUE_DELETE),
2117 qpd->pqm->process, q->device,
2118 -1, false, NULL, 0);
2120 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
2124 failed_try_destroy_debugged_queue:
2131 * Low bits must be 0000/FFFF as required by HW, high bits must be 0 to
2132 * stay in user mode.
2134 #define APE1_FIXED_BITS_MASK 0xFFFF80000000FFFFULL
2135 /* APE1 limit is inclusive and 64K aligned. */
2136 #define APE1_LIMIT_ALIGNMENT 0xFFFF
2138 static bool set_cache_memory_policy(struct device_queue_manager *dqm,
2139 struct qcm_process_device *qpd,
2140 enum cache_policy default_policy,
2141 enum cache_policy alternate_policy,
2142 void __user *alternate_aperture_base,
2143 uint64_t alternate_aperture_size)
2147 if (!dqm->asic_ops.set_cache_memory_policy)
2152 if (alternate_aperture_size == 0) {
2153 /* base > limit disables APE1 */
2154 qpd->sh_mem_ape1_base = 1;
2155 qpd->sh_mem_ape1_limit = 0;
2158 * In FSA64, APE1_Base[63:0] = { 16{SH_MEM_APE1_BASE[31]},
2159 * SH_MEM_APE1_BASE[31:0], 0x0000 }
2160 * APE1_Limit[63:0] = { 16{SH_MEM_APE1_LIMIT[31]},
2161 * SH_MEM_APE1_LIMIT[31:0], 0xFFFF }
2162 * Verify that the base and size parameters can be
2163 * represented in this format and convert them.
2164 * Additionally restrict APE1 to user-mode addresses.
2167 uint64_t base = (uintptr_t)alternate_aperture_base;
2168 uint64_t limit = base + alternate_aperture_size - 1;
2170 if (limit <= base || (base & APE1_FIXED_BITS_MASK) != 0 ||
2171 (limit & APE1_FIXED_BITS_MASK) != APE1_LIMIT_ALIGNMENT) {
2176 qpd->sh_mem_ape1_base = base >> 16;
2177 qpd->sh_mem_ape1_limit = limit >> 16;
2180 retval = dqm->asic_ops.set_cache_memory_policy(
2185 alternate_aperture_base,
2186 alternate_aperture_size);
2188 if ((dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) && (qpd->vmid != 0))
2189 program_sh_mem_settings(dqm, qpd);
2191 pr_debug("sh_mem_config: 0x%x, ape1_base: 0x%x, ape1_limit: 0x%x\n",
2192 qpd->sh_mem_config, qpd->sh_mem_ape1_base,
2193 qpd->sh_mem_ape1_limit);
2200 static int process_termination_nocpsch(struct device_queue_manager *dqm,
2201 struct qcm_process_device *qpd)
2204 struct device_process_node *cur, *next_dpn;
2210 /* Clear all user mode queues */
2211 while (!list_empty(&qpd->queues_list)) {
2212 struct mqd_manager *mqd_mgr;
2215 q = list_first_entry(&qpd->queues_list, struct queue, list);
2216 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
2217 q->properties.type)];
2218 ret = destroy_queue_nocpsch_locked(dqm, qpd, q);
2222 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
2226 /* Unregister process */
2227 list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) {
2228 if (qpd == cur->qpd) {
2229 list_del(&cur->list);
2231 dqm->processes_count--;
2239 /* Outside the DQM lock because under the DQM lock we can't do
2240 * reclaim or take other locks that others hold while reclaiming.
2243 kfd_dec_compute_active(dqm->dev);
2248 static int get_wave_state(struct device_queue_manager *dqm,
2250 void __user *ctl_stack,
2251 u32 *ctl_stack_used_size,
2252 u32 *save_area_used_size)
2254 struct mqd_manager *mqd_mgr;
2258 mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_CP];
2260 if (q->properties.type != KFD_QUEUE_TYPE_COMPUTE ||
2261 q->properties.is_active || !q->device->kfd->cwsr_enabled ||
2262 !mqd_mgr->get_wave_state) {
2270 * get_wave_state is outside the dqm lock to prevent circular locking
2271 * and the queue should be protected against destruction by the process
2274 return mqd_mgr->get_wave_state(mqd_mgr, q->mqd, &q->properties,
2275 ctl_stack, ctl_stack_used_size, save_area_used_size);
2278 static void get_queue_checkpoint_info(struct device_queue_manager *dqm,
2279 const struct queue *q,
2281 u32 *ctl_stack_size)
2283 struct mqd_manager *mqd_mgr;
2284 enum KFD_MQD_TYPE mqd_type =
2285 get_mqd_type_from_queue_type(q->properties.type);
2288 mqd_mgr = dqm->mqd_mgrs[mqd_type];
2289 *mqd_size = mqd_mgr->mqd_size;
2290 *ctl_stack_size = 0;
2292 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE && mqd_mgr->get_checkpoint_info)
2293 mqd_mgr->get_checkpoint_info(mqd_mgr, q->mqd, ctl_stack_size);
2298 static int checkpoint_mqd(struct device_queue_manager *dqm,
2299 const struct queue *q,
2303 struct mqd_manager *mqd_mgr;
2305 enum KFD_MQD_TYPE mqd_type =
2306 get_mqd_type_from_queue_type(q->properties.type);
2310 if (q->properties.is_active || !q->device->kfd->cwsr_enabled) {
2315 mqd_mgr = dqm->mqd_mgrs[mqd_type];
2316 if (!mqd_mgr->checkpoint_mqd) {
2321 mqd_mgr->checkpoint_mqd(mqd_mgr, q->mqd, mqd, ctl_stack);
2328 static int process_termination_cpsch(struct device_queue_manager *dqm,
2329 struct qcm_process_device *qpd)
2333 struct kernel_queue *kq, *kq_next;
2334 struct mqd_manager *mqd_mgr;
2335 struct device_process_node *cur, *next_dpn;
2336 enum kfd_unmap_queues_filter filter =
2337 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES;
2344 /* Clean all kernel queues */
2345 list_for_each_entry_safe(kq, kq_next, &qpd->priv_queue_list, list) {
2346 list_del(&kq->list);
2347 decrement_queue_count(dqm, qpd, kq->queue);
2348 qpd->is_debug = false;
2349 dqm->total_queue_count--;
2350 filter = KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES;
2353 /* Clear all user mode queues */
2354 list_for_each_entry(q, &qpd->queues_list, list) {
2355 if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
2356 deallocate_sdma_queue(dqm, q);
2357 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
2358 deallocate_sdma_queue(dqm, q);
2360 if (q->properties.is_active) {
2361 decrement_queue_count(dqm, qpd, q);
2363 if (dqm->dev->kfd->shared_resources.enable_mes) {
2364 retval = remove_queue_mes(dqm, q, qpd);
2366 pr_err("Failed to remove queue %d\n",
2367 q->properties.queue_id);
2371 dqm->total_queue_count--;
2374 /* Unregister process */
2375 list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) {
2376 if (qpd == cur->qpd) {
2377 list_del(&cur->list);
2379 dqm->processes_count--;
2385 if (!dqm->dev->kfd->shared_resources.enable_mes)
2386 retval = execute_queues_cpsch(dqm, filter, 0, USE_DEFAULT_GRACE_PERIOD);
2388 if ((!dqm->is_hws_hang) && (retval || qpd->reset_wavefronts)) {
2389 pr_warn("Resetting wave fronts (cpsch) on dev %p\n", dqm->dev);
2390 dbgdev_wave_reset_wavefronts(dqm->dev, qpd->pqm->process);
2391 qpd->reset_wavefronts = false;
2394 /* Lastly, free mqd resources.
2395 * Do free_mqd() after dqm_unlock to avoid circular locking.
2397 while (!list_empty(&qpd->queues_list)) {
2398 q = list_first_entry(&qpd->queues_list, struct queue, list);
2399 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
2400 q->properties.type)];
2404 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
2409 /* Outside the DQM lock because under the DQM lock we can't do
2410 * reclaim or take other locks that others hold while reclaiming.
2413 kfd_dec_compute_active(dqm->dev);
2418 static int init_mqd_managers(struct device_queue_manager *dqm)
2421 struct mqd_manager *mqd_mgr;
2423 for (i = 0; i < KFD_MQD_TYPE_MAX; i++) {
2424 mqd_mgr = dqm->asic_ops.mqd_manager_init(i, dqm->dev);
2426 pr_err("mqd manager [%d] initialization failed\n", i);
2429 dqm->mqd_mgrs[i] = mqd_mgr;
2435 for (j = 0; j < i; j++) {
2436 kfree(dqm->mqd_mgrs[j]);
2437 dqm->mqd_mgrs[j] = NULL;
2443 /* Allocate one hiq mqd (HWS) and all SDMA mqd in a continuous trunk*/
2444 static int allocate_hiq_sdma_mqd(struct device_queue_manager *dqm)
2447 struct kfd_node *dev = dqm->dev;
2448 struct kfd_mem_obj *mem_obj = &dqm->hiq_sdma_mqd;
2449 uint32_t size = dqm->mqd_mgrs[KFD_MQD_TYPE_SDMA]->mqd_size *
2450 get_num_all_sdma_engines(dqm) *
2451 dev->kfd->device_info.num_sdma_queues_per_engine +
2452 (dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]->mqd_size *
2453 NUM_XCC(dqm->dev->xcc_mask));
2455 retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev, size,
2456 &(mem_obj->gtt_mem), &(mem_obj->gpu_addr),
2457 (void *)&(mem_obj->cpu_ptr), false);
2462 struct device_queue_manager *device_queue_manager_init(struct kfd_node *dev)
2464 struct device_queue_manager *dqm;
2466 pr_debug("Loading device queue manager\n");
2468 dqm = kzalloc(sizeof(*dqm), GFP_KERNEL);
2472 switch (dev->adev->asic_type) {
2473 /* HWS is not available on Hawaii. */
2475 /* HWS depends on CWSR for timely dequeue. CWSR is not
2476 * available on Tonga.
2478 * FIXME: This argument also applies to Kaveri.
2481 dqm->sched_policy = KFD_SCHED_POLICY_NO_HWS;
2484 dqm->sched_policy = sched_policy;
2489 switch (dqm->sched_policy) {
2490 case KFD_SCHED_POLICY_HWS:
2491 case KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION:
2492 /* initialize dqm for cp scheduling */
2493 dqm->ops.create_queue = create_queue_cpsch;
2494 dqm->ops.initialize = initialize_cpsch;
2495 dqm->ops.start = start_cpsch;
2496 dqm->ops.stop = stop_cpsch;
2497 dqm->ops.pre_reset = pre_reset;
2498 dqm->ops.destroy_queue = destroy_queue_cpsch;
2499 dqm->ops.update_queue = update_queue;
2500 dqm->ops.register_process = register_process;
2501 dqm->ops.unregister_process = unregister_process;
2502 dqm->ops.uninitialize = uninitialize;
2503 dqm->ops.create_kernel_queue = create_kernel_queue_cpsch;
2504 dqm->ops.destroy_kernel_queue = destroy_kernel_queue_cpsch;
2505 dqm->ops.set_cache_memory_policy = set_cache_memory_policy;
2506 dqm->ops.process_termination = process_termination_cpsch;
2507 dqm->ops.evict_process_queues = evict_process_queues_cpsch;
2508 dqm->ops.restore_process_queues = restore_process_queues_cpsch;
2509 dqm->ops.get_wave_state = get_wave_state;
2510 dqm->ops.reset_queues = reset_queues_cpsch;
2511 dqm->ops.get_queue_checkpoint_info = get_queue_checkpoint_info;
2512 dqm->ops.checkpoint_mqd = checkpoint_mqd;
2514 case KFD_SCHED_POLICY_NO_HWS:
2515 /* initialize dqm for no cp scheduling */
2516 dqm->ops.start = start_nocpsch;
2517 dqm->ops.stop = stop_nocpsch;
2518 dqm->ops.pre_reset = pre_reset;
2519 dqm->ops.create_queue = create_queue_nocpsch;
2520 dqm->ops.destroy_queue = destroy_queue_nocpsch;
2521 dqm->ops.update_queue = update_queue;
2522 dqm->ops.register_process = register_process;
2523 dqm->ops.unregister_process = unregister_process;
2524 dqm->ops.initialize = initialize_nocpsch;
2525 dqm->ops.uninitialize = uninitialize;
2526 dqm->ops.set_cache_memory_policy = set_cache_memory_policy;
2527 dqm->ops.process_termination = process_termination_nocpsch;
2528 dqm->ops.evict_process_queues = evict_process_queues_nocpsch;
2529 dqm->ops.restore_process_queues =
2530 restore_process_queues_nocpsch;
2531 dqm->ops.get_wave_state = get_wave_state;
2532 dqm->ops.get_queue_checkpoint_info = get_queue_checkpoint_info;
2533 dqm->ops.checkpoint_mqd = checkpoint_mqd;
2536 pr_err("Invalid scheduling policy %d\n", dqm->sched_policy);
2540 switch (dev->adev->asic_type) {
2542 device_queue_manager_init_vi(&dqm->asic_ops);
2546 device_queue_manager_init_cik(&dqm->asic_ops);
2550 device_queue_manager_init_cik_hawaii(&dqm->asic_ops);
2555 case CHIP_POLARIS10:
2556 case CHIP_POLARIS11:
2557 case CHIP_POLARIS12:
2559 device_queue_manager_init_vi_tonga(&dqm->asic_ops);
2563 if (KFD_GC_VERSION(dev) >= IP_VERSION(11, 0, 0))
2564 device_queue_manager_init_v11(&dqm->asic_ops);
2565 else if (KFD_GC_VERSION(dev) >= IP_VERSION(10, 1, 1))
2566 device_queue_manager_init_v10_navi10(&dqm->asic_ops);
2567 else if (KFD_GC_VERSION(dev) >= IP_VERSION(9, 0, 1))
2568 device_queue_manager_init_v9(&dqm->asic_ops);
2570 WARN(1, "Unexpected ASIC family %u",
2571 dev->adev->asic_type);
2576 if (init_mqd_managers(dqm))
2579 if (!dev->kfd->shared_resources.enable_mes && allocate_hiq_sdma_mqd(dqm)) {
2580 pr_err("Failed to allocate hiq sdma mqd trunk buffer\n");
2584 if (!dqm->ops.initialize(dqm)) {
2585 init_waitqueue_head(&dqm->destroy_wait);
2594 static void deallocate_hiq_sdma_mqd(struct kfd_node *dev,
2595 struct kfd_mem_obj *mqd)
2597 WARN(!mqd, "No hiq sdma mqd trunk to free");
2599 amdgpu_amdkfd_free_gtt_mem(dev->adev, mqd->gtt_mem);
2602 void device_queue_manager_uninit(struct device_queue_manager *dqm)
2605 dqm->ops.uninitialize(dqm);
2606 if (!dqm->dev->kfd->shared_resources.enable_mes)
2607 deallocate_hiq_sdma_mqd(dqm->dev, &dqm->hiq_sdma_mqd);
2611 int kfd_dqm_evict_pasid(struct device_queue_manager *dqm, u32 pasid)
2613 struct kfd_process_device *pdd;
2614 struct kfd_process *p = kfd_lookup_process_by_pasid(pasid);
2619 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid);
2620 pdd = kfd_get_process_device_data(dqm->dev, p);
2622 ret = dqm->ops.evict_process_queues(dqm, &pdd->qpd);
2623 kfd_unref_process(p);
2628 static void kfd_process_hw_exception(struct work_struct *work)
2630 struct device_queue_manager *dqm = container_of(work,
2631 struct device_queue_manager, hw_exception_work);
2632 amdgpu_amdkfd_gpu_reset(dqm->dev->adev);
2635 int reserve_debug_trap_vmid(struct device_queue_manager *dqm,
2636 struct qcm_process_device *qpd)
2639 int updated_vmid_mask;
2641 if (dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) {
2642 pr_err("Unsupported on sched_policy: %i\n", dqm->sched_policy);
2648 if (dqm->trap_debug_vmid != 0) {
2649 pr_err("Trap debug id already reserved\n");
2654 r = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0,
2655 USE_DEFAULT_GRACE_PERIOD, false);
2659 updated_vmid_mask = dqm->dev->kfd->shared_resources.compute_vmid_bitmap;
2660 updated_vmid_mask &= ~(1 << dqm->dev->vm_info.last_vmid_kfd);
2662 dqm->dev->kfd->shared_resources.compute_vmid_bitmap = updated_vmid_mask;
2663 dqm->trap_debug_vmid = dqm->dev->vm_info.last_vmid_kfd;
2664 r = set_sched_resources(dqm);
2668 r = map_queues_cpsch(dqm);
2672 pr_debug("Reserved VMID for trap debug: %i\n", dqm->trap_debug_vmid);
2680 * Releases vmid for the trap debugger
2682 int release_debug_trap_vmid(struct device_queue_manager *dqm,
2683 struct qcm_process_device *qpd)
2686 int updated_vmid_mask;
2687 uint32_t trap_debug_vmid;
2689 if (dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) {
2690 pr_err("Unsupported on sched_policy: %i\n", dqm->sched_policy);
2695 trap_debug_vmid = dqm->trap_debug_vmid;
2696 if (dqm->trap_debug_vmid == 0) {
2697 pr_err("Trap debug id is not reserved\n");
2702 r = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0,
2703 USE_DEFAULT_GRACE_PERIOD, false);
2707 updated_vmid_mask = dqm->dev->kfd->shared_resources.compute_vmid_bitmap;
2708 updated_vmid_mask |= (1 << dqm->dev->vm_info.last_vmid_kfd);
2710 dqm->dev->kfd->shared_resources.compute_vmid_bitmap = updated_vmid_mask;
2711 dqm->trap_debug_vmid = 0;
2712 r = set_sched_resources(dqm);
2716 r = map_queues_cpsch(dqm);
2720 pr_debug("Released VMID for trap debug: %i\n", trap_debug_vmid);
2727 #define QUEUE_NOT_FOUND -1
2728 /* invalidate queue operation in array */
2729 static void q_array_invalidate(uint32_t num_queues, uint32_t *queue_ids)
2733 for (i = 0; i < num_queues; i++)
2734 queue_ids[i] |= KFD_DBG_QUEUE_INVALID_MASK;
2737 /* find queue index in array */
2738 static int q_array_get_index(unsigned int queue_id,
2739 uint32_t num_queues,
2740 uint32_t *queue_ids)
2744 for (i = 0; i < num_queues; i++)
2745 if (queue_id == (queue_ids[i] & ~KFD_DBG_QUEUE_INVALID_MASK))
2748 return QUEUE_NOT_FOUND;
2751 struct copy_context_work_handler_workarea {
2752 struct work_struct copy_context_work;
2753 struct kfd_process *p;
2756 static void copy_context_work_handler (struct work_struct *work)
2758 struct copy_context_work_handler_workarea *workarea;
2759 struct mqd_manager *mqd_mgr;
2761 struct mm_struct *mm;
2762 struct kfd_process *p;
2763 uint32_t tmp_ctl_stack_used_size, tmp_save_area_used_size;
2766 workarea = container_of(work,
2767 struct copy_context_work_handler_workarea,
2771 mm = get_task_mm(p->lead_thread);
2777 for (i = 0; i < p->n_pdds; i++) {
2778 struct kfd_process_device *pdd = p->pdds[i];
2779 struct device_queue_manager *dqm = pdd->dev->dqm;
2780 struct qcm_process_device *qpd = &pdd->qpd;
2782 list_for_each_entry(q, &qpd->queues_list, list) {
2783 mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_CP];
2785 /* We ignore the return value from get_wave_state
2787 * i) right now, it always returns 0, and
2788 * ii) if we hit an error, we would continue to the
2789 * next queue anyway.
2791 mqd_mgr->get_wave_state(mqd_mgr,
2794 (void __user *) q->properties.ctx_save_restore_area_address,
2795 &tmp_ctl_stack_used_size,
2796 &tmp_save_area_used_size);
2799 kthread_unuse_mm(mm);
2803 static uint32_t *get_queue_ids(uint32_t num_queues, uint32_t *usr_queue_id_array)
2805 size_t array_size = num_queues * sizeof(uint32_t);
2806 uint32_t *queue_ids = NULL;
2808 if (!usr_queue_id_array)
2811 queue_ids = kzalloc(array_size, GFP_KERNEL);
2813 return ERR_PTR(-ENOMEM);
2815 if (copy_from_user(queue_ids, usr_queue_id_array, array_size))
2816 return ERR_PTR(-EFAULT);
2821 int resume_queues(struct kfd_process *p,
2822 uint32_t num_queues,
2823 uint32_t *usr_queue_id_array)
2825 uint32_t *queue_ids = NULL;
2826 int total_resumed = 0;
2829 if (usr_queue_id_array) {
2830 queue_ids = get_queue_ids(num_queues, usr_queue_id_array);
2832 if (IS_ERR(queue_ids))
2833 return PTR_ERR(queue_ids);
2835 /* mask all queues as invalid. unmask per successful request */
2836 q_array_invalidate(num_queues, queue_ids);
2839 for (i = 0; i < p->n_pdds; i++) {
2840 struct kfd_process_device *pdd = p->pdds[i];
2841 struct device_queue_manager *dqm = pdd->dev->dqm;
2842 struct qcm_process_device *qpd = &pdd->qpd;
2844 int r, per_device_resumed = 0;
2848 /* unmask queues that resume or already resumed as valid */
2849 list_for_each_entry(q, &qpd->queues_list, list) {
2850 int q_idx = QUEUE_NOT_FOUND;
2853 q_idx = q_array_get_index(
2854 q->properties.queue_id,
2858 if (!queue_ids || q_idx != QUEUE_NOT_FOUND) {
2859 int err = resume_single_queue(dqm, &pdd->qpd, q);
2864 ~KFD_DBG_QUEUE_INVALID_MASK;
2867 KFD_DBG_QUEUE_ERROR_MASK;
2872 if (dqm->dev->kfd->shared_resources.enable_mes) {
2873 wake_up_all(&dqm->destroy_wait);
2877 per_device_resumed++;
2882 if (!per_device_resumed) {
2887 r = execute_queues_cpsch(dqm,
2888 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES,
2890 USE_DEFAULT_GRACE_PERIOD);
2892 pr_err("Failed to resume process queues\n");
2894 list_for_each_entry(q, &qpd->queues_list, list) {
2895 int q_idx = q_array_get_index(
2896 q->properties.queue_id,
2900 /* mask queue as error on resume fail */
2901 if (q_idx != QUEUE_NOT_FOUND)
2903 KFD_DBG_QUEUE_ERROR_MASK;
2907 wake_up_all(&dqm->destroy_wait);
2908 total_resumed += per_device_resumed;
2915 if (copy_to_user((void __user *)usr_queue_id_array, queue_ids,
2916 num_queues * sizeof(uint32_t)))
2917 pr_err("copy_to_user failed on queue resume\n");
2922 return total_resumed;
2925 int suspend_queues(struct kfd_process *p,
2926 uint32_t num_queues,
2927 uint32_t grace_period,
2928 uint64_t exception_clear_mask,
2929 uint32_t *usr_queue_id_array)
2931 uint32_t *queue_ids = get_queue_ids(num_queues, usr_queue_id_array);
2932 int total_suspended = 0;
2935 if (IS_ERR(queue_ids))
2936 return PTR_ERR(queue_ids);
2938 /* mask all queues as invalid. umask on successful request */
2939 q_array_invalidate(num_queues, queue_ids);
2941 for (i = 0; i < p->n_pdds; i++) {
2942 struct kfd_process_device *pdd = p->pdds[i];
2943 struct device_queue_manager *dqm = pdd->dev->dqm;
2944 struct qcm_process_device *qpd = &pdd->qpd;
2946 int r, per_device_suspended = 0;
2948 mutex_lock(&p->event_mutex);
2951 /* unmask queues that suspend or already suspended */
2952 list_for_each_entry(q, &qpd->queues_list, list) {
2953 int q_idx = q_array_get_index(q->properties.queue_id,
2957 if (q_idx != QUEUE_NOT_FOUND) {
2958 int err = suspend_single_queue(dqm, pdd, q);
2959 bool is_mes = dqm->dev->kfd->shared_resources.enable_mes;
2962 queue_ids[q_idx] &= ~KFD_DBG_QUEUE_INVALID_MASK;
2963 if (exception_clear_mask && is_mes)
2964 q->properties.exception_status &=
2965 ~exception_clear_mask;
2970 per_device_suspended++;
2971 } else if (err != -EBUSY) {
2973 queue_ids[q_idx] |= KFD_DBG_QUEUE_ERROR_MASK;
2979 if (!per_device_suspended) {
2981 mutex_unlock(&p->event_mutex);
2982 if (total_suspended)
2983 amdgpu_amdkfd_debug_mem_fence(dqm->dev->adev);
2987 r = execute_queues_cpsch(dqm,
2988 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0,
2992 pr_err("Failed to suspend process queues.\n");
2994 total_suspended += per_device_suspended;
2996 list_for_each_entry(q, &qpd->queues_list, list) {
2997 int q_idx = q_array_get_index(q->properties.queue_id,
2998 num_queues, queue_ids);
3000 if (q_idx == QUEUE_NOT_FOUND)
3003 /* mask queue as error on suspend fail */
3005 queue_ids[q_idx] |= KFD_DBG_QUEUE_ERROR_MASK;
3006 else if (exception_clear_mask)
3007 q->properties.exception_status &=
3008 ~exception_clear_mask;
3012 mutex_unlock(&p->event_mutex);
3013 amdgpu_device_flush_hdp(dqm->dev->adev, NULL);
3016 if (total_suspended) {
3017 struct copy_context_work_handler_workarea copy_context_worker;
3020 ©_context_worker.copy_context_work,
3021 copy_context_work_handler);
3023 copy_context_worker.p = p;
3025 schedule_work(©_context_worker.copy_context_work);
3028 flush_work(©_context_worker.copy_context_work);
3029 destroy_work_on_stack(©_context_worker.copy_context_work);
3032 if (copy_to_user((void __user *)usr_queue_id_array, queue_ids,
3033 num_queues * sizeof(uint32_t)))
3034 pr_err("copy_to_user failed on queue suspend\n");
3038 return total_suspended;
3041 static uint32_t set_queue_type_for_user(struct queue_properties *q_props)
3043 switch (q_props->type) {
3044 case KFD_QUEUE_TYPE_COMPUTE:
3045 return q_props->format == KFD_QUEUE_FORMAT_PM4
3046 ? KFD_IOC_QUEUE_TYPE_COMPUTE
3047 : KFD_IOC_QUEUE_TYPE_COMPUTE_AQL;
3048 case KFD_QUEUE_TYPE_SDMA:
3049 return KFD_IOC_QUEUE_TYPE_SDMA;
3050 case KFD_QUEUE_TYPE_SDMA_XGMI:
3051 return KFD_IOC_QUEUE_TYPE_SDMA_XGMI;
3053 WARN_ONCE(true, "queue type not recognized!");
3058 void set_queue_snapshot_entry(struct queue *q,
3059 uint64_t exception_clear_mask,
3060 struct kfd_queue_snapshot_entry *qss_entry)
3062 qss_entry->ring_base_address = q->properties.queue_address;
3063 qss_entry->write_pointer_address = (uint64_t)q->properties.write_ptr;
3064 qss_entry->read_pointer_address = (uint64_t)q->properties.read_ptr;
3065 qss_entry->ctx_save_restore_address =
3066 q->properties.ctx_save_restore_area_address;
3067 qss_entry->ctx_save_restore_area_size =
3068 q->properties.ctx_save_restore_area_size;
3069 qss_entry->exception_status = q->properties.exception_status;
3070 qss_entry->queue_id = q->properties.queue_id;
3071 qss_entry->gpu_id = q->device->id;
3072 qss_entry->ring_size = (uint32_t)q->properties.queue_size;
3073 qss_entry->queue_type = set_queue_type_for_user(&q->properties);
3074 q->properties.exception_status &= ~exception_clear_mask;
3077 int debug_lock_and_unmap(struct device_queue_manager *dqm)
3081 if (dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) {
3082 pr_err("Unsupported on sched_policy: %i\n", dqm->sched_policy);
3086 if (!kfd_dbg_is_per_vmid_supported(dqm->dev))
3091 r = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, 0, false);
3098 int debug_map_and_unlock(struct device_queue_manager *dqm)
3102 if (dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) {
3103 pr_err("Unsupported on sched_policy: %i\n", dqm->sched_policy);
3107 if (!kfd_dbg_is_per_vmid_supported(dqm->dev))
3110 r = map_queues_cpsch(dqm);
3117 int debug_refresh_runlist(struct device_queue_manager *dqm)
3119 int r = debug_lock_and_unmap(dqm);
3124 return debug_map_and_unlock(dqm);
3127 #if defined(CONFIG_DEBUG_FS)
3129 static void seq_reg_dump(struct seq_file *m,
3130 uint32_t (*dump)[2], uint32_t n_regs)
3134 for (i = 0, count = 0; i < n_regs; i++) {
3136 dump[i-1][0] + sizeof(uint32_t) != dump[i][0]) {
3137 seq_printf(m, "%s %08x: %08x",
3139 dump[i][0], dump[i][1]);
3142 seq_printf(m, " %08x", dump[i][1]);
3150 int dqm_debugfs_hqds(struct seq_file *m, void *data)
3152 struct device_queue_manager *dqm = data;
3153 uint32_t xcc_mask = dqm->dev->xcc_mask;
3154 uint32_t (*dump)[2], n_regs;
3157 uint32_t sdma_engine_start;
3159 if (!dqm->sched_running) {
3160 seq_puts(m, " Device is stopped\n");
3164 for_each_inst(xcc_id, xcc_mask) {
3165 r = dqm->dev->kfd2kgd->hqd_dump(dqm->dev->adev,
3167 KFD_CIK_HIQ_QUEUE, &dump,
3172 " Inst %d, HIQ on MEC %d Pipe %d Queue %d\n",
3174 KFD_CIK_HIQ_PIPE / get_pipes_per_mec(dqm) + 1,
3175 KFD_CIK_HIQ_PIPE % get_pipes_per_mec(dqm),
3177 seq_reg_dump(m, dump, n_regs);
3182 for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) {
3183 int pipe_offset = pipe * get_queues_per_pipe(dqm);
3185 for (queue = 0; queue < get_queues_per_pipe(dqm); queue++) {
3186 if (!test_bit(pipe_offset + queue,
3187 dqm->dev->kfd->shared_resources.cp_queue_bitmap))
3190 r = dqm->dev->kfd2kgd->hqd_dump(dqm->dev->adev,
3198 " Inst %d, CP Pipe %d, Queue %d\n",
3199 xcc_id, pipe, queue);
3200 seq_reg_dump(m, dump, n_regs);
3207 sdma_engine_start = dqm->dev->node_id * get_num_all_sdma_engines(dqm);
3208 for (pipe = sdma_engine_start;
3209 pipe < (sdma_engine_start + get_num_all_sdma_engines(dqm));
3212 queue < dqm->dev->kfd->device_info.num_sdma_queues_per_engine;
3214 r = dqm->dev->kfd2kgd->hqd_sdma_dump(
3215 dqm->dev->adev, pipe, queue, &dump, &n_regs);
3219 seq_printf(m, " SDMA Engine %d, RLC %d\n",
3221 seq_reg_dump(m, dump, n_regs);
3230 int dqm_debugfs_hang_hws(struct device_queue_manager *dqm)
3235 r = pm_debugfs_hang_hws(&dqm->packet_mgr);
3240 dqm->active_runlist = true;
3241 r = execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES,
3242 0, USE_DEFAULT_GRACE_PERIOD);