drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <drm/drm_drv.h>
  26
  27 #include "amdgpu.h"
  28 #include "amdgpu_vcn.h"
  29 #include "amdgpu_pm.h"
  30 #include "soc15.h"
  31 #include "soc15d.h"
  32 #include "vcn_v2_0.h"
  33 #include "mmsch_v1_0.h"
  34 #include "vcn_v2_5.h"
  35
  36 #include "vcn/vcn_2_5_offset.h"
  37 #include "vcn/vcn_2_5_sh_mask.h"
  38 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
  39
  40 #define VCN_VID_SOC_ADDRESS_2_0                                 0x1fa00
  41 #define VCN1_VID_SOC_ADDRESS_3_0                                0x48200
  42
  43 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET                        0x27
  44 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET                    0x0f
  45 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET                  0x10
  46 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET                  0x11
  47 #define mmUVD_NO_OP_INTERNAL_OFFSET                             0x29
  48 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET                       0x66
  49 #define mmUVD_SCRATCH9_INTERNAL_OFFSET                          0xc01d
  50
  51 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET                   0x431
  52 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET          0x3b4
  53 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET         0x3b5
  54 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET                       0x25c
  55
  56 #define VCN25_MAX_HW_INSTANCES_ARCTURUS                 2
  57
  58 static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev);
  59 static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev);
  60 static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev);
  61 static int vcn_v2_5_set_powergating_state(void *handle,
  62                                 enum amd_powergating_state state);
  63 static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
  64                                 int inst_idx, struct dpg_pause_state *new_state);
  65 static int vcn_v2_5_sriov_start(struct amdgpu_device *adev);
  66 static void vcn_v2_5_set_ras_funcs(struct amdgpu_device *adev);
  67
  68 static int amdgpu_ih_clientid_vcns[] = {
  69         SOC15_IH_CLIENTID_VCN,
  70         SOC15_IH_CLIENTID_VCN1
  71 };
  72
  73 /**
  74  * vcn_v2_5_early_init - set function pointers and load microcode
  75  *
  76  * @handle: amdgpu_device pointer
  77  *
  78  * Set ring and irq function pointers
  79  * Load microcode from filesystem
  80  */
  81 static int vcn_v2_5_early_init(void *handle)
  82 {
  83         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  84
  85         if (amdgpu_sriov_vf(adev)) {
  86                 adev->vcn.num_vcn_inst = 2;
  87                 adev->vcn.harvest_config = 0;
  88                 adev->vcn.num_enc_rings = 1;
  89         } else {
  90                 u32 harvest;
  91                 int i;
  92
  93                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
  94                         harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING);
  95                         if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)
  96                                 adev->vcn.harvest_config |= 1 << i;
  97                 }
  98                 if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 |
  99                                         AMDGPU_VCN_HARVEST_VCN1))
 100                         /* both instances are harvested, disable the block */
 101                         return -ENOENT;
 102
 103                 adev->vcn.num_enc_rings = 2;
 104         }
 105
 106         vcn_v2_5_set_dec_ring_funcs(adev);
 107         vcn_v2_5_set_enc_ring_funcs(adev);
 108         vcn_v2_5_set_irq_funcs(adev);
 109         vcn_v2_5_set_ras_funcs(adev);
 110
 111         return amdgpu_vcn_early_init(adev);
 112 }
 113
 114 /**
 115  * vcn_v2_5_sw_init - sw init for VCN block
 116  *
 117  * @handle: amdgpu_device pointer
 118  *
 119  * Load firmware and sw initialization
 120  */
 121 static int vcn_v2_5_sw_init(void *handle)
 122 {
 123         struct amdgpu_ring *ring;
 124         int i, j, r;
 125         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 126
 127         for (j = 0; j < adev->vcn.num_vcn_inst; j++) {
 128                 if (adev->vcn.harvest_config & (1 << j))
 129                         continue;
 130                 /* VCN DEC TRAP */
 131                 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j],
 132                                 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[j].irq);
 133                 if (r)
 134                         return r;
 135
 136                 /* VCN ENC TRAP */
 137                 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 138                         r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j],
 139                                 i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[j].irq);
 140                         if (r)
 141                                 return r;
 142                 }
 143
 144                 /* VCN POISON TRAP */
 145                 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j],
 146                         VCN_2_6__SRCID_UVD_POISON, &adev->vcn.inst[j].ras_poison_irq);
 147                 if (r)
 148                         return r;
 149         }
 150
 151         r = amdgpu_vcn_sw_init(adev);
 152         if (r)
 153                 return r;
 154
 155         amdgpu_vcn_setup_ucode(adev);
 156
 157         r = amdgpu_vcn_resume(adev);
 158         if (r)
 159                 return r;
 160
 161         for (j = 0; j < adev->vcn.num_vcn_inst; j++) {
 162                 volatile struct amdgpu_fw_shared *fw_shared;
 163
 164                 if (adev->vcn.harvest_config & (1 << j))
 165                         continue;
 166                 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
 167                 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
 168                 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
 169                 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
 170                 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
 171                 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
 172
 173                 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
 174                 adev->vcn.inst[j].external.scratch9 = SOC15_REG_OFFSET(VCN, j, mmUVD_SCRATCH9);
 175                 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
 176                 adev->vcn.inst[j].external.data0 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA0);
 177                 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
 178                 adev->vcn.inst[j].external.data1 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA1);
 179                 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
 180                 adev->vcn.inst[j].external.cmd = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_CMD);
 181                 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
 182                 adev->vcn.inst[j].external.nop = SOC15_REG_OFFSET(VCN, j, mmUVD_NO_OP);
 183
 184                 ring = &adev->vcn.inst[j].ring_dec;
 185                 ring->use_doorbell = true;
 186
 187                 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
 188                                 (amdgpu_sriov_vf(adev) ? 2*j : 8*j);
 189
 190                 if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(2, 5, 0))
 191                         ring->vm_hub = AMDGPU_MMHUB_1;
 192                 else
 193                         ring->vm_hub = AMDGPU_MMHUB_0;
 194
 195                 sprintf(ring->name, "vcn_dec_%d", j);
 196                 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[j].irq,
 197                                      0, AMDGPU_RING_PRIO_DEFAULT, NULL);
 198                 if (r)
 199                         return r;
 200
 201                 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 202                         enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(i);
 203
 204                         ring = &adev->vcn.inst[j].ring_enc[i];
 205                         ring->use_doorbell = true;
 206
 207                         ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
 208                                         (amdgpu_sriov_vf(adev) ? (1 + i + 2*j) : (2 + i + 8*j));
 209
 210                         if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(2, 5, 0))
 211                                 ring->vm_hub = AMDGPU_MMHUB_1;
 212                         else
 213                                 ring->vm_hub = AMDGPU_MMHUB_0;
 214
 215                         sprintf(ring->name, "vcn_enc_%d.%d", j, i);
 216                         r = amdgpu_ring_init(adev, ring, 512,
 217                                              &adev->vcn.inst[j].irq, 0,
 218                                              hw_prio, NULL);
 219                         if (r)
 220                                 return r;
 221                 }
 222
 223                 fw_shared = adev->vcn.inst[j].fw_shared.cpu_addr;
 224                 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG);
 225
 226                 if (amdgpu_vcnfw_log)
 227                         amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);
 228         }
 229
 230         if (amdgpu_sriov_vf(adev)) {
 231                 r = amdgpu_virt_alloc_mm_table(adev);
 232                 if (r)
 233                         return r;
 234         }
 235
 236         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
 237                 adev->vcn.pause_dpg_mode = vcn_v2_5_pause_dpg_mode;
 238
 239         r = amdgpu_vcn_ras_sw_init(adev);
 240         if (r)
 241                 return r;
 242
 243         return 0;
 244 }
 245
 246 /**
 247  * vcn_v2_5_sw_fini - sw fini for VCN block
 248  *
 249  * @handle: amdgpu_device pointer
 250  *
 251  * VCN suspend and free up sw allocation
 252  */
 253 static int vcn_v2_5_sw_fini(void *handle)
 254 {
 255         int i, r, idx;
 256         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 257         volatile struct amdgpu_fw_shared *fw_shared;
 258
 259         if (drm_dev_enter(adev_to_drm(adev), &idx)) {
 260                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 261                         if (adev->vcn.harvest_config & (1 << i))
 262                                 continue;
 263                         fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
 264                         fw_shared->present_flag_0 = 0;
 265                 }
 266                 drm_dev_exit(idx);
 267         }
 268
 269
 270         if (amdgpu_sriov_vf(adev))
 271                 amdgpu_virt_free_mm_table(adev);
 272
 273         r = amdgpu_vcn_suspend(adev);
 274         if (r)
 275                 return r;
 276
 277         r = amdgpu_vcn_sw_fini(adev);
 278
 279         return r;
 280 }
 281
 282 /**
 283  * vcn_v2_5_hw_init - start and test VCN block
 284  *
 285  * @handle: amdgpu_device pointer
 286  *
 287  * Initialize the hardware, boot up the VCPU and do some testing
 288  */
 289 static int vcn_v2_5_hw_init(void *handle)
 290 {
 291         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 292         struct amdgpu_ring *ring;
 293         int i, j, r = 0;
 294
 295         if (amdgpu_sriov_vf(adev))
 296                 r = vcn_v2_5_sriov_start(adev);
 297
 298         for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
 299                 if (adev->vcn.harvest_config & (1 << j))
 300                         continue;
 301
 302                 if (amdgpu_sriov_vf(adev)) {
 303                         adev->vcn.inst[j].ring_enc[0].sched.ready = true;
 304                         adev->vcn.inst[j].ring_enc[1].sched.ready = false;
 305                         adev->vcn.inst[j].ring_enc[2].sched.ready = false;
 306                         adev->vcn.inst[j].ring_dec.sched.ready = true;
 307                 } else {
 308
 309                         ring = &adev->vcn.inst[j].ring_dec;
 310
 311                         adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
 312                                                      ring->doorbell_index, j);
 313
 314                         r = amdgpu_ring_test_helper(ring);
 315                         if (r)
 316                                 goto done;
 317
 318                         for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 319                                 ring = &adev->vcn.inst[j].ring_enc[i];
 320                                 r = amdgpu_ring_test_helper(ring);
 321                                 if (r)
 322                                         goto done;
 323                         }
 324                 }
 325         }
 326
 327 done:
 328         if (!r)
 329                 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",
 330                         (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");
 331
 332         return r;
 333 }
 334
 335 /**
 336  * vcn_v2_5_hw_fini - stop the hardware block
 337  *
 338  * @handle: amdgpu_device pointer
 339  *
 340  * Stop the VCN block, mark ring as not ready any more
 341  */
 342 static int vcn_v2_5_hw_fini(void *handle)
 343 {
 344         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 345         int i;
 346
 347         cancel_delayed_work_sync(&adev->vcn.idle_work);
 348
 349         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 350                 if (adev->vcn.harvest_config & (1 << i))
 351                         continue;
 352
 353                 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
 354                     (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
 355                      RREG32_SOC15(VCN, i, mmUVD_STATUS)))
 356                         vcn_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
 357
 358                 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
 359                         amdgpu_irq_put(adev, &adev->vcn.inst[i].ras_poison_irq, 0);
 360         }
 361
 362         return 0;
 363 }
 364
 365 /**
 366  * vcn_v2_5_suspend - suspend VCN block
 367  *
 368  * @handle: amdgpu_device pointer
 369  *
 370  * HW fini and suspend VCN block
 371  */
 372 static int vcn_v2_5_suspend(void *handle)
 373 {
 374         int r;
 375         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 376
 377         r = vcn_v2_5_hw_fini(adev);
 378         if (r)
 379                 return r;
 380
 381         r = amdgpu_vcn_suspend(adev);
 382
 383         return r;
 384 }
 385
 386 /**
 387  * vcn_v2_5_resume - resume VCN block
 388  *
 389  * @handle: amdgpu_device pointer
 390  *
 391  * Resume firmware and hw init VCN block
 392  */
 393 static int vcn_v2_5_resume(void *handle)
 394 {
 395         int r;
 396         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 397
 398         r = amdgpu_vcn_resume(adev);
 399         if (r)
 400                 return r;
 401
 402         r = vcn_v2_5_hw_init(adev);
 403
 404         return r;
 405 }
 406
 407 /**
 408  * vcn_v2_5_mc_resume - memory controller programming
 409  *
 410  * @adev: amdgpu_device pointer
 411  *
 412  * Let the VCN memory controller know it's offsets
 413  */
 414 static void vcn_v2_5_mc_resume(struct amdgpu_device *adev)
 415 {
 416         uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
 417         uint32_t offset;
 418         int i;
 419
 420         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 421                 if (adev->vcn.harvest_config & (1 << i))
 422                         continue;
 423                 /* cache window 0: fw */
 424                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 425                         WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 426                                 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo));
 427                         WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 428                                 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi));
 429                         WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0, 0);
 430                         offset = 0;
 431                 } else {
 432                         WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 433                                 lower_32_bits(adev->vcn.inst[i].gpu_addr));
 434                         WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 435                                 upper_32_bits(adev->vcn.inst[i].gpu_addr));
 436                         offset = size;
 437                         WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0,
 438                                 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
 439                 }
 440                 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE0, size);
 441
 442                 /* cache window 1: stack */
 443                 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
 444                         lower_32_bits(adev->vcn.inst[i].gpu_addr + offset));
 445                 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
 446                         upper_32_bits(adev->vcn.inst[i].gpu_addr + offset));
 447                 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET1, 0);
 448                 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
 449
 450                 /* cache window 2: context */
 451                 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
 452                         lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
 453                 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
 454                         upper_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
 455                 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET2, 0);
 456                 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
 457
 458                 /* non-cache window */
 459                 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,
 460                         lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr));
 461                 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,
 462                         upper_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr));
 463                 WREG32_SOC15(VCN, i, mmUVD_VCPU_NONCACHE_OFFSET0, 0);
 464                 WREG32_SOC15(VCN, i, mmUVD_VCPU_NONCACHE_SIZE0,
 465                         AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)));
 466         }
 467 }
 468
 469 static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
 470 {
 471         uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
 472         uint32_t offset;
 473
 474         /* cache window 0: fw */
 475         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 476                 if (!indirect) {
 477                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 478                                 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 479                                 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect);
 480                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 481                                 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 482                                 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect);
 483                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 484                                 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
 485                 } else {
 486                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 487                                 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
 488                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 489                                 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
 490                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 491                                 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
 492                 }
 493                 offset = 0;
 494         } else {
 495                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 496                         VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 497                         lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
 498                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 499                         VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 500                         upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
 501                 offset = size;
 502                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 503                         VCN, 0, mmUVD_VCPU_CACHE_OFFSET0),
 504                         AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
 505         }
 506
 507         if (!indirect)
 508                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 509                         VCN, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
 510         else
 511                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 512                         VCN, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
 513
 514         /* cache window 1: stack */
 515         if (!indirect) {
 516                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 517                         VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
 518                         lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
 519                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 520                         VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
 521                         upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
 522                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 523                         VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
 524         } else {
 525                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 526                         VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
 527                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 528                         VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
 529                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 530                         VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
 531         }
 532         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 533                 VCN, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
 534
 535         /* cache window 2: context */
 536         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 537                 VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
 538                 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
 539         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 540                 VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
 541                 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
 542         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 543                 VCN, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
 544         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 545                 VCN, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
 546
 547         /* non-cache window */
 548         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 549                 VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
 550                 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
 551         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 552                 VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
 553                 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
 554         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 555                 VCN, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
 556         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 557                 VCN, 0, mmUVD_VCPU_NONCACHE_SIZE0),
 558                 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect);
 559
 560         /* VCN global tiling registers */
 561         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 562                 VCN, 0, mmUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
 563 }
 564
 565 /**
 566  * vcn_v2_5_disable_clock_gating - disable VCN clock gating
 567  *
 568  * @adev: amdgpu_device pointer
 569  *
 570  * Disable clock gating for VCN block
 571  */
 572 static void vcn_v2_5_disable_clock_gating(struct amdgpu_device *adev)
 573 {
 574         uint32_t data;
 575         int i;
 576
 577         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 578                 if (adev->vcn.harvest_config & (1 << i))
 579                         continue;
 580                 /* UVD disable CGC */
 581                 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
 582                 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 583                         data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 584                 else
 585                         data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 586                 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 587                 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 588                 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
 589
 590                 data = RREG32_SOC15(VCN, i, mmUVD_CGC_GATE);
 591                 data &= ~(UVD_CGC_GATE__SYS_MASK
 592                         | UVD_CGC_GATE__UDEC_MASK
 593                         | UVD_CGC_GATE__MPEG2_MASK
 594                         | UVD_CGC_GATE__REGS_MASK
 595                         | UVD_CGC_GATE__RBC_MASK
 596                         | UVD_CGC_GATE__LMI_MC_MASK
 597                         | UVD_CGC_GATE__LMI_UMC_MASK
 598                         | UVD_CGC_GATE__IDCT_MASK
 599                         | UVD_CGC_GATE__MPRD_MASK
 600                         | UVD_CGC_GATE__MPC_MASK
 601                         | UVD_CGC_GATE__LBSI_MASK
 602                         | UVD_CGC_GATE__LRBBM_MASK
 603                         | UVD_CGC_GATE__UDEC_RE_MASK
 604                         | UVD_CGC_GATE__UDEC_CM_MASK
 605                         | UVD_CGC_GATE__UDEC_IT_MASK
 606                         | UVD_CGC_GATE__UDEC_DB_MASK
 607                         | UVD_CGC_GATE__UDEC_MP_MASK
 608                         | UVD_CGC_GATE__WCB_MASK
 609                         | UVD_CGC_GATE__VCPU_MASK
 610                         | UVD_CGC_GATE__MMSCH_MASK);
 611
 612                 WREG32_SOC15(VCN, i, mmUVD_CGC_GATE, data);
 613
 614                 SOC15_WAIT_ON_RREG(VCN, i, mmUVD_CGC_GATE, 0,  0xFFFFFFFF);
 615
 616                 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
 617                 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
 618                         | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
 619                         | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
 620                         | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
 621                         | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
 622                         | UVD_CGC_CTRL__SYS_MODE_MASK
 623                         | UVD_CGC_CTRL__UDEC_MODE_MASK
 624                         | UVD_CGC_CTRL__MPEG2_MODE_MASK
 625                         | UVD_CGC_CTRL__REGS_MODE_MASK
 626                         | UVD_CGC_CTRL__RBC_MODE_MASK
 627                         | UVD_CGC_CTRL__LMI_MC_MODE_MASK
 628                         | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 629                         | UVD_CGC_CTRL__IDCT_MODE_MASK
 630                         | UVD_CGC_CTRL__MPRD_MODE_MASK
 631                         | UVD_CGC_CTRL__MPC_MODE_MASK
 632                         | UVD_CGC_CTRL__LBSI_MODE_MASK
 633                         | UVD_CGC_CTRL__LRBBM_MODE_MASK
 634                         | UVD_CGC_CTRL__WCB_MODE_MASK
 635                         | UVD_CGC_CTRL__VCPU_MODE_MASK
 636                         | UVD_CGC_CTRL__MMSCH_MODE_MASK);
 637                 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
 638
 639                 /* turn on */
 640                 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE);
 641                 data |= (UVD_SUVD_CGC_GATE__SRE_MASK
 642                         | UVD_SUVD_CGC_GATE__SIT_MASK
 643                         | UVD_SUVD_CGC_GATE__SMP_MASK
 644                         | UVD_SUVD_CGC_GATE__SCM_MASK
 645                         | UVD_SUVD_CGC_GATE__SDB_MASK
 646                         | UVD_SUVD_CGC_GATE__SRE_H264_MASK
 647                         | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
 648                         | UVD_SUVD_CGC_GATE__SIT_H264_MASK
 649                         | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
 650                         | UVD_SUVD_CGC_GATE__SCM_H264_MASK
 651                         | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
 652                         | UVD_SUVD_CGC_GATE__SDB_H264_MASK
 653                         | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
 654                         | UVD_SUVD_CGC_GATE__SCLR_MASK
 655                         | UVD_SUVD_CGC_GATE__UVD_SC_MASK
 656                         | UVD_SUVD_CGC_GATE__ENT_MASK
 657                         | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
 658                         | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
 659                         | UVD_SUVD_CGC_GATE__SITE_MASK
 660                         | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
 661                         | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
 662                         | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
 663                         | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
 664                         | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
 665                 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE, data);
 666
 667                 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL);
 668                 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 669                         | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 670                         | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 671                         | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 672                         | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 673                         | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
 674                         | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
 675                         | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 676                         | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 677                         | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
 678                 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data);
 679         }
 680 }
 681
 682 static void vcn_v2_5_clock_gating_dpg_mode(struct amdgpu_device *adev,
 683                 uint8_t sram_sel, int inst_idx, uint8_t indirect)
 684 {
 685         uint32_t reg_data = 0;
 686
 687         /* enable sw clock gating control */
 688         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 689                 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 690         else
 691                 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 692         reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 693         reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 694         reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
 695                  UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
 696                  UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
 697                  UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
 698                  UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
 699                  UVD_CGC_CTRL__SYS_MODE_MASK |
 700                  UVD_CGC_CTRL__UDEC_MODE_MASK |
 701                  UVD_CGC_CTRL__MPEG2_MODE_MASK |
 702                  UVD_CGC_CTRL__REGS_MODE_MASK |
 703                  UVD_CGC_CTRL__RBC_MODE_MASK |
 704                  UVD_CGC_CTRL__LMI_MC_MODE_MASK |
 705                  UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
 706                  UVD_CGC_CTRL__IDCT_MODE_MASK |
 707                  UVD_CGC_CTRL__MPRD_MODE_MASK |
 708                  UVD_CGC_CTRL__MPC_MODE_MASK |
 709                  UVD_CGC_CTRL__LBSI_MODE_MASK |
 710                  UVD_CGC_CTRL__LRBBM_MODE_MASK |
 711                  UVD_CGC_CTRL__WCB_MODE_MASK |
 712                  UVD_CGC_CTRL__VCPU_MODE_MASK |
 713                  UVD_CGC_CTRL__MMSCH_MODE_MASK);
 714         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 715                 VCN, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
 716
 717         /* turn off clock gating */
 718         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 719                 VCN, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect);
 720
 721         /* turn on SUVD clock gating */
 722         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 723                 VCN, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
 724
 725         /* turn on sw mode in UVD_SUVD_CGC_CTRL */
 726         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 727                 VCN, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
 728 }
 729
 730 /**
 731  * vcn_v2_5_enable_clock_gating - enable VCN clock gating
 732  *
 733  * @adev: amdgpu_device pointer
 734  *
 735  * Enable clock gating for VCN block
 736  */
 737 static void vcn_v2_5_enable_clock_gating(struct amdgpu_device *adev)
 738 {
 739         uint32_t data = 0;
 740         int i;
 741
 742         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 743                 if (adev->vcn.harvest_config & (1 << i))
 744                         continue;
 745                 /* enable UVD CGC */
 746                 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
 747                 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 748                         data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 749                 else
 750                         data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 751                 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 752                 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 753                 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
 754
 755                 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
 756                 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
 757                         | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
 758                         | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
 759                         | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
 760                         | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
 761                         | UVD_CGC_CTRL__SYS_MODE_MASK
 762                         | UVD_CGC_CTRL__UDEC_MODE_MASK
 763                         | UVD_CGC_CTRL__MPEG2_MODE_MASK
 764                         | UVD_CGC_CTRL__REGS_MODE_MASK
 765                         | UVD_CGC_CTRL__RBC_MODE_MASK
 766                         | UVD_CGC_CTRL__LMI_MC_MODE_MASK
 767                         | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 768                         | UVD_CGC_CTRL__IDCT_MODE_MASK
 769                         | UVD_CGC_CTRL__MPRD_MODE_MASK
 770                         | UVD_CGC_CTRL__MPC_MODE_MASK
 771                         | UVD_CGC_CTRL__LBSI_MODE_MASK
 772                         | UVD_CGC_CTRL__LRBBM_MODE_MASK
 773                         | UVD_CGC_CTRL__WCB_MODE_MASK
 774                         | UVD_CGC_CTRL__VCPU_MODE_MASK);
 775                 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
 776
 777                 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL);
 778                 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 779                         | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 780                         | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 781                         | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 782                         | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 783                         | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
 784                         | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
 785                         | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 786                         | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 787                         | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
 788                 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data);
 789         }
 790 }
 791
 792 static void vcn_v2_6_enable_ras(struct amdgpu_device *adev, int inst_idx,
 793                                 bool indirect)
 794 {
 795         uint32_t tmp;
 796
 797         if (adev->ip_versions[UVD_HWIP][0] != IP_VERSION(2, 6, 0))
 798                 return;
 799
 800         tmp = VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK |
 801               VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK |
 802               VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK |
 803               VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK;
 804         WREG32_SOC15_DPG_MODE(inst_idx,
 805                               SOC15_DPG_MODE_OFFSET(VCN, 0, mmVCN_RAS_CNTL),
 806                               tmp, 0, indirect);
 807
 808         tmp = UVD_VCPU_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK;
 809         WREG32_SOC15_DPG_MODE(inst_idx,
 810                               SOC15_DPG_MODE_OFFSET(VCN, 0, mmUVD_VCPU_INT_EN),
 811                               tmp, 0, indirect);
 812
 813         tmp = UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK;
 814         WREG32_SOC15_DPG_MODE(inst_idx,
 815                               SOC15_DPG_MODE_OFFSET(VCN, 0, mmUVD_SYS_INT_EN),
 816                               tmp, 0, indirect);
 817 }
 818
 819 static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
 820 {
 821         volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
 822         struct amdgpu_ring *ring;
 823         uint32_t rb_bufsz, tmp;
 824
 825         /* disable register anti-hang mechanism */
 826         WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1,
 827                 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
 828         /* enable dynamic power gating mode */
 829         tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS);
 830         tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
 831         tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
 832         WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp);
 833
 834         if (indirect)
 835                 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;
 836
 837         /* enable clock gating */
 838         vcn_v2_5_clock_gating_dpg_mode(adev, 0, inst_idx, indirect);
 839
 840         /* enable VCPU clock */
 841         tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
 842         tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
 843         tmp |= UVD_VCPU_CNTL__BLK_RST_MASK;
 844         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 845                 VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
 846
 847         /* disable master interupt */
 848         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 849                 VCN, 0, mmUVD_MASTINT_EN), 0, 0, indirect);
 850
 851         /* setup mmUVD_LMI_CTRL */
 852         tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 853                 UVD_LMI_CTRL__REQ_MODE_MASK |
 854                 UVD_LMI_CTRL__CRC_RESET_MASK |
 855                 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
 856                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 857                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 858                 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 859                 0x00100000L);
 860         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 861                 VCN, 0, mmUVD_LMI_CTRL), tmp, 0, indirect);
 862
 863         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 864                 VCN, 0, mmUVD_MPC_CNTL),
 865                 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
 866
 867         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 868                 VCN, 0, mmUVD_MPC_SET_MUXA0),
 869                 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
 870                  (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
 871                  (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
 872                  (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
 873
 874         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 875                 VCN, 0, mmUVD_MPC_SET_MUXB0),
 876                 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
 877                  (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
 878                  (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
 879                  (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
 880
 881         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 882                 VCN, 0, mmUVD_MPC_SET_MUX),
 883                 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
 884                  (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
 885                  (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
 886
 887         vcn_v2_5_mc_resume_dpg_mode(adev, inst_idx, indirect);
 888
 889         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 890                 VCN, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
 891         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 892                 VCN, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
 893
 894         /* enable LMI MC and UMC channels */
 895         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 896                 VCN, 0, mmUVD_LMI_CTRL2), 0, 0, indirect);
 897
 898         vcn_v2_6_enable_ras(adev, inst_idx, indirect);
 899
 900         /* unblock VCPU register access */
 901         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 902                 VCN, 0, mmUVD_RB_ARB_CTRL), 0, 0, indirect);
 903
 904         tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
 905         tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
 906         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 907                 VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
 908
 909         /* enable master interrupt */
 910         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 911                 VCN, 0, mmUVD_MASTINT_EN),
 912                 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
 913
 914         if (indirect)
 915                 psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr,
 916                                     (uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr -
 917                                                (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr));
 918
 919         ring = &adev->vcn.inst[inst_idx].ring_dec;
 920         /* force RBC into idle state */
 921         rb_bufsz = order_base_2(ring->ring_size);
 922         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
 923         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
 924         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
 925         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
 926         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
 927         WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp);
 928
 929         /* Stall DPG before WPTR/RPTR reset */
 930         WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
 931                 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
 932                 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
 933         fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;
 934
 935         /* set the write pointer delay */
 936         WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0);
 937
 938         /* set the wb address */
 939         WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR,
 940                 (upper_32_bits(ring->gpu_addr) >> 2));
 941
 942         /* program the RB_BASE for ring buffer */
 943         WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
 944                 lower_32_bits(ring->gpu_addr));
 945         WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
 946                 upper_32_bits(ring->gpu_addr));
 947
 948         /* Initialize the ring buffer's read and write pointers */
 949         WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0);
 950
 951         WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0);
 952
 953         ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR);
 954         WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR,
 955                 lower_32_bits(ring->wptr));
 956
 957         fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET;
 958         /* Unstall DPG */
 959         WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
 960                 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
 961
 962         return 0;
 963 }
 964
 965 static int vcn_v2_5_start(struct amdgpu_device *adev)
 966 {
 967         struct amdgpu_ring *ring;
 968         uint32_t rb_bufsz, tmp;
 969         int i, j, k, r;
 970
 971         if (adev->pm.dpm_enabled)
 972                 amdgpu_dpm_enable_uvd(adev, true);
 973
 974         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 975                 if (adev->vcn.harvest_config & (1 << i))
 976                         continue;
 977                 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
 978                         r = vcn_v2_5_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
 979                         continue;
 980                 }
 981
 982                 /* disable register anti-hang mechanism */
 983                 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), 0,
 984                         ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
 985
 986                 /* set uvd status busy */
 987                 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
 988                 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp);
 989         }
 990
 991         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
 992                 return 0;
 993
 994         /*SW clock gating */
 995         vcn_v2_5_disable_clock_gating(adev);
 996
 997         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 998                 if (adev->vcn.harvest_config & (1 << i))
 999                         continue;
1000                 /* enable VCPU clock */
1001                 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
1002                         UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
1003
1004                 /* disable master interrupt */
1005                 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0,
1006                         ~UVD_MASTINT_EN__VCPU_EN_MASK);
1007
1008                 /* setup mmUVD_LMI_CTRL */
1009                 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL);
1010                 tmp &= ~0xff;
1011                 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp | 0x8|
1012                         UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
1013                         UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
1014                         UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
1015                         UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
1016
1017                 /* setup mmUVD_MPC_CNTL */
1018                 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL);
1019                 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
1020                 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
1021                 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp);
1022
1023                 /* setup UVD_MPC_SET_MUXA0 */
1024                 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0,
1025                         ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
1026                         (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
1027                         (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1028                         (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
1029
1030                 /* setup UVD_MPC_SET_MUXB0 */
1031                 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0,
1032                         ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
1033                         (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
1034                         (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
1035                         (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
1036
1037                 /* setup mmUVD_MPC_SET_MUX */
1038                 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX,
1039                         ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
1040                         (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
1041                         (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
1042         }
1043
1044         vcn_v2_5_mc_resume(adev);
1045
1046         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1047                 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
1048                 if (adev->vcn.harvest_config & (1 << i))
1049                         continue;
1050                 /* VCN global tiling registers */
1051                 WREG32_SOC15(VCN, i, mmUVD_GFX8_ADDR_CONFIG,
1052                         adev->gfx.config.gb_addr_config);
1053                 WREG32_SOC15(VCN, i, mmUVD_GFX8_ADDR_CONFIG,
1054                         adev->gfx.config.gb_addr_config);
1055
1056                 /* enable LMI MC and UMC channels */
1057                 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0,
1058                         ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1059
1060                 /* unblock VCPU register access */
1061                 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0,
1062                         ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
1063
1064                 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
1065                         ~UVD_VCPU_CNTL__BLK_RST_MASK);
1066
1067                 for (k = 0; k < 10; ++k) {
1068                         uint32_t status;
1069
1070                         for (j = 0; j < 100; ++j) {
1071                                 status = RREG32_SOC15(VCN, i, mmUVD_STATUS);
1072                                 if (status & 2)
1073                                         break;
1074                                 if (amdgpu_emu_mode == 1)
1075                                         msleep(500);
1076                                 else
1077                                         mdelay(10);
1078                         }
1079                         r = 0;
1080                         if (status & 2)
1081                                 break;
1082
1083                         DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
1084                         WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
1085                                 UVD_VCPU_CNTL__BLK_RST_MASK,
1086                                 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1087                         mdelay(10);
1088                         WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
1089                                 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1090
1091                         mdelay(10);
1092                         r = -1;
1093                 }
1094
1095                 if (r) {
1096                         DRM_ERROR("VCN decode not responding, giving up!!!\n");
1097                         return r;
1098                 }
1099
1100                 /* enable master interrupt */
1101                 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN),
1102                         UVD_MASTINT_EN__VCPU_EN_MASK,
1103                         ~UVD_MASTINT_EN__VCPU_EN_MASK);
1104
1105                 /* clear the busy bit of VCN_STATUS */
1106                 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0,
1107                         ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1108
1109                 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0);
1110
1111                 ring = &adev->vcn.inst[i].ring_dec;
1112                 /* force RBC into idle state */
1113                 rb_bufsz = order_base_2(ring->ring_size);
1114                 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1115                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1116                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1117                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1118                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1119                 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp);
1120
1121                 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;
1122                 /* program the RB_BASE for ring buffer */
1123                 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1124                         lower_32_bits(ring->gpu_addr));
1125                 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1126                         upper_32_bits(ring->gpu_addr));
1127
1128                 /* Initialize the ring buffer's read and write pointers */
1129                 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0);
1130
1131                 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR);
1132                 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR,
1133                                 lower_32_bits(ring->wptr));
1134                 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET;
1135
1136                 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET;
1137                 ring = &adev->vcn.inst[i].ring_enc[0];
1138                 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1139                 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1140                 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr);
1141                 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1142                 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4);
1143                 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET;
1144
1145                 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET;
1146                 ring = &adev->vcn.inst[i].ring_enc[1];
1147                 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1148                 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1149                 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1150                 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1151                 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4);
1152                 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET;
1153         }
1154
1155         return 0;
1156 }
1157
1158 static int vcn_v2_5_mmsch_start(struct amdgpu_device *adev,
1159                                 struct amdgpu_mm_table *table)
1160 {
1161         uint32_t data = 0, loop = 0, size = 0;
1162         uint64_t addr = table->gpu_addr;
1163         struct mmsch_v1_1_init_header *header = NULL;
1164
1165         header = (struct mmsch_v1_1_init_header *)table->cpu_addr;
1166         size = header->total_size;
1167
1168         /*
1169          * 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr of
1170          *  memory descriptor location
1171          */
1172         WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr));
1173         WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr));
1174
1175         /* 2, update vmid of descriptor */
1176         data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID);
1177         data &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
1178         /* use domain0 for MM scheduler */
1179         data |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
1180         WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, data);
1181
1182         /* 3, notify mmsch about the size of this descriptor */
1183         WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size);
1184
1185         /* 4, set resp to zero */
1186         WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0);
1187
1188         /*
1189          * 5, kick off the initialization and wait until
1190          * VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero
1191          */
1192         WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, 0x10000001);
1193
1194         data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP);
1195         loop = 10;
1196         while ((data & 0x10000002) != 0x10000002) {
1197                 udelay(100);
1198                 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP);
1199                 loop--;
1200                 if (!loop)
1201                         break;
1202         }
1203
1204         if (!loop) {
1205                 dev_err(adev->dev,
1206                         "failed to init MMSCH, mmMMSCH_VF_MAILBOX_RESP = %x\n",
1207                         data);
1208                 return -EBUSY;
1209         }
1210
1211         return 0;
1212 }
1213
1214 static int vcn_v2_5_sriov_start(struct amdgpu_device *adev)
1215 {
1216         struct amdgpu_ring *ring;
1217         uint32_t offset, size, tmp, i, rb_bufsz;
1218         uint32_t table_size = 0;
1219         struct mmsch_v1_0_cmd_direct_write direct_wt = { { 0 } };
1220         struct mmsch_v1_0_cmd_direct_read_modify_write direct_rd_mod_wt = { { 0 } };
1221         struct mmsch_v1_0_cmd_end end = { { 0 } };
1222         uint32_t *init_table = adev->virt.mm_table.cpu_addr;
1223         struct mmsch_v1_1_init_header *header = (struct mmsch_v1_1_init_header *)init_table;
1224
1225         direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE;
1226         direct_rd_mod_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
1227         end.cmd_header.command_type = MMSCH_COMMAND__END;
1228
1229         header->version = MMSCH_VERSION;
1230         header->total_size = sizeof(struct mmsch_v1_1_init_header) >> 2;
1231         init_table += header->total_size;
1232
1233         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1234                 header->eng[i].table_offset = header->total_size;
1235                 header->eng[i].init_status = 0;
1236                 header->eng[i].table_size = 0;
1237
1238                 table_size = 0;
1239
1240                 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(
1241                         SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS),
1242                         ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY);
1243
1244                 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
1245                 /* mc resume*/
1246                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1247                         MMSCH_V1_0_INSERT_DIRECT_WT(
1248                                 SOC15_REG_OFFSET(VCN, i,
1249                                         mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1250                                 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo);
1251                         MMSCH_V1_0_INSERT_DIRECT_WT(
1252                                 SOC15_REG_OFFSET(VCN, i,
1253                                         mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1254                                 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi);
1255                         offset = 0;
1256                         MMSCH_V1_0_INSERT_DIRECT_WT(
1257                                 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0), 0);
1258                 } else {
1259                         MMSCH_V1_0_INSERT_DIRECT_WT(
1260                                 SOC15_REG_OFFSET(VCN, i,
1261                                         mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1262                                 lower_32_bits(adev->vcn.inst[i].gpu_addr));
1263                         MMSCH_V1_0_INSERT_DIRECT_WT(
1264                                 SOC15_REG_OFFSET(VCN, i,
1265                                         mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1266                                 upper_32_bits(adev->vcn.inst[i].gpu_addr));
1267                         offset = size;
1268                         MMSCH_V1_0_INSERT_DIRECT_WT(
1269                                 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0),
1270                                 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
1271                 }
1272
1273                 MMSCH_V1_0_INSERT_DIRECT_WT(
1274                         SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE0),
1275                         size);
1276                 MMSCH_V1_0_INSERT_DIRECT_WT(
1277                         SOC15_REG_OFFSET(VCN, i,
1278                                 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
1279                         lower_32_bits(adev->vcn.inst[i].gpu_addr + offset));
1280                 MMSCH_V1_0_INSERT_DIRECT_WT(
1281                         SOC15_REG_OFFSET(VCN, i,
1282                                 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
1283                         upper_32_bits(adev->vcn.inst[i].gpu_addr + offset));
1284                 MMSCH_V1_0_INSERT_DIRECT_WT(
1285                         SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET1),
1286                         0);
1287                 MMSCH_V1_0_INSERT_DIRECT_WT(
1288                         SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE1),
1289                         AMDGPU_VCN_STACK_SIZE);
1290                 MMSCH_V1_0_INSERT_DIRECT_WT(
1291                         SOC15_REG_OFFSET(VCN, i,
1292                                 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
1293                         lower_32_bits(adev->vcn.inst[i].gpu_addr + offset +
1294                                 AMDGPU_VCN_STACK_SIZE));
1295                 MMSCH_V1_0_INSERT_DIRECT_WT(
1296                         SOC15_REG_OFFSET(VCN, i,
1297                                 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
1298                         upper_32_bits(adev->vcn.inst[i].gpu_addr + offset +
1299                                 AMDGPU_VCN_STACK_SIZE));
1300                 MMSCH_V1_0_INSERT_DIRECT_WT(
1301                         SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET2),
1302                         0);
1303                 MMSCH_V1_0_INSERT_DIRECT_WT(
1304                         SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE2),
1305                         AMDGPU_VCN_CONTEXT_SIZE);
1306
1307                 ring = &adev->vcn.inst[i].ring_enc[0];
1308                 ring->wptr = 0;
1309
1310                 MMSCH_V1_0_INSERT_DIRECT_WT(
1311                         SOC15_REG_OFFSET(VCN, i, mmUVD_RB_BASE_LO),
1312                         lower_32_bits(ring->gpu_addr));
1313                 MMSCH_V1_0_INSERT_DIRECT_WT(
1314                         SOC15_REG_OFFSET(VCN, i, mmUVD_RB_BASE_HI),
1315                         upper_32_bits(ring->gpu_addr));
1316                 MMSCH_V1_0_INSERT_DIRECT_WT(
1317                         SOC15_REG_OFFSET(VCN, i, mmUVD_RB_SIZE),
1318                         ring->ring_size / 4);
1319
1320                 ring = &adev->vcn.inst[i].ring_dec;
1321                 ring->wptr = 0;
1322                 MMSCH_V1_0_INSERT_DIRECT_WT(
1323                         SOC15_REG_OFFSET(VCN, i,
1324                                 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW),
1325                         lower_32_bits(ring->gpu_addr));
1326                 MMSCH_V1_0_INSERT_DIRECT_WT(
1327                         SOC15_REG_OFFSET(VCN, i,
1328                                 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH),
1329                         upper_32_bits(ring->gpu_addr));
1330
1331                 /* force RBC into idle state */
1332                 rb_bufsz = order_base_2(ring->ring_size);
1333                 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1334                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1335                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1336                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1337                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1338                 MMSCH_V1_0_INSERT_DIRECT_WT(
1339                         SOC15_REG_OFFSET(VCN, i, mmUVD_RBC_RB_CNTL), tmp);
1340
1341                 /* add end packet */
1342                 memcpy((void *)init_table, &end, sizeof(struct mmsch_v1_0_cmd_end));
1343                 table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4;
1344                 init_table += sizeof(struct mmsch_v1_0_cmd_end) / 4;
1345
1346                 /* refine header */
1347                 header->eng[i].table_size = table_size;
1348                 header->total_size += table_size;
1349         }
1350
1351         return vcn_v2_5_mmsch_start(adev, &adev->virt.mm_table);
1352 }
1353
1354 static int vcn_v2_5_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
1355 {
1356         uint32_t tmp;
1357
1358         /* Wait for power status to be 1 */
1359         SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,
1360                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1361
1362         /* wait for read ptr to be equal to write ptr */
1363         tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR);
1364         SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);
1365
1366         tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2);
1367         SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF);
1368
1369         tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
1370         SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);
1371
1372         SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,
1373                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1374
1375         /* disable dynamic power gating mode */
1376         WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0,
1377                         ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1378
1379         return 0;
1380 }
1381
1382 static int vcn_v2_5_stop(struct amdgpu_device *adev)
1383 {
1384         uint32_t tmp;
1385         int i, r = 0;
1386
1387         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1388                 if (adev->vcn.harvest_config & (1 << i))
1389                         continue;
1390                 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1391                         r = vcn_v2_5_stop_dpg_mode(adev, i);
1392                         continue;
1393                 }
1394
1395                 /* wait for vcn idle */
1396                 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);
1397                 if (r)
1398                         return r;
1399
1400                 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1401                         UVD_LMI_STATUS__READ_CLEAN_MASK |
1402                         UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1403                         UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1404                 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);
1405                 if (r)
1406                         return r;
1407
1408                 /* block LMI UMC channel */
1409                 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2);
1410                 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
1411                 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp);
1412
1413                 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
1414                         UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1415                 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);
1416                 if (r)
1417                         return r;
1418
1419                 /* block VCPU register access */
1420                 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL),
1421                         UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
1422                         ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
1423
1424                 /* reset VCPU */
1425                 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
1426                         UVD_VCPU_CNTL__BLK_RST_MASK,
1427                         ~UVD_VCPU_CNTL__BLK_RST_MASK);
1428
1429                 /* disable VCPU clock */
1430                 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
1431                         ~(UVD_VCPU_CNTL__CLK_EN_MASK));
1432
1433                 /* clear status */
1434                 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0);
1435
1436                 vcn_v2_5_enable_clock_gating(adev);
1437
1438                 /* enable register anti-hang mechanism */
1439                 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS),
1440                         UVD_POWER_STATUS__UVD_POWER_STATUS_MASK,
1441                         ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1442         }
1443
1444         if (adev->pm.dpm_enabled)
1445                 amdgpu_dpm_enable_uvd(adev, false);
1446
1447         return 0;
1448 }
1449
1450 static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
1451                                 int inst_idx, struct dpg_pause_state *new_state)
1452 {
1453         struct amdgpu_ring *ring;
1454         uint32_t reg_data = 0;
1455         int ret_code = 0;
1456
1457         /* pause/unpause if state is changed */
1458         if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
1459                 DRM_DEBUG("dpg pause state changed %d -> %d",
1460                         adev->vcn.inst[inst_idx].pause_state.fw_based,  new_state->fw_based);
1461                 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) &
1462                         (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1463
1464                 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
1465                         ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1,
1466                                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1467
1468                         if (!ret_code) {
1469                                 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
1470
1471                                 /* pause DPG */
1472                                 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1473                                 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data);
1474
1475                                 /* wait for ACK */
1476                                 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE,
1477                                            UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
1478                                            UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1479
1480                                 /* Stall DPG before WPTR/RPTR reset */
1481                                 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
1482                                            UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
1483                                            ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
1484
1485                                 /* Restore */
1486                                 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET;
1487                                 ring = &adev->vcn.inst[inst_idx].ring_enc[0];
1488                                 ring->wptr = 0;
1489                                 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr);
1490                                 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1491                                 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4);
1492                                 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1493                                 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1494                                 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET;
1495
1496                                 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET;
1497                                 ring = &adev->vcn.inst[inst_idx].ring_enc[1];
1498                                 ring->wptr = 0;
1499                                 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1500                                 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1501                                 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4);
1502                                 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1503                                 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1504                                 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET;
1505
1506                                 /* Unstall DPG */
1507                                 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
1508                                            0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
1509
1510                                 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS,
1511                                            UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1512                         }
1513                 } else {
1514                         reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1515                         WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data);
1516                         SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1,
1517                                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1518                 }
1519                 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
1520         }
1521
1522         return 0;
1523 }
1524
1525 /**
1526  * vcn_v2_5_dec_ring_get_rptr - get read pointer
1527  *
1528  * @ring: amdgpu_ring pointer
1529  *
1530  * Returns the current hardware read pointer
1531  */
1532 static uint64_t vcn_v2_5_dec_ring_get_rptr(struct amdgpu_ring *ring)
1533 {
1534         struct amdgpu_device *adev = ring->adev;
1535
1536         return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR);
1537 }
1538
1539 /**
1540  * vcn_v2_5_dec_ring_get_wptr - get write pointer
1541  *
1542  * @ring: amdgpu_ring pointer
1543  *
1544  * Returns the current hardware write pointer
1545  */
1546 static uint64_t vcn_v2_5_dec_ring_get_wptr(struct amdgpu_ring *ring)
1547 {
1548         struct amdgpu_device *adev = ring->adev;
1549
1550         if (ring->use_doorbell)
1551                 return *ring->wptr_cpu_addr;
1552         else
1553                 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR);
1554 }
1555
1556 /**
1557  * vcn_v2_5_dec_ring_set_wptr - set write pointer
1558  *
1559  * @ring: amdgpu_ring pointer
1560  *
1561  * Commits the write pointer to the hardware
1562  */
1563 static void vcn_v2_5_dec_ring_set_wptr(struct amdgpu_ring *ring)
1564 {
1565         struct amdgpu_device *adev = ring->adev;
1566
1567         if (ring->use_doorbell) {
1568                 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
1569                 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1570         } else {
1571                 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
1572         }
1573 }
1574
1575 static const struct amdgpu_ring_funcs vcn_v2_5_dec_ring_vm_funcs = {
1576         .type = AMDGPU_RING_TYPE_VCN_DEC,
1577         .align_mask = 0xf,
1578         .secure_submission_supported = true,
1579         .get_rptr = vcn_v2_5_dec_ring_get_rptr,
1580         .get_wptr = vcn_v2_5_dec_ring_get_wptr,
1581         .set_wptr = vcn_v2_5_dec_ring_set_wptr,
1582         .emit_frame_size =
1583                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
1584                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
1585                 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */
1586                 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */
1587                 6,
1588         .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */
1589         .emit_ib = vcn_v2_0_dec_ring_emit_ib,
1590         .emit_fence = vcn_v2_0_dec_ring_emit_fence,
1591         .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush,
1592         .test_ring = vcn_v2_0_dec_ring_test_ring,
1593         .test_ib = amdgpu_vcn_dec_ring_test_ib,
1594         .insert_nop = vcn_v2_0_dec_ring_insert_nop,
1595         .insert_start = vcn_v2_0_dec_ring_insert_start,
1596         .insert_end = vcn_v2_0_dec_ring_insert_end,
1597         .pad_ib = amdgpu_ring_generic_pad_ib,
1598         .begin_use = amdgpu_vcn_ring_begin_use,
1599         .end_use = amdgpu_vcn_ring_end_use,
1600         .emit_wreg = vcn_v2_0_dec_ring_emit_wreg,
1601         .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait,
1602         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1603 };
1604
1605 /**
1606  * vcn_v2_5_enc_ring_get_rptr - get enc read pointer
1607  *
1608  * @ring: amdgpu_ring pointer
1609  *
1610  * Returns the current hardware enc read pointer
1611  */
1612 static uint64_t vcn_v2_5_enc_ring_get_rptr(struct amdgpu_ring *ring)
1613 {
1614         struct amdgpu_device *adev = ring->adev;
1615
1616         if (ring == &adev->vcn.inst[ring->me].ring_enc[0])
1617                 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR);
1618         else
1619                 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2);
1620 }
1621
1622 /**
1623  * vcn_v2_5_enc_ring_get_wptr - get enc write pointer
1624  *
1625  * @ring: amdgpu_ring pointer
1626  *
1627  * Returns the current hardware enc write pointer
1628  */
1629 static uint64_t vcn_v2_5_enc_ring_get_wptr(struct amdgpu_ring *ring)
1630 {
1631         struct amdgpu_device *adev = ring->adev;
1632
1633         if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
1634                 if (ring->use_doorbell)
1635                         return *ring->wptr_cpu_addr;
1636                 else
1637                         return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR);
1638         } else {
1639                 if (ring->use_doorbell)
1640                         return *ring->wptr_cpu_addr;
1641                 else
1642                         return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2);
1643         }
1644 }
1645
1646 /**
1647  * vcn_v2_5_enc_ring_set_wptr - set enc write pointer
1648  *
1649  * @ring: amdgpu_ring pointer
1650  *
1651  * Commits the enc write pointer to the hardware
1652  */
1653 static void vcn_v2_5_enc_ring_set_wptr(struct amdgpu_ring *ring)
1654 {
1655         struct amdgpu_device *adev = ring->adev;
1656
1657         if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
1658                 if (ring->use_doorbell) {
1659                         *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
1660                         WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1661                 } else {
1662                         WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1663                 }
1664         } else {
1665                 if (ring->use_doorbell) {
1666                         *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
1667                         WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1668                 } else {
1669                         WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1670                 }
1671         }
1672 }
1673
1674 static const struct amdgpu_ring_funcs vcn_v2_5_enc_ring_vm_funcs = {
1675         .type = AMDGPU_RING_TYPE_VCN_ENC,
1676         .align_mask = 0x3f,
1677         .nop = VCN_ENC_CMD_NO_OP,
1678         .get_rptr = vcn_v2_5_enc_ring_get_rptr,
1679         .get_wptr = vcn_v2_5_enc_ring_get_wptr,
1680         .set_wptr = vcn_v2_5_enc_ring_set_wptr,
1681         .emit_frame_size =
1682                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1683                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1684                 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
1685                 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
1686                 1, /* vcn_v2_0_enc_ring_insert_end */
1687         .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
1688         .emit_ib = vcn_v2_0_enc_ring_emit_ib,
1689         .emit_fence = vcn_v2_0_enc_ring_emit_fence,
1690         .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
1691         .test_ring = amdgpu_vcn_enc_ring_test_ring,
1692         .test_ib = amdgpu_vcn_enc_ring_test_ib,
1693         .insert_nop = amdgpu_ring_insert_nop,
1694         .insert_end = vcn_v2_0_enc_ring_insert_end,
1695         .pad_ib = amdgpu_ring_generic_pad_ib,
1696         .begin_use = amdgpu_vcn_ring_begin_use,
1697         .end_use = amdgpu_vcn_ring_end_use,
1698         .emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
1699         .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
1700         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1701 };
1702
1703 static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev)
1704 {
1705         int i;
1706
1707         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1708                 if (adev->vcn.harvest_config & (1 << i))
1709                         continue;
1710                 adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs;
1711                 adev->vcn.inst[i].ring_dec.me = i;
1712                 DRM_INFO("VCN(%d) decode is enabled in VM mode\n", i);
1713         }
1714 }
1715
1716 static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev)
1717 {
1718         int i, j;
1719
1720         for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
1721                 if (adev->vcn.harvest_config & (1 << j))
1722                         continue;
1723                 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
1724                         adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_5_enc_ring_vm_funcs;
1725                         adev->vcn.inst[j].ring_enc[i].me = j;
1726                 }
1727                 DRM_INFO("VCN(%d) encode is enabled in VM mode\n", j);
1728         }
1729 }
1730
1731 static bool vcn_v2_5_is_idle(void *handle)
1732 {
1733         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1734         int i, ret = 1;
1735
1736         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1737                 if (adev->vcn.harvest_config & (1 << i))
1738                         continue;
1739                 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE);
1740         }
1741
1742         return ret;
1743 }
1744
1745 static int vcn_v2_5_wait_for_idle(void *handle)
1746 {
1747         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1748         int i, ret = 0;
1749
1750         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1751                 if (adev->vcn.harvest_config & (1 << i))
1752                         continue;
1753                 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE,
1754                         UVD_STATUS__IDLE);
1755                 if (ret)
1756                         return ret;
1757         }
1758
1759         return ret;
1760 }
1761
1762 static int vcn_v2_5_set_clockgating_state(void *handle,
1763                                           enum amd_clockgating_state state)
1764 {
1765         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1766         bool enable = (state == AMD_CG_STATE_GATE);
1767
1768         if (amdgpu_sriov_vf(adev))
1769                 return 0;
1770
1771         if (enable) {
1772                 if (!vcn_v2_5_is_idle(handle))
1773                         return -EBUSY;
1774                 vcn_v2_5_enable_clock_gating(adev);
1775         } else {
1776                 vcn_v2_5_disable_clock_gating(adev);
1777         }
1778
1779         return 0;
1780 }
1781
1782 static int vcn_v2_5_set_powergating_state(void *handle,
1783                                           enum amd_powergating_state state)
1784 {
1785         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1786         int ret;
1787
1788         if (amdgpu_sriov_vf(adev))
1789                 return 0;
1790
1791         if(state == adev->vcn.cur_state)
1792                 return 0;
1793
1794         if (state == AMD_PG_STATE_GATE)
1795                 ret = vcn_v2_5_stop(adev);
1796         else
1797                 ret = vcn_v2_5_start(adev);
1798
1799         if(!ret)
1800                 adev->vcn.cur_state = state;
1801
1802         return ret;
1803 }
1804
1805 static int vcn_v2_5_set_interrupt_state(struct amdgpu_device *adev,
1806                                         struct amdgpu_irq_src *source,
1807                                         unsigned type,
1808                                         enum amdgpu_interrupt_state state)
1809 {
1810         return 0;
1811 }
1812
1813 static int vcn_v2_6_set_ras_interrupt_state(struct amdgpu_device *adev,
1814                                         struct amdgpu_irq_src *source,
1815                                         unsigned int type,
1816                                         enum amdgpu_interrupt_state state)
1817 {
1818         return 0;
1819 }
1820
1821 static int vcn_v2_5_process_interrupt(struct amdgpu_device *adev,
1822                                       struct amdgpu_irq_src *source,
1823                                       struct amdgpu_iv_entry *entry)
1824 {
1825         uint32_t ip_instance;
1826
1827         switch (entry->client_id) {
1828         case SOC15_IH_CLIENTID_VCN:
1829                 ip_instance = 0;
1830                 break;
1831         case SOC15_IH_CLIENTID_VCN1:
1832                 ip_instance = 1;
1833                 break;
1834         default:
1835                 DRM_ERROR("Unhandled client id: %d\n", entry->client_id);
1836                 return 0;
1837         }
1838
1839         DRM_DEBUG("IH: VCN TRAP\n");
1840
1841         switch (entry->src_id) {
1842         case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT:
1843                 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec);
1844                 break;
1845         case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
1846                 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]);
1847                 break;
1848         case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY:
1849                 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]);
1850                 break;
1851         default:
1852                 DRM_ERROR("Unhandled interrupt: %d %d\n",
1853                           entry->src_id, entry->src_data[0]);
1854                 break;
1855         }
1856
1857         return 0;
1858 }
1859
1860 static const struct amdgpu_irq_src_funcs vcn_v2_5_irq_funcs = {
1861         .set = vcn_v2_5_set_interrupt_state,
1862         .process = vcn_v2_5_process_interrupt,
1863 };
1864
1865 static const struct amdgpu_irq_src_funcs vcn_v2_6_ras_irq_funcs = {
1866         .set = vcn_v2_6_set_ras_interrupt_state,
1867         .process = amdgpu_vcn_process_poison_irq,
1868 };
1869
1870 static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev)
1871 {
1872         int i;
1873
1874         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1875                 if (adev->vcn.harvest_config & (1 << i))
1876                         continue;
1877                 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1;
1878                 adev->vcn.inst[i].irq.funcs = &vcn_v2_5_irq_funcs;
1879
1880                 adev->vcn.inst[i].ras_poison_irq.num_types = adev->vcn.num_enc_rings + 1;
1881                 adev->vcn.inst[i].ras_poison_irq.funcs = &vcn_v2_6_ras_irq_funcs;
1882         }
1883 }
1884
1885 static const struct amd_ip_funcs vcn_v2_5_ip_funcs = {
1886         .name = "vcn_v2_5",
1887         .early_init = vcn_v2_5_early_init,
1888         .late_init = NULL,
1889         .sw_init = vcn_v2_5_sw_init,
1890         .sw_fini = vcn_v2_5_sw_fini,
1891         .hw_init = vcn_v2_5_hw_init,
1892         .hw_fini = vcn_v2_5_hw_fini,
1893         .suspend = vcn_v2_5_suspend,
1894         .resume = vcn_v2_5_resume,
1895         .is_idle = vcn_v2_5_is_idle,
1896         .wait_for_idle = vcn_v2_5_wait_for_idle,
1897         .check_soft_reset = NULL,
1898         .pre_soft_reset = NULL,
1899         .soft_reset = NULL,
1900         .post_soft_reset = NULL,
1901         .set_clockgating_state = vcn_v2_5_set_clockgating_state,
1902         .set_powergating_state = vcn_v2_5_set_powergating_state,
1903 };
1904
1905 static const struct amd_ip_funcs vcn_v2_6_ip_funcs = {
1906         .name = "vcn_v2_6",
1907         .early_init = vcn_v2_5_early_init,
1908         .late_init = NULL,
1909         .sw_init = vcn_v2_5_sw_init,
1910         .sw_fini = vcn_v2_5_sw_fini,
1911         .hw_init = vcn_v2_5_hw_init,
1912         .hw_fini = vcn_v2_5_hw_fini,
1913         .suspend = vcn_v2_5_suspend,
1914         .resume = vcn_v2_5_resume,
1915         .is_idle = vcn_v2_5_is_idle,
1916         .wait_for_idle = vcn_v2_5_wait_for_idle,
1917         .check_soft_reset = NULL,
1918         .pre_soft_reset = NULL,
1919         .soft_reset = NULL,
1920         .post_soft_reset = NULL,
1921         .set_clockgating_state = vcn_v2_5_set_clockgating_state,
1922         .set_powergating_state = vcn_v2_5_set_powergating_state,
1923 };
1924
1925 const struct amdgpu_ip_block_version vcn_v2_5_ip_block =
1926 {
1927                 .type = AMD_IP_BLOCK_TYPE_VCN,
1928                 .major = 2,
1929                 .minor = 5,
1930                 .rev = 0,
1931                 .funcs = &vcn_v2_5_ip_funcs,
1932 };
1933
1934 const struct amdgpu_ip_block_version vcn_v2_6_ip_block =
1935 {
1936                 .type = AMD_IP_BLOCK_TYPE_VCN,
1937                 .major = 2,
1938                 .minor = 6,
1939                 .rev = 0,
1940                 .funcs = &vcn_v2_6_ip_funcs,
1941 };
1942
1943 static uint32_t vcn_v2_6_query_poison_by_instance(struct amdgpu_device *adev,
1944                         uint32_t instance, uint32_t sub_block)
1945 {
1946         uint32_t poison_stat = 0, reg_value = 0;
1947
1948         switch (sub_block) {
1949         case AMDGPU_VCN_V2_6_VCPU_VCODEC:
1950                 reg_value = RREG32_SOC15(VCN, instance, mmUVD_RAS_VCPU_VCODEC_STATUS);
1951                 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_VCPU_VCODEC_STATUS, POISONED_PF);
1952                 break;
1953         default:
1954                 break;
1955         }
1956
1957         if (poison_stat)
1958                 dev_info(adev->dev, "Poison detected in VCN%d, sub_block%d\n",
1959                         instance, sub_block);
1960
1961         return poison_stat;
1962 }
1963
1964 static bool vcn_v2_6_query_poison_status(struct amdgpu_device *adev)
1965 {
1966         uint32_t inst, sub;
1967         uint32_t poison_stat = 0;
1968
1969         for (inst = 0; inst < adev->vcn.num_vcn_inst; inst++)
1970                 for (sub = 0; sub < AMDGPU_VCN_V2_6_MAX_SUB_BLOCK; sub++)
1971                         poison_stat +=
1972                         vcn_v2_6_query_poison_by_instance(adev, inst, sub);
1973
1974         return !!poison_stat;
1975 }
1976
1977 const struct amdgpu_ras_block_hw_ops vcn_v2_6_ras_hw_ops = {
1978         .query_poison_status = vcn_v2_6_query_poison_status,
1979 };
1980
1981 static struct amdgpu_vcn_ras vcn_v2_6_ras = {
1982         .ras_block = {
1983                 .hw_ops = &vcn_v2_6_ras_hw_ops,
1984                 .ras_late_init = amdgpu_vcn_ras_late_init,
1985         },
1986 };
1987
1988 static void vcn_v2_5_set_ras_funcs(struct amdgpu_device *adev)
1989 {
1990         switch (adev->ip_versions[VCN_HWIP][0]) {
1991         case IP_VERSION(2, 6, 0):
1992                 adev->vcn.ras = &vcn_v2_6_ras;
1993                 break;
1994         default:
1995                 break;
1996         }
1997 }