drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_vcn.h"
  28 #include "soc15.h"
  29 #include "soc15d.h"
  30 #include "soc15_common.h"
  31
  32 #include "vcn/vcn_1_0_offset.h"
  33 #include "vcn/vcn_1_0_sh_mask.h"
  34 #include "hdp/hdp_4_0_offset.h"
  35 #include "mmhub/mmhub_9_1_offset.h"
  36 #include "mmhub/mmhub_9_1_sh_mask.h"
  37
  38 #include "ivsrcid/vcn/irqsrcs_vcn_1_0.h"
  39
  40 #define mmUVD_RBC_XX_IB_REG_CHECK                               0x05ab
  41 #define mmUVD_RBC_XX_IB_REG_CHECK_BASE_IDX      1
  42 #define mmUVD_REG_XX_MASK                                                       0x05ac
  43 #define mmUVD_REG_XX_MASK_BASE_IDX                              1
  44
  45 static int vcn_v1_0_stop(struct amdgpu_device *adev);
  46 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
  47 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev);
  48 static void vcn_v1_0_set_jpeg_ring_funcs(struct amdgpu_device *adev);
  49 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev);
  50 static void vcn_v1_0_jpeg_ring_set_patch_ring(struct amdgpu_ring *ring, uint32_t ptr);
  51
  52 /**
  53  * vcn_v1_0_early_init - set function pointers
  54  *
  55  * @handle: amdgpu_device pointer
  56  *
  57  * Set ring and irq function pointers
  58  */
  59 static int vcn_v1_0_early_init(void *handle)
  60 {
  61         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  62
  63         adev->vcn.num_enc_rings = 2;
  64
  65         vcn_v1_0_set_dec_ring_funcs(adev);
  66         vcn_v1_0_set_enc_ring_funcs(adev);
  67         vcn_v1_0_set_jpeg_ring_funcs(adev);
  68         vcn_v1_0_set_irq_funcs(adev);
  69
  70         return 0;
  71 }
  72
  73 /**
  74  * vcn_v1_0_sw_init - sw init for VCN block
  75  *
  76  * @handle: amdgpu_device pointer
  77  *
  78  * Load firmware and sw initialization
  79  */
  80 static int vcn_v1_0_sw_init(void *handle)
  81 {
  82         struct amdgpu_ring *ring;
  83         int i, r;
  84         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  85
  86         /* VCN DEC TRAP */
  87         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.irq);
  88         if (r)
  89                 return r;
  90
  91         /* VCN ENC TRAP */
  92         for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
  93                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, i + VCN_1_0__SRCID__UVD_ENC_GENERAL_PURPOSE,
  94                                         &adev->vcn.irq);
  95                 if (r)
  96                         return r;
  97         }
  98
  99         /* VCN JPEG TRAP */
 100         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 126, &adev->vcn.irq);
 101         if (r)
 102                 return r;
 103
 104         r = amdgpu_vcn_sw_init(adev);
 105         if (r)
 106                 return r;
 107
 108         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 109                 const struct common_firmware_header *hdr;
 110                 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
 111                 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN;
 112                 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
 113                 adev->firmware.fw_size +=
 114                         ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
 115                 DRM_INFO("PSP loading VCN firmware\n");
 116         }
 117
 118         r = amdgpu_vcn_resume(adev);
 119         if (r)
 120                 return r;
 121
 122         ring = &adev->vcn.ring_dec;
 123         sprintf(ring->name, "vcn_dec");
 124         r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
 125         if (r)
 126                 return r;
 127
 128         for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 129                 ring = &adev->vcn.ring_enc[i];
 130                 sprintf(ring->name, "vcn_enc%d", i);
 131                 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
 132                 if (r)
 133                         return r;
 134         }
 135
 136         ring = &adev->vcn.ring_jpeg;
 137         sprintf(ring->name, "vcn_jpeg");
 138         r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
 139         if (r)
 140                 return r;
 141
 142         return r;
 143 }
 144
 145 /**
 146  * vcn_v1_0_sw_fini - sw fini for VCN block
 147  *
 148  * @handle: amdgpu_device pointer
 149  *
 150  * VCN suspend and free up sw allocation
 151  */
 152 static int vcn_v1_0_sw_fini(void *handle)
 153 {
 154         int r;
 155         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 156
 157         r = amdgpu_vcn_suspend(adev);
 158         if (r)
 159                 return r;
 160
 161         r = amdgpu_vcn_sw_fini(adev);
 162
 163         return r;
 164 }
 165
 166 /**
 167  * vcn_v1_0_hw_init - start and test VCN block
 168  *
 169  * @handle: amdgpu_device pointer
 170  *
 171  * Initialize the hardware, boot up the VCPU and do some testing
 172  */
 173 static int vcn_v1_0_hw_init(void *handle)
 174 {
 175         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 176         struct amdgpu_ring *ring = &adev->vcn.ring_dec;
 177         int i, r;
 178
 179         ring->ready = true;
 180         r = amdgpu_ring_test_ring(ring);
 181         if (r) {
 182                 ring->ready = false;
 183                 goto done;
 184         }
 185
 186         for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 187                 ring = &adev->vcn.ring_enc[i];
 188                 ring->ready = true;
 189                 r = amdgpu_ring_test_ring(ring);
 190                 if (r) {
 191                         ring->ready = false;
 192                         goto done;
 193                 }
 194         }
 195
 196         ring = &adev->vcn.ring_jpeg;
 197         ring->ready = true;
 198         r = amdgpu_ring_test_ring(ring);
 199         if (r) {
 200                 ring->ready = false;
 201                 goto done;
 202         }
 203
 204 done:
 205         if (!r)
 206                 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",
 207                         (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");
 208
 209         return r;
 210 }
 211
 212 /**
 213  * vcn_v1_0_hw_fini - stop the hardware block
 214  *
 215  * @handle: amdgpu_device pointer
 216  *
 217  * Stop the VCN block, mark ring as not ready any more
 218  */
 219 static int vcn_v1_0_hw_fini(void *handle)
 220 {
 221         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 222         struct amdgpu_ring *ring = &adev->vcn.ring_dec;
 223
 224         if (RREG32_SOC15(VCN, 0, mmUVD_STATUS))
 225                 vcn_v1_0_stop(adev);
 226
 227         ring->ready = false;
 228
 229         return 0;
 230 }
 231
 232 /**
 233  * vcn_v1_0_suspend - suspend VCN block
 234  *
 235  * @handle: amdgpu_device pointer
 236  *
 237  * HW fini and suspend VCN block
 238  */
 239 static int vcn_v1_0_suspend(void *handle)
 240 {
 241         int r;
 242         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 243
 244         r = vcn_v1_0_hw_fini(adev);
 245         if (r)
 246                 return r;
 247
 248         r = amdgpu_vcn_suspend(adev);
 249
 250         return r;
 251 }
 252
 253 /**
 254  * vcn_v1_0_resume - resume VCN block
 255  *
 256  * @handle: amdgpu_device pointer
 257  *
 258  * Resume firmware and hw init VCN block
 259  */
 260 static int vcn_v1_0_resume(void *handle)
 261 {
 262         int r;
 263         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 264
 265         r = amdgpu_vcn_resume(adev);
 266         if (r)
 267                 return r;
 268
 269         r = vcn_v1_0_hw_init(adev);
 270
 271         return r;
 272 }
 273
 274 /**
 275  * vcn_v1_0_mc_resume_spg_mode - memory controller programming
 276  *
 277  * @adev: amdgpu_device pointer
 278  *
 279  * Let the VCN memory controller know it's offsets
 280  */
 281 static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev)
 282 {
 283         uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
 284         uint32_t offset;
 285
 286         /* cache window 0: fw */
 287         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 288                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 289                              (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
 290                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 291                              (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
 292                 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
 293                 offset = 0;
 294         } else {
 295                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 296                         lower_32_bits(adev->vcn.gpu_addr));
 297                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 298                         upper_32_bits(adev->vcn.gpu_addr));
 299                 offset = size;
 300                 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
 301                              AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
 302         }
 303
 304         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
 305
 306         /* cache window 1: stack */
 307         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
 308                      lower_32_bits(adev->vcn.gpu_addr + offset));
 309         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
 310                      upper_32_bits(adev->vcn.gpu_addr + offset));
 311         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
 312         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
 313
 314         /* cache window 2: context */
 315         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
 316                      lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
 317         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
 318                      upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
 319         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
 320         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
 321
 322         WREG32_SOC15(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,
 323                         adev->gfx.config.gb_addr_config);
 324         WREG32_SOC15(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG,
 325                         adev->gfx.config.gb_addr_config);
 326         WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
 327                         adev->gfx.config.gb_addr_config);
 328         WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG,
 329                         adev->gfx.config.gb_addr_config);
 330         WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG,
 331                         adev->gfx.config.gb_addr_config);
 332         WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG,
 333                         adev->gfx.config.gb_addr_config);
 334         WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG,
 335                         adev->gfx.config.gb_addr_config);
 336         WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG,
 337                         adev->gfx.config.gb_addr_config);
 338         WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG,
 339                         adev->gfx.config.gb_addr_config);
 340         WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG,
 341                         adev->gfx.config.gb_addr_config);
 342         WREG32_SOC15(UVD, 0, mmUVD_JPEG_ADDR_CONFIG,
 343                         adev->gfx.config.gb_addr_config);
 344         WREG32_SOC15(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG,
 345                         adev->gfx.config.gb_addr_config);
 346 }
 347
 348 static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev)
 349 {
 350         uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
 351         uint32_t offset;
 352
 353         /* cache window 0: fw */
 354         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 355                 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 356                              (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo),
 357                              0xFFFFFFFF, 0);
 358                 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 359                              (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi),
 360                              0xFFFFFFFF, 0);
 361                 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0,
 362                              0xFFFFFFFF, 0);
 363                 offset = 0;
 364         } else {
 365                 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 366                         lower_32_bits(adev->vcn.gpu_addr), 0xFFFFFFFF, 0);
 367                 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 368                         upper_32_bits(adev->vcn.gpu_addr), 0xFFFFFFFF, 0);
 369                 offset = size;
 370                 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
 371                              AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0xFFFFFFFF, 0);
 372         }
 373
 374         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size, 0xFFFFFFFF, 0);
 375
 376         /* cache window 1: stack */
 377         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
 378                      lower_32_bits(adev->vcn.gpu_addr + offset), 0xFFFFFFFF, 0);
 379         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
 380                      upper_32_bits(adev->vcn.gpu_addr + offset), 0xFFFFFFFF, 0);
 381         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0,
 382                              0xFFFFFFFF, 0);
 383         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE,
 384                              0xFFFFFFFF, 0);
 385
 386         /* cache window 2: context */
 387         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
 388                      lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
 389                              0xFFFFFFFF, 0);
 390         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
 391                      upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
 392                              0xFFFFFFFF, 0);
 393         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0, 0xFFFFFFFF, 0);
 394         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE,
 395                              0xFFFFFFFF, 0);
 396
 397         /* VCN global tiling registers */
 398         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,
 399                         adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 400         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG,
 401                         adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 402         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
 403                         adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 404         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG,
 405                 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 406         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG,
 407                 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 408         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG,
 409                 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 410         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG,
 411                 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 412         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG,
 413                 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 414         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG,
 415                 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 416         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG,
 417                 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 418 }
 419
 420 /**
 421  * vcn_v1_0_disable_clock_gating - disable VCN clock gating
 422  *
 423  * @adev: amdgpu_device pointer
 424  * @sw: enable SW clock gating
 425  *
 426  * Disable clock gating for VCN block
 427  */
 428 static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev)
 429 {
 430         uint32_t data;
 431
 432         /* JPEG disable CGC */
 433         data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
 434
 435         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 436                 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 437         else
 438                 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 439
 440         data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 441         data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 442         WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data);
 443
 444         data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
 445         data &= ~(JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK);
 446         WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data);
 447
 448         /* UVD disable CGC */
 449         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
 450         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 451                 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 452         else
 453                 data &= ~ UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 454
 455         data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 456         data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 457         WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
 458
 459         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE);
 460         data &= ~(UVD_CGC_GATE__SYS_MASK
 461                 | UVD_CGC_GATE__UDEC_MASK
 462                 | UVD_CGC_GATE__MPEG2_MASK
 463                 | UVD_CGC_GATE__REGS_MASK
 464                 | UVD_CGC_GATE__RBC_MASK
 465                 | UVD_CGC_GATE__LMI_MC_MASK
 466                 | UVD_CGC_GATE__LMI_UMC_MASK
 467                 | UVD_CGC_GATE__IDCT_MASK
 468                 | UVD_CGC_GATE__MPRD_MASK
 469                 | UVD_CGC_GATE__MPC_MASK
 470                 | UVD_CGC_GATE__LBSI_MASK
 471                 | UVD_CGC_GATE__LRBBM_MASK
 472                 | UVD_CGC_GATE__UDEC_RE_MASK
 473                 | UVD_CGC_GATE__UDEC_CM_MASK
 474                 | UVD_CGC_GATE__UDEC_IT_MASK
 475                 | UVD_CGC_GATE__UDEC_DB_MASK
 476                 | UVD_CGC_GATE__UDEC_MP_MASK
 477                 | UVD_CGC_GATE__WCB_MASK
 478                 | UVD_CGC_GATE__VCPU_MASK
 479                 | UVD_CGC_GATE__SCPU_MASK);
 480         WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data);
 481
 482         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
 483         data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
 484                 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
 485                 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
 486                 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
 487                 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
 488                 | UVD_CGC_CTRL__SYS_MODE_MASK
 489                 | UVD_CGC_CTRL__UDEC_MODE_MASK
 490                 | UVD_CGC_CTRL__MPEG2_MODE_MASK
 491                 | UVD_CGC_CTRL__REGS_MODE_MASK
 492                 | UVD_CGC_CTRL__RBC_MODE_MASK
 493                 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
 494                 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 495                 | UVD_CGC_CTRL__IDCT_MODE_MASK
 496                 | UVD_CGC_CTRL__MPRD_MODE_MASK
 497                 | UVD_CGC_CTRL__MPC_MODE_MASK
 498                 | UVD_CGC_CTRL__LBSI_MODE_MASK
 499                 | UVD_CGC_CTRL__LRBBM_MODE_MASK
 500                 | UVD_CGC_CTRL__WCB_MODE_MASK
 501                 | UVD_CGC_CTRL__VCPU_MODE_MASK
 502                 | UVD_CGC_CTRL__SCPU_MODE_MASK);
 503         WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
 504
 505         /* turn on */
 506         data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE);
 507         data |= (UVD_SUVD_CGC_GATE__SRE_MASK
 508                 | UVD_SUVD_CGC_GATE__SIT_MASK
 509                 | UVD_SUVD_CGC_GATE__SMP_MASK
 510                 | UVD_SUVD_CGC_GATE__SCM_MASK
 511                 | UVD_SUVD_CGC_GATE__SDB_MASK
 512                 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
 513                 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
 514                 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
 515                 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
 516                 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
 517                 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
 518                 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
 519                 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
 520                 | UVD_SUVD_CGC_GATE__SCLR_MASK
 521                 | UVD_SUVD_CGC_GATE__UVD_SC_MASK
 522                 | UVD_SUVD_CGC_GATE__ENT_MASK
 523                 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
 524                 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
 525                 | UVD_SUVD_CGC_GATE__SITE_MASK
 526                 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
 527                 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
 528                 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
 529                 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
 530                 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
 531         WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data);
 532
 533         data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
 534         data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 535                 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 536                 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 537                 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 538                 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 539                 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
 540                 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
 541                 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 542                 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 543                 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
 544         WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
 545 }
 546
 547 /**
 548  * vcn_v1_0_enable_clock_gating - enable VCN clock gating
 549  *
 550  * @adev: amdgpu_device pointer
 551  * @sw: enable SW clock gating
 552  *
 553  * Enable clock gating for VCN block
 554  */
 555 static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev)
 556 {
 557         uint32_t data = 0;
 558
 559         /* enable JPEG CGC */
 560         data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
 561         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 562                 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 563         else
 564                 data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 565         data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 566         data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 567         WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data);
 568
 569         data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
 570         data |= (JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK);
 571         WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data);
 572
 573         /* enable UVD CGC */
 574         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
 575         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 576                 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 577         else
 578                 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 579         data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 580         data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 581         WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
 582
 583         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
 584         data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
 585                 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
 586                 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
 587                 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
 588                 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
 589                 | UVD_CGC_CTRL__SYS_MODE_MASK
 590                 | UVD_CGC_CTRL__UDEC_MODE_MASK
 591                 | UVD_CGC_CTRL__MPEG2_MODE_MASK
 592                 | UVD_CGC_CTRL__REGS_MODE_MASK
 593                 | UVD_CGC_CTRL__RBC_MODE_MASK
 594                 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
 595                 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 596                 | UVD_CGC_CTRL__IDCT_MODE_MASK
 597                 | UVD_CGC_CTRL__MPRD_MODE_MASK
 598                 | UVD_CGC_CTRL__MPC_MODE_MASK
 599                 | UVD_CGC_CTRL__LBSI_MODE_MASK
 600                 | UVD_CGC_CTRL__LRBBM_MODE_MASK
 601                 | UVD_CGC_CTRL__WCB_MODE_MASK
 602                 | UVD_CGC_CTRL__VCPU_MODE_MASK
 603                 | UVD_CGC_CTRL__SCPU_MODE_MASK);
 604         WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
 605
 606         data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
 607         data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 608                 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 609                 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 610                 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 611                 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 612                 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
 613                 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
 614                 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 615                 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 616                 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
 617         WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
 618 }
 619
 620 static void vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel)
 621 {
 622         uint32_t reg_data = 0;
 623
 624         /* disable JPEG CGC */
 625         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 626                 reg_data = 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 627         else
 628                 reg_data = 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 629         reg_data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 630         reg_data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 631         WREG32_SOC15_DPG_MODE(UVD, 0, mmJPEG_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel);
 632
 633         WREG32_SOC15_DPG_MODE(UVD, 0, mmJPEG_CGC_GATE, 0, 0xFFFFFFFF, sram_sel);
 634
 635         /* enable sw clock gating control */
 636         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 637                 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 638         else
 639                 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 640         reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 641         reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 642         reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
 643                  UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
 644                  UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
 645                  UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
 646                  UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
 647                  UVD_CGC_CTRL__SYS_MODE_MASK |
 648                  UVD_CGC_CTRL__UDEC_MODE_MASK |
 649                  UVD_CGC_CTRL__MPEG2_MODE_MASK |
 650                  UVD_CGC_CTRL__REGS_MODE_MASK |
 651                  UVD_CGC_CTRL__RBC_MODE_MASK |
 652                  UVD_CGC_CTRL__LMI_MC_MODE_MASK |
 653                  UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
 654                  UVD_CGC_CTRL__IDCT_MODE_MASK |
 655                  UVD_CGC_CTRL__MPRD_MODE_MASK |
 656                  UVD_CGC_CTRL__MPC_MODE_MASK |
 657                  UVD_CGC_CTRL__LBSI_MODE_MASK |
 658                  UVD_CGC_CTRL__LRBBM_MODE_MASK |
 659                  UVD_CGC_CTRL__WCB_MODE_MASK |
 660                  UVD_CGC_CTRL__VCPU_MODE_MASK |
 661                  UVD_CGC_CTRL__SCPU_MODE_MASK);
 662         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel);
 663
 664         /* turn off clock gating */
 665         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, sram_sel);
 666
 667         /* turn on SUVD clock gating */
 668         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SUVD_CGC_GATE, 1, 0xFFFFFFFF, sram_sel);
 669
 670         /* turn on sw mode in UVD_SUVD_CGC_CTRL */
 671         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SUVD_CGC_CTRL, 0, 0xFFFFFFFF, sram_sel);
 672 }
 673
 674 static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev)
 675 {
 676         uint32_t data = 0;
 677         int ret;
 678
 679         if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
 680                 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 681                         | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
 682                         | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 683                         | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
 684                         | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 685                         | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
 686                         | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
 687                         | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 688                         | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 689                         | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
 690                         | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
 691
 692                 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
 693                 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF, ret);
 694         } else {
 695                 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 696                         | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
 697                         | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 698                         | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
 699                         | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 700                         | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
 701                         | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
 702                         | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 703                         | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 704                         | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
 705                         | 1 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
 706                 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
 707                 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0,  0xFFFFFFFF, ret);
 708         }
 709
 710         /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS , UVDU_PWR_STATUS are 0 (power on) */
 711
 712         data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
 713         data &= ~0x103;
 714         if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
 715                 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | UVD_POWER_STATUS__UVD_PG_EN_MASK;
 716
 717         WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
 718 }
 719
 720 static void vcn_1_0_enable_static_power_gating(struct amdgpu_device *adev)
 721 {
 722         uint32_t data = 0;
 723         int ret;
 724
 725         if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
 726                 /* Before power off, this indicator has to be turned on */
 727                 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
 728                 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
 729                 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
 730                 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
 731
 732
 733                 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 734                         | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
 735                         | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 736                         | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
 737                         | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 738                         | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
 739                         | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
 740                         | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 741                         | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 742                         | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
 743                         | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
 744
 745                 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
 746
 747                 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
 748                         | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT
 749                         | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
 750                         | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT
 751                         | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
 752                         | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT
 753                         | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT
 754                         | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
 755                         | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
 756                         | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT
 757                         | 2 << UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT);
 758                 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF, ret);
 759         }
 760 }
 761
 762 /**
 763  * vcn_v1_0_start - start VCN block
 764  *
 765  * @adev: amdgpu_device pointer
 766  *
 767  * Setup and start the VCN block
 768  */
 769 static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
 770 {
 771         struct amdgpu_ring *ring = &adev->vcn.ring_dec;
 772         uint32_t rb_bufsz, tmp;
 773         uint32_t lmi_swap_cntl;
 774         int i, j, r;
 775
 776         /* disable byte swapping */
 777         lmi_swap_cntl = 0;
 778
 779         vcn_1_0_disable_static_power_gating(adev);
 780
 781         tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
 782         WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
 783
 784         /* disable clock gating */
 785         vcn_v1_0_disable_clock_gating(adev);
 786
 787         /* disable interupt */
 788         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
 789                         ~UVD_MASTINT_EN__VCPU_EN_MASK);
 790
 791         /* initialize VCN memory controller */
 792         tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);
 793         WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp                |
 794                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 795                 UVD_LMI_CTRL__MASK_MC_URGENT_MASK                       |
 796                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK            |
 797                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
 798
 799 #ifdef __BIG_ENDIAN
 800         /* swap (8 in 32) RB and IB */
 801         lmi_swap_cntl = 0xa;
 802 #endif
 803         WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
 804
 805         tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL);
 806         tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
 807         tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
 808         WREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL, tmp);
 809
 810         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0,
 811                 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
 812                 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
 813                 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
 814                 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
 815
 816         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0,
 817                 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
 818                 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
 819                 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
 820                 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
 821
 822         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX,
 823                 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
 824                 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
 825                 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
 826
 827         vcn_v1_0_mc_resume_spg_mode(adev);
 828
 829         WREG32_SOC15(UVD, 0, mmUVD_REG_XX_MASK, 0x10);
 830         WREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK,
 831                 RREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK) | 0x3);
 832
 833         /* enable VCPU clock */
 834         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);
 835
 836         /* boot up the VCPU */
 837         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
 838                         ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 839
 840         /* enable UMC */
 841         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
 842                         ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 843
 844         tmp = RREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET);
 845         tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
 846         tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
 847         WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, tmp);
 848
 849         for (i = 0; i < 10; ++i) {
 850                 uint32_t status;
 851
 852                 for (j = 0; j < 100; ++j) {
 853                         status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
 854                         if (status & UVD_STATUS__IDLE)
 855                                 break;
 856                         mdelay(10);
 857                 }
 858                 r = 0;
 859                 if (status & UVD_STATUS__IDLE)
 860                         break;
 861
 862                 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
 863                 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
 864                                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
 865                                 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 866                 mdelay(10);
 867                 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
 868                                 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 869                 mdelay(10);
 870                 r = -1;
 871         }
 872
 873         if (r) {
 874                 DRM_ERROR("VCN decode not responding, giving up!!!\n");
 875                 return r;
 876         }
 877         /* enable master interrupt */
 878         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
 879                 UVD_MASTINT_EN__VCPU_EN_MASK, ~UVD_MASTINT_EN__VCPU_EN_MASK);
 880
 881         /* enable system interrupt for JRBC, TODO: move to set interrupt*/
 882         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN),
 883                 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK,
 884                 ~UVD_SYS_INT_EN__UVD_JRBC_EN_MASK);
 885
 886         /* clear the busy bit of UVD_STATUS */
 887         tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY;
 888         WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
 889
 890         /* force RBC into idle state */
 891         rb_bufsz = order_base_2(ring->ring_size);
 892         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
 893         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
 894         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
 895         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
 896         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
 897         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
 898
 899         /* set the write pointer delay */
 900         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
 901
 902         /* set the wb address */
 903         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
 904                         (upper_32_bits(ring->gpu_addr) >> 2));
 905
 906         /* programm the RB_BASE for ring buffer */
 907         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
 908                         lower_32_bits(ring->gpu_addr));
 909         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
 910                         upper_32_bits(ring->gpu_addr));
 911
 912         /* Initialize the ring buffer's read and write pointers */
 913         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
 914
 915         WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
 916
 917         ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
 918         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
 919                         lower_32_bits(ring->wptr));
 920
 921         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
 922                         ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
 923
 924         ring = &adev->vcn.ring_enc[0];
 925         WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
 926         WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
 927         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
 928         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
 929         WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
 930
 931         ring = &adev->vcn.ring_enc[1];
 932         WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
 933         WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
 934         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
 935         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
 936         WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
 937
 938         ring = &adev->vcn.ring_jpeg;
 939         WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
 940         WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK |
 941                         UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
 942         WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, lower_32_bits(ring->gpu_addr));
 943         WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, upper_32_bits(ring->gpu_addr));
 944         WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, 0);
 945         WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, 0);
 946         WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
 947
 948         /* initialize wptr */
 949         ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
 950
 951         /* copy patch commands to the jpeg ring */
 952         vcn_v1_0_jpeg_ring_set_patch_ring(ring,
 953                 (ring->wptr + ring->max_dw * amdgpu_sched_hw_submission));
 954
 955         return 0;
 956 }
 957
 958 static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)
 959 {
 960         struct amdgpu_ring *ring = &adev->vcn.ring_dec;
 961         uint32_t rb_bufsz, tmp;
 962         uint32_t lmi_swap_cntl;
 963
 964         /* disable byte swapping */
 965         lmi_swap_cntl = 0;
 966
 967         vcn_1_0_enable_static_power_gating(adev);
 968
 969         /* enable dynamic power gating mode */
 970         tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
 971         tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
 972         tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
 973         WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp);
 974
 975         /* enable clock gating */
 976         vcn_v1_0_clock_gating_dpg_mode(adev, 0);
 977
 978         /* enable VCPU clock */
 979         tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
 980         tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
 981         tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;
 982         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CNTL, tmp, 0xFFFFFFFF, 0);
 983
 984         /* disable interupt */
 985         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN,
 986                         0, UVD_MASTINT_EN__VCPU_EN_MASK, 0);
 987
 988         /* initialize VCN memory controller */
 989         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL,
 990                 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 991                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 992                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 993                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 994                 UVD_LMI_CTRL__REQ_MODE_MASK |
 995                 UVD_LMI_CTRL__CRC_RESET_MASK |
 996                 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
 997                 0x00100000L, 0xFFFFFFFF, 0);
 998
 999 #ifdef __BIG_ENDIAN
1000         /* swap (8 in 32) RB and IB */
1001         lmi_swap_cntl = 0xa;
1002 #endif
1003         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl, 0xFFFFFFFF, 0);
1004
1005         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_CNTL,
1006                 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0xFFFFFFFF, 0);
1007
1008         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXA0,
1009                 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
1010                  (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
1011                  (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1012                  (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0xFFFFFFFF, 0);
1013
1014         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXB0,
1015                 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
1016                  (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
1017                  (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
1018                  (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0xFFFFFFFF, 0);
1019
1020         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUX,
1021                 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
1022                  (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
1023                  (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0xFFFFFFFF, 0);
1024
1025         vcn_v1_0_mc_resume_dpg_mode(adev);
1026
1027         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_REG_XX_MASK, 0x10, 0xFFFFFFFF, 0);
1028         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 0x3, 0xFFFFFFFF, 0);
1029
1030         /* boot up the VCPU */
1031         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0);
1032
1033         /* enable UMC */
1034         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2,
1035                 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT,
1036                 0xFFFFFFFF, 0);
1037
1038         /* enable master interrupt */
1039         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN,
1040                         UVD_MASTINT_EN__VCPU_EN_MASK, UVD_MASTINT_EN__VCPU_EN_MASK, 0);
1041
1042         vcn_v1_0_clock_gating_dpg_mode(adev, 1);
1043         /* setup mmUVD_LMI_CTRL */
1044         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL,
1045                 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
1046                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
1047                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
1048                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
1049                 UVD_LMI_CTRL__REQ_MODE_MASK |
1050                 UVD_LMI_CTRL__CRC_RESET_MASK |
1051                 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
1052                 0x00100000L, 0xFFFFFFFF, 1);
1053
1054         tmp = adev->gfx.config.gb_addr_config;
1055         /* setup VCN global tiling registers */
1056         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1);
1057         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1);
1058
1059         /* enable System Interrupt for JRBC */
1060         WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SYS_INT_EN,
1061                                                                         UVD_SYS_INT_EN__UVD_JRBC_EN_MASK, 0xFFFFFFFF, 1);
1062
1063         /* force RBC into idle state */
1064         rb_bufsz = order_base_2(ring->ring_size);
1065         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1066         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1067         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1068         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1069         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1070         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
1071
1072         /* set the write pointer delay */
1073         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
1074
1075         /* set the wb address */
1076         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
1077                                                                 (upper_32_bits(ring->gpu_addr) >> 2));
1078
1079         /* programm the RB_BASE for ring buffer */
1080         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1081                                                                 lower_32_bits(ring->gpu_addr));
1082         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1083                                                                 upper_32_bits(ring->gpu_addr));
1084
1085         /* Initialize the ring buffer's read and write pointers */
1086         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
1087
1088         WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
1089
1090         ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1091         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1092                                                                 lower_32_bits(ring->wptr));
1093
1094         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
1095                         ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
1096
1097         /* initialize wptr */
1098         ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
1099
1100         /* copy patch commands to the jpeg ring */
1101         vcn_v1_0_jpeg_ring_set_patch_ring(ring,
1102                 (ring->wptr + ring->max_dw * amdgpu_sched_hw_submission));
1103
1104         return 0;
1105 }
1106
1107 static int vcn_v1_0_start(struct amdgpu_device *adev)
1108 {
1109         int r;
1110
1111         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1112                 r = vcn_v1_0_start_dpg_mode(adev);
1113         else
1114                 r = vcn_v1_0_start_spg_mode(adev);
1115         return r;
1116 }
1117
1118 /**
1119  * vcn_v1_0_stop - stop VCN block
1120  *
1121  * @adev: amdgpu_device pointer
1122  *
1123  * stop the VCN block
1124  */
1125 static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev)
1126 {
1127         int ret_code, tmp;
1128
1129         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, ret_code);
1130
1131         tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1132                 UVD_LMI_STATUS__READ_CLEAN_MASK |
1133                 UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1134                 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1135         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp, ret_code);
1136
1137         /* put VCPU into reset */
1138         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1139                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1140                 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1141
1142         tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
1143                 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1144         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp, ret_code);
1145
1146         /* disable VCPU clock */
1147         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
1148                 ~UVD_VCPU_CNTL__CLK_EN_MASK);
1149
1150         /* reset LMI UMC/LMI */
1151         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1152                 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,
1153                 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
1154
1155         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1156                 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,
1157                 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);
1158
1159         WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0);
1160
1161         vcn_v1_0_enable_clock_gating(adev);
1162         vcn_1_0_enable_static_power_gating(adev);
1163         return 0;
1164 }
1165
1166 static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev)
1167 {
1168         int ret_code = 0;
1169
1170         /* Wait for power status to be UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF */
1171         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1172                         UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1173                         UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
1174
1175         if (!ret_code) {
1176                 int tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
1177                 /* wait for read ptr to be equal to write ptr */
1178                 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
1179
1180                 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1181                         UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1182                         UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
1183         }
1184
1185         /* disable dynamic power gating mode */
1186         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
1187                         ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1188
1189         return 0;
1190 }
1191
1192 static int vcn_v1_0_stop(struct amdgpu_device *adev)
1193 {
1194         int r;
1195
1196         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1197                 r = vcn_v1_0_stop_dpg_mode(adev);
1198         else
1199                 r = vcn_v1_0_stop_spg_mode(adev);
1200
1201         return r;
1202 }
1203
1204 static bool vcn_v1_0_is_idle(void *handle)
1205 {
1206         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1207
1208         return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);
1209 }
1210
1211 static int vcn_v1_0_wait_for_idle(void *handle)
1212 {
1213         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1214         int ret = 0;
1215
1216         SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,
1217                 UVD_STATUS__IDLE, ret);
1218
1219         return ret;
1220 }
1221
1222 static int vcn_v1_0_set_clockgating_state(void *handle,
1223                                           enum amd_clockgating_state state)
1224 {
1225         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1226         bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
1227
1228         if (enable) {
1229                 /* wait for STATUS to clear */
1230                 if (vcn_v1_0_is_idle(handle))
1231                         return -EBUSY;
1232                 vcn_v1_0_enable_clock_gating(adev);
1233         } else {
1234                 /* disable HW gating and enable Sw gating */
1235                 vcn_v1_0_disable_clock_gating(adev);
1236         }
1237         return 0;
1238 }
1239
1240 /**
1241  * vcn_v1_0_dec_ring_get_rptr - get read pointer
1242  *
1243  * @ring: amdgpu_ring pointer
1244  *
1245  * Returns the current hardware read pointer
1246  */
1247 static uint64_t vcn_v1_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
1248 {
1249         struct amdgpu_device *adev = ring->adev;
1250
1251         return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1252 }
1253
1254 /**
1255  * vcn_v1_0_dec_ring_get_wptr - get write pointer
1256  *
1257  * @ring: amdgpu_ring pointer
1258  *
1259  * Returns the current hardware write pointer
1260  */
1261 static uint64_t vcn_v1_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
1262 {
1263         struct amdgpu_device *adev = ring->adev;
1264
1265         return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);
1266 }
1267
1268 /**
1269  * vcn_v1_0_dec_ring_set_wptr - set write pointer
1270  *
1271  * @ring: amdgpu_ring pointer
1272  *
1273  * Commits the write pointer to the hardware
1274  */
1275 static void vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
1276 {
1277         struct amdgpu_device *adev = ring->adev;
1278
1279         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1280                 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2,
1281                         lower_32_bits(ring->wptr) | 0x80000000);
1282
1283         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
1284 }
1285
1286 /**
1287  * vcn_v1_0_dec_ring_insert_start - insert a start command
1288  *
1289  * @ring: amdgpu_ring pointer
1290  *
1291  * Write a start command to the ring.
1292  */
1293 static void vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring *ring)
1294 {
1295         struct amdgpu_device *adev = ring->adev;
1296
1297         amdgpu_ring_write(ring,
1298                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1299         amdgpu_ring_write(ring, 0);
1300         amdgpu_ring_write(ring,
1301                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1302         amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1);
1303 }
1304
1305 /**
1306  * vcn_v1_0_dec_ring_insert_end - insert a end command
1307  *
1308  * @ring: amdgpu_ring pointer
1309  *
1310  * Write a end command to the ring.
1311  */
1312 static void vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring *ring)
1313 {
1314         struct amdgpu_device *adev = ring->adev;
1315
1316         amdgpu_ring_write(ring,
1317                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1318         amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1);
1319 }
1320
1321 /**
1322  * vcn_v1_0_dec_ring_emit_fence - emit an fence & trap command
1323  *
1324  * @ring: amdgpu_ring pointer
1325  * @fence: fence to emit
1326  *
1327  * Write a fence and a trap command to the ring.
1328  */
1329 static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1330                                      unsigned flags)
1331 {
1332         struct amdgpu_device *adev = ring->adev;
1333
1334         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1335
1336         amdgpu_ring_write(ring,
1337                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));
1338         amdgpu_ring_write(ring, seq);
1339         amdgpu_ring_write(ring,
1340                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1341         amdgpu_ring_write(ring, addr & 0xffffffff);
1342         amdgpu_ring_write(ring,
1343                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1344         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
1345         amdgpu_ring_write(ring,
1346                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1347         amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1);
1348
1349         amdgpu_ring_write(ring,
1350                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1351         amdgpu_ring_write(ring, 0);
1352         amdgpu_ring_write(ring,
1353                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1354         amdgpu_ring_write(ring, 0);
1355         amdgpu_ring_write(ring,
1356                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1357         amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1);
1358 }
1359
1360 /**
1361  * vcn_v1_0_dec_ring_emit_ib - execute indirect buffer
1362  *
1363  * @ring: amdgpu_ring pointer
1364  * @ib: indirect buffer to execute
1365  *
1366  * Write ring commands to execute the indirect buffer
1367  */
1368 static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
1369                                   struct amdgpu_ib *ib,
1370                                   unsigned vmid, bool ctx_switch)
1371 {
1372         struct amdgpu_device *adev = ring->adev;
1373
1374         amdgpu_ring_write(ring,
1375                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0));
1376         amdgpu_ring_write(ring, vmid);
1377
1378         amdgpu_ring_write(ring,
1379                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));
1380         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1381         amdgpu_ring_write(ring,
1382                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));
1383         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1384         amdgpu_ring_write(ring,
1385                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0));
1386         amdgpu_ring_write(ring, ib->length_dw);
1387 }
1388
1389 static void vcn_v1_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring,
1390                                             uint32_t reg, uint32_t val,
1391                                             uint32_t mask)
1392 {
1393         struct amdgpu_device *adev = ring->adev;
1394
1395         amdgpu_ring_write(ring,
1396                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1397         amdgpu_ring_write(ring, reg << 2);
1398         amdgpu_ring_write(ring,
1399                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1400         amdgpu_ring_write(ring, val);
1401         amdgpu_ring_write(ring,
1402                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0));
1403         amdgpu_ring_write(ring, mask);
1404         amdgpu_ring_write(ring,
1405                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1406         amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1);
1407 }
1408
1409 static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
1410                                             unsigned vmid, uint64_t pd_addr)
1411 {
1412         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1413         uint32_t data0, data1, mask;
1414
1415         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1416
1417         /* wait for register write */
1418         data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
1419         data1 = lower_32_bits(pd_addr);
1420         mask = 0xffffffff;
1421         vcn_v1_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
1422 }
1423
1424 static void vcn_v1_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
1425                                         uint32_t reg, uint32_t val)
1426 {
1427         struct amdgpu_device *adev = ring->adev;
1428
1429         amdgpu_ring_write(ring,
1430                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1431         amdgpu_ring_write(ring, reg << 2);
1432         amdgpu_ring_write(ring,
1433                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1434         amdgpu_ring_write(ring, val);
1435         amdgpu_ring_write(ring,
1436                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1437         amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1);
1438 }
1439
1440 /**
1441  * vcn_v1_0_enc_ring_get_rptr - get enc read pointer
1442  *
1443  * @ring: amdgpu_ring pointer
1444  *
1445  * Returns the current hardware enc read pointer
1446  */
1447 static uint64_t vcn_v1_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
1448 {
1449         struct amdgpu_device *adev = ring->adev;
1450
1451         if (ring == &adev->vcn.ring_enc[0])
1452                 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
1453         else
1454                 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);
1455 }
1456
1457  /**
1458  * vcn_v1_0_enc_ring_get_wptr - get enc write pointer
1459  *
1460  * @ring: amdgpu_ring pointer
1461  *
1462  * Returns the current hardware enc write pointer
1463  */
1464 static uint64_t vcn_v1_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
1465 {
1466         struct amdgpu_device *adev = ring->adev;
1467
1468         if (ring == &adev->vcn.ring_enc[0])
1469                 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1470         else
1471                 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1472 }
1473
1474  /**
1475  * vcn_v1_0_enc_ring_set_wptr - set enc write pointer
1476  *
1477  * @ring: amdgpu_ring pointer
1478  *
1479  * Commits the enc write pointer to the hardware
1480  */
1481 static void vcn_v1_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
1482 {
1483         struct amdgpu_device *adev = ring->adev;
1484
1485         if (ring == &adev->vcn.ring_enc[0])
1486                 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR,
1487                         lower_32_bits(ring->wptr));
1488         else
1489                 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2,
1490                         lower_32_bits(ring->wptr));
1491 }
1492
1493 /**
1494  * vcn_v1_0_enc_ring_emit_fence - emit an enc fence & trap command
1495  *
1496  * @ring: amdgpu_ring pointer
1497  * @fence: fence to emit
1498  *
1499  * Write enc a fence and a trap command to the ring.
1500  */
1501 static void vcn_v1_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1502                         u64 seq, unsigned flags)
1503 {
1504         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1505
1506         amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE);
1507         amdgpu_ring_write(ring, addr);
1508         amdgpu_ring_write(ring, upper_32_bits(addr));
1509         amdgpu_ring_write(ring, seq);
1510         amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP);
1511 }
1512
1513 static void vcn_v1_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1514 {
1515         amdgpu_ring_write(ring, VCN_ENC_CMD_END);
1516 }
1517
1518 /**
1519  * vcn_v1_0_enc_ring_emit_ib - enc execute indirect buffer
1520  *
1521  * @ring: amdgpu_ring pointer
1522  * @ib: indirect buffer to execute
1523  *
1524  * Write enc ring commands to execute the indirect buffer
1525  */
1526 static void vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1527                 struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch)
1528 {
1529         amdgpu_ring_write(ring, VCN_ENC_CMD_IB);
1530         amdgpu_ring_write(ring, vmid);
1531         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1532         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1533         amdgpu_ring_write(ring, ib->length_dw);
1534 }
1535
1536 static void vcn_v1_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring,
1537                                             uint32_t reg, uint32_t val,
1538                                             uint32_t mask)
1539 {
1540         amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
1541         amdgpu_ring_write(ring, reg << 2);
1542         amdgpu_ring_write(ring, mask);
1543         amdgpu_ring_write(ring, val);
1544 }
1545
1546 static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1547                                             unsigned int vmid, uint64_t pd_addr)
1548 {
1549         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1550
1551         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1552
1553         /* wait for reg writes */
1554         vcn_v1_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2,
1555                                         lower_32_bits(pd_addr), 0xffffffff);
1556 }
1557
1558 static void vcn_v1_0_enc_ring_emit_wreg(struct amdgpu_ring *ring,
1559                                         uint32_t reg, uint32_t val)
1560 {
1561         amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
1562         amdgpu_ring_write(ring, reg << 2);
1563         amdgpu_ring_write(ring, val);
1564 }
1565
1566
1567 /**
1568  * vcn_v1_0_jpeg_ring_get_rptr - get read pointer
1569  *
1570  * @ring: amdgpu_ring pointer
1571  *
1572  * Returns the current hardware read pointer
1573  */
1574 static uint64_t vcn_v1_0_jpeg_ring_get_rptr(struct amdgpu_ring *ring)
1575 {
1576         struct amdgpu_device *adev = ring->adev;
1577
1578         return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR);
1579 }
1580
1581 /**
1582  * vcn_v1_0_jpeg_ring_get_wptr - get write pointer
1583  *
1584  * @ring: amdgpu_ring pointer
1585  *
1586  * Returns the current hardware write pointer
1587  */
1588 static uint64_t vcn_v1_0_jpeg_ring_get_wptr(struct amdgpu_ring *ring)
1589 {
1590         struct amdgpu_device *adev = ring->adev;
1591
1592         return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
1593 }
1594
1595 /**
1596  * vcn_v1_0_jpeg_ring_set_wptr - set write pointer
1597  *
1598  * @ring: amdgpu_ring pointer
1599  *
1600  * Commits the write pointer to the hardware
1601  */
1602 static void vcn_v1_0_jpeg_ring_set_wptr(struct amdgpu_ring *ring)
1603 {
1604         struct amdgpu_device *adev = ring->adev;
1605
1606         WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
1607 }
1608
1609 /**
1610  * vcn_v1_0_jpeg_ring_insert_start - insert a start command
1611  *
1612  * @ring: amdgpu_ring pointer
1613  *
1614  * Write a start command to the ring.
1615  */
1616 static void vcn_v1_0_jpeg_ring_insert_start(struct amdgpu_ring *ring)
1617 {
1618         struct amdgpu_device *adev = ring->adev;
1619
1620         amdgpu_ring_write(ring,
1621                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
1622         amdgpu_ring_write(ring, 0x68e04);
1623
1624         amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0));
1625         amdgpu_ring_write(ring, 0x80010000);
1626 }
1627
1628 /**
1629  * vcn_v1_0_jpeg_ring_insert_end - insert a end command
1630  *
1631  * @ring: amdgpu_ring pointer
1632  *
1633  * Write a end command to the ring.
1634  */
1635 static void vcn_v1_0_jpeg_ring_insert_end(struct amdgpu_ring *ring)
1636 {
1637         struct amdgpu_device *adev = ring->adev;
1638
1639         amdgpu_ring_write(ring,
1640                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
1641         amdgpu_ring_write(ring, 0x68e04);
1642
1643         amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0));
1644         amdgpu_ring_write(ring, 0x00010000);
1645 }
1646
1647 /**
1648  * vcn_v1_0_jpeg_ring_emit_fence - emit an fence & trap command
1649  *
1650  * @ring: amdgpu_ring pointer
1651  * @fence: fence to emit
1652  *
1653  * Write a fence and a trap command to the ring.
1654  */
1655 static void vcn_v1_0_jpeg_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1656                                      unsigned flags)
1657 {
1658         struct amdgpu_device *adev = ring->adev;
1659
1660         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1661
1662         amdgpu_ring_write(ring,
1663                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_DATA0), 0, 0, PACKETJ_TYPE0));
1664         amdgpu_ring_write(ring, seq);
1665
1666         amdgpu_ring_write(ring,
1667                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_DATA1), 0, 0, PACKETJ_TYPE0));
1668         amdgpu_ring_write(ring, seq);
1669
1670         amdgpu_ring_write(ring,
1671                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
1672         amdgpu_ring_write(ring, lower_32_bits(addr));
1673
1674         amdgpu_ring_write(ring,
1675                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
1676         amdgpu_ring_write(ring, upper_32_bits(addr));
1677
1678         amdgpu_ring_write(ring,
1679                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_CMD), 0, 0, PACKETJ_TYPE0));
1680         amdgpu_ring_write(ring, 0x8);
1681
1682         amdgpu_ring_write(ring,
1683                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_CMD), 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4));
1684         amdgpu_ring_write(ring, 0);
1685
1686         amdgpu_ring_write(ring,
1687                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
1688         amdgpu_ring_write(ring, 0x01400200);
1689
1690         amdgpu_ring_write(ring,
1691                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
1692         amdgpu_ring_write(ring, seq);
1693
1694         amdgpu_ring_write(ring,
1695                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
1696         amdgpu_ring_write(ring, lower_32_bits(addr));
1697
1698         amdgpu_ring_write(ring,
1699                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
1700         amdgpu_ring_write(ring, upper_32_bits(addr));
1701
1702         amdgpu_ring_write(ring,
1703                 PACKETJ(0, 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE2));
1704         amdgpu_ring_write(ring, 0xffffffff);
1705
1706         amdgpu_ring_write(ring,
1707                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
1708         amdgpu_ring_write(ring, 0x3fbc);
1709
1710         amdgpu_ring_write(ring,
1711                 PACKETJ(0, 0, 0, PACKETJ_TYPE0));
1712         amdgpu_ring_write(ring, 0x1);
1713
1714         /* emit trap */
1715         amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7));
1716         amdgpu_ring_write(ring, 0);
1717 }
1718
1719 /**
1720  * vcn_v1_0_jpeg_ring_emit_ib - execute indirect buffer
1721  *
1722  * @ring: amdgpu_ring pointer
1723  * @ib: indirect buffer to execute
1724  *
1725  * Write ring commands to execute the indirect buffer.
1726  */
1727 static void vcn_v1_0_jpeg_ring_emit_ib(struct amdgpu_ring *ring,
1728                                   struct amdgpu_ib *ib,
1729                                   unsigned vmid, bool ctx_switch)
1730 {
1731         struct amdgpu_device *adev = ring->adev;
1732
1733         amdgpu_ring_write(ring,
1734                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_VMID), 0, 0, PACKETJ_TYPE0));
1735         amdgpu_ring_write(ring, (vmid | (vmid << 4)));
1736
1737         amdgpu_ring_write(ring,
1738                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JPEG_VMID), 0, 0, PACKETJ_TYPE0));
1739         amdgpu_ring_write(ring, (vmid | (vmid << 4)));
1740
1741         amdgpu_ring_write(ring,
1742                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
1743         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1744
1745         amdgpu_ring_write(ring,
1746                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
1747         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1748
1749         amdgpu_ring_write(ring,
1750                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_IB_SIZE), 0, 0, PACKETJ_TYPE0));
1751         amdgpu_ring_write(ring, ib->length_dw);
1752
1753         amdgpu_ring_write(ring,
1754                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
1755         amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr));
1756
1757         amdgpu_ring_write(ring,
1758                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
1759         amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr));
1760
1761         amdgpu_ring_write(ring,
1762                 PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2));
1763         amdgpu_ring_write(ring, 0);
1764
1765         amdgpu_ring_write(ring,
1766                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
1767         amdgpu_ring_write(ring, 0x01400200);
1768
1769         amdgpu_ring_write(ring,
1770                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
1771         amdgpu_ring_write(ring, 0x2);
1772
1773         amdgpu_ring_write(ring,
1774                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_STATUS), 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3));
1775         amdgpu_ring_write(ring, 0x2);
1776 }
1777
1778 static void vcn_v1_0_jpeg_ring_emit_reg_wait(struct amdgpu_ring *ring,
1779                                             uint32_t reg, uint32_t val,
1780                                             uint32_t mask)
1781 {
1782         struct amdgpu_device *adev = ring->adev;
1783         uint32_t reg_offset = (reg << 2);
1784
1785         amdgpu_ring_write(ring,
1786                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
1787         amdgpu_ring_write(ring, 0x01400200);
1788
1789         amdgpu_ring_write(ring,
1790                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
1791         amdgpu_ring_write(ring, val);
1792
1793         amdgpu_ring_write(ring,
1794                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
1795         if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
1796                 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
1797                 amdgpu_ring_write(ring, 0);
1798                 amdgpu_ring_write(ring,
1799                         PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3));
1800         } else {
1801                 amdgpu_ring_write(ring, reg_offset);
1802                 amdgpu_ring_write(ring,
1803                         PACKETJ(0, 0, 0, PACKETJ_TYPE3));
1804         }
1805         amdgpu_ring_write(ring, mask);
1806 }
1807
1808 static void vcn_v1_0_jpeg_ring_emit_vm_flush(struct amdgpu_ring *ring,
1809                 unsigned vmid, uint64_t pd_addr)
1810 {
1811         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1812         uint32_t data0, data1, mask;
1813
1814         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1815
1816         /* wait for register write */
1817         data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
1818         data1 = lower_32_bits(pd_addr);
1819         mask = 0xffffffff;
1820         vcn_v1_0_jpeg_ring_emit_reg_wait(ring, data0, data1, mask);
1821 }
1822
1823 static void vcn_v1_0_jpeg_ring_emit_wreg(struct amdgpu_ring *ring,
1824                                         uint32_t reg, uint32_t val)
1825 {
1826         struct amdgpu_device *adev = ring->adev;
1827         uint32_t reg_offset = (reg << 2);
1828
1829         amdgpu_ring_write(ring,
1830                 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
1831         if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
1832                         ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
1833                 amdgpu_ring_write(ring, 0);
1834                 amdgpu_ring_write(ring,
1835                         PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0));
1836         } else {
1837                 amdgpu_ring_write(ring, reg_offset);
1838                 amdgpu_ring_write(ring,
1839                         PACKETJ(0, 0, 0, PACKETJ_TYPE0));
1840         }
1841         amdgpu_ring_write(ring, val);
1842 }
1843
1844 static void vcn_v1_0_jpeg_ring_nop(struct amdgpu_ring *ring, uint32_t count)
1845 {
1846         int i;
1847
1848         WARN_ON(ring->wptr % 2 || count % 2);
1849
1850         for (i = 0; i < count / 2; i++) {
1851                 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
1852                 amdgpu_ring_write(ring, 0);
1853         }
1854 }
1855
1856 static void vcn_v1_0_jpeg_ring_patch_wreg(struct amdgpu_ring *ring, uint32_t *ptr, uint32_t reg_offset, uint32_t val)
1857 {
1858         struct amdgpu_device *adev = ring->adev;
1859         ring->ring[(*ptr)++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0);
1860         if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
1861                 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
1862                 ring->ring[(*ptr)++] = 0;
1863                 ring->ring[(*ptr)++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0);
1864         } else {
1865                 ring->ring[(*ptr)++] = reg_offset;
1866                 ring->ring[(*ptr)++] = PACKETJ(0, 0, 0, PACKETJ_TYPE0);
1867         }
1868         ring->ring[(*ptr)++] = val;
1869 }
1870
1871 static void vcn_v1_0_jpeg_ring_set_patch_ring(struct amdgpu_ring *ring, uint32_t ptr)
1872 {
1873         struct amdgpu_device *adev = ring->adev;
1874
1875         uint32_t reg, reg_offset, val, mask, i;
1876
1877         // 1st: program mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW
1878         reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW);
1879         reg_offset = (reg << 2);
1880         val = lower_32_bits(ring->gpu_addr);
1881         vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
1882
1883         // 2nd: program mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH
1884         reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH);
1885         reg_offset = (reg << 2);
1886         val = upper_32_bits(ring->gpu_addr);
1887         vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
1888
1889         // 3rd to 5th: issue MEM_READ commands
1890         for (i = 0; i <= 2; i++) {
1891                 ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE2);
1892                 ring->ring[ptr++] = 0;
1893         }
1894
1895         // 6th: program mmUVD_JRBC_RB_CNTL register to enable NO_FETCH and RPTR write ability
1896         reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);
1897         reg_offset = (reg << 2);
1898         val = 0x13;
1899         vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
1900
1901         // 7th: program mmUVD_JRBC_RB_REF_DATA
1902         reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA);
1903         reg_offset = (reg << 2);
1904         val = 0x1;
1905         vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
1906
1907         // 8th: issue conditional register read mmUVD_JRBC_RB_CNTL
1908         reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);
1909         reg_offset = (reg << 2);
1910         val = 0x1;
1911         mask = 0x1;
1912
1913         ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0);
1914         ring->ring[ptr++] = 0x01400200;
1915         ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0);
1916         ring->ring[ptr++] = val;
1917         ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0);
1918         if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) ||
1919                 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
1920                 ring->ring[ptr++] = 0;
1921                 ring->ring[ptr++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3);
1922         } else {
1923                 ring->ring[ptr++] = reg_offset;
1924                 ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE3);
1925         }
1926         ring->ring[ptr++] = mask;
1927
1928         //9th to 21st: insert no-op
1929         for (i = 0; i <= 12; i++) {
1930                 ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);
1931                 ring->ring[ptr++] = 0;
1932         }
1933
1934         //22nd: reset mmUVD_JRBC_RB_RPTR
1935         reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_RPTR);
1936         reg_offset = (reg << 2);
1937         val = 0;
1938         vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
1939
1940         //23rd: program mmUVD_JRBC_RB_CNTL to disable no_fetch
1941         reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);
1942         reg_offset = (reg << 2);
1943         val = 0x12;
1944         vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
1945 }
1946
1947 static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev,
1948                                         struct amdgpu_irq_src *source,
1949                                         unsigned type,
1950                                         enum amdgpu_interrupt_state state)
1951 {
1952         return 0;
1953 }
1954
1955 static int vcn_v1_0_process_interrupt(struct amdgpu_device *adev,
1956                                       struct amdgpu_irq_src *source,
1957                                       struct amdgpu_iv_entry *entry)
1958 {
1959         DRM_DEBUG("IH: VCN TRAP\n");
1960
1961         switch (entry->src_id) {
1962         case 124:
1963                 amdgpu_fence_process(&adev->vcn.ring_dec);
1964                 break;
1965         case 119:
1966                 amdgpu_fence_process(&adev->vcn.ring_enc[0]);
1967                 break;
1968         case 120:
1969                 amdgpu_fence_process(&adev->vcn.ring_enc[1]);
1970                 break;
1971         case 126:
1972                 amdgpu_fence_process(&adev->vcn.ring_jpeg);
1973                 break;
1974         default:
1975                 DRM_ERROR("Unhandled interrupt: %d %d\n",
1976                           entry->src_id, entry->src_data[0]);
1977                 break;
1978         }
1979
1980         return 0;
1981 }
1982
1983 static void vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
1984 {
1985         struct amdgpu_device *adev = ring->adev;
1986         int i;
1987
1988         WARN_ON(ring->wptr % 2 || count % 2);
1989
1990         for (i = 0; i < count / 2; i++) {
1991                 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0));
1992                 amdgpu_ring_write(ring, 0);
1993         }
1994 }
1995
1996 static int vcn_v1_0_set_powergating_state(void *handle,
1997                                           enum amd_powergating_state state)
1998 {
1999         /* This doesn't actually powergate the VCN block.
2000          * That's done in the dpm code via the SMC.  This
2001          * just re-inits the block as necessary.  The actual
2002          * gating still happens in the dpm code.  We should
2003          * revisit this when there is a cleaner line between
2004          * the smc and the hw blocks
2005          */
2006         int ret;
2007         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2008
2009         if(state == adev->vcn.cur_state)
2010                 return 0;
2011
2012         if (state == AMD_PG_STATE_GATE)
2013                 ret = vcn_v1_0_stop(adev);
2014         else
2015                 ret = vcn_v1_0_start(adev);
2016
2017         if(!ret)
2018                 adev->vcn.cur_state = state;
2019         return ret;
2020 }
2021
2022 static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
2023         .name = "vcn_v1_0",
2024         .early_init = vcn_v1_0_early_init,
2025         .late_init = NULL,
2026         .sw_init = vcn_v1_0_sw_init,
2027         .sw_fini = vcn_v1_0_sw_fini,
2028         .hw_init = vcn_v1_0_hw_init,
2029         .hw_fini = vcn_v1_0_hw_fini,
2030         .suspend = vcn_v1_0_suspend,
2031         .resume = vcn_v1_0_resume,
2032         .is_idle = vcn_v1_0_is_idle,
2033         .wait_for_idle = vcn_v1_0_wait_for_idle,
2034         .check_soft_reset = NULL /* vcn_v1_0_check_soft_reset */,
2035         .pre_soft_reset = NULL /* vcn_v1_0_pre_soft_reset */,
2036         .soft_reset = NULL /* vcn_v1_0_soft_reset */,
2037         .post_soft_reset = NULL /* vcn_v1_0_post_soft_reset */,
2038         .set_clockgating_state = vcn_v1_0_set_clockgating_state,
2039         .set_powergating_state = vcn_v1_0_set_powergating_state,
2040 };
2041
2042 static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
2043         .type = AMDGPU_RING_TYPE_VCN_DEC,
2044         .align_mask = 0xf,
2045         .support_64bit_ptrs = false,
2046         .vmhub = AMDGPU_MMHUB,
2047         .get_rptr = vcn_v1_0_dec_ring_get_rptr,
2048         .get_wptr = vcn_v1_0_dec_ring_get_wptr,
2049         .set_wptr = vcn_v1_0_dec_ring_set_wptr,
2050         .emit_frame_size =
2051                 6 + 6 + /* hdp invalidate / flush */
2052                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
2053                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
2054                 8 + /* vcn_v1_0_dec_ring_emit_vm_flush */
2055                 14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */
2056                 6,
2057         .emit_ib_size = 8, /* vcn_v1_0_dec_ring_emit_ib */
2058         .emit_ib = vcn_v1_0_dec_ring_emit_ib,
2059         .emit_fence = vcn_v1_0_dec_ring_emit_fence,
2060         .emit_vm_flush = vcn_v1_0_dec_ring_emit_vm_flush,
2061         .test_ring = amdgpu_vcn_dec_ring_test_ring,
2062         .test_ib = amdgpu_vcn_dec_ring_test_ib,
2063         .insert_nop = vcn_v1_0_dec_ring_insert_nop,
2064         .insert_start = vcn_v1_0_dec_ring_insert_start,
2065         .insert_end = vcn_v1_0_dec_ring_insert_end,
2066         .pad_ib = amdgpu_ring_generic_pad_ib,
2067         .begin_use = amdgpu_vcn_ring_begin_use,
2068         .end_use = amdgpu_vcn_ring_end_use,
2069         .emit_wreg = vcn_v1_0_dec_ring_emit_wreg,
2070         .emit_reg_wait = vcn_v1_0_dec_ring_emit_reg_wait,
2071         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2072 };
2073
2074 static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = {
2075         .type = AMDGPU_RING_TYPE_VCN_ENC,
2076         .align_mask = 0x3f,
2077         .nop = VCN_ENC_CMD_NO_OP,
2078         .support_64bit_ptrs = false,
2079         .vmhub = AMDGPU_MMHUB,
2080         .get_rptr = vcn_v1_0_enc_ring_get_rptr,
2081         .get_wptr = vcn_v1_0_enc_ring_get_wptr,
2082         .set_wptr = vcn_v1_0_enc_ring_set_wptr,
2083         .emit_frame_size =
2084                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2085                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
2086                 4 + /* vcn_v1_0_enc_ring_emit_vm_flush */
2087                 5 + 5 + /* vcn_v1_0_enc_ring_emit_fence x2 vm fence */
2088                 1, /* vcn_v1_0_enc_ring_insert_end */
2089         .emit_ib_size = 5, /* vcn_v1_0_enc_ring_emit_ib */
2090         .emit_ib = vcn_v1_0_enc_ring_emit_ib,
2091         .emit_fence = vcn_v1_0_enc_ring_emit_fence,
2092         .emit_vm_flush = vcn_v1_0_enc_ring_emit_vm_flush,
2093         .test_ring = amdgpu_vcn_enc_ring_test_ring,
2094         .test_ib = amdgpu_vcn_enc_ring_test_ib,
2095         .insert_nop = amdgpu_ring_insert_nop,
2096         .insert_end = vcn_v1_0_enc_ring_insert_end,
2097         .pad_ib = amdgpu_ring_generic_pad_ib,
2098         .begin_use = amdgpu_vcn_ring_begin_use,
2099         .end_use = amdgpu_vcn_ring_end_use,
2100         .emit_wreg = vcn_v1_0_enc_ring_emit_wreg,
2101         .emit_reg_wait = vcn_v1_0_enc_ring_emit_reg_wait,
2102         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2103 };
2104
2105 static const struct amdgpu_ring_funcs vcn_v1_0_jpeg_ring_vm_funcs = {
2106         .type = AMDGPU_RING_TYPE_VCN_JPEG,
2107         .align_mask = 0xf,
2108         .nop = PACKET0(0x81ff, 0),
2109         .support_64bit_ptrs = false,
2110         .vmhub = AMDGPU_MMHUB,
2111         .extra_dw = 64,
2112         .get_rptr = vcn_v1_0_jpeg_ring_get_rptr,
2113         .get_wptr = vcn_v1_0_jpeg_ring_get_wptr,
2114         .set_wptr = vcn_v1_0_jpeg_ring_set_wptr,
2115         .emit_frame_size =
2116                 6 + 6 + /* hdp invalidate / flush */
2117                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
2118                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
2119                 8 + /* vcn_v1_0_jpeg_ring_emit_vm_flush */
2120                 26 + 26 + /* vcn_v1_0_jpeg_ring_emit_fence x2 vm fence */
2121                 6,
2122         .emit_ib_size = 22, /* vcn_v1_0_jpeg_ring_emit_ib */
2123         .emit_ib = vcn_v1_0_jpeg_ring_emit_ib,
2124         .emit_fence = vcn_v1_0_jpeg_ring_emit_fence,
2125         .emit_vm_flush = vcn_v1_0_jpeg_ring_emit_vm_flush,
2126         .test_ring = amdgpu_vcn_jpeg_ring_test_ring,
2127         .test_ib = amdgpu_vcn_jpeg_ring_test_ib,
2128         .insert_nop = vcn_v1_0_jpeg_ring_nop,
2129         .insert_start = vcn_v1_0_jpeg_ring_insert_start,
2130         .insert_end = vcn_v1_0_jpeg_ring_insert_end,
2131         .pad_ib = amdgpu_ring_generic_pad_ib,
2132         .begin_use = amdgpu_vcn_ring_begin_use,
2133         .end_use = amdgpu_vcn_ring_end_use,
2134         .emit_wreg = vcn_v1_0_jpeg_ring_emit_wreg,
2135         .emit_reg_wait = vcn_v1_0_jpeg_ring_emit_reg_wait,
2136         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2137 };
2138
2139 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev)
2140 {
2141         adev->vcn.ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs;
2142         DRM_INFO("VCN decode is enabled in VM mode\n");
2143 }
2144
2145 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev)
2146 {
2147         int i;
2148
2149         for (i = 0; i < adev->vcn.num_enc_rings; ++i)
2150                 adev->vcn.ring_enc[i].funcs = &vcn_v1_0_enc_ring_vm_funcs;
2151
2152         DRM_INFO("VCN encode is enabled in VM mode\n");
2153 }
2154
2155 static void vcn_v1_0_set_jpeg_ring_funcs(struct amdgpu_device *adev)
2156 {
2157         adev->vcn.ring_jpeg.funcs = &vcn_v1_0_jpeg_ring_vm_funcs;
2158         DRM_INFO("VCN jpeg decode is enabled in VM mode\n");
2159 }
2160
2161 static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = {
2162         .set = vcn_v1_0_set_interrupt_state,
2163         .process = vcn_v1_0_process_interrupt,
2164 };
2165
2166 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev)
2167 {
2168         adev->vcn.irq.num_types = adev->vcn.num_enc_rings + 2;
2169         adev->vcn.irq.funcs = &vcn_v1_0_irq_funcs;
2170 }
2171
2172 const struct amdgpu_ip_block_version vcn_v1_0_ip_block =
2173 {
2174                 .type = AMD_IP_BLOCK_TYPE_VCN,
2175                 .major = 1,
2176                 .minor = 0,
2177                 .rev = 0,
2178                 .funcs = &vcn_v1_0_ip_funcs,
2179 };