2 * Copyright 2020 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/delay.h>
25 #include <linux/firmware.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
30 #include "amdgpu_ucode.h"
31 #include "amdgpu_trace.h"
33 #include "gc/gc_11_0_0_offset.h"
34 #include "gc/gc_11_0_0_sh_mask.h"
35 #include "gc/gc_11_0_0_default.h"
36 #include "hdp/hdp_6_0_0_offset.h"
37 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h"
39 #include "soc15_common.h"
41 #include "sdma_v6_0_0_pkt_open.h"
42 #include "nbio_v4_3.h"
43 #include "sdma_common.h"
44 #include "sdma_v6_0.h"
45 #include "v11_structs.h"
47 MODULE_FIRMWARE("amdgpu/sdma_6_0_0.bin");
48 MODULE_FIRMWARE("amdgpu/sdma_6_0_1.bin");
49 MODULE_FIRMWARE("amdgpu/sdma_6_0_2.bin");
50 MODULE_FIRMWARE("amdgpu/sdma_6_0_3.bin");
51 MODULE_FIRMWARE("amdgpu/sdma_6_1_0.bin");
53 #define SDMA1_REG_OFFSET 0x600
54 #define SDMA0_HYP_DEC_REG_START 0x5880
55 #define SDMA0_HYP_DEC_REG_END 0x589a
56 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
58 static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev);
59 static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev);
60 static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev);
61 static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev);
62 static int sdma_v6_0_start(struct amdgpu_device *adev);
64 static u32 sdma_v6_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
68 if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
69 internal_offset <= SDMA0_HYP_DEC_REG_END) {
70 base = adev->reg_offset[GC_HWIP][0][1];
72 internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance;
74 base = adev->reg_offset[GC_HWIP][0][0];
76 internal_offset += SDMA1_REG_OFFSET;
79 return base + internal_offset;
82 static unsigned sdma_v6_0_ring_init_cond_exec(struct amdgpu_ring *ring)
86 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COND_EXE));
87 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
88 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
89 amdgpu_ring_write(ring, 1);
90 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
91 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
96 static void sdma_v6_0_ring_patch_cond_exec(struct amdgpu_ring *ring,
101 BUG_ON(offset > ring->buf_mask);
102 BUG_ON(ring->ring[offset] != 0x55aa55aa);
104 cur = (ring->wptr - 1) & ring->buf_mask;
106 ring->ring[offset] = cur - offset;
108 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
112 * sdma_v6_0_ring_get_rptr - get the current read pointer
114 * @ring: amdgpu ring pointer
116 * Get the current rptr from the hardware.
118 static uint64_t sdma_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
122 /* XXX check if swapping is necessary on BE */
123 rptr = (u64 *)ring->rptr_cpu_addr;
125 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
126 return ((*rptr) >> 2);
130 * sdma_v6_0_ring_get_wptr - get the current write pointer
132 * @ring: amdgpu ring pointer
134 * Get the current wptr from the hardware.
136 static uint64_t sdma_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
140 if (ring->use_doorbell) {
141 /* XXX check if swapping is necessary on BE */
142 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
143 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
150 * sdma_v6_0_ring_set_wptr - commit the write pointer
152 * @ring: amdgpu ring pointer
154 * Write the wptr back to the hardware.
156 static void sdma_v6_0_ring_set_wptr(struct amdgpu_ring *ring)
158 struct amdgpu_device *adev = ring->adev;
159 uint32_t *wptr_saved;
160 uint32_t *is_queue_unmap;
161 uint64_t aggregated_db_index;
162 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_DMA].mqd_size;
164 DRM_DEBUG("Setting write pointer\n");
166 if (ring->is_mes_queue) {
167 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
168 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
170 aggregated_db_index =
171 amdgpu_mes_get_aggregated_doorbell_index(adev,
174 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
176 *wptr_saved = ring->wptr << 2;
177 if (*is_queue_unmap) {
178 WDOORBELL64(aggregated_db_index, ring->wptr << 2);
179 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
180 ring->doorbell_index, ring->wptr << 2);
181 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
183 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
184 ring->doorbell_index, ring->wptr << 2);
185 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
188 WDOORBELL64(aggregated_db_index,
192 if (ring->use_doorbell) {
193 DRM_DEBUG("Using doorbell -- "
194 "wptr_offs == 0x%08x "
195 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
196 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
198 lower_32_bits(ring->wptr << 2),
199 upper_32_bits(ring->wptr << 2));
200 /* XXX check if swapping is necessary on BE */
201 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
203 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
204 ring->doorbell_index, ring->wptr << 2);
205 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
207 DRM_DEBUG("Not using doorbell -- "
208 "regSDMA%i_GFX_RB_WPTR == 0x%08x "
209 "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
211 lower_32_bits(ring->wptr << 2),
213 upper_32_bits(ring->wptr << 2));
214 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev,
215 ring->me, regSDMA0_QUEUE0_RB_WPTR),
216 lower_32_bits(ring->wptr << 2));
217 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev,
218 ring->me, regSDMA0_QUEUE0_RB_WPTR_HI),
219 upper_32_bits(ring->wptr << 2));
224 static void sdma_v6_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
226 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
229 for (i = 0; i < count; i++)
230 if (sdma && sdma->burst_nop && (i == 0))
231 amdgpu_ring_write(ring, ring->funcs->nop |
232 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
234 amdgpu_ring_write(ring, ring->funcs->nop);
238 * sdma_v6_0_ring_emit_ib - Schedule an IB on the DMA engine
240 * @ring: amdgpu ring pointer
241 * @ib: IB object to schedule
243 * @job: job to retrieve vmid from
245 * Schedule an IB in the DMA ring.
247 static void sdma_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
248 struct amdgpu_job *job,
249 struct amdgpu_ib *ib,
252 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
253 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
255 /* An IB packet must end on a 8 DW boundary--the next dword
256 * must be on a 8-dword boundary. Our IB packet below is 6
257 * dwords long, thus add x number of NOPs, such that, in
258 * modular arithmetic,
259 * wptr + 6 + x = 8k, k >= 0, which in C is,
260 * (wptr + 6 + x) % 8 = 0.
261 * The expression below, is a solution of x.
263 sdma_v6_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
265 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_INDIRECT) |
266 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
267 /* base must be 32 byte aligned */
268 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
269 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
270 amdgpu_ring_write(ring, ib->length_dw);
271 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
272 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
276 * sdma_v6_0_ring_emit_mem_sync - flush the IB by graphics cache rinse
278 * @ring: amdgpu ring pointer
280 * flush the IB by graphics cache rinse.
282 static void sdma_v6_0_ring_emit_mem_sync(struct amdgpu_ring *ring)
284 uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
285 SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
288 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
289 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_GCR_REQ));
290 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
291 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
292 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
293 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
294 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
295 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
296 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
301 * sdma_v6_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
303 * @ring: amdgpu ring pointer
305 * Emit an hdp flush packet on the requested DMA ring.
307 static void sdma_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
309 struct amdgpu_device *adev = ring->adev;
310 u32 ref_and_mask = 0;
311 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
313 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
315 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) |
316 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
317 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
318 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
319 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
320 amdgpu_ring_write(ring, ref_and_mask); /* reference */
321 amdgpu_ring_write(ring, ref_and_mask); /* mask */
322 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
323 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
327 * sdma_v6_0_ring_emit_fence - emit a fence on the DMA ring
329 * @ring: amdgpu ring pointer
331 * @seq: fence seq number
332 * @flags: fence flags
334 * Add a DMA fence packet to the ring to write
335 * the fence seq number and DMA trap packet to generate
336 * an interrupt if needed.
338 static void sdma_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
341 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
342 /* write the fence */
343 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) |
344 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
345 /* zero in first two bits */
347 amdgpu_ring_write(ring, lower_32_bits(addr));
348 amdgpu_ring_write(ring, upper_32_bits(addr));
349 amdgpu_ring_write(ring, lower_32_bits(seq));
351 /* optionally write high bits as well */
354 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) |
355 SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
356 /* zero in first two bits */
358 amdgpu_ring_write(ring, lower_32_bits(addr));
359 amdgpu_ring_write(ring, upper_32_bits(addr));
360 amdgpu_ring_write(ring, upper_32_bits(seq));
363 if (flags & AMDGPU_FENCE_FLAG_INT) {
364 uint32_t ctx = ring->is_mes_queue ?
365 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0;
366 /* generate an interrupt */
367 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_TRAP));
368 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx));
373 * sdma_v6_0_gfx_stop - stop the gfx async dma engines
375 * @adev: amdgpu_device pointer
377 * Stop the gfx async dma ring buffers.
379 static void sdma_v6_0_gfx_stop(struct amdgpu_device *adev)
381 u32 rb_cntl, ib_cntl;
384 amdgpu_sdma_unset_buffer_funcs_helper(adev);
386 for (i = 0; i < adev->sdma.num_instances; i++) {
387 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));
388 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 0);
389 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
390 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));
391 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 0);
392 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);
397 * sdma_v6_0_rlc_stop - stop the compute async dma engines
399 * @adev: amdgpu_device pointer
401 * Stop the compute async dma queues.
403 static void sdma_v6_0_rlc_stop(struct amdgpu_device *adev)
409 * sdma_v6_0_ctxempty_int_enable - enable or disable context empty interrupts
411 * @adev: amdgpu_device pointer
412 * @enable: enable/disable context switching due to queue empty conditions
414 * Enable or disable the async dma engines queue empty context switch.
416 static void sdma_v6_0_ctxempty_int_enable(struct amdgpu_device *adev, bool enable)
421 if (!amdgpu_sriov_vf(adev)) {
422 for (i = 0; i < adev->sdma.num_instances; i++) {
423 f32_cntl = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_CNTL));
424 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
425 CTXEMPTY_INT_ENABLE, enable ? 1 : 0);
426 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_CNTL), f32_cntl);
432 * sdma_v6_0_enable - stop the async dma engines
434 * @adev: amdgpu_device pointer
435 * @enable: enable/disable the DMA MEs.
437 * Halt or unhalt the async dma engines.
439 static void sdma_v6_0_enable(struct amdgpu_device *adev, bool enable)
445 sdma_v6_0_gfx_stop(adev);
446 sdma_v6_0_rlc_stop(adev);
449 if (amdgpu_sriov_vf(adev))
452 for (i = 0; i < adev->sdma.num_instances; i++) {
453 f32_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));
454 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
455 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), f32_cntl);
460 * sdma_v6_0_gfx_resume - setup and start the async dma engines
462 * @adev: amdgpu_device pointer
464 * Set up the gfx DMA ring buffers and enable them.
465 * Returns 0 for success, error for failure.
467 static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev)
469 struct amdgpu_ring *ring;
470 u32 rb_cntl, ib_cntl;
478 for (i = 0; i < adev->sdma.num_instances; i++) {
479 ring = &adev->sdma.instance[i].ring;
481 if (!amdgpu_sriov_vf(adev))
482 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
484 /* Set ring buffer size in dwords */
485 rb_bufsz = order_base_2(ring->ring_size / 4);
486 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));
487 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz);
489 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1);
490 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL,
491 RPTR_WRITEBACK_SWAP_ENABLE, 1);
493 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_PRIV, 1);
494 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
496 /* Initialize the ring buffer's read and write pointers */
497 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0);
498 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0);
499 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0);
500 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0);
502 /* setup the wptr shadow polling */
503 wptr_gpu_addr = ring->wptr_gpu_addr;
504 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO),
505 lower_32_bits(wptr_gpu_addr));
506 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI),
507 upper_32_bits(wptr_gpu_addr));
509 /* set the wb address whether it's enabled or not */
510 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_HI),
511 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
512 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_LO),
513 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
515 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
516 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0);
517 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, F32_WPTR_POLL_ENABLE, 1);
519 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8);
520 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40);
524 /* before programing wptr to a less value, need set minor_ptr_update first */
525 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1);
527 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
528 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2);
529 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
532 doorbell = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL));
533 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET));
535 if (ring->use_doorbell) {
536 doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);
537 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_QUEUE0_DOORBELL_OFFSET,
538 OFFSET, ring->doorbell_index);
540 doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 0);
542 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell);
543 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET), doorbell_offset);
546 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
547 ring->doorbell_index,
548 adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances);
550 if (amdgpu_sriov_vf(adev))
551 sdma_v6_0_ring_set_wptr(ring);
553 /* set minor_ptr_update to 0 after wptr programed */
554 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 0);
556 /* Set up RESP_MODE to non-copy addresses */
557 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL));
558 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
559 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
560 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp);
562 /* program default cache read and write policy */
563 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE));
564 /* clean read policy and write policy bits */
566 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
567 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
568 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);
569 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp);
571 if (!amdgpu_sriov_vf(adev)) {
573 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));
574 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
575 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, TH1_RESET, 0);
576 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), temp);
580 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 1);
581 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
583 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));
584 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 1);
586 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_SWAP_ENABLE, 1);
589 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);
591 if (amdgpu_sriov_vf(adev))
592 sdma_v6_0_enable(adev, true);
594 r = amdgpu_ring_test_helper(ring);
598 if (adev->mman.buffer_funcs_ring == ring)
599 amdgpu_ttm_set_buffer_funcs_status(adev, true);
606 * sdma_v6_0_rlc_resume - setup and start the async dma engines
608 * @adev: amdgpu_device pointer
610 * Set up the compute DMA queues and enable them.
611 * Returns 0 for success, error for failure.
613 static int sdma_v6_0_rlc_resume(struct amdgpu_device *adev)
619 * sdma_v6_0_load_microcode - load the sDMA ME ucode
621 * @adev: amdgpu_device pointer
623 * Loads the sDMA0/1 ucode.
624 * Returns 0 for success, -EINVAL if the ucode is not available.
626 static int sdma_v6_0_load_microcode(struct amdgpu_device *adev)
628 const struct sdma_firmware_header_v2_0 *hdr;
629 const __le32 *fw_data;
635 sdma_v6_0_enable(adev, false);
637 if (!adev->sdma.instance[0].fw)
640 /* use broadcast mode to load SDMA microcode by default */
641 use_broadcast = true;
644 dev_info(adev->dev, "Use broadcast method to load SDMA firmware\n");
645 /* load Control Thread microcode */
646 hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data;
647 amdgpu_ucode_print_sdma_hdr(&hdr->header);
648 fw_size = le32_to_cpu(hdr->ctx_jt_offset + hdr->ctx_jt_size) / 4;
650 fw_data = (const __le32 *)
651 (adev->sdma.instance[0].fw->data +
652 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
654 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0);
656 for (j = 0; j < fw_size; j++) {
657 if (amdgpu_emu_mode == 1 && j % 500 == 0)
659 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++));
662 /* load Context Switch microcode */
663 fw_size = le32_to_cpu(hdr->ctl_jt_offset + hdr->ctl_jt_size) / 4;
665 fw_data = (const __le32 *)
666 (adev->sdma.instance[0].fw->data +
667 le32_to_cpu(hdr->ctl_ucode_offset));
669 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0x8000);
671 for (j = 0; j < fw_size; j++) {
672 if (amdgpu_emu_mode == 1 && j % 500 == 0)
674 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++));
677 dev_info(adev->dev, "Use legacy method to load SDMA firmware\n");
678 for (i = 0; i < adev->sdma.num_instances; i++) {
679 /* load Control Thread microcode */
680 hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data;
681 amdgpu_ucode_print_sdma_hdr(&hdr->header);
682 fw_size = le32_to_cpu(hdr->ctx_jt_offset + hdr->ctx_jt_size) / 4;
684 fw_data = (const __le32 *)
685 (adev->sdma.instance[0].fw->data +
686 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
688 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0);
690 for (j = 0; j < fw_size; j++) {
691 if (amdgpu_emu_mode == 1 && j % 500 == 0)
693 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
696 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version);
698 /* load Context Switch microcode */
699 fw_size = le32_to_cpu(hdr->ctl_jt_offset + hdr->ctl_jt_size) / 4;
701 fw_data = (const __le32 *)
702 (adev->sdma.instance[0].fw->data +
703 le32_to_cpu(hdr->ctl_ucode_offset));
705 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0x8000);
707 for (j = 0; j < fw_size; j++) {
708 if (amdgpu_emu_mode == 1 && j % 500 == 0)
710 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
713 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version);
720 static int sdma_v6_0_soft_reset(void *handle)
722 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
726 sdma_v6_0_gfx_stop(adev);
728 for (i = 0; i < adev->sdma.num_instances; i++) {
729 tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE));
730 tmp |= SDMA0_FREEZE__FREEZE_MASK;
731 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE), tmp);
732 tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));
733 tmp |= SDMA0_F32_CNTL__HALT_MASK;
734 tmp |= SDMA0_F32_CNTL__TH1_RESET_MASK;
735 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), tmp);
737 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_PREEMPT), 0);
741 tmp = GRBM_SOFT_RESET__SOFT_RESET_SDMA0_MASK << i;
742 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp);
743 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
747 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, 0);
748 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
753 return sdma_v6_0_start(adev);
756 static bool sdma_v6_0_check_soft_reset(void *handle)
758 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
759 struct amdgpu_ring *ring;
761 long tmo = msecs_to_jiffies(1000);
763 for (i = 0; i < adev->sdma.num_instances; i++) {
764 ring = &adev->sdma.instance[i].ring;
765 r = amdgpu_ring_test_ib(ring, tmo);
774 * sdma_v6_0_start - setup and start the async dma engines
776 * @adev: amdgpu_device pointer
778 * Set up the DMA engines and enable them.
779 * Returns 0 for success, error for failure.
781 static int sdma_v6_0_start(struct amdgpu_device *adev)
785 if (amdgpu_sriov_vf(adev)) {
786 sdma_v6_0_enable(adev, false);
788 /* set RB registers */
789 r = sdma_v6_0_gfx_resume(adev);
793 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
794 r = sdma_v6_0_load_microcode(adev);
798 /* The value of regSDMA_F32_CNTL is invalid the moment after loading fw */
799 if (amdgpu_emu_mode == 1)
804 sdma_v6_0_enable(adev, true);
805 /* enable sdma ring preemption */
806 sdma_v6_0_ctxempty_int_enable(adev, true);
808 /* start the gfx rings and rlc compute queues */
809 r = sdma_v6_0_gfx_resume(adev);
812 r = sdma_v6_0_rlc_resume(adev);
817 static int sdma_v6_0_mqd_init(struct amdgpu_device *adev, void *mqd,
818 struct amdgpu_mqd_prop *prop)
820 struct v11_sdma_mqd *m = mqd;
821 uint64_t wb_gpu_addr;
823 m->sdmax_rlcx_rb_cntl =
824 order_base_2(prop->queue_size / 4) << SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT |
825 1 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
826 4 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT |
827 1 << SDMA0_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT;
829 m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8);
830 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8);
832 wb_gpu_addr = prop->wptr_gpu_addr;
833 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr);
834 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr);
836 wb_gpu_addr = prop->rptr_gpu_addr;
837 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr);
838 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr);
840 m->sdmax_rlcx_ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 0,
841 regSDMA0_QUEUE0_IB_CNTL));
843 m->sdmax_rlcx_doorbell_offset =
844 prop->doorbell_index << SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT;
846 m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);
848 m->sdmax_rlcx_skip_cntl = 0;
849 m->sdmax_rlcx_context_status = 0;
850 m->sdmax_rlcx_doorbell_log = 0;
852 m->sdmax_rlcx_rb_aql_cntl = regSDMA0_QUEUE0_RB_AQL_CNTL_DEFAULT;
853 m->sdmax_rlcx_dummy_reg = regSDMA0_QUEUE0_DUMMY_REG_DEFAULT;
858 static void sdma_v6_0_set_mqd_funcs(struct amdgpu_device *adev)
860 adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v11_sdma_mqd);
861 adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v6_0_mqd_init;
865 * sdma_v6_0_ring_test_ring - simple async dma engine test
867 * @ring: amdgpu_ring structure holding ring information
869 * Test the DMA engine by writing using it to write an
871 * Returns 0 for success, error for failure.
873 static int sdma_v6_0_ring_test_ring(struct amdgpu_ring *ring)
875 struct amdgpu_device *adev = ring->adev;
881 volatile uint32_t *cpu_ptr = NULL;
885 if (ring->is_mes_queue) {
887 offset = amdgpu_mes_ctx_get_offs(ring,
888 AMDGPU_MES_CTX_PADDING_OFFS);
889 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
890 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
893 r = amdgpu_device_wb_get(adev, &index);
895 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
899 gpu_addr = adev->wb.gpu_addr + (index * 4);
900 adev->wb.wb[index] = cpu_to_le32(tmp);
903 r = amdgpu_ring_alloc(ring, 5);
905 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
906 amdgpu_device_wb_free(adev, index);
910 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |
911 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
912 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
913 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
914 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
915 amdgpu_ring_write(ring, 0xDEADBEEF);
916 amdgpu_ring_commit(ring);
918 for (i = 0; i < adev->usec_timeout; i++) {
919 if (ring->is_mes_queue)
920 tmp = le32_to_cpu(*cpu_ptr);
922 tmp = le32_to_cpu(adev->wb.wb[index]);
923 if (tmp == 0xDEADBEEF)
925 if (amdgpu_emu_mode == 1)
931 if (i >= adev->usec_timeout)
934 if (!ring->is_mes_queue)
935 amdgpu_device_wb_free(adev, index);
941 * sdma_v6_0_ring_test_ib - test an IB on the DMA engine
943 * @ring: amdgpu_ring structure holding ring information
944 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
946 * Test a simple IB in the DMA ring.
947 * Returns 0 on success, error on failure.
949 static int sdma_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
951 struct amdgpu_device *adev = ring->adev;
953 struct dma_fence *f = NULL;
958 volatile uint32_t *cpu_ptr = NULL;
961 memset(&ib, 0, sizeof(ib));
963 if (ring->is_mes_queue) {
965 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
966 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
967 ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
969 offset = amdgpu_mes_ctx_get_offs(ring,
970 AMDGPU_MES_CTX_PADDING_OFFS);
971 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
972 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
975 r = amdgpu_device_wb_get(adev, &index);
977 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
981 gpu_addr = adev->wb.gpu_addr + (index * 4);
982 adev->wb.wb[index] = cpu_to_le32(tmp);
984 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
986 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
991 ib.ptr[0] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |
992 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
993 ib.ptr[1] = lower_32_bits(gpu_addr);
994 ib.ptr[2] = upper_32_bits(gpu_addr);
995 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
996 ib.ptr[4] = 0xDEADBEEF;
997 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
998 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
999 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1002 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1006 r = dma_fence_wait_timeout(f, false, timeout);
1008 DRM_ERROR("amdgpu: IB test timed out\n");
1012 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1016 if (ring->is_mes_queue)
1017 tmp = le32_to_cpu(*cpu_ptr);
1019 tmp = le32_to_cpu(adev->wb.wb[index]);
1021 if (tmp == 0xDEADBEEF)
1027 amdgpu_ib_free(adev, &ib, NULL);
1030 if (!ring->is_mes_queue)
1031 amdgpu_device_wb_free(adev, index);
1037 * sdma_v6_0_vm_copy_pte - update PTEs by copying them from the GART
1039 * @ib: indirect buffer to fill with commands
1040 * @pe: addr of the page entry
1041 * @src: src addr to copy from
1042 * @count: number of page entries to update
1044 * Update PTEs by copying them from the GART using sDMA.
1046 static void sdma_v6_0_vm_copy_pte(struct amdgpu_ib *ib,
1047 uint64_t pe, uint64_t src,
1050 unsigned bytes = count * 8;
1052 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) |
1053 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1054 ib->ptr[ib->length_dw++] = bytes - 1;
1055 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1056 ib->ptr[ib->length_dw++] = lower_32_bits(src);
1057 ib->ptr[ib->length_dw++] = upper_32_bits(src);
1058 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1059 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1064 * sdma_v6_0_vm_write_pte - update PTEs by writing them manually
1066 * @ib: indirect buffer to fill with commands
1067 * @pe: addr of the page entry
1068 * @value: dst addr to write into pe
1069 * @count: number of page entries to update
1070 * @incr: increase next addr by incr bytes
1072 * Update PTEs by writing them manually using sDMA.
1074 static void sdma_v6_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1075 uint64_t value, unsigned count,
1078 unsigned ndw = count * 2;
1080 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |
1081 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1082 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1083 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1084 ib->ptr[ib->length_dw++] = ndw - 1;
1085 for (; ndw > 0; ndw -= 2) {
1086 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1087 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1093 * sdma_v6_0_vm_set_pte_pde - update the page tables using sDMA
1095 * @ib: indirect buffer to fill with commands
1096 * @pe: addr of the page entry
1097 * @addr: dst addr to write into pe
1098 * @count: number of page entries to update
1099 * @incr: increase next addr by incr bytes
1100 * @flags: access flags
1102 * Update the page tables using sDMA.
1104 static void sdma_v6_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1106 uint64_t addr, unsigned count,
1107 uint32_t incr, uint64_t flags)
1109 /* for physically contiguous pages (vram) */
1110 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_PTEPDE);
1111 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1112 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1113 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1114 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1115 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1116 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1117 ib->ptr[ib->length_dw++] = incr; /* increment size */
1118 ib->ptr[ib->length_dw++] = 0;
1119 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1123 * sdma_v6_0_ring_pad_ib - pad the IB
1124 * @ib: indirect buffer to fill with padding
1125 * @ring: amdgpu ring pointer
1127 * Pad the IB with NOPs to a boundary multiple of 8.
1129 static void sdma_v6_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1131 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1135 pad_count = (-ib->length_dw) & 0x7;
1136 for (i = 0; i < pad_count; i++)
1137 if (sdma && sdma->burst_nop && (i == 0))
1138 ib->ptr[ib->length_dw++] =
1139 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP) |
1140 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1142 ib->ptr[ib->length_dw++] =
1143 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP);
1147 * sdma_v6_0_ring_emit_pipeline_sync - sync the pipeline
1149 * @ring: amdgpu_ring pointer
1151 * Make sure all previous operations are completed (CIK).
1153 static void sdma_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1155 uint32_t seq = ring->fence_drv.sync_seq;
1156 uint64_t addr = ring->fence_drv.gpu_addr;
1159 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1160 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1161 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1162 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1163 amdgpu_ring_write(ring, addr & 0xfffffffc);
1164 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1165 amdgpu_ring_write(ring, seq); /* reference */
1166 amdgpu_ring_write(ring, 0xffffffff); /* mask */
1167 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1168 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1172 * sdma_v6_0_ring_emit_vm_flush - vm flush using sDMA
1174 * @ring: amdgpu_ring pointer
1175 * @vmid: vmid number to use
1178 * Update the page table base and flush the VM TLB
1181 static void sdma_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1182 unsigned vmid, uint64_t pd_addr)
1184 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];
1185 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0);
1187 /* Update the PD address for this VMID. */
1188 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
1189 (hub->ctx_addr_distance * vmid),
1190 lower_32_bits(pd_addr));
1191 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
1192 (hub->ctx_addr_distance * vmid),
1193 upper_32_bits(pd_addr));
1195 /* Trigger invalidation. */
1196 amdgpu_ring_write(ring,
1197 SDMA_PKT_VM_INVALIDATION_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1198 SDMA_PKT_VM_INVALIDATION_HEADER_SUB_OP(SDMA_SUBOP_VM_INVALIDATION) |
1199 SDMA_PKT_VM_INVALIDATION_HEADER_GFX_ENG_ID(ring->vm_inv_eng) |
1200 SDMA_PKT_VM_INVALIDATION_HEADER_MM_ENG_ID(0x1f));
1201 amdgpu_ring_write(ring, req);
1202 amdgpu_ring_write(ring, 0xFFFFFFFF);
1203 amdgpu_ring_write(ring,
1204 SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_INVALIDATEACK(1 << vmid) |
1205 SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_ADDRESSRANGEHI(0x1F));
1208 static void sdma_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,
1209 uint32_t reg, uint32_t val)
1211 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1212 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1213 amdgpu_ring_write(ring, reg);
1214 amdgpu_ring_write(ring, val);
1217 static void sdma_v6_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1218 uint32_t val, uint32_t mask)
1220 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1221 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1222 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1223 amdgpu_ring_write(ring, reg << 2);
1224 amdgpu_ring_write(ring, 0);
1225 amdgpu_ring_write(ring, val); /* reference */
1226 amdgpu_ring_write(ring, mask); /* mask */
1227 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1228 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1231 static void sdma_v6_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1232 uint32_t reg0, uint32_t reg1,
1233 uint32_t ref, uint32_t mask)
1235 amdgpu_ring_emit_wreg(ring, reg0, ref);
1236 /* wait for a cycle to reset vm_inv_eng*_ack */
1237 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1238 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1241 static struct amdgpu_sdma_ras sdma_v6_0_3_ras = {
1243 .ras_late_init = amdgpu_ras_block_late_init,
1247 static void sdma_v6_0_set_ras_funcs(struct amdgpu_device *adev)
1249 switch (adev->ip_versions[SDMA0_HWIP][0]) {
1250 case IP_VERSION(6, 0, 3):
1251 adev->sdma.ras = &sdma_v6_0_3_ras;
1259 static int sdma_v6_0_early_init(void *handle)
1261 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1263 sdma_v6_0_set_ring_funcs(adev);
1264 sdma_v6_0_set_buffer_funcs(adev);
1265 sdma_v6_0_set_vm_pte_funcs(adev);
1266 sdma_v6_0_set_irq_funcs(adev);
1267 sdma_v6_0_set_mqd_funcs(adev);
1268 sdma_v6_0_set_ras_funcs(adev);
1273 static int sdma_v6_0_sw_init(void *handle)
1275 struct amdgpu_ring *ring;
1277 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1279 /* SDMA trap event */
1280 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX,
1281 GFX_11_0_0__SRCID__SDMA_TRAP,
1282 &adev->sdma.trap_irq);
1286 r = amdgpu_sdma_init_microcode(adev, 0, true);
1288 DRM_ERROR("Failed to load sdma firmware!\n");
1292 for (i = 0; i < adev->sdma.num_instances; i++) {
1293 ring = &adev->sdma.instance[i].ring;
1294 ring->ring_obj = NULL;
1295 ring->use_doorbell = true;
1298 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1299 ring->use_doorbell?"true":"false");
1301 ring->doorbell_index =
1302 (adev->doorbell_index.sdma_engine[i] << 1); // get DWORD offset
1304 ring->vm_hub = AMDGPU_GFXHUB(0);
1305 sprintf(ring->name, "sdma%d", i);
1306 r = amdgpu_ring_init(adev, ring, 1024,
1307 &adev->sdma.trap_irq,
1308 AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1309 AMDGPU_RING_PRIO_DEFAULT, NULL);
1314 if (amdgpu_sdma_ras_sw_init(adev)) {
1315 dev_err(adev->dev, "Failed to initialize sdma ras block!\n");
1322 static int sdma_v6_0_sw_fini(void *handle)
1324 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1327 for (i = 0; i < adev->sdma.num_instances; i++)
1328 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1330 amdgpu_sdma_destroy_inst_ctx(adev, true);
1335 static int sdma_v6_0_hw_init(void *handle)
1337 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1339 return sdma_v6_0_start(adev);
1342 static int sdma_v6_0_hw_fini(void *handle)
1344 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1346 if (amdgpu_sriov_vf(adev)) {
1347 /* disable the scheduler for SDMA */
1348 amdgpu_sdma_unset_buffer_funcs_helper(adev);
1352 sdma_v6_0_ctxempty_int_enable(adev, false);
1353 sdma_v6_0_enable(adev, false);
1358 static int sdma_v6_0_suspend(void *handle)
1360 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1362 return sdma_v6_0_hw_fini(adev);
1365 static int sdma_v6_0_resume(void *handle)
1367 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1369 return sdma_v6_0_hw_init(adev);
1372 static bool sdma_v6_0_is_idle(void *handle)
1374 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1377 for (i = 0; i < adev->sdma.num_instances; i++) {
1378 u32 tmp = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG));
1380 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1387 static int sdma_v6_0_wait_for_idle(void *handle)
1391 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1393 for (i = 0; i < adev->usec_timeout; i++) {
1394 sdma0 = RREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_STATUS_REG));
1395 sdma1 = RREG32(sdma_v6_0_get_reg_offset(adev, 1, regSDMA0_STATUS_REG));
1397 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1404 static int sdma_v6_0_ring_preempt_ib(struct amdgpu_ring *ring)
1407 struct amdgpu_device *adev = ring->adev;
1409 u64 sdma_gfx_preempt;
1411 amdgpu_sdma_get_index_from_ring(ring, &index);
1413 sdma_v6_0_get_reg_offset(adev, index, regSDMA0_QUEUE0_PREEMPT);
1415 /* assert preemption condition */
1416 amdgpu_ring_set_preempt_cond_exec(ring, false);
1418 /* emit the trailing fence */
1419 ring->trail_seq += 1;
1420 amdgpu_ring_alloc(ring, 10);
1421 sdma_v6_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1422 ring->trail_seq, 0);
1423 amdgpu_ring_commit(ring);
1425 /* assert IB preemption */
1426 WREG32(sdma_gfx_preempt, 1);
1428 /* poll the trailing fence */
1429 for (i = 0; i < adev->usec_timeout; i++) {
1430 if (ring->trail_seq ==
1431 le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1436 if (i >= adev->usec_timeout) {
1438 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1441 /* deassert IB preemption */
1442 WREG32(sdma_gfx_preempt, 0);
1444 /* deassert the preemption condition */
1445 amdgpu_ring_set_preempt_cond_exec(ring, true);
1449 static int sdma_v6_0_set_trap_irq_state(struct amdgpu_device *adev,
1450 struct amdgpu_irq_src *source,
1452 enum amdgpu_interrupt_state state)
1456 u32 reg_offset = sdma_v6_0_get_reg_offset(adev, type, regSDMA0_CNTL);
1458 if (!amdgpu_sriov_vf(adev)) {
1459 sdma_cntl = RREG32(reg_offset);
1460 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1461 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1462 WREG32(reg_offset, sdma_cntl);
1468 static int sdma_v6_0_process_trap_irq(struct amdgpu_device *adev,
1469 struct amdgpu_irq_src *source,
1470 struct amdgpu_iv_entry *entry)
1472 int instances, queue;
1473 uint32_t mes_queue_id = entry->src_data[0];
1475 DRM_DEBUG("IH: SDMA trap\n");
1477 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
1478 struct amdgpu_mes_queue *queue;
1480 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
1482 spin_lock(&adev->mes.queue_id_lock);
1483 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
1485 DRM_DEBUG("process smda queue id = %d\n", mes_queue_id);
1486 amdgpu_fence_process(queue->ring);
1488 spin_unlock(&adev->mes.queue_id_lock);
1492 queue = entry->ring_id & 0xf;
1493 instances = (entry->ring_id & 0xf0) >> 4;
1494 if (instances > 1) {
1495 DRM_ERROR("IH: wrong ring_ID detected, as wrong sdma instance\n");
1499 switch (entry->client_id) {
1500 case SOC21_IH_CLIENTID_GFX:
1503 amdgpu_fence_process(&adev->sdma.instance[instances].ring);
1513 static int sdma_v6_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1514 struct amdgpu_irq_src *source,
1515 struct amdgpu_iv_entry *entry)
1520 static int sdma_v6_0_set_clockgating_state(void *handle,
1521 enum amd_clockgating_state state)
1526 static int sdma_v6_0_set_powergating_state(void *handle,
1527 enum amd_powergating_state state)
1532 static void sdma_v6_0_get_clockgating_state(void *handle, u64 *flags)
1536 const struct amd_ip_funcs sdma_v6_0_ip_funcs = {
1537 .name = "sdma_v6_0",
1538 .early_init = sdma_v6_0_early_init,
1540 .sw_init = sdma_v6_0_sw_init,
1541 .sw_fini = sdma_v6_0_sw_fini,
1542 .hw_init = sdma_v6_0_hw_init,
1543 .hw_fini = sdma_v6_0_hw_fini,
1544 .suspend = sdma_v6_0_suspend,
1545 .resume = sdma_v6_0_resume,
1546 .is_idle = sdma_v6_0_is_idle,
1547 .wait_for_idle = sdma_v6_0_wait_for_idle,
1548 .soft_reset = sdma_v6_0_soft_reset,
1549 .check_soft_reset = sdma_v6_0_check_soft_reset,
1550 .set_clockgating_state = sdma_v6_0_set_clockgating_state,
1551 .set_powergating_state = sdma_v6_0_set_powergating_state,
1552 .get_clockgating_state = sdma_v6_0_get_clockgating_state,
1555 static const struct amdgpu_ring_funcs sdma_v6_0_ring_funcs = {
1556 .type = AMDGPU_RING_TYPE_SDMA,
1558 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1559 .support_64bit_ptrs = true,
1560 .secure_submission_supported = true,
1561 .get_rptr = sdma_v6_0_ring_get_rptr,
1562 .get_wptr = sdma_v6_0_ring_get_wptr,
1563 .set_wptr = sdma_v6_0_ring_set_wptr,
1565 5 + /* sdma_v6_0_ring_init_cond_exec */
1566 6 + /* sdma_v6_0_ring_emit_hdp_flush */
1567 6 + /* sdma_v6_0_ring_emit_pipeline_sync */
1568 /* sdma_v6_0_ring_emit_vm_flush */
1569 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1570 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1571 10 + 10 + 10, /* sdma_v6_0_ring_emit_fence x3 for user fence, vm fence */
1572 .emit_ib_size = 5 + 7 + 6, /* sdma_v6_0_ring_emit_ib */
1573 .emit_ib = sdma_v6_0_ring_emit_ib,
1574 .emit_mem_sync = sdma_v6_0_ring_emit_mem_sync,
1575 .emit_fence = sdma_v6_0_ring_emit_fence,
1576 .emit_pipeline_sync = sdma_v6_0_ring_emit_pipeline_sync,
1577 .emit_vm_flush = sdma_v6_0_ring_emit_vm_flush,
1578 .emit_hdp_flush = sdma_v6_0_ring_emit_hdp_flush,
1579 .test_ring = sdma_v6_0_ring_test_ring,
1580 .test_ib = sdma_v6_0_ring_test_ib,
1581 .insert_nop = sdma_v6_0_ring_insert_nop,
1582 .pad_ib = sdma_v6_0_ring_pad_ib,
1583 .emit_wreg = sdma_v6_0_ring_emit_wreg,
1584 .emit_reg_wait = sdma_v6_0_ring_emit_reg_wait,
1585 .emit_reg_write_reg_wait = sdma_v6_0_ring_emit_reg_write_reg_wait,
1586 .init_cond_exec = sdma_v6_0_ring_init_cond_exec,
1587 .patch_cond_exec = sdma_v6_0_ring_patch_cond_exec,
1588 .preempt_ib = sdma_v6_0_ring_preempt_ib,
1591 static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev)
1595 for (i = 0; i < adev->sdma.num_instances; i++) {
1596 adev->sdma.instance[i].ring.funcs = &sdma_v6_0_ring_funcs;
1597 adev->sdma.instance[i].ring.me = i;
1601 static const struct amdgpu_irq_src_funcs sdma_v6_0_trap_irq_funcs = {
1602 .set = sdma_v6_0_set_trap_irq_state,
1603 .process = sdma_v6_0_process_trap_irq,
1606 static const struct amdgpu_irq_src_funcs sdma_v6_0_illegal_inst_irq_funcs = {
1607 .process = sdma_v6_0_process_illegal_inst_irq,
1610 static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1612 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1613 adev->sdma.num_instances;
1614 adev->sdma.trap_irq.funcs = &sdma_v6_0_trap_irq_funcs;
1615 adev->sdma.illegal_inst_irq.funcs = &sdma_v6_0_illegal_inst_irq_funcs;
1619 * sdma_v6_0_emit_copy_buffer - copy buffer using the sDMA engine
1621 * @ib: indirect buffer to fill with commands
1622 * @src_offset: src GPU address
1623 * @dst_offset: dst GPU address
1624 * @byte_count: number of bytes to xfer
1625 * @tmz: if a secure copy should be used
1627 * Copy GPU buffers using the DMA engine.
1628 * Used by the amdgpu ttm implementation to move pages if
1629 * registered as the asic copy callback.
1631 static void sdma_v6_0_emit_copy_buffer(struct amdgpu_ib *ib,
1632 uint64_t src_offset,
1633 uint64_t dst_offset,
1634 uint32_t byte_count,
1637 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) |
1638 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1639 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1640 ib->ptr[ib->length_dw++] = byte_count - 1;
1641 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1642 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1643 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1644 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1645 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1649 * sdma_v6_0_emit_fill_buffer - fill buffer using the sDMA engine
1651 * @ib: indirect buffer to fill
1652 * @src_data: value to write to buffer
1653 * @dst_offset: dst GPU address
1654 * @byte_count: number of bytes to xfer
1656 * Fill GPU buffers using the DMA engine.
1658 static void sdma_v6_0_emit_fill_buffer(struct amdgpu_ib *ib,
1660 uint64_t dst_offset,
1661 uint32_t byte_count)
1663 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_CONST_FILL);
1664 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1665 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1666 ib->ptr[ib->length_dw++] = src_data;
1667 ib->ptr[ib->length_dw++] = byte_count - 1;
1670 static const struct amdgpu_buffer_funcs sdma_v6_0_buffer_funcs = {
1671 .copy_max_bytes = 0x400000,
1673 .emit_copy_buffer = sdma_v6_0_emit_copy_buffer,
1675 .fill_max_bytes = 0x400000,
1677 .emit_fill_buffer = sdma_v6_0_emit_fill_buffer,
1680 static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev)
1682 adev->mman.buffer_funcs = &sdma_v6_0_buffer_funcs;
1683 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1686 static const struct amdgpu_vm_pte_funcs sdma_v6_0_vm_pte_funcs = {
1687 .copy_pte_num_dw = 7,
1688 .copy_pte = sdma_v6_0_vm_copy_pte,
1689 .write_pte = sdma_v6_0_vm_write_pte,
1690 .set_pte_pde = sdma_v6_0_vm_set_pte_pde,
1693 static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1697 adev->vm_manager.vm_pte_funcs = &sdma_v6_0_vm_pte_funcs;
1698 for (i = 0; i < adev->sdma.num_instances; i++) {
1699 adev->vm_manager.vm_pte_scheds[i] =
1700 &adev->sdma.instance[i].ring.sched;
1702 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1705 const struct amdgpu_ip_block_version sdma_v6_0_ip_block = {
1706 .type = AMD_IP_BLOCK_TYPE_SDMA,
1710 .funcs = &sdma_v6_0_ip_funcs,