drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_ucode.h"
  31 #include "amdgpu_trace.h"
  32
  33 #include "gc/gc_10_1_0_offset.h"
  34 #include "gc/gc_10_1_0_sh_mask.h"
  35 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
  36 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
  37
  38 #include "soc15_common.h"
  39 #include "soc15.h"
  40 #include "navi10_sdma_pkt_open.h"
  41 #include "nbio_v2_3.h"
  42 #include "sdma_common.h"
  43 #include "sdma_v5_0.h"
  44
  45 MODULE_FIRMWARE("amdgpu/navi10_sdma.bin");
  46 MODULE_FIRMWARE("amdgpu/navi10_sdma1.bin");
  47
  48 MODULE_FIRMWARE("amdgpu/navi14_sdma.bin");
  49 MODULE_FIRMWARE("amdgpu/navi14_sdma1.bin");
  50
  51 MODULE_FIRMWARE("amdgpu/navi12_sdma.bin");
  52 MODULE_FIRMWARE("amdgpu/navi12_sdma1.bin");
  53
  54 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_sdma.bin");
  55 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_sdma1.bin");
  56
  57 #define SDMA1_REG_OFFSET 0x600
  58 #define SDMA0_HYP_DEC_REG_START 0x5880
  59 #define SDMA0_HYP_DEC_REG_END 0x5893
  60 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
  61
  62 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev);
  63 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev);
  64 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  65 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev);
  66
  67 static const struct soc15_reg_golden golden_settings_sdma_5[] = {
  68         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
  69         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  70         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  71         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  72         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  73         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  74         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  75         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  76         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  77         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  78         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  79         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x00ffffff, 0x000c5c00),
  80         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
  81         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  82         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  83         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  84         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  85         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  86         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  87         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  88         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  89         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  90         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  91         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x00ffffff, 0x000c5c00)
  92 };
  93
  94 static const struct soc15_reg_golden golden_settings_sdma_5_sriov[] = {
  95         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  96         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  97         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  98         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  99         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 115 };
 116
 117 static const struct soc15_reg_golden golden_settings_sdma_nv10[] = {
 118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
 119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
 120 };
 121
 122 static const struct soc15_reg_golden golden_settings_sdma_nv14[] = {
 123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 125 };
 126
 127 static const struct soc15_reg_golden golden_settings_sdma_nv12[] = {
 128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
 130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
 131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
 132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
 133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 134 };
 135
 136 static const struct soc15_reg_golden golden_settings_sdma_cyan_skillfish[] = {
 137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
 138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
 139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
 140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x007fffff, 0x004c5c00),
 151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
 152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
 153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
 154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x007fffff, 0x004c5c00)
 165 };
 166
 167 static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
 168 {
 169         u32 base;
 170
 171         if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
 172             internal_offset <= SDMA0_HYP_DEC_REG_END) {
 173                 base = adev->reg_offset[GC_HWIP][0][1];
 174                 if (instance == 1)
 175                         internal_offset += SDMA1_HYP_DEC_REG_OFFSET;
 176         } else {
 177                 base = adev->reg_offset[GC_HWIP][0][0];
 178                 if (instance == 1)
 179                         internal_offset += SDMA1_REG_OFFSET;
 180         }
 181
 182         return base + internal_offset;
 183 }
 184
 185 static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev)
 186 {
 187         switch (adev->ip_versions[SDMA0_HWIP][0]) {
 188         case IP_VERSION(5, 0, 0):
 189                 soc15_program_register_sequence(adev,
 190                                                 golden_settings_sdma_5,
 191                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
 192                 soc15_program_register_sequence(adev,
 193                                                 golden_settings_sdma_nv10,
 194                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_nv10));
 195                 break;
 196         case IP_VERSION(5, 0, 2):
 197                 soc15_program_register_sequence(adev,
 198                                                 golden_settings_sdma_5,
 199                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
 200                 soc15_program_register_sequence(adev,
 201                                                 golden_settings_sdma_nv14,
 202                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_nv14));
 203                 break;
 204         case IP_VERSION(5, 0, 5):
 205                 if (amdgpu_sriov_vf(adev))
 206                         soc15_program_register_sequence(adev,
 207                                                         golden_settings_sdma_5_sriov,
 208                                                         (const u32)ARRAY_SIZE(golden_settings_sdma_5_sriov));
 209                 else
 210                         soc15_program_register_sequence(adev,
 211                                                         golden_settings_sdma_5,
 212                                                         (const u32)ARRAY_SIZE(golden_settings_sdma_5));
 213                 soc15_program_register_sequence(adev,
 214                                                 golden_settings_sdma_nv12,
 215                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_nv12));
 216                 break;
 217         case IP_VERSION(5, 0, 1):
 218                 soc15_program_register_sequence(adev,
 219                                                 golden_settings_sdma_cyan_skillfish,
 220                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_cyan_skillfish));
 221                 break;
 222         default:
 223                 break;
 224         }
 225 }
 226
 227 /**
 228  * sdma_v5_0_init_microcode - load ucode images from disk
 229  *
 230  * @adev: amdgpu_device pointer
 231  *
 232  * Use the firmware interface to load the ucode images into
 233  * the driver (not loaded into hw).
 234  * Returns 0 on success, error on failure.
 235  */
 236
 237 // emulation only, won't work on real chip
 238 // navi10 real chip need to use PSP to load firmware
 239 static int sdma_v5_0_init_microcode(struct amdgpu_device *adev)
 240 {
 241         int ret, i;
 242
 243         for (i = 0; i < adev->sdma.num_instances; i++) {
 244                 ret = amdgpu_sdma_init_microcode(adev, i, false);
 245                 if (ret)
 246                         return ret;
 247         }
 248
 249         return ret;
 250 }
 251
 252 static unsigned sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring *ring)
 253 {
 254         unsigned ret;
 255
 256         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
 257         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
 258         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
 259         amdgpu_ring_write(ring, 1);
 260         ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
 261         amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
 262
 263         return ret;
 264 }
 265
 266 static void sdma_v5_0_ring_patch_cond_exec(struct amdgpu_ring *ring,
 267                                            unsigned offset)
 268 {
 269         unsigned cur;
 270
 271         BUG_ON(offset > ring->buf_mask);
 272         BUG_ON(ring->ring[offset] != 0x55aa55aa);
 273
 274         cur = (ring->wptr - 1) & ring->buf_mask;
 275         if (cur > offset)
 276                 ring->ring[offset] = cur - offset;
 277         else
 278                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
 279 }
 280
 281 /**
 282  * sdma_v5_0_ring_get_rptr - get the current read pointer
 283  *
 284  * @ring: amdgpu ring pointer
 285  *
 286  * Get the current rptr from the hardware (NAVI10+).
 287  */
 288 static uint64_t sdma_v5_0_ring_get_rptr(struct amdgpu_ring *ring)
 289 {
 290         u64 *rptr;
 291
 292         /* XXX check if swapping is necessary on BE */
 293         rptr = (u64 *)ring->rptr_cpu_addr;
 294
 295         DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
 296         return ((*rptr) >> 2);
 297 }
 298
 299 /**
 300  * sdma_v5_0_ring_get_wptr - get the current write pointer
 301  *
 302  * @ring: amdgpu ring pointer
 303  *
 304  * Get the current wptr from the hardware (NAVI10+).
 305  */
 306 static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring *ring)
 307 {
 308         struct amdgpu_device *adev = ring->adev;
 309         u64 wptr;
 310
 311         if (ring->use_doorbell) {
 312                 /* XXX check if swapping is necessary on BE */
 313                 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
 314                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
 315         } else {
 316                 wptr = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
 317                 wptr = wptr << 32;
 318                 wptr |= RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
 319                 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
 320         }
 321
 322         return wptr >> 2;
 323 }
 324
 325 /**
 326  * sdma_v5_0_ring_set_wptr - commit the write pointer
 327  *
 328  * @ring: amdgpu ring pointer
 329  *
 330  * Write the wptr back to the hardware (NAVI10+).
 331  */
 332 static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring *ring)
 333 {
 334         struct amdgpu_device *adev = ring->adev;
 335         uint32_t *wptr_saved;
 336         uint32_t *is_queue_unmap;
 337         uint64_t aggregated_db_index;
 338         uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_DMA].mqd_size;
 339
 340         DRM_DEBUG("Setting write pointer\n");
 341         if (ring->is_mes_queue) {
 342                 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
 343                 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
 344                                               sizeof(uint32_t));
 345                 aggregated_db_index =
 346                         amdgpu_mes_get_aggregated_doorbell_index(adev,
 347                         AMDGPU_MES_PRIORITY_LEVEL_NORMAL);
 348
 349                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
 350                              ring->wptr << 2);
 351                 *wptr_saved = ring->wptr << 2;
 352                 if (*is_queue_unmap) {
 353                         WDOORBELL64(aggregated_db_index, ring->wptr << 2);
 354                         DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 355                                         ring->doorbell_index, ring->wptr << 2);
 356                         WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 357                 } else {
 358                         DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 359                                         ring->doorbell_index, ring->wptr << 2);
 360                         WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 361
 362                         if (*is_queue_unmap)
 363                                 WDOORBELL64(aggregated_db_index,
 364                                             ring->wptr << 2);
 365                 }
 366         } else {
 367                 if (ring->use_doorbell) {
 368                         DRM_DEBUG("Using doorbell -- "
 369                                   "wptr_offs == 0x%08x "
 370                                   "lower_32_bits(ring->wptr) << 2 == 0x%08x "
 371                                   "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 372                                   ring->wptr_offs,
 373                                   lower_32_bits(ring->wptr << 2),
 374                                   upper_32_bits(ring->wptr << 2));
 375                         /* XXX check if swapping is necessary on BE */
 376                         atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
 377                                      ring->wptr << 2);
 378                         DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 379                                   ring->doorbell_index, ring->wptr << 2);
 380                         WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 381                 } else {
 382                         DRM_DEBUG("Not using doorbell -- "
 383                                   "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 384                                   "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 385                                   ring->me,
 386                                   lower_32_bits(ring->wptr << 2),
 387                                   ring->me,
 388                                   upper_32_bits(ring->wptr << 2));
 389                         WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev,
 390                                              ring->me, mmSDMA0_GFX_RB_WPTR),
 391                                         lower_32_bits(ring->wptr << 2));
 392                         WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev,
 393                                              ring->me, mmSDMA0_GFX_RB_WPTR_HI),
 394                                         upper_32_bits(ring->wptr << 2));
 395                 }
 396         }
 397 }
 398
 399 static void sdma_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 400 {
 401         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 402         int i;
 403
 404         for (i = 0; i < count; i++)
 405                 if (sdma && sdma->burst_nop && (i == 0))
 406                         amdgpu_ring_write(ring, ring->funcs->nop |
 407                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 408                 else
 409                         amdgpu_ring_write(ring, ring->funcs->nop);
 410 }
 411
 412 /**
 413  * sdma_v5_0_ring_emit_ib - Schedule an IB on the DMA engine
 414  *
 415  * @ring: amdgpu ring pointer
 416  * @job: job to retrieve vmid from
 417  * @ib: IB object to schedule
 418  * @flags: unused
 419  *
 420  * Schedule an IB in the DMA ring (NAVI10).
 421  */
 422 static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
 423                                    struct amdgpu_job *job,
 424                                    struct amdgpu_ib *ib,
 425                                    uint32_t flags)
 426 {
 427         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 428         uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
 429
 430         /* An IB packet must end on a 8 DW boundary--the next dword
 431          * must be on a 8-dword boundary. Our IB packet below is 6
 432          * dwords long, thus add x number of NOPs, such that, in
 433          * modular arithmetic,
 434          * wptr + 6 + x = 8k, k >= 0, which in C is,
 435          * (wptr + 6 + x) % 8 = 0.
 436          * The expression below, is a solution of x.
 437          */
 438         sdma_v5_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
 439
 440         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 441                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 442         /* base must be 32 byte aligned */
 443         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 444         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 445         amdgpu_ring_write(ring, ib->length_dw);
 446         amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
 447         amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
 448 }
 449
 450 /**
 451  * sdma_v5_0_ring_emit_mem_sync - flush the IB by graphics cache rinse
 452  *
 453  * @ring: amdgpu ring pointer
 454  *
 455  * flush the IB by graphics cache rinse.
 456  */
 457 static void sdma_v5_0_ring_emit_mem_sync(struct amdgpu_ring *ring)
 458 {
 459         uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
 460                             SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
 461                             SDMA_GCR_GLI_INV(1);
 462
 463         /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
 464         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
 465         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
 466         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
 467                           SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
 468         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
 469                           SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
 470         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
 471                           SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
 472 }
 473
 474 /**
 475  * sdma_v5_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 476  *
 477  * @ring: amdgpu ring pointer
 478  *
 479  * Emit an hdp flush packet on the requested DMA ring.
 480  */
 481 static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 482 {
 483         struct amdgpu_device *adev = ring->adev;
 484         u32 ref_and_mask = 0;
 485         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
 486
 487         if (ring->me == 0)
 488                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
 489         else
 490                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
 491
 492         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 493                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 494                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 495         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
 496         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
 497         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 498         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 499         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 500                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 501 }
 502
 503 /**
 504  * sdma_v5_0_ring_emit_fence - emit a fence on the DMA ring
 505  *
 506  * @ring: amdgpu ring pointer
 507  * @addr: address
 508  * @seq: sequence number
 509  * @flags: fence related flags
 510  *
 511  * Add a DMA fence packet to the ring to write
 512  * the fence seq number and DMA trap packet to generate
 513  * an interrupt if needed (NAVI10).
 514  */
 515 static void sdma_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 516                                       unsigned flags)
 517 {
 518         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 519         /* write the fence */
 520         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 521                           SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
 522         /* zero in first two bits */
 523         BUG_ON(addr & 0x3);
 524         amdgpu_ring_write(ring, lower_32_bits(addr));
 525         amdgpu_ring_write(ring, upper_32_bits(addr));
 526         amdgpu_ring_write(ring, lower_32_bits(seq));
 527
 528         /* optionally write high bits as well */
 529         if (write64bit) {
 530                 addr += 4;
 531                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 532                                   SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
 533                 /* zero in first two bits */
 534                 BUG_ON(addr & 0x3);
 535                 amdgpu_ring_write(ring, lower_32_bits(addr));
 536                 amdgpu_ring_write(ring, upper_32_bits(addr));
 537                 amdgpu_ring_write(ring, upper_32_bits(seq));
 538         }
 539
 540         if (flags & AMDGPU_FENCE_FLAG_INT) {
 541                 uint32_t ctx = ring->is_mes_queue ?
 542                         (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0;
 543                 /* generate an interrupt */
 544                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 545                 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx));
 546         }
 547 }
 548
 549
 550 /**
 551  * sdma_v5_0_gfx_stop - stop the gfx async dma engines
 552  *
 553  * @adev: amdgpu_device pointer
 554  *
 555  * Stop the gfx async dma ring buffers (NAVI10).
 556  */
 557 static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev)
 558 {
 559         u32 rb_cntl, ib_cntl;
 560         int i;
 561
 562         amdgpu_sdma_unset_buffer_funcs_helper(adev);
 563
 564         for (i = 0; i < adev->sdma.num_instances; i++) {
 565                 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 566                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 567                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 568                 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 569                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 570                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 571         }
 572 }
 573
 574 /**
 575  * sdma_v5_0_rlc_stop - stop the compute async dma engines
 576  *
 577  * @adev: amdgpu_device pointer
 578  *
 579  * Stop the compute async dma queues (NAVI10).
 580  */
 581 static void sdma_v5_0_rlc_stop(struct amdgpu_device *adev)
 582 {
 583         /* XXX todo */
 584 }
 585
 586 /**
 587  * sdma_v5_0_ctx_switch_enable - stop the async dma engines context switch
 588  *
 589  * @adev: amdgpu_device pointer
 590  * @enable: enable/disable the DMA MEs context switch.
 591  *
 592  * Halt or unhalt the async dma engines context switch (NAVI10).
 593  */
 594 static void sdma_v5_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 595 {
 596         u32 f32_cntl = 0, phase_quantum = 0;
 597         int i;
 598
 599         if (amdgpu_sdma_phase_quantum) {
 600                 unsigned value = amdgpu_sdma_phase_quantum;
 601                 unsigned unit = 0;
 602
 603                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 604                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 605                         value = (value + 1) >> 1;
 606                         unit++;
 607                 }
 608                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 609                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 610                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 611                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 612                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 613                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 614                         WARN_ONCE(1,
 615                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 616                                   value << unit);
 617                 }
 618                 phase_quantum =
 619                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 620                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 621         }
 622
 623         for (i = 0; i < adev->sdma.num_instances; i++) {
 624                 if (!amdgpu_sriov_vf(adev)) {
 625                         f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
 626                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 627                                                  AUTO_CTXSW_ENABLE, enable ? 1 : 0);
 628                 }
 629
 630                 if (enable && amdgpu_sdma_phase_quantum) {
 631                         WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
 632                                phase_quantum);
 633                         WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
 634                                phase_quantum);
 635                         WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
 636                                phase_quantum);
 637                 }
 638                 if (!amdgpu_sriov_vf(adev))
 639                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
 640         }
 641
 642 }
 643
 644 /**
 645  * sdma_v5_0_enable - stop the async dma engines
 646  *
 647  * @adev: amdgpu_device pointer
 648  * @enable: enable/disable the DMA MEs.
 649  *
 650  * Halt or unhalt the async dma engines (NAVI10).
 651  */
 652 static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable)
 653 {
 654         u32 f32_cntl;
 655         int i;
 656
 657         if (!enable) {
 658                 sdma_v5_0_gfx_stop(adev);
 659                 sdma_v5_0_rlc_stop(adev);
 660         }
 661
 662         if (amdgpu_sriov_vf(adev))
 663                 return;
 664
 665         for (i = 0; i < adev->sdma.num_instances; i++) {
 666                 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 667                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
 668                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
 669         }
 670 }
 671
 672 /**
 673  * sdma_v5_0_gfx_resume - setup and start the async dma engines
 674  *
 675  * @adev: amdgpu_device pointer
 676  *
 677  * Set up the gfx DMA ring buffers and enable them (NAVI10).
 678  * Returns 0 for success, error for failure.
 679  */
 680 static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
 681 {
 682         struct amdgpu_ring *ring;
 683         u32 rb_cntl, ib_cntl;
 684         u32 rb_bufsz;
 685         u32 doorbell;
 686         u32 doorbell_offset;
 687         u32 temp;
 688         u32 wptr_poll_cntl;
 689         u64 wptr_gpu_addr;
 690         int i, r;
 691
 692         for (i = 0; i < adev->sdma.num_instances; i++) {
 693                 ring = &adev->sdma.instance[i].ring;
 694
 695                 if (!amdgpu_sriov_vf(adev))
 696                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
 697
 698                 /* Set ring buffer size in dwords */
 699                 rb_bufsz = order_base_2(ring->ring_size / 4);
 700                 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 701                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 702 #ifdef __BIG_ENDIAN
 703                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 704                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 705                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 706 #endif
 707                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 708
 709                 /* Initialize the ring buffer's read and write pointers */
 710                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
 711                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
 712                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
 713                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
 714
 715                 /* setup the wptr shadow polling */
 716                 wptr_gpu_addr = ring->wptr_gpu_addr;
 717                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
 718                        lower_32_bits(wptr_gpu_addr));
 719                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
 720                        upper_32_bits(wptr_gpu_addr));
 721                 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,
 722                                                          mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
 723                 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 724                                                SDMA0_GFX_RB_WPTR_POLL_CNTL,
 725                                                F32_POLL_ENABLE, 1);
 726                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
 727                        wptr_poll_cntl);
 728
 729                 /* set the wb address whether it's enabled or not */
 730                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
 731                        upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
 732                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
 733                        lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
 734
 735                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 736
 737                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE),
 738                        ring->gpu_addr >> 8);
 739                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI),
 740                        ring->gpu_addr >> 40);
 741
 742                 ring->wptr = 0;
 743
 744                 /* before programing wptr to a less value, need set minor_ptr_update first */
 745                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
 746
 747                 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
 748                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR),
 749                                lower_32_bits(ring->wptr << 2));
 750                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI),
 751                                upper_32_bits(ring->wptr << 2));
 752                 }
 753
 754                 doorbell = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
 755                 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,
 756                                                 mmSDMA0_GFX_DOORBELL_OFFSET));
 757
 758                 if (ring->use_doorbell) {
 759                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 760                         doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
 761                                         OFFSET, ring->doorbell_index);
 762                 } else {
 763                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 764                 }
 765                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
 766                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET),
 767                        doorbell_offset);
 768
 769                 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
 770                                                       ring->doorbell_index, 20);
 771
 772                 if (amdgpu_sriov_vf(adev))
 773                         sdma_v5_0_ring_set_wptr(ring);
 774
 775                 /* set minor_ptr_update to 0 after wptr programed */
 776                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
 777
 778                 if (!amdgpu_sriov_vf(adev)) {
 779                         /* set utc l1 enable flag always to 1 */
 780                         temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
 781                         temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
 782
 783                         /* enable MCBP */
 784                         temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
 785                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
 786
 787                         /* Set up RESP_MODE to non-copy addresses */
 788                         temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
 789                         temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
 790                         temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
 791                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
 792
 793                         /* program default cache read and write policy */
 794                         temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
 795                         /* clean read policy and write policy bits */
 796                         temp &= 0xFF0FFF;
 797                         temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14));
 798                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
 799                 }
 800
 801                 if (!amdgpu_sriov_vf(adev)) {
 802                         /* unhalt engine */
 803                         temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 804                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
 805                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
 806                 }
 807
 808                 /* enable DMA RB */
 809                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 810                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 811
 812                 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 813                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 814 #ifdef __BIG_ENDIAN
 815                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 816 #endif
 817                 /* enable DMA IBs */
 818                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 819
 820                 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
 821                         sdma_v5_0_ctx_switch_enable(adev, true);
 822                         sdma_v5_0_enable(adev, true);
 823                 }
 824
 825                 r = amdgpu_ring_test_helper(ring);
 826                 if (r)
 827                         return r;
 828
 829                 if (adev->mman.buffer_funcs_ring == ring)
 830                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
 831         }
 832
 833         return 0;
 834 }
 835
 836 /**
 837  * sdma_v5_0_rlc_resume - setup and start the async dma engines
 838  *
 839  * @adev: amdgpu_device pointer
 840  *
 841  * Set up the compute DMA queues and enable them (NAVI10).
 842  * Returns 0 for success, error for failure.
 843  */
 844 static int sdma_v5_0_rlc_resume(struct amdgpu_device *adev)
 845 {
 846         return 0;
 847 }
 848
 849 /**
 850  * sdma_v5_0_load_microcode - load the sDMA ME ucode
 851  *
 852  * @adev: amdgpu_device pointer
 853  *
 854  * Loads the sDMA0/1 ucode.
 855  * Returns 0 for success, -EINVAL if the ucode is not available.
 856  */
 857 static int sdma_v5_0_load_microcode(struct amdgpu_device *adev)
 858 {
 859         const struct sdma_firmware_header_v1_0 *hdr;
 860         const __le32 *fw_data;
 861         u32 fw_size;
 862         int i, j;
 863
 864         /* halt the MEs */
 865         sdma_v5_0_enable(adev, false);
 866
 867         for (i = 0; i < adev->sdma.num_instances; i++) {
 868                 if (!adev->sdma.instance[i].fw)
 869                         return -EINVAL;
 870
 871                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 872                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 873                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 874
 875                 fw_data = (const __le32 *)
 876                         (adev->sdma.instance[i].fw->data +
 877                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 878
 879                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
 880
 881                 for (j = 0; j < fw_size; j++) {
 882                         if (amdgpu_emu_mode == 1 && j % 500 == 0)
 883                                 msleep(1);
 884                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
 885                 }
 886
 887                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
 888         }
 889
 890         return 0;
 891 }
 892
 893 /**
 894  * sdma_v5_0_start - setup and start the async dma engines
 895  *
 896  * @adev: amdgpu_device pointer
 897  *
 898  * Set up the DMA engines and enable them (NAVI10).
 899  * Returns 0 for success, error for failure.
 900  */
 901 static int sdma_v5_0_start(struct amdgpu_device *adev)
 902 {
 903         int r = 0;
 904
 905         if (amdgpu_sriov_vf(adev)) {
 906                 sdma_v5_0_ctx_switch_enable(adev, false);
 907                 sdma_v5_0_enable(adev, false);
 908
 909                 /* set RB registers */
 910                 r = sdma_v5_0_gfx_resume(adev);
 911                 return r;
 912         }
 913
 914         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
 915                 r = sdma_v5_0_load_microcode(adev);
 916                 if (r)
 917                         return r;
 918         }
 919
 920         /* unhalt the MEs */
 921         sdma_v5_0_enable(adev, true);
 922         /* enable sdma ring preemption */
 923         sdma_v5_0_ctx_switch_enable(adev, true);
 924
 925         /* start the gfx rings and rlc compute queues */
 926         r = sdma_v5_0_gfx_resume(adev);
 927         if (r)
 928                 return r;
 929         r = sdma_v5_0_rlc_resume(adev);
 930
 931         return r;
 932 }
 933
 934 static int sdma_v5_0_mqd_init(struct amdgpu_device *adev, void *mqd,
 935                               struct amdgpu_mqd_prop *prop)
 936 {
 937         struct v10_sdma_mqd *m = mqd;
 938         uint64_t wb_gpu_addr;
 939
 940         m->sdmax_rlcx_rb_cntl =
 941                 order_base_2(prop->queue_size / 4) << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
 942                 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
 943                 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT |
 944                 1 << SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT;
 945
 946         m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8);
 947         m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8);
 948
 949         m->sdmax_rlcx_rb_wptr_poll_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, 0,
 950                                                   mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
 951
 952         wb_gpu_addr = prop->wptr_gpu_addr;
 953         m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr);
 954         m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr);
 955
 956         wb_gpu_addr = prop->rptr_gpu_addr;
 957         m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr);
 958         m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr);
 959
 960         m->sdmax_rlcx_ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, 0,
 961                                                         mmSDMA0_GFX_IB_CNTL));
 962
 963         m->sdmax_rlcx_doorbell_offset =
 964                 prop->doorbell_index << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT;
 965
 966         m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_RLC0_DOORBELL, ENABLE, 1);
 967
 968         return 0;
 969 }
 970
 971 static void sdma_v5_0_set_mqd_funcs(struct amdgpu_device *adev)
 972 {
 973         adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v10_sdma_mqd);
 974         adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v5_0_mqd_init;
 975 }
 976
 977 /**
 978  * sdma_v5_0_ring_test_ring - simple async dma engine test
 979  *
 980  * @ring: amdgpu_ring structure holding ring information
 981  *
 982  * Test the DMA engine by writing using it to write an
 983  * value to memory. (NAVI10).
 984  * Returns 0 for success, error for failure.
 985  */
 986 static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring)
 987 {
 988         struct amdgpu_device *adev = ring->adev;
 989         unsigned i;
 990         unsigned index;
 991         int r;
 992         u32 tmp;
 993         u64 gpu_addr;
 994         volatile uint32_t *cpu_ptr = NULL;
 995
 996         tmp = 0xCAFEDEAD;
 997
 998         if (ring->is_mes_queue) {
 999                 uint32_t offset = 0;
1000                 offset = amdgpu_mes_ctx_get_offs(ring,
1001                                          AMDGPU_MES_CTX_PADDING_OFFS);
1002                 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
1003                 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
1004                 *cpu_ptr = tmp;
1005         } else {
1006                 r = amdgpu_device_wb_get(adev, &index);
1007                 if (r) {
1008                         dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
1009                         return r;
1010                 }
1011
1012                 gpu_addr = adev->wb.gpu_addr + (index * 4);
1013                 adev->wb.wb[index] = cpu_to_le32(tmp);
1014         }
1015
1016         r = amdgpu_ring_alloc(ring, 20);
1017         if (r) {
1018                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
1019                 amdgpu_device_wb_free(adev, index);
1020                 return r;
1021         }
1022
1023         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1024                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
1025         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
1026         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
1027         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
1028         amdgpu_ring_write(ring, 0xDEADBEEF);
1029         amdgpu_ring_commit(ring);
1030
1031         for (i = 0; i < adev->usec_timeout; i++) {
1032                 if (ring->is_mes_queue)
1033                         tmp = le32_to_cpu(*cpu_ptr);
1034                 else
1035                         tmp = le32_to_cpu(adev->wb.wb[index]);
1036                 if (tmp == 0xDEADBEEF)
1037                         break;
1038                 if (amdgpu_emu_mode == 1)
1039                         msleep(1);
1040                 else
1041                         udelay(1);
1042         }
1043
1044         if (i >= adev->usec_timeout)
1045                 r = -ETIMEDOUT;
1046
1047         if (!ring->is_mes_queue)
1048                 amdgpu_device_wb_free(adev, index);
1049
1050         return r;
1051 }
1052
1053 /**
1054  * sdma_v5_0_ring_test_ib - test an IB on the DMA engine
1055  *
1056  * @ring: amdgpu_ring structure holding ring information
1057  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
1058  *
1059  * Test a simple IB in the DMA ring (NAVI10).
1060  * Returns 0 on success, error on failure.
1061  */
1062 static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1063 {
1064         struct amdgpu_device *adev = ring->adev;
1065         struct amdgpu_ib ib;
1066         struct dma_fence *f = NULL;
1067         unsigned index;
1068         long r;
1069         u32 tmp = 0;
1070         u64 gpu_addr;
1071         volatile uint32_t *cpu_ptr = NULL;
1072
1073         tmp = 0xCAFEDEAD;
1074         memset(&ib, 0, sizeof(ib));
1075
1076         if (ring->is_mes_queue) {
1077                 uint32_t offset = 0;
1078                 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
1079                 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
1080                 ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
1081
1082                 offset = amdgpu_mes_ctx_get_offs(ring,
1083                                          AMDGPU_MES_CTX_PADDING_OFFS);
1084                 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
1085                 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
1086                 *cpu_ptr = tmp;
1087         } else {
1088                 r = amdgpu_device_wb_get(adev, &index);
1089                 if (r) {
1090                         dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
1091                         return r;
1092                 }
1093
1094                 gpu_addr = adev->wb.gpu_addr + (index * 4);
1095                 adev->wb.wb[index] = cpu_to_le32(tmp);
1096
1097                 r = amdgpu_ib_get(adev, NULL, 256,
1098                                         AMDGPU_IB_POOL_DIRECT, &ib);
1099                 if (r) {
1100                         DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1101                         goto err0;
1102                 }
1103         }
1104
1105         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1106                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1107         ib.ptr[1] = lower_32_bits(gpu_addr);
1108         ib.ptr[2] = upper_32_bits(gpu_addr);
1109         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1110         ib.ptr[4] = 0xDEADBEEF;
1111         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1112         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1113         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1114         ib.length_dw = 8;
1115
1116         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1117         if (r)
1118                 goto err1;
1119
1120         r = dma_fence_wait_timeout(f, false, timeout);
1121         if (r == 0) {
1122                 DRM_ERROR("amdgpu: IB test timed out\n");
1123                 r = -ETIMEDOUT;
1124                 goto err1;
1125         } else if (r < 0) {
1126                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1127                 goto err1;
1128         }
1129
1130         if (ring->is_mes_queue)
1131                 tmp = le32_to_cpu(*cpu_ptr);
1132         else
1133                 tmp = le32_to_cpu(adev->wb.wb[index]);
1134
1135         if (tmp == 0xDEADBEEF)
1136                 r = 0;
1137         else
1138                 r = -EINVAL;
1139
1140 err1:
1141         amdgpu_ib_free(adev, &ib, NULL);
1142         dma_fence_put(f);
1143 err0:
1144         if (!ring->is_mes_queue)
1145                 amdgpu_device_wb_free(adev, index);
1146         return r;
1147 }
1148
1149
1150 /**
1151  * sdma_v5_0_vm_copy_pte - update PTEs by copying them from the GART
1152  *
1153  * @ib: indirect buffer to fill with commands
1154  * @pe: addr of the page entry
1155  * @src: src addr to copy from
1156  * @count: number of page entries to update
1157  *
1158  * Update PTEs by copying them from the GART using sDMA (NAVI10).
1159  */
1160 static void sdma_v5_0_vm_copy_pte(struct amdgpu_ib *ib,
1161                                   uint64_t pe, uint64_t src,
1162                                   unsigned count)
1163 {
1164         unsigned bytes = count * 8;
1165
1166         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1167                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1168         ib->ptr[ib->length_dw++] = bytes - 1;
1169         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1170         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1171         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1172         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1173         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1174
1175 }
1176
1177 /**
1178  * sdma_v5_0_vm_write_pte - update PTEs by writing them manually
1179  *
1180  * @ib: indirect buffer to fill with commands
1181  * @pe: addr of the page entry
1182  * @value: dst addr to write into pe
1183  * @count: number of page entries to update
1184  * @incr: increase next addr by incr bytes
1185  *
1186  * Update PTEs by writing them manually using sDMA (NAVI10).
1187  */
1188 static void sdma_v5_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1189                                    uint64_t value, unsigned count,
1190                                    uint32_t incr)
1191 {
1192         unsigned ndw = count * 2;
1193
1194         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1195                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1196         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1197         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1198         ib->ptr[ib->length_dw++] = ndw - 1;
1199         for (; ndw > 0; ndw -= 2) {
1200                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1201                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1202                 value += incr;
1203         }
1204 }
1205
1206 /**
1207  * sdma_v5_0_vm_set_pte_pde - update the page tables using sDMA
1208  *
1209  * @ib: indirect buffer to fill with commands
1210  * @pe: addr of the page entry
1211  * @addr: dst addr to write into pe
1212  * @count: number of page entries to update
1213  * @incr: increase next addr by incr bytes
1214  * @flags: access flags
1215  *
1216  * Update the page tables using sDMA (NAVI10).
1217  */
1218 static void sdma_v5_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1219                                      uint64_t pe,
1220                                      uint64_t addr, unsigned count,
1221                                      uint32_t incr, uint64_t flags)
1222 {
1223         /* for physically contiguous pages (vram) */
1224         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1225         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1226         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1227         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1228         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1229         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1230         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1231         ib->ptr[ib->length_dw++] = incr; /* increment size */
1232         ib->ptr[ib->length_dw++] = 0;
1233         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1234 }
1235
1236 /**
1237  * sdma_v5_0_ring_pad_ib - pad the IB
1238  * @ring: amdgpu_ring structure holding ring information
1239  * @ib: indirect buffer to fill with padding
1240  *
1241  * Pad the IB with NOPs to a boundary multiple of 8.
1242  */
1243 static void sdma_v5_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1244 {
1245         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1246         u32 pad_count;
1247         int i;
1248
1249         pad_count = (-ib->length_dw) & 0x7;
1250         for (i = 0; i < pad_count; i++)
1251                 if (sdma && sdma->burst_nop && (i == 0))
1252                         ib->ptr[ib->length_dw++] =
1253                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1254                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1255                 else
1256                         ib->ptr[ib->length_dw++] =
1257                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1258 }
1259
1260
1261 /**
1262  * sdma_v5_0_ring_emit_pipeline_sync - sync the pipeline
1263  *
1264  * @ring: amdgpu_ring pointer
1265  *
1266  * Make sure all previous operations are completed (CIK).
1267  */
1268 static void sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1269 {
1270         uint32_t seq = ring->fence_drv.sync_seq;
1271         uint64_t addr = ring->fence_drv.gpu_addr;
1272
1273         /* wait for idle */
1274         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1275                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1276                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1277                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1278         amdgpu_ring_write(ring, addr & 0xfffffffc);
1279         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1280         amdgpu_ring_write(ring, seq); /* reference */
1281         amdgpu_ring_write(ring, 0xffffffff); /* mask */
1282         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1283                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1284 }
1285
1286
1287 /**
1288  * sdma_v5_0_ring_emit_vm_flush - vm flush using sDMA
1289  *
1290  * @ring: amdgpu_ring pointer
1291  * @vmid: vmid number to use
1292  * @pd_addr: address
1293  *
1294  * Update the page table base and flush the VM TLB
1295  * using sDMA (NAVI10).
1296  */
1297 static void sdma_v5_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1298                                          unsigned vmid, uint64_t pd_addr)
1299 {
1300         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1301 }
1302
1303 static void sdma_v5_0_ring_emit_wreg(struct amdgpu_ring *ring,
1304                                      uint32_t reg, uint32_t val)
1305 {
1306         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1307                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1308         amdgpu_ring_write(ring, reg);
1309         amdgpu_ring_write(ring, val);
1310 }
1311
1312 static void sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1313                                          uint32_t val, uint32_t mask)
1314 {
1315         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1316                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1317                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1318         amdgpu_ring_write(ring, reg << 2);
1319         amdgpu_ring_write(ring, 0);
1320         amdgpu_ring_write(ring, val); /* reference */
1321         amdgpu_ring_write(ring, mask); /* mask */
1322         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1323                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1324 }
1325
1326 static void sdma_v5_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1327                                                    uint32_t reg0, uint32_t reg1,
1328                                                    uint32_t ref, uint32_t mask)
1329 {
1330         amdgpu_ring_emit_wreg(ring, reg0, ref);
1331         /* wait for a cycle to reset vm_inv_eng*_ack */
1332         amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1333         amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1334 }
1335
1336 static int sdma_v5_0_early_init(void *handle)
1337 {
1338         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1339
1340         sdma_v5_0_set_ring_funcs(adev);
1341         sdma_v5_0_set_buffer_funcs(adev);
1342         sdma_v5_0_set_vm_pte_funcs(adev);
1343         sdma_v5_0_set_irq_funcs(adev);
1344         sdma_v5_0_set_mqd_funcs(adev);
1345
1346         return 0;
1347 }
1348
1349
1350 static int sdma_v5_0_sw_init(void *handle)
1351 {
1352         struct amdgpu_ring *ring;
1353         int r, i;
1354         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1355
1356         /* SDMA trap event */
1357         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0,
1358                               SDMA0_5_0__SRCID__SDMA_TRAP,
1359                               &adev->sdma.trap_irq);
1360         if (r)
1361                 return r;
1362
1363         /* SDMA trap event */
1364         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1,
1365                               SDMA1_5_0__SRCID__SDMA_TRAP,
1366                               &adev->sdma.trap_irq);
1367         if (r)
1368                 return r;
1369
1370         r = sdma_v5_0_init_microcode(adev);
1371         if (r) {
1372                 DRM_ERROR("Failed to load sdma firmware!\n");
1373                 return r;
1374         }
1375
1376         for (i = 0; i < adev->sdma.num_instances; i++) {
1377                 ring = &adev->sdma.instance[i].ring;
1378                 ring->ring_obj = NULL;
1379                 ring->use_doorbell = true;
1380
1381                 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1382                                 ring->use_doorbell?"true":"false");
1383
1384                 ring->doorbell_index = (i == 0) ?
1385                         (adev->doorbell_index.sdma_engine[0] << 1) //get DWORD offset
1386                         : (adev->doorbell_index.sdma_engine[1] << 1); // get DWORD offset
1387
1388                 ring->vm_hub = AMDGPU_GFXHUB(0);
1389                 sprintf(ring->name, "sdma%d", i);
1390                 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1391                                      (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 :
1392                                      AMDGPU_SDMA_IRQ_INSTANCE1,
1393                                      AMDGPU_RING_PRIO_DEFAULT, NULL);
1394                 if (r)
1395                         return r;
1396         }
1397
1398         return r;
1399 }
1400
1401 static int sdma_v5_0_sw_fini(void *handle)
1402 {
1403         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1404         int i;
1405
1406         for (i = 0; i < adev->sdma.num_instances; i++)
1407                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1408
1409         amdgpu_sdma_destroy_inst_ctx(adev, false);
1410
1411         return 0;
1412 }
1413
1414 static int sdma_v5_0_hw_init(void *handle)
1415 {
1416         int r;
1417         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1418
1419         sdma_v5_0_init_golden_registers(adev);
1420
1421         r = sdma_v5_0_start(adev);
1422
1423         return r;
1424 }
1425
1426 static int sdma_v5_0_hw_fini(void *handle)
1427 {
1428         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1429
1430         if (amdgpu_sriov_vf(adev)) {
1431                 /* disable the scheduler for SDMA */
1432                 amdgpu_sdma_unset_buffer_funcs_helper(adev);
1433                 return 0;
1434         }
1435
1436         sdma_v5_0_ctx_switch_enable(adev, false);
1437         sdma_v5_0_enable(adev, false);
1438
1439         return 0;
1440 }
1441
1442 static int sdma_v5_0_suspend(void *handle)
1443 {
1444         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1445
1446         return sdma_v5_0_hw_fini(adev);
1447 }
1448
1449 static int sdma_v5_0_resume(void *handle)
1450 {
1451         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1452
1453         return sdma_v5_0_hw_init(adev);
1454 }
1455
1456 static bool sdma_v5_0_is_idle(void *handle)
1457 {
1458         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1459         u32 i;
1460
1461         for (i = 0; i < adev->sdma.num_instances; i++) {
1462                 u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1463
1464                 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1465                         return false;
1466         }
1467
1468         return true;
1469 }
1470
1471 static int sdma_v5_0_wait_for_idle(void *handle)
1472 {
1473         unsigned i;
1474         u32 sdma0, sdma1;
1475         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1476
1477         for (i = 0; i < adev->usec_timeout; i++) {
1478                 sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1479                 sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1480
1481                 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1482                         return 0;
1483                 udelay(1);
1484         }
1485         return -ETIMEDOUT;
1486 }
1487
1488 static int sdma_v5_0_soft_reset(void *handle)
1489 {
1490         /* todo */
1491
1492         return 0;
1493 }
1494
1495 static int sdma_v5_0_ring_preempt_ib(struct amdgpu_ring *ring)
1496 {
1497         int i, r = 0;
1498         struct amdgpu_device *adev = ring->adev;
1499         u32 index = 0;
1500         u64 sdma_gfx_preempt;
1501
1502         amdgpu_sdma_get_index_from_ring(ring, &index);
1503         if (index == 0)
1504                 sdma_gfx_preempt = mmSDMA0_GFX_PREEMPT;
1505         else
1506                 sdma_gfx_preempt = mmSDMA1_GFX_PREEMPT;
1507
1508         /* assert preemption condition */
1509         amdgpu_ring_set_preempt_cond_exec(ring, false);
1510
1511         /* emit the trailing fence */
1512         ring->trail_seq += 1;
1513         amdgpu_ring_alloc(ring, 10);
1514         sdma_v5_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1515                                   ring->trail_seq, 0);
1516         amdgpu_ring_commit(ring);
1517
1518         /* assert IB preemption */
1519         WREG32(sdma_gfx_preempt, 1);
1520
1521         /* poll the trailing fence */
1522         for (i = 0; i < adev->usec_timeout; i++) {
1523                 if (ring->trail_seq ==
1524                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1525                         break;
1526                 udelay(1);
1527         }
1528
1529         if (i >= adev->usec_timeout) {
1530                 r = -EINVAL;
1531                 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1532         }
1533
1534         /* deassert IB preemption */
1535         WREG32(sdma_gfx_preempt, 0);
1536
1537         /* deassert the preemption condition */
1538         amdgpu_ring_set_preempt_cond_exec(ring, true);
1539         return r;
1540 }
1541
1542 static int sdma_v5_0_set_trap_irq_state(struct amdgpu_device *adev,
1543                                         struct amdgpu_irq_src *source,
1544                                         unsigned type,
1545                                         enum amdgpu_interrupt_state state)
1546 {
1547         u32 sdma_cntl;
1548
1549         if (!amdgpu_sriov_vf(adev)) {
1550                 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ?
1551                         sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) :
1552                         sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_CNTL);
1553
1554                 sdma_cntl = RREG32(reg_offset);
1555                 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1556                                           state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1557                 WREG32(reg_offset, sdma_cntl);
1558         }
1559
1560         return 0;
1561 }
1562
1563 static int sdma_v5_0_process_trap_irq(struct amdgpu_device *adev,
1564                                       struct amdgpu_irq_src *source,
1565                                       struct amdgpu_iv_entry *entry)
1566 {
1567         uint32_t mes_queue_id = entry->src_data[0];
1568
1569         DRM_DEBUG("IH: SDMA trap\n");
1570
1571         if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
1572                 struct amdgpu_mes_queue *queue;
1573
1574                 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
1575
1576                 spin_lock(&adev->mes.queue_id_lock);
1577                 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
1578                 if (queue) {
1579                         DRM_DEBUG("process smda queue id = %d\n", mes_queue_id);
1580                         amdgpu_fence_process(queue->ring);
1581                 }
1582                 spin_unlock(&adev->mes.queue_id_lock);
1583                 return 0;
1584         }
1585
1586         switch (entry->client_id) {
1587         case SOC15_IH_CLIENTID_SDMA0:
1588                 switch (entry->ring_id) {
1589                 case 0:
1590                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1591                         break;
1592                 case 1:
1593                         /* XXX compute */
1594                         break;
1595                 case 2:
1596                         /* XXX compute */
1597                         break;
1598                 case 3:
1599                         /* XXX page queue*/
1600                         break;
1601                 }
1602                 break;
1603         case SOC15_IH_CLIENTID_SDMA1:
1604                 switch (entry->ring_id) {
1605                 case 0:
1606                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1607                         break;
1608                 case 1:
1609                         /* XXX compute */
1610                         break;
1611                 case 2:
1612                         /* XXX compute */
1613                         break;
1614                 case 3:
1615                         /* XXX page queue*/
1616                         break;
1617                 }
1618                 break;
1619         }
1620         return 0;
1621 }
1622
1623 static int sdma_v5_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1624                                               struct amdgpu_irq_src *source,
1625                                               struct amdgpu_iv_entry *entry)
1626 {
1627         return 0;
1628 }
1629
1630 static void sdma_v5_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1631                                                        bool enable)
1632 {
1633         uint32_t data, def;
1634         int i;
1635
1636         for (i = 0; i < adev->sdma.num_instances; i++) {
1637                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1638                         /* Enable sdma clock gating */
1639                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1640                         data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1641                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1642                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1643                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1644                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1645                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1646                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1647                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1648                         if (def != data)
1649                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1650                 } else {
1651                         /* Disable sdma clock gating */
1652                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1653                         data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1654                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1655                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1656                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1657                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1658                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1659                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1660                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1661                         if (def != data)
1662                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1663                 }
1664         }
1665 }
1666
1667 static void sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1668                                                       bool enable)
1669 {
1670         uint32_t data, def;
1671         int i;
1672
1673         for (i = 0; i < adev->sdma.num_instances; i++) {
1674                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1675                         /* Enable sdma mem light sleep */
1676                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1677                         data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1678                         if (def != data)
1679                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1680
1681                 } else {
1682                         /* Disable sdma mem light sleep */
1683                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1684                         data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1685                         if (def != data)
1686                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1687
1688                 }
1689         }
1690 }
1691
1692 static int sdma_v5_0_set_clockgating_state(void *handle,
1693                                            enum amd_clockgating_state state)
1694 {
1695         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1696
1697         if (amdgpu_sriov_vf(adev))
1698                 return 0;
1699
1700         switch (adev->ip_versions[SDMA0_HWIP][0]) {
1701         case IP_VERSION(5, 0, 0):
1702         case IP_VERSION(5, 0, 2):
1703         case IP_VERSION(5, 0, 5):
1704                 sdma_v5_0_update_medium_grain_clock_gating(adev,
1705                                 state == AMD_CG_STATE_GATE);
1706                 sdma_v5_0_update_medium_grain_light_sleep(adev,
1707                                 state == AMD_CG_STATE_GATE);
1708                 break;
1709         default:
1710                 break;
1711         }
1712
1713         return 0;
1714 }
1715
1716 static int sdma_v5_0_set_powergating_state(void *handle,
1717                                           enum amd_powergating_state state)
1718 {
1719         return 0;
1720 }
1721
1722 static void sdma_v5_0_get_clockgating_state(void *handle, u64 *flags)
1723 {
1724         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1725         int data;
1726
1727         if (amdgpu_sriov_vf(adev))
1728                 *flags = 0;
1729
1730         /* AMD_CG_SUPPORT_SDMA_MGCG */
1731         data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL));
1732         if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
1733                 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1734
1735         /* AMD_CG_SUPPORT_SDMA_LS */
1736         data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1737         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1738                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1739 }
1740
1741 const struct amd_ip_funcs sdma_v5_0_ip_funcs = {
1742         .name = "sdma_v5_0",
1743         .early_init = sdma_v5_0_early_init,
1744         .late_init = NULL,
1745         .sw_init = sdma_v5_0_sw_init,
1746         .sw_fini = sdma_v5_0_sw_fini,
1747         .hw_init = sdma_v5_0_hw_init,
1748         .hw_fini = sdma_v5_0_hw_fini,
1749         .suspend = sdma_v5_0_suspend,
1750         .resume = sdma_v5_0_resume,
1751         .is_idle = sdma_v5_0_is_idle,
1752         .wait_for_idle = sdma_v5_0_wait_for_idle,
1753         .soft_reset = sdma_v5_0_soft_reset,
1754         .set_clockgating_state = sdma_v5_0_set_clockgating_state,
1755         .set_powergating_state = sdma_v5_0_set_powergating_state,
1756         .get_clockgating_state = sdma_v5_0_get_clockgating_state,
1757 };
1758
1759 static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = {
1760         .type = AMDGPU_RING_TYPE_SDMA,
1761         .align_mask = 0xf,
1762         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1763         .support_64bit_ptrs = true,
1764         .secure_submission_supported = true,
1765         .get_rptr = sdma_v5_0_ring_get_rptr,
1766         .get_wptr = sdma_v5_0_ring_get_wptr,
1767         .set_wptr = sdma_v5_0_ring_set_wptr,
1768         .emit_frame_size =
1769                 5 + /* sdma_v5_0_ring_init_cond_exec */
1770                 6 + /* sdma_v5_0_ring_emit_hdp_flush */
1771                 3 + /* hdp_invalidate */
1772                 6 + /* sdma_v5_0_ring_emit_pipeline_sync */
1773                 /* sdma_v5_0_ring_emit_vm_flush */
1774                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1775                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 * 2 +
1776                 10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */
1777         .emit_ib_size = 5 + 7 + 6, /* sdma_v5_0_ring_emit_ib */
1778         .emit_ib = sdma_v5_0_ring_emit_ib,
1779         .emit_mem_sync = sdma_v5_0_ring_emit_mem_sync,
1780         .emit_fence = sdma_v5_0_ring_emit_fence,
1781         .emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync,
1782         .emit_vm_flush = sdma_v5_0_ring_emit_vm_flush,
1783         .emit_hdp_flush = sdma_v5_0_ring_emit_hdp_flush,
1784         .test_ring = sdma_v5_0_ring_test_ring,
1785         .test_ib = sdma_v5_0_ring_test_ib,
1786         .insert_nop = sdma_v5_0_ring_insert_nop,
1787         .pad_ib = sdma_v5_0_ring_pad_ib,
1788         .emit_wreg = sdma_v5_0_ring_emit_wreg,
1789         .emit_reg_wait = sdma_v5_0_ring_emit_reg_wait,
1790         .emit_reg_write_reg_wait = sdma_v5_0_ring_emit_reg_write_reg_wait,
1791         .init_cond_exec = sdma_v5_0_ring_init_cond_exec,
1792         .patch_cond_exec = sdma_v5_0_ring_patch_cond_exec,
1793         .preempt_ib = sdma_v5_0_ring_preempt_ib,
1794 };
1795
1796 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev)
1797 {
1798         int i;
1799
1800         for (i = 0; i < adev->sdma.num_instances; i++) {
1801                 adev->sdma.instance[i].ring.funcs = &sdma_v5_0_ring_funcs;
1802                 adev->sdma.instance[i].ring.me = i;
1803         }
1804 }
1805
1806 static const struct amdgpu_irq_src_funcs sdma_v5_0_trap_irq_funcs = {
1807         .set = sdma_v5_0_set_trap_irq_state,
1808         .process = sdma_v5_0_process_trap_irq,
1809 };
1810
1811 static const struct amdgpu_irq_src_funcs sdma_v5_0_illegal_inst_irq_funcs = {
1812         .process = sdma_v5_0_process_illegal_inst_irq,
1813 };
1814
1815 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev)
1816 {
1817         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1818                                         adev->sdma.num_instances;
1819         adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs;
1820         adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs;
1821 }
1822
1823 /**
1824  * sdma_v5_0_emit_copy_buffer - copy buffer using the sDMA engine
1825  *
1826  * @ib: indirect buffer to copy to
1827  * @src_offset: src GPU address
1828  * @dst_offset: dst GPU address
1829  * @byte_count: number of bytes to xfer
1830  * @tmz: if a secure copy should be used
1831  *
1832  * Copy GPU buffers using the DMA engine (NAVI10).
1833  * Used by the amdgpu ttm implementation to move pages if
1834  * registered as the asic copy callback.
1835  */
1836 static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib *ib,
1837                                        uint64_t src_offset,
1838                                        uint64_t dst_offset,
1839                                        uint32_t byte_count,
1840                                        bool tmz)
1841 {
1842         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1843                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1844                 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1845         ib->ptr[ib->length_dw++] = byte_count - 1;
1846         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1847         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1848         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1849         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1850         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1851 }
1852
1853 /**
1854  * sdma_v5_0_emit_fill_buffer - fill buffer using the sDMA engine
1855  *
1856  * @ib: indirect buffer to fill
1857  * @src_data: value to write to buffer
1858  * @dst_offset: dst GPU address
1859  * @byte_count: number of bytes to xfer
1860  *
1861  * Fill GPU buffers using the DMA engine (NAVI10).
1862  */
1863 static void sdma_v5_0_emit_fill_buffer(struct amdgpu_ib *ib,
1864                                        uint32_t src_data,
1865                                        uint64_t dst_offset,
1866                                        uint32_t byte_count)
1867 {
1868         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1869         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1870         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1871         ib->ptr[ib->length_dw++] = src_data;
1872         ib->ptr[ib->length_dw++] = byte_count - 1;
1873 }
1874
1875 static const struct amdgpu_buffer_funcs sdma_v5_0_buffer_funcs = {
1876         .copy_max_bytes = 0x400000,
1877         .copy_num_dw = 7,
1878         .emit_copy_buffer = sdma_v5_0_emit_copy_buffer,
1879
1880         .fill_max_bytes = 0x400000,
1881         .fill_num_dw = 5,
1882         .emit_fill_buffer = sdma_v5_0_emit_fill_buffer,
1883 };
1884
1885 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev)
1886 {
1887         if (adev->mman.buffer_funcs == NULL) {
1888                 adev->mman.buffer_funcs = &sdma_v5_0_buffer_funcs;
1889                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1890         }
1891 }
1892
1893 static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs = {
1894         .copy_pte_num_dw = 7,
1895         .copy_pte = sdma_v5_0_vm_copy_pte,
1896         .write_pte = sdma_v5_0_vm_write_pte,
1897         .set_pte_pde = sdma_v5_0_vm_set_pte_pde,
1898 };
1899
1900 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1901 {
1902         unsigned i;
1903
1904         if (adev->vm_manager.vm_pte_funcs == NULL) {
1905                 adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs;
1906                 for (i = 0; i < adev->sdma.num_instances; i++) {
1907                         adev->vm_manager.vm_pte_scheds[i] =
1908                                 &adev->sdma.instance[i].ring.sched;
1909                 }
1910                 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1911         }
1912 }
1913
1914 const struct amdgpu_ip_block_version sdma_v5_0_ip_block = {
1915         .type = AMD_IP_BLOCK_TYPE_SDMA,
1916         .major = 5,
1917         .minor = 0,
1918         .rev = 0,
1919         .funcs = &sdma_v5_0_ip_funcs,
1920 };