drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_ucode.h"
  28 #include "amdgpu_trace.h"
  29
  30 #include "sdma0/sdma0_4_2_offset.h"
  31 #include "sdma0/sdma0_4_2_sh_mask.h"
  32 #include "sdma1/sdma1_4_2_offset.h"
  33 #include "sdma1/sdma1_4_2_sh_mask.h"
  34 #include "hdp/hdp_4_0_offset.h"
  35 #include "sdma0/sdma0_4_1_default.h"
  36
  37 #include "soc15_common.h"
  38 #include "soc15.h"
  39 #include "vega10_sdma_pkt_open.h"
  40
  41 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h"
  42 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h"
  43
  44 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin");
  45 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin");
  46 MODULE_FIRMWARE("amdgpu/vega12_sdma.bin");
  47 MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin");
  48 MODULE_FIRMWARE("amdgpu/vega20_sdma.bin");
  49 MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin");
  50 MODULE_FIRMWARE("amdgpu/raven_sdma.bin");
  51 MODULE_FIRMWARE("amdgpu/picasso_sdma.bin");
  52 MODULE_FIRMWARE("amdgpu/raven2_sdma.bin");
  53
  54 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK  0x000000F8L
  55 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
  56
  57 #define WREG32_SDMA(instance, offset, value) \
  58         WREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)), value)
  59 #define RREG32_SDMA(instance, offset) \
  60         RREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)))
  61
  62 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev);
  63 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev);
  64 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  65 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev);
  66
  67 static const struct soc15_reg_golden golden_settings_sdma_4[] = {
  68         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
  69         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100),
  70         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100),
  71         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  72         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
  73         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  74         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000),
  75         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
  76         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  77         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
  78         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  79         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
  80         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000),
  81         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
  82         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
  83         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100),
  84         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  85         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
  86         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  87         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000),
  88         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
  89         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  90         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
  91         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  92         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0),
  93         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000)
  94 };
  95
  96 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = {
  97         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
  98         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
  99         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
 100         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002)
 101 };
 102
 103 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = {
 104         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
 105         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001),
 106         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
 107         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001)
 108 };
 109
 110 static const struct soc15_reg_golden golden_settings_sdma_4_1[] = {
 111         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
 112         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
 113         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100),
 114         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 115         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051),
 116         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100),
 117         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 118         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100),
 119         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 120         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
 121         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000)
 122 };
 123
 124 static const struct soc15_reg_golden golden_settings_sdma0_4_2_init[] = {
 125         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
 126 };
 127
 128 static const struct soc15_reg_golden golden_settings_sdma0_4_2[] =
 129 {
 130         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
 131         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
 132         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 133         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 134         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 135         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 136         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 137         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 138         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RD_BURST_CNTL, 0x0000000f, 0x00000003),
 139         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 140         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
 141         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 142         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 143         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 144         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 145         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 146         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 147         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 148         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 149         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 150         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 151         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 152         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 153         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 154         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 155         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
 156         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xFE000000, 0x00000000),
 157 };
 158
 159 static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = {
 160         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
 161         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
 162         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 163         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 164         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 165         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 166         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 167         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 168         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RD_BURST_CNTL, 0x0000000f, 0x00000003),
 169         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 170         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
 171         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 172         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 173         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 174         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 175         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 176         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 177         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 178         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 179         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 180         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 181         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 182         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 183         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
 184         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 185         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0),
 186         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xFE000000, 0x00000000),
 187 };
 188
 189 static const struct soc15_reg_golden golden_settings_sdma_rv1[] =
 190 {
 191         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002),
 192         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002)
 193 };
 194
 195 static const struct soc15_reg_golden golden_settings_sdma_rv2[] =
 196 {
 197         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00003001),
 198         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003001)
 199 };
 200
 201 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev,
 202                 u32 instance, u32 offset)
 203 {
 204         return ( 0 == instance ? (adev->reg_offset[SDMA0_HWIP][0][0] + offset) :
 205                         (adev->reg_offset[SDMA1_HWIP][0][0] + offset));
 206 }
 207
 208 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
 209 {
 210         switch (adev->asic_type) {
 211         case CHIP_VEGA10:
 212                 soc15_program_register_sequence(adev,
 213                                                  golden_settings_sdma_4,
 214                                                  ARRAY_SIZE(golden_settings_sdma_4));
 215                 soc15_program_register_sequence(adev,
 216                                                  golden_settings_sdma_vg10,
 217                                                  ARRAY_SIZE(golden_settings_sdma_vg10));
 218                 break;
 219         case CHIP_VEGA12:
 220                 soc15_program_register_sequence(adev,
 221                                                 golden_settings_sdma_4,
 222                                                 ARRAY_SIZE(golden_settings_sdma_4));
 223                 soc15_program_register_sequence(adev,
 224                                                 golden_settings_sdma_vg12,
 225                                                 ARRAY_SIZE(golden_settings_sdma_vg12));
 226                 break;
 227         case CHIP_VEGA20:
 228                 soc15_program_register_sequence(adev,
 229                                                 golden_settings_sdma0_4_2_init,
 230                                                 ARRAY_SIZE(golden_settings_sdma0_4_2_init));
 231                 soc15_program_register_sequence(adev,
 232                                                 golden_settings_sdma0_4_2,
 233                                                 ARRAY_SIZE(golden_settings_sdma0_4_2));
 234                 soc15_program_register_sequence(adev,
 235                                                 golden_settings_sdma1_4_2,
 236                                                 ARRAY_SIZE(golden_settings_sdma1_4_2));
 237                 break;
 238         case CHIP_RAVEN:
 239                 soc15_program_register_sequence(adev,
 240                                                 golden_settings_sdma_4_1,
 241                                                 ARRAY_SIZE(golden_settings_sdma_4_1));
 242                 if (adev->rev_id >= 8)
 243                         soc15_program_register_sequence(adev,
 244                                                         golden_settings_sdma_rv2,
 245                                                         ARRAY_SIZE(golden_settings_sdma_rv2));
 246                 else
 247                         soc15_program_register_sequence(adev,
 248                                                         golden_settings_sdma_rv1,
 249                                                         ARRAY_SIZE(golden_settings_sdma_rv1));
 250                 break;
 251         default:
 252                 break;
 253         }
 254 }
 255
 256 /**
 257  * sdma_v4_0_init_microcode - load ucode images from disk
 258  *
 259  * @adev: amdgpu_device pointer
 260  *
 261  * Use the firmware interface to load the ucode images into
 262  * the driver (not loaded into hw).
 263  * Returns 0 on success, error on failure.
 264  */
 265
 266 // emulation only, won't work on real chip
 267 // vega10 real chip need to use PSP to load firmware
 268 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
 269 {
 270         const char *chip_name;
 271         char fw_name[30];
 272         int err = 0, i;
 273         struct amdgpu_firmware_info *info = NULL;
 274         const struct common_firmware_header *header = NULL;
 275         const struct sdma_firmware_header_v1_0 *hdr;
 276
 277         DRM_DEBUG("\n");
 278
 279         switch (adev->asic_type) {
 280         case CHIP_VEGA10:
 281                 chip_name = "vega10";
 282                 break;
 283         case CHIP_VEGA12:
 284                 chip_name = "vega12";
 285                 break;
 286         case CHIP_VEGA20:
 287                 chip_name = "vega20";
 288                 break;
 289         case CHIP_RAVEN:
 290                 if (adev->rev_id >= 8)
 291                         chip_name = "raven2";
 292                 else if (adev->pdev->device == 0x15d8)
 293                         chip_name = "picasso";
 294                 else
 295                         chip_name = "raven";
 296                 break;
 297         default:
 298                 BUG();
 299         }
 300
 301         for (i = 0; i < adev->sdma.num_instances; i++) {
 302                 if (i == 0)
 303                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 304                 else
 305                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
 306                 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 307                 if (err)
 308                         goto out;
 309                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 310                 if (err)
 311                         goto out;
 312                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 313                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 314                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 315                 if (adev->sdma.instance[i].feature_version >= 20)
 316                         adev->sdma.instance[i].burst_nop = true;
 317                 DRM_DEBUG("psp_load == '%s'\n",
 318                                 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
 319
 320                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 321                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 322                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 323                         info->fw = adev->sdma.instance[i].fw;
 324                         header = (const struct common_firmware_header *)info->fw->data;
 325                         adev->firmware.fw_size +=
 326                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 327                 }
 328         }
 329 out:
 330         if (err) {
 331                 DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name);
 332                 for (i = 0; i < adev->sdma.num_instances; i++) {
 333                         release_firmware(adev->sdma.instance[i].fw);
 334                         adev->sdma.instance[i].fw = NULL;
 335                 }
 336         }
 337         return err;
 338 }
 339
 340 /**
 341  * sdma_v4_0_ring_get_rptr - get the current read pointer
 342  *
 343  * @ring: amdgpu ring pointer
 344  *
 345  * Get the current rptr from the hardware (VEGA10+).
 346  */
 347 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring)
 348 {
 349         u64 *rptr;
 350
 351         /* XXX check if swapping is necessary on BE */
 352         rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
 353
 354         DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
 355         return ((*rptr) >> 2);
 356 }
 357
 358 /**
 359  * sdma_v4_0_ring_get_wptr - get the current write pointer
 360  *
 361  * @ring: amdgpu ring pointer
 362  *
 363  * Get the current wptr from the hardware (VEGA10+).
 364  */
 365 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
 366 {
 367         struct amdgpu_device *adev = ring->adev;
 368         u64 wptr;
 369
 370         if (ring->use_doorbell) {
 371                 /* XXX check if swapping is necessary on BE */
 372                 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
 373                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
 374         } else {
 375                 u32 lowbit, highbit;
 376
 377                 lowbit = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR) >> 2;
 378                 highbit = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI) >> 2;
 379
 380                 DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n",
 381                                 ring->me, highbit, lowbit);
 382                 wptr = highbit;
 383                 wptr = wptr << 32;
 384                 wptr |= lowbit;
 385         }
 386
 387         return wptr >> 2;
 388 }
 389
 390 /**
 391  * sdma_v4_0_ring_set_wptr - commit the write pointer
 392  *
 393  * @ring: amdgpu ring pointer
 394  *
 395  * Write the wptr back to the hardware (VEGA10+).
 396  */
 397 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
 398 {
 399         struct amdgpu_device *adev = ring->adev;
 400
 401         DRM_DEBUG("Setting write pointer\n");
 402         if (ring->use_doorbell) {
 403                 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
 404
 405                 DRM_DEBUG("Using doorbell -- "
 406                                 "wptr_offs == 0x%08x "
 407                                 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
 408                                 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 409                                 ring->wptr_offs,
 410                                 lower_32_bits(ring->wptr << 2),
 411                                 upper_32_bits(ring->wptr << 2));
 412                 /* XXX check if swapping is necessary on BE */
 413                 WRITE_ONCE(*wb, (ring->wptr << 2));
 414                 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 415                                 ring->doorbell_index, ring->wptr << 2);
 416                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 417         } else {
 418                 DRM_DEBUG("Not using doorbell -- "
 419                                 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 420                                 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 421                                 ring->me,
 422                                 lower_32_bits(ring->wptr << 2),
 423                                 ring->me,
 424                                 upper_32_bits(ring->wptr << 2));
 425                 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR,
 426                             lower_32_bits(ring->wptr << 2));
 427                 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI,
 428                             upper_32_bits(ring->wptr << 2));
 429         }
 430 }
 431
 432 /**
 433  * sdma_v4_0_page_ring_get_wptr - get the current write pointer
 434  *
 435  * @ring: amdgpu ring pointer
 436  *
 437  * Get the current wptr from the hardware (VEGA10+).
 438  */
 439 static uint64_t sdma_v4_0_page_ring_get_wptr(struct amdgpu_ring *ring)
 440 {
 441         struct amdgpu_device *adev = ring->adev;
 442         u64 wptr;
 443
 444         if (ring->use_doorbell) {
 445                 /* XXX check if swapping is necessary on BE */
 446                 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
 447         } else {
 448                 wptr = RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI);
 449                 wptr = wptr << 32;
 450                 wptr |= RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR);
 451         }
 452
 453         return wptr >> 2;
 454 }
 455
 456 /**
 457  * sdma_v4_0_ring_set_wptr - commit the write pointer
 458  *
 459  * @ring: amdgpu ring pointer
 460  *
 461  * Write the wptr back to the hardware (VEGA10+).
 462  */
 463 static void sdma_v4_0_page_ring_set_wptr(struct amdgpu_ring *ring)
 464 {
 465         struct amdgpu_device *adev = ring->adev;
 466
 467         if (ring->use_doorbell) {
 468                 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
 469
 470                 /* XXX check if swapping is necessary on BE */
 471                 WRITE_ONCE(*wb, (ring->wptr << 2));
 472                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 473         } else {
 474                 uint64_t wptr = ring->wptr << 2;
 475
 476                 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR,
 477                             lower_32_bits(wptr));
 478                 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI,
 479                             upper_32_bits(wptr));
 480         }
 481 }
 482
 483 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 484 {
 485         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 486         int i;
 487
 488         for (i = 0; i < count; i++)
 489                 if (sdma && sdma->burst_nop && (i == 0))
 490                         amdgpu_ring_write(ring, ring->funcs->nop |
 491                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 492                 else
 493                         amdgpu_ring_write(ring, ring->funcs->nop);
 494 }
 495
 496 /**
 497  * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine
 498  *
 499  * @ring: amdgpu ring pointer
 500  * @ib: IB object to schedule
 501  *
 502  * Schedule an IB in the DMA ring (VEGA10).
 503  */
 504 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring,
 505                                         struct amdgpu_ib *ib,
 506                                         unsigned vmid, bool ctx_switch)
 507 {
 508         /* IB packet must end on a 8 DW boundary */
 509         sdma_v4_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8);
 510
 511         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 512                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 513         /* base must be 32 byte aligned */
 514         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 515         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 516         amdgpu_ring_write(ring, ib->length_dw);
 517         amdgpu_ring_write(ring, 0);
 518         amdgpu_ring_write(ring, 0);
 519
 520 }
 521
 522 static void sdma_v4_0_wait_reg_mem(struct amdgpu_ring *ring,
 523                                    int mem_space, int hdp,
 524                                    uint32_t addr0, uint32_t addr1,
 525                                    uint32_t ref, uint32_t mask,
 526                                    uint32_t inv)
 527 {
 528         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 529                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) |
 530                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) |
 531                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 532         if (mem_space) {
 533                 /* memory */
 534                 amdgpu_ring_write(ring, addr0);
 535                 amdgpu_ring_write(ring, addr1);
 536         } else {
 537                 /* registers */
 538                 amdgpu_ring_write(ring, addr0 << 2);
 539                 amdgpu_ring_write(ring, addr1 << 2);
 540         }
 541         amdgpu_ring_write(ring, ref); /* reference */
 542         amdgpu_ring_write(ring, mask); /* mask */
 543         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 544                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */
 545 }
 546
 547 /**
 548  * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 549  *
 550  * @ring: amdgpu ring pointer
 551  *
 552  * Emit an hdp flush packet on the requested DMA ring.
 553  */
 554 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 555 {
 556         struct amdgpu_device *adev = ring->adev;
 557         u32 ref_and_mask = 0;
 558         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;
 559
 560         if (ring->me == 0)
 561                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
 562         else
 563                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
 564
 565         sdma_v4_0_wait_reg_mem(ring, 0, 1,
 566                                adev->nbio_funcs->get_hdp_flush_done_offset(adev),
 567                                adev->nbio_funcs->get_hdp_flush_req_offset(adev),
 568                                ref_and_mask, ref_and_mask, 10);
 569 }
 570
 571 /**
 572  * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring
 573  *
 574  * @ring: amdgpu ring pointer
 575  * @fence: amdgpu fence object
 576  *
 577  * Add a DMA fence packet to the ring to write
 578  * the fence seq number and DMA trap packet to generate
 579  * an interrupt if needed (VEGA10).
 580  */
 581 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 582                                       unsigned flags)
 583 {
 584         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 585         /* write the fence */
 586         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 587         /* zero in first two bits */
 588         BUG_ON(addr & 0x3);
 589         amdgpu_ring_write(ring, lower_32_bits(addr));
 590         amdgpu_ring_write(ring, upper_32_bits(addr));
 591         amdgpu_ring_write(ring, lower_32_bits(seq));
 592
 593         /* optionally write high bits as well */
 594         if (write64bit) {
 595                 addr += 4;
 596                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 597                 /* zero in first two bits */
 598                 BUG_ON(addr & 0x3);
 599                 amdgpu_ring_write(ring, lower_32_bits(addr));
 600                 amdgpu_ring_write(ring, upper_32_bits(addr));
 601                 amdgpu_ring_write(ring, upper_32_bits(seq));
 602         }
 603
 604         /* generate an interrupt */
 605         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 606         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 607 }
 608
 609
 610 /**
 611  * sdma_v4_0_gfx_stop - stop the gfx async dma engines
 612  *
 613  * @adev: amdgpu_device pointer
 614  *
 615  * Stop the gfx async dma ring buffers (VEGA10).
 616  */
 617 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev)
 618 {
 619         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 620         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 621         u32 rb_cntl, ib_cntl;
 622         int i;
 623
 624         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 625             (adev->mman.buffer_funcs_ring == sdma1))
 626                         amdgpu_ttm_set_buffer_funcs_status(adev, false);
 627
 628         for (i = 0; i < adev->sdma.num_instances; i++) {
 629                 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);
 630                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 631                 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
 632                 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL);
 633                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 634                 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);
 635         }
 636
 637         sdma0->ready = false;
 638         sdma1->ready = false;
 639 }
 640
 641 /**
 642  * sdma_v4_0_rlc_stop - stop the compute async dma engines
 643  *
 644  * @adev: amdgpu_device pointer
 645  *
 646  * Stop the compute async dma queues (VEGA10).
 647  */
 648 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev)
 649 {
 650         /* XXX todo */
 651 }
 652
 653 /**
 654  * sdma_v4_0_page_stop - stop the page async dma engines
 655  *
 656  * @adev: amdgpu_device pointer
 657  *
 658  * Stop the page async dma ring buffers (VEGA10).
 659  */
 660 static void sdma_v4_0_page_stop(struct amdgpu_device *adev)
 661 {
 662         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].page;
 663         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].page;
 664         u32 rb_cntl, ib_cntl;
 665         int i;
 666
 667         for (i = 0; i < adev->sdma.num_instances; i++) {
 668                 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL);
 669                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL,
 670                                         RB_ENABLE, 0);
 671                 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
 672                 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL);
 673                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL,
 674                                         IB_ENABLE, 0);
 675                 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl);
 676         }
 677
 678         sdma0->ready = false;
 679         sdma1->ready = false;
 680 }
 681
 682 /**
 683  * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch
 684  *
 685  * @adev: amdgpu_device pointer
 686  * @enable: enable/disable the DMA MEs context switch.
 687  *
 688  * Halt or unhalt the async dma engines context switch (VEGA10).
 689  */
 690 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 691 {
 692         u32 f32_cntl, phase_quantum = 0;
 693         int i;
 694
 695         if (amdgpu_sdma_phase_quantum) {
 696                 unsigned value = amdgpu_sdma_phase_quantum;
 697                 unsigned unit = 0;
 698
 699                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 700                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 701                         value = (value + 1) >> 1;
 702                         unit++;
 703                 }
 704                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 705                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 706                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 707                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 708                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 709                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 710                         WARN_ONCE(1,
 711                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 712                                   value << unit);
 713                 }
 714                 phase_quantum =
 715                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 716                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 717         }
 718
 719         for (i = 0; i < adev->sdma.num_instances; i++) {
 720                 f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL);
 721                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 722                                 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
 723                 if (enable && amdgpu_sdma_phase_quantum) {
 724                         WREG32_SDMA(i, mmSDMA0_PHASE0_QUANTUM, phase_quantum);
 725                         WREG32_SDMA(i, mmSDMA0_PHASE1_QUANTUM, phase_quantum);
 726                         WREG32_SDMA(i, mmSDMA0_PHASE2_QUANTUM, phase_quantum);
 727                 }
 728                 WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl);
 729         }
 730
 731 }
 732
 733 /**
 734  * sdma_v4_0_enable - stop the async dma engines
 735  *
 736  * @adev: amdgpu_device pointer
 737  * @enable: enable/disable the DMA MEs.
 738  *
 739  * Halt or unhalt the async dma engines (VEGA10).
 740  */
 741 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable)
 742 {
 743         u32 f32_cntl;
 744         int i;
 745
 746         if (enable == false) {
 747                 sdma_v4_0_gfx_stop(adev);
 748                 sdma_v4_0_rlc_stop(adev);
 749                 if (adev->sdma.has_page_queue)
 750                         sdma_v4_0_page_stop(adev);
 751         }
 752
 753         for (i = 0; i < adev->sdma.num_instances; i++) {
 754                 f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL);
 755                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
 756                 WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl);
 757         }
 758 }
 759
 760 /**
 761  * sdma_v4_0_rb_cntl - get parameters for rb_cntl
 762  */
 763 static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl)
 764 {
 765         /* Set ring buffer size in dwords */
 766         uint32_t rb_bufsz = order_base_2(ring->ring_size / 4);
 767
 768         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 769 #ifdef __BIG_ENDIAN
 770         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 771         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 772                                 RPTR_WRITEBACK_SWAP_ENABLE, 1);
 773 #endif
 774         return rb_cntl;
 775 }
 776
 777 /**
 778  * sdma_v4_0_gfx_resume - setup and start the async dma engines
 779  *
 780  * @adev: amdgpu_device pointer
 781  * @i: instance to resume
 782  *
 783  * Set up the gfx DMA ring buffers and enable them (VEGA10).
 784  * Returns 0 for success, error for failure.
 785  */
 786 static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i)
 787 {
 788         struct amdgpu_ring *ring = &adev->sdma.instance[i].ring;
 789         u32 rb_cntl, ib_cntl, wptr_poll_cntl;
 790         u32 wb_offset;
 791         u32 doorbell;
 792         u32 doorbell_offset;
 793         u64 wptr_gpu_addr;
 794
 795         wb_offset = (ring->rptr_offs * 4);
 796
 797         rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);
 798         rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl);
 799         WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
 800
 801         /* Initialize the ring buffer's read and write pointers */
 802         WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR, 0);
 803         WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_HI, 0);
 804         WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0);
 805         WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_HI, 0);
 806
 807         /* set the wb address whether it's enabled or not */
 808         WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI,
 809                upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 810         WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO,
 811                lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 812
 813         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 814                                 RPTR_WRITEBACK_ENABLE, 1);
 815
 816         WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE, ring->gpu_addr >> 8);
 817         WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE_HI, ring->gpu_addr >> 40);
 818
 819         ring->wptr = 0;
 820
 821         /* before programing wptr to a less value, need set minor_ptr_update first */
 822         WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 1);
 823
 824         doorbell = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL);
 825         doorbell_offset = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET);
 826
 827         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE,
 828                                  ring->use_doorbell);
 829         doorbell_offset = REG_SET_FIELD(doorbell_offset,
 830                                         SDMA0_GFX_DOORBELL_OFFSET,
 831                                         OFFSET, ring->doorbell_index);
 832         WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL, doorbell);
 833         WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET, doorbell_offset);
 834         adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
 835                                               ring->doorbell_index);
 836
 837         sdma_v4_0_ring_set_wptr(ring);
 838
 839         /* set minor_ptr_update to 0 after wptr programed */
 840         WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 0);
 841
 842         /* setup the wptr shadow polling */
 843         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 844         WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO,
 845                     lower_32_bits(wptr_gpu_addr));
 846         WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI,
 847                     upper_32_bits(wptr_gpu_addr));
 848         wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL);
 849         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 850                                        SDMA0_GFX_RB_WPTR_POLL_CNTL,
 851                                        F32_POLL_ENABLE, amdgpu_sriov_vf(adev));
 852         WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
 853
 854         /* enable DMA RB */
 855         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 856         WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
 857
 858         ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL);
 859         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 860 #ifdef __BIG_ENDIAN
 861         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 862 #endif
 863         /* enable DMA IBs */
 864         WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);
 865
 866         ring->ready = true;
 867 }
 868
 869 /**
 870  * sdma_v4_0_page_resume - setup and start the async dma engines
 871  *
 872  * @adev: amdgpu_device pointer
 873  * @i: instance to resume
 874  *
 875  * Set up the page DMA ring buffers and enable them (VEGA10).
 876  * Returns 0 for success, error for failure.
 877  */
 878 static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i)
 879 {
 880         struct amdgpu_ring *ring = &adev->sdma.instance[i].page;
 881         u32 rb_cntl, ib_cntl, wptr_poll_cntl;
 882         u32 wb_offset;
 883         u32 doorbell;
 884         u32 doorbell_offset;
 885         u64 wptr_gpu_addr;
 886
 887         wb_offset = (ring->rptr_offs * 4);
 888
 889         rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL);
 890         rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl);
 891         WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
 892
 893         /* Initialize the ring buffer's read and write pointers */
 894         WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR, 0);
 895         WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_HI, 0);
 896         WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR, 0);
 897         WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_HI, 0);
 898
 899         /* set the wb address whether it's enabled or not */
 900         WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_HI,
 901                upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 902         WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_LO,
 903                lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 904
 905         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL,
 906                                 RPTR_WRITEBACK_ENABLE, 1);
 907
 908         WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE, ring->gpu_addr >> 8);
 909         WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE_HI, ring->gpu_addr >> 40);
 910
 911         ring->wptr = 0;
 912
 913         /* before programing wptr to a less value, need set minor_ptr_update first */
 914         WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 1);
 915
 916         doorbell = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL);
 917         doorbell_offset = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET);
 918
 919         doorbell = REG_SET_FIELD(doorbell, SDMA0_PAGE_DOORBELL, ENABLE,
 920                                  ring->use_doorbell);
 921         doorbell_offset = REG_SET_FIELD(doorbell_offset,
 922                                         SDMA0_PAGE_DOORBELL_OFFSET,
 923                                         OFFSET, ring->doorbell_index);
 924         WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL, doorbell);
 925         WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset);
 926         /* TODO: enable doorbell support */
 927         /*adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
 928                                               ring->doorbell_index);*/
 929
 930         sdma_v4_0_ring_set_wptr(ring);
 931
 932         /* set minor_ptr_update to 0 after wptr programed */
 933         WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 0);
 934
 935         /* setup the wptr shadow polling */
 936         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 937         WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO,
 938                     lower_32_bits(wptr_gpu_addr));
 939         WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI,
 940                     upper_32_bits(wptr_gpu_addr));
 941         wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL);
 942         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 943                                        SDMA0_PAGE_RB_WPTR_POLL_CNTL,
 944                                        F32_POLL_ENABLE, amdgpu_sriov_vf(adev));
 945         WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
 946
 947         /* enable DMA RB */
 948         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, RB_ENABLE, 1);
 949         WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
 950
 951         ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL);
 952         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_ENABLE, 1);
 953 #ifdef __BIG_ENDIAN
 954         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1);
 955 #endif
 956         /* enable DMA IBs */
 957         WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl);
 958
 959         ring->ready = true;
 960 }
 961
 962 static void
 963 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable)
 964 {
 965         uint32_t def, data;
 966
 967         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) {
 968                 /* enable idle interrupt */
 969                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
 970                 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
 971
 972                 if (data != def)
 973                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
 974         } else {
 975                 /* disable idle interrupt */
 976                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
 977                 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
 978                 if (data != def)
 979                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
 980         }
 981 }
 982
 983 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev)
 984 {
 985         uint32_t def, data;
 986
 987         /* Enable HW based PG. */
 988         def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
 989         data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK;
 990         if (data != def)
 991                 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
 992
 993         /* enable interrupt */
 994         def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
 995         data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
 996         if (data != def)
 997                 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
 998
 999         /* Configure hold time to filter in-valid power on/off request. Use default right now */
1000         def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1001         data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK;
1002         data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK);
1003         /* Configure switch time for hysteresis purpose. Use default right now */
1004         data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK;
1005         data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK);
1006         if(data != def)
1007                 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1008 }
1009
1010 static void sdma_v4_0_init_pg(struct amdgpu_device *adev)
1011 {
1012         if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA))
1013                 return;
1014
1015         switch (adev->asic_type) {
1016         case CHIP_RAVEN:
1017                 sdma_v4_1_init_power_gating(adev);
1018                 sdma_v4_1_update_power_gating(adev, true);
1019                 break;
1020         default:
1021                 break;
1022         }
1023 }
1024
1025 /**
1026  * sdma_v4_0_rlc_resume - setup and start the async dma engines
1027  *
1028  * @adev: amdgpu_device pointer
1029  *
1030  * Set up the compute DMA queues and enable them (VEGA10).
1031  * Returns 0 for success, error for failure.
1032  */
1033 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev)
1034 {
1035         sdma_v4_0_init_pg(adev);
1036
1037         return 0;
1038 }
1039
1040 /**
1041  * sdma_v4_0_load_microcode - load the sDMA ME ucode
1042  *
1043  * @adev: amdgpu_device pointer
1044  *
1045  * Loads the sDMA0/1 ucode.
1046  * Returns 0 for success, -EINVAL if the ucode is not available.
1047  */
1048 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev)
1049 {
1050         const struct sdma_firmware_header_v1_0 *hdr;
1051         const __le32 *fw_data;
1052         u32 fw_size;
1053         int i, j;
1054
1055         /* halt the MEs */
1056         sdma_v4_0_enable(adev, false);
1057
1058         for (i = 0; i < adev->sdma.num_instances; i++) {
1059                 if (!adev->sdma.instance[i].fw)
1060                         return -EINVAL;
1061
1062                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
1063                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
1064                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1065
1066                 fw_data = (const __le32 *)
1067                         (adev->sdma.instance[i].fw->data +
1068                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1069
1070                 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 0);
1071
1072                 for (j = 0; j < fw_size; j++)
1073                         WREG32_SDMA(i, mmSDMA0_UCODE_DATA,
1074                                     le32_to_cpup(fw_data++));
1075
1076                 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR,
1077                             adev->sdma.instance[i].fw_version);
1078         }
1079
1080         return 0;
1081 }
1082
1083 /**
1084  * sdma_v4_0_start - setup and start the async dma engines
1085  *
1086  * @adev: amdgpu_device pointer
1087  *
1088  * Set up the DMA engines and enable them (VEGA10).
1089  * Returns 0 for success, error for failure.
1090  */
1091 static int sdma_v4_0_start(struct amdgpu_device *adev)
1092 {
1093         struct amdgpu_ring *ring;
1094         int i, r;
1095
1096         if (amdgpu_sriov_vf(adev)) {
1097                 sdma_v4_0_ctx_switch_enable(adev, false);
1098                 sdma_v4_0_enable(adev, false);
1099         } else {
1100
1101                 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1102                         r = sdma_v4_0_load_microcode(adev);
1103                         if (r)
1104                                 return r;
1105                 }
1106
1107                 /* unhalt the MEs */
1108                 sdma_v4_0_enable(adev, true);
1109                 /* enable sdma ring preemption */
1110                 sdma_v4_0_ctx_switch_enable(adev, true);
1111         }
1112
1113         /* start the gfx rings and rlc compute queues */
1114         for (i = 0; i < adev->sdma.num_instances; i++) {
1115                 uint32_t temp;
1116
1117                 WREG32_SDMA(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL, 0);
1118                 sdma_v4_0_gfx_resume(adev, i);
1119                 if (adev->sdma.has_page_queue)
1120                         sdma_v4_0_page_resume(adev, i);
1121
1122                 /* set utc l1 enable flag always to 1 */
1123                 temp = RREG32_SDMA(i, mmSDMA0_CNTL);
1124                 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
1125                 WREG32_SDMA(i, mmSDMA0_CNTL, temp);
1126
1127                 if (!amdgpu_sriov_vf(adev)) {
1128                         /* unhalt engine */
1129                         temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL);
1130                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
1131                         WREG32_SDMA(i, mmSDMA0_F32_CNTL, temp);
1132                 }
1133         }
1134
1135         if (amdgpu_sriov_vf(adev)) {
1136                 sdma_v4_0_ctx_switch_enable(adev, true);
1137                 sdma_v4_0_enable(adev, true);
1138         } else {
1139                 r = sdma_v4_0_rlc_resume(adev);
1140                 if (r)
1141                         return r;
1142         }
1143
1144         for (i = 0; i < adev->sdma.num_instances; i++) {
1145                 ring = &adev->sdma.instance[i].ring;
1146
1147                 r = amdgpu_ring_test_ring(ring);
1148                 if (r) {
1149                         ring->ready = false;
1150                         return r;
1151                 }
1152
1153                 if (adev->sdma.has_page_queue) {
1154                         struct amdgpu_ring *page = &adev->sdma.instance[i].page;
1155
1156                         r = amdgpu_ring_test_ring(page);
1157                         if (r) {
1158                                 page->ready = false;
1159                                 return r;
1160                         }
1161                 }
1162
1163                 if (adev->mman.buffer_funcs_ring == ring)
1164                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
1165         }
1166
1167         return r;
1168 }
1169
1170 /**
1171  * sdma_v4_0_ring_test_ring - simple async dma engine test
1172  *
1173  * @ring: amdgpu_ring structure holding ring information
1174  *
1175  * Test the DMA engine by writing using it to write an
1176  * value to memory. (VEGA10).
1177  * Returns 0 for success, error for failure.
1178  */
1179 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring)
1180 {
1181         struct amdgpu_device *adev = ring->adev;
1182         unsigned i;
1183         unsigned index;
1184         int r;
1185         u32 tmp;
1186         u64 gpu_addr;
1187
1188         r = amdgpu_device_wb_get(adev, &index);
1189         if (r) {
1190                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
1191                 return r;
1192         }
1193
1194         gpu_addr = adev->wb.gpu_addr + (index * 4);
1195         tmp = 0xCAFEDEAD;
1196         adev->wb.wb[index] = cpu_to_le32(tmp);
1197
1198         r = amdgpu_ring_alloc(ring, 5);
1199         if (r) {
1200                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
1201                 amdgpu_device_wb_free(adev, index);
1202                 return r;
1203         }
1204
1205         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1206                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
1207         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
1208         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
1209         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
1210         amdgpu_ring_write(ring, 0xDEADBEEF);
1211         amdgpu_ring_commit(ring);
1212
1213         for (i = 0; i < adev->usec_timeout; i++) {
1214                 tmp = le32_to_cpu(adev->wb.wb[index]);
1215                 if (tmp == 0xDEADBEEF)
1216                         break;
1217                 DRM_UDELAY(1);
1218         }
1219
1220         if (i < adev->usec_timeout) {
1221                 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i);
1222         } else {
1223                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
1224                           ring->idx, tmp);
1225                 r = -EINVAL;
1226         }
1227         amdgpu_device_wb_free(adev, index);
1228
1229         return r;
1230 }
1231
1232 /**
1233  * sdma_v4_0_ring_test_ib - test an IB on the DMA engine
1234  *
1235  * @ring: amdgpu_ring structure holding ring information
1236  *
1237  * Test a simple IB in the DMA ring (VEGA10).
1238  * Returns 0 on success, error on failure.
1239  */
1240 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1241 {
1242         struct amdgpu_device *adev = ring->adev;
1243         struct amdgpu_ib ib;
1244         struct dma_fence *f = NULL;
1245         unsigned index;
1246         long r;
1247         u32 tmp = 0;
1248         u64 gpu_addr;
1249
1250         r = amdgpu_device_wb_get(adev, &index);
1251         if (r) {
1252                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
1253                 return r;
1254         }
1255
1256         gpu_addr = adev->wb.gpu_addr + (index * 4);
1257         tmp = 0xCAFEDEAD;
1258         adev->wb.wb[index] = cpu_to_le32(tmp);
1259         memset(&ib, 0, sizeof(ib));
1260         r = amdgpu_ib_get(adev, NULL, 256, &ib);
1261         if (r) {
1262                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1263                 goto err0;
1264         }
1265
1266         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1267                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1268         ib.ptr[1] = lower_32_bits(gpu_addr);
1269         ib.ptr[2] = upper_32_bits(gpu_addr);
1270         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1271         ib.ptr[4] = 0xDEADBEEF;
1272         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1273         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1274         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1275         ib.length_dw = 8;
1276
1277         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1278         if (r)
1279                 goto err1;
1280
1281         r = dma_fence_wait_timeout(f, false, timeout);
1282         if (r == 0) {
1283                 DRM_ERROR("amdgpu: IB test timed out\n");
1284                 r = -ETIMEDOUT;
1285                 goto err1;
1286         } else if (r < 0) {
1287                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1288                 goto err1;
1289         }
1290         tmp = le32_to_cpu(adev->wb.wb[index]);
1291         if (tmp == 0xDEADBEEF) {
1292                 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
1293                 r = 0;
1294         } else {
1295                 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
1296                 r = -EINVAL;
1297         }
1298 err1:
1299         amdgpu_ib_free(adev, &ib, NULL);
1300         dma_fence_put(f);
1301 err0:
1302         amdgpu_device_wb_free(adev, index);
1303         return r;
1304 }
1305
1306
1307 /**
1308  * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART
1309  *
1310  * @ib: indirect buffer to fill with commands
1311  * @pe: addr of the page entry
1312  * @src: src addr to copy from
1313  * @count: number of page entries to update
1314  *
1315  * Update PTEs by copying them from the GART using sDMA (VEGA10).
1316  */
1317 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib,
1318                                   uint64_t pe, uint64_t src,
1319                                   unsigned count)
1320 {
1321         unsigned bytes = count * 8;
1322
1323         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1324                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1325         ib->ptr[ib->length_dw++] = bytes - 1;
1326         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1327         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1328         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1329         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1330         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1331
1332 }
1333
1334 /**
1335  * sdma_v4_0_vm_write_pte - update PTEs by writing them manually
1336  *
1337  * @ib: indirect buffer to fill with commands
1338  * @pe: addr of the page entry
1339  * @addr: dst addr to write into pe
1340  * @count: number of page entries to update
1341  * @incr: increase next addr by incr bytes
1342  * @flags: access flags
1343  *
1344  * Update PTEs by writing them manually using sDMA (VEGA10).
1345  */
1346 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1347                                    uint64_t value, unsigned count,
1348                                    uint32_t incr)
1349 {
1350         unsigned ndw = count * 2;
1351
1352         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1353                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1354         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1355         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1356         ib->ptr[ib->length_dw++] = ndw - 1;
1357         for (; ndw > 0; ndw -= 2) {
1358                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1359                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1360                 value += incr;
1361         }
1362 }
1363
1364 /**
1365  * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA
1366  *
1367  * @ib: indirect buffer to fill with commands
1368  * @pe: addr of the page entry
1369  * @addr: dst addr to write into pe
1370  * @count: number of page entries to update
1371  * @incr: increase next addr by incr bytes
1372  * @flags: access flags
1373  *
1374  * Update the page tables using sDMA (VEGA10).
1375  */
1376 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1377                                      uint64_t pe,
1378                                      uint64_t addr, unsigned count,
1379                                      uint32_t incr, uint64_t flags)
1380 {
1381         /* for physically contiguous pages (vram) */
1382         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1383         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1384         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1385         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1386         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1387         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1388         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1389         ib->ptr[ib->length_dw++] = incr; /* increment size */
1390         ib->ptr[ib->length_dw++] = 0;
1391         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1392 }
1393
1394 /**
1395  * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw
1396  *
1397  * @ib: indirect buffer to fill with padding
1398  *
1399  */
1400 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1401 {
1402         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
1403         u32 pad_count;
1404         int i;
1405
1406         pad_count = (8 - (ib->length_dw & 0x7)) % 8;
1407         for (i = 0; i < pad_count; i++)
1408                 if (sdma && sdma->burst_nop && (i == 0))
1409                         ib->ptr[ib->length_dw++] =
1410                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1411                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1412                 else
1413                         ib->ptr[ib->length_dw++] =
1414                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1415 }
1416
1417
1418 /**
1419  * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline
1420  *
1421  * @ring: amdgpu_ring pointer
1422  *
1423  * Make sure all previous operations are completed (CIK).
1424  */
1425 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1426 {
1427         uint32_t seq = ring->fence_drv.sync_seq;
1428         uint64_t addr = ring->fence_drv.gpu_addr;
1429
1430         /* wait for idle */
1431         sdma_v4_0_wait_reg_mem(ring, 1, 0,
1432                                addr & 0xfffffffc,
1433                                upper_32_bits(addr) & 0xffffffff,
1434                                seq, 0xffffffff, 4);
1435 }
1436
1437
1438 /**
1439  * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA
1440  *
1441  * @ring: amdgpu_ring pointer
1442  * @vm: amdgpu_vm pointer
1443  *
1444  * Update the page table base and flush the VM TLB
1445  * using sDMA (VEGA10).
1446  */
1447 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1448                                          unsigned vmid, uint64_t pd_addr)
1449 {
1450         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1451 }
1452
1453 static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring,
1454                                      uint32_t reg, uint32_t val)
1455 {
1456         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1457                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1458         amdgpu_ring_write(ring, reg);
1459         amdgpu_ring_write(ring, val);
1460 }
1461
1462 static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1463                                          uint32_t val, uint32_t mask)
1464 {
1465         sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10);
1466 }
1467
1468 static int sdma_v4_0_early_init(void *handle)
1469 {
1470         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1471
1472         if (adev->asic_type == CHIP_RAVEN) {
1473                 adev->sdma.num_instances = 1;
1474                 adev->sdma.has_page_queue = false;
1475         } else {
1476                 adev->sdma.num_instances = 2;
1477                 if (adev->asic_type != CHIP_VEGA20)
1478                         adev->sdma.has_page_queue = true;
1479         }
1480
1481         sdma_v4_0_set_ring_funcs(adev);
1482         sdma_v4_0_set_buffer_funcs(adev);
1483         sdma_v4_0_set_vm_pte_funcs(adev);
1484         sdma_v4_0_set_irq_funcs(adev);
1485
1486         return 0;
1487 }
1488
1489
1490 static int sdma_v4_0_sw_init(void *handle)
1491 {
1492         struct amdgpu_ring *ring;
1493         int r, i;
1494         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1495
1496         /* SDMA trap event */
1497         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, SDMA0_4_0__SRCID__SDMA_TRAP,
1498                               &adev->sdma.trap_irq);
1499         if (r)
1500                 return r;
1501
1502         /* SDMA trap event */
1503         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, SDMA1_4_0__SRCID__SDMA_TRAP,
1504                               &adev->sdma.trap_irq);
1505         if (r)
1506                 return r;
1507
1508         r = sdma_v4_0_init_microcode(adev);
1509         if (r) {
1510                 DRM_ERROR("Failed to load sdma firmware!\n");
1511                 return r;
1512         }
1513
1514         for (i = 0; i < adev->sdma.num_instances; i++) {
1515                 ring = &adev->sdma.instance[i].ring;
1516                 ring->ring_obj = NULL;
1517                 ring->use_doorbell = true;
1518
1519                 DRM_INFO("use_doorbell being set to: [%s]\n",
1520                                 ring->use_doorbell?"true":"false");
1521
1522                 if (adev->asic_type == CHIP_VEGA10)
1523                         ring->doorbell_index = (i == 0) ?
1524                                 (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 << 1) //get DWORD offset
1525                                 : (AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 << 1); // get DWORD offset
1526                 else
1527                         ring->doorbell_index = (i == 0) ?
1528                                 (AMDGPU_DOORBELL64_sDMA_ENGINE0 << 1) //get DWORD offset
1529                                 : (AMDGPU_DOORBELL64_sDMA_ENGINE1 << 1); // get DWORD offset
1530
1531
1532                 sprintf(ring->name, "sdma%d", i);
1533                 r = amdgpu_ring_init(adev, ring, 1024,
1534                                      &adev->sdma.trap_irq,
1535                                      (i == 0) ?
1536                                      AMDGPU_SDMA_IRQ_TRAP0 :
1537                                      AMDGPU_SDMA_IRQ_TRAP1);
1538                 if (r)
1539                         return r;
1540
1541                 if (adev->sdma.has_page_queue) {
1542                         ring = &adev->sdma.instance[i].page;
1543                         ring->ring_obj = NULL;
1544                         ring->use_doorbell = false;
1545
1546                         sprintf(ring->name, "page%d", i);
1547                         r = amdgpu_ring_init(adev, ring, 1024,
1548                                              &adev->sdma.trap_irq,
1549                                              (i == 0) ?
1550                                              AMDGPU_SDMA_IRQ_TRAP0 :
1551                                              AMDGPU_SDMA_IRQ_TRAP1);
1552                         if (r)
1553                                 return r;
1554                 }
1555         }
1556
1557         return r;
1558 }
1559
1560 static int sdma_v4_0_sw_fini(void *handle)
1561 {
1562         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1563         int i;
1564
1565         for (i = 0; i < adev->sdma.num_instances; i++) {
1566                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1567                 if (adev->sdma.has_page_queue)
1568                         amdgpu_ring_fini(&adev->sdma.instance[i].page);
1569         }
1570
1571         for (i = 0; i < adev->sdma.num_instances; i++) {
1572                 release_firmware(adev->sdma.instance[i].fw);
1573                 adev->sdma.instance[i].fw = NULL;
1574         }
1575
1576         return 0;
1577 }
1578
1579 static int sdma_v4_0_hw_init(void *handle)
1580 {
1581         int r;
1582         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1583
1584         if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs &&
1585                         adev->powerplay.pp_funcs->set_powergating_by_smu)
1586                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false);
1587
1588         sdma_v4_0_init_golden_registers(adev);
1589
1590         r = sdma_v4_0_start(adev);
1591
1592         return r;
1593 }
1594
1595 static int sdma_v4_0_hw_fini(void *handle)
1596 {
1597         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1598
1599         if (amdgpu_sriov_vf(adev))
1600                 return 0;
1601
1602         sdma_v4_0_ctx_switch_enable(adev, false);
1603         sdma_v4_0_enable(adev, false);
1604
1605         if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs
1606                         && adev->powerplay.pp_funcs->set_powergating_by_smu)
1607                 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true);
1608
1609         return 0;
1610 }
1611
1612 static int sdma_v4_0_suspend(void *handle)
1613 {
1614         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1615
1616         return sdma_v4_0_hw_fini(adev);
1617 }
1618
1619 static int sdma_v4_0_resume(void *handle)
1620 {
1621         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1622
1623         return sdma_v4_0_hw_init(adev);
1624 }
1625
1626 static bool sdma_v4_0_is_idle(void *handle)
1627 {
1628         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1629         u32 i;
1630
1631         for (i = 0; i < adev->sdma.num_instances; i++) {
1632                 u32 tmp = RREG32_SDMA(i, mmSDMA0_STATUS_REG);
1633
1634                 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1635                         return false;
1636         }
1637
1638         return true;
1639 }
1640
1641 static int sdma_v4_0_wait_for_idle(void *handle)
1642 {
1643         unsigned i;
1644         u32 sdma0, sdma1;
1645         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1646
1647         for (i = 0; i < adev->usec_timeout; i++) {
1648                 sdma0 = RREG32_SDMA(0, mmSDMA0_STATUS_REG);
1649                 sdma1 = RREG32_SDMA(1, mmSDMA0_STATUS_REG);
1650
1651                 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1652                         return 0;
1653                 udelay(1);
1654         }
1655         return -ETIMEDOUT;
1656 }
1657
1658 static int sdma_v4_0_soft_reset(void *handle)
1659 {
1660         /* todo */
1661
1662         return 0;
1663 }
1664
1665 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev,
1666                                         struct amdgpu_irq_src *source,
1667                                         unsigned type,
1668                                         enum amdgpu_interrupt_state state)
1669 {
1670         unsigned int instance = (type == AMDGPU_SDMA_IRQ_TRAP0) ? 0 : 1;
1671         u32 sdma_cntl;
1672
1673         sdma_cntl = RREG32_SDMA(instance, mmSDMA0_CNTL);
1674         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1675                        state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1676         WREG32_SDMA(instance, mmSDMA0_CNTL, sdma_cntl);
1677
1678         return 0;
1679 }
1680
1681 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
1682                                       struct amdgpu_irq_src *source,
1683                                       struct amdgpu_iv_entry *entry)
1684 {
1685         uint32_t instance;
1686
1687         DRM_DEBUG("IH: SDMA trap\n");
1688         switch (entry->client_id) {
1689         case SOC15_IH_CLIENTID_SDMA0:
1690                 instance = 0;
1691                 break;
1692         case SOC15_IH_CLIENTID_SDMA1:
1693                 instance = 1;
1694                 break;
1695         default:
1696                 return 0;
1697         }
1698
1699         switch (entry->ring_id) {
1700         case 0:
1701                 amdgpu_fence_process(&adev->sdma.instance[instance].ring);
1702                 break;
1703         case 1:
1704                 /* XXX compute */
1705                 break;
1706         case 2:
1707                 /* XXX compute */
1708                 break;
1709         case 3:
1710                 amdgpu_fence_process(&adev->sdma.instance[instance].page);
1711                 break;
1712         }
1713         return 0;
1714 }
1715
1716 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1717                                               struct amdgpu_irq_src *source,
1718                                               struct amdgpu_iv_entry *entry)
1719 {
1720         int instance;
1721
1722         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1723
1724         switch (entry->client_id) {
1725         case SOC15_IH_CLIENTID_SDMA0:
1726                 instance = 0;
1727                 break;
1728         case SOC15_IH_CLIENTID_SDMA1:
1729                 instance = 1;
1730                 break;
1731         default:
1732                 return 0;
1733         }
1734
1735         switch (entry->ring_id) {
1736         case 0:
1737                 drm_sched_fault(&adev->sdma.instance[instance].ring.sched);
1738                 break;
1739         }
1740         return 0;
1741 }
1742
1743 static void sdma_v4_0_update_medium_grain_clock_gating(
1744                 struct amdgpu_device *adev,
1745                 bool enable)
1746 {
1747         uint32_t data, def;
1748
1749         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1750                 /* enable sdma0 clock gating */
1751                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
1752                 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1753                           SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1754                           SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1755                           SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1756                           SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1757                           SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1758                           SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1759                           SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1760                 if (def != data)
1761                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data);
1762
1763                 if (adev->sdma.num_instances > 1) {
1764                         def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL));
1765                         data &= ~(SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1766                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1767                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1768                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1769                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1770                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1771                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1772                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1773                         if (def != data)
1774                                 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data);
1775                 }
1776         } else {
1777                 /* disable sdma0 clock gating */
1778                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
1779                 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1780                          SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1781                          SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1782                          SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1783                          SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1784                          SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1785                          SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1786                          SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1787
1788                 if (def != data)
1789                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data);
1790
1791                 if (adev->sdma.num_instances > 1) {
1792                         def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL));
1793                         data |= (SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1794                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1795                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1796                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1797                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1798                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1799                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1800                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1801                         if (def != data)
1802                                 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data);
1803                 }
1804         }
1805 }
1806
1807
1808 static void sdma_v4_0_update_medium_grain_light_sleep(
1809                 struct amdgpu_device *adev,
1810                 bool enable)
1811 {
1812         uint32_t data, def;
1813
1814         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1815                 /* 1-not override: enable sdma0 mem light sleep */
1816                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1817                 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1818                 if (def != data)
1819                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1820
1821                 /* 1-not override: enable sdma1 mem light sleep */
1822                 if (adev->sdma.num_instances > 1) {
1823                         def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL));
1824                         data |= SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1825                         if (def != data)
1826                                 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data);
1827                 }
1828         } else {
1829                 /* 0-override:disable sdma0 mem light sleep */
1830                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1831                 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1832                 if (def != data)
1833                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1834
1835                 /* 0-override:disable sdma1 mem light sleep */
1836                 if (adev->sdma.num_instances > 1) {
1837                         def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL));
1838                         data &= ~SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1839                         if (def != data)
1840                                 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data);
1841                 }
1842         }
1843 }
1844
1845 static int sdma_v4_0_set_clockgating_state(void *handle,
1846                                           enum amd_clockgating_state state)
1847 {
1848         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1849
1850         if (amdgpu_sriov_vf(adev))
1851                 return 0;
1852
1853         switch (adev->asic_type) {
1854         case CHIP_VEGA10:
1855         case CHIP_VEGA12:
1856         case CHIP_VEGA20:
1857         case CHIP_RAVEN:
1858                 sdma_v4_0_update_medium_grain_clock_gating(adev,
1859                                 state == AMD_CG_STATE_GATE ? true : false);
1860                 sdma_v4_0_update_medium_grain_light_sleep(adev,
1861                                 state == AMD_CG_STATE_GATE ? true : false);
1862                 break;
1863         default:
1864                 break;
1865         }
1866         return 0;
1867 }
1868
1869 static int sdma_v4_0_set_powergating_state(void *handle,
1870                                           enum amd_powergating_state state)
1871 {
1872         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1873
1874         switch (adev->asic_type) {
1875         case CHIP_RAVEN:
1876                 sdma_v4_1_update_power_gating(adev,
1877                                 state == AMD_PG_STATE_GATE ? true : false);
1878                 break;
1879         default:
1880                 break;
1881         }
1882
1883         return 0;
1884 }
1885
1886 static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags)
1887 {
1888         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1889         int data;
1890
1891         if (amdgpu_sriov_vf(adev))
1892                 *flags = 0;
1893
1894         /* AMD_CG_SUPPORT_SDMA_MGCG */
1895         data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
1896         if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
1897                 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1898
1899         /* AMD_CG_SUPPORT_SDMA_LS */
1900         data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1901         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1902                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1903 }
1904
1905 const struct amd_ip_funcs sdma_v4_0_ip_funcs = {
1906         .name = "sdma_v4_0",
1907         .early_init = sdma_v4_0_early_init,
1908         .late_init = NULL,
1909         .sw_init = sdma_v4_0_sw_init,
1910         .sw_fini = sdma_v4_0_sw_fini,
1911         .hw_init = sdma_v4_0_hw_init,
1912         .hw_fini = sdma_v4_0_hw_fini,
1913         .suspend = sdma_v4_0_suspend,
1914         .resume = sdma_v4_0_resume,
1915         .is_idle = sdma_v4_0_is_idle,
1916         .wait_for_idle = sdma_v4_0_wait_for_idle,
1917         .soft_reset = sdma_v4_0_soft_reset,
1918         .set_clockgating_state = sdma_v4_0_set_clockgating_state,
1919         .set_powergating_state = sdma_v4_0_set_powergating_state,
1920         .get_clockgating_state = sdma_v4_0_get_clockgating_state,
1921 };
1922
1923 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
1924         .type = AMDGPU_RING_TYPE_SDMA,
1925         .align_mask = 0xf,
1926         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1927         .support_64bit_ptrs = true,
1928         .vmhub = AMDGPU_MMHUB,
1929         .get_rptr = sdma_v4_0_ring_get_rptr,
1930         .get_wptr = sdma_v4_0_ring_get_wptr,
1931         .set_wptr = sdma_v4_0_ring_set_wptr,
1932         .emit_frame_size =
1933                 6 + /* sdma_v4_0_ring_emit_hdp_flush */
1934                 3 + /* hdp invalidate */
1935                 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
1936                 /* sdma_v4_0_ring_emit_vm_flush */
1937                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1938                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1939                 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
1940         .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
1941         .emit_ib = sdma_v4_0_ring_emit_ib,
1942         .emit_fence = sdma_v4_0_ring_emit_fence,
1943         .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
1944         .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
1945         .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
1946         .test_ring = sdma_v4_0_ring_test_ring,
1947         .test_ib = sdma_v4_0_ring_test_ib,
1948         .insert_nop = sdma_v4_0_ring_insert_nop,
1949         .pad_ib = sdma_v4_0_ring_pad_ib,
1950         .emit_wreg = sdma_v4_0_ring_emit_wreg,
1951         .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
1952         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1953 };
1954
1955 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = {
1956         .type = AMDGPU_RING_TYPE_SDMA,
1957         .align_mask = 0xf,
1958         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1959         .support_64bit_ptrs = true,
1960         .vmhub = AMDGPU_MMHUB,
1961         .get_rptr = sdma_v4_0_ring_get_rptr,
1962         .get_wptr = sdma_v4_0_page_ring_get_wptr,
1963         .set_wptr = sdma_v4_0_page_ring_set_wptr,
1964         .emit_frame_size =
1965                 6 + /* sdma_v4_0_ring_emit_hdp_flush */
1966                 3 + /* hdp invalidate */
1967                 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
1968                 /* sdma_v4_0_ring_emit_vm_flush */
1969                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1970                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1971                 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
1972         .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
1973         .emit_ib = sdma_v4_0_ring_emit_ib,
1974         .emit_fence = sdma_v4_0_ring_emit_fence,
1975         .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
1976         .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
1977         .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
1978         .test_ring = sdma_v4_0_ring_test_ring,
1979         .test_ib = sdma_v4_0_ring_test_ib,
1980         .insert_nop = sdma_v4_0_ring_insert_nop,
1981         .pad_ib = sdma_v4_0_ring_pad_ib,
1982         .emit_wreg = sdma_v4_0_ring_emit_wreg,
1983         .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
1984         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1985 };
1986
1987 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
1988 {
1989         int i;
1990
1991         for (i = 0; i < adev->sdma.num_instances; i++) {
1992                 adev->sdma.instance[i].ring.funcs = &sdma_v4_0_ring_funcs;
1993                 adev->sdma.instance[i].ring.me = i;
1994                 if (adev->sdma.has_page_queue) {
1995                         adev->sdma.instance[i].page.funcs = &sdma_v4_0_page_ring_funcs;
1996                         adev->sdma.instance[i].page.me = i;
1997                 }
1998         }
1999 }
2000
2001 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = {
2002         .set = sdma_v4_0_set_trap_irq_state,
2003         .process = sdma_v4_0_process_trap_irq,
2004 };
2005
2006 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = {
2007         .process = sdma_v4_0_process_illegal_inst_irq,
2008 };
2009
2010 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev)
2011 {
2012         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
2013         adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs;
2014         adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs;
2015 }
2016
2017 /**
2018  * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine
2019  *
2020  * @ring: amdgpu_ring structure holding ring information
2021  * @src_offset: src GPU address
2022  * @dst_offset: dst GPU address
2023  * @byte_count: number of bytes to xfer
2024  *
2025  * Copy GPU buffers using the DMA engine (VEGA10/12).
2026  * Used by the amdgpu ttm implementation to move pages if
2027  * registered as the asic copy callback.
2028  */
2029 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib,
2030                                        uint64_t src_offset,
2031                                        uint64_t dst_offset,
2032                                        uint32_t byte_count)
2033 {
2034         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
2035                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
2036         ib->ptr[ib->length_dw++] = byte_count - 1;
2037         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
2038         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
2039         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
2040         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2041         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2042 }
2043
2044 /**
2045  * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine
2046  *
2047  * @ring: amdgpu_ring structure holding ring information
2048  * @src_data: value to write to buffer
2049  * @dst_offset: dst GPU address
2050  * @byte_count: number of bytes to xfer
2051  *
2052  * Fill GPU buffers using the DMA engine (VEGA10/12).
2053  */
2054 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib,
2055                                        uint32_t src_data,
2056                                        uint64_t dst_offset,
2057                                        uint32_t byte_count)
2058 {
2059         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
2060         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2061         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2062         ib->ptr[ib->length_dw++] = src_data;
2063         ib->ptr[ib->length_dw++] = byte_count - 1;
2064 }
2065
2066 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = {
2067         .copy_max_bytes = 0x400000,
2068         .copy_num_dw = 7,
2069         .emit_copy_buffer = sdma_v4_0_emit_copy_buffer,
2070
2071         .fill_max_bytes = 0x400000,
2072         .fill_num_dw = 5,
2073         .emit_fill_buffer = sdma_v4_0_emit_fill_buffer,
2074 };
2075
2076 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev)
2077 {
2078         adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs;
2079         adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
2080 }
2081
2082 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = {
2083         .copy_pte_num_dw = 7,
2084         .copy_pte = sdma_v4_0_vm_copy_pte,
2085
2086         .write_pte = sdma_v4_0_vm_write_pte,
2087         .set_pte_pde = sdma_v4_0_vm_set_pte_pde,
2088 };
2089
2090 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev)
2091 {
2092         struct drm_gpu_scheduler *sched;
2093         unsigned i;
2094
2095         adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs;
2096         for (i = 0; i < adev->sdma.num_instances; i++) {
2097                 if (adev->sdma.has_page_queue)
2098                         sched = &adev->sdma.instance[i].page.sched;
2099                 else
2100                         sched = &adev->sdma.instance[i].ring.sched;
2101                 adev->vm_manager.vm_pte_rqs[i] =
2102                         &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
2103         }
2104         adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
2105 }
2106
2107 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = {
2108         .type = AMD_IP_BLOCK_TYPE_SDMA,
2109         .major = 4,
2110         .minor = 0,
2111         .rev = 0,
2112         .funcs = &sdma_v4_0_ip_funcs,
2113 };