drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_ucode.h"
  28 #include "amdgpu_trace.h"
  29 #include "vi.h"
  30 #include "vid.h"
  31
  32 #include "oss/oss_2_4_d.h"
  33 #include "oss/oss_2_4_sh_mask.h"
  34
  35 #include "gmc/gmc_7_1_d.h"
  36 #include "gmc/gmc_7_1_sh_mask.h"
  37
  38 #include "gca/gfx_8_0_d.h"
  39 #include "gca/gfx_8_0_enum.h"
  40 #include "gca/gfx_8_0_sh_mask.h"
  41
  42 #include "bif/bif_5_0_d.h"
  43 #include "bif/bif_5_0_sh_mask.h"
  44
  45 #include "iceland_sdma_pkt_open.h"
  46
  47 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev);
  48 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev);
  49 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev);
  50 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev);
  51
  52 MODULE_FIRMWARE("amdgpu/topaz_sdma.bin");
  53 MODULE_FIRMWARE("amdgpu/topaz_sdma1.bin");
  54
  55 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
  56 {
  57         SDMA0_REGISTER_OFFSET,
  58         SDMA1_REGISTER_OFFSET
  59 };
  60
  61 static const u32 golden_settings_iceland_a11[] =
  62 {
  63         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
  64         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
  65         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
  66         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
  67 };
  68
  69 static const u32 iceland_mgcg_cgcg_init[] =
  70 {
  71         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
  72         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
  73 };
  74
  75 /*
  76  * sDMA - System DMA
  77  * Starting with CIK, the GPU has new asynchronous
  78  * DMA engines.  These engines are used for compute
  79  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
  80  * and each one supports 1 ring buffer used for gfx
  81  * and 2 queues used for compute.
  82  *
  83  * The programming model is very similar to the CP
  84  * (ring buffer, IBs, etc.), but sDMA has it's own
  85  * packet format that is different from the PM4 format
  86  * used by the CP. sDMA supports copying data, writing
  87  * embedded data, solid fills, and a number of other
  88  * things.  It also has support for tiling/detiling of
  89  * buffers.
  90  */
  91
  92 static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev)
  93 {
  94         switch (adev->asic_type) {
  95         case CHIP_TOPAZ:
  96                 amdgpu_program_register_sequence(adev,
  97                                                  iceland_mgcg_cgcg_init,
  98                                                  (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
  99                 amdgpu_program_register_sequence(adev,
 100                                                  golden_settings_iceland_a11,
 101                                                  (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
 102                 break;
 103         default:
 104                 break;
 105         }
 106 }
 107
 108 static void sdma_v2_4_free_microcode(struct amdgpu_device *adev)
 109 {
 110         int i;
 111         for (i = 0; i < adev->sdma.num_instances; i++) {
 112                 release_firmware(adev->sdma.instance[i].fw);
 113                 adev->sdma.instance[i].fw = NULL;
 114         }
 115 }
 116
 117 /**
 118  * sdma_v2_4_init_microcode - load ucode images from disk
 119  *
 120  * @adev: amdgpu_device pointer
 121  *
 122  * Use the firmware interface to load the ucode images into
 123  * the driver (not loaded into hw).
 124  * Returns 0 on success, error on failure.
 125  */
 126 static int sdma_v2_4_init_microcode(struct amdgpu_device *adev)
 127 {
 128         const char *chip_name;
 129         char fw_name[30];
 130         int err = 0, i;
 131         struct amdgpu_firmware_info *info = NULL;
 132         const struct common_firmware_header *header = NULL;
 133         const struct sdma_firmware_header_v1_0 *hdr;
 134
 135         DRM_DEBUG("\n");
 136
 137         switch (adev->asic_type) {
 138         case CHIP_TOPAZ:
 139                 chip_name = "topaz";
 140                 break;
 141         default: BUG();
 142         }
 143
 144         for (i = 0; i < adev->sdma.num_instances; i++) {
 145                 if (i == 0)
 146                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 147                 else
 148                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
 149                 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 150                 if (err)
 151                         goto out;
 152                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 153                 if (err)
 154                         goto out;
 155                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 156                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 157                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 158                 if (adev->sdma.instance[i].feature_version >= 20)
 159                         adev->sdma.instance[i].burst_nop = true;
 160
 161                 if (adev->firmware.smu_load) {
 162                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 163                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 164                         info->fw = adev->sdma.instance[i].fw;
 165                         header = (const struct common_firmware_header *)info->fw->data;
 166                         adev->firmware.fw_size +=
 167                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 168                 }
 169         }
 170
 171 out:
 172         if (err) {
 173                 printk(KERN_ERR
 174                        "sdma_v2_4: Failed to load firmware \"%s\"\n",
 175                        fw_name);
 176                 for (i = 0; i < adev->sdma.num_instances; i++) {
 177                         release_firmware(adev->sdma.instance[i].fw);
 178                         adev->sdma.instance[i].fw = NULL;
 179                 }
 180         }
 181         return err;
 182 }
 183
 184 /**
 185  * sdma_v2_4_ring_get_rptr - get the current read pointer
 186  *
 187  * @ring: amdgpu ring pointer
 188  *
 189  * Get the current rptr from the hardware (VI+).
 190  */
 191 static uint32_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring)
 192 {
 193         u32 rptr;
 194
 195         /* XXX check if swapping is necessary on BE */
 196         rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2;
 197
 198         return rptr;
 199 }
 200
 201 /**
 202  * sdma_v2_4_ring_get_wptr - get the current write pointer
 203  *
 204  * @ring: amdgpu ring pointer
 205  *
 206  * Get the current wptr from the hardware (VI+).
 207  */
 208 static uint32_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)
 209 {
 210         struct amdgpu_device *adev = ring->adev;
 211         int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
 212         u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
 213
 214         return wptr;
 215 }
 216
 217 /**
 218  * sdma_v2_4_ring_set_wptr - commit the write pointer
 219  *
 220  * @ring: amdgpu ring pointer
 221  *
 222  * Write the wptr back to the hardware (VI+).
 223  */
 224 static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring)
 225 {
 226         struct amdgpu_device *adev = ring->adev;
 227         int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
 228
 229         WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2);
 230 }
 231
 232 static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 233 {
 234         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 235         int i;
 236
 237         for (i = 0; i < count; i++)
 238                 if (sdma && sdma->burst_nop && (i == 0))
 239                         amdgpu_ring_write(ring, ring->nop |
 240                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 241                 else
 242                         amdgpu_ring_write(ring, ring->nop);
 243 }
 244
 245 /**
 246  * sdma_v2_4_ring_emit_ib - Schedule an IB on the DMA engine
 247  *
 248  * @ring: amdgpu ring pointer
 249  * @ib: IB object to schedule
 250  *
 251  * Schedule an IB in the DMA ring (VI).
 252  */
 253 static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring,
 254                                    struct amdgpu_ib *ib,
 255                                    unsigned vm_id, bool ctx_switch)
 256 {
 257         u32 vmid = vm_id & 0xf;
 258
 259         /* IB packet must end on a 8 DW boundary */
 260         sdma_v2_4_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8);
 261
 262         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 263                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
 264         /* base must be 32 byte aligned */
 265         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 266         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 267         amdgpu_ring_write(ring, ib->length_dw);
 268         amdgpu_ring_write(ring, 0);
 269         amdgpu_ring_write(ring, 0);
 270
 271 }
 272
 273 /**
 274  * sdma_v2_4_hdp_flush_ring_emit - emit an hdp flush on the DMA ring
 275  *
 276  * @ring: amdgpu ring pointer
 277  *
 278  * Emit an hdp flush packet on the requested DMA ring.
 279  */
 280 static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 281 {
 282         u32 ref_and_mask = 0;
 283
 284         if (ring == &ring->adev->sdma.instance[0].ring)
 285                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
 286         else
 287                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
 288
 289         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 290                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 291                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 292         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
 293         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
 294         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 295         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 296         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 297                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 298 }
 299
 300 static void sdma_v2_4_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
 301 {
 302         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 303                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 304         amdgpu_ring_write(ring, mmHDP_DEBUG0);
 305         amdgpu_ring_write(ring, 1);
 306 }
 307 /**
 308  * sdma_v2_4_ring_emit_fence - emit a fence on the DMA ring
 309  *
 310  * @ring: amdgpu ring pointer
 311  * @fence: amdgpu fence object
 312  *
 313  * Add a DMA fence packet to the ring to write
 314  * the fence seq number and DMA trap packet to generate
 315  * an interrupt if needed (VI).
 316  */
 317 static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 318                                       unsigned flags)
 319 {
 320         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 321         /* write the fence */
 322         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 323         amdgpu_ring_write(ring, lower_32_bits(addr));
 324         amdgpu_ring_write(ring, upper_32_bits(addr));
 325         amdgpu_ring_write(ring, lower_32_bits(seq));
 326
 327         /* optionally write high bits as well */
 328         if (write64bit) {
 329                 addr += 4;
 330                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 331                 amdgpu_ring_write(ring, lower_32_bits(addr));
 332                 amdgpu_ring_write(ring, upper_32_bits(addr));
 333                 amdgpu_ring_write(ring, upper_32_bits(seq));
 334         }
 335
 336         /* generate an interrupt */
 337         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 338         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 339 }
 340
 341 /**
 342  * sdma_v2_4_gfx_stop - stop the gfx async dma engines
 343  *
 344  * @adev: amdgpu_device pointer
 345  *
 346  * Stop the gfx async dma ring buffers (VI).
 347  */
 348 static void sdma_v2_4_gfx_stop(struct amdgpu_device *adev)
 349 {
 350         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 351         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 352         u32 rb_cntl, ib_cntl;
 353         int i;
 354
 355         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 356             (adev->mman.buffer_funcs_ring == sdma1))
 357                 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
 358
 359         for (i = 0; i < adev->sdma.num_instances; i++) {
 360                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 361                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 362                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 363                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 364                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 365                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 366         }
 367         sdma0->ready = false;
 368         sdma1->ready = false;
 369 }
 370
 371 /**
 372  * sdma_v2_4_rlc_stop - stop the compute async dma engines
 373  *
 374  * @adev: amdgpu_device pointer
 375  *
 376  * Stop the compute async dma queues (VI).
 377  */
 378 static void sdma_v2_4_rlc_stop(struct amdgpu_device *adev)
 379 {
 380         /* XXX todo */
 381 }
 382
 383 /**
 384  * sdma_v2_4_enable - stop the async dma engines
 385  *
 386  * @adev: amdgpu_device pointer
 387  * @enable: enable/disable the DMA MEs.
 388  *
 389  * Halt or unhalt the async dma engines (VI).
 390  */
 391 static void sdma_v2_4_enable(struct amdgpu_device *adev, bool enable)
 392 {
 393         u32 f32_cntl;
 394         int i;
 395
 396         if (!enable) {
 397                 sdma_v2_4_gfx_stop(adev);
 398                 sdma_v2_4_rlc_stop(adev);
 399         }
 400
 401         for (i = 0; i < adev->sdma.num_instances; i++) {
 402                 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
 403                 if (enable)
 404                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
 405                 else
 406                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
 407                 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
 408         }
 409 }
 410
 411 /**
 412  * sdma_v2_4_gfx_resume - setup and start the async dma engines
 413  *
 414  * @adev: amdgpu_device pointer
 415  *
 416  * Set up the gfx DMA ring buffers and enable them (VI).
 417  * Returns 0 for success, error for failure.
 418  */
 419 static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev)
 420 {
 421         struct amdgpu_ring *ring;
 422         u32 rb_cntl, ib_cntl;
 423         u32 rb_bufsz;
 424         u32 wb_offset;
 425         int i, j, r;
 426
 427         for (i = 0; i < adev->sdma.num_instances; i++) {
 428                 ring = &adev->sdma.instance[i].ring;
 429                 wb_offset = (ring->rptr_offs * 4);
 430
 431                 mutex_lock(&adev->srbm_mutex);
 432                 for (j = 0; j < 16; j++) {
 433                         vi_srbm_select(adev, 0, 0, 0, j);
 434                         /* SDMA GFX */
 435                         WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
 436                         WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
 437                 }
 438                 vi_srbm_select(adev, 0, 0, 0, 0);
 439                 mutex_unlock(&adev->srbm_mutex);
 440
 441                 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
 442                        adev->gfx.config.gb_addr_config & 0x70);
 443
 444                 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 445
 446                 /* Set ring buffer size in dwords */
 447                 rb_bufsz = order_base_2(ring->ring_size / 4);
 448                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 449                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 450 #ifdef __BIG_ENDIAN
 451                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 452                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 453                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 454 #endif
 455                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 456
 457                 /* Initialize the ring buffer's read and write pointers */
 458                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
 459                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
 460                 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
 461                 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
 462
 463                 /* set the wb address whether it's enabled or not */
 464                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
 465                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 466                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
 467                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 468
 469                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 470
 471                 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
 472                 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 473
 474                 ring->wptr = 0;
 475                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
 476
 477                 /* enable DMA RB */
 478                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 479                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 480
 481                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 482                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 483 #ifdef __BIG_ENDIAN
 484                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 485 #endif
 486                 /* enable DMA IBs */
 487                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 488
 489                 ring->ready = true;
 490         }
 491
 492         sdma_v2_4_enable(adev, true);
 493         for (i = 0; i < adev->sdma.num_instances; i++) {
 494                 ring = &adev->sdma.instance[i].ring;
 495                 r = amdgpu_ring_test_ring(ring);
 496                 if (r) {
 497                         ring->ready = false;
 498                         return r;
 499                 }
 500
 501                 if (adev->mman.buffer_funcs_ring == ring)
 502                         amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
 503         }
 504
 505         return 0;
 506 }
 507
 508 /**
 509  * sdma_v2_4_rlc_resume - setup and start the async dma engines
 510  *
 511  * @adev: amdgpu_device pointer
 512  *
 513  * Set up the compute DMA queues and enable them (VI).
 514  * Returns 0 for success, error for failure.
 515  */
 516 static int sdma_v2_4_rlc_resume(struct amdgpu_device *adev)
 517 {
 518         /* XXX todo */
 519         return 0;
 520 }
 521
 522 /**
 523  * sdma_v2_4_load_microcode - load the sDMA ME ucode
 524  *
 525  * @adev: amdgpu_device pointer
 526  *
 527  * Loads the sDMA0/1 ucode.
 528  * Returns 0 for success, -EINVAL if the ucode is not available.
 529  */
 530 static int sdma_v2_4_load_microcode(struct amdgpu_device *adev)
 531 {
 532         const struct sdma_firmware_header_v1_0 *hdr;
 533         const __le32 *fw_data;
 534         u32 fw_size;
 535         int i, j;
 536
 537         /* halt the MEs */
 538         sdma_v2_4_enable(adev, false);
 539
 540         for (i = 0; i < adev->sdma.num_instances; i++) {
 541                 if (!adev->sdma.instance[i].fw)
 542                         return -EINVAL;
 543                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 544                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 545                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 546                 fw_data = (const __le32 *)
 547                         (adev->sdma.instance[i].fw->data +
 548                          le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 549                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
 550                 for (j = 0; j < fw_size; j++)
 551                         WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
 552                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
 553         }
 554
 555         return 0;
 556 }
 557
 558 /**
 559  * sdma_v2_4_start - setup and start the async dma engines
 560  *
 561  * @adev: amdgpu_device pointer
 562  *
 563  * Set up the DMA engines and enable them (VI).
 564  * Returns 0 for success, error for failure.
 565  */
 566 static int sdma_v2_4_start(struct amdgpu_device *adev)
 567 {
 568         int r;
 569
 570         if (!adev->pp_enabled) {
 571                 if (!adev->firmware.smu_load) {
 572                         r = sdma_v2_4_load_microcode(adev);
 573                         if (r)
 574                                 return r;
 575                 } else {
 576                         r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
 577                                                         AMDGPU_UCODE_ID_SDMA0);
 578                         if (r)
 579                                 return -EINVAL;
 580                         r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
 581                                                         AMDGPU_UCODE_ID_SDMA1);
 582                         if (r)
 583                                 return -EINVAL;
 584                 }
 585         }
 586
 587         /* halt the engine before programing */
 588         sdma_v2_4_enable(adev, false);
 589
 590         /* start the gfx rings and rlc compute queues */
 591         r = sdma_v2_4_gfx_resume(adev);
 592         if (r)
 593                 return r;
 594         r = sdma_v2_4_rlc_resume(adev);
 595         if (r)
 596                 return r;
 597
 598         return 0;
 599 }
 600
 601 /**
 602  * sdma_v2_4_ring_test_ring - simple async dma engine test
 603  *
 604  * @ring: amdgpu_ring structure holding ring information
 605  *
 606  * Test the DMA engine by writing using it to write an
 607  * value to memory. (VI).
 608  * Returns 0 for success, error for failure.
 609  */
 610 static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring)
 611 {
 612         struct amdgpu_device *adev = ring->adev;
 613         unsigned i;
 614         unsigned index;
 615         int r;
 616         u32 tmp;
 617         u64 gpu_addr;
 618
 619         r = amdgpu_wb_get(adev, &index);
 620         if (r) {
 621                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 622                 return r;
 623         }
 624
 625         gpu_addr = adev->wb.gpu_addr + (index * 4);
 626         tmp = 0xCAFEDEAD;
 627         adev->wb.wb[index] = cpu_to_le32(tmp);
 628
 629         r = amdgpu_ring_alloc(ring, 5);
 630         if (r) {
 631                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 632                 amdgpu_wb_free(adev, index);
 633                 return r;
 634         }
 635
 636         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 637                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 638         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 639         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 640         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
 641         amdgpu_ring_write(ring, 0xDEADBEEF);
 642         amdgpu_ring_commit(ring);
 643
 644         for (i = 0; i < adev->usec_timeout; i++) {
 645                 tmp = le32_to_cpu(adev->wb.wb[index]);
 646                 if (tmp == 0xDEADBEEF)
 647                         break;
 648                 DRM_UDELAY(1);
 649         }
 650
 651         if (i < adev->usec_timeout) {
 652                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
 653         } else {
 654                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 655                           ring->idx, tmp);
 656                 r = -EINVAL;
 657         }
 658         amdgpu_wb_free(adev, index);
 659
 660         return r;
 661 }
 662
 663 /**
 664  * sdma_v2_4_ring_test_ib - test an IB on the DMA engine
 665  *
 666  * @ring: amdgpu_ring structure holding ring information
 667  *
 668  * Test a simple IB in the DMA ring (VI).
 669  * Returns 0 on success, error on failure.
 670  */
 671 static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 672 {
 673         struct amdgpu_device *adev = ring->adev;
 674         struct amdgpu_ib ib;
 675         struct fence *f = NULL;
 676         unsigned index;
 677         u32 tmp = 0;
 678         u64 gpu_addr;
 679         long r;
 680
 681         r = amdgpu_wb_get(adev, &index);
 682         if (r) {
 683                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 684                 return r;
 685         }
 686
 687         gpu_addr = adev->wb.gpu_addr + (index * 4);
 688         tmp = 0xCAFEDEAD;
 689         adev->wb.wb[index] = cpu_to_le32(tmp);
 690         memset(&ib, 0, sizeof(ib));
 691         r = amdgpu_ib_get(adev, NULL, 256, &ib);
 692         if (r) {
 693                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 694                 goto err0;
 695         }
 696
 697         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 698                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 699         ib.ptr[1] = lower_32_bits(gpu_addr);
 700         ib.ptr[2] = upper_32_bits(gpu_addr);
 701         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
 702         ib.ptr[4] = 0xDEADBEEF;
 703         ib.ptr[5] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 704         ib.ptr[6] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 705         ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 706         ib.length_dw = 8;
 707
 708         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
 709         if (r)
 710                 goto err1;
 711
 712         r = fence_wait_timeout(f, false, timeout);
 713         if (r == 0) {
 714                 DRM_ERROR("amdgpu: IB test timed out\n");
 715                 r = -ETIMEDOUT;
 716                 goto err1;
 717         } else if (r) {
 718                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 719                 goto err1;
 720         }
 721         tmp = le32_to_cpu(adev->wb.wb[index]);
 722         if (tmp == 0xDEADBEEF) {
 723                 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
 724                 r = 0;
 725         } else {
 726                 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
 727                 r = -EINVAL;
 728         }
 729
 730 err1:
 731         amdgpu_ib_free(adev, &ib, NULL);
 732         fence_put(f);
 733 err0:
 734         amdgpu_wb_free(adev, index);
 735         return r;
 736 }
 737
 738 /**
 739  * sdma_v2_4_vm_copy_pte - update PTEs by copying them from the GART
 740  *
 741  * @ib: indirect buffer to fill with commands
 742  * @pe: addr of the page entry
 743  * @src: src addr to copy from
 744  * @count: number of page entries to update
 745  *
 746  * Update PTEs by copying them from the GART using sDMA (CIK).
 747  */
 748 static void sdma_v2_4_vm_copy_pte(struct amdgpu_ib *ib,
 749                                   uint64_t pe, uint64_t src,
 750                                   unsigned count)
 751 {
 752         while (count) {
 753                 unsigned bytes = count * 8;
 754                 if (bytes > 0x1FFFF8)
 755                         bytes = 0x1FFFF8;
 756
 757                 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
 758                         SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
 759                 ib->ptr[ib->length_dw++] = bytes;
 760                 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 761                 ib->ptr[ib->length_dw++] = lower_32_bits(src);
 762                 ib->ptr[ib->length_dw++] = upper_32_bits(src);
 763                 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 764                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 765
 766                 pe += bytes;
 767                 src += bytes;
 768                 count -= bytes / 8;
 769         }
 770 }
 771
 772 /**
 773  * sdma_v2_4_vm_write_pte - update PTEs by writing them manually
 774  *
 775  * @ib: indirect buffer to fill with commands
 776  * @pe: addr of the page entry
 777  * @addr: dst addr to write into pe
 778  * @count: number of page entries to update
 779  * @incr: increase next addr by incr bytes
 780  * @flags: access flags
 781  *
 782  * Update PTEs by writing them manually using sDMA (CIK).
 783  */
 784 static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib,
 785                                    const dma_addr_t *pages_addr, uint64_t pe,
 786                                    uint64_t addr, unsigned count,
 787                                    uint32_t incr, uint32_t flags)
 788 {
 789         uint64_t value;
 790         unsigned ndw;
 791
 792         while (count) {
 793                 ndw = count * 2;
 794                 if (ndw > 0xFFFFE)
 795                         ndw = 0xFFFFE;
 796
 797                 /* for non-physically contiguous pages (system) */
 798                 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 799                         SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
 800                 ib->ptr[ib->length_dw++] = pe;
 801                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 802                 ib->ptr[ib->length_dw++] = ndw;
 803                 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
 804                         value = amdgpu_vm_map_gart(pages_addr, addr);
 805                         addr += incr;
 806                         value |= flags;
 807                         ib->ptr[ib->length_dw++] = value;
 808                         ib->ptr[ib->length_dw++] = upper_32_bits(value);
 809                 }
 810         }
 811 }
 812
 813 /**
 814  * sdma_v2_4_vm_set_pte_pde - update the page tables using sDMA
 815  *
 816  * @ib: indirect buffer to fill with commands
 817  * @pe: addr of the page entry
 818  * @addr: dst addr to write into pe
 819  * @count: number of page entries to update
 820  * @incr: increase next addr by incr bytes
 821  * @flags: access flags
 822  *
 823  * Update the page tables using sDMA (CIK).
 824  */
 825 static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib,
 826                                      uint64_t pe,
 827                                      uint64_t addr, unsigned count,
 828                                      uint32_t incr, uint32_t flags)
 829 {
 830         uint64_t value;
 831         unsigned ndw;
 832
 833         while (count) {
 834                 ndw = count;
 835                 if (ndw > 0x7FFFF)
 836                         ndw = 0x7FFFF;
 837
 838                 if (flags & AMDGPU_PTE_VALID)
 839                         value = addr;
 840                 else
 841                         value = 0;
 842
 843                 /* for physically contiguous pages (vram) */
 844                 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
 845                 ib->ptr[ib->length_dw++] = pe; /* dst addr */
 846                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 847                 ib->ptr[ib->length_dw++] = flags; /* mask */
 848                 ib->ptr[ib->length_dw++] = 0;
 849                 ib->ptr[ib->length_dw++] = value; /* value */
 850                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
 851                 ib->ptr[ib->length_dw++] = incr; /* increment size */
 852                 ib->ptr[ib->length_dw++] = 0;
 853                 ib->ptr[ib->length_dw++] = ndw; /* number of entries */
 854
 855                 pe += ndw * 8;
 856                 addr += ndw * incr;
 857                 count -= ndw;
 858         }
 859 }
 860
 861 /**
 862  * sdma_v2_4_ring_pad_ib - pad the IB to the required number of dw
 863  *
 864  * @ib: indirect buffer to fill with padding
 865  *
 866  */
 867 static void sdma_v2_4_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
 868 {
 869         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 870         u32 pad_count;
 871         int i;
 872
 873         pad_count = (8 - (ib->length_dw & 0x7)) % 8;
 874         for (i = 0; i < pad_count; i++)
 875                 if (sdma && sdma->burst_nop && (i == 0))
 876                         ib->ptr[ib->length_dw++] =
 877                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
 878                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
 879                 else
 880                         ib->ptr[ib->length_dw++] =
 881                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 882 }
 883
 884 /**
 885  * sdma_v2_4_ring_emit_pipeline_sync - sync the pipeline
 886  *
 887  * @ring: amdgpu_ring pointer
 888  *
 889  * Make sure all previous operations are completed (CIK).
 890  */
 891 static void sdma_v2_4_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
 892 {
 893         uint32_t seq = ring->fence_drv.sync_seq;
 894         uint64_t addr = ring->fence_drv.gpu_addr;
 895
 896         /* wait for idle */
 897         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 898                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
 899                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
 900                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
 901         amdgpu_ring_write(ring, addr & 0xfffffffc);
 902         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
 903         amdgpu_ring_write(ring, seq); /* reference */
 904         amdgpu_ring_write(ring, 0xfffffff); /* mask */
 905         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 906                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
 907 }
 908
 909 /**
 910  * sdma_v2_4_ring_emit_vm_flush - cik vm flush using sDMA
 911  *
 912  * @ring: amdgpu_ring pointer
 913  * @vm: amdgpu_vm pointer
 914  *
 915  * Update the page table base and flush the VM TLB
 916  * using sDMA (VI).
 917  */
 918 static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
 919                                          unsigned vm_id, uint64_t pd_addr)
 920 {
 921         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 922                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 923         if (vm_id < 8) {
 924                 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
 925         } else {
 926                 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
 927         }
 928         amdgpu_ring_write(ring, pd_addr >> 12);
 929
 930         /* flush TLB */
 931         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 932                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 933         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
 934         amdgpu_ring_write(ring, 1 << vm_id);
 935
 936         /* wait for flush */
 937         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 938                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
 939                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
 940         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
 941         amdgpu_ring_write(ring, 0);
 942         amdgpu_ring_write(ring, 0); /* reference */
 943         amdgpu_ring_write(ring, 0); /* mask */
 944         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 945                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 946 }
 947
 948 static int sdma_v2_4_early_init(void *handle)
 949 {
 950         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 951
 952         adev->sdma.num_instances = SDMA_MAX_INSTANCE;
 953
 954         sdma_v2_4_set_ring_funcs(adev);
 955         sdma_v2_4_set_buffer_funcs(adev);
 956         sdma_v2_4_set_vm_pte_funcs(adev);
 957         sdma_v2_4_set_irq_funcs(adev);
 958
 959         return 0;
 960 }
 961
 962 static int sdma_v2_4_sw_init(void *handle)
 963 {
 964         struct amdgpu_ring *ring;
 965         int r, i;
 966         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 967
 968         /* SDMA trap event */
 969         r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
 970         if (r)
 971                 return r;
 972
 973         /* SDMA Privileged inst */
 974         r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
 975         if (r)
 976                 return r;
 977
 978         /* SDMA Privileged inst */
 979         r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
 980         if (r)
 981                 return r;
 982
 983         r = sdma_v2_4_init_microcode(adev);
 984         if (r) {
 985                 DRM_ERROR("Failed to load sdma firmware!\n");
 986                 return r;
 987         }
 988
 989         for (i = 0; i < adev->sdma.num_instances; i++) {
 990                 ring = &adev->sdma.instance[i].ring;
 991                 ring->ring_obj = NULL;
 992                 ring->use_doorbell = false;
 993                 sprintf(ring->name, "sdma%d", i);
 994                 r = amdgpu_ring_init(adev, ring, 1024,
 995                                      SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
 996                                      &adev->sdma.trap_irq,
 997                                      (i == 0) ?
 998                                      AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1,
 999                                      AMDGPU_RING_TYPE_SDMA);
1000                 if (r)
1001                         return r;
1002         }
1003
1004         return r;
1005 }
1006
1007 static int sdma_v2_4_sw_fini(void *handle)
1008 {
1009         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1010         int i;
1011
1012         for (i = 0; i < adev->sdma.num_instances; i++)
1013                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1014
1015         sdma_v2_4_free_microcode(adev);
1016         return 0;
1017 }
1018
1019 static int sdma_v2_4_hw_init(void *handle)
1020 {
1021         int r;
1022         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1023
1024         sdma_v2_4_init_golden_registers(adev);
1025
1026         r = sdma_v2_4_start(adev);
1027         if (r)
1028                 return r;
1029
1030         return r;
1031 }
1032
1033 static int sdma_v2_4_hw_fini(void *handle)
1034 {
1035         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1036
1037         sdma_v2_4_enable(adev, false);
1038
1039         return 0;
1040 }
1041
1042 static int sdma_v2_4_suspend(void *handle)
1043 {
1044         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1045
1046         return sdma_v2_4_hw_fini(adev);
1047 }
1048
1049 static int sdma_v2_4_resume(void *handle)
1050 {
1051         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1052
1053         return sdma_v2_4_hw_init(adev);
1054 }
1055
1056 static bool sdma_v2_4_is_idle(void *handle)
1057 {
1058         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1059         u32 tmp = RREG32(mmSRBM_STATUS2);
1060
1061         if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1062                    SRBM_STATUS2__SDMA1_BUSY_MASK))
1063             return false;
1064
1065         return true;
1066 }
1067
1068 static int sdma_v2_4_wait_for_idle(void *handle)
1069 {
1070         unsigned i;
1071         u32 tmp;
1072         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1073
1074         for (i = 0; i < adev->usec_timeout; i++) {
1075                 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1076                                 SRBM_STATUS2__SDMA1_BUSY_MASK);
1077
1078                 if (!tmp)
1079                         return 0;
1080                 udelay(1);
1081         }
1082         return -ETIMEDOUT;
1083 }
1084
1085 static int sdma_v2_4_soft_reset(void *handle)
1086 {
1087         u32 srbm_soft_reset = 0;
1088         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1089         u32 tmp = RREG32(mmSRBM_STATUS2);
1090
1091         if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
1092                 /* sdma0 */
1093                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1094                 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1095                 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1096                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1097         }
1098         if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
1099                 /* sdma1 */
1100                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1101                 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1102                 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1103                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1104         }
1105
1106         if (srbm_soft_reset) {
1107                 tmp = RREG32(mmSRBM_SOFT_RESET);
1108                 tmp |= srbm_soft_reset;
1109                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1110                 WREG32(mmSRBM_SOFT_RESET, tmp);
1111                 tmp = RREG32(mmSRBM_SOFT_RESET);
1112
1113                 udelay(50);
1114
1115                 tmp &= ~srbm_soft_reset;
1116                 WREG32(mmSRBM_SOFT_RESET, tmp);
1117                 tmp = RREG32(mmSRBM_SOFT_RESET);
1118
1119                 /* Wait a little for things to settle down */
1120                 udelay(50);
1121         }
1122
1123         return 0;
1124 }
1125
1126 static int sdma_v2_4_set_trap_irq_state(struct amdgpu_device *adev,
1127                                         struct amdgpu_irq_src *src,
1128                                         unsigned type,
1129                                         enum amdgpu_interrupt_state state)
1130 {
1131         u32 sdma_cntl;
1132
1133         switch (type) {
1134         case AMDGPU_SDMA_IRQ_TRAP0:
1135                 switch (state) {
1136                 case AMDGPU_IRQ_STATE_DISABLE:
1137                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1138                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1139                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1140                         break;
1141                 case AMDGPU_IRQ_STATE_ENABLE:
1142                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1143                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1144                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1145                         break;
1146                 default:
1147                         break;
1148                 }
1149                 break;
1150         case AMDGPU_SDMA_IRQ_TRAP1:
1151                 switch (state) {
1152                 case AMDGPU_IRQ_STATE_DISABLE:
1153                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1154                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1155                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1156                         break;
1157                 case AMDGPU_IRQ_STATE_ENABLE:
1158                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1159                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1160                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1161                         break;
1162                 default:
1163                         break;
1164                 }
1165                 break;
1166         default:
1167                 break;
1168         }
1169         return 0;
1170 }
1171
1172 static int sdma_v2_4_process_trap_irq(struct amdgpu_device *adev,
1173                                       struct amdgpu_irq_src *source,
1174                                       struct amdgpu_iv_entry *entry)
1175 {
1176         u8 instance_id, queue_id;
1177
1178         instance_id = (entry->ring_id & 0x3) >> 0;
1179         queue_id = (entry->ring_id & 0xc) >> 2;
1180         DRM_DEBUG("IH: SDMA trap\n");
1181         switch (instance_id) {
1182         case 0:
1183                 switch (queue_id) {
1184                 case 0:
1185                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1186                         break;
1187                 case 1:
1188                         /* XXX compute */
1189                         break;
1190                 case 2:
1191                         /* XXX compute */
1192                         break;
1193                 }
1194                 break;
1195         case 1:
1196                 switch (queue_id) {
1197                 case 0:
1198                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1199                         break;
1200                 case 1:
1201                         /* XXX compute */
1202                         break;
1203                 case 2:
1204                         /* XXX compute */
1205                         break;
1206                 }
1207                 break;
1208         }
1209         return 0;
1210 }
1211
1212 static int sdma_v2_4_process_illegal_inst_irq(struct amdgpu_device *adev,
1213                                               struct amdgpu_irq_src *source,
1214                                               struct amdgpu_iv_entry *entry)
1215 {
1216         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1217         schedule_work(&adev->reset_work);
1218         return 0;
1219 }
1220
1221 static int sdma_v2_4_set_clockgating_state(void *handle,
1222                                           enum amd_clockgating_state state)
1223 {
1224         /* XXX handled via the smc on VI */
1225         return 0;
1226 }
1227
1228 static int sdma_v2_4_set_powergating_state(void *handle,
1229                                           enum amd_powergating_state state)
1230 {
1231         return 0;
1232 }
1233
1234 const struct amd_ip_funcs sdma_v2_4_ip_funcs = {
1235         .name = "sdma_v2_4",
1236         .early_init = sdma_v2_4_early_init,
1237         .late_init = NULL,
1238         .sw_init = sdma_v2_4_sw_init,
1239         .sw_fini = sdma_v2_4_sw_fini,
1240         .hw_init = sdma_v2_4_hw_init,
1241         .hw_fini = sdma_v2_4_hw_fini,
1242         .suspend = sdma_v2_4_suspend,
1243         .resume = sdma_v2_4_resume,
1244         .is_idle = sdma_v2_4_is_idle,
1245         .wait_for_idle = sdma_v2_4_wait_for_idle,
1246         .soft_reset = sdma_v2_4_soft_reset,
1247         .set_clockgating_state = sdma_v2_4_set_clockgating_state,
1248         .set_powergating_state = sdma_v2_4_set_powergating_state,
1249 };
1250
1251 static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
1252         .get_rptr = sdma_v2_4_ring_get_rptr,
1253         .get_wptr = sdma_v2_4_ring_get_wptr,
1254         .set_wptr = sdma_v2_4_ring_set_wptr,
1255         .parse_cs = NULL,
1256         .emit_ib = sdma_v2_4_ring_emit_ib,
1257         .emit_fence = sdma_v2_4_ring_emit_fence,
1258         .emit_pipeline_sync = sdma_v2_4_ring_emit_pipeline_sync,
1259         .emit_vm_flush = sdma_v2_4_ring_emit_vm_flush,
1260         .emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush,
1261         .emit_hdp_invalidate = sdma_v2_4_ring_emit_hdp_invalidate,
1262         .test_ring = sdma_v2_4_ring_test_ring,
1263         .test_ib = sdma_v2_4_ring_test_ib,
1264         .insert_nop = sdma_v2_4_ring_insert_nop,
1265         .pad_ib = sdma_v2_4_ring_pad_ib,
1266 };
1267
1268 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev)
1269 {
1270         int i;
1271
1272         for (i = 0; i < adev->sdma.num_instances; i++)
1273                 adev->sdma.instance[i].ring.funcs = &sdma_v2_4_ring_funcs;
1274 }
1275
1276 static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs = {
1277         .set = sdma_v2_4_set_trap_irq_state,
1278         .process = sdma_v2_4_process_trap_irq,
1279 };
1280
1281 static const struct amdgpu_irq_src_funcs sdma_v2_4_illegal_inst_irq_funcs = {
1282         .process = sdma_v2_4_process_illegal_inst_irq,
1283 };
1284
1285 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev)
1286 {
1287         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1288         adev->sdma.trap_irq.funcs = &sdma_v2_4_trap_irq_funcs;
1289         adev->sdma.illegal_inst_irq.funcs = &sdma_v2_4_illegal_inst_irq_funcs;
1290 }
1291
1292 /**
1293  * sdma_v2_4_emit_copy_buffer - copy buffer using the sDMA engine
1294  *
1295  * @ring: amdgpu_ring structure holding ring information
1296  * @src_offset: src GPU address
1297  * @dst_offset: dst GPU address
1298  * @byte_count: number of bytes to xfer
1299  *
1300  * Copy GPU buffers using the DMA engine (VI).
1301  * Used by the amdgpu ttm implementation to move pages if
1302  * registered as the asic copy callback.
1303  */
1304 static void sdma_v2_4_emit_copy_buffer(struct amdgpu_ib *ib,
1305                                        uint64_t src_offset,
1306                                        uint64_t dst_offset,
1307                                        uint32_t byte_count)
1308 {
1309         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1310                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1311         ib->ptr[ib->length_dw++] = byte_count;
1312         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1313         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1314         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1315         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1316         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1317 }
1318
1319 /**
1320  * sdma_v2_4_emit_fill_buffer - fill buffer using the sDMA engine
1321  *
1322  * @ring: amdgpu_ring structure holding ring information
1323  * @src_data: value to write to buffer
1324  * @dst_offset: dst GPU address
1325  * @byte_count: number of bytes to xfer
1326  *
1327  * Fill GPU buffers using the DMA engine (VI).
1328  */
1329 static void sdma_v2_4_emit_fill_buffer(struct amdgpu_ib *ib,
1330                                        uint32_t src_data,
1331                                        uint64_t dst_offset,
1332                                        uint32_t byte_count)
1333 {
1334         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1335         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1336         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1337         ib->ptr[ib->length_dw++] = src_data;
1338         ib->ptr[ib->length_dw++] = byte_count;
1339 }
1340
1341 static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs = {
1342         .copy_max_bytes = 0x1fffff,
1343         .copy_num_dw = 7,
1344         .emit_copy_buffer = sdma_v2_4_emit_copy_buffer,
1345
1346         .fill_max_bytes = 0x1fffff,
1347         .fill_num_dw = 7,
1348         .emit_fill_buffer = sdma_v2_4_emit_fill_buffer,
1349 };
1350
1351 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev)
1352 {
1353         if (adev->mman.buffer_funcs == NULL) {
1354                 adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs;
1355                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1356         }
1357 }
1358
1359 static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = {
1360         .copy_pte = sdma_v2_4_vm_copy_pte,
1361         .write_pte = sdma_v2_4_vm_write_pte,
1362         .set_pte_pde = sdma_v2_4_vm_set_pte_pde,
1363 };
1364
1365 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev)
1366 {
1367         unsigned i;
1368
1369         if (adev->vm_manager.vm_pte_funcs == NULL) {
1370                 adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs;
1371                 for (i = 0; i < adev->sdma.num_instances; i++)
1372                         adev->vm_manager.vm_pte_rings[i] =
1373                                 &adev->sdma.instance[i].ring;
1374
1375                 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
1376         }
1377 }