drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c

   1 /*
   2  * Copyright 2021 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "amdgpu.h"
  25 #include "amdgpu_jpeg.h"
  26 #include "amdgpu_pm.h"
  27 #include "soc15.h"
  28 #include "soc15d.h"
  29 #include "jpeg_v2_0.h"
  30 #include "jpeg_v4_0.h"
  31 #include "mmsch_v4_0.h"
  32
  33 #include "vcn/vcn_4_0_0_offset.h"
  34 #include "vcn/vcn_4_0_0_sh_mask.h"
  35 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h"
  36
  37 #define regUVD_JPEG_PITCH_INTERNAL_OFFSET                  0x401f
  38
  39 static int jpeg_v4_0_start_sriov(struct amdgpu_device *adev);
  40 static void jpeg_v4_0_set_dec_ring_funcs(struct amdgpu_device *adev);
  41 static void jpeg_v4_0_set_irq_funcs(struct amdgpu_device *adev);
  42 static int jpeg_v4_0_set_powergating_state(void *handle,
  43                                 enum amd_powergating_state state);
  44 static void jpeg_v4_0_set_ras_funcs(struct amdgpu_device *adev);
  45
  46 static void jpeg_v4_0_dec_ring_set_wptr(struct amdgpu_ring *ring);
  47
  48 /**
  49  * jpeg_v4_0_early_init - set function pointers
  50  *
  51  * @handle: amdgpu_device pointer
  52  *
  53  * Set ring and irq function pointers
  54  */
  55 static int jpeg_v4_0_early_init(void *handle)
  56 {
  57         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  58
  59
  60         adev->jpeg.num_jpeg_inst = 1;
  61
  62         jpeg_v4_0_set_dec_ring_funcs(adev);
  63         jpeg_v4_0_set_irq_funcs(adev);
  64         jpeg_v4_0_set_ras_funcs(adev);
  65
  66         return 0;
  67 }
  68
  69 /**
  70  * jpeg_v4_0_sw_init - sw init for JPEG block
  71  *
  72  * @handle: amdgpu_device pointer
  73  *
  74  * Load firmware and sw initialization
  75  */
  76 static int jpeg_v4_0_sw_init(void *handle)
  77 {
  78         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  79         struct amdgpu_ring *ring;
  80         int r;
  81
  82         /* JPEG TRAP */
  83         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
  84                 VCN_4_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq);
  85         if (r)
  86                 return r;
  87
  88         /* JPEG DJPEG POISON EVENT */
  89         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
  90                         VCN_4_0__SRCID_DJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq);
  91         if (r)
  92                 return r;
  93
  94         /* JPEG EJPEG POISON EVENT */
  95         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
  96                         VCN_4_0__SRCID_EJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq);
  97         if (r)
  98                 return r;
  99
 100         r = amdgpu_jpeg_sw_init(adev);
 101         if (r)
 102                 return r;
 103
 104         r = amdgpu_jpeg_resume(adev);
 105         if (r)
 106                 return r;
 107
 108         ring = &adev->jpeg.inst->ring_dec;
 109         ring->use_doorbell = true;
 110         ring->doorbell_index = amdgpu_sriov_vf(adev) ? (((adev->doorbell_index.vcn.vcn_ring0_1) << 1) + 4) : ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1);
 111         ring->vm_hub = AMDGPU_MMHUB_0;
 112
 113         sprintf(ring->name, "jpeg_dec");
 114         r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0,
 115                              AMDGPU_RING_PRIO_DEFAULT, NULL);
 116         if (r)
 117                 return r;
 118
 119         adev->jpeg.internal.jpeg_pitch = regUVD_JPEG_PITCH_INTERNAL_OFFSET;
 120         adev->jpeg.inst->external.jpeg_pitch = SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_PITCH);
 121
 122         r = amdgpu_jpeg_ras_sw_init(adev);
 123         if (r)
 124                 return r;
 125
 126         return 0;
 127 }
 128
 129 /**
 130  * jpeg_v4_0_sw_fini - sw fini for JPEG block
 131  *
 132  * @handle: amdgpu_device pointer
 133  *
 134  * JPEG suspend and free up sw allocation
 135  */
 136 static int jpeg_v4_0_sw_fini(void *handle)
 137 {
 138         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 139         int r;
 140
 141         r = amdgpu_jpeg_suspend(adev);
 142         if (r)
 143                 return r;
 144
 145         r = amdgpu_jpeg_sw_fini(adev);
 146
 147         return r;
 148 }
 149
 150 /**
 151  * jpeg_v4_0_hw_init - start and test JPEG block
 152  *
 153  * @handle: amdgpu_device pointer
 154  *
 155  */
 156 static int jpeg_v4_0_hw_init(void *handle)
 157 {
 158         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 159         struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec;
 160         int r;
 161
 162         if (amdgpu_sriov_vf(adev)) {
 163                 r = jpeg_v4_0_start_sriov(adev);
 164                 if (r)
 165                         return r;
 166                 ring->wptr = 0;
 167                 ring->wptr_old = 0;
 168                 jpeg_v4_0_dec_ring_set_wptr(ring);
 169                 ring->sched.ready = true;
 170         } else {
 171                 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
 172                                                 (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0);
 173
 174                 WREG32_SOC15(VCN, 0, regVCN_JPEG_DB_CTRL,
 175                         ring->doorbell_index << VCN_JPEG_DB_CTRL__OFFSET__SHIFT |
 176                         VCN_JPEG_DB_CTRL__EN_MASK);
 177
 178                 r = amdgpu_ring_test_helper(ring);
 179                 if (r)
 180                         return r;
 181         }
 182
 183         DRM_DEV_INFO(adev->dev, "JPEG decode initialized successfully.\n");
 184
 185         return 0;
 186 }
 187
 188 /**
 189  * jpeg_v4_0_hw_fini - stop the hardware block
 190  *
 191  * @handle: amdgpu_device pointer
 192  *
 193  * Stop the JPEG block, mark ring as not ready any more
 194  */
 195 static int jpeg_v4_0_hw_fini(void *handle)
 196 {
 197         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 198
 199         cancel_delayed_work_sync(&adev->vcn.idle_work);
 200         if (!amdgpu_sriov_vf(adev)) {
 201                 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
 202                         RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS))
 203                         jpeg_v4_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
 204         }
 205         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG))
 206                 amdgpu_irq_put(adev, &adev->jpeg.inst->ras_poison_irq, 0);
 207
 208         return 0;
 209 }
 210
 211 /**
 212  * jpeg_v4_0_suspend - suspend JPEG block
 213  *
 214  * @handle: amdgpu_device pointer
 215  *
 216  * HW fini and suspend JPEG block
 217  */
 218 static int jpeg_v4_0_suspend(void *handle)
 219 {
 220         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 221         int r;
 222
 223         r = jpeg_v4_0_hw_fini(adev);
 224         if (r)
 225                 return r;
 226
 227         r = amdgpu_jpeg_suspend(adev);
 228
 229         return r;
 230 }
 231
 232 /**
 233  * jpeg_v4_0_resume - resume JPEG block
 234  *
 235  * @handle: amdgpu_device pointer
 236  *
 237  * Resume firmware and hw init JPEG block
 238  */
 239 static int jpeg_v4_0_resume(void *handle)
 240 {
 241         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 242         int r;
 243
 244         r = amdgpu_jpeg_resume(adev);
 245         if (r)
 246                 return r;
 247
 248         r = jpeg_v4_0_hw_init(adev);
 249
 250         return r;
 251 }
 252
 253 static void jpeg_v4_0_disable_clock_gating(struct amdgpu_device *adev)
 254 {
 255         uint32_t data = 0;
 256
 257         data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL);
 258         if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) {
 259                 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 260                 data &= (~JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK);
 261         } else {
 262                 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 263         }
 264
 265         data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 266         data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 267         WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data);
 268
 269         data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE);
 270         data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK
 271                 | JPEG_CGC_GATE__JPEG2_DEC_MASK
 272                 | JPEG_CGC_GATE__JMCIF_MASK
 273                 | JPEG_CGC_GATE__JRBBM_MASK);
 274         WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data);
 275 }
 276
 277 static void jpeg_v4_0_enable_clock_gating(struct amdgpu_device *adev)
 278 {
 279         uint32_t data = 0;
 280
 281         data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL);
 282         if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) {
 283                 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 284                 data |= JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK;
 285         } else {
 286                 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 287         }
 288
 289         data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 290         data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 291         WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data);
 292
 293         data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE);
 294         data |= (JPEG_CGC_GATE__JPEG_DEC_MASK
 295                 |JPEG_CGC_GATE__JPEG2_DEC_MASK
 296                 |JPEG_CGC_GATE__JMCIF_MASK
 297                 |JPEG_CGC_GATE__JRBBM_MASK);
 298         WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data);
 299 }
 300
 301 static int jpeg_v4_0_disable_static_power_gating(struct amdgpu_device *adev)
 302 {
 303         if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
 304                 uint32_t data = 0;
 305                 int r = 0;
 306
 307                 data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
 308                 WREG32(SOC15_REG_OFFSET(JPEG, 0, regUVD_PGFSM_CONFIG), data);
 309
 310                 r = SOC15_WAIT_ON_RREG(JPEG, 0,
 311                         regUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON,
 312                         UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);
 313
 314                 if (r) {
 315                         DRM_DEV_ERROR(adev->dev, "amdgpu: JPEG disable power gating failed\n");
 316                         return r;
 317                 }
 318         }
 319
 320         /* disable anti hang mechanism */
 321         WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0,
 322                 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
 323
 324         /* keep the JPEG in static PG mode */
 325         WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0,
 326                 ~UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK);
 327
 328         return 0;
 329 }
 330
 331 static int jpeg_v4_0_enable_static_power_gating(struct amdgpu_device *adev)
 332 {
 333         /* enable anti hang mechanism */
 334         WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS),
 335                 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK,
 336                 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
 337
 338         if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
 339                 uint32_t data = 0;
 340                 int r = 0;
 341
 342                 data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
 343                 WREG32(SOC15_REG_OFFSET(JPEG, 0, regUVD_PGFSM_CONFIG), data);
 344
 345                 r = SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_PGFSM_STATUS,
 346                         (2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT),
 347                         UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);
 348
 349                 if (r) {
 350                         DRM_DEV_ERROR(adev->dev, "amdgpu: JPEG enable power gating failed\n");
 351                         return r;
 352                 }
 353         }
 354
 355         return 0;
 356 }
 357
 358 /**
 359  * jpeg_v4_0_start - start JPEG block
 360  *
 361  * @adev: amdgpu_device pointer
 362  *
 363  * Setup and start the JPEG block
 364  */
 365 static int jpeg_v4_0_start(struct amdgpu_device *adev)
 366 {
 367         struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec;
 368         int r;
 369
 370         if (adev->pm.dpm_enabled)
 371                 amdgpu_dpm_enable_jpeg(adev, true);
 372
 373         /* disable power gating */
 374         r = jpeg_v4_0_disable_static_power_gating(adev);
 375         if (r)
 376                 return r;
 377
 378         /* JPEG disable CGC */
 379         jpeg_v4_0_disable_clock_gating(adev);
 380
 381         /* MJPEG global tiling registers */
 382         WREG32_SOC15(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG,
 383                 adev->gfx.config.gb_addr_config);
 384
 385
 386         /* enable JMI channel */
 387         WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL), 0,
 388                 ~UVD_JMI_CNTL__SOFT_RESET_MASK);
 389
 390         /* enable System Interrupt for JRBC */
 391         WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regJPEG_SYS_INT_EN),
 392                 JPEG_SYS_INT_EN__DJRBC_MASK,
 393                 ~JPEG_SYS_INT_EN__DJRBC_MASK);
 394
 395         WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_VMID, 0);
 396         WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
 397         WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
 398                 lower_32_bits(ring->gpu_addr));
 399         WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
 400                 upper_32_bits(ring->gpu_addr));
 401         WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR, 0);
 402         WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, 0);
 403         WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_CNTL, 0x00000002L);
 404         WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_SIZE, ring->ring_size / 4);
 405         ring->wptr = RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR);
 406
 407         return 0;
 408 }
 409
 410 static int jpeg_v4_0_start_sriov(struct amdgpu_device *adev)
 411 {
 412         struct amdgpu_ring *ring;
 413         uint64_t ctx_addr;
 414         uint32_t param, resp, expected;
 415         uint32_t tmp, timeout;
 416
 417         struct amdgpu_mm_table *table = &adev->virt.mm_table;
 418         uint32_t *table_loc;
 419         uint32_t table_size;
 420         uint32_t size, size_dw;
 421         uint32_t init_status;
 422
 423         struct mmsch_v4_0_cmd_direct_write
 424                 direct_wt = { {0} };
 425         struct mmsch_v4_0_cmd_end end = { {0} };
 426         struct mmsch_v4_0_init_header header;
 427
 428         direct_wt.cmd_header.command_type =
 429                 MMSCH_COMMAND__DIRECT_REG_WRITE;
 430         end.cmd_header.command_type =
 431                 MMSCH_COMMAND__END;
 432
 433         header.version = MMSCH_VERSION;
 434         header.total_size = RREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_SIZE);
 435
 436         header.jpegdec.init_status = 0;
 437         header.jpegdec.table_offset = 0;
 438         header.jpegdec.table_size = 0;
 439
 440         table_loc = (uint32_t *)table->cpu_addr;
 441         table_loc += header.total_size;
 442
 443         table_size = 0;
 444
 445         ring = &adev->jpeg.inst->ring_dec;
 446
 447         MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(JPEG, 0,
 448                 regUVD_LMI_JRBC_RB_64BIT_BAR_LOW),
 449                 lower_32_bits(ring->gpu_addr));
 450         MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(JPEG, 0,
 451                 regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH),
 452                 upper_32_bits(ring->gpu_addr));
 453         MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(JPEG, 0,
 454                 regUVD_JRBC_RB_SIZE), ring->ring_size / 4);
 455
 456         /* add end packet */
 457         MMSCH_V4_0_INSERT_END();
 458
 459         /* refine header */
 460         header.jpegdec.init_status = 0;
 461         header.jpegdec.table_offset = header.total_size;
 462         header.jpegdec.table_size = table_size;
 463         header.total_size += table_size;
 464
 465         /* Update init table header in memory */
 466         size = sizeof(struct mmsch_v4_0_init_header);
 467         table_loc = (uint32_t *)table->cpu_addr;
 468         memcpy((void *)table_loc, &header, size);
 469
 470         /* message MMSCH (in VCN[0]) to initialize this client
 471          * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr
 472          * of memory descriptor location
 473          */
 474         ctx_addr = table->gpu_addr;
 475         WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr));
 476         WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr));
 477
 478         /* 2, update vmid of descriptor */
 479         tmp = RREG32_SOC15(VCN, 0, regMMSCH_VF_VMID);
 480         tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
 481         /* use domain0 for MM scheduler */
 482         tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
 483         WREG32_SOC15(VCN, 0, regMMSCH_VF_VMID, tmp);
 484
 485         /* 3, notify mmsch about the size of this descriptor */
 486         size = header.total_size;
 487         WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_SIZE, size);
 488
 489         /* 4, set resp to zero */
 490         WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP, 0);
 491
 492         /* 5, kick off the initialization and wait until
 493          * MMSCH_VF_MAILBOX_RESP becomes non-zero
 494          */
 495         param = 0x00000001;
 496         WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_HOST, param);
 497         tmp = 0;
 498         timeout = 1000;
 499         resp = 0;
 500         expected = MMSCH_VF_MAILBOX_RESP__OK;
 501         init_status = ((struct mmsch_v4_0_init_header *)(table_loc))->jpegdec.init_status;
 502         while (resp != expected) {
 503                 resp = RREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP);
 504
 505                 if (resp != 0)
 506                         break;
 507                 udelay(10);
 508                 tmp = tmp + 10;
 509                 if (tmp >= timeout) {
 510                         DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\
 511                                 " waiting for regMMSCH_VF_MAILBOX_RESP "\
 512                                 "(expected=0x%08x, readback=0x%08x)\n",
 513                                 tmp, expected, resp);
 514                         return -EBUSY;
 515                 }
 516         }
 517         if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE && init_status != MMSCH_VF_ENGINE_STATUS__PASS)
 518                 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init status for jpeg: %x\n", resp, init_status);
 519
 520         return 0;
 521
 522 }
 523
 524 /**
 525  * jpeg_v4_0_stop - stop JPEG block
 526  *
 527  * @adev: amdgpu_device pointer
 528  *
 529  * stop the JPEG block
 530  */
 531 static int jpeg_v4_0_stop(struct amdgpu_device *adev)
 532 {
 533         int r;
 534
 535         /* reset JMI */
 536         WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL),
 537                 UVD_JMI_CNTL__SOFT_RESET_MASK,
 538                 ~UVD_JMI_CNTL__SOFT_RESET_MASK);
 539
 540         jpeg_v4_0_enable_clock_gating(adev);
 541
 542         /* enable power gating */
 543         r = jpeg_v4_0_enable_static_power_gating(adev);
 544         if (r)
 545                 return r;
 546
 547         if (adev->pm.dpm_enabled)
 548                 amdgpu_dpm_enable_jpeg(adev, false);
 549
 550         return 0;
 551 }
 552
 553 /**
 554  * jpeg_v4_0_dec_ring_get_rptr - get read pointer
 555  *
 556  * @ring: amdgpu_ring pointer
 557  *
 558  * Returns the current hardware read pointer
 559  */
 560 static uint64_t jpeg_v4_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
 561 {
 562         struct amdgpu_device *adev = ring->adev;
 563
 564         return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR);
 565 }
 566
 567 /**
 568  * jpeg_v4_0_dec_ring_get_wptr - get write pointer
 569  *
 570  * @ring: amdgpu_ring pointer
 571  *
 572  * Returns the current hardware write pointer
 573  */
 574 static uint64_t jpeg_v4_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
 575 {
 576         struct amdgpu_device *adev = ring->adev;
 577
 578         if (ring->use_doorbell)
 579                 return *ring->wptr_cpu_addr;
 580         else
 581                 return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR);
 582 }
 583
 584 /**
 585  * jpeg_v4_0_dec_ring_set_wptr - set write pointer
 586  *
 587  * @ring: amdgpu_ring pointer
 588  *
 589  * Commits the write pointer to the hardware
 590  */
 591 static void jpeg_v4_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
 592 {
 593         struct amdgpu_device *adev = ring->adev;
 594
 595         if (ring->use_doorbell) {
 596                 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
 597                 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
 598         } else {
 599                 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
 600         }
 601 }
 602
 603 static bool jpeg_v4_0_is_idle(void *handle)
 604 {
 605         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 606         int ret = 1;
 607
 608         ret &= (((RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS) &
 609                 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==
 610                 UVD_JRBC_STATUS__RB_JOB_DONE_MASK));
 611
 612         return ret;
 613 }
 614
 615 static int jpeg_v4_0_wait_for_idle(void *handle)
 616 {
 617         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 618
 619         return SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_JRBC_STATUS,
 620                 UVD_JRBC_STATUS__RB_JOB_DONE_MASK,
 621                 UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
 622 }
 623
 624 static int jpeg_v4_0_set_clockgating_state(void *handle,
 625                                           enum amd_clockgating_state state)
 626 {
 627         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 628         bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
 629
 630         if (enable) {
 631                 if (!jpeg_v4_0_is_idle(handle))
 632                         return -EBUSY;
 633                 jpeg_v4_0_enable_clock_gating(adev);
 634         } else {
 635                 jpeg_v4_0_disable_clock_gating(adev);
 636         }
 637
 638         return 0;
 639 }
 640
 641 static int jpeg_v4_0_set_powergating_state(void *handle,
 642                                           enum amd_powergating_state state)
 643 {
 644         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 645         int ret;
 646
 647         if (amdgpu_sriov_vf(adev)) {
 648                 adev->jpeg.cur_state = AMD_PG_STATE_UNGATE;
 649                 return 0;
 650         }
 651
 652         if (state == adev->jpeg.cur_state)
 653                 return 0;
 654
 655         if (state == AMD_PG_STATE_GATE)
 656                 ret = jpeg_v4_0_stop(adev);
 657         else
 658                 ret = jpeg_v4_0_start(adev);
 659
 660         if (!ret)
 661                 adev->jpeg.cur_state = state;
 662
 663         return ret;
 664 }
 665
 666 static int jpeg_v4_0_set_interrupt_state(struct amdgpu_device *adev,
 667                                         struct amdgpu_irq_src *source,
 668                                         unsigned type,
 669                                         enum amdgpu_interrupt_state state)
 670 {
 671         return 0;
 672 }
 673
 674 static int jpeg_v4_0_set_ras_interrupt_state(struct amdgpu_device *adev,
 675                                         struct amdgpu_irq_src *source,
 676                                         unsigned int type,
 677                                         enum amdgpu_interrupt_state state)
 678 {
 679         return 0;
 680 }
 681
 682 static int jpeg_v4_0_process_interrupt(struct amdgpu_device *adev,
 683                                       struct amdgpu_irq_src *source,
 684                                       struct amdgpu_iv_entry *entry)
 685 {
 686         DRM_DEBUG("IH: JPEG TRAP\n");
 687
 688         switch (entry->src_id) {
 689         case VCN_4_0__SRCID__JPEG_DECODE:
 690                 amdgpu_fence_process(&adev->jpeg.inst->ring_dec);
 691                 break;
 692         default:
 693                 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n",
 694                           entry->src_id, entry->src_data[0]);
 695                 break;
 696         }
 697
 698         return 0;
 699 }
 700
 701 static const struct amd_ip_funcs jpeg_v4_0_ip_funcs = {
 702         .name = "jpeg_v4_0",
 703         .early_init = jpeg_v4_0_early_init,
 704         .late_init = NULL,
 705         .sw_init = jpeg_v4_0_sw_init,
 706         .sw_fini = jpeg_v4_0_sw_fini,
 707         .hw_init = jpeg_v4_0_hw_init,
 708         .hw_fini = jpeg_v4_0_hw_fini,
 709         .suspend = jpeg_v4_0_suspend,
 710         .resume = jpeg_v4_0_resume,
 711         .is_idle = jpeg_v4_0_is_idle,
 712         .wait_for_idle = jpeg_v4_0_wait_for_idle,
 713         .check_soft_reset = NULL,
 714         .pre_soft_reset = NULL,
 715         .soft_reset = NULL,
 716         .post_soft_reset = NULL,
 717         .set_clockgating_state = jpeg_v4_0_set_clockgating_state,
 718         .set_powergating_state = jpeg_v4_0_set_powergating_state,
 719 };
 720
 721 static const struct amdgpu_ring_funcs jpeg_v4_0_dec_ring_vm_funcs = {
 722         .type = AMDGPU_RING_TYPE_VCN_JPEG,
 723         .align_mask = 0xf,
 724         .get_rptr = jpeg_v4_0_dec_ring_get_rptr,
 725         .get_wptr = jpeg_v4_0_dec_ring_get_wptr,
 726         .set_wptr = jpeg_v4_0_dec_ring_set_wptr,
 727         .emit_frame_size =
 728                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
 729                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
 730                 8 + /* jpeg_v4_0_dec_ring_emit_vm_flush */
 731                 18 + 18 + /* jpeg_v4_0_dec_ring_emit_fence x2 vm fence */
 732                 8 + 16,
 733         .emit_ib_size = 22, /* jpeg_v4_0_dec_ring_emit_ib */
 734         .emit_ib = jpeg_v2_0_dec_ring_emit_ib,
 735         .emit_fence = jpeg_v2_0_dec_ring_emit_fence,
 736         .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush,
 737         .test_ring = amdgpu_jpeg_dec_ring_test_ring,
 738         .test_ib = amdgpu_jpeg_dec_ring_test_ib,
 739         .insert_nop = jpeg_v2_0_dec_ring_nop,
 740         .insert_start = jpeg_v2_0_dec_ring_insert_start,
 741         .insert_end = jpeg_v2_0_dec_ring_insert_end,
 742         .pad_ib = amdgpu_ring_generic_pad_ib,
 743         .begin_use = amdgpu_jpeg_ring_begin_use,
 744         .end_use = amdgpu_jpeg_ring_end_use,
 745         .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,
 746         .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,
 747         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
 748 };
 749
 750 static void jpeg_v4_0_set_dec_ring_funcs(struct amdgpu_device *adev)
 751 {
 752         adev->jpeg.inst->ring_dec.funcs = &jpeg_v4_0_dec_ring_vm_funcs;
 753         DRM_DEV_INFO(adev->dev, "JPEG decode is enabled in VM mode\n");
 754 }
 755
 756 static const struct amdgpu_irq_src_funcs jpeg_v4_0_irq_funcs = {
 757         .set = jpeg_v4_0_set_interrupt_state,
 758         .process = jpeg_v4_0_process_interrupt,
 759 };
 760
 761 static const struct amdgpu_irq_src_funcs jpeg_v4_0_ras_irq_funcs = {
 762         .set = jpeg_v4_0_set_ras_interrupt_state,
 763         .process = amdgpu_jpeg_process_poison_irq,
 764 };
 765
 766 static void jpeg_v4_0_set_irq_funcs(struct amdgpu_device *adev)
 767 {
 768         adev->jpeg.inst->irq.num_types = 1;
 769         adev->jpeg.inst->irq.funcs = &jpeg_v4_0_irq_funcs;
 770
 771         adev->jpeg.inst->ras_poison_irq.num_types = 1;
 772         adev->jpeg.inst->ras_poison_irq.funcs = &jpeg_v4_0_ras_irq_funcs;
 773 }
 774
 775 const struct amdgpu_ip_block_version jpeg_v4_0_ip_block = {
 776         .type = AMD_IP_BLOCK_TYPE_JPEG,
 777         .major = 4,
 778         .minor = 0,
 779         .rev = 0,
 780         .funcs = &jpeg_v4_0_ip_funcs,
 781 };
 782
 783 static uint32_t jpeg_v4_0_query_poison_by_instance(struct amdgpu_device *adev,
 784                 uint32_t instance, uint32_t sub_block)
 785 {
 786         uint32_t poison_stat = 0, reg_value = 0;
 787
 788         switch (sub_block) {
 789         case AMDGPU_JPEG_V4_0_JPEG0:
 790                 reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG0_STATUS);
 791                 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG0_STATUS, POISONED_PF);
 792                 break;
 793         case AMDGPU_JPEG_V4_0_JPEG1:
 794                 reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG1_STATUS);
 795                 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG1_STATUS, POISONED_PF);
 796                 break;
 797         default:
 798                 break;
 799         }
 800
 801         if (poison_stat)
 802                 dev_info(adev->dev, "Poison detected in JPEG%d sub_block%d\n",
 803                         instance, sub_block);
 804
 805         return poison_stat;
 806 }
 807
 808 static bool jpeg_v4_0_query_ras_poison_status(struct amdgpu_device *adev)
 809 {
 810         uint32_t inst = 0, sub = 0, poison_stat = 0;
 811
 812         for (inst = 0; inst < adev->jpeg.num_jpeg_inst; inst++)
 813                 for (sub = 0; sub < AMDGPU_JPEG_V4_0_MAX_SUB_BLOCK; sub++)
 814                         poison_stat +=
 815                                 jpeg_v4_0_query_poison_by_instance(adev, inst, sub);
 816
 817         return !!poison_stat;
 818 }
 819
 820 const struct amdgpu_ras_block_hw_ops jpeg_v4_0_ras_hw_ops = {
 821         .query_poison_status = jpeg_v4_0_query_ras_poison_status,
 822 };
 823
 824 static struct amdgpu_jpeg_ras jpeg_v4_0_ras = {
 825         .ras_block = {
 826                 .hw_ops = &jpeg_v4_0_ras_hw_ops,
 827                 .ras_late_init = amdgpu_jpeg_ras_late_init,
 828         },
 829 };
 830
 831 static void jpeg_v4_0_set_ras_funcs(struct amdgpu_device *adev)
 832 {
 833         switch (adev->ip_versions[JPEG_HWIP][0]) {
 834         case IP_VERSION(4, 0, 0):
 835                 adev->jpeg.ras = &jpeg_v4_0_ras;
 836                 break;
 837         default:
 838                 break;
 839         }
 840 }