2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "amdgpu_jpeg.h"
28 #include "jpeg_v2_0.h"
29 #include "jpeg_v2_5.h"
31 #include "vcn/vcn_2_5_offset.h"
32 #include "vcn/vcn_2_5_sh_mask.h"
33 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
35 #define mmUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f
37 #define JPEG25_MAX_HW_INSTANCES_ARCTURUS 2
39 static void jpeg_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev);
40 static void jpeg_v2_5_set_irq_funcs(struct amdgpu_device *adev);
41 static int jpeg_v2_5_set_powergating_state(void *handle,
42 enum amd_powergating_state state);
43 static void jpeg_v2_5_set_ras_funcs(struct amdgpu_device *adev);
45 static int amdgpu_ih_clientid_jpeg[] = {
46 SOC15_IH_CLIENTID_VCN,
47 SOC15_IH_CLIENTID_VCN1
51 * jpeg_v2_5_early_init - set function pointers
53 * @handle: amdgpu_device pointer
55 * Set ring and irq function pointers
57 static int jpeg_v2_5_early_init(void *handle)
59 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
63 adev->jpeg.num_jpeg_inst = JPEG25_MAX_HW_INSTANCES_ARCTURUS;
64 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
65 harvest = RREG32_SOC15(JPEG, i, mmCC_UVD_HARVESTING);
66 if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)
67 adev->jpeg.harvest_config |= 1 << i;
69 if (adev->jpeg.harvest_config == (AMDGPU_JPEG_HARVEST_JPEG0 |
70 AMDGPU_JPEG_HARVEST_JPEG1))
73 jpeg_v2_5_set_dec_ring_funcs(adev);
74 jpeg_v2_5_set_irq_funcs(adev);
75 jpeg_v2_5_set_ras_funcs(adev);
81 * jpeg_v2_5_sw_init - sw init for JPEG block
83 * @handle: amdgpu_device pointer
85 * Load firmware and sw initialization
87 static int jpeg_v2_5_sw_init(void *handle)
89 struct amdgpu_ring *ring;
91 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
93 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
94 if (adev->jpeg.harvest_config & (1 << i))
98 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_jpeg[i],
99 VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst[i].irq);
103 /* JPEG DJPEG POISON EVENT */
104 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_jpeg[i],
105 VCN_2_6__SRCID_DJPEG0_POISON, &adev->jpeg.inst[i].ras_poison_irq);
109 /* JPEG EJPEG POISON EVENT */
110 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_jpeg[i],
111 VCN_2_6__SRCID_EJPEG0_POISON, &adev->jpeg.inst[i].ras_poison_irq);
116 r = amdgpu_jpeg_sw_init(adev);
120 r = amdgpu_jpeg_resume(adev);
124 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
125 if (adev->jpeg.harvest_config & (1 << i))
128 ring = &adev->jpeg.inst[i].ring_dec;
129 ring->use_doorbell = true;
130 if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(2, 5, 0))
131 ring->vm_hub = AMDGPU_MMHUB_1;
133 ring->vm_hub = AMDGPU_MMHUB_0;
134 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + 8 * i;
135 sprintf(ring->name, "jpeg_dec_%d", i);
136 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst[i].irq,
137 0, AMDGPU_RING_PRIO_DEFAULT, NULL);
141 adev->jpeg.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;
142 adev->jpeg.inst[i].external.jpeg_pitch = SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_PITCH);
145 r = amdgpu_jpeg_ras_sw_init(adev);
153 * jpeg_v2_5_sw_fini - sw fini for JPEG block
155 * @handle: amdgpu_device pointer
157 * JPEG suspend and free up sw allocation
159 static int jpeg_v2_5_sw_fini(void *handle)
162 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
164 r = amdgpu_jpeg_suspend(adev);
168 r = amdgpu_jpeg_sw_fini(adev);
174 * jpeg_v2_5_hw_init - start and test JPEG block
176 * @handle: amdgpu_device pointer
179 static int jpeg_v2_5_hw_init(void *handle)
181 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
182 struct amdgpu_ring *ring;
185 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
186 if (adev->jpeg.harvest_config & (1 << i))
189 ring = &adev->jpeg.inst[i].ring_dec;
190 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
191 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i, i);
193 r = amdgpu_ring_test_helper(ring);
198 DRM_INFO("JPEG decode initialized successfully.\n");
204 * jpeg_v2_5_hw_fini - stop the hardware block
206 * @handle: amdgpu_device pointer
208 * Stop the JPEG block, mark ring as not ready any more
210 static int jpeg_v2_5_hw_fini(void *handle)
212 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
215 cancel_delayed_work_sync(&adev->vcn.idle_work);
217 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
218 if (adev->jpeg.harvest_config & (1 << i))
221 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
222 RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS))
223 jpeg_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
225 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG))
226 amdgpu_irq_put(adev, &adev->jpeg.inst[i].ras_poison_irq, 0);
233 * jpeg_v2_5_suspend - suspend JPEG block
235 * @handle: amdgpu_device pointer
237 * HW fini and suspend JPEG block
239 static int jpeg_v2_5_suspend(void *handle)
241 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
244 r = jpeg_v2_5_hw_fini(adev);
248 r = amdgpu_jpeg_suspend(adev);
254 * jpeg_v2_5_resume - resume JPEG block
256 * @handle: amdgpu_device pointer
258 * Resume firmware and hw init JPEG block
260 static int jpeg_v2_5_resume(void *handle)
262 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
265 r = amdgpu_jpeg_resume(adev);
269 r = jpeg_v2_5_hw_init(adev);
274 static void jpeg_v2_5_disable_clock_gating(struct amdgpu_device *adev, int inst)
278 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL);
279 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)
280 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
282 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
284 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
285 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
286 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL, data);
288 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE);
289 data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK
290 | JPEG_CGC_GATE__JPEG2_DEC_MASK
291 | JPEG_CGC_GATE__JMCIF_MASK
292 | JPEG_CGC_GATE__JRBBM_MASK);
293 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE, data);
295 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL);
296 data &= ~(JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK
297 | JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK
298 | JPEG_CGC_CTRL__JMCIF_MODE_MASK
299 | JPEG_CGC_CTRL__JRBBM_MODE_MASK);
300 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL, data);
303 static void jpeg_v2_5_enable_clock_gating(struct amdgpu_device *adev, int inst)
307 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE);
308 data |= (JPEG_CGC_GATE__JPEG_DEC_MASK
309 |JPEG_CGC_GATE__JPEG2_DEC_MASK
310 |JPEG_CGC_GATE__JPEG_ENC_MASK
311 |JPEG_CGC_GATE__JMCIF_MASK
312 |JPEG_CGC_GATE__JRBBM_MASK);
313 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE, data);
317 * jpeg_v2_5_start - start JPEG block
319 * @adev: amdgpu_device pointer
321 * Setup and start the JPEG block
323 static int jpeg_v2_5_start(struct amdgpu_device *adev)
325 struct amdgpu_ring *ring;
328 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
329 if (adev->jpeg.harvest_config & (1 << i))
332 ring = &adev->jpeg.inst[i].ring_dec;
333 /* disable anti hang mechanism */
334 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS), 0,
335 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
337 /* JPEG disable CGC */
338 jpeg_v2_5_disable_clock_gating(adev, i);
340 /* MJPEG global tiling registers */
341 WREG32_SOC15(JPEG, i, mmJPEG_DEC_GFX8_ADDR_CONFIG,
342 adev->gfx.config.gb_addr_config);
343 WREG32_SOC15(JPEG, i, mmJPEG_DEC_GFX10_ADDR_CONFIG,
344 adev->gfx.config.gb_addr_config);
346 /* enable JMI channel */
347 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL), 0,
348 ~UVD_JMI_CNTL__SOFT_RESET_MASK);
350 /* enable System Interrupt for JRBC */
351 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmJPEG_SYS_INT_EN),
352 JPEG_SYS_INT_EN__DJRBC_MASK,
353 ~JPEG_SYS_INT_EN__DJRBC_MASK);
355 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_VMID, 0);
356 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
357 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
358 lower_32_bits(ring->gpu_addr));
359 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
360 upper_32_bits(ring->gpu_addr));
361 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_RPTR, 0);
362 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR, 0);
363 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_CNTL, 0x00000002L);
364 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4);
365 ring->wptr = RREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR);
372 * jpeg_v2_5_stop - stop JPEG block
374 * @adev: amdgpu_device pointer
376 * stop the JPEG block
378 static int jpeg_v2_5_stop(struct amdgpu_device *adev)
382 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
383 if (adev->jpeg.harvest_config & (1 << i))
387 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL),
388 UVD_JMI_CNTL__SOFT_RESET_MASK,
389 ~UVD_JMI_CNTL__SOFT_RESET_MASK);
391 jpeg_v2_5_enable_clock_gating(adev, i);
393 /* enable anti hang mechanism */
394 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS),
395 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK,
396 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
403 * jpeg_v2_5_dec_ring_get_rptr - get read pointer
405 * @ring: amdgpu_ring pointer
407 * Returns the current hardware read pointer
409 static uint64_t jpeg_v2_5_dec_ring_get_rptr(struct amdgpu_ring *ring)
411 struct amdgpu_device *adev = ring->adev;
413 return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_RPTR);
417 * jpeg_v2_5_dec_ring_get_wptr - get write pointer
419 * @ring: amdgpu_ring pointer
421 * Returns the current hardware write pointer
423 static uint64_t jpeg_v2_5_dec_ring_get_wptr(struct amdgpu_ring *ring)
425 struct amdgpu_device *adev = ring->adev;
427 if (ring->use_doorbell)
428 return *ring->wptr_cpu_addr;
430 return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR);
434 * jpeg_v2_5_dec_ring_set_wptr - set write pointer
436 * @ring: amdgpu_ring pointer
438 * Commits the write pointer to the hardware
440 static void jpeg_v2_5_dec_ring_set_wptr(struct amdgpu_ring *ring)
442 struct amdgpu_device *adev = ring->adev;
444 if (ring->use_doorbell) {
445 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
446 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
448 WREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
453 * jpeg_v2_6_dec_ring_insert_start - insert a start command
455 * @ring: amdgpu_ring pointer
457 * Write a start command to the ring.
459 static void jpeg_v2_6_dec_ring_insert_start(struct amdgpu_ring *ring)
461 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
462 0, 0, PACKETJ_TYPE0));
463 amdgpu_ring_write(ring, 0x6aa04); /* PCTL0_MMHUB_DEEPSLEEP_IB */
465 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
466 0, 0, PACKETJ_TYPE0));
467 amdgpu_ring_write(ring, 0x80000000 | (1 << (ring->me * 2 + 14)));
471 * jpeg_v2_6_dec_ring_insert_end - insert a end command
473 * @ring: amdgpu_ring pointer
475 * Write a end command to the ring.
477 static void jpeg_v2_6_dec_ring_insert_end(struct amdgpu_ring *ring)
479 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
480 0, 0, PACKETJ_TYPE0));
481 amdgpu_ring_write(ring, 0x6aa04); /* PCTL0_MMHUB_DEEPSLEEP_IB */
483 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
484 0, 0, PACKETJ_TYPE0));
485 amdgpu_ring_write(ring, (1 << (ring->me * 2 + 14)));
488 static bool jpeg_v2_5_is_idle(void *handle)
490 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
493 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
494 if (adev->jpeg.harvest_config & (1 << i))
497 ret &= (((RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS) &
498 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==
499 UVD_JRBC_STATUS__RB_JOB_DONE_MASK));
505 static int jpeg_v2_5_wait_for_idle(void *handle)
507 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
510 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
511 if (adev->jpeg.harvest_config & (1 << i))
514 ret = SOC15_WAIT_ON_RREG(JPEG, i, mmUVD_JRBC_STATUS,
515 UVD_JRBC_STATUS__RB_JOB_DONE_MASK,
516 UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
524 static int jpeg_v2_5_set_clockgating_state(void *handle,
525 enum amd_clockgating_state state)
527 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
528 bool enable = (state == AMD_CG_STATE_GATE);
531 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
532 if (adev->jpeg.harvest_config & (1 << i))
536 if (!jpeg_v2_5_is_idle(handle))
538 jpeg_v2_5_enable_clock_gating(adev, i);
540 jpeg_v2_5_disable_clock_gating(adev, i);
547 static int jpeg_v2_5_set_powergating_state(void *handle,
548 enum amd_powergating_state state)
550 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
553 if(state == adev->jpeg.cur_state)
556 if (state == AMD_PG_STATE_GATE)
557 ret = jpeg_v2_5_stop(adev);
559 ret = jpeg_v2_5_start(adev);
562 adev->jpeg.cur_state = state;
567 static int jpeg_v2_5_set_interrupt_state(struct amdgpu_device *adev,
568 struct amdgpu_irq_src *source,
570 enum amdgpu_interrupt_state state)
575 static int jpeg_v2_6_set_ras_interrupt_state(struct amdgpu_device *adev,
576 struct amdgpu_irq_src *source,
578 enum amdgpu_interrupt_state state)
583 static int jpeg_v2_5_process_interrupt(struct amdgpu_device *adev,
584 struct amdgpu_irq_src *source,
585 struct amdgpu_iv_entry *entry)
587 uint32_t ip_instance;
589 switch (entry->client_id) {
590 case SOC15_IH_CLIENTID_VCN:
593 case SOC15_IH_CLIENTID_VCN1:
597 DRM_ERROR("Unhandled client id: %d\n", entry->client_id);
601 DRM_DEBUG("IH: JPEG TRAP\n");
603 switch (entry->src_id) {
604 case VCN_2_0__SRCID__JPEG_DECODE:
605 amdgpu_fence_process(&adev->jpeg.inst[ip_instance].ring_dec);
608 DRM_ERROR("Unhandled interrupt: %d %d\n",
609 entry->src_id, entry->src_data[0]);
616 static const struct amd_ip_funcs jpeg_v2_5_ip_funcs = {
618 .early_init = jpeg_v2_5_early_init,
620 .sw_init = jpeg_v2_5_sw_init,
621 .sw_fini = jpeg_v2_5_sw_fini,
622 .hw_init = jpeg_v2_5_hw_init,
623 .hw_fini = jpeg_v2_5_hw_fini,
624 .suspend = jpeg_v2_5_suspend,
625 .resume = jpeg_v2_5_resume,
626 .is_idle = jpeg_v2_5_is_idle,
627 .wait_for_idle = jpeg_v2_5_wait_for_idle,
628 .check_soft_reset = NULL,
629 .pre_soft_reset = NULL,
631 .post_soft_reset = NULL,
632 .set_clockgating_state = jpeg_v2_5_set_clockgating_state,
633 .set_powergating_state = jpeg_v2_5_set_powergating_state,
636 static const struct amd_ip_funcs jpeg_v2_6_ip_funcs = {
638 .early_init = jpeg_v2_5_early_init,
640 .sw_init = jpeg_v2_5_sw_init,
641 .sw_fini = jpeg_v2_5_sw_fini,
642 .hw_init = jpeg_v2_5_hw_init,
643 .hw_fini = jpeg_v2_5_hw_fini,
644 .suspend = jpeg_v2_5_suspend,
645 .resume = jpeg_v2_5_resume,
646 .is_idle = jpeg_v2_5_is_idle,
647 .wait_for_idle = jpeg_v2_5_wait_for_idle,
648 .check_soft_reset = NULL,
649 .pre_soft_reset = NULL,
651 .post_soft_reset = NULL,
652 .set_clockgating_state = jpeg_v2_5_set_clockgating_state,
653 .set_powergating_state = jpeg_v2_5_set_powergating_state,
656 static const struct amdgpu_ring_funcs jpeg_v2_5_dec_ring_vm_funcs = {
657 .type = AMDGPU_RING_TYPE_VCN_JPEG,
659 .get_rptr = jpeg_v2_5_dec_ring_get_rptr,
660 .get_wptr = jpeg_v2_5_dec_ring_get_wptr,
661 .set_wptr = jpeg_v2_5_dec_ring_set_wptr,
663 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
664 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
665 8 + /* jpeg_v2_5_dec_ring_emit_vm_flush */
666 18 + 18 + /* jpeg_v2_5_dec_ring_emit_fence x2 vm fence */
668 .emit_ib_size = 22, /* jpeg_v2_5_dec_ring_emit_ib */
669 .emit_ib = jpeg_v2_0_dec_ring_emit_ib,
670 .emit_fence = jpeg_v2_0_dec_ring_emit_fence,
671 .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush,
672 .test_ring = amdgpu_jpeg_dec_ring_test_ring,
673 .test_ib = amdgpu_jpeg_dec_ring_test_ib,
674 .insert_nop = jpeg_v2_0_dec_ring_nop,
675 .insert_start = jpeg_v2_0_dec_ring_insert_start,
676 .insert_end = jpeg_v2_0_dec_ring_insert_end,
677 .pad_ib = amdgpu_ring_generic_pad_ib,
678 .begin_use = amdgpu_jpeg_ring_begin_use,
679 .end_use = amdgpu_jpeg_ring_end_use,
680 .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,
681 .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,
682 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
685 static const struct amdgpu_ring_funcs jpeg_v2_6_dec_ring_vm_funcs = {
686 .type = AMDGPU_RING_TYPE_VCN_JPEG,
688 .get_rptr = jpeg_v2_5_dec_ring_get_rptr,
689 .get_wptr = jpeg_v2_5_dec_ring_get_wptr,
690 .set_wptr = jpeg_v2_5_dec_ring_set_wptr,
692 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
693 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
694 8 + /* jpeg_v2_5_dec_ring_emit_vm_flush */
695 18 + 18 + /* jpeg_v2_5_dec_ring_emit_fence x2 vm fence */
697 .emit_ib_size = 22, /* jpeg_v2_5_dec_ring_emit_ib */
698 .emit_ib = jpeg_v2_0_dec_ring_emit_ib,
699 .emit_fence = jpeg_v2_0_dec_ring_emit_fence,
700 .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush,
701 .test_ring = amdgpu_jpeg_dec_ring_test_ring,
702 .test_ib = amdgpu_jpeg_dec_ring_test_ib,
703 .insert_nop = jpeg_v2_0_dec_ring_nop,
704 .insert_start = jpeg_v2_6_dec_ring_insert_start,
705 .insert_end = jpeg_v2_6_dec_ring_insert_end,
706 .pad_ib = amdgpu_ring_generic_pad_ib,
707 .begin_use = amdgpu_jpeg_ring_begin_use,
708 .end_use = amdgpu_jpeg_ring_end_use,
709 .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,
710 .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,
711 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
714 static void jpeg_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev)
718 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
719 if (adev->jpeg.harvest_config & (1 << i))
721 if (adev->asic_type == CHIP_ARCTURUS)
722 adev->jpeg.inst[i].ring_dec.funcs = &jpeg_v2_5_dec_ring_vm_funcs;
723 else /* CHIP_ALDEBARAN */
724 adev->jpeg.inst[i].ring_dec.funcs = &jpeg_v2_6_dec_ring_vm_funcs;
725 adev->jpeg.inst[i].ring_dec.me = i;
726 DRM_INFO("JPEG(%d) JPEG decode is enabled in VM mode\n", i);
730 static const struct amdgpu_irq_src_funcs jpeg_v2_5_irq_funcs = {
731 .set = jpeg_v2_5_set_interrupt_state,
732 .process = jpeg_v2_5_process_interrupt,
735 static const struct amdgpu_irq_src_funcs jpeg_v2_6_ras_irq_funcs = {
736 .set = jpeg_v2_6_set_ras_interrupt_state,
737 .process = amdgpu_jpeg_process_poison_irq,
740 static void jpeg_v2_5_set_irq_funcs(struct amdgpu_device *adev)
744 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
745 if (adev->jpeg.harvest_config & (1 << i))
748 adev->jpeg.inst[i].irq.num_types = 1;
749 adev->jpeg.inst[i].irq.funcs = &jpeg_v2_5_irq_funcs;
751 adev->jpeg.inst[i].ras_poison_irq.num_types = 1;
752 adev->jpeg.inst[i].ras_poison_irq.funcs = &jpeg_v2_6_ras_irq_funcs;
756 const struct amdgpu_ip_block_version jpeg_v2_5_ip_block =
758 .type = AMD_IP_BLOCK_TYPE_JPEG,
762 .funcs = &jpeg_v2_5_ip_funcs,
765 const struct amdgpu_ip_block_version jpeg_v2_6_ip_block =
767 .type = AMD_IP_BLOCK_TYPE_JPEG,
771 .funcs = &jpeg_v2_6_ip_funcs,
774 static uint32_t jpeg_v2_6_query_poison_by_instance(struct amdgpu_device *adev,
775 uint32_t instance, uint32_t sub_block)
777 uint32_t poison_stat = 0, reg_value = 0;
780 case AMDGPU_JPEG_V2_6_JPEG0:
781 reg_value = RREG32_SOC15(JPEG, instance, mmUVD_RAS_JPEG0_STATUS);
782 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG0_STATUS, POISONED_PF);
784 case AMDGPU_JPEG_V2_6_JPEG1:
785 reg_value = RREG32_SOC15(JPEG, instance, mmUVD_RAS_JPEG1_STATUS);
786 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG1_STATUS, POISONED_PF);
793 dev_info(adev->dev, "Poison detected in JPEG%d sub_block%d\n",
794 instance, sub_block);
799 static bool jpeg_v2_6_query_ras_poison_status(struct amdgpu_device *adev)
801 uint32_t inst = 0, sub = 0, poison_stat = 0;
803 for (inst = 0; inst < adev->jpeg.num_jpeg_inst; inst++)
804 for (sub = 0; sub < AMDGPU_JPEG_V2_6_MAX_SUB_BLOCK; sub++)
806 jpeg_v2_6_query_poison_by_instance(adev, inst, sub);
808 return !!poison_stat;
811 const struct amdgpu_ras_block_hw_ops jpeg_v2_6_ras_hw_ops = {
812 .query_poison_status = jpeg_v2_6_query_ras_poison_status,
815 static struct amdgpu_jpeg_ras jpeg_v2_6_ras = {
817 .hw_ops = &jpeg_v2_6_ras_hw_ops,
818 .ras_late_init = amdgpu_jpeg_ras_late_init,
822 static void jpeg_v2_5_set_ras_funcs(struct amdgpu_device *adev)
824 switch (adev->ip_versions[JPEG_HWIP][0]) {
825 case IP_VERSION(2, 6, 0):
826 adev->jpeg.ras = &jpeg_v2_6_ras;