drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <linux/pci.h>
  26
  27 #include <drm/drm_cache.h>
  28
  29 #include "amdgpu.h"
  30 #include "gmc_v9_0.h"
  31 #include "amdgpu_atomfirmware.h"
  32 #include "amdgpu_gem.h"
  33
  34 #include "gc/gc_9_0_sh_mask.h"
  35 #include "dce/dce_12_0_offset.h"
  36 #include "dce/dce_12_0_sh_mask.h"
  37 #include "vega10_enum.h"
  38 #include "mmhub/mmhub_1_0_offset.h"
  39 #include "athub/athub_1_0_sh_mask.h"
  40 #include "athub/athub_1_0_offset.h"
  41 #include "oss/osssys_4_0_offset.h"
  42
  43 #include "soc15.h"
  44 #include "soc15d.h"
  45 #include "soc15_common.h"
  46 #include "umc/umc_6_0_sh_mask.h"
  47
  48 #include "gfxhub_v1_0.h"
  49 #include "mmhub_v1_0.h"
  50 #include "athub_v1_0.h"
  51 #include "gfxhub_v1_1.h"
  52 #include "mmhub_v9_4.h"
  53 #include "mmhub_v1_7.h"
  54 #include "umc_v6_1.h"
  55 #include "umc_v6_0.h"
  56 #include "hdp_v4_0.h"
  57
  58 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
  59
  60 #include "amdgpu_ras.h"
  61 #include "amdgpu_xgmi.h"
  62
  63 /* add these here since we already include dce12 headers and these are for DCN */
  64 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x055d
  65 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
  66 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
  67 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
  68 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
  69 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
  70 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0                                                                  0x049d
  71 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX                                                         2
  72
  73
  74 static const char *gfxhub_client_ids[] = {
  75         "CB",
  76         "DB",
  77         "IA",
  78         "WD",
  79         "CPF",
  80         "CPC",
  81         "CPG",
  82         "RLC",
  83         "TCP",
  84         "SQC (inst)",
  85         "SQC (data)",
  86         "SQG",
  87         "PA",
  88 };
  89
  90 static const char *mmhub_client_ids_raven[][2] = {
  91         [0][0] = "MP1",
  92         [1][0] = "MP0",
  93         [2][0] = "VCN",
  94         [3][0] = "VCNU",
  95         [4][0] = "HDP",
  96         [5][0] = "DCE",
  97         [13][0] = "UTCL2",
  98         [19][0] = "TLS",
  99         [26][0] = "OSS",
 100         [27][0] = "SDMA0",
 101         [0][1] = "MP1",
 102         [1][1] = "MP0",
 103         [2][1] = "VCN",
 104         [3][1] = "VCNU",
 105         [4][1] = "HDP",
 106         [5][1] = "XDP",
 107         [6][1] = "DBGU0",
 108         [7][1] = "DCE",
 109         [8][1] = "DCEDWB0",
 110         [9][1] = "DCEDWB1",
 111         [26][1] = "OSS",
 112         [27][1] = "SDMA0",
 113 };
 114
 115 static const char *mmhub_client_ids_renoir[][2] = {
 116         [0][0] = "MP1",
 117         [1][0] = "MP0",
 118         [2][0] = "HDP",
 119         [4][0] = "DCEDMC",
 120         [5][0] = "DCEVGA",
 121         [13][0] = "UTCL2",
 122         [19][0] = "TLS",
 123         [26][0] = "OSS",
 124         [27][0] = "SDMA0",
 125         [28][0] = "VCN",
 126         [29][0] = "VCNU",
 127         [30][0] = "JPEG",
 128         [0][1] = "MP1",
 129         [1][1] = "MP0",
 130         [2][1] = "HDP",
 131         [3][1] = "XDP",
 132         [6][1] = "DBGU0",
 133         [7][1] = "DCEDMC",
 134         [8][1] = "DCEVGA",
 135         [9][1] = "DCEDWB",
 136         [26][1] = "OSS",
 137         [27][1] = "SDMA0",
 138         [28][1] = "VCN",
 139         [29][1] = "VCNU",
 140         [30][1] = "JPEG",
 141 };
 142
 143 static const char *mmhub_client_ids_vega10[][2] = {
 144         [0][0] = "MP0",
 145         [1][0] = "UVD",
 146         [2][0] = "UVDU",
 147         [3][0] = "HDP",
 148         [13][0] = "UTCL2",
 149         [14][0] = "OSS",
 150         [15][0] = "SDMA1",
 151         [32+0][0] = "VCE0",
 152         [32+1][0] = "VCE0U",
 153         [32+2][0] = "XDMA",
 154         [32+3][0] = "DCE",
 155         [32+4][0] = "MP1",
 156         [32+14][0] = "SDMA0",
 157         [0][1] = "MP0",
 158         [1][1] = "UVD",
 159         [2][1] = "UVDU",
 160         [3][1] = "DBGU0",
 161         [4][1] = "HDP",
 162         [5][1] = "XDP",
 163         [14][1] = "OSS",
 164         [15][1] = "SDMA0",
 165         [32+0][1] = "VCE0",
 166         [32+1][1] = "VCE0U",
 167         [32+2][1] = "XDMA",
 168         [32+3][1] = "DCE",
 169         [32+4][1] = "DCEDWB",
 170         [32+5][1] = "MP1",
 171         [32+6][1] = "DBGU1",
 172         [32+14][1] = "SDMA1",
 173 };
 174
 175 static const char *mmhub_client_ids_vega12[][2] = {
 176         [0][0] = "MP0",
 177         [1][0] = "VCE0",
 178         [2][0] = "VCE0U",
 179         [3][0] = "HDP",
 180         [13][0] = "UTCL2",
 181         [14][0] = "OSS",
 182         [15][0] = "SDMA1",
 183         [32+0][0] = "DCE",
 184         [32+1][0] = "XDMA",
 185         [32+2][0] = "UVD",
 186         [32+3][0] = "UVDU",
 187         [32+4][0] = "MP1",
 188         [32+15][0] = "SDMA0",
 189         [0][1] = "MP0",
 190         [1][1] = "VCE0",
 191         [2][1] = "VCE0U",
 192         [3][1] = "DBGU0",
 193         [4][1] = "HDP",
 194         [5][1] = "XDP",
 195         [14][1] = "OSS",
 196         [15][1] = "SDMA0",
 197         [32+0][1] = "DCE",
 198         [32+1][1] = "DCEDWB",
 199         [32+2][1] = "XDMA",
 200         [32+3][1] = "UVD",
 201         [32+4][1] = "UVDU",
 202         [32+5][1] = "MP1",
 203         [32+6][1] = "DBGU1",
 204         [32+15][1] = "SDMA1",
 205 };
 206
 207 static const char *mmhub_client_ids_vega20[][2] = {
 208         [0][0] = "XDMA",
 209         [1][0] = "DCE",
 210         [2][0] = "VCE0",
 211         [3][0] = "VCE0U",
 212         [4][0] = "UVD",
 213         [5][0] = "UVD1U",
 214         [13][0] = "OSS",
 215         [14][0] = "HDP",
 216         [15][0] = "SDMA0",
 217         [32+0][0] = "UVD",
 218         [32+1][0] = "UVDU",
 219         [32+2][0] = "MP1",
 220         [32+3][0] = "MP0",
 221         [32+12][0] = "UTCL2",
 222         [32+14][0] = "SDMA1",
 223         [0][1] = "XDMA",
 224         [1][1] = "DCE",
 225         [2][1] = "DCEDWB",
 226         [3][1] = "VCE0",
 227         [4][1] = "VCE0U",
 228         [5][1] = "UVD1",
 229         [6][1] = "UVD1U",
 230         [7][1] = "DBGU0",
 231         [8][1] = "XDP",
 232         [13][1] = "OSS",
 233         [14][1] = "HDP",
 234         [15][1] = "SDMA0",
 235         [32+0][1] = "UVD",
 236         [32+1][1] = "UVDU",
 237         [32+2][1] = "DBGU1",
 238         [32+3][1] = "MP1",
 239         [32+4][1] = "MP0",
 240         [32+14][1] = "SDMA1",
 241 };
 242
 243 static const char *mmhub_client_ids_arcturus[][2] = {
 244         [0][0] = "DBGU1",
 245         [1][0] = "XDP",
 246         [2][0] = "MP1",
 247         [14][0] = "HDP",
 248         [171][0] = "JPEG",
 249         [172][0] = "VCN",
 250         [173][0] = "VCNU",
 251         [203][0] = "JPEG1",
 252         [204][0] = "VCN1",
 253         [205][0] = "VCN1U",
 254         [256][0] = "SDMA0",
 255         [257][0] = "SDMA1",
 256         [258][0] = "SDMA2",
 257         [259][0] = "SDMA3",
 258         [260][0] = "SDMA4",
 259         [261][0] = "SDMA5",
 260         [262][0] = "SDMA6",
 261         [263][0] = "SDMA7",
 262         [384][0] = "OSS",
 263         [0][1] = "DBGU1",
 264         [1][1] = "XDP",
 265         [2][1] = "MP1",
 266         [14][1] = "HDP",
 267         [171][1] = "JPEG",
 268         [172][1] = "VCN",
 269         [173][1] = "VCNU",
 270         [203][1] = "JPEG1",
 271         [204][1] = "VCN1",
 272         [205][1] = "VCN1U",
 273         [256][1] = "SDMA0",
 274         [257][1] = "SDMA1",
 275         [258][1] = "SDMA2",
 276         [259][1] = "SDMA3",
 277         [260][1] = "SDMA4",
 278         [261][1] = "SDMA5",
 279         [262][1] = "SDMA6",
 280         [263][1] = "SDMA7",
 281         [384][1] = "OSS",
 282 };
 283
 284 static const char *mmhub_client_ids_aldebaran[][2] = {
 285         [2][0] = "MP1",
 286         [3][0] = "MP0",
 287         [32+1][0] = "DBGU_IO0",
 288         [32+2][0] = "DBGU_IO2",
 289         [32+4][0] = "MPIO",
 290         [96+11][0] = "JPEG0",
 291         [96+12][0] = "VCN0",
 292         [96+13][0] = "VCNU0",
 293         [128+11][0] = "JPEG1",
 294         [128+12][0] = "VCN1",
 295         [128+13][0] = "VCNU1",
 296         [160+1][0] = "XDP",
 297         [160+14][0] = "HDP",
 298         [256+0][0] = "SDMA0",
 299         [256+1][0] = "SDMA1",
 300         [256+2][0] = "SDMA2",
 301         [256+3][0] = "SDMA3",
 302         [256+4][0] = "SDMA4",
 303         [384+0][0] = "OSS",
 304         [2][1] = "MP1",
 305         [3][1] = "MP0",
 306         [32+1][1] = "DBGU_IO0",
 307         [32+2][1] = "DBGU_IO2",
 308         [32+4][1] = "MPIO",
 309         [96+11][1] = "JPEG0",
 310         [96+12][1] = "VCN0",
 311         [96+13][1] = "VCNU0",
 312         [128+11][1] = "JPEG1",
 313         [128+12][1] = "VCN1",
 314         [128+13][1] = "VCNU1",
 315         [160+1][1] = "XDP",
 316         [160+14][1] = "HDP",
 317         [256+0][1] = "SDMA0",
 318         [256+1][1] = "SDMA1",
 319         [256+2][1] = "SDMA2",
 320         [256+3][1] = "SDMA3",
 321         [256+4][1] = "SDMA4",
 322         [384+0][1] = "OSS",
 323 };
 324
 325 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] =
 326 {
 327         SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa),
 328         SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565)
 329 };
 330
 331 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] =
 332 {
 333         SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800),
 334         SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008)
 335 };
 336
 337 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = {
 338         (0x000143c0 + 0x00000000),
 339         (0x000143c0 + 0x00000800),
 340         (0x000143c0 + 0x00001000),
 341         (0x000143c0 + 0x00001800),
 342         (0x000543c0 + 0x00000000),
 343         (0x000543c0 + 0x00000800),
 344         (0x000543c0 + 0x00001000),
 345         (0x000543c0 + 0x00001800),
 346         (0x000943c0 + 0x00000000),
 347         (0x000943c0 + 0x00000800),
 348         (0x000943c0 + 0x00001000),
 349         (0x000943c0 + 0x00001800),
 350         (0x000d43c0 + 0x00000000),
 351         (0x000d43c0 + 0x00000800),
 352         (0x000d43c0 + 0x00001000),
 353         (0x000d43c0 + 0x00001800),
 354         (0x001143c0 + 0x00000000),
 355         (0x001143c0 + 0x00000800),
 356         (0x001143c0 + 0x00001000),
 357         (0x001143c0 + 0x00001800),
 358         (0x001543c0 + 0x00000000),
 359         (0x001543c0 + 0x00000800),
 360         (0x001543c0 + 0x00001000),
 361         (0x001543c0 + 0x00001800),
 362         (0x001943c0 + 0x00000000),
 363         (0x001943c0 + 0x00000800),
 364         (0x001943c0 + 0x00001000),
 365         (0x001943c0 + 0x00001800),
 366         (0x001d43c0 + 0x00000000),
 367         (0x001d43c0 + 0x00000800),
 368         (0x001d43c0 + 0x00001000),
 369         (0x001d43c0 + 0x00001800),
 370 };
 371
 372 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = {
 373         (0x000143e0 + 0x00000000),
 374         (0x000143e0 + 0x00000800),
 375         (0x000143e0 + 0x00001000),
 376         (0x000143e0 + 0x00001800),
 377         (0x000543e0 + 0x00000000),
 378         (0x000543e0 + 0x00000800),
 379         (0x000543e0 + 0x00001000),
 380         (0x000543e0 + 0x00001800),
 381         (0x000943e0 + 0x00000000),
 382         (0x000943e0 + 0x00000800),
 383         (0x000943e0 + 0x00001000),
 384         (0x000943e0 + 0x00001800),
 385         (0x000d43e0 + 0x00000000),
 386         (0x000d43e0 + 0x00000800),
 387         (0x000d43e0 + 0x00001000),
 388         (0x000d43e0 + 0x00001800),
 389         (0x001143e0 + 0x00000000),
 390         (0x001143e0 + 0x00000800),
 391         (0x001143e0 + 0x00001000),
 392         (0x001143e0 + 0x00001800),
 393         (0x001543e0 + 0x00000000),
 394         (0x001543e0 + 0x00000800),
 395         (0x001543e0 + 0x00001000),
 396         (0x001543e0 + 0x00001800),
 397         (0x001943e0 + 0x00000000),
 398         (0x001943e0 + 0x00000800),
 399         (0x001943e0 + 0x00001000),
 400         (0x001943e0 + 0x00001800),
 401         (0x001d43e0 + 0x00000000),
 402         (0x001d43e0 + 0x00000800),
 403         (0x001d43e0 + 0x00001000),
 404         (0x001d43e0 + 0x00001800),
 405 };
 406
 407 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev,
 408                 struct amdgpu_irq_src *src,
 409                 unsigned type,
 410                 enum amdgpu_interrupt_state state)
 411 {
 412         u32 bits, i, tmp, reg;
 413
 414         /* Devices newer then VEGA10/12 shall have these programming
 415              sequences performed by PSP BL */
 416         if (adev->asic_type >= CHIP_VEGA20)
 417                 return 0;
 418
 419         bits = 0x7f;
 420
 421         switch (state) {
 422         case AMDGPU_IRQ_STATE_DISABLE:
 423                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
 424                         reg = ecc_umc_mcumc_ctrl_addrs[i];
 425                         tmp = RREG32(reg);
 426                         tmp &= ~bits;
 427                         WREG32(reg, tmp);
 428                 }
 429                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
 430                         reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
 431                         tmp = RREG32(reg);
 432                         tmp &= ~bits;
 433                         WREG32(reg, tmp);
 434                 }
 435                 break;
 436         case AMDGPU_IRQ_STATE_ENABLE:
 437                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
 438                         reg = ecc_umc_mcumc_ctrl_addrs[i];
 439                         tmp = RREG32(reg);
 440                         tmp |= bits;
 441                         WREG32(reg, tmp);
 442                 }
 443                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
 444                         reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
 445                         tmp = RREG32(reg);
 446                         tmp |= bits;
 447                         WREG32(reg, tmp);
 448                 }
 449                 break;
 450         default:
 451                 break;
 452         }
 453
 454         return 0;
 455 }
 456
 457 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
 458                                         struct amdgpu_irq_src *src,
 459                                         unsigned type,
 460                                         enum amdgpu_interrupt_state state)
 461 {
 462         struct amdgpu_vmhub *hub;
 463         u32 tmp, reg, bits, i, j;
 464
 465         bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 466                 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 467                 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 468                 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 469                 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 470                 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 471                 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
 472
 473         switch (state) {
 474         case AMDGPU_IRQ_STATE_DISABLE:
 475                 for (j = 0; j < adev->num_vmhubs; j++) {
 476                         hub = &adev->vmhub[j];
 477                         for (i = 0; i < 16; i++) {
 478                                 reg = hub->vm_context0_cntl + i;
 479                                 tmp = RREG32(reg);
 480                                 tmp &= ~bits;
 481                                 WREG32(reg, tmp);
 482                         }
 483                 }
 484                 break;
 485         case AMDGPU_IRQ_STATE_ENABLE:
 486                 for (j = 0; j < adev->num_vmhubs; j++) {
 487                         hub = &adev->vmhub[j];
 488                         for (i = 0; i < 16; i++) {
 489                                 reg = hub->vm_context0_cntl + i;
 490                                 tmp = RREG32(reg);
 491                                 tmp |= bits;
 492                                 WREG32(reg, tmp);
 493                         }
 494                 }
 495                 break;
 496         default:
 497                 break;
 498         }
 499
 500         return 0;
 501 }
 502
 503 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
 504                                       struct amdgpu_irq_src *source,
 505                                       struct amdgpu_iv_entry *entry)
 506 {
 507         bool retry_fault = !!(entry->src_data[1] & 0x80);
 508         uint32_t status = 0, cid = 0, rw = 0;
 509         struct amdgpu_task_info task_info;
 510         struct amdgpu_vmhub *hub;
 511         const char *mmhub_cid;
 512         const char *hub_name;
 513         u64 addr;
 514
 515         addr = (u64)entry->src_data[0] << 12;
 516         addr |= ((u64)entry->src_data[1] & 0xf) << 44;
 517
 518         if (retry_fault) {
 519                 /* Returning 1 here also prevents sending the IV to the KFD */
 520
 521                 /* Process it onyl if it's the first fault for this address */
 522                 if (entry->ih != &adev->irq.ih_soft &&
 523                     amdgpu_gmc_filter_faults(adev, addr, entry->pasid,
 524                                              entry->timestamp))
 525                         return 1;
 526
 527                 /* Delegate it to a different ring if the hardware hasn't
 528                  * already done it.
 529                  */
 530                 if (entry->ih == &adev->irq.ih) {
 531                         amdgpu_irq_delegate(adev, entry, 8);
 532                         return 1;
 533                 }
 534
 535                 /* Try to handle the recoverable page faults by filling page
 536                  * tables
 537                  */
 538                 if (amdgpu_vm_handle_fault(adev, entry->pasid, addr))
 539                         return 1;
 540         }
 541
 542         if (!printk_ratelimit())
 543                 return 0;
 544
 545         if (entry->client_id == SOC15_IH_CLIENTID_VMC) {
 546                 hub_name = "mmhub0";
 547                 hub = &adev->vmhub[AMDGPU_MMHUB_0];
 548         } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) {
 549                 hub_name = "mmhub1";
 550                 hub = &adev->vmhub[AMDGPU_MMHUB_1];
 551         } else {
 552                 hub_name = "gfxhub0";
 553                 hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 554         }
 555
 556         memset(&task_info, 0, sizeof(struct amdgpu_task_info));
 557         amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
 558
 559         dev_err(adev->dev,
 560                 "[%s] %s page fault (src_id:%u ring:%u vmid:%u "
 561                 "pasid:%u, for process %s pid %d thread %s pid %d)\n",
 562                 hub_name, retry_fault ? "retry" : "no-retry",
 563                 entry->src_id, entry->ring_id, entry->vmid,
 564                 entry->pasid, task_info.process_name, task_info.tgid,
 565                 task_info.task_name, task_info.pid);
 566         dev_err(adev->dev, "  in page starting at address 0x%016llx from IH client 0x%x (%s)\n",
 567                 addr, entry->client_id,
 568                 soc15_ih_clientid_name[entry->client_id]);
 569
 570         if (amdgpu_sriov_vf(adev))
 571                 return 0;
 572
 573         /*
 574          * Issue a dummy read to wait for the status register to
 575          * be updated to avoid reading an incorrect value due to
 576          * the new fast GRBM interface.
 577          */
 578         if ((entry->vmid_src == AMDGPU_GFXHUB_0) &&
 579             (adev->asic_type < CHIP_ALDEBARAN))
 580                 RREG32(hub->vm_l2_pro_fault_status);
 581
 582         status = RREG32(hub->vm_l2_pro_fault_status);
 583         cid = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, CID);
 584         rw = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, RW);
 585         WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
 586
 587
 588         dev_err(adev->dev,
 589                 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
 590                 status);
 591         if (hub == &adev->vmhub[AMDGPU_GFXHUB_0]) {
 592                 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
 593                         cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" :
 594                         gfxhub_client_ids[cid],
 595                         cid);
 596         } else {
 597                 switch (adev->asic_type) {
 598                 case CHIP_VEGA10:
 599                         mmhub_cid = mmhub_client_ids_vega10[cid][rw];
 600                         break;
 601                 case CHIP_VEGA12:
 602                         mmhub_cid = mmhub_client_ids_vega12[cid][rw];
 603                         break;
 604                 case CHIP_VEGA20:
 605                         mmhub_cid = mmhub_client_ids_vega20[cid][rw];
 606                         break;
 607                 case CHIP_ARCTURUS:
 608                         mmhub_cid = mmhub_client_ids_arcturus[cid][rw];
 609                         break;
 610                 case CHIP_RAVEN:
 611                         mmhub_cid = mmhub_client_ids_raven[cid][rw];
 612                         break;
 613                 case CHIP_RENOIR:
 614                         mmhub_cid = mmhub_client_ids_renoir[cid][rw];
 615                         break;
 616                 case CHIP_ALDEBARAN:
 617                         mmhub_cid = mmhub_client_ids_aldebaran[cid][rw];
 618                         break;
 619                 default:
 620                         mmhub_cid = NULL;
 621                         break;
 622                 }
 623                 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
 624                         mmhub_cid ? mmhub_cid : "unknown", cid);
 625         }
 626         dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
 627                 REG_GET_FIELD(status,
 628                 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
 629         dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
 630                 REG_GET_FIELD(status,
 631                 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
 632         dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
 633                 REG_GET_FIELD(status,
 634                 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
 635         dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
 636                 REG_GET_FIELD(status,
 637                 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
 638         dev_err(adev->dev, "\t RW: 0x%x\n", rw);
 639         return 0;
 640 }
 641
 642 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = {
 643         .set = gmc_v9_0_vm_fault_interrupt_state,
 644         .process = gmc_v9_0_process_interrupt,
 645 };
 646
 647
 648 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = {
 649         .set = gmc_v9_0_ecc_interrupt_state,
 650         .process = amdgpu_umc_process_ecc_irq,
 651 };
 652
 653 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
 654 {
 655         adev->gmc.vm_fault.num_types = 1;
 656         adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
 657
 658         if (!amdgpu_sriov_vf(adev) &&
 659             !adev->gmc.xgmi.connected_to_cpu) {
 660                 adev->gmc.ecc_irq.num_types = 1;
 661                 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs;
 662         }
 663 }
 664
 665 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid,
 666                                         uint32_t flush_type)
 667 {
 668         u32 req = 0;
 669
 670         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
 671                             PER_VMID_INVALIDATE_REQ, 1 << vmid);
 672         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
 673         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
 674         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
 675         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
 676         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
 677         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
 678         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
 679                             CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
 680
 681         return req;
 682 }
 683
 684 /**
 685  * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore
 686  *
 687  * @adev: amdgpu_device pointer
 688  * @vmhub: vmhub type
 689  *
 690  */
 691 static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev,
 692                                        uint32_t vmhub)
 693 {
 694         if (adev->asic_type == CHIP_ALDEBARAN)
 695                 return false;
 696
 697         return ((vmhub == AMDGPU_MMHUB_0 ||
 698                  vmhub == AMDGPU_MMHUB_1) &&
 699                 (!amdgpu_sriov_vf(adev)) &&
 700                 (!(!(adev->apu_flags & AMD_APU_IS_RAVEN2) &&
 701                    (adev->apu_flags & AMD_APU_IS_PICASSO))));
 702 }
 703
 704 static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,
 705                                         uint8_t vmid, uint16_t *p_pasid)
 706 {
 707         uint32_t value;
 708
 709         value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
 710                      + vmid);
 711         *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
 712
 713         return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
 714 }
 715
 716 /*
 717  * GART
 718  * VMID 0 is the physical GPU addresses as used by the kernel.
 719  * VMIDs 1-15 are used for userspace clients and are handled
 720  * by the amdgpu vm/hsa code.
 721  */
 722
 723 /**
 724  * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type
 725  *
 726  * @adev: amdgpu_device pointer
 727  * @vmid: vm instance to flush
 728  * @vmhub: which hub to flush
 729  * @flush_type: the flush type
 730  *
 731  * Flush the TLB for the requested page table using certain type.
 732  */
 733 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
 734                                         uint32_t vmhub, uint32_t flush_type)
 735 {
 736         bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub);
 737         const unsigned eng = 17;
 738         u32 j, inv_req, inv_req2, tmp;
 739         struct amdgpu_vmhub *hub;
 740
 741         BUG_ON(vmhub >= adev->num_vmhubs);
 742
 743         hub = &adev->vmhub[vmhub];
 744         if (adev->gmc.xgmi.num_physical_nodes &&
 745             adev->asic_type == CHIP_VEGA20) {
 746                 /* Vega20+XGMI caches PTEs in TC and TLB. Add a
 747                  * heavy-weight TLB flush (type 2), which flushes
 748                  * both. Due to a race condition with concurrent
 749                  * memory accesses using the same TLB cache line, we
 750                  * still need a second TLB flush after this.
 751                  */
 752                 inv_req = gmc_v9_0_get_invalidate_req(vmid, 2);
 753                 inv_req2 = gmc_v9_0_get_invalidate_req(vmid, flush_type);
 754         } else {
 755                 inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type);
 756                 inv_req2 = 0;
 757         }
 758
 759         /* This is necessary for a HW workaround under SRIOV as well
 760          * as GFXOFF under bare metal
 761          */
 762         if (adev->gfx.kiq.ring.sched.ready &&
 763             (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&
 764             down_read_trylock(&adev->reset_sem)) {
 765                 uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
 766                 uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
 767
 768                 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req,
 769                                                    1 << vmid);
 770                 up_read(&adev->reset_sem);
 771                 return;
 772         }
 773
 774         spin_lock(&adev->gmc.invalidate_lock);
 775
 776         /*
 777          * It may lose gpuvm invalidate acknowldege state across power-gating
 778          * off cycle, add semaphore acquire before invalidation and semaphore
 779          * release after invalidation to avoid entering power gated state
 780          * to WA the Issue
 781          */
 782
 783         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 784         if (use_semaphore) {
 785                 for (j = 0; j < adev->usec_timeout; j++) {
 786                         /* a read return value of 1 means semaphore acuqire */
 787                         tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem +
 788                                             hub->eng_distance * eng);
 789                         if (tmp & 0x1)
 790                                 break;
 791                         udelay(1);
 792                 }
 793
 794                 if (j >= adev->usec_timeout)
 795                         DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
 796         }
 797
 798         do {
 799                 WREG32_NO_KIQ(hub->vm_inv_eng0_req +
 800                               hub->eng_distance * eng, inv_req);
 801
 802                 /*
 803                  * Issue a dummy read to wait for the ACK register to
 804                  * be cleared to avoid a false ACK due to the new fast
 805                  * GRBM interface.
 806                  */
 807                 if ((vmhub == AMDGPU_GFXHUB_0) &&
 808                     (adev->asic_type < CHIP_ALDEBARAN))
 809                         RREG32_NO_KIQ(hub->vm_inv_eng0_req +
 810                                       hub->eng_distance * eng);
 811
 812                 for (j = 0; j < adev->usec_timeout; j++) {
 813                         tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack +
 814                                             hub->eng_distance * eng);
 815                         if (tmp & (1 << vmid))
 816                                 break;
 817                         udelay(1);
 818                 }
 819
 820                 inv_req = inv_req2;
 821                 inv_req2 = 0;
 822         } while (inv_req);
 823
 824         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 825         if (use_semaphore)
 826                 /*
 827                  * add semaphore release after invalidation,
 828                  * write with 0 means semaphore release
 829                  */
 830                 WREG32_NO_KIQ(hub->vm_inv_eng0_sem +
 831                               hub->eng_distance * eng, 0);
 832
 833         spin_unlock(&adev->gmc.invalidate_lock);
 834
 835         if (j < adev->usec_timeout)
 836                 return;
 837
 838         DRM_ERROR("Timeout waiting for VM flush ACK!\n");
 839 }
 840
 841 /**
 842  * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid
 843  *
 844  * @adev: amdgpu_device pointer
 845  * @pasid: pasid to be flush
 846  * @flush_type: the flush type
 847  * @all_hub: flush all hubs
 848  *
 849  * Flush the TLB for the requested pasid.
 850  */
 851 static int gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
 852                                         uint16_t pasid, uint32_t flush_type,
 853                                         bool all_hub)
 854 {
 855         int vmid, i;
 856         signed long r;
 857         uint32_t seq;
 858         uint16_t queried_pasid;
 859         bool ret;
 860         struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
 861         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
 862
 863         if (amdgpu_in_reset(adev))
 864                 return -EIO;
 865
 866         if (ring->sched.ready && down_read_trylock(&adev->reset_sem)) {
 867                 /* Vega20+XGMI caches PTEs in TC and TLB. Add a
 868                  * heavy-weight TLB flush (type 2), which flushes
 869                  * both. Due to a race condition with concurrent
 870                  * memory accesses using the same TLB cache line, we
 871                  * still need a second TLB flush after this.
 872                  */
 873                 bool vega20_xgmi_wa = (adev->gmc.xgmi.num_physical_nodes &&
 874                                        adev->asic_type == CHIP_VEGA20);
 875                 /* 2 dwords flush + 8 dwords fence */
 876                 unsigned int ndw = kiq->pmf->invalidate_tlbs_size + 8;
 877
 878                 if (vega20_xgmi_wa)
 879                         ndw += kiq->pmf->invalidate_tlbs_size;
 880
 881                 spin_lock(&adev->gfx.kiq.ring_lock);
 882                 /* 2 dwords flush + 8 dwords fence */
 883                 amdgpu_ring_alloc(ring, ndw);
 884                 if (vega20_xgmi_wa)
 885                         kiq->pmf->kiq_invalidate_tlbs(ring,
 886                                                       pasid, 2, all_hub);
 887                 kiq->pmf->kiq_invalidate_tlbs(ring,
 888                                         pasid, flush_type, all_hub);
 889                 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
 890                 if (r) {
 891                         amdgpu_ring_undo(ring);
 892                         spin_unlock(&adev->gfx.kiq.ring_lock);
 893                         up_read(&adev->reset_sem);
 894                         return -ETIME;
 895                 }
 896
 897                 amdgpu_ring_commit(ring);
 898                 spin_unlock(&adev->gfx.kiq.ring_lock);
 899                 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
 900                 if (r < 1) {
 901                         dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r);
 902                         up_read(&adev->reset_sem);
 903                         return -ETIME;
 904                 }
 905                 up_read(&adev->reset_sem);
 906                 return 0;
 907         }
 908
 909         for (vmid = 1; vmid < 16; vmid++) {
 910
 911                 ret = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
 912                                 &queried_pasid);
 913                 if (ret && queried_pasid == pasid) {
 914                         if (all_hub) {
 915                                 for (i = 0; i < adev->num_vmhubs; i++)
 916                                         gmc_v9_0_flush_gpu_tlb(adev, vmid,
 917                                                         i, flush_type);
 918                         } else {
 919                                 gmc_v9_0_flush_gpu_tlb(adev, vmid,
 920                                                 AMDGPU_GFXHUB_0, flush_type);
 921                         }
 922                         break;
 923                 }
 924         }
 925
 926         return 0;
 927
 928 }
 929
 930 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 931                                             unsigned vmid, uint64_t pd_addr)
 932 {
 933         bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub);
 934         struct amdgpu_device *adev = ring->adev;
 935         struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
 936         uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0);
 937         unsigned eng = ring->vm_inv_eng;
 938
 939         /*
 940          * It may lose gpuvm invalidate acknowldege state across power-gating
 941          * off cycle, add semaphore acquire before invalidation and semaphore
 942          * release after invalidation to avoid entering power gated state
 943          * to WA the Issue
 944          */
 945
 946         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 947         if (use_semaphore)
 948                 /* a read return value of 1 means semaphore acuqire */
 949                 amdgpu_ring_emit_reg_wait(ring,
 950                                           hub->vm_inv_eng0_sem +
 951                                           hub->eng_distance * eng, 0x1, 0x1);
 952
 953         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
 954                               (hub->ctx_addr_distance * vmid),
 955                               lower_32_bits(pd_addr));
 956
 957         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
 958                               (hub->ctx_addr_distance * vmid),
 959                               upper_32_bits(pd_addr));
 960
 961         amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req +
 962                                             hub->eng_distance * eng,
 963                                             hub->vm_inv_eng0_ack +
 964                                             hub->eng_distance * eng,
 965                                             req, 1 << vmid);
 966
 967         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 968         if (use_semaphore)
 969                 /*
 970                  * add semaphore release after invalidation,
 971                  * write with 0 means semaphore release
 972                  */
 973                 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem +
 974                                       hub->eng_distance * eng, 0);
 975
 976         return pd_addr;
 977 }
 978
 979 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
 980                                         unsigned pasid)
 981 {
 982         struct amdgpu_device *adev = ring->adev;
 983         uint32_t reg;
 984
 985         /* Do nothing because there's no lut register for mmhub1. */
 986         if (ring->funcs->vmhub == AMDGPU_MMHUB_1)
 987                 return;
 988
 989         if (ring->funcs->vmhub == AMDGPU_GFXHUB_0)
 990                 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
 991         else
 992                 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
 993
 994         amdgpu_ring_emit_wreg(ring, reg, pasid);
 995 }
 996
 997 /*
 998  * PTE format on VEGA 10:
 999  * 63:59 reserved
1000  * 58:57 mtype
1001  * 56 F
1002  * 55 L
1003  * 54 P
1004  * 53 SW
1005  * 52 T
1006  * 50:48 reserved
1007  * 47:12 4k physical page base address
1008  * 11:7 fragment
1009  * 6 write
1010  * 5 read
1011  * 4 exe
1012  * 3 Z
1013  * 2 snooped
1014  * 1 system
1015  * 0 valid
1016  *
1017  * PDE format on VEGA 10:
1018  * 63:59 block fragment size
1019  * 58:55 reserved
1020  * 54 P
1021  * 53:48 reserved
1022  * 47:6 physical base address of PD or PTE
1023  * 5:3 reserved
1024  * 2 C
1025  * 1 system
1026  * 0 valid
1027  */
1028
1029 static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)
1030
1031 {
1032         switch (flags) {
1033         case AMDGPU_VM_MTYPE_DEFAULT:
1034                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
1035         case AMDGPU_VM_MTYPE_NC:
1036                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
1037         case AMDGPU_VM_MTYPE_WC:
1038                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_WC);
1039         case AMDGPU_VM_MTYPE_RW:
1040                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_RW);
1041         case AMDGPU_VM_MTYPE_CC:
1042                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_CC);
1043         case AMDGPU_VM_MTYPE_UC:
1044                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_UC);
1045         default:
1046                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
1047         }
1048 }
1049
1050 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
1051                                 uint64_t *addr, uint64_t *flags)
1052 {
1053         if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
1054                 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr);
1055         BUG_ON(*addr & 0xFFFF00000000003FULL);
1056
1057         if (!adev->gmc.translate_further)
1058                 return;
1059
1060         if (level == AMDGPU_VM_PDB1) {
1061                 /* Set the block fragment size */
1062                 if (!(*flags & AMDGPU_PDE_PTE))
1063                         *flags |= AMDGPU_PDE_BFS(0x9);
1064
1065         } else if (level == AMDGPU_VM_PDB0) {
1066                 if (*flags & AMDGPU_PDE_PTE)
1067                         *flags &= ~AMDGPU_PDE_PTE;
1068                 else
1069                         *flags |= AMDGPU_PTE_TF;
1070         }
1071 }
1072
1073 static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev,
1074                                 struct amdgpu_bo_va_mapping *mapping,
1075                                 uint64_t *flags)
1076 {
1077         *flags &= ~AMDGPU_PTE_EXECUTABLE;
1078         *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
1079
1080         *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
1081         *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK;
1082
1083         if (mapping->flags & AMDGPU_PTE_PRT) {
1084                 *flags |= AMDGPU_PTE_PRT;
1085                 *flags &= ~AMDGPU_PTE_VALID;
1086         }
1087
1088         if ((adev->asic_type == CHIP_ARCTURUS ||
1089             adev->asic_type == CHIP_ALDEBARAN) &&
1090             !(*flags & AMDGPU_PTE_SYSTEM) &&
1091             mapping->bo_va->is_xgmi)
1092                 *flags |= AMDGPU_PTE_SNOOPED;
1093
1094         if (adev->asic_type == CHIP_ALDEBARAN)
1095                 *flags |= mapping->flags & AMDGPU_PTE_SNOOPED;
1096 }
1097
1098 static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
1099 {
1100         u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
1101         unsigned size;
1102
1103         if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
1104                 size = AMDGPU_VBIOS_VGA_ALLOCATION;
1105         } else {
1106                 u32 viewport;
1107
1108                 switch (adev->asic_type) {
1109                 case CHIP_RAVEN:
1110                 case CHIP_RENOIR:
1111                         viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
1112                         size = (REG_GET_FIELD(viewport,
1113                                               HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
1114                                 REG_GET_FIELD(viewport,
1115                                               HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
1116                                 4);
1117                         break;
1118                 case CHIP_VEGA10:
1119                 case CHIP_VEGA12:
1120                 case CHIP_VEGA20:
1121                 default:
1122                         viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE);
1123                         size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
1124                                 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) *
1125                                 4);
1126                         break;
1127                 }
1128         }
1129
1130         return size;
1131 }
1132
1133 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
1134         .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
1135         .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid,
1136         .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,
1137         .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping,
1138         .map_mtype = gmc_v9_0_map_mtype,
1139         .get_vm_pde = gmc_v9_0_get_vm_pde,
1140         .get_vm_pte = gmc_v9_0_get_vm_pte,
1141         .get_vbios_fb_size = gmc_v9_0_get_vbios_fb_size,
1142 };
1143
1144 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev)
1145 {
1146         adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs;
1147 }
1148
1149 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
1150 {
1151         switch (adev->asic_type) {
1152         case CHIP_VEGA10:
1153                 adev->umc.funcs = &umc_v6_0_funcs;
1154                 break;
1155         case CHIP_VEGA20:
1156                 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
1157                 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
1158                 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
1159                 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20;
1160                 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
1161                 adev->umc.ras_funcs = &umc_v6_1_ras_funcs;
1162                 break;
1163         case CHIP_ARCTURUS:
1164                 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
1165                 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
1166                 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
1167                 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT;
1168                 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
1169                 adev->umc.ras_funcs = &umc_v6_1_ras_funcs;
1170                 break;
1171         default:
1172                 break;
1173         }
1174 }
1175
1176 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev)
1177 {
1178         switch (adev->asic_type) {
1179         case CHIP_ARCTURUS:
1180                 adev->mmhub.funcs = &mmhub_v9_4_funcs;
1181                 break;
1182         case CHIP_ALDEBARAN:
1183                 adev->mmhub.funcs = &mmhub_v1_7_funcs;
1184                 break;
1185         default:
1186                 adev->mmhub.funcs = &mmhub_v1_0_funcs;
1187                 break;
1188         }
1189 }
1190
1191 static void gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device *adev)
1192 {
1193         switch (adev->asic_type) {
1194         case CHIP_VEGA20:
1195                 adev->mmhub.ras_funcs = &mmhub_v1_0_ras_funcs;
1196                 break;
1197         case CHIP_ARCTURUS:
1198                 adev->mmhub.ras_funcs = &mmhub_v9_4_ras_funcs;
1199                 break;
1200         case CHIP_ALDEBARAN:
1201                 adev->mmhub.ras_funcs = &mmhub_v1_7_ras_funcs;
1202                 break;
1203         default:
1204                 /* mmhub ras is not available */
1205                 break;
1206         }
1207 }
1208
1209 static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev)
1210 {
1211         adev->gfxhub.funcs = &gfxhub_v1_0_funcs;
1212 }
1213
1214 static void gmc_v9_0_set_hdp_ras_funcs(struct amdgpu_device *adev)
1215 {
1216         adev->hdp.ras_funcs = &hdp_v4_0_ras_funcs;
1217 }
1218
1219 static int gmc_v9_0_early_init(void *handle)
1220 {
1221         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1222
1223         if (adev->asic_type == CHIP_VEGA20 ||
1224             adev->asic_type == CHIP_ARCTURUS)
1225                 adev->gmc.xgmi.supported = true;
1226
1227         if (adev->asic_type == CHIP_ALDEBARAN) {
1228                 adev->gmc.xgmi.supported = true;
1229                 adev->gmc.xgmi.connected_to_cpu =
1230                         adev->smuio.funcs->is_host_gpu_xgmi_supported(adev);
1231         }
1232
1233         gmc_v9_0_set_gmc_funcs(adev);
1234         gmc_v9_0_set_irq_funcs(adev);
1235         gmc_v9_0_set_umc_funcs(adev);
1236         gmc_v9_0_set_mmhub_funcs(adev);
1237         gmc_v9_0_set_mmhub_ras_funcs(adev);
1238         gmc_v9_0_set_gfxhub_funcs(adev);
1239         gmc_v9_0_set_hdp_ras_funcs(adev);
1240
1241         adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
1242         adev->gmc.shared_aperture_end =
1243                 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
1244         adev->gmc.private_aperture_start = 0x1000000000000000ULL;
1245         adev->gmc.private_aperture_end =
1246                 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
1247
1248         return 0;
1249 }
1250
1251 static int gmc_v9_0_late_init(void *handle)
1252 {
1253         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1254         int r;
1255
1256         r = amdgpu_gmc_allocate_vm_inv_eng(adev);
1257         if (r)
1258                 return r;
1259
1260         /*
1261          * Workaround performance drop issue with VBIOS enables partial
1262          * writes, while disables HBM ECC for vega10.
1263          */
1264         if (!amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_VEGA10)) {
1265                 if (!(adev->ras_enabled & (1 << AMDGPU_RAS_BLOCK__UMC))) {
1266                         if (adev->df.funcs->enable_ecc_force_par_wr_rmw)
1267                                 adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false);
1268                 }
1269         }
1270
1271         if (!amdgpu_persistent_edc_harvesting_supported(adev)) {
1272                 if (adev->mmhub.ras_funcs &&
1273                     adev->mmhub.ras_funcs->reset_ras_error_count)
1274                         adev->mmhub.ras_funcs->reset_ras_error_count(adev);
1275
1276                 if (adev->hdp.ras_funcs &&
1277                     adev->hdp.ras_funcs->reset_ras_error_count)
1278                         adev->hdp.ras_funcs->reset_ras_error_count(adev);
1279         }
1280
1281         r = amdgpu_gmc_ras_late_init(adev);
1282         if (r)
1283                 return r;
1284
1285         return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
1286 }
1287
1288 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
1289                                         struct amdgpu_gmc *mc)
1290 {
1291         u64 base = 0;
1292
1293         if (!amdgpu_sriov_vf(adev))
1294                 base = adev->mmhub.funcs->get_fb_location(adev);
1295
1296         /* add the xgmi offset of the physical node */
1297         base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
1298         if (adev->gmc.xgmi.connected_to_cpu) {
1299                 amdgpu_gmc_sysvm_location(adev, mc);
1300         } else {
1301                 amdgpu_gmc_vram_location(adev, mc, base);
1302                 amdgpu_gmc_gart_location(adev, mc);
1303                 amdgpu_gmc_agp_location(adev, mc);
1304         }
1305         /* base offset of vram pages */
1306         adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev);
1307
1308         /* XXX: add the xgmi offset of the physical node? */
1309         adev->vm_manager.vram_base_offset +=
1310                 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
1311 }
1312
1313 /**
1314  * gmc_v9_0_mc_init - initialize the memory controller driver params
1315  *
1316  * @adev: amdgpu_device pointer
1317  *
1318  * Look up the amount of vram, vram width, and decide how to place
1319  * vram and gart within the GPU's physical address space.
1320  * Returns 0 for success.
1321  */
1322 static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
1323 {
1324         int r;
1325
1326         /* size in MB on si */
1327         adev->gmc.mc_vram_size =
1328                 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
1329         adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
1330
1331         if (!(adev->flags & AMD_IS_APU) &&
1332             !adev->gmc.xgmi.connected_to_cpu) {
1333                 r = amdgpu_device_resize_fb_bar(adev);
1334                 if (r)
1335                         return r;
1336         }
1337         adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
1338         adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
1339
1340 #ifdef CONFIG_X86_64
1341         /*
1342          * AMD Accelerated Processing Platform (APP) supporting GPU-HOST xgmi
1343          * interface can use VRAM through here as it appears system reserved
1344          * memory in host address space.
1345          *
1346          * For APUs, VRAM is just the stolen system memory and can be accessed
1347          * directly.
1348          *
1349          * Otherwise, use the legacy Host Data Path (HDP) through PCIe BAR.
1350          */
1351
1352         /* check whether both host-gpu and gpu-gpu xgmi links exist */
1353         if ((adev->flags & AMD_IS_APU) ||
1354             (adev->gmc.xgmi.supported &&
1355              adev->gmc.xgmi.connected_to_cpu)) {
1356                 adev->gmc.aper_base =
1357                         adev->gfxhub.funcs->get_mc_fb_offset(adev) +
1358                         adev->gmc.xgmi.physical_node_id *
1359                         adev->gmc.xgmi.node_segment_size;
1360                 adev->gmc.aper_size = adev->gmc.real_vram_size;
1361         }
1362
1363 #endif
1364         /* In case the PCI BAR is larger than the actual amount of vram */
1365         adev->gmc.visible_vram_size = adev->gmc.aper_size;
1366         if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
1367                 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
1368
1369         /* set the gart size */
1370         if (amdgpu_gart_size == -1) {
1371                 switch (adev->asic_type) {
1372                 case CHIP_VEGA10:  /* all engines support GPUVM */
1373                 case CHIP_VEGA12:  /* all engines support GPUVM */
1374                 case CHIP_VEGA20:
1375                 case CHIP_ARCTURUS:
1376                 case CHIP_ALDEBARAN:
1377                 default:
1378                         adev->gmc.gart_size = 512ULL << 20;
1379                         break;
1380                 case CHIP_RAVEN:   /* DCE SG support */
1381                 case CHIP_RENOIR:
1382                         adev->gmc.gart_size = 1024ULL << 20;
1383                         break;
1384                 }
1385         } else {
1386                 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
1387         }
1388
1389         adev->gmc.gart_size += adev->pm.smu_prv_buffer_size;
1390
1391         gmc_v9_0_vram_gtt_location(adev, &adev->gmc);
1392
1393         return 0;
1394 }
1395
1396 static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
1397 {
1398         int r;
1399
1400         if (adev->gart.bo) {
1401                 WARN(1, "VEGA10 PCIE GART already initialized\n");
1402                 return 0;
1403         }
1404
1405         if (adev->gmc.xgmi.connected_to_cpu) {
1406                 adev->gmc.vmid0_page_table_depth = 1;
1407                 adev->gmc.vmid0_page_table_block_size = 12;
1408         } else {
1409                 adev->gmc.vmid0_page_table_depth = 0;
1410                 adev->gmc.vmid0_page_table_block_size = 0;
1411         }
1412
1413         /* Initialize common gart structure */
1414         r = amdgpu_gart_init(adev);
1415         if (r)
1416                 return r;
1417         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
1418         adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) |
1419                                  AMDGPU_PTE_EXECUTABLE;
1420
1421         r = amdgpu_gart_table_vram_alloc(adev);
1422         if (r)
1423                 return r;
1424
1425         if (adev->gmc.xgmi.connected_to_cpu) {
1426                 r = amdgpu_gmc_pdb0_alloc(adev);
1427         }
1428
1429         return r;
1430 }
1431
1432 /**
1433  * gmc_v9_0_save_registers - saves regs
1434  *
1435  * @adev: amdgpu_device pointer
1436  *
1437  * This saves potential register values that should be
1438  * restored upon resume
1439  */
1440 static void gmc_v9_0_save_registers(struct amdgpu_device *adev)
1441 {
1442         if (adev->asic_type == CHIP_RAVEN)
1443                 adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0);
1444 }
1445
1446 static int gmc_v9_0_sw_init(void *handle)
1447 {
1448         int r, vram_width = 0, vram_type = 0, vram_vendor = 0;
1449         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1450
1451         adev->gfxhub.funcs->init(adev);
1452
1453         adev->mmhub.funcs->init(adev);
1454
1455         spin_lock_init(&adev->gmc.invalidate_lock);
1456
1457         r = amdgpu_atomfirmware_get_vram_info(adev,
1458                 &vram_width, &vram_type, &vram_vendor);
1459         if (amdgpu_sriov_vf(adev))
1460                 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN,
1461                  * and DF related registers is not readable, seems hardcord is the
1462                  * only way to set the correct vram_width
1463                  */
1464                 adev->gmc.vram_width = 2048;
1465         else if (amdgpu_emu_mode != 1)
1466                 adev->gmc.vram_width = vram_width;
1467
1468         if (!adev->gmc.vram_width) {
1469                 int chansize, numchan;
1470
1471                 /* hbm memory channel size */
1472                 if (adev->flags & AMD_IS_APU)
1473                         chansize = 64;
1474                 else
1475                         chansize = 128;
1476
1477                 numchan = adev->df.funcs->get_hbm_channel_number(adev);
1478                 adev->gmc.vram_width = numchan * chansize;
1479         }
1480
1481         adev->gmc.vram_type = vram_type;
1482         adev->gmc.vram_vendor = vram_vendor;
1483         switch (adev->asic_type) {
1484         case CHIP_RAVEN:
1485                 adev->num_vmhubs = 2;
1486
1487                 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
1488                         amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1489                 } else {
1490                         /* vm_size is 128TB + 512GB for legacy 3-level page support */
1491                         amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48);
1492                         adev->gmc.translate_further =
1493                                 adev->vm_manager.num_level > 1;
1494                 }
1495                 break;
1496         case CHIP_VEGA10:
1497         case CHIP_VEGA12:
1498         case CHIP_VEGA20:
1499         case CHIP_RENOIR:
1500         case CHIP_ALDEBARAN:
1501                 adev->num_vmhubs = 2;
1502
1503
1504                 /*
1505                  * To fulfill 4-level page support,
1506                  * vm size is 256TB (48bit), maximum size of Vega10,
1507                  * block size 512 (9bit)
1508                  */
1509                 /* sriov restrict max_pfn below AMDGPU_GMC_HOLE */
1510                 if (amdgpu_sriov_vf(adev))
1511                         amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 47);
1512                 else
1513                         amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1514                 break;
1515         case CHIP_ARCTURUS:
1516                 adev->num_vmhubs = 3;
1517
1518                 /* Keep the vm size same with Vega20 */
1519                 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1520                 break;
1521         default:
1522                 break;
1523         }
1524
1525         /* This interrupt is VMC page fault.*/
1526         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT,
1527                                 &adev->gmc.vm_fault);
1528         if (r)
1529                 return r;
1530
1531         if (adev->asic_type == CHIP_ARCTURUS) {
1532                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT,
1533                                         &adev->gmc.vm_fault);
1534                 if (r)
1535                         return r;
1536         }
1537
1538         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT,
1539                                 &adev->gmc.vm_fault);
1540
1541         if (r)
1542                 return r;
1543
1544         if (!amdgpu_sriov_vf(adev) &&
1545             !adev->gmc.xgmi.connected_to_cpu) {
1546                 /* interrupt sent to DF. */
1547                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0,
1548                                       &adev->gmc.ecc_irq);
1549                 if (r)
1550                         return r;
1551         }
1552
1553         /* Set the internal MC address mask
1554          * This is the max address of the GPU's
1555          * internal address space.
1556          */
1557         adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
1558
1559         r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
1560         if (r) {
1561                 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
1562                 return r;
1563         }
1564         adev->need_swiotlb = drm_need_swiotlb(44);
1565
1566         if (adev->gmc.xgmi.supported) {
1567                 r = adev->gfxhub.funcs->get_xgmi_info(adev);
1568                 if (r)
1569                         return r;
1570         }
1571
1572         r = gmc_v9_0_mc_init(adev);
1573         if (r)
1574                 return r;
1575
1576         amdgpu_gmc_get_vbios_allocations(adev);
1577
1578         /* Memory manager */
1579         r = amdgpu_bo_init(adev);
1580         if (r)
1581                 return r;
1582
1583         r = gmc_v9_0_gart_init(adev);
1584         if (r)
1585                 return r;
1586
1587         /*
1588          * number of VMs
1589          * VMID 0 is reserved for System
1590          * amdgpu graphics/compute will use VMIDs 1..n-1
1591          * amdkfd will use VMIDs n..15
1592          *
1593          * The first KFD VMID is 8 for GPUs with graphics, 3 for
1594          * compute-only GPUs. On compute-only GPUs that leaves 2 VMIDs
1595          * for video processing.
1596          */
1597         adev->vm_manager.first_kfd_vmid =
1598                 (adev->asic_type == CHIP_ARCTURUS ||
1599                  adev->asic_type == CHIP_ALDEBARAN) ? 3 : 8;
1600
1601         amdgpu_vm_manager_init(adev);
1602
1603         gmc_v9_0_save_registers(adev);
1604
1605         return 0;
1606 }
1607
1608 static int gmc_v9_0_sw_fini(void *handle)
1609 {
1610         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1611
1612         amdgpu_gmc_ras_fini(adev);
1613         amdgpu_gem_force_release(adev);
1614         amdgpu_vm_manager_fini(adev);
1615         amdgpu_gart_table_vram_free(adev);
1616         amdgpu_bo_unref(&adev->gmc.pdb0_bo);
1617         amdgpu_bo_fini(adev);
1618
1619         return 0;
1620 }
1621
1622 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
1623 {
1624
1625         switch (adev->asic_type) {
1626         case CHIP_VEGA10:
1627                 if (amdgpu_sriov_vf(adev))
1628                         break;
1629                 fallthrough;
1630         case CHIP_VEGA20:
1631                 soc15_program_register_sequence(adev,
1632                                                 golden_settings_mmhub_1_0_0,
1633                                                 ARRAY_SIZE(golden_settings_mmhub_1_0_0));
1634                 soc15_program_register_sequence(adev,
1635                                                 golden_settings_athub_1_0_0,
1636                                                 ARRAY_SIZE(golden_settings_athub_1_0_0));
1637                 break;
1638         case CHIP_VEGA12:
1639                 break;
1640         case CHIP_RAVEN:
1641                 /* TODO for renoir */
1642                 soc15_program_register_sequence(adev,
1643                                                 golden_settings_athub_1_0_0,
1644                                                 ARRAY_SIZE(golden_settings_athub_1_0_0));
1645                 break;
1646         default:
1647                 break;
1648         }
1649 }
1650
1651 /**
1652  * gmc_v9_0_restore_registers - restores regs
1653  *
1654  * @adev: amdgpu_device pointer
1655  *
1656  * This restores register values, saved at suspend.
1657  */
1658 void gmc_v9_0_restore_registers(struct amdgpu_device *adev)
1659 {
1660         if (adev->asic_type == CHIP_RAVEN) {
1661                 WREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register);
1662                 WARN_ON(adev->gmc.sdpif_register !=
1663                         RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0));
1664         }
1665 }
1666
1667 /**
1668  * gmc_v9_0_gart_enable - gart enable
1669  *
1670  * @adev: amdgpu_device pointer
1671  */
1672 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
1673 {
1674         int r;
1675
1676         if (adev->gmc.xgmi.connected_to_cpu)
1677                 amdgpu_gmc_init_pdb0(adev);
1678
1679         if (adev->gart.bo == NULL) {
1680                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
1681                 return -EINVAL;
1682         }
1683
1684         r = amdgpu_gart_table_vram_pin(adev);
1685         if (r)
1686                 return r;
1687
1688         r = adev->gfxhub.funcs->gart_enable(adev);
1689         if (r)
1690                 return r;
1691
1692         r = adev->mmhub.funcs->gart_enable(adev);
1693         if (r)
1694                 return r;
1695
1696         DRM_INFO("PCIE GART of %uM enabled.\n",
1697                  (unsigned)(adev->gmc.gart_size >> 20));
1698         if (adev->gmc.pdb0_bo)
1699                 DRM_INFO("PDB0 located at 0x%016llX\n",
1700                                 (unsigned long long)amdgpu_bo_gpu_offset(adev->gmc.pdb0_bo));
1701         DRM_INFO("PTB located at 0x%016llX\n",
1702                         (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
1703
1704         adev->gart.ready = true;
1705         return 0;
1706 }
1707
1708 static int gmc_v9_0_hw_init(void *handle)
1709 {
1710         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1711         bool value;
1712         int r, i;
1713
1714         /* The sequence of these two function calls matters.*/
1715         gmc_v9_0_init_golden_registers(adev);
1716
1717         if (adev->mode_info.num_crtc) {
1718                 /* Lockout access through VGA aperture*/
1719                 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
1720                 /* disable VGA render */
1721                 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
1722         }
1723
1724         if (adev->mmhub.funcs->update_power_gating)
1725                 adev->mmhub.funcs->update_power_gating(adev, true);
1726
1727         adev->hdp.funcs->init_registers(adev);
1728
1729         /* After HDP is initialized, flush HDP.*/
1730         adev->hdp.funcs->flush_hdp(adev, NULL);
1731
1732         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
1733                 value = false;
1734         else
1735                 value = true;
1736
1737         if (!amdgpu_sriov_vf(adev)) {
1738                 adev->gfxhub.funcs->set_fault_enable_default(adev, value);
1739                 adev->mmhub.funcs->set_fault_enable_default(adev, value);
1740         }
1741         for (i = 0; i < adev->num_vmhubs; ++i)
1742                 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0);
1743
1744         if (adev->umc.funcs && adev->umc.funcs->init_registers)
1745                 adev->umc.funcs->init_registers(adev);
1746
1747         r = gmc_v9_0_gart_enable(adev);
1748
1749         return r;
1750 }
1751
1752 /**
1753  * gmc_v9_0_gart_disable - gart disable
1754  *
1755  * @adev: amdgpu_device pointer
1756  *
1757  * This disables all VM page table.
1758  */
1759 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
1760 {
1761         adev->gfxhub.funcs->gart_disable(adev);
1762         adev->mmhub.funcs->gart_disable(adev);
1763         amdgpu_gart_table_vram_unpin(adev);
1764 }
1765
1766 static int gmc_v9_0_hw_fini(void *handle)
1767 {
1768         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1769
1770         if (amdgpu_sriov_vf(adev)) {
1771                 /* full access mode, so don't touch any GMC register */
1772                 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
1773                 return 0;
1774         }
1775
1776         amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
1777         amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1778         gmc_v9_0_gart_disable(adev);
1779
1780         return 0;
1781 }
1782
1783 static int gmc_v9_0_suspend(void *handle)
1784 {
1785         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1786
1787         return gmc_v9_0_hw_fini(adev);
1788 }
1789
1790 static int gmc_v9_0_resume(void *handle)
1791 {
1792         int r;
1793         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1794
1795         r = gmc_v9_0_hw_init(adev);
1796         if (r)
1797                 return r;
1798
1799         amdgpu_vmid_reset_all(adev);
1800
1801         return 0;
1802 }
1803
1804 static bool gmc_v9_0_is_idle(void *handle)
1805 {
1806         /* MC is always ready in GMC v9.*/
1807         return true;
1808 }
1809
1810 static int gmc_v9_0_wait_for_idle(void *handle)
1811 {
1812         /* There is no need to wait for MC idle in GMC v9.*/
1813         return 0;
1814 }
1815
1816 static int gmc_v9_0_soft_reset(void *handle)
1817 {
1818         /* XXX for emulation.*/
1819         return 0;
1820 }
1821
1822 static int gmc_v9_0_set_clockgating_state(void *handle,
1823                                         enum amd_clockgating_state state)
1824 {
1825         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1826
1827         adev->mmhub.funcs->set_clockgating(adev, state);
1828
1829         athub_v1_0_set_clockgating(adev, state);
1830
1831         return 0;
1832 }
1833
1834 static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags)
1835 {
1836         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1837
1838         adev->mmhub.funcs->get_clockgating(adev, flags);
1839
1840         athub_v1_0_get_clockgating(adev, flags);
1841 }
1842
1843 static int gmc_v9_0_set_powergating_state(void *handle,
1844                                         enum amd_powergating_state state)
1845 {
1846         return 0;
1847 }
1848
1849 const struct amd_ip_funcs gmc_v9_0_ip_funcs = {
1850         .name = "gmc_v9_0",
1851         .early_init = gmc_v9_0_early_init,
1852         .late_init = gmc_v9_0_late_init,
1853         .sw_init = gmc_v9_0_sw_init,
1854         .sw_fini = gmc_v9_0_sw_fini,
1855         .hw_init = gmc_v9_0_hw_init,
1856         .hw_fini = gmc_v9_0_hw_fini,
1857         .suspend = gmc_v9_0_suspend,
1858         .resume = gmc_v9_0_resume,
1859         .is_idle = gmc_v9_0_is_idle,
1860         .wait_for_idle = gmc_v9_0_wait_for_idle,
1861         .soft_reset = gmc_v9_0_soft_reset,
1862         .set_clockgating_state = gmc_v9_0_set_clockgating_state,
1863         .set_powergating_state = gmc_v9_0_set_powergating_state,
1864         .get_clockgating_state = gmc_v9_0_get_clockgating_state,
1865 };
1866
1867 const struct amdgpu_ip_block_version gmc_v9_0_ip_block =
1868 {
1869         .type = AMD_IP_BLOCK_TYPE_GMC,
1870         .major = 9,
1871         .minor = 0,
1872         .rev = 0,
1873         .funcs = &gmc_v9_0_ip_funcs,
1874 };