drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <drm/drmP.h>
  25 #include "amdgpu.h"
  26 #include "gmc_v8_0.h"
  27 #include "amdgpu_ucode.h"
  28
  29 #include "gmc/gmc_8_1_d.h"
  30 #include "gmc/gmc_8_1_sh_mask.h"
  31
  32 #include "bif/bif_5_0_d.h"
  33 #include "bif/bif_5_0_sh_mask.h"
  34
  35 #include "oss/oss_3_0_d.h"
  36 #include "oss/oss_3_0_sh_mask.h"
  37
  38 #include "vid.h"
  39 #include "vi.h"
  40
  41 #include "amdgpu_atombios.h"
  42
  43
  44 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev);
  45 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
  46 static int gmc_v8_0_wait_for_idle(void *handle);
  47
  48 MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
  49 MODULE_FIRMWARE("amdgpu/polaris11_mc.bin");
  50 MODULE_FIRMWARE("amdgpu/polaris10_mc.bin");
  51 MODULE_FIRMWARE("amdgpu/polaris12_mc.bin");
  52
  53 static const u32 golden_settings_tonga_a11[] =
  54 {
  55         mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
  56         mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028,
  57         mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991,
  58         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  59         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  60         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  61         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  62 };
  63
  64 static const u32 tonga_mgcg_cgcg_init[] =
  65 {
  66         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  67 };
  68
  69 static const u32 golden_settings_fiji_a10[] =
  70 {
  71         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  72         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  73         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  74         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  75 };
  76
  77 static const u32 fiji_mgcg_cgcg_init[] =
  78 {
  79         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  80 };
  81
  82 static const u32 golden_settings_polaris11_a11[] =
  83 {
  84         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  85         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  86         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  87         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
  88 };
  89
  90 static const u32 golden_settings_polaris10_a11[] =
  91 {
  92         mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
  93         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  94         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  95         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  96         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
  97 };
  98
  99 static const u32 cz_mgcg_cgcg_init[] =
 100 {
 101         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
 102 };
 103
 104 static const u32 stoney_mgcg_cgcg_init[] =
 105 {
 106         mmATC_MISC_CG, 0xffffffff, 0x000c0200,
 107         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
 108 };
 109
 110 static const u32 golden_settings_stoney_common[] =
 111 {
 112         mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004,
 113         mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000
 114 };
 115
 116 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
 117 {
 118         switch (adev->asic_type) {
 119         case CHIP_FIJI:
 120                 amdgpu_program_register_sequence(adev,
 121                                                  fiji_mgcg_cgcg_init,
 122                                                  (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
 123                 amdgpu_program_register_sequence(adev,
 124                                                  golden_settings_fiji_a10,
 125                                                  (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
 126                 break;
 127         case CHIP_TONGA:
 128                 amdgpu_program_register_sequence(adev,
 129                                                  tonga_mgcg_cgcg_init,
 130                                                  (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
 131                 amdgpu_program_register_sequence(adev,
 132                                                  golden_settings_tonga_a11,
 133                                                  (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
 134                 break;
 135         case CHIP_POLARIS11:
 136         case CHIP_POLARIS12:
 137                 amdgpu_program_register_sequence(adev,
 138                                                  golden_settings_polaris11_a11,
 139                                                  (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
 140                 break;
 141         case CHIP_POLARIS10:
 142                 amdgpu_program_register_sequence(adev,
 143                                                  golden_settings_polaris10_a11,
 144                                                  (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
 145                 break;
 146         case CHIP_CARRIZO:
 147                 amdgpu_program_register_sequence(adev,
 148                                                  cz_mgcg_cgcg_init,
 149                                                  (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
 150                 break;
 151         case CHIP_STONEY:
 152                 amdgpu_program_register_sequence(adev,
 153                                                  stoney_mgcg_cgcg_init,
 154                                                  (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
 155                 amdgpu_program_register_sequence(adev,
 156                                                  golden_settings_stoney_common,
 157                                                  (const u32)ARRAY_SIZE(golden_settings_stoney_common));
 158                 break;
 159         default:
 160                 break;
 161         }
 162 }
 163
 164 static void gmc_v8_0_mc_stop(struct amdgpu_device *adev,
 165                              struct amdgpu_mode_mc_save *save)
 166 {
 167         u32 blackout;
 168
 169         if (adev->mode_info.num_crtc)
 170                 amdgpu_display_stop_mc_access(adev, save);
 171
 172         gmc_v8_0_wait_for_idle(adev);
 173
 174         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 175         if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
 176                 /* Block CPU access */
 177                 WREG32(mmBIF_FB_EN, 0);
 178                 /* blackout the MC */
 179                 blackout = REG_SET_FIELD(blackout,
 180                                          MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1);
 181                 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
 182         }
 183         /* wait for the MC to settle */
 184         udelay(100);
 185 }
 186
 187 static void gmc_v8_0_mc_resume(struct amdgpu_device *adev,
 188                                struct amdgpu_mode_mc_save *save)
 189 {
 190         u32 tmp;
 191
 192         /* unblackout the MC */
 193         tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 194         tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
 195         WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
 196         /* allow CPU access */
 197         tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
 198         tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
 199         WREG32(mmBIF_FB_EN, tmp);
 200
 201         if (adev->mode_info.num_crtc)
 202                 amdgpu_display_resume_mc_access(adev, save);
 203 }
 204
 205 /**
 206  * gmc_v8_0_init_microcode - load ucode images from disk
 207  *
 208  * @adev: amdgpu_device pointer
 209  *
 210  * Use the firmware interface to load the ucode images into
 211  * the driver (not loaded into hw).
 212  * Returns 0 on success, error on failure.
 213  */
 214 static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
 215 {
 216         const char *chip_name;
 217         char fw_name[30];
 218         int err;
 219
 220         DRM_DEBUG("\n");
 221
 222         switch (adev->asic_type) {
 223         case CHIP_TONGA:
 224                 chip_name = "tonga";
 225                 break;
 226         case CHIP_POLARIS11:
 227                 chip_name = "polaris11";
 228                 break;
 229         case CHIP_POLARIS10:
 230                 chip_name = "polaris10";
 231                 break;
 232         case CHIP_POLARIS12:
 233                 chip_name = "polaris12";
 234                 break;
 235         case CHIP_FIJI:
 236         case CHIP_CARRIZO:
 237         case CHIP_STONEY:
 238                 return 0;
 239         default: BUG();
 240         }
 241
 242         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
 243         err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
 244         if (err)
 245                 goto out;
 246         err = amdgpu_ucode_validate(adev->mc.fw);
 247
 248 out:
 249         if (err) {
 250                 pr_err("mc: Failed to load firmware \"%s\"\n", fw_name);
 251                 release_firmware(adev->mc.fw);
 252                 adev->mc.fw = NULL;
 253         }
 254         return err;
 255 }
 256
 257 /**
 258  * gmc_v8_0_tonga_mc_load_microcode - load tonga MC ucode into the hw
 259  *
 260  * @adev: amdgpu_device pointer
 261  *
 262  * Load the GDDR MC ucode into the hw (CIK).
 263  * Returns 0 on success, error on failure.
 264  */
 265 static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev)
 266 {
 267         const struct mc_firmware_header_v1_0 *hdr;
 268         const __le32 *fw_data = NULL;
 269         const __le32 *io_mc_regs = NULL;
 270         u32 running;
 271         int i, ucode_size, regs_size;
 272
 273         /* Skip MC ucode loading on SR-IOV capable boards.
 274          * vbios does this for us in asic_init in that case.
 275          * Skip MC ucode loading on VF, because hypervisor will do that
 276          * for this adaptor.
 277          */
 278         if (amdgpu_sriov_bios(adev))
 279                 return 0;
 280
 281         if (!adev->mc.fw)
 282                 return -EINVAL;
 283
 284         hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
 285         amdgpu_ucode_print_mc_hdr(&hdr->header);
 286
 287         adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 288         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 289         io_mc_regs = (const __le32 *)
 290                 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 291         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 292         fw_data = (const __le32 *)
 293                 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 294
 295         running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
 296
 297         if (running == 0) {
 298                 /* reset the engine and set to writable */
 299                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 300                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 301
 302                 /* load mc io regs */
 303                 for (i = 0; i < regs_size; i++) {
 304                         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 305                         WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 306                 }
 307                 /* load the MC ucode */
 308                 for (i = 0; i < ucode_size; i++)
 309                         WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 310
 311                 /* put the engine back into the active state */
 312                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 313                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 314                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 315
 316                 /* wait for training to complete */
 317                 for (i = 0; i < adev->usec_timeout; i++) {
 318                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 319                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
 320                                 break;
 321                         udelay(1);
 322                 }
 323                 for (i = 0; i < adev->usec_timeout; i++) {
 324                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 325                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
 326                                 break;
 327                         udelay(1);
 328                 }
 329         }
 330
 331         return 0;
 332 }
 333
 334 static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev)
 335 {
 336         const struct mc_firmware_header_v1_0 *hdr;
 337         const __le32 *fw_data = NULL;
 338         const __le32 *io_mc_regs = NULL;
 339         u32 data, vbios_version;
 340         int i, ucode_size, regs_size;
 341
 342         /* Skip MC ucode loading on SR-IOV capable boards.
 343          * vbios does this for us in asic_init in that case.
 344          * Skip MC ucode loading on VF, because hypervisor will do that
 345          * for this adaptor.
 346          */
 347         if (amdgpu_sriov_bios(adev))
 348                 return 0;
 349
 350         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
 351         data = RREG32(mmMC_SEQ_IO_DEBUG_DATA);
 352         vbios_version = data & 0xf;
 353
 354         if (vbios_version == 0)
 355                 return 0;
 356
 357         if (!adev->mc.fw)
 358                 return -EINVAL;
 359
 360         hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
 361         amdgpu_ucode_print_mc_hdr(&hdr->header);
 362
 363         adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 364         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 365         io_mc_regs = (const __le32 *)
 366                 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 367         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 368         fw_data = (const __le32 *)
 369                 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 370
 371         data = RREG32(mmMC_SEQ_MISC0);
 372         data &= ~(0x40);
 373         WREG32(mmMC_SEQ_MISC0, data);
 374
 375         /* load mc io regs */
 376         for (i = 0; i < regs_size; i++) {
 377                 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 378                 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 379         }
 380
 381         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 382         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 383
 384         /* load the MC ucode */
 385         for (i = 0; i < ucode_size; i++)
 386                 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 387
 388         /* put the engine back into the active state */
 389         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 390         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 391         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 392
 393         /* wait for training to complete */
 394         for (i = 0; i < adev->usec_timeout; i++) {
 395                 data = RREG32(mmMC_SEQ_MISC0);
 396                 if (data & 0x80)
 397                         break;
 398                 udelay(1);
 399         }
 400
 401         return 0;
 402 }
 403
 404 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev,
 405                                        struct amdgpu_mc *mc)
 406 {
 407         u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
 408         base <<= 24;
 409
 410         if (mc->mc_vram_size > 0xFFC0000000ULL) {
 411                 /* leave room for at least 1024M GTT */
 412                 dev_warn(adev->dev, "limiting VRAM\n");
 413                 mc->real_vram_size = 0xFFC0000000ULL;
 414                 mc->mc_vram_size = 0xFFC0000000ULL;
 415         }
 416         amdgpu_vram_location(adev, &adev->mc, base);
 417         adev->mc.gtt_base_align = 0;
 418         amdgpu_gtt_location(adev, mc);
 419 }
 420
 421 /**
 422  * gmc_v8_0_mc_program - program the GPU memory controller
 423  *
 424  * @adev: amdgpu_device pointer
 425  *
 426  * Set the location of vram, gart, and AGP in the GPU's
 427  * physical address space (CIK).
 428  */
 429 static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
 430 {
 431         u32 tmp;
 432         int i, j;
 433
 434         /* Initialize HDP */
 435         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
 436                 WREG32((0xb05 + j), 0x00000000);
 437                 WREG32((0xb06 + j), 0x00000000);
 438                 WREG32((0xb07 + j), 0x00000000);
 439                 WREG32((0xb08 + j), 0x00000000);
 440                 WREG32((0xb09 + j), 0x00000000);
 441         }
 442         WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 443
 444         if (gmc_v8_0_wait_for_idle((void *)adev)) {
 445                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 446         }
 447         /* Update configuration */
 448         WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 449                adev->mc.vram_start >> 12);
 450         WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 451                adev->mc.vram_end >> 12);
 452         WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
 453                adev->vram_scratch.gpu_addr >> 12);
 454         WREG32(mmMC_VM_AGP_BASE, 0);
 455         WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
 456         WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
 457         if (gmc_v8_0_wait_for_idle((void *)adev)) {
 458                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 459         }
 460
 461         WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
 462
 463         tmp = RREG32(mmHDP_MISC_CNTL);
 464         tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
 465         WREG32(mmHDP_MISC_CNTL, tmp);
 466
 467         tmp = RREG32(mmHDP_HOST_PATH_CNTL);
 468         WREG32(mmHDP_HOST_PATH_CNTL, tmp);
 469 }
 470
 471 /**
 472  * gmc_v8_0_mc_init - initialize the memory controller driver params
 473  *
 474  * @adev: amdgpu_device pointer
 475  *
 476  * Look up the amount of vram, vram width, and decide how to place
 477  * vram and gart within the GPU's physical address space (CIK).
 478  * Returns 0 for success.
 479  */
 480 static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
 481 {
 482         adev->mc.vram_width = amdgpu_atombios_get_vram_width(adev);
 483         if (!adev->mc.vram_width) {
 484                 u32 tmp;
 485                 int chansize, numchan;
 486
 487                 /* Get VRAM informations */
 488                 tmp = RREG32(mmMC_ARB_RAMCFG);
 489                 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
 490                         chansize = 64;
 491                 } else {
 492                         chansize = 32;
 493                 }
 494                 tmp = RREG32(mmMC_SHARED_CHMAP);
 495                 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 496                 case 0:
 497                 default:
 498                         numchan = 1;
 499                         break;
 500                 case 1:
 501                         numchan = 2;
 502                         break;
 503                 case 2:
 504                         numchan = 4;
 505                         break;
 506                 case 3:
 507                         numchan = 8;
 508                         break;
 509                 case 4:
 510                         numchan = 3;
 511                         break;
 512                 case 5:
 513                         numchan = 6;
 514                         break;
 515                 case 6:
 516                         numchan = 10;
 517                         break;
 518                 case 7:
 519                         numchan = 12;
 520                         break;
 521                 case 8:
 522                         numchan = 16;
 523                         break;
 524                 }
 525                 adev->mc.vram_width = numchan * chansize;
 526         }
 527         /* Could aper size report 0 ? */
 528         adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
 529         adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
 530         /* size in MB on si */
 531         adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 532         adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 533
 534 #ifdef CONFIG_X86_64
 535         if (adev->flags & AMD_IS_APU) {
 536                 adev->mc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
 537                 adev->mc.aper_size = adev->mc.real_vram_size;
 538         }
 539 #endif
 540
 541         /* In case the PCI BAR is larger than the actual amount of vram */
 542         adev->mc.visible_vram_size = adev->mc.aper_size;
 543         if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
 544                 adev->mc.visible_vram_size = adev->mc.real_vram_size;
 545
 546         /* unless the user had overridden it, set the gart
 547          * size equal to the 1024 or vram, whichever is larger.
 548          */
 549         if (amdgpu_gart_size == -1)
 550                 adev->mc.gtt_size = max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
 551                                         adev->mc.mc_vram_size);
 552         else
 553                 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
 554
 555         gmc_v8_0_vram_gtt_location(adev, &adev->mc);
 556
 557         return 0;
 558 }
 559
 560 /*
 561  * GART
 562  * VMID 0 is the physical GPU addresses as used by the kernel.
 563  * VMIDs 1-15 are used for userspace clients and are handled
 564  * by the amdgpu vm/hsa code.
 565  */
 566
 567 /**
 568  * gmc_v8_0_gart_flush_gpu_tlb - gart tlb flush callback
 569  *
 570  * @adev: amdgpu_device pointer
 571  * @vmid: vm instance to flush
 572  *
 573  * Flush the TLB for the requested page table (CIK).
 574  */
 575 static void gmc_v8_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
 576                                         uint32_t vmid)
 577 {
 578         /* flush hdp cache */
 579         WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
 580
 581         /* bits 0-15 are the VM contexts0-15 */
 582         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 583 }
 584
 585 /**
 586  * gmc_v8_0_gart_set_pte_pde - update the page tables using MMIO
 587  *
 588  * @adev: amdgpu_device pointer
 589  * @cpu_pt_addr: cpu address of the page table
 590  * @gpu_page_idx: entry in the page table to update
 591  * @addr: dst addr to write into pte/pde
 592  * @flags: access flags
 593  *
 594  * Update the page tables using the CPU.
 595  */
 596 static int gmc_v8_0_gart_set_pte_pde(struct amdgpu_device *adev,
 597                                      void *cpu_pt_addr,
 598                                      uint32_t gpu_page_idx,
 599                                      uint64_t addr,
 600                                      uint64_t flags)
 601 {
 602         void __iomem *ptr = (void *)cpu_pt_addr;
 603         uint64_t value;
 604
 605         /*
 606          * PTE format on VI:
 607          * 63:40 reserved
 608          * 39:12 4k physical page base address
 609          * 11:7 fragment
 610          * 6 write
 611          * 5 read
 612          * 4 exe
 613          * 3 reserved
 614          * 2 snooped
 615          * 1 system
 616          * 0 valid
 617          *
 618          * PDE format on VI:
 619          * 63:59 block fragment size
 620          * 58:40 reserved
 621          * 39:1 physical base address of PTE
 622          * bits 5:1 must be 0.
 623          * 0 valid
 624          */
 625         value = addr & 0x000000FFFFFFF000ULL;
 626         value |= flags;
 627         writeq(value, ptr + (gpu_page_idx * 8));
 628
 629         return 0;
 630 }
 631
 632 static uint64_t gmc_v8_0_get_vm_pte_flags(struct amdgpu_device *adev,
 633                                           uint32_t flags)
 634 {
 635         uint64_t pte_flag = 0;
 636
 637         if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
 638                 pte_flag |= AMDGPU_PTE_EXECUTABLE;
 639         if (flags & AMDGPU_VM_PAGE_READABLE)
 640                 pte_flag |= AMDGPU_PTE_READABLE;
 641         if (flags & AMDGPU_VM_PAGE_WRITEABLE)
 642                 pte_flag |= AMDGPU_PTE_WRITEABLE;
 643         if (flags & AMDGPU_VM_PAGE_PRT)
 644                 pte_flag |= AMDGPU_PTE_PRT;
 645
 646         return pte_flag;
 647 }
 648
 649 static uint64_t gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, uint64_t addr)
 650 {
 651         BUG_ON(addr & 0xFFFFFF0000000FFFULL);
 652         return addr;
 653 }
 654
 655 /**
 656  * gmc_v8_0_set_fault_enable_default - update VM fault handling
 657  *
 658  * @adev: amdgpu_device pointer
 659  * @value: true redirects VM faults to the default page
 660  */
 661 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev,
 662                                               bool value)
 663 {
 664         u32 tmp;
 665
 666         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 667         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 668                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 669         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 670                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 671         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 672                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 673         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 674                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 675         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 676                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 677         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 678                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 679         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 680                             EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 681         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 682 }
 683
 684 /**
 685  * gmc_v8_0_set_prt - set PRT VM fault
 686  *
 687  * @adev: amdgpu_device pointer
 688  * @enable: enable/disable VM fault handling for PRT
 689 */
 690 static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable)
 691 {
 692         u32 tmp;
 693
 694         if (enable && !adev->mc.prt_warning) {
 695                 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
 696                 adev->mc.prt_warning = true;
 697         }
 698
 699         tmp = RREG32(mmVM_PRT_CNTL);
 700         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 701                             CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 702         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 703                             CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 704         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 705                             TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 706         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 707                             TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 708         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 709                             L2_CACHE_STORE_INVALID_ENTRIES, enable);
 710         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 711                             L1_TLB_STORE_INVALID_ENTRIES, enable);
 712         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 713                             MASK_PDE0_FAULT, enable);
 714         WREG32(mmVM_PRT_CNTL, tmp);
 715
 716         if (enable) {
 717                 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
 718                 uint32_t high = adev->vm_manager.max_pfn;
 719
 720                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
 721                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
 722                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
 723                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
 724                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
 725                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
 726                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
 727                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
 728         } else {
 729                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
 730                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
 731                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
 732                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
 733                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
 734                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
 735                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
 736                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
 737         }
 738 }
 739
 740 /**
 741  * gmc_v8_0_gart_enable - gart enable
 742  *
 743  * @adev: amdgpu_device pointer
 744  *
 745  * This sets up the TLBs, programs the page tables for VMID0,
 746  * sets up the hw for VMIDs 1-15 which are allocated on
 747  * demand, and sets up the global locations for the LDS, GDS,
 748  * and GPUVM for FSA64 clients (CIK).
 749  * Returns 0 for success, errors for failure.
 750  */
 751 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
 752 {
 753         int r, i;
 754         u32 tmp;
 755
 756         if (adev->gart.robj == NULL) {
 757                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 758                 return -EINVAL;
 759         }
 760         r = amdgpu_gart_table_vram_pin(adev);
 761         if (r)
 762                 return r;
 763         /* Setup TLB control */
 764         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 765         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 766         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
 767         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 768         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
 769         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 770         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 771         /* Setup L2 cache */
 772         tmp = RREG32(mmVM_L2_CNTL);
 773         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 774         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 775         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
 776         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
 777         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
 778         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 779         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 780         WREG32(mmVM_L2_CNTL, tmp);
 781         tmp = RREG32(mmVM_L2_CNTL2);
 782         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 783         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 784         WREG32(mmVM_L2_CNTL2, tmp);
 785         tmp = RREG32(mmVM_L2_CNTL3);
 786         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
 787         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4);
 788         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4);
 789         WREG32(mmVM_L2_CNTL3, tmp);
 790         /* XXX: set to enable PTE/PDE in system memory */
 791         tmp = RREG32(mmVM_L2_CNTL4);
 792         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0);
 793         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0);
 794         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0);
 795         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0);
 796         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0);
 797         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0);
 798         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0);
 799         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0);
 800         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0);
 801         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0);
 802         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0);
 803         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0);
 804         WREG32(mmVM_L2_CNTL4, tmp);
 805         /* setup context0 */
 806         WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12);
 807         WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12);
 808         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
 809         WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 810                         (u32)(adev->dummy_page.addr >> 12));
 811         WREG32(mmVM_CONTEXT0_CNTL2, 0);
 812         tmp = RREG32(mmVM_CONTEXT0_CNTL);
 813         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 814         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 815         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 816         WREG32(mmVM_CONTEXT0_CNTL, tmp);
 817
 818         WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0);
 819         WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0);
 820         WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0);
 821
 822         /* empty context1-15 */
 823         /* FIXME start with 4G, once using 2 level pt switch to full
 824          * vm size space
 825          */
 826         /* set vm size, must be a multiple of 4 */
 827         WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
 828         WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
 829         for (i = 1; i < 16; i++) {
 830                 if (i < 8)
 831                         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
 832                                adev->gart.table_addr >> 12);
 833                 else
 834                         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
 835                                adev->gart.table_addr >> 12);
 836         }
 837
 838         /* enable context1-15 */
 839         WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 840                (u32)(adev->dummy_page.addr >> 12));
 841         WREG32(mmVM_CONTEXT1_CNTL2, 4);
 842         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 843         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 844         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
 845         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 846         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 847         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 848         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 849         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 850         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 851         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 852         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
 853                             adev->vm_manager.block_size - 9);
 854         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 855         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
 856                 gmc_v8_0_set_fault_enable_default(adev, false);
 857         else
 858                 gmc_v8_0_set_fault_enable_default(adev, true);
 859
 860         gmc_v8_0_gart_flush_gpu_tlb(adev, 0);
 861         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 862                  (unsigned)(adev->mc.gtt_size >> 20),
 863                  (unsigned long long)adev->gart.table_addr);
 864         adev->gart.ready = true;
 865         return 0;
 866 }
 867
 868 static int gmc_v8_0_gart_init(struct amdgpu_device *adev)
 869 {
 870         int r;
 871
 872         if (adev->gart.robj) {
 873                 WARN(1, "R600 PCIE GART already initialized\n");
 874                 return 0;
 875         }
 876         /* Initialize common gart structure */
 877         r = amdgpu_gart_init(adev);
 878         if (r)
 879                 return r;
 880         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 881         adev->gart.gart_pte_flags = AMDGPU_PTE_EXECUTABLE;
 882         return amdgpu_gart_table_vram_alloc(adev);
 883 }
 884
 885 /**
 886  * gmc_v8_0_gart_disable - gart disable
 887  *
 888  * @adev: amdgpu_device pointer
 889  *
 890  * This disables all VM page table (CIK).
 891  */
 892 static void gmc_v8_0_gart_disable(struct amdgpu_device *adev)
 893 {
 894         u32 tmp;
 895
 896         /* Disable all tables */
 897         WREG32(mmVM_CONTEXT0_CNTL, 0);
 898         WREG32(mmVM_CONTEXT1_CNTL, 0);
 899         /* Setup TLB control */
 900         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 901         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 902         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
 903         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
 904         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 905         /* Setup L2 cache */
 906         tmp = RREG32(mmVM_L2_CNTL);
 907         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 908         WREG32(mmVM_L2_CNTL, tmp);
 909         WREG32(mmVM_L2_CNTL2, 0);
 910         amdgpu_gart_table_vram_unpin(adev);
 911 }
 912
 913 /**
 914  * gmc_v8_0_gart_fini - vm fini callback
 915  *
 916  * @adev: amdgpu_device pointer
 917  *
 918  * Tears down the driver GART/VM setup (CIK).
 919  */
 920 static void gmc_v8_0_gart_fini(struct amdgpu_device *adev)
 921 {
 922         amdgpu_gart_table_vram_free(adev);
 923         amdgpu_gart_fini(adev);
 924 }
 925
 926 /**
 927  * gmc_v8_0_vm_decode_fault - print human readable fault info
 928  *
 929  * @adev: amdgpu_device pointer
 930  * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
 931  * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
 932  *
 933  * Print human readable fault information (CIK).
 934  */
 935 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev,
 936                                      u32 status, u32 addr, u32 mc_client)
 937 {
 938         u32 mc_id;
 939         u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
 940         u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 941                                         PROTECTIONS);
 942         char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
 943                 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
 944
 945         mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 946                               MEMORY_CLIENT_ID);
 947
 948         dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
 949                protections, vmid, addr,
 950                REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 951                              MEMORY_CLIENT_RW) ?
 952                "write" : "read", block, mc_client, mc_id);
 953 }
 954
 955 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type)
 956 {
 957         switch (mc_seq_vram_type) {
 958         case MC_SEQ_MISC0__MT__GDDR1:
 959                 return AMDGPU_VRAM_TYPE_GDDR1;
 960         case MC_SEQ_MISC0__MT__DDR2:
 961                 return AMDGPU_VRAM_TYPE_DDR2;
 962         case MC_SEQ_MISC0__MT__GDDR3:
 963                 return AMDGPU_VRAM_TYPE_GDDR3;
 964         case MC_SEQ_MISC0__MT__GDDR4:
 965                 return AMDGPU_VRAM_TYPE_GDDR4;
 966         case MC_SEQ_MISC0__MT__GDDR5:
 967                 return AMDGPU_VRAM_TYPE_GDDR5;
 968         case MC_SEQ_MISC0__MT__HBM:
 969                 return AMDGPU_VRAM_TYPE_HBM;
 970         case MC_SEQ_MISC0__MT__DDR3:
 971                 return AMDGPU_VRAM_TYPE_DDR3;
 972         default:
 973                 return AMDGPU_VRAM_TYPE_UNKNOWN;
 974         }
 975 }
 976
 977 static int gmc_v8_0_early_init(void *handle)
 978 {
 979         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 980
 981         gmc_v8_0_set_gart_funcs(adev);
 982         gmc_v8_0_set_irq_funcs(adev);
 983
 984         adev->mc.shared_aperture_start = 0x2000000000000000ULL;
 985         adev->mc.shared_aperture_end =
 986                 adev->mc.shared_aperture_start + (4ULL << 30) - 1;
 987         adev->mc.private_aperture_start =
 988                 adev->mc.shared_aperture_end + 1;
 989         adev->mc.private_aperture_end =
 990                 adev->mc.private_aperture_start + (4ULL << 30) - 1;
 991
 992         return 0;
 993 }
 994
 995 static int gmc_v8_0_late_init(void *handle)
 996 {
 997         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 998
 999         if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
1000                 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
1001         else
1002                 return 0;
1003 }
1004
1005 #define mmMC_SEQ_MISC0_FIJI 0xA71
1006
1007 static int gmc_v8_0_sw_init(void *handle)
1008 {
1009         int r;
1010         int dma_bits;
1011         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1012
1013         if (adev->flags & AMD_IS_APU) {
1014                 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
1015         } else {
1016                 u32 tmp;
1017
1018                 if (adev->asic_type == CHIP_FIJI)
1019                         tmp = RREG32(mmMC_SEQ_MISC0_FIJI);
1020                 else
1021                         tmp = RREG32(mmMC_SEQ_MISC0);
1022                 tmp &= MC_SEQ_MISC0__MT__MASK;
1023                 adev->mc.vram_type = gmc_v8_0_convert_vram_type(tmp);
1024         }
1025
1026         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->mc.vm_fault);
1027         if (r)
1028                 return r;
1029
1030         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->mc.vm_fault);
1031         if (r)
1032                 return r;
1033
1034         /* Adjust VM size here.
1035          * Currently set to 4GB ((1 << 20) 4k pages).
1036          * Max GPUVM size for cayman and SI is 40 bits.
1037          */
1038         amdgpu_vm_adjust_size(adev, 64);
1039         adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
1040
1041         /* Set the internal MC address mask
1042          * This is the max address of the GPU's
1043          * internal address space.
1044          */
1045         adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1046
1047         adev->mc.stolen_size = 256 * 1024;
1048
1049         /* set DMA mask + need_dma32 flags.
1050          * PCIE - can handle 40-bits.
1051          * IGP - can handle 40-bits
1052          * PCI - dma32 for legacy pci gart, 40 bits on newer asics
1053          */
1054         adev->need_dma32 = false;
1055         dma_bits = adev->need_dma32 ? 32 : 40;
1056         r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
1057         if (r) {
1058                 adev->need_dma32 = true;
1059                 dma_bits = 32;
1060                 pr_warn("amdgpu: No suitable DMA available\n");
1061         }
1062         r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
1063         if (r) {
1064                 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
1065                 pr_warn("amdgpu: No coherent DMA available\n");
1066         }
1067
1068         r = gmc_v8_0_init_microcode(adev);
1069         if (r) {
1070                 DRM_ERROR("Failed to load mc firmware!\n");
1071                 return r;
1072         }
1073
1074         r = gmc_v8_0_mc_init(adev);
1075         if (r)
1076                 return r;
1077
1078         /* Memory manager */
1079         r = amdgpu_bo_init(adev);
1080         if (r)
1081                 return r;
1082
1083         r = gmc_v8_0_gart_init(adev);
1084         if (r)
1085                 return r;
1086
1087         /*
1088          * number of VMs
1089          * VMID 0 is reserved for System
1090          * amdgpu graphics/compute will use VMIDs 1-7
1091          * amdkfd will use VMIDs 8-15
1092          */
1093         adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
1094         adev->vm_manager.num_level = 1;
1095         amdgpu_vm_manager_init(adev);
1096
1097         /* base offset of vram pages */
1098         if (adev->flags & AMD_IS_APU) {
1099                 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
1100
1101                 tmp <<= 22;
1102                 adev->vm_manager.vram_base_offset = tmp;
1103         } else {
1104                 adev->vm_manager.vram_base_offset = 0;
1105         }
1106
1107         return 0;
1108 }
1109
1110 static int gmc_v8_0_sw_fini(void *handle)
1111 {
1112         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1113
1114         amdgpu_vm_manager_fini(adev);
1115         gmc_v8_0_gart_fini(adev);
1116         amdgpu_gem_force_release(adev);
1117         amdgpu_bo_fini(adev);
1118
1119         return 0;
1120 }
1121
1122 static int gmc_v8_0_hw_init(void *handle)
1123 {
1124         int r;
1125         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1126
1127         gmc_v8_0_init_golden_registers(adev);
1128
1129         gmc_v8_0_mc_program(adev);
1130
1131         if (adev->asic_type == CHIP_TONGA) {
1132                 r = gmc_v8_0_tonga_mc_load_microcode(adev);
1133                 if (r) {
1134                         DRM_ERROR("Failed to load MC firmware!\n");
1135                         return r;
1136                 }
1137         } else if (adev->asic_type == CHIP_POLARIS11 ||
1138                         adev->asic_type == CHIP_POLARIS10 ||
1139                         adev->asic_type == CHIP_POLARIS12) {
1140                 r = gmc_v8_0_polaris_mc_load_microcode(adev);
1141                 if (r) {
1142                         DRM_ERROR("Failed to load MC firmware!\n");
1143                         return r;
1144                 }
1145         }
1146
1147         r = gmc_v8_0_gart_enable(adev);
1148         if (r)
1149                 return r;
1150
1151         return r;
1152 }
1153
1154 static int gmc_v8_0_hw_fini(void *handle)
1155 {
1156         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1157
1158         amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
1159         gmc_v8_0_gart_disable(adev);
1160
1161         return 0;
1162 }
1163
1164 static int gmc_v8_0_suspend(void *handle)
1165 {
1166         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1167
1168         gmc_v8_0_hw_fini(adev);
1169
1170         return 0;
1171 }
1172
1173 static int gmc_v8_0_resume(void *handle)
1174 {
1175         int r;
1176         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1177
1178         r = gmc_v8_0_hw_init(adev);
1179         if (r)
1180                 return r;
1181
1182         amdgpu_vm_reset_all_ids(adev);
1183
1184         return 0;
1185 }
1186
1187 static bool gmc_v8_0_is_idle(void *handle)
1188 {
1189         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1190         u32 tmp = RREG32(mmSRBM_STATUS);
1191
1192         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1193                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1194                 return false;
1195
1196         return true;
1197 }
1198
1199 static int gmc_v8_0_wait_for_idle(void *handle)
1200 {
1201         unsigned i;
1202         u32 tmp;
1203         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1204
1205         for (i = 0; i < adev->usec_timeout; i++) {
1206                 /* read MC_STATUS */
1207                 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1208                                                SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1209                                                SRBM_STATUS__MCC_BUSY_MASK |
1210                                                SRBM_STATUS__MCD_BUSY_MASK |
1211                                                SRBM_STATUS__VMC_BUSY_MASK |
1212                                                SRBM_STATUS__VMC1_BUSY_MASK);
1213                 if (!tmp)
1214                         return 0;
1215                 udelay(1);
1216         }
1217         return -ETIMEDOUT;
1218
1219 }
1220
1221 static bool gmc_v8_0_check_soft_reset(void *handle)
1222 {
1223         u32 srbm_soft_reset = 0;
1224         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1225         u32 tmp = RREG32(mmSRBM_STATUS);
1226
1227         if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1228                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1229                                                 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1230
1231         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1232                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1233                 if (!(adev->flags & AMD_IS_APU))
1234                         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1235                                                         SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1236         }
1237         if (srbm_soft_reset) {
1238                 adev->mc.srbm_soft_reset = srbm_soft_reset;
1239                 return true;
1240         } else {
1241                 adev->mc.srbm_soft_reset = 0;
1242                 return false;
1243         }
1244 }
1245
1246 static int gmc_v8_0_pre_soft_reset(void *handle)
1247 {
1248         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1249
1250         if (!adev->mc.srbm_soft_reset)
1251                 return 0;
1252
1253         gmc_v8_0_mc_stop(adev, &adev->mc.save);
1254         if (gmc_v8_0_wait_for_idle(adev)) {
1255                 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1256         }
1257
1258         return 0;
1259 }
1260
1261 static int gmc_v8_0_soft_reset(void *handle)
1262 {
1263         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1264         u32 srbm_soft_reset;
1265
1266         if (!adev->mc.srbm_soft_reset)
1267                 return 0;
1268         srbm_soft_reset = adev->mc.srbm_soft_reset;
1269
1270         if (srbm_soft_reset) {
1271                 u32 tmp;
1272
1273                 tmp = RREG32(mmSRBM_SOFT_RESET);
1274                 tmp |= srbm_soft_reset;
1275                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1276                 WREG32(mmSRBM_SOFT_RESET, tmp);
1277                 tmp = RREG32(mmSRBM_SOFT_RESET);
1278
1279                 udelay(50);
1280
1281                 tmp &= ~srbm_soft_reset;
1282                 WREG32(mmSRBM_SOFT_RESET, tmp);
1283                 tmp = RREG32(mmSRBM_SOFT_RESET);
1284
1285                 /* Wait a little for things to settle down */
1286                 udelay(50);
1287         }
1288
1289         return 0;
1290 }
1291
1292 static int gmc_v8_0_post_soft_reset(void *handle)
1293 {
1294         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1295
1296         if (!adev->mc.srbm_soft_reset)
1297                 return 0;
1298
1299         gmc_v8_0_mc_resume(adev, &adev->mc.save);
1300         return 0;
1301 }
1302
1303 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1304                                              struct amdgpu_irq_src *src,
1305                                              unsigned type,
1306                                              enum amdgpu_interrupt_state state)
1307 {
1308         u32 tmp;
1309         u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1310                     VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1311                     VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1312                     VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1313                     VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1314                     VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1315                     VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1316
1317         switch (state) {
1318         case AMDGPU_IRQ_STATE_DISABLE:
1319                 /* system context */
1320                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1321                 tmp &= ~bits;
1322                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1323                 /* VMs */
1324                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1325                 tmp &= ~bits;
1326                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1327                 break;
1328         case AMDGPU_IRQ_STATE_ENABLE:
1329                 /* system context */
1330                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1331                 tmp |= bits;
1332                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1333                 /* VMs */
1334                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1335                 tmp |= bits;
1336                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1337                 break;
1338         default:
1339                 break;
1340         }
1341
1342         return 0;
1343 }
1344
1345 static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
1346                                       struct amdgpu_irq_src *source,
1347                                       struct amdgpu_iv_entry *entry)
1348 {
1349         u32 addr, status, mc_client;
1350
1351         if (amdgpu_sriov_vf(adev)) {
1352                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1353                         entry->src_id, entry->src_data[0]);
1354                 dev_err(adev->dev, " Can't decode VM fault info here on SRIOV VF\n");
1355                 return 0;
1356         }
1357
1358         addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1359         status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1360         mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1361         /* reset addr and status */
1362         WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1363
1364         if (!addr && !status)
1365                 return 0;
1366
1367         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1368                 gmc_v8_0_set_fault_enable_default(adev, false);
1369
1370         if (printk_ratelimit()) {
1371                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1372                         entry->src_id, entry->src_data[0]);
1373                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1374                         addr);
1375                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1376                         status);
1377                 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client);
1378         }
1379
1380         return 0;
1381 }
1382
1383 static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev,
1384                                                      bool enable)
1385 {
1386         uint32_t data;
1387
1388         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
1389                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1390                 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1391                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1392
1393                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1394                 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1395                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1396
1397                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1398                 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK;
1399                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1400
1401                 data = RREG32(mmMC_XPB_CLK_GAT);
1402                 data |= MC_XPB_CLK_GAT__ENABLE_MASK;
1403                 WREG32(mmMC_XPB_CLK_GAT, data);
1404
1405                 data = RREG32(mmATC_MISC_CG);
1406                 data |= ATC_MISC_CG__ENABLE_MASK;
1407                 WREG32(mmATC_MISC_CG, data);
1408
1409                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1410                 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK;
1411                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1412
1413                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1414                 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK;
1415                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1416
1417                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1418                 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK;
1419                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1420
1421                 data = RREG32(mmVM_L2_CG);
1422                 data |= VM_L2_CG__ENABLE_MASK;
1423                 WREG32(mmVM_L2_CG, data);
1424         } else {
1425                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1426                 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1427                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1428
1429                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1430                 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1431                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1432
1433                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1434                 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK;
1435                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1436
1437                 data = RREG32(mmMC_XPB_CLK_GAT);
1438                 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK;
1439                 WREG32(mmMC_XPB_CLK_GAT, data);
1440
1441                 data = RREG32(mmATC_MISC_CG);
1442                 data &= ~ATC_MISC_CG__ENABLE_MASK;
1443                 WREG32(mmATC_MISC_CG, data);
1444
1445                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1446                 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK;
1447                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1448
1449                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1450                 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK;
1451                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1452
1453                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1454                 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK;
1455                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1456
1457                 data = RREG32(mmVM_L2_CG);
1458                 data &= ~VM_L2_CG__ENABLE_MASK;
1459                 WREG32(mmVM_L2_CG, data);
1460         }
1461 }
1462
1463 static void fiji_update_mc_light_sleep(struct amdgpu_device *adev,
1464                                        bool enable)
1465 {
1466         uint32_t data;
1467
1468         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) {
1469                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1470                 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1471                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1472
1473                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1474                 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1475                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1476
1477                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1478                 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1479                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1480
1481                 data = RREG32(mmMC_XPB_CLK_GAT);
1482                 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1483                 WREG32(mmMC_XPB_CLK_GAT, data);
1484
1485                 data = RREG32(mmATC_MISC_CG);
1486                 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1487                 WREG32(mmATC_MISC_CG, data);
1488
1489                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1490                 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1491                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1492
1493                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1494                 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1495                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1496
1497                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1498                 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1499                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1500
1501                 data = RREG32(mmVM_L2_CG);
1502                 data |= VM_L2_CG__MEM_LS_ENABLE_MASK;
1503                 WREG32(mmVM_L2_CG, data);
1504         } else {
1505                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1506                 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1507                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1508
1509                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1510                 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1511                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1512
1513                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1514                 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1515                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1516
1517                 data = RREG32(mmMC_XPB_CLK_GAT);
1518                 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1519                 WREG32(mmMC_XPB_CLK_GAT, data);
1520
1521                 data = RREG32(mmATC_MISC_CG);
1522                 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1523                 WREG32(mmATC_MISC_CG, data);
1524
1525                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1526                 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1527                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1528
1529                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1530                 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1531                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1532
1533                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1534                 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1535                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1536
1537                 data = RREG32(mmVM_L2_CG);
1538                 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK;
1539                 WREG32(mmVM_L2_CG, data);
1540         }
1541 }
1542
1543 static int gmc_v8_0_set_clockgating_state(void *handle,
1544                                           enum amd_clockgating_state state)
1545 {
1546         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1547
1548         if (amdgpu_sriov_vf(adev))
1549                 return 0;
1550
1551         switch (adev->asic_type) {
1552         case CHIP_FIJI:
1553                 fiji_update_mc_medium_grain_clock_gating(adev,
1554                                 state == AMD_CG_STATE_GATE);
1555                 fiji_update_mc_light_sleep(adev,
1556                                 state == AMD_CG_STATE_GATE);
1557                 break;
1558         default:
1559                 break;
1560         }
1561         return 0;
1562 }
1563
1564 static int gmc_v8_0_set_powergating_state(void *handle,
1565                                           enum amd_powergating_state state)
1566 {
1567         return 0;
1568 }
1569
1570 static void gmc_v8_0_get_clockgating_state(void *handle, u32 *flags)
1571 {
1572         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1573         int data;
1574
1575         if (amdgpu_sriov_vf(adev))
1576                 *flags = 0;
1577
1578         /* AMD_CG_SUPPORT_MC_MGCG */
1579         data = RREG32(mmMC_HUB_MISC_HUB_CG);
1580         if (data & MC_HUB_MISC_HUB_CG__ENABLE_MASK)
1581                 *flags |= AMD_CG_SUPPORT_MC_MGCG;
1582
1583         /* AMD_CG_SUPPORT_MC_LS */
1584         if (data & MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK)
1585                 *flags |= AMD_CG_SUPPORT_MC_LS;
1586 }
1587
1588 static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
1589         .name = "gmc_v8_0",
1590         .early_init = gmc_v8_0_early_init,
1591         .late_init = gmc_v8_0_late_init,
1592         .sw_init = gmc_v8_0_sw_init,
1593         .sw_fini = gmc_v8_0_sw_fini,
1594         .hw_init = gmc_v8_0_hw_init,
1595         .hw_fini = gmc_v8_0_hw_fini,
1596         .suspend = gmc_v8_0_suspend,
1597         .resume = gmc_v8_0_resume,
1598         .is_idle = gmc_v8_0_is_idle,
1599         .wait_for_idle = gmc_v8_0_wait_for_idle,
1600         .check_soft_reset = gmc_v8_0_check_soft_reset,
1601         .pre_soft_reset = gmc_v8_0_pre_soft_reset,
1602         .soft_reset = gmc_v8_0_soft_reset,
1603         .post_soft_reset = gmc_v8_0_post_soft_reset,
1604         .set_clockgating_state = gmc_v8_0_set_clockgating_state,
1605         .set_powergating_state = gmc_v8_0_set_powergating_state,
1606         .get_clockgating_state = gmc_v8_0_get_clockgating_state,
1607 };
1608
1609 static const struct amdgpu_gart_funcs gmc_v8_0_gart_funcs = {
1610         .flush_gpu_tlb = gmc_v8_0_gart_flush_gpu_tlb,
1611         .set_pte_pde = gmc_v8_0_gart_set_pte_pde,
1612         .set_prt = gmc_v8_0_set_prt,
1613         .get_vm_pte_flags = gmc_v8_0_get_vm_pte_flags,
1614         .get_vm_pde = gmc_v8_0_get_vm_pde
1615 };
1616
1617 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {
1618         .set = gmc_v8_0_vm_fault_interrupt_state,
1619         .process = gmc_v8_0_process_interrupt,
1620 };
1621
1622 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev)
1623 {
1624         if (adev->gart.gart_funcs == NULL)
1625                 adev->gart.gart_funcs = &gmc_v8_0_gart_funcs;
1626 }
1627
1628 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev)
1629 {
1630         adev->mc.vm_fault.num_types = 1;
1631         adev->mc.vm_fault.funcs = &gmc_v8_0_irq_funcs;
1632 }
1633
1634 const struct amdgpu_ip_block_version gmc_v8_0_ip_block =
1635 {
1636         .type = AMD_IP_BLOCK_TYPE_GMC,
1637         .major = 8,
1638         .minor = 0,
1639         .rev = 0,
1640         .funcs = &gmc_v8_0_ip_funcs,
1641 };
1642
1643 const struct amdgpu_ip_block_version gmc_v8_1_ip_block =
1644 {
1645         .type = AMD_IP_BLOCK_TYPE_GMC,
1646         .major = 8,
1647         .minor = 1,
1648         .rev = 0,
1649         .funcs = &gmc_v8_0_ip_funcs,
1650 };
1651
1652 const struct amdgpu_ip_block_version gmc_v8_5_ip_block =
1653 {
1654         .type = AMD_IP_BLOCK_TYPE_GMC,
1655         .major = 8,
1656         .minor = 5,
1657         .rev = 0,
1658         .funcs = &gmc_v8_0_ip_funcs,
1659 };