drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c

   1 /*
   2  * Copyright 2021 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/pci.h>
  25
  26 #include <drm/drm_cache.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_atomfirmware.h"
  30 #include "gmc_v11_0.h"
  31 #include "umc_v8_10.h"
  32 #include "athub/athub_3_0_0_sh_mask.h"
  33 #include "athub/athub_3_0_0_offset.h"
  34 #include "oss/osssys_6_0_0_offset.h"
  35 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
  36 #include "navi10_enum.h"
  37 #include "soc15.h"
  38 #include "soc15d.h"
  39 #include "soc15_common.h"
  40 #include "nbio_v4_3.h"
  41 #include "gfxhub_v3_0.h"
  42 #include "gfxhub_v3_0_3.h"
  43 #include "mmhub_v3_0.h"
  44 #include "mmhub_v3_0_1.h"
  45 #include "mmhub_v3_0_2.h"
  46 #include "athub_v3_0.h"
  47
  48
  49 static int gmc_v11_0_ecc_interrupt_state(struct amdgpu_device *adev,
  50                                          struct amdgpu_irq_src *src,
  51                                          unsigned type,
  52                                          enum amdgpu_interrupt_state state)
  53 {
  54         return 0;
  55 }
  56
  57 static int
  58 gmc_v11_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
  59                                    struct amdgpu_irq_src *src, unsigned type,
  60                                    enum amdgpu_interrupt_state state)
  61 {
  62         switch (state) {
  63         case AMDGPU_IRQ_STATE_DISABLE:
  64                 /* MM HUB */
  65                 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, false);
  66                 /* GFX HUB */
  67                 /* This works because this interrupt is only
  68                  * enabled at init/resume and disabled in
  69                  * fini/suspend, so the overall state doesn't
  70                  * change over the course of suspend/resume.
  71                  */
  72                 if (!adev->in_s0ix)
  73                         amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, false);
  74                 break;
  75         case AMDGPU_IRQ_STATE_ENABLE:
  76                 /* MM HUB */
  77                 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, true);
  78                 /* GFX HUB */
  79                 /* This works because this interrupt is only
  80                  * enabled at init/resume and disabled in
  81                  * fini/suspend, so the overall state doesn't
  82                  * change over the course of suspend/resume.
  83                  */
  84                 if (!adev->in_s0ix)
  85                         amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, true);
  86                 break;
  87         default:
  88                 break;
  89         }
  90
  91         return 0;
  92 }
  93
  94 static int gmc_v11_0_process_interrupt(struct amdgpu_device *adev,
  95                                        struct amdgpu_irq_src *source,
  96                                        struct amdgpu_iv_entry *entry)
  97 {
  98         struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src];
  99         uint32_t status = 0;
 100         u64 addr;
 101
 102         addr = (u64)entry->src_data[0] << 12;
 103         addr |= ((u64)entry->src_data[1] & 0xf) << 44;
 104
 105         if (!amdgpu_sriov_vf(adev)) {
 106                 /*
 107                  * Issue a dummy read to wait for the status register to
 108                  * be updated to avoid reading an incorrect value due to
 109                  * the new fast GRBM interface.
 110                  */
 111                 if (entry->vmid_src == AMDGPU_GFXHUB_0)
 112                         RREG32(hub->vm_l2_pro_fault_status);
 113
 114                 status = RREG32(hub->vm_l2_pro_fault_status);
 115                 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
 116         }
 117
 118         if (printk_ratelimit()) {
 119                 struct amdgpu_task_info task_info;
 120
 121                 memset(&task_info, 0, sizeof(struct amdgpu_task_info));
 122                 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
 123
 124                 dev_err(adev->dev,
 125                         "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, "
 126                         "for process %s pid %d thread %s pid %d)\n",
 127                         entry->vmid_src ? "mmhub" : "gfxhub",
 128                         entry->src_id, entry->ring_id, entry->vmid,
 129                         entry->pasid, task_info.process_name, task_info.tgid,
 130                         task_info.task_name, task_info.pid);
 131                 dev_err(adev->dev, "  in page starting at address 0x%016llx from client %d\n",
 132                         addr, entry->client_id);
 133                 if (!amdgpu_sriov_vf(adev))
 134                         hub->vmhub_funcs->print_l2_protection_fault_status(adev, status);
 135         }
 136
 137         return 0;
 138 }
 139
 140 static const struct amdgpu_irq_src_funcs gmc_v11_0_irq_funcs = {
 141         .set = gmc_v11_0_vm_fault_interrupt_state,
 142         .process = gmc_v11_0_process_interrupt,
 143 };
 144
 145 static const struct amdgpu_irq_src_funcs gmc_v11_0_ecc_funcs = {
 146         .set = gmc_v11_0_ecc_interrupt_state,
 147         .process = amdgpu_umc_process_ecc_irq,
 148 };
 149
 150 static void gmc_v11_0_set_irq_funcs(struct amdgpu_device *adev)
 151 {
 152         adev->gmc.vm_fault.num_types = 1;
 153         adev->gmc.vm_fault.funcs = &gmc_v11_0_irq_funcs;
 154
 155         if (!amdgpu_sriov_vf(adev)) {
 156                 adev->gmc.ecc_irq.num_types = 1;
 157                 adev->gmc.ecc_irq.funcs = &gmc_v11_0_ecc_funcs;
 158         }
 159 }
 160
 161 /**
 162  * gmc_v11_0_use_invalidate_semaphore - judge whether to use semaphore
 163  *
 164  * @adev: amdgpu_device pointer
 165  * @vmhub: vmhub type
 166  *
 167  */
 168 static bool gmc_v11_0_use_invalidate_semaphore(struct amdgpu_device *adev,
 169                                        uint32_t vmhub)
 170 {
 171         return ((vmhub == AMDGPU_MMHUB_0) &&
 172                 (!amdgpu_sriov_vf(adev)));
 173 }
 174
 175 static bool gmc_v11_0_get_vmid_pasid_mapping_info(
 176                                         struct amdgpu_device *adev,
 177                                         uint8_t vmid, uint16_t *p_pasid)
 178 {
 179         *p_pasid = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid) & 0xffff;
 180
 181         return !!(*p_pasid);
 182 }
 183
 184 /*
 185  * GART
 186  * VMID 0 is the physical GPU addresses as used by the kernel.
 187  * VMIDs 1-15 are used for userspace clients and are handled
 188  * by the amdgpu vm/hsa code.
 189  */
 190
 191 static void gmc_v11_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
 192                                    unsigned int vmhub, uint32_t flush_type)
 193 {
 194         bool use_semaphore = gmc_v11_0_use_invalidate_semaphore(adev, vmhub);
 195         struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
 196         u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type);
 197         u32 tmp;
 198         /* Use register 17 for GART */
 199         const unsigned eng = 17;
 200         unsigned int i;
 201         unsigned char hub_ip = 0;
 202
 203         hub_ip = (vmhub == AMDGPU_GFXHUB_0) ?
 204                    GC_HWIP : MMHUB_HWIP;
 205
 206         spin_lock(&adev->gmc.invalidate_lock);
 207         /*
 208          * It may lose gpuvm invalidate acknowldege state across power-gating
 209          * off cycle, add semaphore acquire before invalidation and semaphore
 210          * release after invalidation to avoid entering power gated state
 211          * to WA the Issue
 212          */
 213
 214         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 215         if (use_semaphore) {
 216                 for (i = 0; i < adev->usec_timeout; i++) {
 217                         /* a read return value of 1 means semaphore acuqire */
 218                         tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem +
 219                                             hub->eng_distance * eng, hub_ip);
 220                         if (tmp & 0x1)
 221                                 break;
 222                         udelay(1);
 223                 }
 224
 225                 if (i >= adev->usec_timeout)
 226                         DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
 227         }
 228
 229         WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req, hub_ip);
 230
 231         /* Wait for ACK with a delay.*/
 232         for (i = 0; i < adev->usec_timeout; i++) {
 233                 tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_ack +
 234                                     hub->eng_distance * eng, hub_ip);
 235                 tmp &= 1 << vmid;
 236                 if (tmp)
 237                         break;
 238
 239                 udelay(1);
 240         }
 241
 242         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 243         if (use_semaphore)
 244                 /*
 245                  * add semaphore release after invalidation,
 246                  * write with 0 means semaphore release
 247                  */
 248                 WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem +
 249                               hub->eng_distance * eng, 0, hub_ip);
 250
 251         /* Issue additional private vm invalidation to MMHUB */
 252         if ((vmhub != AMDGPU_GFXHUB_0) &&
 253             (hub->vm_l2_bank_select_reserved_cid2) &&
 254                 !amdgpu_sriov_vf(adev)) {
 255                 inv_req = RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2);
 256                 /* bit 25: RSERVED_CACHE_PRIVATE_INVALIDATION */
 257                 inv_req |= (1 << 25);
 258                 /* Issue private invalidation */
 259                 WREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2, inv_req);
 260                 /* Read back to ensure invalidation is done*/
 261                 RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2);
 262         }
 263
 264         spin_unlock(&adev->gmc.invalidate_lock);
 265
 266         if (i < adev->usec_timeout)
 267                 return;
 268
 269         DRM_ERROR("Timeout waiting for VM flush ACK!\n");
 270 }
 271
 272 /**
 273  * gmc_v11_0_flush_gpu_tlb - gart tlb flush callback
 274  *
 275  * @adev: amdgpu_device pointer
 276  * @vmid: vm instance to flush
 277  * @vmhub: which hub to flush
 278  * @flush_type: the flush type
 279  *
 280  * Flush the TLB for the requested page table.
 281  */
 282 static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
 283                                         uint32_t vmhub, uint32_t flush_type)
 284 {
 285         if ((vmhub == AMDGPU_GFXHUB_0) && !adev->gfx.is_poweron)
 286                 return;
 287
 288         /* flush hdp cache */
 289         adev->hdp.funcs->flush_hdp(adev, NULL);
 290
 291         /* For SRIOV run time, driver shouldn't access the register through MMIO
 292          * Directly use kiq to do the vm invalidation instead
 293          */
 294         if ((adev->gfx.kiq[0].ring.sched.ready || adev->mes.ring.sched.ready) &&
 295             (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) {
 296                 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
 297                 const unsigned eng = 17;
 298                 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type);
 299                 u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
 300                 u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
 301
 302                 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req,
 303                                 1 << vmid);
 304                 return;
 305         }
 306
 307         mutex_lock(&adev->mman.gtt_window_lock);
 308         gmc_v11_0_flush_vm_hub(adev, vmid, vmhub, 0);
 309         mutex_unlock(&adev->mman.gtt_window_lock);
 310         return;
 311 }
 312
 313 /**
 314  * gmc_v11_0_flush_gpu_tlb_pasid - tlb flush via pasid
 315  *
 316  * @adev: amdgpu_device pointer
 317  * @pasid: pasid to be flush
 318  * @flush_type: the flush type
 319  * @all_hub: flush all hubs
 320  *
 321  * Flush the TLB for the requested pasid.
 322  */
 323 static int gmc_v11_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
 324                                         uint16_t pasid, uint32_t flush_type,
 325                                         bool all_hub)
 326 {
 327         int vmid, i;
 328         signed long r;
 329         uint32_t seq;
 330         uint16_t queried_pasid;
 331         bool ret;
 332         struct amdgpu_ring *ring = &adev->gfx.kiq[0].ring;
 333         struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
 334
 335         if (amdgpu_emu_mode == 0 && ring->sched.ready) {
 336                 spin_lock(&adev->gfx.kiq[0].ring_lock);
 337                 /* 2 dwords flush + 8 dwords fence */
 338                 amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8);
 339                 kiq->pmf->kiq_invalidate_tlbs(ring,
 340                                         pasid, flush_type, all_hub);
 341                 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
 342                 if (r) {
 343                         amdgpu_ring_undo(ring);
 344                         spin_unlock(&adev->gfx.kiq[0].ring_lock);
 345                         return -ETIME;
 346                 }
 347
 348                 amdgpu_ring_commit(ring);
 349                 spin_unlock(&adev->gfx.kiq[0].ring_lock);
 350                 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
 351                 if (r < 1) {
 352                         dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r);
 353                         return -ETIME;
 354                 }
 355
 356                 return 0;
 357         }
 358
 359         for (vmid = 1; vmid < 16; vmid++) {
 360
 361                 ret = gmc_v11_0_get_vmid_pasid_mapping_info(adev, vmid,
 362                                 &queried_pasid);
 363                 if (ret && queried_pasid == pasid) {
 364                         if (all_hub) {
 365                                 for (i = 0; i < adev->num_vmhubs; i++)
 366                                         gmc_v11_0_flush_gpu_tlb(adev, vmid,
 367                                                         i, flush_type);
 368                         } else {
 369                                 gmc_v11_0_flush_gpu_tlb(adev, vmid,
 370                                                 AMDGPU_GFXHUB_0, flush_type);
 371                         }
 372                 }
 373         }
 374
 375         return 0;
 376 }
 377
 378 static uint64_t gmc_v11_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 379                                              unsigned vmid, uint64_t pd_addr)
 380 {
 381         bool use_semaphore = gmc_v11_0_use_invalidate_semaphore(ring->adev, ring->vm_hub);
 382         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];
 383         uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0);
 384         unsigned eng = ring->vm_inv_eng;
 385
 386         /*
 387          * It may lose gpuvm invalidate acknowldege state across power-gating
 388          * off cycle, add semaphore acquire before invalidation and semaphore
 389          * release after invalidation to avoid entering power gated state
 390          * to WA the Issue
 391          */
 392
 393         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 394         if (use_semaphore)
 395                 /* a read return value of 1 means semaphore acuqire */
 396                 amdgpu_ring_emit_reg_wait(ring,
 397                                           hub->vm_inv_eng0_sem +
 398                                           hub->eng_distance * eng, 0x1, 0x1);
 399
 400         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
 401                               (hub->ctx_addr_distance * vmid),
 402                               lower_32_bits(pd_addr));
 403
 404         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
 405                               (hub->ctx_addr_distance * vmid),
 406                               upper_32_bits(pd_addr));
 407
 408         amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req +
 409                                             hub->eng_distance * eng,
 410                                             hub->vm_inv_eng0_ack +
 411                                             hub->eng_distance * eng,
 412                                             req, 1 << vmid);
 413
 414         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 415         if (use_semaphore)
 416                 /*
 417                  * add semaphore release after invalidation,
 418                  * write with 0 means semaphore release
 419                  */
 420                 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem +
 421                                       hub->eng_distance * eng, 0);
 422
 423         return pd_addr;
 424 }
 425
 426 static void gmc_v11_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
 427                                          unsigned pasid)
 428 {
 429         struct amdgpu_device *adev = ring->adev;
 430         uint32_t reg;
 431
 432         /* MES fw manages IH_VMID_x_LUT updating */
 433         if (ring->is_mes_queue)
 434                 return;
 435
 436         if (ring->vm_hub == AMDGPU_GFXHUB_0)
 437                 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid;
 438         else
 439                 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT_MM) + vmid;
 440
 441         amdgpu_ring_emit_wreg(ring, reg, pasid);
 442 }
 443
 444 /*
 445  * PTE format:
 446  * 63:59 reserved
 447  * 58:57 reserved
 448  * 56 F
 449  * 55 L
 450  * 54 reserved
 451  * 53:52 SW
 452  * 51 T
 453  * 50:48 mtype
 454  * 47:12 4k physical page base address
 455  * 11:7 fragment
 456  * 6 write
 457  * 5 read
 458  * 4 exe
 459  * 3 Z
 460  * 2 snooped
 461  * 1 system
 462  * 0 valid
 463  *
 464  * PDE format:
 465  * 63:59 block fragment size
 466  * 58:55 reserved
 467  * 54 P
 468  * 53:48 reserved
 469  * 47:6 physical base address of PD or PTE
 470  * 5:3 reserved
 471  * 2 C
 472  * 1 system
 473  * 0 valid
 474  */
 475
 476 static uint64_t gmc_v11_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)
 477 {
 478         switch (flags) {
 479         case AMDGPU_VM_MTYPE_DEFAULT:
 480                 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
 481         case AMDGPU_VM_MTYPE_NC:
 482                 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
 483         case AMDGPU_VM_MTYPE_WC:
 484                 return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC);
 485         case AMDGPU_VM_MTYPE_CC:
 486                 return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC);
 487         case AMDGPU_VM_MTYPE_UC:
 488                 return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC);
 489         default:
 490                 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
 491         }
 492 }
 493
 494 static void gmc_v11_0_get_vm_pde(struct amdgpu_device *adev, int level,
 495                                  uint64_t *addr, uint64_t *flags)
 496 {
 497         if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
 498                 *addr = adev->vm_manager.vram_base_offset + *addr -
 499                         adev->gmc.vram_start;
 500         BUG_ON(*addr & 0xFFFF00000000003FULL);
 501
 502         if (!adev->gmc.translate_further)
 503                 return;
 504
 505         if (level == AMDGPU_VM_PDB1) {
 506                 /* Set the block fragment size */
 507                 if (!(*flags & AMDGPU_PDE_PTE))
 508                         *flags |= AMDGPU_PDE_BFS(0x9);
 509
 510         } else if (level == AMDGPU_VM_PDB0) {
 511                 if (*flags & AMDGPU_PDE_PTE)
 512                         *flags &= ~AMDGPU_PDE_PTE;
 513                 else
 514                         *flags |= AMDGPU_PTE_TF;
 515         }
 516 }
 517
 518 static void gmc_v11_0_get_vm_pte(struct amdgpu_device *adev,
 519                                  struct amdgpu_bo_va_mapping *mapping,
 520                                  uint64_t *flags)
 521 {
 522         struct amdgpu_bo *bo = mapping->bo_va->base.bo;
 523
 524         *flags &= ~AMDGPU_PTE_EXECUTABLE;
 525         *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
 526
 527         *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK;
 528         *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK);
 529
 530         *flags &= ~AMDGPU_PTE_NOALLOC;
 531         *flags |= (mapping->flags & AMDGPU_PTE_NOALLOC);
 532
 533         if (mapping->flags & AMDGPU_PTE_PRT) {
 534                 *flags |= AMDGPU_PTE_PRT;
 535                 *flags |= AMDGPU_PTE_SNOOPED;
 536                 *flags |= AMDGPU_PTE_LOG;
 537                 *flags |= AMDGPU_PTE_SYSTEM;
 538                 *flags &= ~AMDGPU_PTE_VALID;
 539         }
 540
 541         if (bo && bo->flags & (AMDGPU_GEM_CREATE_COHERENT |
 542                                AMDGPU_GEM_CREATE_UNCACHED))
 543                 *flags = (*flags & ~AMDGPU_PTE_MTYPE_NV10_MASK) |
 544                          AMDGPU_PTE_MTYPE_NV10(MTYPE_UC);
 545 }
 546
 547 static unsigned gmc_v11_0_get_vbios_fb_size(struct amdgpu_device *adev)
 548 {
 549         return 0;
 550 }
 551
 552 static const struct amdgpu_gmc_funcs gmc_v11_0_gmc_funcs = {
 553         .flush_gpu_tlb = gmc_v11_0_flush_gpu_tlb,
 554         .flush_gpu_tlb_pasid = gmc_v11_0_flush_gpu_tlb_pasid,
 555         .emit_flush_gpu_tlb = gmc_v11_0_emit_flush_gpu_tlb,
 556         .emit_pasid_mapping = gmc_v11_0_emit_pasid_mapping,
 557         .map_mtype = gmc_v11_0_map_mtype,
 558         .get_vm_pde = gmc_v11_0_get_vm_pde,
 559         .get_vm_pte = gmc_v11_0_get_vm_pte,
 560         .get_vbios_fb_size = gmc_v11_0_get_vbios_fb_size,
 561 };
 562
 563 static void gmc_v11_0_set_gmc_funcs(struct amdgpu_device *adev)
 564 {
 565         adev->gmc.gmc_funcs = &gmc_v11_0_gmc_funcs;
 566 }
 567
 568 static void gmc_v11_0_set_umc_funcs(struct amdgpu_device *adev)
 569 {
 570         switch (adev->ip_versions[UMC_HWIP][0]) {
 571         case IP_VERSION(8, 10, 0):
 572                 adev->umc.channel_inst_num = UMC_V8_10_CHANNEL_INSTANCE_NUM;
 573                 adev->umc.umc_inst_num = UMC_V8_10_UMC_INSTANCE_NUM;
 574                 adev->umc.max_ras_err_cnt_per_query = UMC_V8_10_TOTAL_CHANNEL_NUM(adev);
 575                 adev->umc.channel_offs = UMC_V8_10_PER_CHANNEL_OFFSET;
 576                 adev->umc.retire_unit = UMC_V8_10_NA_COL_2BITS_POWER_OF_2_NUM;
 577                 if (adev->umc.node_inst_num == 4)
 578                         adev->umc.channel_idx_tbl = &umc_v8_10_channel_idx_tbl_ext0[0][0][0];
 579                 else
 580                         adev->umc.channel_idx_tbl = &umc_v8_10_channel_idx_tbl[0][0][0];
 581                 adev->umc.ras = &umc_v8_10_ras;
 582                 break;
 583         case IP_VERSION(8, 11, 0):
 584                 break;
 585         default:
 586                 break;
 587         }
 588 }
 589
 590
 591 static void gmc_v11_0_set_mmhub_funcs(struct amdgpu_device *adev)
 592 {
 593         switch (adev->ip_versions[MMHUB_HWIP][0]) {
 594         case IP_VERSION(3, 0, 1):
 595                 adev->mmhub.funcs = &mmhub_v3_0_1_funcs;
 596                 break;
 597         case IP_VERSION(3, 0, 2):
 598                 adev->mmhub.funcs = &mmhub_v3_0_2_funcs;
 599                 break;
 600         default:
 601                 adev->mmhub.funcs = &mmhub_v3_0_funcs;
 602                 break;
 603         }
 604 }
 605
 606 static void gmc_v11_0_set_gfxhub_funcs(struct amdgpu_device *adev)
 607 {
 608         switch (adev->ip_versions[GC_HWIP][0]) {
 609         case IP_VERSION(11, 0, 3):
 610                 adev->gfxhub.funcs = &gfxhub_v3_0_3_funcs;
 611                 break;
 612         default:
 613                 adev->gfxhub.funcs = &gfxhub_v3_0_funcs;
 614                 break;
 615         }
 616 }
 617
 618 static int gmc_v11_0_early_init(void *handle)
 619 {
 620         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 621
 622         gmc_v11_0_set_gfxhub_funcs(adev);
 623         gmc_v11_0_set_mmhub_funcs(adev);
 624         gmc_v11_0_set_gmc_funcs(adev);
 625         gmc_v11_0_set_irq_funcs(adev);
 626         gmc_v11_0_set_umc_funcs(adev);
 627
 628         adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
 629         adev->gmc.shared_aperture_end =
 630                 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
 631         adev->gmc.private_aperture_start = 0x1000000000000000ULL;
 632         adev->gmc.private_aperture_end =
 633                 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
 634
 635         return 0;
 636 }
 637
 638 static int gmc_v11_0_late_init(void *handle)
 639 {
 640         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 641         int r;
 642
 643         r = amdgpu_gmc_allocate_vm_inv_eng(adev);
 644         if (r)
 645                 return r;
 646
 647         r = amdgpu_gmc_ras_late_init(adev);
 648         if (r)
 649                 return r;
 650
 651         return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
 652 }
 653
 654 static void gmc_v11_0_vram_gtt_location(struct amdgpu_device *adev,
 655                                         struct amdgpu_gmc *mc)
 656 {
 657         u64 base = 0;
 658
 659         base = adev->mmhub.funcs->get_fb_location(adev);
 660
 661         amdgpu_gmc_vram_location(adev, &adev->gmc, base);
 662         amdgpu_gmc_gart_location(adev, mc);
 663         amdgpu_gmc_agp_location(adev, mc);
 664
 665         /* base offset of vram pages */
 666         if (amdgpu_sriov_vf(adev))
 667                 adev->vm_manager.vram_base_offset = 0;
 668         else
 669                 adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev);
 670 }
 671
 672 /**
 673  * gmc_v11_0_mc_init - initialize the memory controller driver params
 674  *
 675  * @adev: amdgpu_device pointer
 676  *
 677  * Look up the amount of vram, vram width, and decide how to place
 678  * vram and gart within the GPU's physical address space.
 679  * Returns 0 for success.
 680  */
 681 static int gmc_v11_0_mc_init(struct amdgpu_device *adev)
 682 {
 683         int r;
 684
 685         /* size in MB on si */
 686         adev->gmc.mc_vram_size =
 687                 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
 688         adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
 689
 690         if (!(adev->flags & AMD_IS_APU)) {
 691                 r = amdgpu_device_resize_fb_bar(adev);
 692                 if (r)
 693                         return r;
 694         }
 695         adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
 696         adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
 697
 698 #ifdef CONFIG_X86_64
 699         if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) {
 700                 adev->gmc.aper_base = adev->mmhub.funcs->get_mc_fb_offset(adev);
 701                 adev->gmc.aper_size = adev->gmc.real_vram_size;
 702         }
 703 #endif
 704         /* In case the PCI BAR is larger than the actual amount of vram */
 705         adev->gmc.visible_vram_size = adev->gmc.aper_size;
 706         if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
 707                 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
 708
 709         /* set the gart size */
 710         if (amdgpu_gart_size == -1) {
 711                 adev->gmc.gart_size = 512ULL << 20;
 712         } else
 713                 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
 714
 715         gmc_v11_0_vram_gtt_location(adev, &adev->gmc);
 716
 717         return 0;
 718 }
 719
 720 static int gmc_v11_0_gart_init(struct amdgpu_device *adev)
 721 {
 722         int r;
 723
 724         if (adev->gart.bo) {
 725                 WARN(1, "PCIE GART already initialized\n");
 726                 return 0;
 727         }
 728
 729         /* Initialize common gart structure */
 730         r = amdgpu_gart_init(adev);
 731         if (r)
 732                 return r;
 733
 734         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 735         adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) |
 736                                  AMDGPU_PTE_EXECUTABLE;
 737
 738         return amdgpu_gart_table_vram_alloc(adev);
 739 }
 740
 741 static int gmc_v11_0_sw_init(void *handle)
 742 {
 743         int r, vram_width = 0, vram_type = 0, vram_vendor = 0;
 744         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 745
 746         adev->mmhub.funcs->init(adev);
 747
 748         spin_lock_init(&adev->gmc.invalidate_lock);
 749
 750         r = amdgpu_atomfirmware_get_vram_info(adev,
 751                                               &vram_width, &vram_type, &vram_vendor);
 752         adev->gmc.vram_width = vram_width;
 753
 754         adev->gmc.vram_type = vram_type;
 755         adev->gmc.vram_vendor = vram_vendor;
 756
 757         switch (adev->ip_versions[GC_HWIP][0]) {
 758         case IP_VERSION(11, 0, 0):
 759         case IP_VERSION(11, 0, 1):
 760         case IP_VERSION(11, 0, 2):
 761         case IP_VERSION(11, 0, 3):
 762         case IP_VERSION(11, 0, 4):
 763                 adev->num_vmhubs = 2;
 764                 /*
 765                  * To fulfill 4-level page support,
 766                  * vm size is 256TB (48bit), maximum size,
 767                  * block size 512 (9bit)
 768                  */
 769                 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
 770                 break;
 771         default:
 772                 break;
 773         }
 774
 775         /* This interrupt is VMC page fault.*/
 776         r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_VMC,
 777                               VMC_1_0__SRCID__VM_FAULT,
 778                               &adev->gmc.vm_fault);
 779
 780         if (r)
 781                 return r;
 782
 783         r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX,
 784                               UTCL2_1_0__SRCID__FAULT,
 785                               &adev->gmc.vm_fault);
 786         if (r)
 787                 return r;
 788
 789         if (!amdgpu_sriov_vf(adev)) {
 790                 /* interrupt sent to DF. */
 791                 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_DF, 0,
 792                                       &adev->gmc.ecc_irq);
 793                 if (r)
 794                         return r;
 795         }
 796
 797         /*
 798          * Set the internal MC address mask This is the max address of the GPU's
 799          * internal address space.
 800          */
 801         adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
 802
 803         r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
 804         if (r) {
 805                 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
 806                 return r;
 807         }
 808
 809         adev->need_swiotlb = drm_need_swiotlb(44);
 810
 811         r = gmc_v11_0_mc_init(adev);
 812         if (r)
 813                 return r;
 814
 815         amdgpu_gmc_get_vbios_allocations(adev);
 816
 817         /* Memory manager */
 818         r = amdgpu_bo_init(adev);
 819         if (r)
 820                 return r;
 821
 822         r = gmc_v11_0_gart_init(adev);
 823         if (r)
 824                 return r;
 825
 826         /*
 827          * number of VMs
 828          * VMID 0 is reserved for System
 829          * amdgpu graphics/compute will use VMIDs 1-7
 830          * amdkfd will use VMIDs 8-15
 831          */
 832         adev->vm_manager.first_kfd_vmid = 8;
 833
 834         amdgpu_vm_manager_init(adev);
 835
 836         r = amdgpu_gmc_ras_sw_init(adev);
 837         if (r)
 838                 return r;
 839
 840         return 0;
 841 }
 842
 843 /**
 844  * gmc_v11_0_gart_fini - vm fini callback
 845  *
 846  * @adev: amdgpu_device pointer
 847  *
 848  * Tears down the driver GART/VM setup (CIK).
 849  */
 850 static void gmc_v11_0_gart_fini(struct amdgpu_device *adev)
 851 {
 852         amdgpu_gart_table_vram_free(adev);
 853 }
 854
 855 static int gmc_v11_0_sw_fini(void *handle)
 856 {
 857         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 858
 859         amdgpu_vm_manager_fini(adev);
 860         gmc_v11_0_gart_fini(adev);
 861         amdgpu_gem_force_release(adev);
 862         amdgpu_bo_fini(adev);
 863
 864         return 0;
 865 }
 866
 867 static void gmc_v11_0_init_golden_registers(struct amdgpu_device *adev)
 868 {
 869         if (amdgpu_sriov_vf(adev)) {
 870                 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 871
 872                 WREG32(hub->vm_contexts_disable, 0);
 873                 return;
 874         }
 875 }
 876
 877 /**
 878  * gmc_v11_0_gart_enable - gart enable
 879  *
 880  * @adev: amdgpu_device pointer
 881  */
 882 static int gmc_v11_0_gart_enable(struct amdgpu_device *adev)
 883 {
 884         int r;
 885         bool value;
 886
 887         if (adev->gart.bo == NULL) {
 888                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 889                 return -EINVAL;
 890         }
 891
 892         amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
 893
 894         r = adev->mmhub.funcs->gart_enable(adev);
 895         if (r)
 896                 return r;
 897
 898         /* Flush HDP after it is initialized */
 899         adev->hdp.funcs->flush_hdp(adev, NULL);
 900
 901         value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
 902                 false : true;
 903
 904         adev->mmhub.funcs->set_fault_enable_default(adev, value);
 905         gmc_v11_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0);
 906
 907         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 908                  (unsigned)(adev->gmc.gart_size >> 20),
 909                  (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
 910
 911         return 0;
 912 }
 913
 914 static int gmc_v11_0_hw_init(void *handle)
 915 {
 916         int r;
 917         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 918
 919         /* The sequence of these two function calls matters.*/
 920         gmc_v11_0_init_golden_registers(adev);
 921
 922         r = gmc_v11_0_gart_enable(adev);
 923         if (r)
 924                 return r;
 925
 926         if (adev->umc.funcs && adev->umc.funcs->init_registers)
 927                 adev->umc.funcs->init_registers(adev);
 928
 929         return 0;
 930 }
 931
 932 /**
 933  * gmc_v11_0_gart_disable - gart disable
 934  *
 935  * @adev: amdgpu_device pointer
 936  *
 937  * This disables all VM page table.
 938  */
 939 static void gmc_v11_0_gart_disable(struct amdgpu_device *adev)
 940 {
 941         adev->mmhub.funcs->gart_disable(adev);
 942 }
 943
 944 static int gmc_v11_0_hw_fini(void *handle)
 945 {
 946         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 947
 948         if (amdgpu_sriov_vf(adev)) {
 949                 /* full access mode, so don't touch any GMC register */
 950                 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
 951                 return 0;
 952         }
 953
 954         amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
 955         gmc_v11_0_gart_disable(adev);
 956
 957         return 0;
 958 }
 959
 960 static int gmc_v11_0_suspend(void *handle)
 961 {
 962         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 963
 964         gmc_v11_0_hw_fini(adev);
 965
 966         return 0;
 967 }
 968
 969 static int gmc_v11_0_resume(void *handle)
 970 {
 971         int r;
 972         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 973
 974         r = gmc_v11_0_hw_init(adev);
 975         if (r)
 976                 return r;
 977
 978         amdgpu_vmid_reset_all(adev);
 979
 980         return 0;
 981 }
 982
 983 static bool gmc_v11_0_is_idle(void *handle)
 984 {
 985         /* MC is always ready in GMC v11.*/
 986         return true;
 987 }
 988
 989 static int gmc_v11_0_wait_for_idle(void *handle)
 990 {
 991         /* There is no need to wait for MC idle in GMC v11.*/
 992         return 0;
 993 }
 994
 995 static int gmc_v11_0_soft_reset(void *handle)
 996 {
 997         return 0;
 998 }
 999
1000 static int gmc_v11_0_set_clockgating_state(void *handle,
1001                                            enum amd_clockgating_state state)
1002 {
1003         int r;
1004         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1005
1006         r = adev->mmhub.funcs->set_clockgating(adev, state);
1007         if (r)
1008                 return r;
1009
1010         return athub_v3_0_set_clockgating(adev, state);
1011 }
1012
1013 static void gmc_v11_0_get_clockgating_state(void *handle, u64 *flags)
1014 {
1015         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1016
1017         adev->mmhub.funcs->get_clockgating(adev, flags);
1018
1019         athub_v3_0_get_clockgating(adev, flags);
1020 }
1021
1022 static int gmc_v11_0_set_powergating_state(void *handle,
1023                                            enum amd_powergating_state state)
1024 {
1025         return 0;
1026 }
1027
1028 const struct amd_ip_funcs gmc_v11_0_ip_funcs = {
1029         .name = "gmc_v11_0",
1030         .early_init = gmc_v11_0_early_init,
1031         .sw_init = gmc_v11_0_sw_init,
1032         .hw_init = gmc_v11_0_hw_init,
1033         .late_init = gmc_v11_0_late_init,
1034         .sw_fini = gmc_v11_0_sw_fini,
1035         .hw_fini = gmc_v11_0_hw_fini,
1036         .suspend = gmc_v11_0_suspend,
1037         .resume = gmc_v11_0_resume,
1038         .is_idle = gmc_v11_0_is_idle,
1039         .wait_for_idle = gmc_v11_0_wait_for_idle,
1040         .soft_reset = gmc_v11_0_soft_reset,
1041         .set_clockgating_state = gmc_v11_0_set_clockgating_state,
1042         .set_powergating_state = gmc_v11_0_set_powergating_state,
1043         .get_clockgating_state = gmc_v11_0_get_clockgating_state,
1044 };
1045
1046 const struct amdgpu_ip_block_version gmc_v11_0_ip_block = {
1047         .type = AMD_IP_BLOCK_TYPE_GMC,
1048         .major = 11,
1049         .minor = 0,
1050         .rev = 0,
1051         .funcs = &gmc_v11_0_ip_funcs,
1052 };