drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "amdgpu.h"
  25 #include "gfxhub_v2_0.h"
  26
  27 #include "gc/gc_10_1_0_offset.h"
  28 #include "gc/gc_10_1_0_sh_mask.h"
  29 #include "gc/gc_10_1_0_default.h"
  30 #include "navi10_enum.h"
  31
  32 #include "soc15_common.h"
  33
  34 u64 gfxhub_v2_0_get_fb_location(struct amdgpu_device *adev)
  35 {
  36         u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE);
  37
  38         base &= GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
  39         base <<= 24;
  40
  41         return base;
  42 }
  43
  44 u64 gfxhub_v2_0_get_mc_fb_offset(struct amdgpu_device *adev)
  45 {
  46         return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24;
  47 }
  48
  49 void gfxhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
  50                                 uint64_t page_table_base)
  51 {
  52         /* two registers distance between mmGCVM_CONTEXT0_* to mmGCVM_CONTEXT1_* */
  53         int offset = mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
  54                         - mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
  55
  56         WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
  57                                 offset * vmid, lower_32_bits(page_table_base));
  58
  59         WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
  60                                 offset * vmid, upper_32_bits(page_table_base));
  61 }
  62
  63 static void gfxhub_v2_0_init_gart_aperture_regs(struct amdgpu_device *adev)
  64 {
  65         uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
  66
  67         gfxhub_v2_0_setup_vm_pt_regs(adev, 0, pt_base);
  68
  69         WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
  70                      (u32)(adev->gmc.gart_start >> 12));
  71         WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
  72                      (u32)(adev->gmc.gart_start >> 44));
  73
  74         WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
  75                      (u32)(adev->gmc.gart_end >> 12));
  76         WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
  77                      (u32)(adev->gmc.gart_end >> 44));
  78 }
  79
  80 static void gfxhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev)
  81 {
  82         uint64_t value;
  83
  84         if (!amdgpu_sriov_vf(adev)) {
  85                 /*
  86                  * the new L1 policy will block SRIOV guest from writing
  87                  * these regs, and they will be programed at host.
  88                  * so skip programing these regs.
  89                  */
  90                 /* Disable AGP. */
  91                 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0);
  92                 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, 0);
  93                 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, 0x00FFFFFF);
  94
  95                 /* Program the system aperture low logical page number. */
  96                 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR,
  97                              adev->gmc.vram_start >> 18);
  98                 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
  99                              adev->gmc.vram_end >> 18);
 100
 101                 /* Set default page address. */
 102                 value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start
 103                         + adev->vm_manager.vram_base_offset;
 104                 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
 105                              (u32)(value >> 12));
 106                 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
 107                              (u32)(value >> 44));
 108         }
 109
 110         /* Program "protection fault". */
 111         WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
 112                      (u32)(adev->dummy_page_addr >> 12));
 113         WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
 114                      (u32)((u64)adev->dummy_page_addr >> 44));
 115
 116         WREG32_FIELD15(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2,
 117                        ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
 118 }
 119
 120
 121 static void gfxhub_v2_0_init_tlb_regs(struct amdgpu_device *adev)
 122 {
 123         uint32_t tmp;
 124
 125         /* Setup TLB control */
 126         tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);
 127
 128         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 129         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 130         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
 131                             ENABLE_ADVANCED_DRIVER_MODEL, 1);
 132         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
 133                             SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 134         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
 135         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
 136                             MTYPE, MTYPE_UC); /* UC, uncached */
 137
 138         WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp);
 139 }
 140
 141 static void gfxhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
 142 {
 143         uint32_t tmp;
 144
 145         /* These regs are not accessible for VF, PF will program these in SRIOV */
 146         if (amdgpu_sriov_vf(adev))
 147                 return;
 148
 149         /* Setup L2 cache */
 150         tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);
 151         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);
 152         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
 153         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
 154                             ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 155         /* XXX for emulation, Refer to closed source code.*/
 156         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
 157                             L2_PDE0_CACHE_TAG_GENERATION_MODE, 0);
 158         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
 159         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 160         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
 161         WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp);
 162
 163         tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2);
 164         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 165         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 166         WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp);
 167
 168         tmp = mmGCVM_L2_CNTL3_DEFAULT;
 169         if (adev->gmc.translate_further) {
 170                 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);
 171                 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
 172                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
 173         } else {
 174                 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);
 175                 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
 176                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
 177         }
 178         WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp);
 179
 180         tmp = mmGCVM_L2_CNTL4_DEFAULT;
 181         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
 182         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
 183         WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp);
 184 }
 185
 186 static void gfxhub_v2_0_enable_system_domain(struct amdgpu_device *adev)
 187 {
 188         uint32_t tmp;
 189
 190         tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL);
 191         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 192         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 193         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,
 194                             RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
 195         WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL, tmp);
 196 }
 197
 198 static void gfxhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev)
 199 {
 200         WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
 201                      0xFFFFFFFF);
 202         WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
 203                      0x0000000F);
 204
 205         WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
 206                      0);
 207         WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
 208                      0);
 209
 210         WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);
 211         WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);
 212
 213 }
 214
 215 static void gfxhub_v2_0_setup_vmid_config(struct amdgpu_device *adev)
 216 {
 217         int i;
 218         uint32_t tmp;
 219
 220         for (i = 0; i <= 14; i++) {
 221                 tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i);
 222                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 223                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
 224                                     adev->vm_manager.num_level);
 225                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 226                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 227                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 228                                 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 229                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 230                                 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 231                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 232                                 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 233                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 234                                 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 235                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 236                                 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 237                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 238                                 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 239                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 240                                 PAGE_TABLE_BLOCK_SIZE,
 241                                 adev->vm_manager.block_size - 9);
 242                 /* Send no-retry XNACK on fault to suppress VM fault storm. */
 243                 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
 244                                     RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
 245                                     !amdgpu_noretry);
 246                 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i, tmp);
 247                 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0);
 248                 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0);
 249                 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,  i*2,
 250                         lower_32_bits(adev->vm_manager.max_pfn - 1));
 251                 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2,
 252                         upper_32_bits(adev->vm_manager.max_pfn - 1));
 253         }
 254 }
 255
 256 static void gfxhub_v2_0_program_invalidation(struct amdgpu_device *adev)
 257 {
 258         unsigned i;
 259
 260         for (i = 0 ; i < 18; ++i) {
 261                 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
 262                                     2 * i, 0xffffffff);
 263                 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
 264                                     2 * i, 0x1f);
 265         }
 266 }
 267
 268 int gfxhub_v2_0_gart_enable(struct amdgpu_device *adev)
 269 {
 270         /* GART Enable. */
 271         gfxhub_v2_0_init_gart_aperture_regs(adev);
 272         gfxhub_v2_0_init_system_aperture_regs(adev);
 273         gfxhub_v2_0_init_tlb_regs(adev);
 274         gfxhub_v2_0_init_cache_regs(adev);
 275
 276         gfxhub_v2_0_enable_system_domain(adev);
 277         gfxhub_v2_0_disable_identity_aperture(adev);
 278         gfxhub_v2_0_setup_vmid_config(adev);
 279         gfxhub_v2_0_program_invalidation(adev);
 280
 281         return 0;
 282 }
 283
 284 void gfxhub_v2_0_gart_disable(struct amdgpu_device *adev)
 285 {
 286         u32 tmp;
 287         u32 i;
 288
 289         /* Disable all tables */
 290         for (i = 0; i < 16; i++)
 291                 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL, i, 0);
 292
 293         /* Setup TLB control */
 294         tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);
 295         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 296         tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
 297                             ENABLE_ADVANCED_DRIVER_MODEL, 0);
 298         WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp);
 299
 300         if (!amdgpu_sriov_vf(adev)) {
 301                 /* Setup L2 cache */
 302                 WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0);
 303                 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0);
 304         }
 305 }
 306
 307 /**
 308  * gfxhub_v2_0_set_fault_enable_default - update GART/VM fault handling
 309  *
 310  * @adev: amdgpu_device pointer
 311  * @value: true redirects VM faults to the default page
 312  */
 313 void gfxhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev,
 314                                           bool value)
 315 {
 316         u32 tmp;
 317         tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);
 318         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 319                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 320         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 321                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 322         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 323                             PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 324         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 325                             PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 326         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 327                             TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
 328                             value);
 329         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 330                             NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 331         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 332                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 333         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 334                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 335         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 336                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 337         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 338                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 339         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 340                             EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 341         if (!value) {
 342                 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 343                                 CRASH_ON_NO_RETRY_FAULT, 1);
 344                 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
 345                                 CRASH_ON_RETRY_FAULT, 1);
 346         }
 347         WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp);
 348 }
 349
 350 void gfxhub_v2_0_init(struct amdgpu_device *adev)
 351 {
 352         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 353
 354         hub->ctx0_ptb_addr_lo32 =
 355                 SOC15_REG_OFFSET(GC, 0,
 356                                  mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
 357         hub->ctx0_ptb_addr_hi32 =
 358                 SOC15_REG_OFFSET(GC, 0,
 359                                  mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
 360         hub->vm_inv_eng0_sem =
 361                 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_SEM);
 362         hub->vm_inv_eng0_req =
 363                 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_REQ);
 364         hub->vm_inv_eng0_ack =
 365                 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ACK);
 366         hub->vm_context0_cntl =
 367                 SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL);
 368         hub->vm_l2_pro_fault_status =
 369                 SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS);
 370         hub->vm_l2_pro_fault_cntl =
 371                 SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);
 372 }