drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

   1 /*
   2  * Copyright 2022 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "amdgpu_xcp.h"
  25 #include "gfxhub_v1_2.h"
  26 #include "gfxhub_v1_1.h"
  27
  28 #include "gc/gc_9_4_3_offset.h"
  29 #include "gc/gc_9_4_3_sh_mask.h"
  30 #include "vega10_enum.h"
  31
  32 #include "soc15_common.h"
  33
  34 #define regVM_L2_CNTL3_DEFAULT  0x80100007
  35 #define regVM_L2_CNTL4_DEFAULT  0x000000c1
  36
  37 static u64 gfxhub_v1_2_get_mc_fb_offset(struct amdgpu_device *adev)
  38 {
  39         return (u64)RREG32_SOC15(GC, GET_INST(GC, 0), regMC_VM_FB_OFFSET) << 24;
  40 }
  41
  42 static void gfxhub_v1_2_xcc_setup_vm_pt_regs(struct amdgpu_device *adev,
  43                                              uint32_t vmid,
  44                                              uint64_t page_table_base,
  45                                              uint32_t xcc_mask)
  46 {
  47         struct amdgpu_vmhub *hub;
  48         int i;
  49
  50         for_each_inst(i, xcc_mask) {
  51                 hub = &adev->vmhub[AMDGPU_GFXHUB(i)];
  52                 WREG32_SOC15_OFFSET(GC, GET_INST(GC, i),
  53                                     regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
  54                                     hub->ctx_addr_distance * vmid,
  55                                     lower_32_bits(page_table_base));
  56
  57                 WREG32_SOC15_OFFSET(GC, GET_INST(GC, i),
  58                                     regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
  59                                     hub->ctx_addr_distance * vmid,
  60                                     upper_32_bits(page_table_base));
  61         }
  62 }
  63
  64 static void gfxhub_v1_2_setup_vm_pt_regs(struct amdgpu_device *adev,
  65                                          uint32_t vmid,
  66                                          uint64_t page_table_base)
  67 {
  68         uint32_t xcc_mask;
  69
  70         xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0);
  71         gfxhub_v1_2_xcc_setup_vm_pt_regs(adev, vmid, page_table_base, xcc_mask);
  72 }
  73
  74 static void gfxhub_v1_2_xcc_init_gart_aperture_regs(struct amdgpu_device *adev,
  75                                                     uint32_t xcc_mask)
  76 {
  77         uint64_t pt_base;
  78         int i;
  79
  80         if (adev->gmc.pdb0_bo)
  81                 pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo);
  82         else
  83                 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
  84
  85         gfxhub_v1_2_xcc_setup_vm_pt_regs(adev, 0, pt_base, xcc_mask);
  86
  87         /* If use GART for FB translation, vmid0 page table covers both
  88          * vram and system memory (gart)
  89          */
  90         for_each_inst(i, xcc_mask) {
  91                 if (adev->gmc.pdb0_bo) {
  92                         WREG32_SOC15(GC, GET_INST(GC, i),
  93                                      regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
  94                                      (u32)(adev->gmc.fb_start >> 12));
  95                         WREG32_SOC15(GC, GET_INST(GC, i),
  96                                      regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
  97                                      (u32)(adev->gmc.fb_start >> 44));
  98
  99                         WREG32_SOC15(GC, GET_INST(GC, i),
 100                                      regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
 101                                      (u32)(adev->gmc.gart_end >> 12));
 102                         WREG32_SOC15(GC, GET_INST(GC, i),
 103                                      regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
 104                                      (u32)(adev->gmc.gart_end >> 44));
 105                 } else {
 106                         WREG32_SOC15(GC, GET_INST(GC, i),
 107                                      regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
 108                                      (u32)(adev->gmc.gart_start >> 12));
 109                         WREG32_SOC15(GC, GET_INST(GC, i),
 110                                      regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
 111                                      (u32)(adev->gmc.gart_start >> 44));
 112
 113                         WREG32_SOC15(GC, GET_INST(GC, i),
 114                                      regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
 115                                      (u32)(adev->gmc.gart_end >> 12));
 116                         WREG32_SOC15(GC, GET_INST(GC, i),
 117                                      regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
 118                                      (u32)(adev->gmc.gart_end >> 44));
 119                 }
 120         }
 121 }
 122
 123 static void
 124 gfxhub_v1_2_xcc_init_system_aperture_regs(struct amdgpu_device *adev,
 125                                           uint32_t xcc_mask)
 126 {
 127         uint64_t value;
 128         uint32_t tmp;
 129         int i;
 130
 131         for_each_inst(i, xcc_mask) {
 132                 /* Program the AGP BAR */
 133                 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_AGP_BASE, 0);
 134                 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
 135                 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
 136
 137                 if (!amdgpu_sriov_vf(adev) || adev->asic_type <= CHIP_VEGA10) {
 138                         /* Program the system aperture low logical page number. */
 139                         WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 140                                 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
 141
 142                         if (adev->apu_flags & AMD_APU_IS_RAVEN2)
 143                                 /*
 144                                 * Raven2 has a HW issue that it is unable to use the
 145                                 * vram which is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR.
 146                                 * So here is the workaround that increase system
 147                                 * aperture high address (add 1) to get rid of the VM
 148                                 * fault and hardware hang.
 149                                 */
 150                                 WREG32_SOC15_RLC(GC, GET_INST(GC, i),
 151                                                  regMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 152                                                  max((adev->gmc.fb_end >> 18) + 0x1,
 153                                                      adev->gmc.agp_end >> 18));
 154                         else
 155                                 WREG32_SOC15_RLC(GC, GET_INST(GC, i),
 156                                         regMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 157                                         max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 158
 159                         /* Set default page address. */
 160                         value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);
 161                         WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
 162                                      (u32)(value >> 12));
 163                         WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
 164                                      (u32)(value >> 44));
 165
 166                         /* Program "protection fault". */
 167                         WREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
 168                                      (u32)(adev->dummy_page_addr >> 12));
 169                         WREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
 170                                      (u32)((u64)adev->dummy_page_addr >> 44));
 171
 172                         tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL2);
 173                         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
 174                                             ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
 175                         WREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL2, tmp);
 176                 }
 177
 178                 /* In the case squeezing vram into GART aperture, we don't use
 179                  * FB aperture and AGP aperture. Disable them.
 180                  */
 181                 if (adev->gmc.pdb0_bo) {
 182                         WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_FB_LOCATION_TOP, 0);
 183                         WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_FB_LOCATION_BASE, 0x00FFFFFF);
 184                         WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_AGP_TOP, 0);
 185                         WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_AGP_BOT, 0xFFFFFF);
 186                         WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x3FFFFFFF);
 187                         WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0);
 188                 }
 189         }
 190 }
 191
 192 static void gfxhub_v1_2_xcc_init_tlb_regs(struct amdgpu_device *adev,
 193                                           uint32_t xcc_mask)
 194 {
 195         uint32_t tmp;
 196         int i;
 197
 198         for_each_inst(i, xcc_mask) {
 199                 /* Setup TLB control */
 200                 tmp = RREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_MX_L1_TLB_CNTL);
 201
 202                 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 203                                     ENABLE_L1_TLB, 1);
 204                 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 205                                     SYSTEM_ACCESS_MODE, 3);
 206                 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 207                                     ENABLE_ADVANCED_DRIVER_MODEL, 1);
 208                 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 209                                     SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 210                 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 211                                     MTYPE, MTYPE_UC);/* XXX for emulation. */
 212                 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
 213
 214                 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_MX_L1_TLB_CNTL, tmp);
 215         }
 216 }
 217
 218 static void gfxhub_v1_2_xcc_init_cache_regs(struct amdgpu_device *adev,
 219                                             uint32_t xcc_mask)
 220 {
 221         uint32_t tmp;
 222         int i;
 223
 224         for_each_inst(i, xcc_mask) {
 225                 /* Setup L2 cache */
 226                 tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_CNTL);
 227                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 228                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 229                 /* XXX for emulation, Refer to closed source code.*/
 230                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
 231                                     0);
 232                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
 233                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 234                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
 235                 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL, tmp);
 236
 237                 tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_CNTL2);
 238                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 239                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 240                 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL2, tmp);
 241
 242                 tmp = regVM_L2_CNTL3_DEFAULT;
 243                 if (adev->gmc.translate_further) {
 244                         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
 245                         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
 246                                             L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
 247                 } else {
 248                         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
 249                         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
 250                                             L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
 251                 }
 252                 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL3, tmp);
 253
 254                 tmp = regVM_L2_CNTL4_DEFAULT;
 255                 if (adev->gmc.xgmi.connected_to_cpu) {
 256                         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 1);
 257                         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 1);
 258                 } else {
 259                         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
 260                         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
 261                 }
 262                 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regVM_L2_CNTL4, tmp);
 263         }
 264 }
 265
 266 static void gfxhub_v1_2_xcc_enable_system_domain(struct amdgpu_device *adev,
 267                                                  uint32_t xcc_mask)
 268 {
 269         uint32_t tmp;
 270         int i;
 271
 272         for_each_inst(i, xcc_mask) {
 273                 tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_CONTEXT0_CNTL);
 274                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 275                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH,
 276                                 adev->gmc.vmid0_page_table_depth);
 277                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE,
 278                                 adev->gmc.vmid0_page_table_block_size);
 279                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,
 280                                     RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
 281                 WREG32_SOC15(GC, GET_INST(GC, i), regVM_CONTEXT0_CNTL, tmp);
 282         }
 283 }
 284
 285 static void
 286 gfxhub_v1_2_xcc_disable_identity_aperture(struct amdgpu_device *adev,
 287                                           uint32_t xcc_mask)
 288 {
 289         int i;
 290
 291         for_each_inst(i, xcc_mask) {
 292                 WREG32_SOC15(GC, GET_INST(GC, i),
 293                              regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
 294                              0XFFFFFFFF);
 295                 WREG32_SOC15(GC, GET_INST(GC, i),
 296                              regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
 297                              0x0000000F);
 298
 299                 WREG32_SOC15(GC, GET_INST(GC, i),
 300                              regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
 301                              0);
 302                 WREG32_SOC15(GC, GET_INST(GC, i),
 303                              regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
 304                              0);
 305
 306                 WREG32_SOC15(GC, GET_INST(GC, i),
 307                              regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);
 308                 WREG32_SOC15(GC, GET_INST(GC, i),
 309                              regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);
 310         }
 311 }
 312
 313 static void gfxhub_v1_2_xcc_setup_vmid_config(struct amdgpu_device *adev,
 314                                               uint32_t xcc_mask)
 315 {
 316         struct amdgpu_vmhub *hub;
 317         unsigned num_level, block_size;
 318         uint32_t tmp;
 319         int i, j;
 320
 321         num_level = adev->vm_manager.num_level;
 322         block_size = adev->vm_manager.block_size;
 323         if (adev->gmc.translate_further)
 324                 num_level -= 1;
 325         else
 326                 block_size -= 9;
 327
 328         for_each_inst(j, xcc_mask) {
 329                 hub = &adev->vmhub[AMDGPU_GFXHUB(j)];
 330                 for (i = 0; i <= 14; i++) {
 331                         tmp = RREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_CONTEXT1_CNTL, i);
 332                         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 333                         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
 334                                             num_level);
 335                         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 336                                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 337                         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 338                                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
 339                                             1);
 340                         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 341                                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 342                         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 343                                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 344                         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 345                                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 346                         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 347                                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 348                         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 349                                             EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 350                         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 351                                             PAGE_TABLE_BLOCK_SIZE,
 352                                             block_size);
 353                         /* Send no-retry XNACK on fault to suppress VM fault storm.
 354                          * On 9.4.2 and 9.4.3, XNACK can be enabled in
 355                          * the SQ per-process.
 356                          * Retry faults need to be enabled for that to work.
 357                          */
 358                         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 359                                             RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
 360                                             !adev->gmc.noretry ||
 361                                             adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) ||
 362                                             adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3));
 363                         WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_CONTEXT1_CNTL,
 364                                             i * hub->ctx_distance, tmp);
 365                         WREG32_SOC15_OFFSET(GC, GET_INST(GC, j),
 366                                             regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
 367                                             i * hub->ctx_addr_distance, 0);
 368                         WREG32_SOC15_OFFSET(GC, GET_INST(GC, j),
 369                                             regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
 370                                             i * hub->ctx_addr_distance, 0);
 371                         WREG32_SOC15_OFFSET(GC, GET_INST(GC, j),
 372                                             regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
 373                                             i * hub->ctx_addr_distance,
 374                                             lower_32_bits(adev->vm_manager.max_pfn - 1));
 375                         WREG32_SOC15_OFFSET(GC, GET_INST(GC, j),
 376                                             regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
 377                                             i * hub->ctx_addr_distance,
 378                                             upper_32_bits(adev->vm_manager.max_pfn - 1));
 379                 }
 380         }
 381 }
 382
 383 static void gfxhub_v1_2_xcc_program_invalidation(struct amdgpu_device *adev,
 384                                                  uint32_t xcc_mask)
 385 {
 386         struct amdgpu_vmhub *hub;
 387         unsigned int i, j;
 388
 389         for_each_inst(j, xcc_mask) {
 390                 hub = &adev->vmhub[AMDGPU_GFXHUB(j)];
 391
 392                 for (i = 0 ; i < 18; ++i) {
 393                         WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
 394                                             i * hub->eng_addr_distance, 0xffffffff);
 395                         WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
 396                                             i * hub->eng_addr_distance, 0x1f);
 397                 }
 398         }
 399 }
 400
 401 static int gfxhub_v1_2_xcc_gart_enable(struct amdgpu_device *adev,
 402                                        uint32_t xcc_mask)
 403 {
 404         uint32_t tmp_mask;
 405         int i;
 406
 407         tmp_mask = xcc_mask;
 408         /*
 409          * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, because they are
 410          * VF copy registers so vbios post doesn't program them, for
 411          * SRIOV driver need to program them
 412          */
 413         if (amdgpu_sriov_vf(adev)) {
 414                 for_each_inst(i, tmp_mask) {
 415                         i = ffs(tmp_mask) - 1;
 416                         WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_FB_LOCATION_BASE,
 417                                      adev->gmc.vram_start >> 24);
 418                         WREG32_SOC15_RLC(GC, GET_INST(GC, i), regMC_VM_FB_LOCATION_TOP,
 419                                      adev->gmc.vram_end >> 24);
 420                 }
 421         }
 422
 423         /* GART Enable. */
 424         gfxhub_v1_2_xcc_init_gart_aperture_regs(adev, xcc_mask);
 425         gfxhub_v1_2_xcc_init_system_aperture_regs(adev, xcc_mask);
 426         gfxhub_v1_2_xcc_init_tlb_regs(adev, xcc_mask);
 427         if (!amdgpu_sriov_vf(adev))
 428                 gfxhub_v1_2_xcc_init_cache_regs(adev, xcc_mask);
 429
 430         gfxhub_v1_2_xcc_enable_system_domain(adev, xcc_mask);
 431         if (!amdgpu_sriov_vf(adev))
 432                 gfxhub_v1_2_xcc_disable_identity_aperture(adev, xcc_mask);
 433         gfxhub_v1_2_xcc_setup_vmid_config(adev, xcc_mask);
 434         gfxhub_v1_2_xcc_program_invalidation(adev, xcc_mask);
 435
 436         return 0;
 437 }
 438
 439 static int gfxhub_v1_2_gart_enable(struct amdgpu_device *adev)
 440 {
 441         uint32_t xcc_mask;
 442
 443         xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0);
 444         return gfxhub_v1_2_xcc_gart_enable(adev, xcc_mask);
 445 }
 446
 447 static void gfxhub_v1_2_xcc_gart_disable(struct amdgpu_device *adev,
 448                                          uint32_t xcc_mask)
 449 {
 450         struct amdgpu_vmhub *hub;
 451         u32 tmp;
 452         u32 i, j;
 453
 454         for_each_inst(j, xcc_mask) {
 455                 hub = &adev->vmhub[AMDGPU_GFXHUB(j)];
 456                 /* Disable all tables */
 457                 for (i = 0; i < 16; i++)
 458                         WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_CONTEXT0_CNTL,
 459                                             i * hub->ctx_distance, 0);
 460
 461                 /* Setup TLB control */
 462                 tmp = RREG32_SOC15(GC, GET_INST(GC, j), regMC_VM_MX_L1_TLB_CNTL);
 463                 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 464                 tmp = REG_SET_FIELD(tmp,
 465                                         MC_VM_MX_L1_TLB_CNTL,
 466                                         ENABLE_ADVANCED_DRIVER_MODEL,
 467                                         0);
 468                 WREG32_SOC15_RLC(GC, GET_INST(GC, j), regMC_VM_MX_L1_TLB_CNTL, tmp);
 469
 470                 /* Setup L2 cache */
 471                 tmp = RREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL);
 472                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 473                 WREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL, tmp);
 474                 WREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL3, 0);
 475         }
 476 }
 477
 478 static void gfxhub_v1_2_gart_disable(struct amdgpu_device *adev)
 479 {
 480         uint32_t xcc_mask;
 481
 482         xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0);
 483         gfxhub_v1_2_xcc_gart_disable(adev, xcc_mask);
 484 }
 485
 486 static void gfxhub_v1_2_xcc_set_fault_enable_default(struct amdgpu_device *adev,
 487                                                      bool value,
 488                                                      uint32_t xcc_mask)
 489 {
 490         u32 tmp;
 491         int i;
 492
 493         for_each_inst(i, xcc_mask) {
 494                 tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL);
 495                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 496                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 497                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 498                                 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 499                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 500                                 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 501                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 502                                 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 503                 tmp = REG_SET_FIELD(tmp,
 504                                 VM_L2_PROTECTION_FAULT_CNTL,
 505                                 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
 506                                 value);
 507                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 508                                 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 509                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 510                                 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 511                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 512                                 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 513                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 514                                 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 515                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 516                                 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 517                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 518                                 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 519                 if (!value) {
 520                         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 521                                         CRASH_ON_NO_RETRY_FAULT, 1);
 522                         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 523                                         CRASH_ON_RETRY_FAULT, 1);
 524                 }
 525                 WREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL, tmp);
 526         }
 527 }
 528
 529 /**
 530  * gfxhub_v1_2_set_fault_enable_default - update GART/VM fault handling
 531  *
 532  * @adev: amdgpu_device pointer
 533  * @value: true redirects VM faults to the default page
 534  */
 535 static void gfxhub_v1_2_set_fault_enable_default(struct amdgpu_device *adev,
 536                                                  bool value)
 537 {
 538         uint32_t xcc_mask;
 539
 540         xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0);
 541         gfxhub_v1_2_xcc_set_fault_enable_default(adev, value, xcc_mask);
 542 }
 543
 544 static void gfxhub_v1_2_xcc_init(struct amdgpu_device *adev, uint32_t xcc_mask)
 545 {
 546         struct amdgpu_vmhub *hub;
 547         int i;
 548
 549         for_each_inst(i, xcc_mask) {
 550                 hub = &adev->vmhub[AMDGPU_GFXHUB(i)];
 551
 552                 hub->ctx0_ptb_addr_lo32 =
 553                         SOC15_REG_OFFSET(GC, GET_INST(GC, i),
 554                                 regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
 555                 hub->ctx0_ptb_addr_hi32 =
 556                         SOC15_REG_OFFSET(GC, GET_INST(GC, i),
 557                                 regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
 558                 hub->vm_inv_eng0_sem =
 559                         SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_INVALIDATE_ENG0_SEM);
 560                 hub->vm_inv_eng0_req =
 561                         SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_INVALIDATE_ENG0_REQ);
 562                 hub->vm_inv_eng0_ack =
 563                         SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_INVALIDATE_ENG0_ACK);
 564                 hub->vm_context0_cntl =
 565                         SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_CONTEXT0_CNTL);
 566                 hub->vm_l2_pro_fault_status =
 567                         SOC15_REG_OFFSET(GC, GET_INST(GC, i),
 568                                 regVM_L2_PROTECTION_FAULT_STATUS);
 569                 hub->vm_l2_pro_fault_cntl =
 570                         SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL);
 571
 572                 hub->ctx_distance = regVM_CONTEXT1_CNTL -
 573                                 regVM_CONTEXT0_CNTL;
 574                 hub->ctx_addr_distance =
 575                                 regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
 576                                 regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
 577                 hub->eng_distance = regVM_INVALIDATE_ENG1_REQ -
 578                                 regVM_INVALIDATE_ENG0_REQ;
 579                 hub->eng_addr_distance =
 580                                 regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
 581                                 regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
 582         }
 583 }
 584
 585 static void gfxhub_v1_2_init(struct amdgpu_device *adev)
 586 {
 587         uint32_t xcc_mask;
 588
 589         xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0);
 590         gfxhub_v1_2_xcc_init(adev, xcc_mask);
 591 }
 592
 593 static int gfxhub_v1_2_get_xgmi_info(struct amdgpu_device *adev)
 594 {
 595         u32 max_num_physical_nodes;
 596         u32 max_physical_node_id;
 597         u32 xgmi_lfb_cntl;
 598         u32 max_region;
 599         u64 seg_size;
 600
 601         xgmi_lfb_cntl = RREG32_SOC15(GC, GET_INST(GC, 0), regMC_VM_XGMI_LFB_CNTL);
 602         seg_size = REG_GET_FIELD(
 603                 RREG32_SOC15(GC, GET_INST(GC, 0), regMC_VM_XGMI_LFB_SIZE),
 604                 MC_VM_XGMI_LFB_SIZE, PF_LFB_SIZE) << 24;
 605         max_region =
 606                 REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION);
 607
 608
 609
 610         max_num_physical_nodes   = 8;
 611         max_physical_node_id     = 7;
 612
 613         /* PF_MAX_REGION=0 means xgmi is disabled */
 614         if (max_region || adev->gmc.xgmi.connected_to_cpu) {
 615                 adev->gmc.xgmi.num_physical_nodes = max_region + 1;
 616
 617                 if (adev->gmc.xgmi.num_physical_nodes > max_num_physical_nodes)
 618                         return -EINVAL;
 619
 620                 adev->gmc.xgmi.physical_node_id =
 621                         REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL,
 622                                         PF_LFB_REGION);
 623
 624                 if (adev->gmc.xgmi.physical_node_id > max_physical_node_id)
 625                         return -EINVAL;
 626
 627                 adev->gmc.xgmi.node_segment_size = seg_size;
 628         }
 629
 630         return 0;
 631 }
 632
 633 const struct amdgpu_gfxhub_funcs gfxhub_v1_2_funcs = {
 634         .get_mc_fb_offset = gfxhub_v1_2_get_mc_fb_offset,
 635         .setup_vm_pt_regs = gfxhub_v1_2_setup_vm_pt_regs,
 636         .gart_enable = gfxhub_v1_2_gart_enable,
 637         .gart_disable = gfxhub_v1_2_gart_disable,
 638         .set_fault_enable_default = gfxhub_v1_2_set_fault_enable_default,
 639         .init = gfxhub_v1_2_init,
 640         .get_xgmi_info = gfxhub_v1_2_get_xgmi_info,
 641 };
 642
 643 static int gfxhub_v1_2_xcp_resume(void *handle, uint32_t inst_mask)
 644 {
 645         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 646         bool value;
 647         int ret;
 648
 649         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
 650                 value = false;
 651         else
 652                 value = true;
 653
 654         gfxhub_v1_2_xcc_set_fault_enable_default(adev, value, inst_mask);
 655
 656         if (!amdgpu_sriov_vf(adev))
 657                 ret = gfxhub_v1_2_xcc_gart_enable(adev, inst_mask);
 658
 659         return ret;
 660 }
 661
 662 static int gfxhub_v1_2_xcp_suspend(void *handle, uint32_t inst_mask)
 663 {
 664         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 665
 666         if (!amdgpu_sriov_vf(adev))
 667                 gfxhub_v1_2_xcc_gart_disable(adev, inst_mask);
 668
 669         return 0;
 670 }
 671
 672 struct amdgpu_xcp_ip_funcs gfxhub_v1_2_xcp_funcs = {
 673         .suspend = &gfxhub_v1_2_xcp_suspend,
 674         .resume = &gfxhub_v1_2_xcp_resume
 675 };