drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "gfxhub_v1_0.h"
  25
  26 #include "vega10/soc15ip.h"
  27 #include "vega10/GC/gc_9_0_offset.h"
  28 #include "vega10/GC/gc_9_0_sh_mask.h"
  29 #include "vega10/GC/gc_9_0_default.h"
  30 #include "vega10/vega10_enum.h"
  31
  32 #include "soc15_common.h"
  33
  34 u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev)
  35 {
  36         return (u64)RREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_OFFSET)) << 24;
  37 }
  38
  39 static void gfxhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
  40 {
  41         uint64_t value;
  42
  43         BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
  44         value = adev->gart.table_addr - adev->mc.vram_start
  45                 + adev->vm_manager.vram_base_offset;
  46         value &= 0x0000FFFFFFFFF000ULL;
  47         value |= 0x1; /*valid bit*/
  48
  49         WREG32(SOC15_REG_OFFSET(GC, 0,
  50                                 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),
  51                lower_32_bits(value));
  52
  53         WREG32(SOC15_REG_OFFSET(GC, 0,
  54                                 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),
  55                upper_32_bits(value));
  56 }
  57
  58 static void gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
  59 {
  60         gfxhub_v1_0_init_gart_pt_regs(adev);
  61
  62         WREG32(SOC15_REG_OFFSET(GC, 0,
  63                                 mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),
  64                 (u32)(adev->mc.gtt_start >> 12));
  65         WREG32(SOC15_REG_OFFSET(GC, 0,
  66                                 mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),
  67                 (u32)(adev->mc.gtt_start >> 44));
  68
  69         WREG32(SOC15_REG_OFFSET(GC, 0,
  70                                 mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),
  71                 (u32)(adev->mc.gtt_end >> 12));
  72         WREG32(SOC15_REG_OFFSET(GC, 0,
  73                                 mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
  74                 (u32)(adev->mc.gtt_end >> 44));
  75 }
  76
  77 static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
  78 {
  79         uint64_t value;
  80         uint32_t tmp;
  81
  82         /* Disable AGP. */
  83         WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_BASE), 0);
  84         WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_TOP), 0);
  85         WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_BOT), 0xFFFFFFFF);
  86
  87         /* Program the system aperture low logical page number. */
  88         WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR),
  89                 adev->mc.vram_start >> 18);
  90         WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR),
  91                 adev->mc.vram_end >> 18);
  92
  93         /* Set default page address. */
  94         value = adev->vram_scratch.gpu_addr - adev->mc.vram_start
  95                 + adev->vm_manager.vram_base_offset;
  96         WREG32(SOC15_REG_OFFSET(GC, 0,
  97                                 mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),
  98                (u32)(value >> 12));
  99         WREG32(SOC15_REG_OFFSET(GC, 0,
 100                                 mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),
 101                (u32)(value >> 44));
 102
 103         /* Program "protection fault". */
 104         WREG32(SOC15_REG_OFFSET(GC, 0,
 105                                 mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),
 106                (u32)(adev->dummy_page.addr >> 12));
 107         WREG32(SOC15_REG_OFFSET(GC, 0,
 108                                 mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),
 109                (u32)((u64)adev->dummy_page.addr >> 44));
 110
 111         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL2));
 112         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
 113                             ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
 114         WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL2), tmp);
 115 }
 116
 117 static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)
 118 {
 119         uint32_t tmp;
 120
 121         /* Setup TLB control */
 122         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL));
 123
 124         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 125         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 126         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 127                             ENABLE_ADVANCED_DRIVER_MODEL, 1);
 128         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 129                             SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 130         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
 131         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 132                             MTYPE, MTYPE_UC);/* XXX for emulation. */
 133         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
 134
 135         WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp);
 136 }
 137
 138 static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
 139 {
 140         uint32_t tmp;
 141
 142         /* Setup L2 cache */
 143         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL));
 144         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 145         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
 146         /* XXX for emulation, Refer to closed source code.*/
 147         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
 148                             0);
 149         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
 150         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 151         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
 152         WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL), tmp);
 153
 154         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL2));
 155         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 156         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 157         WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL2), tmp);
 158
 159         tmp = mmVM_L2_CNTL3_DEFAULT;
 160         WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL3), tmp);
 161
 162         tmp = mmVM_L2_CNTL4_DEFAULT;
 163         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
 164         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
 165         WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL4), tmp);
 166 }
 167
 168 static void gfxhub_v1_0_enable_system_domain(struct amdgpu_device *adev)
 169 {
 170         uint32_t tmp;
 171
 172         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL));
 173         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 174         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 175         WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL), tmp);
 176 }
 177
 178 static void gfxhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev)
 179 {
 180         WREG32(SOC15_REG_OFFSET(GC, 0,
 181                                 mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32),
 182                0XFFFFFFFF);
 183         WREG32(SOC15_REG_OFFSET(GC, 0,
 184                 mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32), 0x0000000F);
 185
 186         WREG32(SOC15_REG_OFFSET(GC, 0,
 187                 mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32), 0);
 188         WREG32(SOC15_REG_OFFSET(GC, 0,
 189                 mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32), 0);
 190
 191         WREG32(SOC15_REG_OFFSET(GC, 0,
 192                 mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32), 0);
 193         WREG32(SOC15_REG_OFFSET(GC, 0,
 194                 mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32), 0);
 195
 196 }
 197
 198 static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
 199 {
 200         int i;
 201         uint32_t tmp;
 202
 203         for (i = 0; i <= 14; i++) {
 204                 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL) + i);
 205                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 206                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
 207                                     adev->vm_manager.num_level);
 208                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 209                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 210                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 211                                 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 212                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 213                                 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 214                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 215                                 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 216                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 217                                 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 218                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 219                                 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 220                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 221                                 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 222                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 223                                 PAGE_TABLE_BLOCK_SIZE,
 224                                 adev->vm_manager.block_size - 9);
 225                 WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL) + i, tmp);
 226                 WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32) + i*2, 0);
 227                 WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32) + i*2, 0);
 228                 WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32) + i*2,
 229                         lower_32_bits(adev->vm_manager.max_pfn - 1));
 230                 WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32) + i*2,
 231                         upper_32_bits(adev->vm_manager.max_pfn - 1));
 232         }
 233 }
 234
 235 static void gfxhub_v1_0_program_invalidation(struct amdgpu_device *adev)
 236 {
 237         unsigned i;
 238
 239         for (i = 0 ; i < 18; ++i) {
 240                 WREG32(SOC15_REG_OFFSET(GC, 0,
 241                                         mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32) +
 242                        2 * i, 0xffffffff);
 243                 WREG32(SOC15_REG_OFFSET(GC, 0,
 244                                         mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32) +
 245                        2 * i, 0x1f);
 246         }
 247 }
 248
 249 int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
 250 {
 251         if (amdgpu_sriov_vf(adev)) {
 252                 /*
 253                  * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
 254                  * VF copy registers so vbios post doesn't program them, for
 255                  * SRIOV driver need to program them
 256                  */
 257                 WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_BASE),
 258                                 adev->mc.vram_start >> 24);
 259                 WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_TOP),
 260                                 adev->mc.vram_end >> 24);
 261         }
 262
 263         /* GART Enable. */
 264         gfxhub_v1_0_init_gart_aperture_regs(adev);
 265         gfxhub_v1_0_init_system_aperture_regs(adev);
 266         gfxhub_v1_0_init_tlb_regs(adev);
 267         gfxhub_v1_0_init_cache_regs(adev);
 268
 269         gfxhub_v1_0_enable_system_domain(adev);
 270         gfxhub_v1_0_disable_identity_aperture(adev);
 271         gfxhub_v1_0_setup_vmid_config(adev);
 272         gfxhub_v1_0_program_invalidation(adev);
 273
 274         return 0;
 275 }
 276
 277 void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev)
 278 {
 279         u32 tmp;
 280         u32 i;
 281
 282         /* Disable all tables */
 283         for (i = 0; i < 16; i++)
 284                 WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL) + i, 0);
 285
 286         /* Setup TLB control */
 287         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL));
 288         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 289         tmp = REG_SET_FIELD(tmp,
 290                                 MC_VM_MX_L1_TLB_CNTL,
 291                                 ENABLE_ADVANCED_DRIVER_MODEL,
 292                                 0);
 293         WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp);
 294
 295         /* Setup L2 cache */
 296         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL));
 297         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 298         WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL), tmp);
 299         WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL3), 0);
 300 }
 301
 302 /**
 303  * gfxhub_v1_0_set_fault_enable_default - update GART/VM fault handling
 304  *
 305  * @adev: amdgpu_device pointer
 306  * @value: true redirects VM faults to the default page
 307  */
 308 void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,
 309                                           bool value)
 310 {
 311         u32 tmp;
 312         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL));
 313         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 314                         RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 315         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 316                         PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 317         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 318                         PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 319         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 320                         PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 321         tmp = REG_SET_FIELD(tmp,
 322                         VM_L2_PROTECTION_FAULT_CNTL,
 323                         TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
 324                         value);
 325         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 326                         NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 327         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 328                         DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 329         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 330                         VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 331         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 332                         READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 333         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 334                         WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 335         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 336                         EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 337         WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL), tmp);
 338 }
 339
 340 void gfxhub_v1_0_init(struct amdgpu_device *adev)
 341 {
 342         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB];
 343
 344         hub->ctx0_ptb_addr_lo32 =
 345                 SOC15_REG_OFFSET(GC, 0,
 346                                  mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
 347         hub->ctx0_ptb_addr_hi32 =
 348                 SOC15_REG_OFFSET(GC, 0,
 349                                  mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
 350         hub->vm_inv_eng0_req =
 351                 SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_REQ);
 352         hub->vm_inv_eng0_ack =
 353                 SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ACK);
 354         hub->vm_context0_cntl =
 355                 SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL);
 356         hub->vm_l2_pro_fault_status =
 357                 SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS);
 358         hub->vm_l2_pro_fault_cntl =
 359                 SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
 360 }