drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

   1 /*
   2  * Copyright 2022 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24
  25 #include "amdgpu.h"
  26 #include "amdgpu_gfx.h"
  27 #include "soc15.h"
  28 #include "soc15d.h"
  29 #include "soc15_common.h"
  30 #include "vega10_enum.h"
  31
  32 #include "v9_structs.h"
  33
  34 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h"
  35
  36 #include "gc/gc_9_4_3_offset.h"
  37 #include "gc/gc_9_4_3_sh_mask.h"
  38
  39 #include "gfx_v9_4_3.h"
  40 #include "amdgpu_xcp.h"
  41
  42 MODULE_FIRMWARE("amdgpu/gc_9_4_3_mec.bin");
  43 MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin");
  44
  45 #define GFX9_MEC_HPD_SIZE 4096
  46 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
  47
  48 #define GOLDEN_GB_ADDR_CONFIG 0x2a114042
  49
  50 struct amdgpu_gfx_ras gfx_v9_4_3_ras;
  51
  52 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev);
  53 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev);
  54 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev);
  55 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev);
  56 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev,
  57                                 struct amdgpu_cu_info *cu_info);
  58
  59 static void gfx_v9_4_3_kiq_set_resources(struct amdgpu_ring *kiq_ring,
  60                                 uint64_t queue_mask)
  61 {
  62         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
  63         amdgpu_ring_write(kiq_ring,
  64                 PACKET3_SET_RESOURCES_VMID_MASK(0) |
  65                 /* vmid_mask:0* queue_type:0 (KIQ) */
  66                 PACKET3_SET_RESOURCES_QUEUE_TYPE(0));
  67         amdgpu_ring_write(kiq_ring,
  68                         lower_32_bits(queue_mask));     /* queue mask lo */
  69         amdgpu_ring_write(kiq_ring,
  70                         upper_32_bits(queue_mask));     /* queue mask hi */
  71         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
  72         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
  73         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
  74         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
  75 }
  76
  77 static void gfx_v9_4_3_kiq_map_queues(struct amdgpu_ring *kiq_ring,
  78                                  struct amdgpu_ring *ring)
  79 {
  80         struct amdgpu_device *adev = kiq_ring->adev;
  81         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
  82         uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
  83         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
  84
  85         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
  86         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
  87         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
  88                          PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
  89                          PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
  90                          PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
  91                          PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
  92                          PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
  93                          /*queue_type: normal compute queue */
  94                          PACKET3_MAP_QUEUES_QUEUE_TYPE(0) |
  95                          /* alloc format: all_on_one_pipe */
  96                          PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) |
  97                          PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
  98                          /* num_queues: must be 1 */
  99                          PACKET3_MAP_QUEUES_NUM_QUEUES(1));
 100         amdgpu_ring_write(kiq_ring,
 101                         PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
 102         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
 103         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
 104         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
 105         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
 106 }
 107
 108 static void gfx_v9_4_3_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
 109                                    struct amdgpu_ring *ring,
 110                                    enum amdgpu_unmap_queues_action action,
 111                                    u64 gpu_addr, u64 seq)
 112 {
 113         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
 114
 115         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
 116         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
 117                           PACKET3_UNMAP_QUEUES_ACTION(action) |
 118                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
 119                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
 120                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
 121         amdgpu_ring_write(kiq_ring,
 122                         PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
 123
 124         if (action == PREEMPT_QUEUES_NO_UNMAP) {
 125                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
 126                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
 127                 amdgpu_ring_write(kiq_ring, seq);
 128         } else {
 129                 amdgpu_ring_write(kiq_ring, 0);
 130                 amdgpu_ring_write(kiq_ring, 0);
 131                 amdgpu_ring_write(kiq_ring, 0);
 132         }
 133 }
 134
 135 static void gfx_v9_4_3_kiq_query_status(struct amdgpu_ring *kiq_ring,
 136                                    struct amdgpu_ring *ring,
 137                                    u64 addr,
 138                                    u64 seq)
 139 {
 140         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
 141
 142         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
 143         amdgpu_ring_write(kiq_ring,
 144                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
 145                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
 146                           PACKET3_QUERY_STATUS_COMMAND(2));
 147         /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
 148         amdgpu_ring_write(kiq_ring,
 149                         PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
 150                         PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
 151         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
 152         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
 153         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
 154         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
 155 }
 156
 157 static void gfx_v9_4_3_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
 158                                 uint16_t pasid, uint32_t flush_type,
 159                                 bool all_hub)
 160 {
 161         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
 162         amdgpu_ring_write(kiq_ring,
 163                         PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
 164                         PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
 165                         PACKET3_INVALIDATE_TLBS_PASID(pasid) |
 166                         PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
 167 }
 168
 169 static const struct kiq_pm4_funcs gfx_v9_4_3_kiq_pm4_funcs = {
 170         .kiq_set_resources = gfx_v9_4_3_kiq_set_resources,
 171         .kiq_map_queues = gfx_v9_4_3_kiq_map_queues,
 172         .kiq_unmap_queues = gfx_v9_4_3_kiq_unmap_queues,
 173         .kiq_query_status = gfx_v9_4_3_kiq_query_status,
 174         .kiq_invalidate_tlbs = gfx_v9_4_3_kiq_invalidate_tlbs,
 175         .set_resources_size = 8,
 176         .map_queues_size = 7,
 177         .unmap_queues_size = 6,
 178         .query_status_size = 7,
 179         .invalidate_tlbs_size = 2,
 180 };
 181
 182 static void gfx_v9_4_3_set_kiq_pm4_funcs(struct amdgpu_device *adev)
 183 {
 184         int i, num_xcc;
 185
 186         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
 187         for (i = 0; i < num_xcc; i++)
 188                 adev->gfx.kiq[i].pmf = &gfx_v9_4_3_kiq_pm4_funcs;
 189 }
 190
 191 static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev)
 192 {
 193         int i, num_xcc, dev_inst;
 194
 195         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
 196         for (i = 0; i < num_xcc; i++) {
 197                 dev_inst = GET_INST(GC, i);
 198                 if (dev_inst >= 2)
 199                         WREG32_SOC15(GC, dev_inst, regGRBM_MCM_ADDR, 0x4);
 200
 201                 /* Golden settings applied by driver for ASIC with rev_id 0 */
 202                 if (adev->rev_id == 0) {
 203                         WREG32_SOC15(GC, dev_inst, regGB_ADDR_CONFIG,
 204                                      GOLDEN_GB_ADDR_CONFIG);
 205
 206                         WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL1,
 207                                               REDUCE_FIFO_DEPTH_BY_2, 2);
 208                 }
 209         }
 210 }
 211
 212 static void gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
 213                                        bool wc, uint32_t reg, uint32_t val)
 214 {
 215         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
 216         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
 217                                 WRITE_DATA_DST_SEL(0) |
 218                                 (wc ? WR_CONFIRM : 0));
 219         amdgpu_ring_write(ring, reg);
 220         amdgpu_ring_write(ring, 0);
 221         amdgpu_ring_write(ring, val);
 222 }
 223
 224 static void gfx_v9_4_3_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
 225                                   int mem_space, int opt, uint32_t addr0,
 226                                   uint32_t addr1, uint32_t ref, uint32_t mask,
 227                                   uint32_t inv)
 228 {
 229         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
 230         amdgpu_ring_write(ring,
 231                                  /* memory (1) or register (0) */
 232                                  (WAIT_REG_MEM_MEM_SPACE(mem_space) |
 233                                  WAIT_REG_MEM_OPERATION(opt) | /* wait */
 234                                  WAIT_REG_MEM_FUNCTION(3) |  /* equal */
 235                                  WAIT_REG_MEM_ENGINE(eng_sel)));
 236
 237         if (mem_space)
 238                 BUG_ON(addr0 & 0x3); /* Dword align */
 239         amdgpu_ring_write(ring, addr0);
 240         amdgpu_ring_write(ring, addr1);
 241         amdgpu_ring_write(ring, ref);
 242         amdgpu_ring_write(ring, mask);
 243         amdgpu_ring_write(ring, inv); /* poll interval */
 244 }
 245
 246 static int gfx_v9_4_3_ring_test_ring(struct amdgpu_ring *ring)
 247 {
 248         uint32_t scratch_reg0_offset, xcc_offset;
 249         struct amdgpu_device *adev = ring->adev;
 250         uint32_t tmp = 0;
 251         unsigned i;
 252         int r;
 253
 254         /* Use register offset which is local to XCC in the packet */
 255         xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);
 256         scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0);
 257         WREG32(scratch_reg0_offset, 0xCAFEDEAD);
 258
 259         r = amdgpu_ring_alloc(ring, 3);
 260         if (r)
 261                 return r;
 262
 263         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
 264         amdgpu_ring_write(ring, xcc_offset - PACKET3_SET_UCONFIG_REG_START);
 265         amdgpu_ring_write(ring, 0xDEADBEEF);
 266         amdgpu_ring_commit(ring);
 267
 268         for (i = 0; i < adev->usec_timeout; i++) {
 269                 tmp = RREG32(scratch_reg0_offset);
 270                 if (tmp == 0xDEADBEEF)
 271                         break;
 272                 udelay(1);
 273         }
 274
 275         if (i >= adev->usec_timeout)
 276                 r = -ETIMEDOUT;
 277         return r;
 278 }
 279
 280 static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 281 {
 282         struct amdgpu_device *adev = ring->adev;
 283         struct amdgpu_ib ib;
 284         struct dma_fence *f = NULL;
 285
 286         unsigned index;
 287         uint64_t gpu_addr;
 288         uint32_t tmp;
 289         long r;
 290
 291         r = amdgpu_device_wb_get(adev, &index);
 292         if (r)
 293                 return r;
 294
 295         gpu_addr = adev->wb.gpu_addr + (index * 4);
 296         adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
 297         memset(&ib, 0, sizeof(ib));
 298         r = amdgpu_ib_get(adev, NULL, 16,
 299                           AMDGPU_IB_POOL_DIRECT, &ib);
 300         if (r)
 301                 goto err1;
 302
 303         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
 304         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
 305         ib.ptr[2] = lower_32_bits(gpu_addr);
 306         ib.ptr[3] = upper_32_bits(gpu_addr);
 307         ib.ptr[4] = 0xDEADBEEF;
 308         ib.length_dw = 5;
 309
 310         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 311         if (r)
 312                 goto err2;
 313
 314         r = dma_fence_wait_timeout(f, false, timeout);
 315         if (r == 0) {
 316                 r = -ETIMEDOUT;
 317                 goto err2;
 318         } else if (r < 0) {
 319                 goto err2;
 320         }
 321
 322         tmp = adev->wb.wb[index];
 323         if (tmp == 0xDEADBEEF)
 324                 r = 0;
 325         else
 326                 r = -EINVAL;
 327
 328 err2:
 329         amdgpu_ib_free(adev, &ib, NULL);
 330         dma_fence_put(f);
 331 err1:
 332         amdgpu_device_wb_free(adev, index);
 333         return r;
 334 }
 335
 336
 337 /* This value might differs per partition */
 338 static uint64_t gfx_v9_4_3_get_gpu_clock_counter(struct amdgpu_device *adev)
 339 {
 340         uint64_t clock;
 341
 342         amdgpu_gfx_off_ctrl(adev, false);
 343         mutex_lock(&adev->gfx.gpu_clock_mutex);
 344         WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
 345         clock = (uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_LSB) |
 346                 ((uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
 347         mutex_unlock(&adev->gfx.gpu_clock_mutex);
 348         amdgpu_gfx_off_ctrl(adev, true);
 349
 350         return clock;
 351 }
 352
 353 static void gfx_v9_4_3_free_microcode(struct amdgpu_device *adev)
 354 {
 355         amdgpu_ucode_release(&adev->gfx.pfp_fw);
 356         amdgpu_ucode_release(&adev->gfx.me_fw);
 357         amdgpu_ucode_release(&adev->gfx.ce_fw);
 358         amdgpu_ucode_release(&adev->gfx.rlc_fw);
 359         amdgpu_ucode_release(&adev->gfx.mec_fw);
 360         amdgpu_ucode_release(&adev->gfx.mec2_fw);
 361
 362         kfree(adev->gfx.rlc.register_list_format);
 363 }
 364
 365 static int gfx_v9_4_3_init_rlc_microcode(struct amdgpu_device *adev,
 366                                           const char *chip_name)
 367 {
 368         char fw_name[30];
 369         int err;
 370         const struct rlc_firmware_header_v2_0 *rlc_hdr;
 371         uint16_t version_major;
 372         uint16_t version_minor;
 373
 374         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
 375
 376         err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name);
 377         if (err)
 378                 goto out;
 379         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
 380
 381         version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
 382         version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
 383         err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);
 384 out:
 385         if (err)
 386                 amdgpu_ucode_release(&adev->gfx.rlc_fw);
 387
 388         return err;
 389 }
 390
 391 static bool gfx_v9_4_3_should_disable_gfxoff(struct pci_dev *pdev)
 392 {
 393         return true;
 394 }
 395
 396 static void gfx_v9_4_3_check_if_need_gfxoff(struct amdgpu_device *adev)
 397 {
 398         if (gfx_v9_4_3_should_disable_gfxoff(adev->pdev))
 399                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 400 }
 401
 402 static int gfx_v9_4_3_init_cp_compute_microcode(struct amdgpu_device *adev,
 403                                           const char *chip_name)
 404 {
 405         char fw_name[30];
 406         int err;
 407
 408         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
 409
 410         err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name);
 411         if (err)
 412                 goto out;
 413         amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1);
 414         amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT);
 415
 416         adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version;
 417         adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version;
 418
 419         gfx_v9_4_3_check_if_need_gfxoff(adev);
 420
 421 out:
 422         if (err)
 423                 amdgpu_ucode_release(&adev->gfx.mec_fw);
 424         return err;
 425 }
 426
 427 static int gfx_v9_4_3_init_microcode(struct amdgpu_device *adev)
 428 {
 429         const char *chip_name;
 430         int r;
 431
 432         chip_name = "gc_9_4_3";
 433
 434         r = gfx_v9_4_3_init_rlc_microcode(adev, chip_name);
 435         if (r)
 436                 return r;
 437
 438         r = gfx_v9_4_3_init_cp_compute_microcode(adev, chip_name);
 439         if (r)
 440                 return r;
 441
 442         return r;
 443 }
 444
 445 static void gfx_v9_4_3_mec_fini(struct amdgpu_device *adev)
 446 {
 447         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
 448         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
 449 }
 450
 451 static int gfx_v9_4_3_mec_init(struct amdgpu_device *adev)
 452 {
 453         int r, i, num_xcc;
 454         u32 *hpd;
 455         const __le32 *fw_data;
 456         unsigned fw_size;
 457         u32 *fw;
 458         size_t mec_hpd_size;
 459
 460         const struct gfx_firmware_header_v1_0 *mec_hdr;
 461
 462         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
 463         for (i = 0; i < num_xcc; i++)
 464                 bitmap_zero(adev->gfx.mec_bitmap[i].queue_bitmap,
 465                         AMDGPU_MAX_COMPUTE_QUEUES);
 466
 467         /* take ownership of the relevant compute queues */
 468         amdgpu_gfx_compute_queue_acquire(adev);
 469         mec_hpd_size =
 470                 adev->gfx.num_compute_rings * num_xcc * GFX9_MEC_HPD_SIZE;
 471         if (mec_hpd_size) {
 472                 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
 473                                               AMDGPU_GEM_DOMAIN_VRAM |
 474                                               AMDGPU_GEM_DOMAIN_GTT,
 475                                               &adev->gfx.mec.hpd_eop_obj,
 476                                               &adev->gfx.mec.hpd_eop_gpu_addr,
 477                                               (void **)&hpd);
 478                 if (r) {
 479                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
 480                         gfx_v9_4_3_mec_fini(adev);
 481                         return r;
 482                 }
 483
 484                 if (amdgpu_emu_mode == 1) {
 485                         for (i = 0; i < mec_hpd_size / 4; i++) {
 486                                 memset((void *)(hpd + i), 0, 4);
 487                                 if (i % 50 == 0)
 488                                         msleep(1);
 489                         }
 490                 } else {
 491                         memset(hpd, 0, mec_hpd_size);
 492                 }
 493
 494                 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
 495                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
 496         }
 497
 498         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
 499
 500         fw_data = (const __le32 *)
 501                 (adev->gfx.mec_fw->data +
 502                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
 503         fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
 504
 505         r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
 506                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
 507                                       &adev->gfx.mec.mec_fw_obj,
 508                                       &adev->gfx.mec.mec_fw_gpu_addr,
 509                                       (void **)&fw);
 510         if (r) {
 511                 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r);
 512                 gfx_v9_4_3_mec_fini(adev);
 513                 return r;
 514         }
 515
 516         memcpy(fw, fw_data, fw_size);
 517
 518         amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
 519         amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
 520
 521         return 0;
 522 }
 523
 524 static void gfx_v9_4_3_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num,
 525                                         u32 sh_num, u32 instance, int xcc_id)
 526 {
 527         u32 data;
 528
 529         if (instance == 0xffffffff)
 530                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
 531                                      INSTANCE_BROADCAST_WRITES, 1);
 532         else
 533                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
 534                                      INSTANCE_INDEX, instance);
 535
 536         if (se_num == 0xffffffff)
 537                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
 538                                      SE_BROADCAST_WRITES, 1);
 539         else
 540                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
 541
 542         if (sh_num == 0xffffffff)
 543                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
 544                                      SH_BROADCAST_WRITES, 1);
 545         else
 546                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
 547
 548         WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data);
 549 }
 550
 551 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t address)
 552 {
 553         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX,
 554                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
 555                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
 556                 (address << SQ_IND_INDEX__INDEX__SHIFT) |
 557                 (SQ_IND_INDEX__FORCE_READ_MASK));
 558         return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA);
 559 }
 560
 561 static void wave_read_regs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
 562                            uint32_t wave, uint32_t thread,
 563                            uint32_t regno, uint32_t num, uint32_t *out)
 564 {
 565         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX,
 566                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
 567                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
 568                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
 569                 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
 570                 (SQ_IND_INDEX__FORCE_READ_MASK) |
 571                 (SQ_IND_INDEX__AUTO_INCR_MASK));
 572         while (num--)
 573                 *(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA);
 574 }
 575
 576 static void gfx_v9_4_3_read_wave_data(struct amdgpu_device *adev,
 577                                       uint32_t xcc_id, uint32_t simd, uint32_t wave,
 578                                       uint32_t *dst, int *no_fields)
 579 {
 580         /* type 1 wave data */
 581         dst[(*no_fields)++] = 1;
 582         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS);
 583         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO);
 584         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI);
 585         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO);
 586         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI);
 587         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_HW_ID);
 588         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0);
 589         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1);
 590         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_GPR_ALLOC);
 591         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_LDS_ALLOC);
 592         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_TRAPSTS);
 593         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS);
 594         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_DBG0);
 595         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_M0);
 596         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_MODE);
 597 }
 598
 599 static void gfx_v9_4_3_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
 600                                        uint32_t wave, uint32_t start,
 601                                        uint32_t size, uint32_t *dst)
 602 {
 603         wave_read_regs(adev, xcc_id, simd, wave, 0,
 604                        start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
 605 }
 606
 607 static void gfx_v9_4_3_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
 608                                        uint32_t wave, uint32_t thread,
 609                                        uint32_t start, uint32_t size,
 610                                        uint32_t *dst)
 611 {
 612         wave_read_regs(adev, xcc_id, simd, wave, thread,
 613                        start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
 614 }
 615
 616 static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev,
 617                                         u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)
 618 {
 619         soc15_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id));
 620 }
 621
 622
 623 static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev,
 624                                                 int num_xccs_per_xcp)
 625 {
 626         int ret, i, num_xcc;
 627         u32 tmp = 0;
 628
 629         if (adev->psp.funcs) {
 630                 ret = psp_spatial_partition(&adev->psp,
 631                                             NUM_XCC(adev->gfx.xcc_mask) /
 632                                                     num_xccs_per_xcp);
 633                 if (ret)
 634                         return ret;
 635         } else {
 636                 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
 637
 638                 for (i = 0; i < num_xcc; i++) {
 639                         tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP,
 640                                             num_xccs_per_xcp);
 641                         tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID,
 642                                             i % num_xccs_per_xcp);
 643                         WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL,
 644                                      tmp);
 645                 }
 646                 ret = 0;
 647         }
 648
 649         adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp;
 650
 651         return ret;
 652 }
 653
 654 static int gfx_v9_4_3_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node)
 655 {
 656         int xcc;
 657
 658         xcc = hweight8(adev->gfx.xcc_mask & GENMASK(ih_node / 2, 0));
 659         if (!xcc) {
 660                 dev_err(adev->dev, "Couldn't find xcc mapping from IH node");
 661                 return -EINVAL;
 662         }
 663
 664         return xcc - 1;
 665 }
 666
 667 static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = {
 668         .get_gpu_clock_counter = &gfx_v9_4_3_get_gpu_clock_counter,
 669         .select_se_sh = &gfx_v9_4_3_xcc_select_se_sh,
 670         .read_wave_data = &gfx_v9_4_3_read_wave_data,
 671         .read_wave_sgprs = &gfx_v9_4_3_read_wave_sgprs,
 672         .read_wave_vgprs = &gfx_v9_4_3_read_wave_vgprs,
 673         .select_me_pipe_q = &gfx_v9_4_3_select_me_pipe_q,
 674         .switch_partition_mode = &gfx_v9_4_3_switch_compute_partition,
 675         .ih_node_to_logical_xcc = &gfx_v9_4_3_ih_to_xcc_inst,
 676 };
 677
 678 static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev)
 679 {
 680         u32 gb_addr_config;
 681
 682         adev->gfx.funcs = &gfx_v9_4_3_gfx_funcs;
 683         adev->gfx.ras = &gfx_v9_4_3_ras;
 684
 685         switch (adev->ip_versions[GC_HWIP][0]) {
 686         case IP_VERSION(9, 4, 3):
 687                 adev->gfx.config.max_hw_contexts = 8;
 688                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
 689                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
 690                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
 691                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
 692                 gb_addr_config = RREG32_SOC15(GC, GET_INST(GC, 0), regGB_ADDR_CONFIG);
 693                 break;
 694         default:
 695                 BUG();
 696                 break;
 697         }
 698
 699         adev->gfx.config.gb_addr_config = gb_addr_config;
 700
 701         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
 702                         REG_GET_FIELD(
 703                                         adev->gfx.config.gb_addr_config,
 704                                         GB_ADDR_CONFIG,
 705                                         NUM_PIPES);
 706
 707         adev->gfx.config.max_tile_pipes =
 708                 adev->gfx.config.gb_addr_config_fields.num_pipes;
 709
 710         adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
 711                         REG_GET_FIELD(
 712                                         adev->gfx.config.gb_addr_config,
 713                                         GB_ADDR_CONFIG,
 714                                         NUM_BANKS);
 715         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
 716                         REG_GET_FIELD(
 717                                         adev->gfx.config.gb_addr_config,
 718                                         GB_ADDR_CONFIG,
 719                                         MAX_COMPRESSED_FRAGS);
 720         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
 721                         REG_GET_FIELD(
 722                                         adev->gfx.config.gb_addr_config,
 723                                         GB_ADDR_CONFIG,
 724                                         NUM_RB_PER_SE);
 725         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
 726                         REG_GET_FIELD(
 727                                         adev->gfx.config.gb_addr_config,
 728                                         GB_ADDR_CONFIG,
 729                                         NUM_SHADER_ENGINES);
 730         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
 731                         REG_GET_FIELD(
 732                                         adev->gfx.config.gb_addr_config,
 733                                         GB_ADDR_CONFIG,
 734                                         PIPE_INTERLEAVE_SIZE));
 735
 736         return 0;
 737 }
 738
 739 static int gfx_v9_4_3_compute_ring_init(struct amdgpu_device *adev, int ring_id,
 740                                         int xcc_id, int mec, int pipe, int queue)
 741 {
 742         unsigned irq_type;
 743         struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
 744         unsigned int hw_prio;
 745         uint32_t xcc_doorbell_start;
 746
 747         ring = &adev->gfx.compute_ring[xcc_id * adev->gfx.num_compute_rings +
 748                                        ring_id];
 749
 750         /* mec0 is me1 */
 751         ring->xcc_id = xcc_id;
 752         ring->me = mec + 1;
 753         ring->pipe = pipe;
 754         ring->queue = queue;
 755
 756         ring->ring_obj = NULL;
 757         ring->use_doorbell = true;
 758         xcc_doorbell_start = adev->doorbell_index.mec_ring0 +
 759                              xcc_id * adev->doorbell_index.xcc_doorbell_range;
 760         ring->doorbell_index = (xcc_doorbell_start + ring_id) << 1;
 761         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr +
 762                              (ring_id + xcc_id * adev->gfx.num_compute_rings) *
 763                                      GFX9_MEC_HPD_SIZE;
 764         ring->vm_hub = AMDGPU_GFXHUB(xcc_id);
 765         sprintf(ring->name, "comp_%d.%d.%d.%d",
 766                         ring->xcc_id, ring->me, ring->pipe, ring->queue);
 767
 768         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
 769                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
 770                 + ring->pipe;
 771         hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
 772                         AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
 773         /* type-2 packets are deprecated on MEC, use type-3 instead */
 774         return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
 775                                 hw_prio, NULL);
 776 }
 777
 778 static int gfx_v9_4_3_sw_init(void *handle)
 779 {
 780         int i, j, k, r, ring_id, xcc_id, num_xcc;
 781         struct amdgpu_kiq *kiq;
 782         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 783
 784         adev->gfx.mec.num_mec = 2;
 785         adev->gfx.mec.num_pipe_per_mec = 4;
 786         adev->gfx.mec.num_queue_per_pipe = 8;
 787
 788         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
 789
 790         /* EOP Event */
 791         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq);
 792         if (r)
 793                 return r;
 794
 795         /* Privileged reg */
 796         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT,
 797                               &adev->gfx.priv_reg_irq);
 798         if (r)
 799                 return r;
 800
 801         /* Privileged inst */
 802         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT,
 803                               &adev->gfx.priv_inst_irq);
 804         if (r)
 805                 return r;
 806
 807         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
 808
 809         r = adev->gfx.rlc.funcs->init(adev);
 810         if (r) {
 811                 DRM_ERROR("Failed to init rlc BOs!\n");
 812                 return r;
 813         }
 814
 815         r = gfx_v9_4_3_mec_init(adev);
 816         if (r) {
 817                 DRM_ERROR("Failed to init MEC BOs!\n");
 818                 return r;
 819         }
 820
 821         /* set up the compute queues - allocate horizontally across pipes */
 822         for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) {
 823                 ring_id = 0;
 824                 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
 825                         for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
 826                                 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec;
 827                                      k++) {
 828                                         if (!amdgpu_gfx_is_mec_queue_enabled(
 829                                                         adev, xcc_id, i, k, j))
 830                                                 continue;
 831
 832                                         r = gfx_v9_4_3_compute_ring_init(adev,
 833                                                                        ring_id,
 834                                                                        xcc_id,
 835                                                                        i, k, j);
 836                                         if (r)
 837                                                 return r;
 838
 839                                         ring_id++;
 840                                 }
 841                         }
 842                 }
 843
 844                 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, xcc_id);
 845                 if (r) {
 846                         DRM_ERROR("Failed to init KIQ BOs!\n");
 847                         return r;
 848                 }
 849
 850                 kiq = &adev->gfx.kiq[xcc_id];
 851                 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, xcc_id);
 852                 if (r)
 853                         return r;
 854
 855                 /* create MQD for all compute queues as wel as KIQ for SRIOV case */
 856                 r = amdgpu_gfx_mqd_sw_init(adev,
 857                                 sizeof(struct v9_mqd_allocation), xcc_id);
 858                 if (r)
 859                         return r;
 860         }
 861
 862         r = gfx_v9_4_3_gpu_early_init(adev);
 863         if (r)
 864                 return r;
 865
 866         r = amdgpu_gfx_sysfs_init(adev);
 867         if (r)
 868                 return r;
 869
 870         return amdgpu_gfx_ras_sw_init(adev);
 871 }
 872
 873 static int gfx_v9_4_3_sw_fini(void *handle)
 874 {
 875         int i, num_xcc;
 876         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 877
 878         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
 879         for (i = 0; i < adev->gfx.num_compute_rings * num_xcc; i++)
 880                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
 881
 882         for (i = 0; i < num_xcc; i++) {
 883                 amdgpu_gfx_mqd_sw_fini(adev, i);
 884                 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[i].ring);
 885                 amdgpu_gfx_kiq_fini(adev, i);
 886         }
 887
 888         gfx_v9_4_3_mec_fini(adev);
 889         amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
 890         gfx_v9_4_3_free_microcode(adev);
 891         amdgpu_gfx_sysfs_fini(adev);
 892
 893         return 0;
 894 }
 895
 896 #define DEFAULT_SH_MEM_BASES    (0x6000)
 897 static void gfx_v9_4_3_xcc_init_compute_vmid(struct amdgpu_device *adev,
 898                                              int xcc_id)
 899 {
 900         int i;
 901         uint32_t sh_mem_config;
 902         uint32_t sh_mem_bases;
 903
 904         /*
 905          * Configure apertures:
 906          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
 907          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
 908          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
 909          */
 910         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
 911
 912         sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
 913                         SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
 914                         SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
 915
 916         mutex_lock(&adev->srbm_mutex);
 917         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
 918                 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id));
 919                 /* CP and shaders */
 920                 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, sh_mem_config);
 921                 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases);
 922         }
 923         soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
 924         mutex_unlock(&adev->srbm_mutex);
 925
 926         /* Initialize all compute VMIDs to have no GDS, GWS, or OA
 927            acccess. These should be enabled by FW for target VMIDs. */
 928         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
 929                 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * i, 0);
 930                 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * i, 0);
 931                 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, i, 0);
 932                 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, i, 0);
 933         }
 934 }
 935
 936 static void gfx_v9_4_3_xcc_init_gds_vmid(struct amdgpu_device *adev, int xcc_id)
 937 {
 938         int vmid;
 939
 940         /*
 941          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
 942          * access. Compute VMIDs should be enabled by FW for target VMIDs,
 943          * the driver can enable them for graphics. VMID0 should maintain
 944          * access so that HWS firmware can save/restore entries.
 945          */
 946         for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
 947                 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * vmid, 0);
 948                 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * vmid, 0);
 949                 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, vmid, 0);
 950                 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, vmid, 0);
 951         }
 952 }
 953
 954 static void gfx_v9_4_3_xcc_constants_init(struct amdgpu_device *adev,
 955                                           int xcc_id)
 956 {
 957         u32 tmp;
 958         int i;
 959
 960         /* XXX SH_MEM regs */
 961         /* where to put LDS, scratch, GPUVM in FSA64 space */
 962         mutex_lock(&adev->srbm_mutex);
 963         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) {
 964                 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id));
 965                 /* CP and shaders */
 966                 if (i == 0) {
 967                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
 968                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
 969                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,
 970                                             !!adev->gmc.noretry);
 971                         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),
 972                                          regSH_MEM_CONFIG, tmp);
 973                         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),
 974                                          regSH_MEM_BASES, 0);
 975                 } else {
 976                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
 977                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
 978                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,
 979                                             !!adev->gmc.noretry);
 980                         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),
 981                                          regSH_MEM_CONFIG, tmp);
 982                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
 983                                             (adev->gmc.private_aperture_start >>
 984                                              48));
 985                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
 986                                             (adev->gmc.shared_aperture_start >>
 987                                              48));
 988                         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),
 989                                          regSH_MEM_BASES, tmp);
 990                 }
 991         }
 992         soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0));
 993
 994         mutex_unlock(&adev->srbm_mutex);
 995
 996         gfx_v9_4_3_xcc_init_compute_vmid(adev, xcc_id);
 997         gfx_v9_4_3_xcc_init_gds_vmid(adev, xcc_id);
 998 }
 999
1000 static void gfx_v9_4_3_constants_init(struct amdgpu_device *adev)
1001 {
1002         int i, num_xcc;
1003
1004         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1005
1006         gfx_v9_4_3_get_cu_info(adev, &adev->gfx.cu_info);
1007         adev->gfx.config.db_debug2 =
1008                 RREG32_SOC15(GC, GET_INST(GC, 0), regDB_DEBUG2);
1009
1010         for (i = 0; i < num_xcc; i++)
1011                 gfx_v9_4_3_xcc_constants_init(adev, i);
1012 }
1013
1014 static void
1015 gfx_v9_4_3_xcc_enable_save_restore_machine(struct amdgpu_device *adev,
1016                                            int xcc_id)
1017 {
1018         WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_SRM_CNTL, SRM_ENABLE, 1);
1019 }
1020
1021 static void gfx_v9_4_3_xcc_init_pg(struct amdgpu_device *adev, int xcc_id)
1022 {
1023         /*
1024          * Rlc save restore list is workable since v2_1.
1025          * And it's needed by gfxoff feature.
1026          */
1027         if (adev->gfx.rlc.is_rlc_v2_1)
1028                 gfx_v9_4_3_xcc_enable_save_restore_machine(adev, xcc_id);
1029 }
1030
1031 static void gfx_v9_4_3_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id)
1032 {
1033         uint32_t data;
1034
1035         data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG);
1036         data |= CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE_MASK;
1037         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data);
1038 }
1039
1040 static void gfx_v9_4_3_xcc_program_xcc_id(struct amdgpu_device *adev,
1041                                           int xcc_id)
1042 {
1043         uint32_t tmp = 0;
1044         int num_xcc;
1045
1046         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1047         switch (num_xcc) {
1048         /* directly config VIRTUAL_XCC_ID to 0 for 1-XCC */
1049         case 1:
1050                 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HYP_XCP_CTL, 0x8);
1051                 break;
1052         case 2:
1053         case 4:
1054         case 6:
1055         case 8:
1056                 tmp = (xcc_id % adev->gfx.num_xcc_per_xcp) << REG_FIELD_SHIFT(CP_HYP_XCP_CTL, VIRTUAL_XCC_ID);
1057                 tmp = tmp | (adev->gfx.num_xcc_per_xcp << REG_FIELD_SHIFT(CP_HYP_XCP_CTL, NUM_XCC_IN_XCP));
1058                 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HYP_XCP_CTL, tmp);
1059
1060                 break;
1061         default:
1062                 break;
1063         }
1064 }
1065
1066 static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev)
1067 {
1068         uint32_t rlc_setting;
1069
1070         /* if RLC is not enabled, do nothing */
1071         rlc_setting = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL);
1072         if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
1073                 return false;
1074
1075         return true;
1076 }
1077
1078 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id)
1079 {
1080         uint32_t data;
1081         unsigned i;
1082
1083         data = RLC_SAFE_MODE__CMD_MASK;
1084         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
1085         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data);
1086
1087         /* wait for RLC_SAFE_MODE */
1088         for (i = 0; i < adev->usec_timeout; i++) {
1089                 if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
1090                         break;
1091                 udelay(1);
1092         }
1093 }
1094
1095 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev,
1096                                            int xcc_id)
1097 {
1098         uint32_t data;
1099
1100         data = RLC_SAFE_MODE__CMD_MASK;
1101         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data);
1102 }
1103
1104 static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev)
1105 {
1106         /* init spm vmid with 0xf */
1107         if (adev->gfx.rlc.funcs->update_spm_vmid)
1108                 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
1109
1110         return 0;
1111 }
1112
1113 static void gfx_v9_4_3_xcc_wait_for_rlc_serdes(struct amdgpu_device *adev,
1114                                                int xcc_id)
1115 {
1116         u32 i, j, k;
1117         u32 mask;
1118
1119         mutex_lock(&adev->grbm_idx_mutex);
1120         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1121                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1122                         gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff,
1123                                                     xcc_id);
1124                         for (k = 0; k < adev->usec_timeout; k++) {
1125                                 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_CU_MASTER_BUSY) == 0)
1126                                         break;
1127                                 udelay(1);
1128                         }
1129                         if (k == adev->usec_timeout) {
1130                                 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff,
1131                                                             0xffffffff,
1132                                                             0xffffffff, xcc_id);
1133                                 mutex_unlock(&adev->grbm_idx_mutex);
1134                                 DRM_INFO("Timeout wait for RLC serdes %u,%u\n",
1135                                          i, j);
1136                                 return;
1137                         }
1138                 }
1139         }
1140         gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
1141                                     xcc_id);
1142         mutex_unlock(&adev->grbm_idx_mutex);
1143
1144         mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
1145                 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
1146                 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
1147                 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
1148         for (k = 0; k < adev->usec_timeout; k++) {
1149                 if ((RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
1150                         break;
1151                 udelay(1);
1152         }
1153 }
1154
1155 static void gfx_v9_4_3_xcc_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1156                                                      bool enable, int xcc_id)
1157 {
1158         u32 tmp;
1159
1160         /* These interrupts should be enabled to drive DS clock */
1161
1162         tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0);
1163
1164         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
1165         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
1166         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
1167
1168         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp);
1169 }
1170
1171 static void gfx_v9_4_3_xcc_rlc_stop(struct amdgpu_device *adev, int xcc_id)
1172 {
1173         WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL,
1174                               RLC_ENABLE_F32, 0);
1175         gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id);
1176         gfx_v9_4_3_xcc_wait_for_rlc_serdes(adev, xcc_id);
1177 }
1178
1179 static void gfx_v9_4_3_rlc_stop(struct amdgpu_device *adev)
1180 {
1181         int i, num_xcc;
1182
1183         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1184         for (i = 0; i < num_xcc; i++)
1185                 gfx_v9_4_3_xcc_rlc_stop(adev, i);
1186 }
1187
1188 static void gfx_v9_4_3_xcc_rlc_reset(struct amdgpu_device *adev, int xcc_id)
1189 {
1190         WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET,
1191                               SOFT_RESET_RLC, 1);
1192         udelay(50);
1193         WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET,
1194                               SOFT_RESET_RLC, 0);
1195         udelay(50);
1196 }
1197
1198 static void gfx_v9_4_3_rlc_reset(struct amdgpu_device *adev)
1199 {
1200         int i, num_xcc;
1201
1202         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1203         for (i = 0; i < num_xcc; i++)
1204                 gfx_v9_4_3_xcc_rlc_reset(adev, i);
1205 }
1206
1207 static void gfx_v9_4_3_xcc_rlc_start(struct amdgpu_device *adev, int xcc_id)
1208 {
1209         WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL,
1210                               RLC_ENABLE_F32, 1);
1211         udelay(50);
1212
1213         /* carrizo do enable cp interrupt after cp inited */
1214         if (!(adev->flags & AMD_IS_APU)) {
1215                 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id);
1216                 udelay(50);
1217         }
1218 }
1219
1220 static void gfx_v9_4_3_rlc_start(struct amdgpu_device *adev)
1221 {
1222 #ifdef AMDGPU_RLC_DEBUG_RETRY
1223         u32 rlc_ucode_ver;
1224 #endif
1225         int i, num_xcc;
1226
1227         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1228         for (i = 0; i < num_xcc; i++) {
1229                 gfx_v9_4_3_xcc_rlc_start(adev, i);
1230 #ifdef AMDGPU_RLC_DEBUG_RETRY
1231                 /* RLC_GPM_GENERAL_6 : RLC Ucode version */
1232                 rlc_ucode_ver = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_6);
1233                 if (rlc_ucode_ver == 0x108) {
1234                         dev_info(adev->dev,
1235                                  "Using rlc debug ucode. regRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n",
1236                                  rlc_ucode_ver, adev->gfx.rlc_fw_version);
1237                         /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles,
1238                          * default is 0x9C4 to create a 100us interval */
1239                         WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_TIMER_INT_3, 0x9C4);
1240                         /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
1241                          * to disable the page fault retry interrupts, default is
1242                          * 0x100 (256) */
1243                         WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_12, 0x100);
1244                 }
1245 #endif
1246         }
1247 }
1248
1249 static int gfx_v9_4_3_xcc_rlc_load_microcode(struct amdgpu_device *adev,
1250                                              int xcc_id)
1251 {
1252         const struct rlc_firmware_header_v2_0 *hdr;
1253         const __le32 *fw_data;
1254         unsigned i, fw_size;
1255
1256         if (!adev->gfx.rlc_fw)
1257                 return -EINVAL;
1258
1259         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1260         amdgpu_ucode_print_rlc_hdr(&hdr->header);
1261
1262         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1263                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1264         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1265
1266         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR,
1267                         RLCG_UCODE_LOADING_START_ADDRESS);
1268         for (i = 0; i < fw_size; i++) {
1269                 if (amdgpu_emu_mode == 1 && i % 100 == 0) {
1270                         dev_info(adev->dev, "Write RLC ucode data %u DWs\n", i);
1271                         msleep(1);
1272                 }
1273                 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
1274         }
1275         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
1276
1277         return 0;
1278 }
1279
1280 static int gfx_v9_4_3_xcc_rlc_resume(struct amdgpu_device *adev, int xcc_id)
1281 {
1282         int r;
1283
1284         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1285                 gfx_v9_4_3_xcc_rlc_stop(adev, xcc_id);
1286                 /* legacy rlc firmware loading */
1287                 r = gfx_v9_4_3_xcc_rlc_load_microcode(adev, xcc_id);
1288                 if (r)
1289                         return r;
1290                 gfx_v9_4_3_xcc_rlc_start(adev, xcc_id);
1291         }
1292
1293         amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id);
1294         /* disable CG */
1295         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0);
1296         gfx_v9_4_3_xcc_init_pg(adev, xcc_id);
1297         amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id);
1298
1299         return 0;
1300 }
1301
1302 static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev)
1303 {
1304         int r, i, num_xcc;
1305
1306         if (amdgpu_sriov_vf(adev))
1307                 return 0;
1308
1309         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1310         for (i = 0; i < num_xcc; i++) {
1311                 r = gfx_v9_4_3_xcc_rlc_resume(adev, i);
1312                 if (r)
1313                         return r;
1314         }
1315
1316         return 0;
1317 }
1318
1319 static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev,
1320                                        unsigned vmid)
1321 {
1322         u32 reg, data;
1323
1324         reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL);
1325         if (amdgpu_sriov_is_pp_one_vf(adev))
1326                 data = RREG32_NO_KIQ(reg);
1327         else
1328                 data = RREG32(reg);
1329
1330         data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
1331         data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
1332
1333         if (amdgpu_sriov_is_pp_one_vf(adev))
1334                 WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data);
1335         else
1336                 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data);
1337 }
1338
1339 static const struct soc15_reg_rlcg rlcg_access_gc_9_4_3[] = {
1340         {SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)},
1341         {SOC15_REG_ENTRY(GC, 0, regSQ_IND_INDEX)},
1342 };
1343
1344 static bool gfx_v9_4_3_check_rlcg_range(struct amdgpu_device *adev,
1345                                         uint32_t offset,
1346                                         struct soc15_reg_rlcg *entries, int arr_size)
1347 {
1348         int i, inst;
1349         uint32_t reg;
1350
1351         if (!entries)
1352                 return false;
1353
1354         for (i = 0; i < arr_size; i++) {
1355                 const struct soc15_reg_rlcg *entry;
1356
1357                 entry = &entries[i];
1358                 inst = adev->ip_map.logical_to_dev_inst ?
1359                                adev->ip_map.logical_to_dev_inst(
1360                                        adev, entry->hwip, entry->instance) :
1361                                entry->instance;
1362                 reg = adev->reg_offset[entry->hwip][inst][entry->segment] +
1363                       entry->reg;
1364                 if (offset == reg)
1365                         return true;
1366         }
1367
1368         return false;
1369 }
1370
1371 static bool gfx_v9_4_3_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
1372 {
1373         return gfx_v9_4_3_check_rlcg_range(adev, offset,
1374                                         (void *)rlcg_access_gc_9_4_3,
1375                                         ARRAY_SIZE(rlcg_access_gc_9_4_3));
1376 }
1377
1378 static void gfx_v9_4_3_xcc_cp_compute_enable(struct amdgpu_device *adev,
1379                                              bool enable, int xcc_id)
1380 {
1381         if (enable) {
1382                 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 0);
1383         } else {
1384                 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL,
1385                         (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
1386                 adev->gfx.kiq[xcc_id].ring.sched.ready = false;
1387         }
1388         udelay(50);
1389 }
1390
1391 static int gfx_v9_4_3_xcc_cp_compute_load_microcode(struct amdgpu_device *adev,
1392                                                     int xcc_id)
1393 {
1394         const struct gfx_firmware_header_v1_0 *mec_hdr;
1395         const __le32 *fw_data;
1396         unsigned i;
1397         u32 tmp;
1398         u32 mec_ucode_addr_offset;
1399         u32 mec_ucode_data_offset;
1400
1401         if (!adev->gfx.mec_fw)
1402                 return -EINVAL;
1403
1404         gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id);
1405
1406         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1407         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
1408
1409         fw_data = (const __le32 *)
1410                 (adev->gfx.mec_fw->data +
1411                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
1412         tmp = 0;
1413         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
1414         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
1415         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp);
1416
1417         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO,
1418                 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
1419         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI,
1420                 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
1421
1422         mec_ucode_addr_offset =
1423                 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_ADDR);
1424         mec_ucode_data_offset =
1425                 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_DATA);
1426
1427         /* MEC1 */
1428         WREG32(mec_ucode_addr_offset, mec_hdr->jt_offset);
1429         for (i = 0; i < mec_hdr->jt_size; i++)
1430                 WREG32(mec_ucode_data_offset,
1431                        le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
1432
1433         WREG32(mec_ucode_addr_offset, adev->gfx.mec_fw_version);
1434         /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
1435
1436         return 0;
1437 }
1438
1439 /* KIQ functions */
1440 static void gfx_v9_4_3_xcc_kiq_setting(struct amdgpu_ring *ring, int xcc_id)
1441 {
1442         uint32_t tmp;
1443         struct amdgpu_device *adev = ring->adev;
1444
1445         /* tell RLC which is KIQ queue */
1446         tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS);
1447         tmp &= 0xffffff00;
1448         tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
1449         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp);
1450         tmp |= 0x80;
1451         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp);
1452 }
1453
1454 static void gfx_v9_4_3_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd)
1455 {
1456         struct amdgpu_device *adev = ring->adev;
1457
1458         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
1459                 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) {
1460                         mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
1461                         mqd->cp_hqd_queue_priority =
1462                                 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
1463                 }
1464         }
1465 }
1466
1467 static int gfx_v9_4_3_xcc_mqd_init(struct amdgpu_ring *ring, int xcc_id)
1468 {
1469         struct amdgpu_device *adev = ring->adev;
1470         struct v9_mqd *mqd = ring->mqd_ptr;
1471         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
1472         uint32_t tmp;
1473
1474         mqd->header = 0xC0310800;
1475         mqd->compute_pipelinestat_enable = 0x00000001;
1476         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
1477         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
1478         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
1479         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
1480         mqd->compute_misc_reserved = 0x00000003;
1481
1482         mqd->dynamic_cu_mask_addr_lo =
1483                 lower_32_bits(ring->mqd_gpu_addr
1484                               + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
1485         mqd->dynamic_cu_mask_addr_hi =
1486                 upper_32_bits(ring->mqd_gpu_addr
1487                               + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
1488
1489         eop_base_addr = ring->eop_gpu_addr >> 8;
1490         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
1491         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
1492
1493         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
1494         tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL);
1495         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
1496                         (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1));
1497
1498         mqd->cp_hqd_eop_control = tmp;
1499
1500         /* enable doorbell? */
1501         tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL);
1502
1503         if (ring->use_doorbell) {
1504                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1505                                     DOORBELL_OFFSET, ring->doorbell_index);
1506                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1507                                     DOORBELL_EN, 1);
1508                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1509                                     DOORBELL_SOURCE, 0);
1510                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1511                                     DOORBELL_HIT, 0);
1512         } else {
1513                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1514                                          DOORBELL_EN, 0);
1515         }
1516
1517         mqd->cp_hqd_pq_doorbell_control = tmp;
1518
1519         /* disable the queue if it's active */
1520         ring->wptr = 0;
1521         mqd->cp_hqd_dequeue_request = 0;
1522         mqd->cp_hqd_pq_rptr = 0;
1523         mqd->cp_hqd_pq_wptr_lo = 0;
1524         mqd->cp_hqd_pq_wptr_hi = 0;
1525
1526         /* set the pointer to the MQD */
1527         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
1528         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
1529
1530         /* set MQD vmid to 0 */
1531         tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL);
1532         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
1533         mqd->cp_mqd_control = tmp;
1534
1535         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
1536         hqd_gpu_addr = ring->gpu_addr >> 8;
1537         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
1538         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
1539
1540         /* set up the HQD, this is similar to CP_RB0_CNTL */
1541         tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL);
1542         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
1543                             (order_base_2(ring->ring_size / 4) - 1));
1544         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
1545                         ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
1546 #ifdef __BIG_ENDIAN
1547         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
1548 #endif
1549         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
1550         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
1551         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
1552         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
1553         mqd->cp_hqd_pq_control = tmp;
1554
1555         /* set the wb address whether it's enabled or not */
1556         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
1557         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
1558         mqd->cp_hqd_pq_rptr_report_addr_hi =
1559                 upper_32_bits(wb_gpu_addr) & 0xffff;
1560
1561         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
1562         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
1563         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
1564         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
1565
1566         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
1567         ring->wptr = 0;
1568         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR);
1569
1570         /* set the vmid for the queue */
1571         mqd->cp_hqd_vmid = 0;
1572
1573         tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE);
1574         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
1575         mqd->cp_hqd_persistent_state = tmp;
1576
1577         /* set MIN_IB_AVAIL_SIZE */
1578         tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL);
1579         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
1580         mqd->cp_hqd_ib_control = tmp;
1581
1582         /* set static priority for a queue/ring */
1583         gfx_v9_4_3_mqd_set_priority(ring, mqd);
1584         mqd->cp_hqd_quantum = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM);
1585
1586         /* map_queues packet doesn't need activate the queue,
1587          * so only kiq need set this field.
1588          */
1589         if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
1590                 mqd->cp_hqd_active = 1;
1591
1592         return 0;
1593 }
1594
1595 static int gfx_v9_4_3_xcc_kiq_init_register(struct amdgpu_ring *ring,
1596                                             int xcc_id)
1597 {
1598         struct amdgpu_device *adev = ring->adev;
1599         struct v9_mqd *mqd = ring->mqd_ptr;
1600         int j;
1601
1602         /* disable wptr polling */
1603         WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0);
1604
1605         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR,
1606                mqd->cp_hqd_eop_base_addr_lo);
1607         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI,
1608                mqd->cp_hqd_eop_base_addr_hi);
1609
1610         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
1611         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL,
1612                mqd->cp_hqd_eop_control);
1613
1614         /* enable doorbell? */
1615         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL,
1616                mqd->cp_hqd_pq_doorbell_control);
1617
1618         /* disable the queue if it's active */
1619         if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) {
1620                 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1);
1621                 for (j = 0; j < adev->usec_timeout; j++) {
1622                         if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1))
1623                                 break;
1624                         udelay(1);
1625                 }
1626                 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST,
1627                        mqd->cp_hqd_dequeue_request);
1628                 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR,
1629                        mqd->cp_hqd_pq_rptr);
1630                 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO,
1631                        mqd->cp_hqd_pq_wptr_lo);
1632                 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI,
1633                        mqd->cp_hqd_pq_wptr_hi);
1634         }
1635
1636         /* set the pointer to the MQD */
1637         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR,
1638                mqd->cp_mqd_base_addr_lo);
1639         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI,
1640                mqd->cp_mqd_base_addr_hi);
1641
1642         /* set MQD vmid to 0 */
1643         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL,
1644                mqd->cp_mqd_control);
1645
1646         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
1647         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE,
1648                mqd->cp_hqd_pq_base_lo);
1649         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI,
1650                mqd->cp_hqd_pq_base_hi);
1651
1652         /* set up the HQD, this is similar to CP_RB0_CNTL */
1653         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL,
1654                mqd->cp_hqd_pq_control);
1655
1656         /* set the wb address whether it's enabled or not */
1657         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR,
1658                                 mqd->cp_hqd_pq_rptr_report_addr_lo);
1659         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
1660                                 mqd->cp_hqd_pq_rptr_report_addr_hi);
1661
1662         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
1663         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR,
1664                mqd->cp_hqd_pq_wptr_poll_addr_lo);
1665         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI,
1666                mqd->cp_hqd_pq_wptr_poll_addr_hi);
1667
1668         /* enable the doorbell if requested */
1669         if (ring->use_doorbell) {
1670                 WREG32_SOC15(
1671                         GC, GET_INST(GC, xcc_id),
1672                         regCP_MEC_DOORBELL_RANGE_LOWER,
1673                         ((adev->doorbell_index.kiq +
1674                           xcc_id * adev->doorbell_index.xcc_doorbell_range) *
1675                          2) << 2);
1676                 WREG32_SOC15(
1677                         GC, GET_INST(GC, xcc_id),
1678                         regCP_MEC_DOORBELL_RANGE_UPPER,
1679                         ((adev->doorbell_index.userqueue_end +
1680                           xcc_id * adev->doorbell_index.xcc_doorbell_range) *
1681                          2) << 2);
1682         }
1683
1684         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL,
1685                mqd->cp_hqd_pq_doorbell_control);
1686
1687         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
1688         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO,
1689                mqd->cp_hqd_pq_wptr_lo);
1690         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI,
1691                mqd->cp_hqd_pq_wptr_hi);
1692
1693         /* set the vmid for the queue */
1694         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, mqd->cp_hqd_vmid);
1695
1696         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE,
1697                mqd->cp_hqd_persistent_state);
1698
1699         /* activate the queue */
1700         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE,
1701                mqd->cp_hqd_active);
1702
1703         if (ring->use_doorbell)
1704                 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1);
1705
1706         return 0;
1707 }
1708
1709 static int gfx_v9_4_3_xcc_q_fini_register(struct amdgpu_ring *ring,
1710                                             int xcc_id)
1711 {
1712         struct amdgpu_device *adev = ring->adev;
1713         int j;
1714
1715         /* disable the queue if it's active */
1716         if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) {
1717
1718                 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1);
1719
1720                 for (j = 0; j < adev->usec_timeout; j++) {
1721                         if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1))
1722                                 break;
1723                         udelay(1);
1724                 }
1725
1726                 if (j == AMDGPU_MAX_USEC_TIMEOUT) {
1727                         DRM_DEBUG("%s dequeue request failed.\n", ring->name);
1728
1729                         /* Manual disable if dequeue request times out */
1730                         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0);
1731                 }
1732
1733                 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST,
1734                       0);
1735         }
1736
1737         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IQ_TIMER, 0);
1738         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL, 0);
1739         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, 0);
1740         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000);
1741         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0);
1742         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0);
1743         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0);
1744         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0);
1745
1746         return 0;
1747 }
1748
1749 static int gfx_v9_4_3_xcc_kiq_init_queue(struct amdgpu_ring *ring, int xcc_id)
1750 {
1751         struct amdgpu_device *adev = ring->adev;
1752         struct v9_mqd *mqd = ring->mqd_ptr;
1753         struct v9_mqd *tmp_mqd;
1754
1755         gfx_v9_4_3_xcc_kiq_setting(ring, xcc_id);
1756
1757         /* GPU could be in bad state during probe, driver trigger the reset
1758          * after load the SMU, in this case , the mqd is not be initialized.
1759          * driver need to re-init the mqd.
1760          * check mqd->cp_hqd_pq_control since this value should not be 0
1761          */
1762         tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[xcc_id].mqd_backup;
1763         if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control) {
1764                 /* for GPU_RESET case , reset MQD to a clean status */
1765                 if (adev->gfx.kiq[xcc_id].mqd_backup)
1766                         memcpy(mqd, adev->gfx.kiq[xcc_id].mqd_backup, sizeof(struct v9_mqd_allocation));
1767
1768                 /* reset ring buffer */
1769                 ring->wptr = 0;
1770                 amdgpu_ring_clear_ring(ring);
1771                 mutex_lock(&adev->srbm_mutex);
1772                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id));
1773                 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id);
1774                 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
1775                 mutex_unlock(&adev->srbm_mutex);
1776         } else {
1777                 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
1778                 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
1779                 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
1780                 mutex_lock(&adev->srbm_mutex);
1781                 if (amdgpu_sriov_vf(adev) && adev->in_suspend)
1782                         amdgpu_ring_clear_ring(ring);
1783                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id));
1784                 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id);
1785                 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id);
1786                 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
1787                 mutex_unlock(&adev->srbm_mutex);
1788
1789                 if (adev->gfx.kiq[xcc_id].mqd_backup)
1790                         memcpy(adev->gfx.kiq[xcc_id].mqd_backup, mqd, sizeof(struct v9_mqd_allocation));
1791         }
1792
1793         return 0;
1794 }
1795
1796 static int gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id)
1797 {
1798         struct amdgpu_device *adev = ring->adev;
1799         struct v9_mqd *mqd = ring->mqd_ptr;
1800         int mqd_idx = ring - &adev->gfx.compute_ring[0];
1801         struct v9_mqd *tmp_mqd;
1802
1803         /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control
1804          * is not be initialized before
1805          */
1806         tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx];
1807
1808         if (!tmp_mqd->cp_hqd_pq_control ||
1809             (!amdgpu_in_reset(adev) && !adev->in_suspend)) {
1810                 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
1811                 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
1812                 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
1813                 mutex_lock(&adev->srbm_mutex);
1814                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id));
1815                 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id);
1816                 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
1817                 mutex_unlock(&adev->srbm_mutex);
1818
1819                 if (adev->gfx.mec.mqd_backup[mqd_idx])
1820                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
1821         } else {
1822                 /* restore MQD to a clean status */
1823                 if (adev->gfx.mec.mqd_backup[mqd_idx])
1824                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
1825                 /* reset ring buffer */
1826                 ring->wptr = 0;
1827                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
1828                 amdgpu_ring_clear_ring(ring);
1829         }
1830
1831         return 0;
1832 }
1833
1834 static int gfx_v9_4_3_xcc_kcq_fini_register(struct amdgpu_device *adev, int xcc_id)
1835 {
1836         struct amdgpu_ring *ring;
1837         int j;
1838
1839         for (j = 0; j < adev->gfx.num_compute_rings; j++) {
1840                 ring = &adev->gfx.compute_ring[j +  xcc_id * adev->gfx.num_compute_rings];
1841                 if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
1842                         mutex_lock(&adev->srbm_mutex);
1843                         soc15_grbm_select(adev, ring->me,
1844                                         ring->pipe,
1845                                         ring->queue, 0, GET_INST(GC, xcc_id));
1846                         gfx_v9_4_3_xcc_q_fini_register(ring, xcc_id);
1847                         soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
1848                         mutex_unlock(&adev->srbm_mutex);
1849                 }
1850         }
1851
1852         return 0;
1853 }
1854
1855 static int gfx_v9_4_3_xcc_kiq_resume(struct amdgpu_device *adev, int xcc_id)
1856 {
1857         struct amdgpu_ring *ring;
1858         int r;
1859
1860         ring = &adev->gfx.kiq[xcc_id].ring;
1861
1862         r = amdgpu_bo_reserve(ring->mqd_obj, false);
1863         if (unlikely(r != 0))
1864                 return r;
1865
1866         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
1867         if (unlikely(r != 0)) {
1868                 amdgpu_bo_unreserve(ring->mqd_obj);
1869                 return r;
1870         }
1871
1872         gfx_v9_4_3_xcc_kiq_init_queue(ring, xcc_id);
1873         amdgpu_bo_kunmap(ring->mqd_obj);
1874         ring->mqd_ptr = NULL;
1875         amdgpu_bo_unreserve(ring->mqd_obj);
1876         return 0;
1877 }
1878
1879 static int gfx_v9_4_3_xcc_kcq_resume(struct amdgpu_device *adev, int xcc_id)
1880 {
1881         struct amdgpu_ring *ring = NULL;
1882         int r = 0, i;
1883
1884         gfx_v9_4_3_xcc_cp_compute_enable(adev, true, xcc_id);
1885
1886         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1887                 ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings];
1888
1889                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
1890                 if (unlikely(r != 0))
1891                         goto done;
1892                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
1893                 if (!r) {
1894                         r = gfx_v9_4_3_xcc_kcq_init_queue(ring, xcc_id);
1895                         amdgpu_bo_kunmap(ring->mqd_obj);
1896                         ring->mqd_ptr = NULL;
1897                 }
1898                 amdgpu_bo_unreserve(ring->mqd_obj);
1899                 if (r)
1900                         goto done;
1901         }
1902
1903         r = amdgpu_gfx_enable_kcq(adev, xcc_id);
1904 done:
1905         return r;
1906 }
1907
1908 static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id)
1909 {
1910         struct amdgpu_ring *ring;
1911         int r, j;
1912
1913         gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id);
1914
1915         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1916                 gfx_v9_4_3_xcc_disable_gpa_mode(adev, xcc_id);
1917
1918                 r = gfx_v9_4_3_xcc_cp_compute_load_microcode(adev, xcc_id);
1919                 if (r)
1920                         return r;
1921         }
1922
1923         /* set the virtual and physical id based on partition_mode */
1924         gfx_v9_4_3_xcc_program_xcc_id(adev, xcc_id);
1925
1926         r = gfx_v9_4_3_xcc_kiq_resume(adev, xcc_id);
1927         if (r)
1928                 return r;
1929
1930         r = gfx_v9_4_3_xcc_kcq_resume(adev, xcc_id);
1931         if (r)
1932                 return r;
1933
1934         for (j = 0; j < adev->gfx.num_compute_rings; j++) {
1935                 ring = &adev->gfx.compute_ring
1936                                 [j + xcc_id * adev->gfx.num_compute_rings];
1937                 r = amdgpu_ring_test_helper(ring);
1938                 if (r)
1939                         return r;
1940         }
1941
1942         gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id);
1943
1944         return 0;
1945 }
1946
1947 static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev)
1948 {
1949         int r = 0, i, num_xcc;
1950
1951         if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr,
1952                                             AMDGPU_XCP_FL_NONE) ==
1953             AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE)
1954                 r = amdgpu_xcp_switch_partition_mode(adev->xcp_mgr,
1955                                                      amdgpu_user_partt_mode);
1956
1957         if (r)
1958                 return r;
1959
1960         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1961         for (i = 0; i < num_xcc; i++) {
1962                 r = gfx_v9_4_3_xcc_cp_resume(adev, i);
1963                 if (r)
1964                         return r;
1965         }
1966
1967         return 0;
1968 }
1969
1970 static void gfx_v9_4_3_xcc_cp_enable(struct amdgpu_device *adev, bool enable,
1971                                      int xcc_id)
1972 {
1973         gfx_v9_4_3_xcc_cp_compute_enable(adev, enable, xcc_id);
1974 }
1975
1976 static void gfx_v9_4_3_xcc_fini(struct amdgpu_device *adev, int xcc_id)
1977 {
1978         if (amdgpu_gfx_disable_kcq(adev, xcc_id))
1979                 DRM_ERROR("XCD %d KCQ disable failed\n", xcc_id);
1980
1981         if (amdgpu_sriov_vf(adev)) {
1982                 /* must disable polling for SRIOV when hw finished, otherwise
1983                  * CPC engine may still keep fetching WB address which is already
1984                  * invalid after sw finished and trigger DMAR reading error in
1985                  * hypervisor side.
1986                  */
1987                 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0);
1988                 return;
1989         }
1990
1991         /* Use deinitialize sequence from CAIL when unbinding device
1992          * from driver, otherwise KIQ is hanging when binding back
1993          */
1994         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
1995                 mutex_lock(&adev->srbm_mutex);
1996                 soc15_grbm_select(adev, adev->gfx.kiq[xcc_id].ring.me,
1997                                   adev->gfx.kiq[xcc_id].ring.pipe,
1998                                   adev->gfx.kiq[xcc_id].ring.queue, 0,
1999                                   GET_INST(GC, xcc_id));
2000                 gfx_v9_4_3_xcc_q_fini_register(&adev->gfx.kiq[xcc_id].ring,
2001                                                  xcc_id);
2002                 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
2003                 mutex_unlock(&adev->srbm_mutex);
2004         }
2005
2006         gfx_v9_4_3_xcc_kcq_fini_register(adev, xcc_id);
2007         gfx_v9_4_3_xcc_cp_enable(adev, false, xcc_id);
2008 }
2009
2010 static int gfx_v9_4_3_hw_init(void *handle)
2011 {
2012         int r;
2013         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2014
2015         if (!amdgpu_sriov_vf(adev))
2016                 gfx_v9_4_3_init_golden_registers(adev);
2017
2018         gfx_v9_4_3_constants_init(adev);
2019
2020         r = adev->gfx.rlc.funcs->resume(adev);
2021         if (r)
2022                 return r;
2023
2024         r = gfx_v9_4_3_cp_resume(adev);
2025         if (r)
2026                 return r;
2027
2028         return r;
2029 }
2030
2031 static int gfx_v9_4_3_hw_fini(void *handle)
2032 {
2033         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2034         int i, num_xcc;
2035
2036         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
2037         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
2038
2039         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
2040         for (i = 0; i < num_xcc; i++) {
2041                 gfx_v9_4_3_xcc_fini(adev, i);
2042         }
2043
2044         return 0;
2045 }
2046
2047 static int gfx_v9_4_3_suspend(void *handle)
2048 {
2049         return gfx_v9_4_3_hw_fini(handle);
2050 }
2051
2052 static int gfx_v9_4_3_resume(void *handle)
2053 {
2054         return gfx_v9_4_3_hw_init(handle);
2055 }
2056
2057 static bool gfx_v9_4_3_is_idle(void *handle)
2058 {
2059         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2060         int i, num_xcc;
2061
2062         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
2063         for (i = 0; i < num_xcc; i++) {
2064                 if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS),
2065                                         GRBM_STATUS, GUI_ACTIVE))
2066                         return false;
2067         }
2068         return true;
2069 }
2070
2071 static int gfx_v9_4_3_wait_for_idle(void *handle)
2072 {
2073         unsigned i;
2074         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2075
2076         for (i = 0; i < adev->usec_timeout; i++) {
2077                 if (gfx_v9_4_3_is_idle(handle))
2078                         return 0;
2079                 udelay(1);
2080         }
2081         return -ETIMEDOUT;
2082 }
2083
2084 static int gfx_v9_4_3_soft_reset(void *handle)
2085 {
2086         u32 grbm_soft_reset = 0;
2087         u32 tmp;
2088         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2089
2090         /* GRBM_STATUS */
2091         tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS);
2092         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
2093                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
2094                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
2095                    GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
2096                    GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
2097                    GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
2098                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2099                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
2100                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2101                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
2102         }
2103
2104         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
2105                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2106                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
2107         }
2108
2109         /* GRBM_STATUS2 */
2110         tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS2);
2111         if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
2112                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2113                                                 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2114
2115
2116         if (grbm_soft_reset) {
2117                 /* stop the rlc */
2118                 adev->gfx.rlc.funcs->stop(adev);
2119
2120                 /* Disable MEC parsing/prefetching */
2121                 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, 0);
2122
2123                 if (grbm_soft_reset) {
2124                         tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET);
2125                         tmp |= grbm_soft_reset;
2126                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
2127                         WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp);
2128                         tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET);
2129
2130                         udelay(50);
2131
2132                         tmp &= ~grbm_soft_reset;
2133                         WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp);
2134                         tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET);
2135                 }
2136
2137                 /* Wait a little for things to settle down */
2138                 udelay(50);
2139         }
2140         return 0;
2141 }
2142
2143 static void gfx_v9_4_3_ring_emit_gds_switch(struct amdgpu_ring *ring,
2144                                           uint32_t vmid,
2145                                           uint32_t gds_base, uint32_t gds_size,
2146                                           uint32_t gws_base, uint32_t gws_size,
2147                                           uint32_t oa_base, uint32_t oa_size)
2148 {
2149         struct amdgpu_device *adev = ring->adev;
2150
2151         /* GDS Base */
2152         gfx_v9_4_3_write_data_to_reg(ring, 0, false,
2153                                    SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_BASE) + 2 * vmid,
2154                                    gds_base);
2155
2156         /* GDS Size */
2157         gfx_v9_4_3_write_data_to_reg(ring, 0, false,
2158                                    SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_SIZE) + 2 * vmid,
2159                                    gds_size);
2160
2161         /* GWS */
2162         gfx_v9_4_3_write_data_to_reg(ring, 0, false,
2163                                    SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_GWS_VMID0) + vmid,
2164                                    gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
2165
2166         /* OA */
2167         gfx_v9_4_3_write_data_to_reg(ring, 0, false,
2168                                    SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_OA_VMID0) + vmid,
2169                                    (1 << (oa_size + oa_base)) - (1 << oa_base));
2170 }
2171
2172 static int gfx_v9_4_3_early_init(void *handle)
2173 {
2174         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2175
2176         adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
2177                                           AMDGPU_MAX_COMPUTE_RINGS);
2178         gfx_v9_4_3_set_kiq_pm4_funcs(adev);
2179         gfx_v9_4_3_set_ring_funcs(adev);
2180         gfx_v9_4_3_set_irq_funcs(adev);
2181         gfx_v9_4_3_set_gds_init(adev);
2182         gfx_v9_4_3_set_rlc_funcs(adev);
2183
2184         return gfx_v9_4_3_init_microcode(adev);
2185 }
2186
2187 static int gfx_v9_4_3_late_init(void *handle)
2188 {
2189         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2190         int r;
2191
2192         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
2193         if (r)
2194                 return r;
2195
2196         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
2197         if (r)
2198                 return r;
2199
2200         return 0;
2201 }
2202
2203 static void gfx_v9_4_3_xcc_update_sram_fgcg(struct amdgpu_device *adev,
2204                                             bool enable, int xcc_id)
2205 {
2206         uint32_t def, data;
2207
2208         if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))
2209                 return;
2210
2211         def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id),
2212                                   regRLC_CGTT_MGCG_OVERRIDE);
2213
2214         if (enable)
2215                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
2216         else
2217                 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
2218
2219         if (def != data)
2220                 WREG32_SOC15(GC, GET_INST(GC, xcc_id),
2221                              regRLC_CGTT_MGCG_OVERRIDE, data);
2222
2223         def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CLK_CNTL);
2224
2225         if (enable)
2226                 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
2227         else
2228                 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
2229
2230         if (def != data)
2231                 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CLK_CNTL, data);
2232 }
2233
2234 static void gfx_v9_4_3_xcc_update_repeater_fgcg(struct amdgpu_device *adev,
2235                                                 bool enable, int xcc_id)
2236 {
2237         uint32_t def, data;
2238
2239         if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG))
2240                 return;
2241
2242         def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id),
2243                                   regRLC_CGTT_MGCG_OVERRIDE);
2244
2245         if (enable)
2246                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK;
2247         else
2248                 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK;
2249
2250         if (def != data)
2251                 WREG32_SOC15(GC, GET_INST(GC, xcc_id),
2252                              regRLC_CGTT_MGCG_OVERRIDE, data);
2253 }
2254
2255 static void
2256 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(struct amdgpu_device *adev,
2257                                                 bool enable, int xcc_id)
2258 {
2259         uint32_t data, def;
2260
2261         /* It is disabled by HW by default */
2262         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
2263                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
2264                 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);
2265
2266                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
2267                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
2268                           RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
2269                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
2270
2271                 if (def != data)
2272                         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data);
2273
2274                 /* MGLS is a global flag to control all MGLS in GFX */
2275                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
2276                         /* 2 - RLC memory Light sleep */
2277                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
2278                                 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL);
2279                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
2280                                 if (def != data)
2281                                         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data);
2282                         }
2283                         /* 3 - CP memory Light sleep */
2284                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
2285                                 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL);
2286                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2287                                 if (def != data)
2288                                         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data);
2289                         }
2290                 }
2291         } else {
2292                 /* 1 - MGCG_OVERRIDE */
2293                 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);
2294
2295                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
2296                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
2297                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
2298                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
2299
2300                 if (def != data)
2301                         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data);
2302
2303                 /* 2 - disable MGLS in RLC */
2304                 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL);
2305                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
2306                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
2307                         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data);
2308                 }
2309
2310                 /* 3 - disable MGLS in CP */
2311                 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL);
2312                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
2313                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2314                         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data);
2315                 }
2316         }
2317
2318 }
2319
2320 static void
2321 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
2322                                                 bool enable, int xcc_id)
2323 {
2324         uint32_t def, data;
2325
2326         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
2327
2328                 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);
2329                 /* unset CGCG override */
2330                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
2331                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
2332                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
2333                 else
2334                         data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
2335                 /* update CGCG and CGLS override bits */
2336                 if (def != data)
2337                         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data);
2338
2339                 /* enable cgcg FSM(0x0000363F) */
2340                 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL);
2341
2342                 data = (0x36
2343                         << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
2344                        RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
2345                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
2346                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
2347                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
2348                 if (def != data)
2349                         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data);
2350
2351                 /* set IDLE_POLL_COUNT(0x00900100) */
2352                 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL);
2353                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
2354                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
2355                 if (def != data)
2356                         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data);
2357         } else {
2358                 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL);
2359                 /* reset CGCG/CGLS bits */
2360                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
2361                 /* disable cgcg and cgls in FSM */
2362                 if (def != data)
2363                         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data);
2364         }
2365
2366 }
2367
2368 static int gfx_v9_4_3_xcc_update_gfx_clock_gating(struct amdgpu_device *adev,
2369                                                   bool enable, int xcc_id)
2370 {
2371         amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id);
2372
2373         if (enable) {
2374                 /* FGCG */
2375                 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id);
2376                 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id);
2377
2378                 /* CGCG/CGLS should be enabled after MGCG/MGLS
2379                  * ===  MGCG + MGLS ===
2380                  */
2381                 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable,
2382                                                                 xcc_id);
2383                 /* ===  CGCG + CGLS === */
2384                 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable,
2385                                                                 xcc_id);
2386         } else {
2387                 /* CGCG/CGLS should be disabled before MGCG/MGLS
2388                  * ===  CGCG + CGLS ===
2389                  */
2390                 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable,
2391                                                                 xcc_id);
2392                 /* ===  MGCG + MGLS === */
2393                 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable,
2394                                                                 xcc_id);
2395
2396                 /* FGCG */
2397                 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id);
2398                 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id);
2399         }
2400
2401         amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id);
2402
2403         return 0;
2404 }
2405
2406 static const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = {
2407         .is_rlc_enabled = gfx_v9_4_3_is_rlc_enabled,
2408         .set_safe_mode = gfx_v9_4_3_xcc_set_safe_mode,
2409         .unset_safe_mode = gfx_v9_4_3_xcc_unset_safe_mode,
2410         .init = gfx_v9_4_3_rlc_init,
2411         .resume = gfx_v9_4_3_rlc_resume,
2412         .stop = gfx_v9_4_3_rlc_stop,
2413         .reset = gfx_v9_4_3_rlc_reset,
2414         .start = gfx_v9_4_3_rlc_start,
2415         .update_spm_vmid = gfx_v9_4_3_update_spm_vmid,
2416         .is_rlcg_access_range = gfx_v9_4_3_is_rlcg_access_range,
2417 };
2418
2419 static int gfx_v9_4_3_set_powergating_state(void *handle,
2420                                           enum amd_powergating_state state)
2421 {
2422         return 0;
2423 }
2424
2425 static int gfx_v9_4_3_set_clockgating_state(void *handle,
2426                                           enum amd_clockgating_state state)
2427 {
2428         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2429         int i, num_xcc;
2430
2431         if (amdgpu_sriov_vf(adev))
2432                 return 0;
2433
2434         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
2435         switch (adev->ip_versions[GC_HWIP][0]) {
2436         case IP_VERSION(9, 4, 3):
2437                 for (i = 0; i < num_xcc; i++)
2438                         gfx_v9_4_3_xcc_update_gfx_clock_gating(
2439                                 adev, state == AMD_CG_STATE_GATE, i);
2440                 break;
2441         default:
2442                 break;
2443         }
2444         return 0;
2445 }
2446
2447 static void gfx_v9_4_3_get_clockgating_state(void *handle, u64 *flags)
2448 {
2449         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2450         int data;
2451
2452         if (amdgpu_sriov_vf(adev))
2453                 *flags = 0;
2454
2455         /* AMD_CG_SUPPORT_GFX_MGCG */
2456         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE));
2457         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
2458                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
2459
2460         /* AMD_CG_SUPPORT_GFX_CGCG */
2461         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL));
2462         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
2463                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
2464
2465         /* AMD_CG_SUPPORT_GFX_CGLS */
2466         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
2467                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
2468
2469         /* AMD_CG_SUPPORT_GFX_RLC_LS */
2470         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_MEM_SLP_CNTL));
2471         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
2472                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
2473
2474         /* AMD_CG_SUPPORT_GFX_CP_LS */
2475         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCP_MEM_SLP_CNTL));
2476         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
2477                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
2478 }
2479
2480 static void gfx_v9_4_3_ring_emit_hdp_flush(struct amdgpu_ring *ring)
2481 {
2482         struct amdgpu_device *adev = ring->adev;
2483         u32 ref_and_mask, reg_mem_engine;
2484         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
2485
2486         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
2487                 switch (ring->me) {
2488                 case 1:
2489                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
2490                         break;
2491                 case 2:
2492                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
2493                         break;
2494                 default:
2495                         return;
2496                 }
2497                 reg_mem_engine = 0;
2498         } else {
2499                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
2500                 reg_mem_engine = 1; /* pfp */
2501         }
2502
2503         gfx_v9_4_3_wait_reg_mem(ring, reg_mem_engine, 0, 1,
2504                               adev->nbio.funcs->get_hdp_flush_req_offset(adev),
2505                               adev->nbio.funcs->get_hdp_flush_done_offset(adev),
2506                               ref_and_mask, ref_and_mask, 0x20);
2507 }
2508
2509 static void gfx_v9_4_3_ring_emit_ib_compute(struct amdgpu_ring *ring,
2510                                           struct amdgpu_job *job,
2511                                           struct amdgpu_ib *ib,
2512                                           uint32_t flags)
2513 {
2514         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
2515         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
2516
2517         /* Currently, there is a high possibility to get wave ID mismatch
2518          * between ME and GDS, leading to a hw deadlock, because ME generates
2519          * different wave IDs than the GDS expects. This situation happens
2520          * randomly when at least 5 compute pipes use GDS ordered append.
2521          * The wave IDs generated by ME are also wrong after suspend/resume.
2522          * Those are probably bugs somewhere else in the kernel driver.
2523          *
2524          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
2525          * GDS to 0 for this ring (me/pipe).
2526          */
2527         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
2528                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2529                 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID);
2530                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
2531         }
2532
2533         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2534         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
2535         amdgpu_ring_write(ring,
2536 #ifdef __BIG_ENDIAN
2537                                 (2 << 0) |
2538 #endif
2539                                 lower_32_bits(ib->gpu_addr));
2540         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
2541         amdgpu_ring_write(ring, control);
2542 }
2543
2544 static void gfx_v9_4_3_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
2545                                      u64 seq, unsigned flags)
2546 {
2547         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2548         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2549         bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY;
2550
2551         /* RELEASE_MEM - flush caches, send int */
2552         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
2553         amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN |
2554                                                EOP_TC_NC_ACTION_EN) :
2555                                               (EOP_TCL1_ACTION_EN |
2556                                                EOP_TC_ACTION_EN |
2557                                                EOP_TC_WB_ACTION_EN |
2558                                                EOP_TC_MD_ACTION_EN)) |
2559                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2560                                  EVENT_INDEX(5)));
2561         amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
2562
2563         /*
2564          * the address should be Qword aligned if 64bit write, Dword
2565          * aligned if only send 32bit data low (discard data high)
2566          */
2567         if (write64bit)
2568                 BUG_ON(addr & 0x7);
2569         else
2570                 BUG_ON(addr & 0x3);
2571         amdgpu_ring_write(ring, lower_32_bits(addr));
2572         amdgpu_ring_write(ring, upper_32_bits(addr));
2573         amdgpu_ring_write(ring, lower_32_bits(seq));
2574         amdgpu_ring_write(ring, upper_32_bits(seq));
2575         amdgpu_ring_write(ring, 0);
2576 }
2577
2578 static void gfx_v9_4_3_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
2579 {
2580         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2581         uint32_t seq = ring->fence_drv.sync_seq;
2582         uint64_t addr = ring->fence_drv.gpu_addr;
2583
2584         gfx_v9_4_3_wait_reg_mem(ring, usepfp, 1, 0,
2585                               lower_32_bits(addr), upper_32_bits(addr),
2586                               seq, 0xffffffff, 4);
2587 }
2588
2589 static void gfx_v9_4_3_ring_emit_vm_flush(struct amdgpu_ring *ring,
2590                                         unsigned vmid, uint64_t pd_addr)
2591 {
2592         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
2593 }
2594
2595 static u64 gfx_v9_4_3_ring_get_rptr_compute(struct amdgpu_ring *ring)
2596 {
2597         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */
2598 }
2599
2600 static u64 gfx_v9_4_3_ring_get_wptr_compute(struct amdgpu_ring *ring)
2601 {
2602         u64 wptr;
2603
2604         /* XXX check if swapping is necessary on BE */
2605         if (ring->use_doorbell)
2606                 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
2607         else
2608                 BUG();
2609         return wptr;
2610 }
2611
2612 static void gfx_v9_4_3_ring_set_wptr_compute(struct amdgpu_ring *ring)
2613 {
2614         struct amdgpu_device *adev = ring->adev;
2615
2616         /* XXX check if swapping is necessary on BE */
2617         if (ring->use_doorbell) {
2618                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
2619                 WDOORBELL64(ring->doorbell_index, ring->wptr);
2620         } else {
2621                 BUG(); /* only DOORBELL method supported on gfx9 now */
2622         }
2623 }
2624
2625 static void gfx_v9_4_3_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
2626                                          u64 seq, unsigned int flags)
2627 {
2628         struct amdgpu_device *adev = ring->adev;
2629
2630         /* we only allocate 32bit for each seq wb address */
2631         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
2632
2633         /* write fence seq to the "addr" */
2634         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2635         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
2636                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
2637         amdgpu_ring_write(ring, lower_32_bits(addr));
2638         amdgpu_ring_write(ring, upper_32_bits(addr));
2639         amdgpu_ring_write(ring, lower_32_bits(seq));
2640
2641         if (flags & AMDGPU_FENCE_FLAG_INT) {
2642                 /* set register to trigger INT */
2643                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2644                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
2645                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
2646                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS));
2647                 amdgpu_ring_write(ring, 0);
2648                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
2649         }
2650 }
2651
2652 static void gfx_v9_4_3_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
2653                                     uint32_t reg_val_offs)
2654 {
2655         struct amdgpu_device *adev = ring->adev;
2656
2657         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
2658         amdgpu_ring_write(ring, 0 |     /* src: register*/
2659                                 (5 << 8) |      /* dst: memory */
2660                                 (1 << 20));     /* write confirm */
2661         amdgpu_ring_write(ring, reg);
2662         amdgpu_ring_write(ring, 0);
2663         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
2664                                 reg_val_offs * 4));
2665         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
2666                                 reg_val_offs * 4));
2667 }
2668
2669 static void gfx_v9_4_3_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
2670                                     uint32_t val)
2671 {
2672         uint32_t cmd = 0;
2673
2674         switch (ring->funcs->type) {
2675         case AMDGPU_RING_TYPE_GFX:
2676                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
2677                 break;
2678         case AMDGPU_RING_TYPE_KIQ:
2679                 cmd = (1 << 16); /* no inc addr */
2680                 break;
2681         default:
2682                 cmd = WR_CONFIRM;
2683                 break;
2684         }
2685         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2686         amdgpu_ring_write(ring, cmd);
2687         amdgpu_ring_write(ring, reg);
2688         amdgpu_ring_write(ring, 0);
2689         amdgpu_ring_write(ring, val);
2690 }
2691
2692 static void gfx_v9_4_3_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
2693                                         uint32_t val, uint32_t mask)
2694 {
2695         gfx_v9_4_3_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
2696 }
2697
2698 static void gfx_v9_4_3_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
2699                                                   uint32_t reg0, uint32_t reg1,
2700                                                   uint32_t ref, uint32_t mask)
2701 {
2702         amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
2703                                                    ref, mask);
2704 }
2705
2706 static void gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2707         struct amdgpu_device *adev, int me, int pipe,
2708         enum amdgpu_interrupt_state state, int xcc_id)
2709 {
2710         u32 mec_int_cntl, mec_int_cntl_reg;
2711
2712         /*
2713          * amdgpu controls only the first MEC. That's why this function only
2714          * handles the setting of interrupts for this specific MEC. All other
2715          * pipes' interrupts are set by amdkfd.
2716          */
2717
2718         if (me == 1) {
2719                 switch (pipe) {
2720                 case 0:
2721                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL);
2722                         break;
2723                 case 1:
2724                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL);
2725                         break;
2726                 case 2:
2727                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL);
2728                         break;
2729                 case 3:
2730                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL);
2731                         break;
2732                 default:
2733                         DRM_DEBUG("invalid pipe %d\n", pipe);
2734                         return;
2735                 }
2736         } else {
2737                 DRM_DEBUG("invalid me %d\n", me);
2738                 return;
2739         }
2740
2741         switch (state) {
2742         case AMDGPU_IRQ_STATE_DISABLE:
2743                 mec_int_cntl = RREG32(mec_int_cntl_reg);
2744                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
2745                                              TIME_STAMP_INT_ENABLE, 0);
2746                 WREG32(mec_int_cntl_reg, mec_int_cntl);
2747                 break;
2748         case AMDGPU_IRQ_STATE_ENABLE:
2749                 mec_int_cntl = RREG32(mec_int_cntl_reg);
2750                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
2751                                              TIME_STAMP_INT_ENABLE, 1);
2752                 WREG32(mec_int_cntl_reg, mec_int_cntl);
2753                 break;
2754         default:
2755                 break;
2756         }
2757 }
2758
2759 static int gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device *adev,
2760                                              struct amdgpu_irq_src *source,
2761                                              unsigned type,
2762                                              enum amdgpu_interrupt_state state)
2763 {
2764         int i, num_xcc;
2765
2766         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
2767         switch (state) {
2768         case AMDGPU_IRQ_STATE_DISABLE:
2769         case AMDGPU_IRQ_STATE_ENABLE:
2770                 for (i = 0; i < num_xcc; i++)
2771                         WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0,
2772                                 PRIV_REG_INT_ENABLE,
2773                                 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
2774                 break;
2775         default:
2776                 break;
2777         }
2778
2779         return 0;
2780 }
2781
2782 static int gfx_v9_4_3_set_priv_inst_fault_state(struct amdgpu_device *adev,
2783                                               struct amdgpu_irq_src *source,
2784                                               unsigned type,
2785                                               enum amdgpu_interrupt_state state)
2786 {
2787         int i, num_xcc;
2788
2789         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
2790         switch (state) {
2791         case AMDGPU_IRQ_STATE_DISABLE:
2792         case AMDGPU_IRQ_STATE_ENABLE:
2793                 for (i = 0; i < num_xcc; i++)
2794                         WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0,
2795                                 PRIV_INSTR_INT_ENABLE,
2796                                 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
2797                 break;
2798         default:
2799                 break;
2800         }
2801
2802         return 0;
2803 }
2804
2805 static int gfx_v9_4_3_set_eop_interrupt_state(struct amdgpu_device *adev,
2806                                             struct amdgpu_irq_src *src,
2807                                             unsigned type,
2808                                             enum amdgpu_interrupt_state state)
2809 {
2810         int i, num_xcc;
2811
2812         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
2813         for (i = 0; i < num_xcc; i++) {
2814                 switch (type) {
2815                 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
2816                         gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2817                                 adev, 1, 0, state, i);
2818                         break;
2819                 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
2820                         gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2821                                 adev, 1, 1, state, i);
2822                         break;
2823                 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
2824                         gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2825                                 adev, 1, 2, state, i);
2826                         break;
2827                 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
2828                         gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2829                                 adev, 1, 3, state, i);
2830                         break;
2831                 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
2832                         gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2833                                 adev, 2, 0, state, i);
2834                         break;
2835                 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
2836                         gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2837                                 adev, 2, 1, state, i);
2838                         break;
2839                 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
2840                         gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2841                                 adev, 2, 2, state, i);
2842                         break;
2843                 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
2844                         gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2845                                 adev, 2, 3, state, i);
2846                         break;
2847                 default:
2848                         break;
2849                 }
2850         }
2851
2852         return 0;
2853 }
2854
2855 static int gfx_v9_4_3_eop_irq(struct amdgpu_device *adev,
2856                             struct amdgpu_irq_src *source,
2857                             struct amdgpu_iv_entry *entry)
2858 {
2859         int i, xcc_id;
2860         u8 me_id, pipe_id, queue_id;
2861         struct amdgpu_ring *ring;
2862
2863         DRM_DEBUG("IH: CP EOP\n");
2864         me_id = (entry->ring_id & 0x0c) >> 2;
2865         pipe_id = (entry->ring_id & 0x03) >> 0;
2866         queue_id = (entry->ring_id & 0x70) >> 4;
2867
2868         xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id);
2869
2870         if (xcc_id == -EINVAL)
2871                 return -EINVAL;
2872
2873         switch (me_id) {
2874         case 0:
2875         case 1:
2876         case 2:
2877                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2878                         ring = &adev->gfx.compute_ring
2879                                         [i +
2880                                          xcc_id * adev->gfx.num_compute_rings];
2881                         /* Per-queue interrupt is supported for MEC starting from VI.
2882                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
2883                           */
2884
2885                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
2886                                 amdgpu_fence_process(ring);
2887                 }
2888                 break;
2889         }
2890         return 0;
2891 }
2892
2893 static void gfx_v9_4_3_fault(struct amdgpu_device *adev,
2894                            struct amdgpu_iv_entry *entry)
2895 {
2896         u8 me_id, pipe_id, queue_id;
2897         struct amdgpu_ring *ring;
2898         int i, xcc_id;
2899
2900         me_id = (entry->ring_id & 0x0c) >> 2;
2901         pipe_id = (entry->ring_id & 0x03) >> 0;
2902         queue_id = (entry->ring_id & 0x70) >> 4;
2903
2904         xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id);
2905
2906         if (xcc_id == -EINVAL)
2907                 return;
2908
2909         switch (me_id) {
2910         case 0:
2911         case 1:
2912         case 2:
2913                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2914                         ring = &adev->gfx.compute_ring
2915                                         [i +
2916                                          xcc_id * adev->gfx.num_compute_rings];
2917                         if (ring->me == me_id && ring->pipe == pipe_id &&
2918                             ring->queue == queue_id)
2919                                 drm_sched_fault(&ring->sched);
2920                 }
2921                 break;
2922         }
2923 }
2924
2925 static int gfx_v9_4_3_priv_reg_irq(struct amdgpu_device *adev,
2926                                  struct amdgpu_irq_src *source,
2927                                  struct amdgpu_iv_entry *entry)
2928 {
2929         DRM_ERROR("Illegal register access in command stream\n");
2930         gfx_v9_4_3_fault(adev, entry);
2931         return 0;
2932 }
2933
2934 static int gfx_v9_4_3_priv_inst_irq(struct amdgpu_device *adev,
2935                                   struct amdgpu_irq_src *source,
2936                                   struct amdgpu_iv_entry *entry)
2937 {
2938         DRM_ERROR("Illegal instruction in command stream\n");
2939         gfx_v9_4_3_fault(adev, entry);
2940         return 0;
2941 }
2942
2943 static void gfx_v9_4_3_emit_mem_sync(struct amdgpu_ring *ring)
2944 {
2945         const unsigned int cp_coher_cntl =
2946                         PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) |
2947                         PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) |
2948                         PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) |
2949                         PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) |
2950                         PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1);
2951
2952         /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */
2953         amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5));
2954         amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */
2955         amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
2956         amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
2957         amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
2958         amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
2959         amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
2960 }
2961
2962 static void gfx_v9_4_3_emit_wave_limit_cs(struct amdgpu_ring *ring,
2963                                         uint32_t pipe, bool enable)
2964 {
2965         struct amdgpu_device *adev = ring->adev;
2966         uint32_t val;
2967         uint32_t wcl_cs_reg;
2968
2969         /* regSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */
2970         val = enable ? 0x1 : 0x7f;
2971
2972         switch (pipe) {
2973         case 0:
2974                 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS0);
2975                 break;
2976         case 1:
2977                 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS1);
2978                 break;
2979         case 2:
2980                 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS2);
2981                 break;
2982         case 3:
2983                 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS3);
2984                 break;
2985         default:
2986                 DRM_DEBUG("invalid pipe %d\n", pipe);
2987                 return;
2988         }
2989
2990         amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val);
2991
2992 }
2993 static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable)
2994 {
2995         struct amdgpu_device *adev = ring->adev;
2996         uint32_t val;
2997         int i;
2998
2999         /* regSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit
3000          * number of gfx waves. Setting 5 bit will make sure gfx only gets
3001          * around 25% of gpu resources.
3002          */
3003         val = enable ? 0x1f : 0x07ffffff;
3004         amdgpu_ring_emit_wreg(ring,
3005                               SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_GFX),
3006                               val);
3007
3008         /* Restrict waves for normal/low priority compute queues as well
3009          * to get best QoS for high priority compute jobs.
3010          *
3011          * amdgpu controls only 1st ME(0-3 CS pipes).
3012          */
3013         for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {
3014                 if (i != ring->pipe)
3015                         gfx_v9_4_3_emit_wave_limit_cs(ring, i, enable);
3016
3017         }
3018 }
3019
3020 enum amdgpu_gfx_cp_ras_mem_id {
3021         AMDGPU_GFX_CP_MEM1 = 1,
3022         AMDGPU_GFX_CP_MEM2,
3023         AMDGPU_GFX_CP_MEM3,
3024         AMDGPU_GFX_CP_MEM4,
3025         AMDGPU_GFX_CP_MEM5,
3026 };
3027
3028 enum amdgpu_gfx_gcea_ras_mem_id {
3029         AMDGPU_GFX_GCEA_IOWR_CMDMEM = 4,
3030         AMDGPU_GFX_GCEA_IORD_CMDMEM,
3031         AMDGPU_GFX_GCEA_GMIWR_CMDMEM,
3032         AMDGPU_GFX_GCEA_GMIRD_CMDMEM,
3033         AMDGPU_GFX_GCEA_DRAMWR_CMDMEM,
3034         AMDGPU_GFX_GCEA_DRAMRD_CMDMEM,
3035         AMDGPU_GFX_GCEA_MAM_DMEM0,
3036         AMDGPU_GFX_GCEA_MAM_DMEM1,
3037         AMDGPU_GFX_GCEA_MAM_DMEM2,
3038         AMDGPU_GFX_GCEA_MAM_DMEM3,
3039         AMDGPU_GFX_GCEA_MAM_AMEM0,
3040         AMDGPU_GFX_GCEA_MAM_AMEM1,
3041         AMDGPU_GFX_GCEA_MAM_AMEM2,
3042         AMDGPU_GFX_GCEA_MAM_AMEM3,
3043         AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER,
3044         AMDGPU_GFX_GCEA_WRET_TAGMEM,
3045         AMDGPU_GFX_GCEA_RRET_TAGMEM,
3046         AMDGPU_GFX_GCEA_IOWR_DATAMEM,
3047         AMDGPU_GFX_GCEA_GMIWR_DATAMEM,
3048         AMDGPU_GFX_GCEA_DRAM_DATAMEM,
3049 };
3050
3051 enum amdgpu_gfx_gc_cane_ras_mem_id {
3052         AMDGPU_GFX_GC_CANE_MEM0 = 0,
3053 };
3054
3055 enum amdgpu_gfx_gcutcl2_ras_mem_id {
3056         AMDGPU_GFX_GCUTCL2_MEM2P512X95 = 160,
3057 };
3058
3059 enum amdgpu_gfx_gds_ras_mem_id {
3060         AMDGPU_GFX_GDS_MEM0 = 0,
3061 };
3062
3063 enum amdgpu_gfx_lds_ras_mem_id {
3064         AMDGPU_GFX_LDS_BANK0 = 0,
3065         AMDGPU_GFX_LDS_BANK1,
3066         AMDGPU_GFX_LDS_BANK2,
3067         AMDGPU_GFX_LDS_BANK3,
3068         AMDGPU_GFX_LDS_BANK4,
3069         AMDGPU_GFX_LDS_BANK5,
3070         AMDGPU_GFX_LDS_BANK6,
3071         AMDGPU_GFX_LDS_BANK7,
3072         AMDGPU_GFX_LDS_BANK8,
3073         AMDGPU_GFX_LDS_BANK9,
3074         AMDGPU_GFX_LDS_BANK10,
3075         AMDGPU_GFX_LDS_BANK11,
3076         AMDGPU_GFX_LDS_BANK12,
3077         AMDGPU_GFX_LDS_BANK13,
3078         AMDGPU_GFX_LDS_BANK14,
3079         AMDGPU_GFX_LDS_BANK15,
3080         AMDGPU_GFX_LDS_BANK16,
3081         AMDGPU_GFX_LDS_BANK17,
3082         AMDGPU_GFX_LDS_BANK18,
3083         AMDGPU_GFX_LDS_BANK19,
3084         AMDGPU_GFX_LDS_BANK20,
3085         AMDGPU_GFX_LDS_BANK21,
3086         AMDGPU_GFX_LDS_BANK22,
3087         AMDGPU_GFX_LDS_BANK23,
3088         AMDGPU_GFX_LDS_BANK24,
3089         AMDGPU_GFX_LDS_BANK25,
3090         AMDGPU_GFX_LDS_BANK26,
3091         AMDGPU_GFX_LDS_BANK27,
3092         AMDGPU_GFX_LDS_BANK28,
3093         AMDGPU_GFX_LDS_BANK29,
3094         AMDGPU_GFX_LDS_BANK30,
3095         AMDGPU_GFX_LDS_BANK31,
3096         AMDGPU_GFX_LDS_SP_BUFFER_A,
3097         AMDGPU_GFX_LDS_SP_BUFFER_B,
3098 };
3099
3100 enum amdgpu_gfx_rlc_ras_mem_id {
3101         AMDGPU_GFX_RLC_GPMF32 = 1,
3102         AMDGPU_GFX_RLC_RLCVF32,
3103         AMDGPU_GFX_RLC_SCRATCH,
3104         AMDGPU_GFX_RLC_SRM_ARAM,
3105         AMDGPU_GFX_RLC_SRM_DRAM,
3106         AMDGPU_GFX_RLC_TCTAG,
3107         AMDGPU_GFX_RLC_SPM_SE,
3108         AMDGPU_GFX_RLC_SPM_GRBMT,
3109 };
3110
3111 enum amdgpu_gfx_sp_ras_mem_id {
3112         AMDGPU_GFX_SP_SIMDID0 = 0,
3113 };
3114
3115 enum amdgpu_gfx_spi_ras_mem_id {
3116         AMDGPU_GFX_SPI_MEM0 = 0,
3117         AMDGPU_GFX_SPI_MEM1,
3118         AMDGPU_GFX_SPI_MEM2,
3119         AMDGPU_GFX_SPI_MEM3,
3120 };
3121
3122 enum amdgpu_gfx_sqc_ras_mem_id {
3123         AMDGPU_GFX_SQC_INST_CACHE_A = 100,
3124         AMDGPU_GFX_SQC_INST_CACHE_B = 101,
3125         AMDGPU_GFX_SQC_INST_CACHE_TAG_A = 102,
3126         AMDGPU_GFX_SQC_INST_CACHE_TAG_B = 103,
3127         AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A = 104,
3128         AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B = 105,
3129         AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A = 106,
3130         AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B = 107,
3131         AMDGPU_GFX_SQC_DATA_CACHE_A = 200,
3132         AMDGPU_GFX_SQC_DATA_CACHE_B = 201,
3133         AMDGPU_GFX_SQC_DATA_CACHE_TAG_A = 202,
3134         AMDGPU_GFX_SQC_DATA_CACHE_TAG_B = 203,
3135         AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A = 204,
3136         AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B = 205,
3137         AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A = 206,
3138         AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B = 207,
3139         AMDGPU_GFX_SQC_DIRTY_BIT_A = 208,
3140         AMDGPU_GFX_SQC_DIRTY_BIT_B = 209,
3141         AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0 = 210,
3142         AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1 = 211,
3143         AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A = 212,
3144         AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B = 213,
3145         AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE = 108,
3146 };
3147
3148 enum amdgpu_gfx_sq_ras_mem_id {
3149         AMDGPU_GFX_SQ_SGPR_MEM0 = 0,
3150         AMDGPU_GFX_SQ_SGPR_MEM1,
3151         AMDGPU_GFX_SQ_SGPR_MEM2,
3152         AMDGPU_GFX_SQ_SGPR_MEM3,
3153 };
3154
3155 enum amdgpu_gfx_ta_ras_mem_id {
3156         AMDGPU_GFX_TA_FS_AFIFO_RAM_LO = 1,
3157         AMDGPU_GFX_TA_FS_AFIFO_RAM_HI,
3158         AMDGPU_GFX_TA_FS_CFIFO_RAM,
3159         AMDGPU_GFX_TA_FSX_LFIFO,
3160         AMDGPU_GFX_TA_FS_DFIFO_RAM,
3161 };
3162
3163 enum amdgpu_gfx_tcc_ras_mem_id {
3164         AMDGPU_GFX_TCC_MEM1 = 1,
3165 };
3166
3167 enum amdgpu_gfx_tca_ras_mem_id {
3168         AMDGPU_GFX_TCA_MEM1 = 1,
3169 };
3170
3171 enum amdgpu_gfx_tci_ras_mem_id {
3172         AMDGPU_GFX_TCIW_MEM = 1,
3173 };
3174
3175 enum amdgpu_gfx_tcp_ras_mem_id {
3176         AMDGPU_GFX_TCP_LFIFO0 = 1,
3177         AMDGPU_GFX_TCP_SET0BANK0_RAM,
3178         AMDGPU_GFX_TCP_SET0BANK1_RAM,
3179         AMDGPU_GFX_TCP_SET0BANK2_RAM,
3180         AMDGPU_GFX_TCP_SET0BANK3_RAM,
3181         AMDGPU_GFX_TCP_SET1BANK0_RAM,
3182         AMDGPU_GFX_TCP_SET1BANK1_RAM,
3183         AMDGPU_GFX_TCP_SET1BANK2_RAM,
3184         AMDGPU_GFX_TCP_SET1BANK3_RAM,
3185         AMDGPU_GFX_TCP_SET2BANK0_RAM,
3186         AMDGPU_GFX_TCP_SET2BANK1_RAM,
3187         AMDGPU_GFX_TCP_SET2BANK2_RAM,
3188         AMDGPU_GFX_TCP_SET2BANK3_RAM,
3189         AMDGPU_GFX_TCP_SET3BANK0_RAM,
3190         AMDGPU_GFX_TCP_SET3BANK1_RAM,
3191         AMDGPU_GFX_TCP_SET3BANK2_RAM,
3192         AMDGPU_GFX_TCP_SET3BANK3_RAM,
3193         AMDGPU_GFX_TCP_VM_FIFO,
3194         AMDGPU_GFX_TCP_DB_TAGRAM0,
3195         AMDGPU_GFX_TCP_DB_TAGRAM1,
3196         AMDGPU_GFX_TCP_DB_TAGRAM2,
3197         AMDGPU_GFX_TCP_DB_TAGRAM3,
3198         AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0,
3199         AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1,
3200         AMDGPU_GFX_TCP_CMD_FIFO,
3201 };
3202
3203 enum amdgpu_gfx_td_ras_mem_id {
3204         AMDGPU_GFX_TD_UTD_CS_FIFO_MEM = 1,
3205         AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM,
3206         AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM,
3207 };
3208
3209 enum amdgpu_gfx_tcx_ras_mem_id {
3210         AMDGPU_GFX_TCX_FIFOD0 = 0,
3211         AMDGPU_GFX_TCX_FIFOD1,
3212         AMDGPU_GFX_TCX_FIFOD2,
3213         AMDGPU_GFX_TCX_FIFOD3,
3214         AMDGPU_GFX_TCX_FIFOD4,
3215         AMDGPU_GFX_TCX_FIFOD5,
3216         AMDGPU_GFX_TCX_FIFOD6,
3217         AMDGPU_GFX_TCX_FIFOD7,
3218         AMDGPU_GFX_TCX_FIFOB0,
3219         AMDGPU_GFX_TCX_FIFOB1,
3220         AMDGPU_GFX_TCX_FIFOB2,
3221         AMDGPU_GFX_TCX_FIFOB3,
3222         AMDGPU_GFX_TCX_FIFOB4,
3223         AMDGPU_GFX_TCX_FIFOB5,
3224         AMDGPU_GFX_TCX_FIFOB6,
3225         AMDGPU_GFX_TCX_FIFOB7,
3226         AMDGPU_GFX_TCX_FIFOA0,
3227         AMDGPU_GFX_TCX_FIFOA1,
3228         AMDGPU_GFX_TCX_FIFOA2,
3229         AMDGPU_GFX_TCX_FIFOA3,
3230         AMDGPU_GFX_TCX_FIFOA4,
3231         AMDGPU_GFX_TCX_FIFOA5,
3232         AMDGPU_GFX_TCX_FIFOA6,
3233         AMDGPU_GFX_TCX_FIFOA7,
3234         AMDGPU_GFX_TCX_CFIFO0,
3235         AMDGPU_GFX_TCX_CFIFO1,
3236         AMDGPU_GFX_TCX_CFIFO2,
3237         AMDGPU_GFX_TCX_CFIFO3,
3238         AMDGPU_GFX_TCX_CFIFO4,
3239         AMDGPU_GFX_TCX_CFIFO5,
3240         AMDGPU_GFX_TCX_CFIFO6,
3241         AMDGPU_GFX_TCX_CFIFO7,
3242         AMDGPU_GFX_TCX_FIFO_ACKB0,
3243         AMDGPU_GFX_TCX_FIFO_ACKB1,
3244         AMDGPU_GFX_TCX_FIFO_ACKB2,
3245         AMDGPU_GFX_TCX_FIFO_ACKB3,
3246         AMDGPU_GFX_TCX_FIFO_ACKB4,
3247         AMDGPU_GFX_TCX_FIFO_ACKB5,
3248         AMDGPU_GFX_TCX_FIFO_ACKB6,
3249         AMDGPU_GFX_TCX_FIFO_ACKB7,
3250         AMDGPU_GFX_TCX_FIFO_ACKD0,
3251         AMDGPU_GFX_TCX_FIFO_ACKD1,
3252         AMDGPU_GFX_TCX_FIFO_ACKD2,
3253         AMDGPU_GFX_TCX_FIFO_ACKD3,
3254         AMDGPU_GFX_TCX_FIFO_ACKD4,
3255         AMDGPU_GFX_TCX_FIFO_ACKD5,
3256         AMDGPU_GFX_TCX_FIFO_ACKD6,
3257         AMDGPU_GFX_TCX_FIFO_ACKD7,
3258         AMDGPU_GFX_TCX_DST_FIFOA0,
3259         AMDGPU_GFX_TCX_DST_FIFOA1,
3260         AMDGPU_GFX_TCX_DST_FIFOA2,
3261         AMDGPU_GFX_TCX_DST_FIFOA3,
3262         AMDGPU_GFX_TCX_DST_FIFOA4,
3263         AMDGPU_GFX_TCX_DST_FIFOA5,
3264         AMDGPU_GFX_TCX_DST_FIFOA6,
3265         AMDGPU_GFX_TCX_DST_FIFOA7,
3266         AMDGPU_GFX_TCX_DST_FIFOB0,
3267         AMDGPU_GFX_TCX_DST_FIFOB1,
3268         AMDGPU_GFX_TCX_DST_FIFOB2,
3269         AMDGPU_GFX_TCX_DST_FIFOB3,
3270         AMDGPU_GFX_TCX_DST_FIFOB4,
3271         AMDGPU_GFX_TCX_DST_FIFOB5,
3272         AMDGPU_GFX_TCX_DST_FIFOB6,
3273         AMDGPU_GFX_TCX_DST_FIFOB7,
3274         AMDGPU_GFX_TCX_DST_FIFOD0,
3275         AMDGPU_GFX_TCX_DST_FIFOD1,
3276         AMDGPU_GFX_TCX_DST_FIFOD2,
3277         AMDGPU_GFX_TCX_DST_FIFOD3,
3278         AMDGPU_GFX_TCX_DST_FIFOD4,
3279         AMDGPU_GFX_TCX_DST_FIFOD5,
3280         AMDGPU_GFX_TCX_DST_FIFOD6,
3281         AMDGPU_GFX_TCX_DST_FIFOD7,
3282         AMDGPU_GFX_TCX_DST_FIFO_ACKB0,
3283         AMDGPU_GFX_TCX_DST_FIFO_ACKB1,
3284         AMDGPU_GFX_TCX_DST_FIFO_ACKB2,
3285         AMDGPU_GFX_TCX_DST_FIFO_ACKB3,
3286         AMDGPU_GFX_TCX_DST_FIFO_ACKB4,
3287         AMDGPU_GFX_TCX_DST_FIFO_ACKB5,
3288         AMDGPU_GFX_TCX_DST_FIFO_ACKB6,
3289         AMDGPU_GFX_TCX_DST_FIFO_ACKB7,
3290         AMDGPU_GFX_TCX_DST_FIFO_ACKD0,
3291         AMDGPU_GFX_TCX_DST_FIFO_ACKD1,
3292         AMDGPU_GFX_TCX_DST_FIFO_ACKD2,
3293         AMDGPU_GFX_TCX_DST_FIFO_ACKD3,
3294         AMDGPU_GFX_TCX_DST_FIFO_ACKD4,
3295         AMDGPU_GFX_TCX_DST_FIFO_ACKD5,
3296         AMDGPU_GFX_TCX_DST_FIFO_ACKD6,
3297         AMDGPU_GFX_TCX_DST_FIFO_ACKD7,
3298 };
3299
3300 enum amdgpu_gfx_atc_l2_ras_mem_id {
3301         AMDGPU_GFX_ATC_L2_MEM0 = 0,
3302 };
3303
3304 enum amdgpu_gfx_utcl2_ras_mem_id {
3305         AMDGPU_GFX_UTCL2_MEM0 = 0,
3306 };
3307
3308 enum amdgpu_gfx_vml2_ras_mem_id {
3309         AMDGPU_GFX_VML2_MEM0 = 0,
3310 };
3311
3312 enum amdgpu_gfx_vml2_walker_ras_mem_id {
3313         AMDGPU_GFX_VML2_WALKER_MEM0 = 0,
3314 };
3315
3316 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_cp_mem_list[] = {
3317         {AMDGPU_GFX_CP_MEM1, "CP_MEM1"},
3318         {AMDGPU_GFX_CP_MEM2, "CP_MEM2"},
3319         {AMDGPU_GFX_CP_MEM3, "CP_MEM3"},
3320         {AMDGPU_GFX_CP_MEM4, "CP_MEM4"},
3321         {AMDGPU_GFX_CP_MEM5, "CP_MEM5"},
3322 };
3323
3324 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcea_mem_list[] = {
3325         {AMDGPU_GFX_GCEA_IOWR_CMDMEM, "GCEA_IOWR_CMDMEM"},
3326         {AMDGPU_GFX_GCEA_IORD_CMDMEM, "GCEA_IORD_CMDMEM"},
3327         {AMDGPU_GFX_GCEA_GMIWR_CMDMEM, "GCEA_GMIWR_CMDMEM"},
3328         {AMDGPU_GFX_GCEA_GMIRD_CMDMEM, "GCEA_GMIRD_CMDMEM"},
3329         {AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, "GCEA_DRAMWR_CMDMEM"},
3330         {AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, "GCEA_DRAMRD_CMDMEM"},
3331         {AMDGPU_GFX_GCEA_MAM_DMEM0, "GCEA_MAM_DMEM0"},
3332         {AMDGPU_GFX_GCEA_MAM_DMEM1, "GCEA_MAM_DMEM1"},
3333         {AMDGPU_GFX_GCEA_MAM_DMEM2, "GCEA_MAM_DMEM2"},
3334         {AMDGPU_GFX_GCEA_MAM_DMEM3, "GCEA_MAM_DMEM3"},
3335         {AMDGPU_GFX_GCEA_MAM_AMEM0, "GCEA_MAM_AMEM0"},
3336         {AMDGPU_GFX_GCEA_MAM_AMEM1, "GCEA_MAM_AMEM1"},
3337         {AMDGPU_GFX_GCEA_MAM_AMEM2, "GCEA_MAM_AMEM2"},
3338         {AMDGPU_GFX_GCEA_MAM_AMEM3, "GCEA_MAM_AMEM3"},
3339         {AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, "GCEA_MAM_AFLUSH_BUFFER"},
3340         {AMDGPU_GFX_GCEA_WRET_TAGMEM, "GCEA_WRET_TAGMEM"},
3341         {AMDGPU_GFX_GCEA_RRET_TAGMEM, "GCEA_RRET_TAGMEM"},
3342         {AMDGPU_GFX_GCEA_IOWR_DATAMEM, "GCEA_IOWR_DATAMEM"},
3343         {AMDGPU_GFX_GCEA_GMIWR_DATAMEM, "GCEA_GMIWR_DATAMEM"},
3344         {AMDGPU_GFX_GCEA_DRAM_DATAMEM, "GCEA_DRAM_DATAMEM"},
3345 };
3346
3347 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gc_cane_mem_list[] = {
3348         {AMDGPU_GFX_GC_CANE_MEM0, "GC_CANE_MEM0"},
3349 };
3350
3351 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcutcl2_mem_list[] = {
3352         {AMDGPU_GFX_GCUTCL2_MEM2P512X95, "GCUTCL2_MEM2P512X95"},
3353 };
3354
3355 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gds_mem_list[] = {
3356         {AMDGPU_GFX_GDS_MEM0, "GDS_MEM"},
3357 };
3358
3359 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_lds_mem_list[] = {
3360         {AMDGPU_GFX_LDS_BANK0, "LDS_BANK0"},
3361         {AMDGPU_GFX_LDS_BANK1, "LDS_BANK1"},
3362         {AMDGPU_GFX_LDS_BANK2, "LDS_BANK2"},
3363         {AMDGPU_GFX_LDS_BANK3, "LDS_BANK3"},
3364         {AMDGPU_GFX_LDS_BANK4, "LDS_BANK4"},
3365         {AMDGPU_GFX_LDS_BANK5, "LDS_BANK5"},
3366         {AMDGPU_GFX_LDS_BANK6, "LDS_BANK6"},
3367         {AMDGPU_GFX_LDS_BANK7, "LDS_BANK7"},
3368         {AMDGPU_GFX_LDS_BANK8, "LDS_BANK8"},
3369         {AMDGPU_GFX_LDS_BANK9, "LDS_BANK9"},
3370         {AMDGPU_GFX_LDS_BANK10, "LDS_BANK10"},
3371         {AMDGPU_GFX_LDS_BANK11, "LDS_BANK11"},
3372         {AMDGPU_GFX_LDS_BANK12, "LDS_BANK12"},
3373         {AMDGPU_GFX_LDS_BANK13, "LDS_BANK13"},
3374         {AMDGPU_GFX_LDS_BANK14, "LDS_BANK14"},
3375         {AMDGPU_GFX_LDS_BANK15, "LDS_BANK15"},
3376         {AMDGPU_GFX_LDS_BANK16, "LDS_BANK16"},
3377         {AMDGPU_GFX_LDS_BANK17, "LDS_BANK17"},
3378         {AMDGPU_GFX_LDS_BANK18, "LDS_BANK18"},
3379         {AMDGPU_GFX_LDS_BANK19, "LDS_BANK19"},
3380         {AMDGPU_GFX_LDS_BANK20, "LDS_BANK20"},
3381         {AMDGPU_GFX_LDS_BANK21, "LDS_BANK21"},
3382         {AMDGPU_GFX_LDS_BANK22, "LDS_BANK22"},
3383         {AMDGPU_GFX_LDS_BANK23, "LDS_BANK23"},
3384         {AMDGPU_GFX_LDS_BANK24, "LDS_BANK24"},
3385         {AMDGPU_GFX_LDS_BANK25, "LDS_BANK25"},
3386         {AMDGPU_GFX_LDS_BANK26, "LDS_BANK26"},
3387         {AMDGPU_GFX_LDS_BANK27, "LDS_BANK27"},
3388         {AMDGPU_GFX_LDS_BANK28, "LDS_BANK28"},
3389         {AMDGPU_GFX_LDS_BANK29, "LDS_BANK29"},
3390         {AMDGPU_GFX_LDS_BANK30, "LDS_BANK30"},
3391         {AMDGPU_GFX_LDS_BANK31, "LDS_BANK31"},
3392         {AMDGPU_GFX_LDS_SP_BUFFER_A, "LDS_SP_BUFFER_A"},
3393         {AMDGPU_GFX_LDS_SP_BUFFER_B, "LDS_SP_BUFFER_B"},
3394 };
3395
3396 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_rlc_mem_list[] = {
3397         {AMDGPU_GFX_RLC_GPMF32, "RLC_GPMF32"},
3398         {AMDGPU_GFX_RLC_RLCVF32, "RLC_RLCVF32"},
3399         {AMDGPU_GFX_RLC_SCRATCH, "RLC_SCRATCH"},
3400         {AMDGPU_GFX_RLC_SRM_ARAM, "RLC_SRM_ARAM"},
3401         {AMDGPU_GFX_RLC_SRM_DRAM, "RLC_SRM_DRAM"},
3402         {AMDGPU_GFX_RLC_TCTAG, "RLC_TCTAG"},
3403         {AMDGPU_GFX_RLC_SPM_SE, "RLC_SPM_SE"},
3404         {AMDGPU_GFX_RLC_SPM_GRBMT, "RLC_SPM_GRBMT"},
3405 };
3406
3407 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sp_mem_list[] = {
3408         {AMDGPU_GFX_SP_SIMDID0, "SP_SIMDID0"},
3409 };
3410
3411 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_spi_mem_list[] = {
3412         {AMDGPU_GFX_SPI_MEM0, "SPI_MEM0"},
3413         {AMDGPU_GFX_SPI_MEM1, "SPI_MEM1"},
3414         {AMDGPU_GFX_SPI_MEM2, "SPI_MEM2"},
3415         {AMDGPU_GFX_SPI_MEM3, "SPI_MEM3"},
3416 };
3417
3418 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sqc_mem_list[] = {
3419         {AMDGPU_GFX_SQC_INST_CACHE_A, "SQC_INST_CACHE_A"},
3420         {AMDGPU_GFX_SQC_INST_CACHE_B, "SQC_INST_CACHE_B"},
3421         {AMDGPU_GFX_SQC_INST_CACHE_TAG_A, "SQC_INST_CACHE_TAG_A"},
3422         {AMDGPU_GFX_SQC_INST_CACHE_TAG_B, "SQC_INST_CACHE_TAG_B"},
3423         {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A, "SQC_INST_CACHE_MISS_FIFO_A"},
3424         {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B, "SQC_INST_CACHE_MISS_FIFO_B"},
3425         {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A, "SQC_INST_CACHE_GATCL1_MISS_FIFO_A"},
3426         {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B, "SQC_INST_CACHE_GATCL1_MISS_FIFO_B"},
3427         {AMDGPU_GFX_SQC_DATA_CACHE_A, "SQC_DATA_CACHE_A"},
3428         {AMDGPU_GFX_SQC_DATA_CACHE_B, "SQC_DATA_CACHE_B"},
3429         {AMDGPU_GFX_SQC_DATA_CACHE_TAG_A, "SQC_DATA_CACHE_TAG_A"},
3430         {AMDGPU_GFX_SQC_DATA_CACHE_TAG_B, "SQC_DATA_CACHE_TAG_B"},
3431         {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A, "SQC_DATA_CACHE_MISS_FIFO_A"},
3432         {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B, "SQC_DATA_CACHE_MISS_FIFO_B"},
3433         {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A, "SQC_DATA_CACHE_HIT_FIFO_A"},
3434         {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B, "SQC_DATA_CACHE_HIT_FIFO_B"},
3435         {AMDGPU_GFX_SQC_DIRTY_BIT_A, "SQC_DIRTY_BIT_A"},
3436         {AMDGPU_GFX_SQC_DIRTY_BIT_B, "SQC_DIRTY_BIT_B"},
3437         {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0, "SQC_WRITE_DATA_BUFFER_CU0"},
3438         {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1, "SQC_WRITE_DATA_BUFFER_CU1"},
3439         {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A"},
3440         {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B"},
3441         {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE, "SQC_UTCL1_MISS_LFIFO_INST_CACHE"},
3442 };
3443
3444 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sq_mem_list[] = {
3445         {AMDGPU_GFX_SQ_SGPR_MEM0, "SQ_SGPR_MEM0"},
3446         {AMDGPU_GFX_SQ_SGPR_MEM1, "SQ_SGPR_MEM1"},
3447         {AMDGPU_GFX_SQ_SGPR_MEM2, "SQ_SGPR_MEM2"},
3448         {AMDGPU_GFX_SQ_SGPR_MEM3, "SQ_SGPR_MEM3"},
3449 };
3450
3451 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_ta_mem_list[] = {
3452         {AMDGPU_GFX_TA_FS_AFIFO_RAM_LO, "TA_FS_AFIFO_RAM_LO"},
3453         {AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, "TA_FS_AFIFO_RAM_HI"},
3454         {AMDGPU_GFX_TA_FS_CFIFO_RAM, "TA_FS_CFIFO_RAM"},
3455         {AMDGPU_GFX_TA_FSX_LFIFO, "TA_FSX_LFIFO"},
3456         {AMDGPU_GFX_TA_FS_DFIFO_RAM, "TA_FS_DFIFO_RAM"},
3457 };
3458
3459 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcc_mem_list[] = {
3460         {AMDGPU_GFX_TCC_MEM1, "TCC_MEM1"},
3461 };
3462
3463 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tca_mem_list[] = {
3464         {AMDGPU_GFX_TCA_MEM1, "TCA_MEM1"},
3465 };
3466
3467 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tci_mem_list[] = {
3468         {AMDGPU_GFX_TCIW_MEM, "TCIW_MEM"},
3469 };
3470
3471 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcp_mem_list[] = {
3472         {AMDGPU_GFX_TCP_LFIFO0, "TCP_LFIFO0"},
3473         {AMDGPU_GFX_TCP_SET0BANK0_RAM, "TCP_SET0BANK0_RAM"},
3474         {AMDGPU_GFX_TCP_SET0BANK1_RAM, "TCP_SET0BANK1_RAM"},
3475         {AMDGPU_GFX_TCP_SET0BANK2_RAM, "TCP_SET0BANK2_RAM"},
3476         {AMDGPU_GFX_TCP_SET0BANK3_RAM, "TCP_SET0BANK3_RAM"},
3477         {AMDGPU_GFX_TCP_SET1BANK0_RAM, "TCP_SET1BANK0_RAM"},
3478         {AMDGPU_GFX_TCP_SET1BANK1_RAM, "TCP_SET1BANK1_RAM"},
3479         {AMDGPU_GFX_TCP_SET1BANK2_RAM, "TCP_SET1BANK2_RAM"},
3480         {AMDGPU_GFX_TCP_SET1BANK3_RAM, "TCP_SET1BANK3_RAM"},
3481         {AMDGPU_GFX_TCP_SET2BANK0_RAM, "TCP_SET2BANK0_RAM"},
3482         {AMDGPU_GFX_TCP_SET2BANK1_RAM, "TCP_SET2BANK1_RAM"},
3483         {AMDGPU_GFX_TCP_SET2BANK2_RAM, "TCP_SET2BANK2_RAM"},
3484         {AMDGPU_GFX_TCP_SET2BANK3_RAM, "TCP_SET2BANK3_RAM"},
3485         {AMDGPU_GFX_TCP_SET3BANK0_RAM, "TCP_SET3BANK0_RAM"},
3486         {AMDGPU_GFX_TCP_SET3BANK1_RAM, "TCP_SET3BANK1_RAM"},
3487         {AMDGPU_GFX_TCP_SET3BANK2_RAM, "TCP_SET3BANK2_RAM"},
3488         {AMDGPU_GFX_TCP_SET3BANK3_RAM, "TCP_SET3BANK3_RAM"},
3489         {AMDGPU_GFX_TCP_VM_FIFO, "TCP_VM_FIFO"},
3490         {AMDGPU_GFX_TCP_DB_TAGRAM0, "TCP_DB_TAGRAM0"},
3491         {AMDGPU_GFX_TCP_DB_TAGRAM1, "TCP_DB_TAGRAM1"},
3492         {AMDGPU_GFX_TCP_DB_TAGRAM2, "TCP_DB_TAGRAM2"},
3493         {AMDGPU_GFX_TCP_DB_TAGRAM3, "TCP_DB_TAGRAM3"},
3494         {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, "TCP_UTCL1_LFIFO_PROBE0"},
3495         {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, "TCP_UTCL1_LFIFO_PROBE1"},
3496         {AMDGPU_GFX_TCP_CMD_FIFO, "TCP_CMD_FIFO"},
3497 };
3498
3499 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_td_mem_list[] = {
3500         {AMDGPU_GFX_TD_UTD_CS_FIFO_MEM, "TD_UTD_CS_FIFO_MEM"},
3501         {AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, "TD_UTD_SS_FIFO_LO_MEM"},
3502         {AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, "TD_UTD_SS_FIFO_HI_MEM"},
3503 };
3504
3505 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcx_mem_list[] = {
3506         {AMDGPU_GFX_TCX_FIFOD0, "TCX_FIFOD0"},
3507         {AMDGPU_GFX_TCX_FIFOD1, "TCX_FIFOD1"},
3508         {AMDGPU_GFX_TCX_FIFOD2, "TCX_FIFOD2"},
3509         {AMDGPU_GFX_TCX_FIFOD3, "TCX_FIFOD3"},
3510         {AMDGPU_GFX_TCX_FIFOD4, "TCX_FIFOD4"},
3511         {AMDGPU_GFX_TCX_FIFOD5, "TCX_FIFOD5"},
3512         {AMDGPU_GFX_TCX_FIFOD6, "TCX_FIFOD6"},
3513         {AMDGPU_GFX_TCX_FIFOD7, "TCX_FIFOD7"},
3514         {AMDGPU_GFX_TCX_FIFOB0, "TCX_FIFOB0"},
3515         {AMDGPU_GFX_TCX_FIFOB1, "TCX_FIFOB1"},
3516         {AMDGPU_GFX_TCX_FIFOB2, "TCX_FIFOB2"},
3517         {AMDGPU_GFX_TCX_FIFOB3, "TCX_FIFOB3"},
3518         {AMDGPU_GFX_TCX_FIFOB4, "TCX_FIFOB4"},
3519         {AMDGPU_GFX_TCX_FIFOB5, "TCX_FIFOB5"},
3520         {AMDGPU_GFX_TCX_FIFOB6, "TCX_FIFOB6"},
3521         {AMDGPU_GFX_TCX_FIFOB7, "TCX_FIFOB7"},
3522         {AMDGPU_GFX_TCX_FIFOA0, "TCX_FIFOA0"},
3523         {AMDGPU_GFX_TCX_FIFOA1, "TCX_FIFOA1"},
3524         {AMDGPU_GFX_TCX_FIFOA2, "TCX_FIFOA2"},
3525         {AMDGPU_GFX_TCX_FIFOA3, "TCX_FIFOA3"},
3526         {AMDGPU_GFX_TCX_FIFOA4, "TCX_FIFOA4"},
3527         {AMDGPU_GFX_TCX_FIFOA5, "TCX_FIFOA5"},
3528         {AMDGPU_GFX_TCX_FIFOA6, "TCX_FIFOA6"},
3529         {AMDGPU_GFX_TCX_FIFOA7, "TCX_FIFOA7"},
3530         {AMDGPU_GFX_TCX_CFIFO0, "TCX_CFIFO0"},
3531         {AMDGPU_GFX_TCX_CFIFO1, "TCX_CFIFO1"},
3532         {AMDGPU_GFX_TCX_CFIFO2, "TCX_CFIFO2"},
3533         {AMDGPU_GFX_TCX_CFIFO3, "TCX_CFIFO3"},
3534         {AMDGPU_GFX_TCX_CFIFO4, "TCX_CFIFO4"},
3535         {AMDGPU_GFX_TCX_CFIFO5, "TCX_CFIFO5"},
3536         {AMDGPU_GFX_TCX_CFIFO6, "TCX_CFIFO6"},
3537         {AMDGPU_GFX_TCX_CFIFO7, "TCX_CFIFO7"},
3538         {AMDGPU_GFX_TCX_FIFO_ACKB0, "TCX_FIFO_ACKB0"},
3539         {AMDGPU_GFX_TCX_FIFO_ACKB1, "TCX_FIFO_ACKB1"},
3540         {AMDGPU_GFX_TCX_FIFO_ACKB2, "TCX_FIFO_ACKB2"},
3541         {AMDGPU_GFX_TCX_FIFO_ACKB3, "TCX_FIFO_ACKB3"},
3542         {AMDGPU_GFX_TCX_FIFO_ACKB4, "TCX_FIFO_ACKB4"},
3543         {AMDGPU_GFX_TCX_FIFO_ACKB5, "TCX_FIFO_ACKB5"},
3544         {AMDGPU_GFX_TCX_FIFO_ACKB6, "TCX_FIFO_ACKB6"},
3545         {AMDGPU_GFX_TCX_FIFO_ACKB7, "TCX_FIFO_ACKB7"},
3546         {AMDGPU_GFX_TCX_FIFO_ACKD0, "TCX_FIFO_ACKD0"},
3547         {AMDGPU_GFX_TCX_FIFO_ACKD1, "TCX_FIFO_ACKD1"},
3548         {AMDGPU_GFX_TCX_FIFO_ACKD2, "TCX_FIFO_ACKD2"},
3549         {AMDGPU_GFX_TCX_FIFO_ACKD3, "TCX_FIFO_ACKD3"},
3550         {AMDGPU_GFX_TCX_FIFO_ACKD4, "TCX_FIFO_ACKD4"},
3551         {AMDGPU_GFX_TCX_FIFO_ACKD5, "TCX_FIFO_ACKD5"},
3552         {AMDGPU_GFX_TCX_FIFO_ACKD6, "TCX_FIFO_ACKD6"},
3553         {AMDGPU_GFX_TCX_FIFO_ACKD7, "TCX_FIFO_ACKD7"},
3554         {AMDGPU_GFX_TCX_DST_FIFOA0, "TCX_DST_FIFOA0"},
3555         {AMDGPU_GFX_TCX_DST_FIFOA1, "TCX_DST_FIFOA1"},
3556         {AMDGPU_GFX_TCX_DST_FIFOA2, "TCX_DST_FIFOA2"},
3557         {AMDGPU_GFX_TCX_DST_FIFOA3, "TCX_DST_FIFOA3"},
3558         {AMDGPU_GFX_TCX_DST_FIFOA4, "TCX_DST_FIFOA4"},
3559         {AMDGPU_GFX_TCX_DST_FIFOA5, "TCX_DST_FIFOA5"},
3560         {AMDGPU_GFX_TCX_DST_FIFOA6, "TCX_DST_FIFOA6"},
3561         {AMDGPU_GFX_TCX_DST_FIFOA7, "TCX_DST_FIFOA7"},
3562         {AMDGPU_GFX_TCX_DST_FIFOB0, "TCX_DST_FIFOB0"},
3563         {AMDGPU_GFX_TCX_DST_FIFOB1, "TCX_DST_FIFOB1"},
3564         {AMDGPU_GFX_TCX_DST_FIFOB2, "TCX_DST_FIFOB2"},
3565         {AMDGPU_GFX_TCX_DST_FIFOB3, "TCX_DST_FIFOB3"},
3566         {AMDGPU_GFX_TCX_DST_FIFOB4, "TCX_DST_FIFOB4"},
3567         {AMDGPU_GFX_TCX_DST_FIFOB5, "TCX_DST_FIFOB5"},
3568         {AMDGPU_GFX_TCX_DST_FIFOB6, "TCX_DST_FIFOB6"},
3569         {AMDGPU_GFX_TCX_DST_FIFOB7, "TCX_DST_FIFOB7"},
3570         {AMDGPU_GFX_TCX_DST_FIFOD0, "TCX_DST_FIFOD0"},
3571         {AMDGPU_GFX_TCX_DST_FIFOD1, "TCX_DST_FIFOD1"},
3572         {AMDGPU_GFX_TCX_DST_FIFOD2, "TCX_DST_FIFOD2"},
3573         {AMDGPU_GFX_TCX_DST_FIFOD3, "TCX_DST_FIFOD3"},
3574         {AMDGPU_GFX_TCX_DST_FIFOD4, "TCX_DST_FIFOD4"},
3575         {AMDGPU_GFX_TCX_DST_FIFOD5, "TCX_DST_FIFOD5"},
3576         {AMDGPU_GFX_TCX_DST_FIFOD6, "TCX_DST_FIFOD6"},
3577         {AMDGPU_GFX_TCX_DST_FIFOD7, "TCX_DST_FIFOD7"},
3578         {AMDGPU_GFX_TCX_DST_FIFO_ACKB0, "TCX_DST_FIFO_ACKB0"},
3579         {AMDGPU_GFX_TCX_DST_FIFO_ACKB1, "TCX_DST_FIFO_ACKB1"},
3580         {AMDGPU_GFX_TCX_DST_FIFO_ACKB2, "TCX_DST_FIFO_ACKB2"},
3581         {AMDGPU_GFX_TCX_DST_FIFO_ACKB3, "TCX_DST_FIFO_ACKB3"},
3582         {AMDGPU_GFX_TCX_DST_FIFO_ACKB4, "TCX_DST_FIFO_ACKB4"},
3583         {AMDGPU_GFX_TCX_DST_FIFO_ACKB5, "TCX_DST_FIFO_ACKB5"},
3584         {AMDGPU_GFX_TCX_DST_FIFO_ACKB6, "TCX_DST_FIFO_ACKB6"},
3585         {AMDGPU_GFX_TCX_DST_FIFO_ACKB7, "TCX_DST_FIFO_ACKB7"},
3586         {AMDGPU_GFX_TCX_DST_FIFO_ACKD0, "TCX_DST_FIFO_ACKD0"},
3587         {AMDGPU_GFX_TCX_DST_FIFO_ACKD1, "TCX_DST_FIFO_ACKD1"},
3588         {AMDGPU_GFX_TCX_DST_FIFO_ACKD2, "TCX_DST_FIFO_ACKD2"},
3589         {AMDGPU_GFX_TCX_DST_FIFO_ACKD3, "TCX_DST_FIFO_ACKD3"},
3590         {AMDGPU_GFX_TCX_DST_FIFO_ACKD4, "TCX_DST_FIFO_ACKD4"},
3591         {AMDGPU_GFX_TCX_DST_FIFO_ACKD5, "TCX_DST_FIFO_ACKD5"},
3592         {AMDGPU_GFX_TCX_DST_FIFO_ACKD6, "TCX_DST_FIFO_ACKD6"},
3593         {AMDGPU_GFX_TCX_DST_FIFO_ACKD7, "TCX_DST_FIFO_ACKD7"},
3594 };
3595
3596 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_atc_l2_mem_list[] = {
3597         {AMDGPU_GFX_ATC_L2_MEM, "ATC_L2_MEM"},
3598 };
3599
3600 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_utcl2_mem_list[] = {
3601         {AMDGPU_GFX_UTCL2_MEM, "UTCL2_MEM"},
3602 };
3603
3604 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_mem_list[] = {
3605         {AMDGPU_GFX_VML2_MEM, "VML2_MEM"},
3606 };
3607
3608 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_walker_mem_list[] = {
3609         {AMDGPU_GFX_VML2_WALKER_MEM, "VML2_WALKER_MEM"},
3610 };
3611
3612 static const struct amdgpu_gfx_ras_mem_id_entry gfx_v9_4_3_ras_mem_list_array[AMDGPU_GFX_MEM_TYPE_NUM] = {
3613         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_cp_mem_list)
3614         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcea_mem_list)
3615         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gc_cane_mem_list)
3616         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcutcl2_mem_list)
3617         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gds_mem_list)
3618         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_lds_mem_list)
3619         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_rlc_mem_list)
3620         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sp_mem_list)
3621         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_spi_mem_list)
3622         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sqc_mem_list)
3623         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sq_mem_list)
3624         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_ta_mem_list)
3625         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcc_mem_list)
3626         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tca_mem_list)
3627         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tci_mem_list)
3628         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcp_mem_list)
3629         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_td_mem_list)
3630         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcx_mem_list)
3631         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_atc_l2_mem_list)
3632         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_utcl2_mem_list)
3633         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_mem_list)
3634         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_walker_mem_list)
3635 };
3636
3637 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ce_reg_list[] = {
3638         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_CE_ERR_STATUS_LOW, regRLC_CE_ERR_STATUS_HIGH),
3639             1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"},
3640             AMDGPU_GFX_RLC_MEM, 1},
3641         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_CE_ERR_STATUS_LO, regCPC_CE_ERR_STATUS_HI),
3642             1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"},
3643             AMDGPU_GFX_CP_MEM, 1},
3644         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_CE_ERR_STATUS_LO, regCPF_CE_ERR_STATUS_HI),
3645             1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"},
3646             AMDGPU_GFX_CP_MEM, 1},
3647         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_CE_ERR_STATUS_LO, regCPG_CE_ERR_STATUS_HI),
3648             1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"},
3649             AMDGPU_GFX_CP_MEM, 1},
3650         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_CE_ERR_STATUS_LO, regGDS_CE_ERR_STATUS_HI),
3651             1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"},
3652             AMDGPU_GFX_GDS_MEM, 1},
3653         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_CE_ERR_STATUS_LO, regGC_CANE_CE_ERR_STATUS_HI),
3654             1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"},
3655             AMDGPU_GFX_GC_CANE_MEM, 1},
3656         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_CE_ERR_STATUS_LO, regSPI_CE_ERR_STATUS_HI),
3657             1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"},
3658             AMDGPU_GFX_SPI_MEM, 8},
3659         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_CE_ERR_STATUS_LO, regSP0_CE_ERR_STATUS_HI),
3660             10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"},
3661             AMDGPU_GFX_SP_MEM, 1},
3662         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_CE_ERR_STATUS_LO, regSP1_CE_ERR_STATUS_HI),
3663             10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"},
3664             AMDGPU_GFX_SP_MEM, 1},
3665         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_CE_ERR_STATUS_LO, regSQ_CE_ERR_STATUS_HI),
3666             10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"},
3667             AMDGPU_GFX_SQ_MEM, 8},
3668         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_CE_EDC_LO, regSQC_CE_EDC_HI),
3669             5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"},
3670             AMDGPU_GFX_SQC_MEM, 8},
3671         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_CE_ERR_STATUS_LO, regTCX_CE_ERR_STATUS_HI),
3672             2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"},
3673             AMDGPU_GFX_TCX_MEM, 1},
3674         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_CE_ERR_STATUS_LO, regTCC_CE_ERR_STATUS_HI),
3675             16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"},
3676             AMDGPU_GFX_TCC_MEM, 1},
3677         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_CE_EDC_LO, regTA_CE_EDC_HI),
3678             10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"},
3679             AMDGPU_GFX_TA_MEM, 8},
3680         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_CE_EDC_LO_REG, regTCI_CE_EDC_HI_REG),
3681             31, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"},
3682             AMDGPU_GFX_TCI_MEM, 1},
3683         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_CE_EDC_LO_REG, regTCP_CE_EDC_HI_REG),
3684             10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"},
3685             AMDGPU_GFX_TCP_MEM, 8},
3686         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_CE_EDC_LO, regTD_CE_EDC_HI),
3687             10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"},
3688             AMDGPU_GFX_TD_MEM, 8},
3689         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_CE_ERR_STATUS_LO, regGCEA_CE_ERR_STATUS_HI),
3690             16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"},
3691             AMDGPU_GFX_GCEA_MEM, 1},
3692         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_CE_ERR_STATUS_LO, regLDS_CE_ERR_STATUS_HI),
3693             10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"},
3694             AMDGPU_GFX_LDS_MEM, 1},
3695 };
3696
3697 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ue_reg_list[] = {
3698         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_UE_ERR_STATUS_LOW, regRLC_UE_ERR_STATUS_HIGH),
3699             1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"},
3700             AMDGPU_GFX_RLC_MEM, 1},
3701         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_UE_ERR_STATUS_LO, regCPC_UE_ERR_STATUS_HI),
3702             1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"},
3703             AMDGPU_GFX_CP_MEM, 1},
3704         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_UE_ERR_STATUS_LO, regCPF_UE_ERR_STATUS_HI),
3705             1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"},
3706             AMDGPU_GFX_CP_MEM, 1},
3707         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_UE_ERR_STATUS_LO, regCPG_UE_ERR_STATUS_HI),
3708             1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"},
3709             AMDGPU_GFX_CP_MEM, 1},
3710         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_UE_ERR_STATUS_LO, regGDS_UE_ERR_STATUS_HI),
3711             1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"},
3712             AMDGPU_GFX_GDS_MEM, 1},
3713         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_UE_ERR_STATUS_LO, regGC_CANE_UE_ERR_STATUS_HI),
3714             1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"},
3715             AMDGPU_GFX_GC_CANE_MEM, 1},
3716         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_UE_ERR_STATUS_LO, regSPI_UE_ERR_STATUS_HI),
3717             1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"},
3718             AMDGPU_GFX_SPI_MEM, 8},
3719         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_UE_ERR_STATUS_LO, regSP0_UE_ERR_STATUS_HI),
3720             10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"},
3721             AMDGPU_GFX_SP_MEM, 1},
3722         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_UE_ERR_STATUS_LO, regSP1_UE_ERR_STATUS_HI),
3723             10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"},
3724             AMDGPU_GFX_SP_MEM, 1},
3725         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_UE_ERR_STATUS_LO, regSQ_UE_ERR_STATUS_HI),
3726             10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"},
3727             AMDGPU_GFX_SQ_MEM, 8},
3728         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_UE_EDC_LO, regSQC_UE_EDC_HI),
3729             5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"},
3730             AMDGPU_GFX_SQC_MEM, 8},
3731         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_UE_ERR_STATUS_LO, regTCX_UE_ERR_STATUS_HI),
3732             2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"},
3733             AMDGPU_GFX_TCX_MEM, 1},
3734         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_UE_ERR_STATUS_LO, regTCC_UE_ERR_STATUS_HI),
3735             16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"},
3736             AMDGPU_GFX_TCC_MEM, 1},
3737         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_UE_EDC_LO, regTA_UE_EDC_HI),
3738             10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"},
3739             AMDGPU_GFX_TA_MEM, 8},
3740         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_UE_EDC_LO_REG, regTCI_UE_EDC_HI_REG),
3741             31, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"},
3742             AMDGPU_GFX_TCI_MEM, 1},
3743         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_UE_EDC_LO_REG, regTCP_UE_EDC_HI_REG),
3744             10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"},
3745             AMDGPU_GFX_TCP_MEM, 8},
3746         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_UE_EDC_LO, regTD_UE_EDC_HI),
3747             10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"},
3748             AMDGPU_GFX_TD_MEM, 8},
3749         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCA_UE_ERR_STATUS_LO, regTCA_UE_ERR_STATUS_HI),
3750             2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCA"},
3751             AMDGPU_GFX_TCA_MEM, 1},
3752         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_UE_ERR_STATUS_LO, regGCEA_UE_ERR_STATUS_HI),
3753             16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"},
3754             AMDGPU_GFX_GCEA_MEM, 1},
3755         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_UE_ERR_STATUS_LO, regLDS_UE_ERR_STATUS_HI),
3756             10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"},
3757             AMDGPU_GFX_LDS_MEM, 1},
3758 };
3759
3760 static const struct soc15_reg_entry gfx_v9_4_3_ea_err_status_regs = {
3761         SOC15_REG_ENTRY(GC, 0, regGCEA_ERR_STATUS), 0, 1, 16
3762 };
3763
3764 static void gfx_v9_4_3_inst_query_ras_err_count(struct amdgpu_device *adev,
3765                                         void *ras_error_status, int xcc_id)
3766 {
3767         struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
3768         unsigned long ce_count = 0, ue_count = 0;
3769         uint32_t i, j, k;
3770
3771         mutex_lock(&adev->grbm_idx_mutex);
3772
3773         for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) {
3774                 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) {
3775                         for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) {
3776                                 /* no need to select if instance number is 1 */
3777                                 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 ||
3778                                     gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1)
3779                                         gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id);
3780
3781                                 amdgpu_ras_inst_query_ras_error_count(adev,
3782                                         &(gfx_v9_4_3_ce_reg_list[i].reg_entry),
3783                                         1,
3784                                         gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].mem_id_ent,
3785                                         gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].size,
3786                                         GET_INST(GC, xcc_id),
3787                                         AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE,
3788                                         &ce_count);
3789
3790                                 amdgpu_ras_inst_query_ras_error_count(adev,
3791                                         &(gfx_v9_4_3_ue_reg_list[i].reg_entry),
3792                                         1,
3793                                         gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent,
3794                                         gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size,
3795                                         GET_INST(GC, xcc_id),
3796                                         AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
3797                                         &ue_count);
3798                         }
3799                 }
3800         }
3801
3802         gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
3803                         xcc_id);
3804         mutex_unlock(&adev->grbm_idx_mutex);
3805
3806         /* the caller should make sure initialize value of
3807          * err_data->ue_count and err_data->ce_count
3808          */
3809         err_data->ce_count += ce_count;
3810         err_data->ue_count += ue_count;
3811 }
3812
3813 static void gfx_v9_4_3_inst_reset_ras_err_count(struct amdgpu_device *adev,
3814                                         void *ras_error_status, int xcc_id)
3815 {
3816         uint32_t i, j, k;
3817
3818         mutex_lock(&adev->grbm_idx_mutex);
3819
3820         for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) {
3821                 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) {
3822                         for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) {
3823                                 /* no need to select if instance number is 1 */
3824                                 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 ||
3825                                     gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1)
3826                                         gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id);
3827
3828                                 amdgpu_ras_inst_reset_ras_error_count(adev,
3829                                         &(gfx_v9_4_3_ce_reg_list[i].reg_entry),
3830                                         1,
3831                                         GET_INST(GC, xcc_id));
3832
3833                                 amdgpu_ras_inst_reset_ras_error_count(adev,
3834                                         &(gfx_v9_4_3_ue_reg_list[i].reg_entry),
3835                                         1,
3836                                         GET_INST(GC, xcc_id));
3837                         }
3838                 }
3839         }
3840
3841         gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
3842                         xcc_id);
3843         mutex_unlock(&adev->grbm_idx_mutex);
3844 }
3845
3846 static void gfx_v9_4_3_inst_query_ea_err_status(struct amdgpu_device *adev,
3847                                         int xcc_id)
3848 {
3849         uint32_t i, j;
3850         uint32_t reg_value;
3851
3852         mutex_lock(&adev->grbm_idx_mutex);
3853
3854         for (i = 0; i < gfx_v9_4_3_ea_err_status_regs.se_num; i++) {
3855                 for (j = 0; j < gfx_v9_4_3_ea_err_status_regs.instance; j++) {
3856                         gfx_v9_4_3_xcc_select_se_sh(adev, i, 0, j, xcc_id);
3857                         reg_value = RREG32_SOC15(GC, GET_INST(GC, xcc_id),
3858                                         regGCEA_ERR_STATUS);
3859                         if (REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_STATUS) ||
3860                             REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_WRRSP_STATUS) ||
3861                             REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_DATAPARITY_ERROR)) {
3862                                 dev_warn(adev->dev,
3863                                         "GCEA err detected at instance: %d, status: 0x%x!\n",
3864                                         j, reg_value);
3865                         }
3866                         /* clear after read */
3867                         reg_value = REG_SET_FIELD(reg_value, GCEA_ERR_STATUS,
3868                                                   CLEAR_ERROR_STATUS, 0x1);
3869                         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGCEA_ERR_STATUS,
3870                                         reg_value);
3871                 }
3872         }
3873
3874         gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
3875                         xcc_id);
3876         mutex_unlock(&adev->grbm_idx_mutex);
3877 }
3878
3879 static void gfx_v9_4_3_inst_query_utc_err_status(struct amdgpu_device *adev,
3880                                         int xcc_id)
3881 {
3882         uint32_t data;
3883
3884         data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regUTCL2_MEM_ECC_STATUS);
3885         if (data) {
3886                 dev_warn(adev->dev, "GFX UTCL2 Mem Ecc Status: 0x%x!\n", data);
3887                 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regUTCL2_MEM_ECC_STATUS, 0x3);
3888         }
3889
3890         data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_MEM_ECC_STATUS);
3891         if (data) {
3892                 dev_warn(adev->dev, "GFX VML2 Mem Ecc Status: 0x%x!\n", data);
3893                 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_MEM_ECC_STATUS, 0x3);
3894         }
3895
3896         data = RREG32_SOC15(GC, GET_INST(GC, xcc_id),
3897                                 regVML2_WALKER_MEM_ECC_STATUS);
3898         if (data) {
3899                 dev_warn(adev->dev, "GFX VML2 Walker Mem Ecc Status: 0x%x!\n", data);
3900                 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_WALKER_MEM_ECC_STATUS,
3901                                 0x3);
3902         }
3903 }
3904
3905 static void gfx_v9_4_3_log_cu_timeout_status(struct amdgpu_device *adev,
3906                                         uint32_t status, int xcc_id)
3907 {
3908         struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
3909         uint32_t i, simd, wave;
3910         uint32_t wave_status;
3911         uint32_t wave_pc_lo, wave_pc_hi;
3912         uint32_t wave_exec_lo, wave_exec_hi;
3913         uint32_t wave_inst_dw0, wave_inst_dw1;
3914         uint32_t wave_ib_sts;
3915
3916         for (i = 0; i < 32; i++) {
3917                 if (!((i << 1) & status))
3918                         continue;
3919
3920                 simd = i / cu_info->max_waves_per_simd;
3921                 wave = i % cu_info->max_waves_per_simd;
3922
3923                 wave_status = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS);
3924                 wave_pc_lo = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO);
3925                 wave_pc_hi = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI);
3926                 wave_exec_lo =
3927                         wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO);
3928                 wave_exec_hi =
3929                         wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI);
3930                 wave_inst_dw0 =
3931                         wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0);
3932                 wave_inst_dw1 =
3933                         wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1);
3934                 wave_ib_sts = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS);
3935
3936                 dev_info(
3937                         adev->dev,
3938                         "\t SIMD %d, Wave %d: status 0x%x, pc 0x%llx, exec 0x%llx, inst 0x%llx, ib_sts 0x%x\n",
3939                         simd, wave, wave_status,
3940                         ((uint64_t)wave_pc_hi << 32 | wave_pc_lo),
3941                         ((uint64_t)wave_exec_hi << 32 | wave_exec_lo),
3942                         ((uint64_t)wave_inst_dw1 << 32 | wave_inst_dw0),
3943                         wave_ib_sts);
3944         }
3945 }
3946
3947 static void gfx_v9_4_3_inst_query_sq_timeout_status(struct amdgpu_device *adev,
3948                                         int xcc_id)
3949 {
3950         uint32_t se_idx, sh_idx, cu_idx;
3951         uint32_t status;
3952
3953         mutex_lock(&adev->grbm_idx_mutex);
3954         for (se_idx = 0; se_idx < adev->gfx.config.max_shader_engines; se_idx++) {
3955                 for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se; sh_idx++) {
3956                         for (cu_idx = 0; cu_idx < adev->gfx.config.max_cu_per_sh; cu_idx++) {
3957                                 gfx_v9_4_3_xcc_select_se_sh(adev, se_idx, sh_idx,
3958                                                         cu_idx, xcc_id);
3959                                 status = RREG32_SOC15(GC, GET_INST(GC, xcc_id),
3960                                                       regSQ_TIMEOUT_STATUS);
3961                                 if (status != 0) {
3962                                         dev_info(
3963                                                 adev->dev,
3964                                                 "GFX Watchdog Timeout: SE %d, SH %d, CU %d\n",
3965                                                 se_idx, sh_idx, cu_idx);
3966                                         gfx_v9_4_3_log_cu_timeout_status(
3967                                                 adev, status, xcc_id);
3968                                 }
3969                                 /* clear old status */
3970                                 WREG32_SOC15(GC, GET_INST(GC, xcc_id),
3971                                                 regSQ_TIMEOUT_STATUS, 0);
3972                         }
3973                 }
3974         }
3975         gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
3976                         xcc_id);
3977         mutex_unlock(&adev->grbm_idx_mutex);
3978 }
3979
3980 static void gfx_v9_4_3_inst_query_ras_err_status(struct amdgpu_device *adev,
3981                                         void *ras_error_status, int xcc_id)
3982 {
3983         gfx_v9_4_3_inst_query_ea_err_status(adev, xcc_id);
3984         gfx_v9_4_3_inst_query_utc_err_status(adev, xcc_id);
3985         gfx_v9_4_3_inst_query_sq_timeout_status(adev, xcc_id);
3986 }
3987
3988 static void gfx_v9_4_3_inst_reset_utc_err_status(struct amdgpu_device *adev,
3989                                         int xcc_id)
3990 {
3991         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regUTCL2_MEM_ECC_STATUS, 0x3);
3992         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_MEM_ECC_STATUS, 0x3);
3993         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_WALKER_MEM_ECC_STATUS, 0x3);
3994 }
3995
3996 static void gfx_v9_4_3_inst_reset_ea_err_status(struct amdgpu_device *adev,
3997                                         int xcc_id)
3998 {
3999         uint32_t i, j;
4000         uint32_t value;
4001
4002         mutex_lock(&adev->grbm_idx_mutex);
4003         for (i = 0; i < gfx_v9_4_3_ea_err_status_regs.se_num; i++) {
4004                 for (j = 0; j < gfx_v9_4_3_ea_err_status_regs.instance; j++) {
4005                         gfx_v9_4_3_xcc_select_se_sh(adev, i, 0, j, xcc_id);
4006                         value = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGCEA_ERR_STATUS);
4007                         value = REG_SET_FIELD(value, GCEA_ERR_STATUS,
4008                                                 CLEAR_ERROR_STATUS, 0x1);
4009                         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGCEA_ERR_STATUS, value);
4010                 }
4011         }
4012         gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
4013                         xcc_id);
4014         mutex_unlock(&adev->grbm_idx_mutex);
4015 }
4016
4017 static void gfx_v9_4_3_inst_reset_sq_timeout_status(struct amdgpu_device *adev,
4018                                         int xcc_id)
4019 {
4020         uint32_t se_idx, sh_idx, cu_idx;
4021
4022         mutex_lock(&adev->grbm_idx_mutex);
4023         for (se_idx = 0; se_idx < adev->gfx.config.max_shader_engines; se_idx++) {
4024                 for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se; sh_idx++) {
4025                         for (cu_idx = 0; cu_idx < adev->gfx.config.max_cu_per_sh; cu_idx++) {
4026                                 gfx_v9_4_3_xcc_select_se_sh(adev, se_idx, sh_idx,
4027                                                         cu_idx, xcc_id);
4028                                 WREG32_SOC15(GC, GET_INST(GC, xcc_id),
4029                                                 regSQ_TIMEOUT_STATUS, 0);
4030                         }
4031                 }
4032         }
4033         gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
4034                         xcc_id);
4035         mutex_unlock(&adev->grbm_idx_mutex);
4036 }
4037
4038 static void gfx_v9_4_3_inst_reset_ras_err_status(struct amdgpu_device *adev,
4039                                         void *ras_error_status, int xcc_id)
4040 {
4041         gfx_v9_4_3_inst_reset_utc_err_status(adev, xcc_id);
4042         gfx_v9_4_3_inst_reset_ea_err_status(adev, xcc_id);
4043         gfx_v9_4_3_inst_reset_sq_timeout_status(adev, xcc_id);
4044 }
4045
4046 static void gfx_v9_4_3_query_ras_error_count(struct amdgpu_device *adev,
4047                                         void *ras_error_status)
4048 {
4049         amdgpu_gfx_ras_error_func(adev, ras_error_status,
4050                         gfx_v9_4_3_inst_query_ras_err_count);
4051 }
4052
4053 static void gfx_v9_4_3_reset_ras_error_count(struct amdgpu_device *adev)
4054 {
4055         amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_reset_ras_err_count);
4056 }
4057
4058 static void gfx_v9_4_3_query_ras_error_status(struct amdgpu_device *adev)
4059 {
4060         amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_query_ras_err_status);
4061 }
4062
4063 static void gfx_v9_4_3_reset_ras_error_status(struct amdgpu_device *adev)
4064 {
4065         amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_reset_ras_err_status);
4066 }
4067
4068 static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = {
4069         .name = "gfx_v9_4_3",
4070         .early_init = gfx_v9_4_3_early_init,
4071         .late_init = gfx_v9_4_3_late_init,
4072         .sw_init = gfx_v9_4_3_sw_init,
4073         .sw_fini = gfx_v9_4_3_sw_fini,
4074         .hw_init = gfx_v9_4_3_hw_init,
4075         .hw_fini = gfx_v9_4_3_hw_fini,
4076         .suspend = gfx_v9_4_3_suspend,
4077         .resume = gfx_v9_4_3_resume,
4078         .is_idle = gfx_v9_4_3_is_idle,
4079         .wait_for_idle = gfx_v9_4_3_wait_for_idle,
4080         .soft_reset = gfx_v9_4_3_soft_reset,
4081         .set_clockgating_state = gfx_v9_4_3_set_clockgating_state,
4082         .set_powergating_state = gfx_v9_4_3_set_powergating_state,
4083         .get_clockgating_state = gfx_v9_4_3_get_clockgating_state,
4084 };
4085
4086 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = {
4087         .type = AMDGPU_RING_TYPE_COMPUTE,
4088         .align_mask = 0xff,
4089         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4090         .support_64bit_ptrs = true,
4091         .get_rptr = gfx_v9_4_3_ring_get_rptr_compute,
4092         .get_wptr = gfx_v9_4_3_ring_get_wptr_compute,
4093         .set_wptr = gfx_v9_4_3_ring_set_wptr_compute,
4094         .emit_frame_size =
4095                 20 + /* gfx_v9_4_3_ring_emit_gds_switch */
4096                 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */
4097                 5 + /* hdp invalidate */
4098                 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */
4099                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
4100                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
4101                 2 + /* gfx_v9_4_3_ring_emit_vm_flush */
4102                 8 + 8 + 8 + /* gfx_v9_4_3_ring_emit_fence x3 for user fence, vm fence */
4103                 7 + /* gfx_v9_4_3_emit_mem_sync */
4104                 5 + /* gfx_v9_4_3_emit_wave_limit for updating regSPI_WCL_PIPE_PERCENT_GFX register */
4105                 15, /* for updating 3 regSPI_WCL_PIPE_PERCENT_CS registers */
4106         .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */
4107         .emit_ib = gfx_v9_4_3_ring_emit_ib_compute,
4108         .emit_fence = gfx_v9_4_3_ring_emit_fence,
4109         .emit_pipeline_sync = gfx_v9_4_3_ring_emit_pipeline_sync,
4110         .emit_vm_flush = gfx_v9_4_3_ring_emit_vm_flush,
4111         .emit_gds_switch = gfx_v9_4_3_ring_emit_gds_switch,
4112         .emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush,
4113         .test_ring = gfx_v9_4_3_ring_test_ring,
4114         .test_ib = gfx_v9_4_3_ring_test_ib,
4115         .insert_nop = amdgpu_ring_insert_nop,
4116         .pad_ib = amdgpu_ring_generic_pad_ib,
4117         .emit_wreg = gfx_v9_4_3_ring_emit_wreg,
4118         .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait,
4119         .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait,
4120         .emit_mem_sync = gfx_v9_4_3_emit_mem_sync,
4121         .emit_wave_limit = gfx_v9_4_3_emit_wave_limit,
4122 };
4123
4124 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = {
4125         .type = AMDGPU_RING_TYPE_KIQ,
4126         .align_mask = 0xff,
4127         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4128         .support_64bit_ptrs = true,
4129         .get_rptr = gfx_v9_4_3_ring_get_rptr_compute,
4130         .get_wptr = gfx_v9_4_3_ring_get_wptr_compute,
4131         .set_wptr = gfx_v9_4_3_ring_set_wptr_compute,
4132         .emit_frame_size =
4133                 20 + /* gfx_v9_4_3_ring_emit_gds_switch */
4134                 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */
4135                 5 + /* hdp invalidate */
4136                 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */
4137                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
4138                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
4139                 2 + /* gfx_v9_4_3_ring_emit_vm_flush */
4140                 8 + 8 + 8, /* gfx_v9_4_3_ring_emit_fence_kiq x3 for user fence, vm fence */
4141         .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */
4142         .emit_fence = gfx_v9_4_3_ring_emit_fence_kiq,
4143         .test_ring = gfx_v9_4_3_ring_test_ring,
4144         .insert_nop = amdgpu_ring_insert_nop,
4145         .pad_ib = amdgpu_ring_generic_pad_ib,
4146         .emit_rreg = gfx_v9_4_3_ring_emit_rreg,
4147         .emit_wreg = gfx_v9_4_3_ring_emit_wreg,
4148         .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait,
4149         .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait,
4150 };
4151
4152 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev)
4153 {
4154         int i, j, num_xcc;
4155
4156         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
4157         for (i = 0; i < num_xcc; i++) {
4158                 adev->gfx.kiq[i].ring.funcs = &gfx_v9_4_3_ring_funcs_kiq;
4159
4160                 for (j = 0; j < adev->gfx.num_compute_rings; j++)
4161                         adev->gfx.compute_ring[j + i * adev->gfx.num_compute_rings].funcs
4162                                         = &gfx_v9_4_3_ring_funcs_compute;
4163         }
4164 }
4165
4166 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_eop_irq_funcs = {
4167         .set = gfx_v9_4_3_set_eop_interrupt_state,
4168         .process = gfx_v9_4_3_eop_irq,
4169 };
4170
4171 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_reg_irq_funcs = {
4172         .set = gfx_v9_4_3_set_priv_reg_fault_state,
4173         .process = gfx_v9_4_3_priv_reg_irq,
4174 };
4175
4176 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_inst_irq_funcs = {
4177         .set = gfx_v9_4_3_set_priv_inst_fault_state,
4178         .process = gfx_v9_4_3_priv_inst_irq,
4179 };
4180
4181 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev)
4182 {
4183         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4184         adev->gfx.eop_irq.funcs = &gfx_v9_4_3_eop_irq_funcs;
4185
4186         adev->gfx.priv_reg_irq.num_types = 1;
4187         adev->gfx.priv_reg_irq.funcs = &gfx_v9_4_3_priv_reg_irq_funcs;
4188
4189         adev->gfx.priv_inst_irq.num_types = 1;
4190         adev->gfx.priv_inst_irq.funcs = &gfx_v9_4_3_priv_inst_irq_funcs;
4191 }
4192
4193 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev)
4194 {
4195         adev->gfx.rlc.funcs = &gfx_v9_4_3_rlc_funcs;
4196 }
4197
4198
4199 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev)
4200 {
4201         /* init asci gds info */
4202         switch (adev->ip_versions[GC_HWIP][0]) {
4203         case IP_VERSION(9, 4, 3):
4204                 /* 9.4.3 removed all the GDS internal memory,
4205                  * only support GWS opcode in kernel, like barrier
4206                  * semaphore.etc */
4207                 adev->gds.gds_size = 0;
4208                 break;
4209         default:
4210                 adev->gds.gds_size = 0x10000;
4211                 break;
4212         }
4213
4214         switch (adev->ip_versions[GC_HWIP][0]) {
4215         case IP_VERSION(9, 4, 3):
4216                 /* deprecated for 9.4.3, no usage at all */
4217                 adev->gds.gds_compute_max_wave_id = 0;
4218                 break;
4219         default:
4220                 /* this really depends on the chip */
4221                 adev->gds.gds_compute_max_wave_id = 0x7ff;
4222                 break;
4223         }
4224
4225         adev->gds.gws_size = 64;
4226         adev->gds.oa_size = 16;
4227 }
4228
4229 static void gfx_v9_4_3_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
4230                                                  u32 bitmap)
4231 {
4232         u32 data;
4233
4234         if (!bitmap)
4235                 return;
4236
4237         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4238         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4239
4240         WREG32_SOC15(GC, GET_INST(GC, 0), regGC_USER_SHADER_ARRAY_CONFIG, data);
4241 }
4242
4243 static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev)
4244 {
4245         u32 data, mask;
4246
4247         data = RREG32_SOC15(GC, GET_INST(GC, 0), regCC_GC_SHADER_ARRAY_CONFIG);
4248         data |= RREG32_SOC15(GC, GET_INST(GC, 0), regGC_USER_SHADER_ARRAY_CONFIG);
4249
4250         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4251         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4252
4253         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
4254
4255         return (~data) & mask;
4256 }
4257
4258 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev,
4259                                  struct amdgpu_cu_info *cu_info)
4260 {
4261         int i, j, k, counter, active_cu_number = 0;
4262         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
4263         unsigned disable_masks[4 * 4];
4264
4265         if (!adev || !cu_info)
4266                 return -EINVAL;
4267
4268         /*
4269          * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs
4270          */
4271         if (adev->gfx.config.max_shader_engines *
4272                 adev->gfx.config.max_sh_per_se > 16)
4273                 return -EINVAL;
4274
4275         amdgpu_gfx_parse_disable_cu(disable_masks,
4276                                     adev->gfx.config.max_shader_engines,
4277                                     adev->gfx.config.max_sh_per_se);
4278
4279         mutex_lock(&adev->grbm_idx_mutex);
4280         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4281                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4282                         mask = 1;
4283                         ao_bitmap = 0;
4284                         counter = 0;
4285                         gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, 0);
4286                         gfx_v9_4_3_set_user_cu_inactive_bitmap(
4287                                 adev, disable_masks[i * adev->gfx.config.max_sh_per_se + j]);
4288                         bitmap = gfx_v9_4_3_get_cu_active_bitmap(adev);
4289
4290                         /*
4291                          * The bitmap(and ao_cu_bitmap) in cu_info structure is
4292                          * 4x4 size array, and it's usually suitable for Vega
4293                          * ASICs which has 4*2 SE/SH layout.
4294                          * But for Arcturus, SE/SH layout is changed to 8*1.
4295                          * To mostly reduce the impact, we make it compatible
4296                          * with current bitmap array as below:
4297                          *    SE4,SH0 --> bitmap[0][1]
4298                          *    SE5,SH0 --> bitmap[1][1]
4299                          *    SE6,SH0 --> bitmap[2][1]
4300                          *    SE7,SH0 --> bitmap[3][1]
4301                          */
4302                         cu_info->bitmap[i % 4][j + i / 4] = bitmap;
4303
4304                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
4305                                 if (bitmap & mask) {
4306                                         if (counter < adev->gfx.config.max_cu_per_sh)
4307                                                 ao_bitmap |= mask;
4308                                         counter++;
4309                                 }
4310                                 mask <<= 1;
4311                         }
4312                         active_cu_number += counter;
4313                         if (i < 2 && j < 2)
4314                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
4315                         cu_info->ao_cu_bitmap[i % 4][j + i / 4] = ao_bitmap;
4316                 }
4317         }
4318         gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
4319                                     0);
4320         mutex_unlock(&adev->grbm_idx_mutex);
4321
4322         cu_info->number = active_cu_number;
4323         cu_info->ao_cu_mask = ao_cu_mask;
4324         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
4325
4326         return 0;
4327 }
4328
4329 const struct amdgpu_ip_block_version gfx_v9_4_3_ip_block = {
4330         .type = AMD_IP_BLOCK_TYPE_GFX,
4331         .major = 9,
4332         .minor = 4,
4333         .rev = 0,
4334         .funcs = &gfx_v9_4_3_ip_funcs,
4335 };
4336
4337 static int gfx_v9_4_3_xcp_resume(void *handle, uint32_t inst_mask)
4338 {
4339         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4340         uint32_t tmp_mask;
4341         int i, r;
4342
4343         /* TODO : Initialize golden regs */
4344         /* gfx_v9_4_3_init_golden_registers(adev); */
4345
4346         tmp_mask = inst_mask;
4347         for_each_inst(i, tmp_mask)
4348                 gfx_v9_4_3_xcc_constants_init(adev, i);
4349
4350         if (!amdgpu_sriov_vf(adev)) {
4351                 tmp_mask = inst_mask;
4352                 for_each_inst(i, tmp_mask) {
4353                         r = gfx_v9_4_3_xcc_rlc_resume(adev, i);
4354                         if (r)
4355                                 return r;
4356                 }
4357         }
4358
4359         tmp_mask = inst_mask;
4360         for_each_inst(i, tmp_mask) {
4361                 r = gfx_v9_4_3_xcc_cp_resume(adev, i);
4362                 if (r)
4363                         return r;
4364         }
4365
4366         return 0;
4367 }
4368
4369 static int gfx_v9_4_3_xcp_suspend(void *handle, uint32_t inst_mask)
4370 {
4371         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4372         int i;
4373
4374         for_each_inst(i, inst_mask)
4375                 gfx_v9_4_3_xcc_fini(adev, i);
4376
4377         return 0;
4378 }
4379
4380 struct amdgpu_xcp_ip_funcs gfx_v9_4_3_xcp_funcs = {
4381         .suspend = &gfx_v9_4_3_xcp_suspend,
4382         .resume = &gfx_v9_4_3_xcp_resume
4383 };
4384
4385 struct amdgpu_ras_block_hw_ops  gfx_v9_4_3_ras_ops = {
4386         .query_ras_error_count = &gfx_v9_4_3_query_ras_error_count,
4387         .reset_ras_error_count = &gfx_v9_4_3_reset_ras_error_count,
4388         .query_ras_error_status = &gfx_v9_4_3_query_ras_error_status,
4389         .reset_ras_error_status = &gfx_v9_4_3_reset_ras_error_status,
4390 };
4391
4392 struct amdgpu_gfx_ras gfx_v9_4_3_ras = {
4393         .ras_block = {
4394                 .hw_ops = &gfx_v9_4_3_ras_ops,
4395         },
4396 };