drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/kernel.h>
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_gfx.h"
  28 #include "soc15.h"
  29 #include "soc15d.h"
  30 #include "amdgpu_atomfirmware.h"
  31
  32 #include "gc/gc_9_0_offset.h"
  33 #include "gc/gc_9_0_sh_mask.h"
  34 #include "vega10_enum.h"
  35 #include "hdp/hdp_4_0_offset.h"
  36
  37 #include "soc15_common.h"
  38 #include "clearstate_gfx9.h"
  39 #include "v9_structs.h"
  40
  41 #define GFX9_NUM_GFX_RINGS     1
  42 #define GFX9_MEC_HPD_SIZE 2048
  43 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
  44 #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L
  45
  46 #define mmPWR_MISC_CNTL_STATUS                                  0x0183
  47 #define mmPWR_MISC_CNTL_STATUS_BASE_IDX                         0
  48 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT        0x0
  49 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT          0x1
  50 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK          0x00000001L
  51 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK            0x00000006L
  52
  53 MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
  54 MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
  55 MODULE_FIRMWARE("amdgpu/vega10_me.bin");
  56 MODULE_FIRMWARE("amdgpu/vega10_mec.bin");
  57 MODULE_FIRMWARE("amdgpu/vega10_mec2.bin");
  58 MODULE_FIRMWARE("amdgpu/vega10_rlc.bin");
  59
  60 MODULE_FIRMWARE("amdgpu/vega12_ce.bin");
  61 MODULE_FIRMWARE("amdgpu/vega12_pfp.bin");
  62 MODULE_FIRMWARE("amdgpu/vega12_me.bin");
  63 MODULE_FIRMWARE("amdgpu/vega12_mec.bin");
  64 MODULE_FIRMWARE("amdgpu/vega12_mec2.bin");
  65 MODULE_FIRMWARE("amdgpu/vega12_rlc.bin");
  66
  67 MODULE_FIRMWARE("amdgpu/vega20_ce.bin");
  68 MODULE_FIRMWARE("amdgpu/vega20_pfp.bin");
  69 MODULE_FIRMWARE("amdgpu/vega20_me.bin");
  70 MODULE_FIRMWARE("amdgpu/vega20_mec.bin");
  71 MODULE_FIRMWARE("amdgpu/vega20_mec2.bin");
  72 MODULE_FIRMWARE("amdgpu/vega20_rlc.bin");
  73
  74 MODULE_FIRMWARE("amdgpu/raven_ce.bin");
  75 MODULE_FIRMWARE("amdgpu/raven_pfp.bin");
  76 MODULE_FIRMWARE("amdgpu/raven_me.bin");
  77 MODULE_FIRMWARE("amdgpu/raven_mec.bin");
  78 MODULE_FIRMWARE("amdgpu/raven_mec2.bin");
  79 MODULE_FIRMWARE("amdgpu/raven_rlc.bin");
  80
  81 static const struct soc15_reg_golden golden_settings_gc_9_0[] =
  82 {
  83         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420),
  84         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
  85         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
  86         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
  87         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
  88         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000),
  89         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800),
  90         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800),
  91         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87),
  92         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f),
  93         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000),
  94         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
  95         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68),
  96         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197),
  97         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
  98         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff)
  99 };
 100
 101 static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] =
 102 {
 103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0x0000f000, 0x00012107),
 104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
 105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042),
 106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x2a114042),
 107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00008000, 0x00048000),
 108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000),
 109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800)
 110 };
 111
 112 static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] =
 113 {
 114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x0f000080, 0x04000080),
 115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000),
 116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
 117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x22014042),
 118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x22014042),
 119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0x00003e00, 0x00000400),
 120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xff840000, 0x04040000),
 121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00030000),
 122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff010f, 0x01000107),
 123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x000b0000, 0x000b0000),
 124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01000000, 0x01000000)
 125 };
 126
 127 static const struct soc15_reg_golden golden_settings_gc_9_1[] =
 128 {
 129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
 130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080),
 131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080),
 132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080),
 133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420),
 134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
 135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080),
 136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
 137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
 138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080),
 140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080),
 141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080),
 142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080),
 143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080),
 144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
 145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
 146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120),
 147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
 148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
 149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080)
 150 };
 151
 152 static const struct soc15_reg_golden golden_settings_gc_9_1_rv1[] =
 153 {
 154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
 155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24000042),
 156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24000042),
 157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04048000),
 158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_MODE_CNTL_1, 0x06000000, 0x06000000),
 159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000),
 160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x00000800)
 161 };
 162
 163 static const struct soc15_reg_golden golden_settings_gc_9_x_common[] =
 164 {
 165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_INDEX, 0xffffffff, 0x00000000),
 166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2544c382)
 167 };
 168
 169 static const struct soc15_reg_golden golden_settings_gc_9_2_1[] =
 170 {
 171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420),
 172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
 173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
 174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
 175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000),
 177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800),
 178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800),
 179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87),
 180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f),
 181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000),
 182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
 183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68),
 184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197),
 185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
 186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff)
 187 };
 188
 189 static const struct soc15_reg_golden golden_settings_gc_9_2_1_vg12[] =
 190 {
 191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x00000080, 0x04000080),
 192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
 193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000),
 194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24104041),
 195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24104041),
 196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000),
 197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff03ff, 0x01000107),
 198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
 199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x76325410),
 200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000)
 201 };
 202
 203 static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[] =
 204 {
 205         mmRLC_SRM_INDEX_CNTL_ADDR_0 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 206         mmRLC_SRM_INDEX_CNTL_ADDR_1 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 207         mmRLC_SRM_INDEX_CNTL_ADDR_2 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 208         mmRLC_SRM_INDEX_CNTL_ADDR_3 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 209         mmRLC_SRM_INDEX_CNTL_ADDR_4 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 210         mmRLC_SRM_INDEX_CNTL_ADDR_5 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 211         mmRLC_SRM_INDEX_CNTL_ADDR_6 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 212         mmRLC_SRM_INDEX_CNTL_ADDR_7 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 213 };
 214
 215 static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] =
 216 {
 217         mmRLC_SRM_INDEX_CNTL_DATA_0 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 218         mmRLC_SRM_INDEX_CNTL_DATA_1 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 219         mmRLC_SRM_INDEX_CNTL_DATA_2 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 220         mmRLC_SRM_INDEX_CNTL_DATA_3 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 221         mmRLC_SRM_INDEX_CNTL_DATA_4 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 222         mmRLC_SRM_INDEX_CNTL_DATA_5 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 223         mmRLC_SRM_INDEX_CNTL_DATA_6 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 224         mmRLC_SRM_INDEX_CNTL_DATA_7 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 225 };
 226
 227 #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
 228 #define VEGA12_GB_ADDR_CONFIG_GOLDEN 0x24104041
 229 #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042
 230
 231 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
 232 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
 233 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev);
 234 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
 235 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
 236                                  struct amdgpu_cu_info *cu_info);
 237 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
 238 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
 239 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
 240
 241 static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
 242 {
 243         switch (adev->asic_type) {
 244         case CHIP_VEGA10:
 245                 soc15_program_register_sequence(adev,
 246                                                  golden_settings_gc_9_0,
 247                                                  ARRAY_SIZE(golden_settings_gc_9_0));
 248                 soc15_program_register_sequence(adev,
 249                                                  golden_settings_gc_9_0_vg10,
 250                                                  ARRAY_SIZE(golden_settings_gc_9_0_vg10));
 251                 break;
 252         case CHIP_VEGA12:
 253                 soc15_program_register_sequence(adev,
 254                                                 golden_settings_gc_9_2_1,
 255                                                 ARRAY_SIZE(golden_settings_gc_9_2_1));
 256                 soc15_program_register_sequence(adev,
 257                                                 golden_settings_gc_9_2_1_vg12,
 258                                                 ARRAY_SIZE(golden_settings_gc_9_2_1_vg12));
 259                 break;
 260         case CHIP_VEGA20:
 261                 soc15_program_register_sequence(adev,
 262                                                 golden_settings_gc_9_0,
 263                                                 ARRAY_SIZE(golden_settings_gc_9_0));
 264                 soc15_program_register_sequence(adev,
 265                                                 golden_settings_gc_9_0_vg20,
 266                                                 ARRAY_SIZE(golden_settings_gc_9_0_vg20));
 267                 break;
 268         case CHIP_RAVEN:
 269                 soc15_program_register_sequence(adev,
 270                                                  golden_settings_gc_9_1,
 271                                                  ARRAY_SIZE(golden_settings_gc_9_1));
 272                 soc15_program_register_sequence(adev,
 273                                                  golden_settings_gc_9_1_rv1,
 274                                                  ARRAY_SIZE(golden_settings_gc_9_1_rv1));
 275                 break;
 276         default:
 277                 break;
 278         }
 279
 280         soc15_program_register_sequence(adev, golden_settings_gc_9_x_common,
 281                                         (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common));
 282 }
 283
 284 static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
 285 {
 286         adev->gfx.scratch.num_reg = 8;
 287         adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
 288         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
 289 }
 290
 291 static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
 292                                        bool wc, uint32_t reg, uint32_t val)
 293 {
 294         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
 295         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
 296                                 WRITE_DATA_DST_SEL(0) |
 297                                 (wc ? WR_CONFIRM : 0));
 298         amdgpu_ring_write(ring, reg);
 299         amdgpu_ring_write(ring, 0);
 300         amdgpu_ring_write(ring, val);
 301 }
 302
 303 static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
 304                                   int mem_space, int opt, uint32_t addr0,
 305                                   uint32_t addr1, uint32_t ref, uint32_t mask,
 306                                   uint32_t inv)
 307 {
 308         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
 309         amdgpu_ring_write(ring,
 310                                  /* memory (1) or register (0) */
 311                                  (WAIT_REG_MEM_MEM_SPACE(mem_space) |
 312                                  WAIT_REG_MEM_OPERATION(opt) | /* wait */
 313                                  WAIT_REG_MEM_FUNCTION(3) |  /* equal */
 314                                  WAIT_REG_MEM_ENGINE(eng_sel)));
 315
 316         if (mem_space)
 317                 BUG_ON(addr0 & 0x3); /* Dword align */
 318         amdgpu_ring_write(ring, addr0);
 319         amdgpu_ring_write(ring, addr1);
 320         amdgpu_ring_write(ring, ref);
 321         amdgpu_ring_write(ring, mask);
 322         amdgpu_ring_write(ring, inv); /* poll interval */
 323 }
 324
 325 static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring)
 326 {
 327         struct amdgpu_device *adev = ring->adev;
 328         uint32_t scratch;
 329         uint32_t tmp = 0;
 330         unsigned i;
 331         int r;
 332
 333         r = amdgpu_gfx_scratch_get(adev, &scratch);
 334         if (r) {
 335                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
 336                 return r;
 337         }
 338         WREG32(scratch, 0xCAFEDEAD);
 339         r = amdgpu_ring_alloc(ring, 3);
 340         if (r) {
 341                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 342                           ring->idx, r);
 343                 amdgpu_gfx_scratch_free(adev, scratch);
 344                 return r;
 345         }
 346         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
 347         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
 348         amdgpu_ring_write(ring, 0xDEADBEEF);
 349         amdgpu_ring_commit(ring);
 350
 351         for (i = 0; i < adev->usec_timeout; i++) {
 352                 tmp = RREG32(scratch);
 353                 if (tmp == 0xDEADBEEF)
 354                         break;
 355                 DRM_UDELAY(1);
 356         }
 357         if (i < adev->usec_timeout) {
 358                 DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
 359                          ring->idx, i);
 360         } else {
 361                 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
 362                           ring->idx, scratch, tmp);
 363                 r = -EINVAL;
 364         }
 365         amdgpu_gfx_scratch_free(adev, scratch);
 366         return r;
 367 }
 368
 369 static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 370 {
 371         struct amdgpu_device *adev = ring->adev;
 372         struct amdgpu_ib ib;
 373         struct dma_fence *f = NULL;
 374
 375         unsigned index;
 376         uint64_t gpu_addr;
 377         uint32_t tmp;
 378         long r;
 379
 380         r = amdgpu_device_wb_get(adev, &index);
 381         if (r) {
 382                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 383                 return r;
 384         }
 385
 386         gpu_addr = adev->wb.gpu_addr + (index * 4);
 387         adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
 388         memset(&ib, 0, sizeof(ib));
 389         r = amdgpu_ib_get(adev, NULL, 16, &ib);
 390         if (r) {
 391                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 392                 goto err1;
 393         }
 394         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
 395         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
 396         ib.ptr[2] = lower_32_bits(gpu_addr);
 397         ib.ptr[3] = upper_32_bits(gpu_addr);
 398         ib.ptr[4] = 0xDEADBEEF;
 399         ib.length_dw = 5;
 400
 401         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 402         if (r)
 403                 goto err2;
 404
 405         r = dma_fence_wait_timeout(f, false, timeout);
 406         if (r == 0) {
 407                         DRM_ERROR("amdgpu: IB test timed out.\n");
 408                         r = -ETIMEDOUT;
 409                         goto err2;
 410         } else if (r < 0) {
 411                         DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 412                         goto err2;
 413         }
 414
 415         tmp = adev->wb.wb[index];
 416         if (tmp == 0xDEADBEEF) {
 417                         DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
 418                         r = 0;
 419         } else {
 420                         DRM_ERROR("ib test on ring %d failed\n", ring->idx);
 421                         r = -EINVAL;
 422         }
 423
 424 err2:
 425         amdgpu_ib_free(adev, &ib, NULL);
 426         dma_fence_put(f);
 427 err1:
 428         amdgpu_device_wb_free(adev, index);
 429         return r;
 430 }
 431
 432
 433 static void gfx_v9_0_free_microcode(struct amdgpu_device *adev)
 434 {
 435         release_firmware(adev->gfx.pfp_fw);
 436         adev->gfx.pfp_fw = NULL;
 437         release_firmware(adev->gfx.me_fw);
 438         adev->gfx.me_fw = NULL;
 439         release_firmware(adev->gfx.ce_fw);
 440         adev->gfx.ce_fw = NULL;
 441         release_firmware(adev->gfx.rlc_fw);
 442         adev->gfx.rlc_fw = NULL;
 443         release_firmware(adev->gfx.mec_fw);
 444         adev->gfx.mec_fw = NULL;
 445         release_firmware(adev->gfx.mec2_fw);
 446         adev->gfx.mec2_fw = NULL;
 447
 448         kfree(adev->gfx.rlc.register_list_format);
 449 }
 450
 451 static void gfx_v9_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
 452 {
 453         const struct rlc_firmware_header_v2_1 *rlc_hdr;
 454
 455         rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
 456         adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
 457         adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
 458         adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
 459         adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
 460         adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
 461         adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
 462         adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
 463         adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
 464         adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
 465         adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
 466         adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
 467         adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
 468         adev->gfx.rlc.reg_list_format_direct_reg_list_length =
 469                         le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
 470 }
 471
 472 static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
 473 {
 474         const char *chip_name;
 475         char fw_name[30];
 476         int err;
 477         struct amdgpu_firmware_info *info = NULL;
 478         const struct common_firmware_header *header = NULL;
 479         const struct gfx_firmware_header_v1_0 *cp_hdr;
 480         const struct rlc_firmware_header_v2_0 *rlc_hdr;
 481         unsigned int *tmp = NULL;
 482         unsigned int i = 0;
 483         uint16_t version_major;
 484         uint16_t version_minor;
 485
 486         DRM_DEBUG("\n");
 487
 488         switch (adev->asic_type) {
 489         case CHIP_VEGA10:
 490                 chip_name = "vega10";
 491                 break;
 492         case CHIP_VEGA12:
 493                 chip_name = "vega12";
 494                 break;
 495         case CHIP_VEGA20:
 496                 chip_name = "vega20";
 497                 break;
 498         case CHIP_RAVEN:
 499                 chip_name = "raven";
 500                 break;
 501         default:
 502                 BUG();
 503         }
 504
 505         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
 506         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
 507         if (err)
 508                 goto out;
 509         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
 510         if (err)
 511                 goto out;
 512         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
 513         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 514         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 515
 516         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
 517         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
 518         if (err)
 519                 goto out;
 520         err = amdgpu_ucode_validate(adev->gfx.me_fw);
 521         if (err)
 522                 goto out;
 523         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
 524         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 525         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 526
 527         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
 528         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
 529         if (err)
 530                 goto out;
 531         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
 532         if (err)
 533                 goto out;
 534         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
 535         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 536         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 537
 538         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
 539         err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
 540         if (err)
 541                 goto out;
 542         err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
 543         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
 544
 545         version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
 546         version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
 547         if (version_major == 2 && version_minor == 1)
 548                 adev->gfx.rlc.is_rlc_v2_1 = true;
 549
 550         adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
 551         adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
 552         adev->gfx.rlc.save_and_restore_offset =
 553                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
 554         adev->gfx.rlc.clear_state_descriptor_offset =
 555                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
 556         adev->gfx.rlc.avail_scratch_ram_locations =
 557                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
 558         adev->gfx.rlc.reg_restore_list_size =
 559                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
 560         adev->gfx.rlc.reg_list_format_start =
 561                         le32_to_cpu(rlc_hdr->reg_list_format_start);
 562         adev->gfx.rlc.reg_list_format_separate_start =
 563                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
 564         adev->gfx.rlc.starting_offsets_start =
 565                         le32_to_cpu(rlc_hdr->starting_offsets_start);
 566         adev->gfx.rlc.reg_list_format_size_bytes =
 567                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
 568         adev->gfx.rlc.reg_list_size_bytes =
 569                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
 570         adev->gfx.rlc.register_list_format =
 571                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
 572                                 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
 573         if (!adev->gfx.rlc.register_list_format) {
 574                 err = -ENOMEM;
 575                 goto out;
 576         }
 577
 578         tmp = (unsigned int *)((uintptr_t)rlc_hdr +
 579                         le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
 580         for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
 581                 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
 582
 583         adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
 584
 585         tmp = (unsigned int *)((uintptr_t)rlc_hdr +
 586                         le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
 587         for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
 588                 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
 589
 590         if (adev->gfx.rlc.is_rlc_v2_1)
 591                 gfx_v9_0_init_rlc_ext_microcode(adev);
 592
 593         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
 594         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
 595         if (err)
 596                 goto out;
 597         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
 598         if (err)
 599                 goto out;
 600         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
 601         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 602         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 603
 604
 605         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
 606         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
 607         if (!err) {
 608                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
 609                 if (err)
 610                         goto out;
 611                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
 612                 adev->gfx.mec2_fw->data;
 613                 adev->gfx.mec2_fw_version =
 614                 le32_to_cpu(cp_hdr->header.ucode_version);
 615                 adev->gfx.mec2_feature_version =
 616                 le32_to_cpu(cp_hdr->ucode_feature_version);
 617         } else {
 618                 err = 0;
 619                 adev->gfx.mec2_fw = NULL;
 620         }
 621
 622         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 623                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
 624                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
 625                 info->fw = adev->gfx.pfp_fw;
 626                 header = (const struct common_firmware_header *)info->fw->data;
 627                 adev->firmware.fw_size +=
 628                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 629
 630                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
 631                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
 632                 info->fw = adev->gfx.me_fw;
 633                 header = (const struct common_firmware_header *)info->fw->data;
 634                 adev->firmware.fw_size +=
 635                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 636
 637                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
 638                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
 639                 info->fw = adev->gfx.ce_fw;
 640                 header = (const struct common_firmware_header *)info->fw->data;
 641                 adev->firmware.fw_size +=
 642                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 643
 644                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
 645                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
 646                 info->fw = adev->gfx.rlc_fw;
 647                 header = (const struct common_firmware_header *)info->fw->data;
 648                 adev->firmware.fw_size +=
 649                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 650
 651                 if (adev->gfx.rlc.is_rlc_v2_1) {
 652                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
 653                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
 654                         info->fw = adev->gfx.rlc_fw;
 655                         adev->firmware.fw_size +=
 656                                 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
 657
 658                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
 659                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
 660                         info->fw = adev->gfx.rlc_fw;
 661                         adev->firmware.fw_size +=
 662                                 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
 663
 664                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
 665                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
 666                         info->fw = adev->gfx.rlc_fw;
 667                         adev->firmware.fw_size +=
 668                                 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
 669                 }
 670
 671                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
 672                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
 673                 info->fw = adev->gfx.mec_fw;
 674                 header = (const struct common_firmware_header *)info->fw->data;
 675                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
 676                 adev->firmware.fw_size +=
 677                         ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 678
 679                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
 680                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
 681                 info->fw = adev->gfx.mec_fw;
 682                 adev->firmware.fw_size +=
 683                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 684
 685                 if (adev->gfx.mec2_fw) {
 686                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
 687                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 688                         info->fw = adev->gfx.mec2_fw;
 689                         header = (const struct common_firmware_header *)info->fw->data;
 690                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
 691                         adev->firmware.fw_size +=
 692                                 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 693                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
 694                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
 695                         info->fw = adev->gfx.mec2_fw;
 696                         adev->firmware.fw_size +=
 697                                 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 698                 }
 699
 700         }
 701
 702 out:
 703         if (err) {
 704                 dev_err(adev->dev,
 705                         "gfx9: Failed to load firmware \"%s\"\n",
 706                         fw_name);
 707                 release_firmware(adev->gfx.pfp_fw);
 708                 adev->gfx.pfp_fw = NULL;
 709                 release_firmware(adev->gfx.me_fw);
 710                 adev->gfx.me_fw = NULL;
 711                 release_firmware(adev->gfx.ce_fw);
 712                 adev->gfx.ce_fw = NULL;
 713                 release_firmware(adev->gfx.rlc_fw);
 714                 adev->gfx.rlc_fw = NULL;
 715                 release_firmware(adev->gfx.mec_fw);
 716                 adev->gfx.mec_fw = NULL;
 717                 release_firmware(adev->gfx.mec2_fw);
 718                 adev->gfx.mec2_fw = NULL;
 719         }
 720         return err;
 721 }
 722
 723 static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
 724 {
 725         u32 count = 0;
 726         const struct cs_section_def *sect = NULL;
 727         const struct cs_extent_def *ext = NULL;
 728
 729         /* begin clear state */
 730         count += 2;
 731         /* context control state */
 732         count += 3;
 733
 734         for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
 735                 for (ext = sect->section; ext->extent != NULL; ++ext) {
 736                         if (sect->id == SECT_CONTEXT)
 737                                 count += 2 + ext->reg_count;
 738                         else
 739                                 return 0;
 740                 }
 741         }
 742
 743         /* end clear state */
 744         count += 2;
 745         /* clear state */
 746         count += 2;
 747
 748         return count;
 749 }
 750
 751 static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev,
 752                                     volatile u32 *buffer)
 753 {
 754         u32 count = 0, i;
 755         const struct cs_section_def *sect = NULL;
 756         const struct cs_extent_def *ext = NULL;
 757
 758         if (adev->gfx.rlc.cs_data == NULL)
 759                 return;
 760         if (buffer == NULL)
 761                 return;
 762
 763         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 764         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
 765
 766         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
 767         buffer[count++] = cpu_to_le32(0x80000000);
 768         buffer[count++] = cpu_to_le32(0x80000000);
 769
 770         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
 771                 for (ext = sect->section; ext->extent != NULL; ++ext) {
 772                         if (sect->id == SECT_CONTEXT) {
 773                                 buffer[count++] =
 774                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
 775                                 buffer[count++] = cpu_to_le32(ext->reg_index -
 776                                                 PACKET3_SET_CONTEXT_REG_START);
 777                                 for (i = 0; i < ext->reg_count; i++)
 778                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
 779                         } else {
 780                                 return;
 781                         }
 782                 }
 783         }
 784
 785         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 786         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
 787
 788         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
 789         buffer[count++] = cpu_to_le32(0);
 790 }
 791
 792 static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev)
 793 {
 794         uint32_t data;
 795
 796         /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */
 797         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F);
 798         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7);
 799         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077);
 800         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16));
 801
 802         /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */
 803         WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000);
 804
 805         /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */
 806         WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500);
 807
 808         mutex_lock(&adev->grbm_idx_mutex);
 809         /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/
 810         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 811         WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff);
 812
 813         /* set mmRLC_LB_PARAMS = 0x003F_1006 */
 814         data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003);
 815         data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010);
 816         data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F);
 817         WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data);
 818
 819         /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */
 820         data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7);
 821         data &= 0x0000FFFF;
 822         data |= 0x00C00000;
 823         WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data);
 824
 825         /* set RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF */
 826         WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, 0xFFF);
 827
 828         /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved,
 829          * but used for RLC_LB_CNTL configuration */
 830         data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK;
 831         data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09);
 832         data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000);
 833         WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data);
 834         mutex_unlock(&adev->grbm_idx_mutex);
 835 }
 836
 837 static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
 838 {
 839         WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
 840 }
 841
 842 static void rv_init_cp_jump_table(struct amdgpu_device *adev)
 843 {
 844         const __le32 *fw_data;
 845         volatile u32 *dst_ptr;
 846         int me, i, max_me = 5;
 847         u32 bo_offset = 0;
 848         u32 table_offset, table_size;
 849
 850         /* write the cp table buffer */
 851         dst_ptr = adev->gfx.rlc.cp_table_ptr;
 852         for (me = 0; me < max_me; me++) {
 853                 if (me == 0) {
 854                         const struct gfx_firmware_header_v1_0 *hdr =
 855                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
 856                         fw_data = (const __le32 *)
 857                                 (adev->gfx.ce_fw->data +
 858                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 859                         table_offset = le32_to_cpu(hdr->jt_offset);
 860                         table_size = le32_to_cpu(hdr->jt_size);
 861                 } else if (me == 1) {
 862                         const struct gfx_firmware_header_v1_0 *hdr =
 863                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
 864                         fw_data = (const __le32 *)
 865                                 (adev->gfx.pfp_fw->data +
 866                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 867                         table_offset = le32_to_cpu(hdr->jt_offset);
 868                         table_size = le32_to_cpu(hdr->jt_size);
 869                 } else if (me == 2) {
 870                         const struct gfx_firmware_header_v1_0 *hdr =
 871                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
 872                         fw_data = (const __le32 *)
 873                                 (adev->gfx.me_fw->data +
 874                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 875                         table_offset = le32_to_cpu(hdr->jt_offset);
 876                         table_size = le32_to_cpu(hdr->jt_size);
 877                 } else if (me == 3) {
 878                         const struct gfx_firmware_header_v1_0 *hdr =
 879                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
 880                         fw_data = (const __le32 *)
 881                                 (adev->gfx.mec_fw->data +
 882                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 883                         table_offset = le32_to_cpu(hdr->jt_offset);
 884                         table_size = le32_to_cpu(hdr->jt_size);
 885                 } else  if (me == 4) {
 886                         const struct gfx_firmware_header_v1_0 *hdr =
 887                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
 888                         fw_data = (const __le32 *)
 889                                 (adev->gfx.mec2_fw->data +
 890                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 891                         table_offset = le32_to_cpu(hdr->jt_offset);
 892                         table_size = le32_to_cpu(hdr->jt_size);
 893                 }
 894
 895                 for (i = 0; i < table_size; i ++) {
 896                         dst_ptr[bo_offset + i] =
 897                                 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
 898                 }
 899
 900                 bo_offset += table_size;
 901         }
 902 }
 903
 904 static void gfx_v9_0_rlc_fini(struct amdgpu_device *adev)
 905 {
 906         /* clear state block */
 907         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
 908                         &adev->gfx.rlc.clear_state_gpu_addr,
 909                         (void **)&adev->gfx.rlc.cs_ptr);
 910
 911         /* jump table block */
 912         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
 913                         &adev->gfx.rlc.cp_table_gpu_addr,
 914                         (void **)&adev->gfx.rlc.cp_table_ptr);
 915 }
 916
 917 static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
 918 {
 919         volatile u32 *dst_ptr;
 920         u32 dws;
 921         const struct cs_section_def *cs_data;
 922         int r;
 923
 924         adev->gfx.rlc.cs_data = gfx9_cs_data;
 925
 926         cs_data = adev->gfx.rlc.cs_data;
 927
 928         if (cs_data) {
 929                 /* clear state block */
 930                 adev->gfx.rlc.clear_state_size = dws = gfx_v9_0_get_csb_size(adev);
 931                 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
 932                                               AMDGPU_GEM_DOMAIN_VRAM,
 933                                               &adev->gfx.rlc.clear_state_obj,
 934                                               &adev->gfx.rlc.clear_state_gpu_addr,
 935                                               (void **)&adev->gfx.rlc.cs_ptr);
 936                 if (r) {
 937                         dev_err(adev->dev, "(%d) failed to create rlc csb bo\n",
 938                                 r);
 939                         gfx_v9_0_rlc_fini(adev);
 940                         return r;
 941                 }
 942                 /* set up the cs buffer */
 943                 dst_ptr = adev->gfx.rlc.cs_ptr;
 944                 gfx_v9_0_get_csb_buffer(adev, dst_ptr);
 945                 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
 946                 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
 947         }
 948
 949         if (adev->asic_type == CHIP_RAVEN) {
 950                 /* TODO: double check the cp_table_size for RV */
 951                 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
 952                 r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size,
 953                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 954                                               &adev->gfx.rlc.cp_table_obj,
 955                                               &adev->gfx.rlc.cp_table_gpu_addr,
 956                                               (void **)&adev->gfx.rlc.cp_table_ptr);
 957                 if (r) {
 958                         dev_err(adev->dev,
 959                                 "(%d) failed to create cp table bo\n", r);
 960                         gfx_v9_0_rlc_fini(adev);
 961                         return r;
 962                 }
 963
 964                 rv_init_cp_jump_table(adev);
 965                 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
 966                 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
 967
 968                 gfx_v9_0_init_lbpw(adev);
 969         }
 970
 971         return 0;
 972 }
 973
 974 static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
 975 {
 976         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
 977         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
 978 }
 979
 980 static int gfx_v9_0_mec_init(struct amdgpu_device *adev)
 981 {
 982         int r;
 983         u32 *hpd;
 984         const __le32 *fw_data;
 985         unsigned fw_size;
 986         u32 *fw;
 987         size_t mec_hpd_size;
 988
 989         const struct gfx_firmware_header_v1_0 *mec_hdr;
 990
 991         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
 992
 993         /* take ownership of the relevant compute queues */
 994         amdgpu_gfx_compute_queue_acquire(adev);
 995         mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE;
 996
 997         r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
 998                                       AMDGPU_GEM_DOMAIN_GTT,
 999                                       &adev->gfx.mec.hpd_eop_obj,
1000                                       &adev->gfx.mec.hpd_eop_gpu_addr,
1001                                       (void **)&hpd);
1002         if (r) {
1003                 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
1004                 gfx_v9_0_mec_fini(adev);
1005                 return r;
1006         }
1007
1008         memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
1009
1010         amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
1011         amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1012
1013         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1014
1015         fw_data = (const __le32 *)
1016                 (adev->gfx.mec_fw->data +
1017                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
1018         fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
1019
1020         r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
1021                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
1022                                       &adev->gfx.mec.mec_fw_obj,
1023                                       &adev->gfx.mec.mec_fw_gpu_addr,
1024                                       (void **)&fw);
1025         if (r) {
1026                 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r);
1027                 gfx_v9_0_mec_fini(adev);
1028                 return r;
1029         }
1030
1031         memcpy(fw, fw_data, fw_size);
1032
1033         amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
1034         amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
1035
1036         return 0;
1037 }
1038
1039 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
1040 {
1041         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1042                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1043                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
1044                 (address << SQ_IND_INDEX__INDEX__SHIFT) |
1045                 (SQ_IND_INDEX__FORCE_READ_MASK));
1046         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1047 }
1048
1049 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
1050                            uint32_t wave, uint32_t thread,
1051                            uint32_t regno, uint32_t num, uint32_t *out)
1052 {
1053         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1054                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1055                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
1056                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
1057                 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
1058                 (SQ_IND_INDEX__FORCE_READ_MASK) |
1059                 (SQ_IND_INDEX__AUTO_INCR_MASK));
1060         while (num--)
1061                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1062 }
1063
1064 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
1065 {
1066         /* type 1 wave data */
1067         dst[(*no_fields)++] = 1;
1068         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
1069         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
1070         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
1071         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
1072         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
1073         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
1074         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
1075         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
1076         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
1077         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
1078         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
1079         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
1080         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
1081         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
1082 }
1083
1084 static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
1085                                      uint32_t wave, uint32_t start,
1086                                      uint32_t size, uint32_t *dst)
1087 {
1088         wave_read_regs(
1089                 adev, simd, wave, 0,
1090                 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
1091 }
1092
1093 static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
1094                                      uint32_t wave, uint32_t thread,
1095                                      uint32_t start, uint32_t size,
1096                                      uint32_t *dst)
1097 {
1098         wave_read_regs(
1099                 adev, simd, wave, thread,
1100                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
1101 }
1102
1103 static void gfx_v9_0_select_me_pipe_q(struct amdgpu_device *adev,
1104                                   u32 me, u32 pipe, u32 q)
1105 {
1106         soc15_grbm_select(adev, me, pipe, q, 0);
1107 }
1108
1109 static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
1110         .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
1111         .select_se_sh = &gfx_v9_0_select_se_sh,
1112         .read_wave_data = &gfx_v9_0_read_wave_data,
1113         .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
1114         .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs,
1115         .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q
1116 };
1117
1118 static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
1119 {
1120         u32 gb_addr_config;
1121         int err;
1122
1123         adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
1124
1125         switch (adev->asic_type) {
1126         case CHIP_VEGA10:
1127                 adev->gfx.config.max_hw_contexts = 8;
1128                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1129                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1130                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1131                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1132                 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN;
1133                 break;
1134         case CHIP_VEGA12:
1135                 adev->gfx.config.max_hw_contexts = 8;
1136                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1137                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1138                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1139                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1140                 gb_addr_config = VEGA12_GB_ADDR_CONFIG_GOLDEN;
1141                 DRM_INFO("fix gfx.config for vega12\n");
1142                 break;
1143         case CHIP_VEGA20:
1144                 adev->gfx.config.max_hw_contexts = 8;
1145                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1146                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1147                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1148                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1149                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
1150                 gb_addr_config &= ~0xf3e777ff;
1151                 gb_addr_config |= 0x22014042;
1152                 /* check vbios table if gpu info is not available */
1153                 err = amdgpu_atomfirmware_get_gfx_info(adev);
1154                 if (err)
1155                         return err;
1156                 break;
1157         case CHIP_RAVEN:
1158                 adev->gfx.config.max_hw_contexts = 8;
1159                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1160                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1161                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1162                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1163                 gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
1164                 break;
1165         default:
1166                 BUG();
1167                 break;
1168         }
1169
1170         adev->gfx.config.gb_addr_config = gb_addr_config;
1171
1172         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
1173                         REG_GET_FIELD(
1174                                         adev->gfx.config.gb_addr_config,
1175                                         GB_ADDR_CONFIG,
1176                                         NUM_PIPES);
1177
1178         adev->gfx.config.max_tile_pipes =
1179                 adev->gfx.config.gb_addr_config_fields.num_pipes;
1180
1181         adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
1182                         REG_GET_FIELD(
1183                                         adev->gfx.config.gb_addr_config,
1184                                         GB_ADDR_CONFIG,
1185                                         NUM_BANKS);
1186         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
1187                         REG_GET_FIELD(
1188                                         adev->gfx.config.gb_addr_config,
1189                                         GB_ADDR_CONFIG,
1190                                         MAX_COMPRESSED_FRAGS);
1191         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
1192                         REG_GET_FIELD(
1193                                         adev->gfx.config.gb_addr_config,
1194                                         GB_ADDR_CONFIG,
1195                                         NUM_RB_PER_SE);
1196         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
1197                         REG_GET_FIELD(
1198                                         adev->gfx.config.gb_addr_config,
1199                                         GB_ADDR_CONFIG,
1200                                         NUM_SHADER_ENGINES);
1201         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
1202                         REG_GET_FIELD(
1203                                         adev->gfx.config.gb_addr_config,
1204                                         GB_ADDR_CONFIG,
1205                                         PIPE_INTERLEAVE_SIZE));
1206
1207         return 0;
1208 }
1209
1210 static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev,
1211                                    struct amdgpu_ngg_buf *ngg_buf,
1212                                    int size_se,
1213                                    int default_size_se)
1214 {
1215         int r;
1216
1217         if (size_se < 0) {
1218                 dev_err(adev->dev, "Buffer size is invalid: %d\n", size_se);
1219                 return -EINVAL;
1220         }
1221         size_se = size_se ? size_se : default_size_se;
1222
1223         ngg_buf->size = size_se * adev->gfx.config.max_shader_engines;
1224         r = amdgpu_bo_create_kernel(adev, ngg_buf->size,
1225                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1226                                     &ngg_buf->bo,
1227                                     &ngg_buf->gpu_addr,
1228                                     NULL);
1229         if (r) {
1230                 dev_err(adev->dev, "(%d) failed to create NGG buffer\n", r);
1231                 return r;
1232         }
1233         ngg_buf->bo_size = amdgpu_bo_size(ngg_buf->bo);
1234
1235         return r;
1236 }
1237
1238 static int gfx_v9_0_ngg_fini(struct amdgpu_device *adev)
1239 {
1240         int i;
1241
1242         for (i = 0; i < NGG_BUF_MAX; i++)
1243                 amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo,
1244                                       &adev->gfx.ngg.buf[i].gpu_addr,
1245                                       NULL);
1246
1247         memset(&adev->gfx.ngg.buf[0], 0,
1248                         sizeof(struct amdgpu_ngg_buf) * NGG_BUF_MAX);
1249
1250         adev->gfx.ngg.init = false;
1251
1252         return 0;
1253 }
1254
1255 static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
1256 {
1257         int r;
1258
1259         if (!amdgpu_ngg || adev->gfx.ngg.init == true)
1260                 return 0;
1261
1262         /* GDS reserve memory: 64 bytes alignment */
1263         adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
1264         adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;
1265         adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;
1266         adev->gfx.ngg.gds_reserve_addr = RREG32_SOC15(GC, 0, mmGDS_VMID0_BASE);
1267         adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
1268
1269         /* Primitive Buffer */
1270         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM],
1271                                     amdgpu_prim_buf_per_se,
1272                                     64 * 1024);
1273         if (r) {
1274                 dev_err(adev->dev, "Failed to create Primitive Buffer\n");
1275                 goto err;
1276         }
1277
1278         /* Position Buffer */
1279         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_POS],
1280                                     amdgpu_pos_buf_per_se,
1281                                     256 * 1024);
1282         if (r) {
1283                 dev_err(adev->dev, "Failed to create Position Buffer\n");
1284                 goto err;
1285         }
1286
1287         /* Control Sideband */
1288         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_CNTL],
1289                                     amdgpu_cntl_sb_buf_per_se,
1290                                     256);
1291         if (r) {
1292                 dev_err(adev->dev, "Failed to create Control Sideband Buffer\n");
1293                 goto err;
1294         }
1295
1296         /* Parameter Cache, not created by default */
1297         if (amdgpu_param_buf_per_se <= 0)
1298                 goto out;
1299
1300         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PARAM],
1301                                     amdgpu_param_buf_per_se,
1302                                     512 * 1024);
1303         if (r) {
1304                 dev_err(adev->dev, "Failed to create Parameter Cache\n");
1305                 goto err;
1306         }
1307
1308 out:
1309         adev->gfx.ngg.init = true;
1310         return 0;
1311 err:
1312         gfx_v9_0_ngg_fini(adev);
1313         return r;
1314 }
1315
1316 static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
1317 {
1318         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
1319         int r;
1320         u32 data, base;
1321
1322         if (!amdgpu_ngg)
1323                 return 0;
1324
1325         /* Program buffer size */
1326         data = REG_SET_FIELD(0, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE,
1327                              adev->gfx.ngg.buf[NGG_PRIM].size >> 8);
1328         data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE,
1329                              adev->gfx.ngg.buf[NGG_POS].size >> 8);
1330         WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_1, data);
1331
1332         data = REG_SET_FIELD(0, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE,
1333                              adev->gfx.ngg.buf[NGG_CNTL].size >> 8);
1334         data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE,
1335                              adev->gfx.ngg.buf[NGG_PARAM].size >> 10);
1336         WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_2, data);
1337
1338         /* Program buffer base address */
1339         base = lower_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
1340         data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base);
1341         WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE, data);
1342
1343         base = upper_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
1344         data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base);
1345         WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE_HI, data);
1346
1347         base = lower_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
1348         data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base);
1349         WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE, data);
1350
1351         base = upper_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
1352         data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base);
1353         WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE_HI, data);
1354
1355         base = lower_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
1356         data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base);
1357         WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE, data);
1358
1359         base = upper_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
1360         data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base);
1361         WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI, data);
1362
1363         /* Clear GDS reserved memory */
1364         r = amdgpu_ring_alloc(ring, 17);
1365         if (r) {
1366                 DRM_ERROR("amdgpu: NGG failed to lock ring %d (%d).\n",
1367                           ring->idx, r);
1368                 return r;
1369         }
1370
1371         gfx_v9_0_write_data_to_reg(ring, 0, false,
1372                                    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
1373                                    (adev->gds.mem.total_size +
1374                                     adev->gfx.ngg.gds_reserve_size) >>
1375                                    AMDGPU_GDS_SHIFT);
1376
1377         amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
1378         amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
1379                                 PACKET3_DMA_DATA_DST_SEL(1) |
1380                                 PACKET3_DMA_DATA_SRC_SEL(2)));
1381         amdgpu_ring_write(ring, 0);
1382         amdgpu_ring_write(ring, 0);
1383         amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
1384         amdgpu_ring_write(ring, 0);
1385         amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT |
1386                                 adev->gfx.ngg.gds_reserve_size);
1387
1388         gfx_v9_0_write_data_to_reg(ring, 0, false,
1389                                    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0);
1390
1391         amdgpu_ring_commit(ring);
1392
1393         return 0;
1394 }
1395
1396 static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1397                                       int mec, int pipe, int queue)
1398 {
1399         int r;
1400         unsigned irq_type;
1401         struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1402
1403         ring = &adev->gfx.compute_ring[ring_id];
1404
1405         /* mec0 is me1 */
1406         ring->me = mec + 1;
1407         ring->pipe = pipe;
1408         ring->queue = queue;
1409
1410         ring->ring_obj = NULL;
1411         ring->use_doorbell = true;
1412         ring->doorbell_index = (AMDGPU_DOORBELL_MEC_RING0 + ring_id) << 1;
1413         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1414                                 + (ring_id * GFX9_MEC_HPD_SIZE);
1415         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1416
1417         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1418                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1419                 + ring->pipe;
1420
1421         /* type-2 packets are deprecated on MEC, use type-3 instead */
1422         r = amdgpu_ring_init(adev, ring, 1024,
1423                              &adev->gfx.eop_irq, irq_type);
1424         if (r)
1425                 return r;
1426
1427
1428         return 0;
1429 }
1430
1431 static int gfx_v9_0_sw_init(void *handle)
1432 {
1433         int i, j, k, r, ring_id;
1434         struct amdgpu_ring *ring;
1435         struct amdgpu_kiq *kiq;
1436         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1437
1438         switch (adev->asic_type) {
1439         case CHIP_VEGA10:
1440         case CHIP_VEGA12:
1441         case CHIP_VEGA20:
1442         case CHIP_RAVEN:
1443                 adev->gfx.mec.num_mec = 2;
1444                 break;
1445         default:
1446                 adev->gfx.mec.num_mec = 1;
1447                 break;
1448         }
1449
1450         adev->gfx.mec.num_pipe_per_mec = 4;
1451         adev->gfx.mec.num_queue_per_pipe = 8;
1452
1453         /* KIQ event */
1454         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 178, &adev->gfx.kiq.irq);
1455         if (r)
1456                 return r;
1457
1458         /* EOP Event */
1459         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 181, &adev->gfx.eop_irq);
1460         if (r)
1461                 return r;
1462
1463         /* Privileged reg */
1464         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 184,
1465                               &adev->gfx.priv_reg_irq);
1466         if (r)
1467                 return r;
1468
1469         /* Privileged inst */
1470         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 185,
1471                               &adev->gfx.priv_inst_irq);
1472         if (r)
1473                 return r;
1474
1475         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1476
1477         gfx_v9_0_scratch_init(adev);
1478
1479         r = gfx_v9_0_init_microcode(adev);
1480         if (r) {
1481                 DRM_ERROR("Failed to load gfx firmware!\n");
1482                 return r;
1483         }
1484
1485         r = gfx_v9_0_rlc_init(adev);
1486         if (r) {
1487                 DRM_ERROR("Failed to init rlc BOs!\n");
1488                 return r;
1489         }
1490
1491         r = gfx_v9_0_mec_init(adev);
1492         if (r) {
1493                 DRM_ERROR("Failed to init MEC BOs!\n");
1494                 return r;
1495         }
1496
1497         /* set up the gfx ring */
1498         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
1499                 ring = &adev->gfx.gfx_ring[i];
1500                 ring->ring_obj = NULL;
1501                 if (!i)
1502                         sprintf(ring->name, "gfx");
1503                 else
1504                         sprintf(ring->name, "gfx_%d", i);
1505                 ring->use_doorbell = true;
1506                 ring->doorbell_index = AMDGPU_DOORBELL64_GFX_RING0 << 1;
1507                 r = amdgpu_ring_init(adev, ring, 1024,
1508                                      &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
1509                 if (r)
1510                         return r;
1511         }
1512
1513         /* set up the compute queues - allocate horizontally across pipes */
1514         ring_id = 0;
1515         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1516                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1517                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
1518                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j))
1519                                         continue;
1520
1521                                 r = gfx_v9_0_compute_ring_init(adev,
1522                                                                ring_id,
1523                                                                i, k, j);
1524                                 if (r)
1525                                         return r;
1526
1527                                 ring_id++;
1528                         }
1529                 }
1530         }
1531
1532         r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE);
1533         if (r) {
1534                 DRM_ERROR("Failed to init KIQ BOs!\n");
1535                 return r;
1536         }
1537
1538         kiq = &adev->gfx.kiq;
1539         r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
1540         if (r)
1541                 return r;
1542
1543         /* create MQD for all compute queues as wel as KIQ for SRIOV case */
1544         r = amdgpu_gfx_compute_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation));
1545         if (r)
1546                 return r;
1547
1548         /* reserve GDS, GWS and OA resource for gfx */
1549         r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
1550                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
1551                                     &adev->gds.gds_gfx_bo, NULL, NULL);
1552         if (r)
1553                 return r;
1554
1555         r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
1556                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
1557                                     &adev->gds.gws_gfx_bo, NULL, NULL);
1558         if (r)
1559                 return r;
1560
1561         r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
1562                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
1563                                     &adev->gds.oa_gfx_bo, NULL, NULL);
1564         if (r)
1565                 return r;
1566
1567         adev->gfx.ce_ram_size = 0x8000;
1568
1569         r = gfx_v9_0_gpu_early_init(adev);
1570         if (r)
1571                 return r;
1572
1573         r = gfx_v9_0_ngg_init(adev);
1574         if (r)
1575                 return r;
1576
1577         return 0;
1578 }
1579
1580
1581 static int gfx_v9_0_sw_fini(void *handle)
1582 {
1583         int i;
1584         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1585
1586         amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
1587         amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
1588         amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
1589
1590         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1591                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1592         for (i = 0; i < adev->gfx.num_compute_rings; i++)
1593                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1594
1595         amdgpu_gfx_compute_mqd_sw_fini(adev);
1596         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
1597         amdgpu_gfx_kiq_fini(adev);
1598
1599         gfx_v9_0_mec_fini(adev);
1600         gfx_v9_0_ngg_fini(adev);
1601         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
1602                                 &adev->gfx.rlc.clear_state_gpu_addr,
1603                                 (void **)&adev->gfx.rlc.cs_ptr);
1604         if (adev->asic_type == CHIP_RAVEN) {
1605                 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
1606                                 &adev->gfx.rlc.cp_table_gpu_addr,
1607                                 (void **)&adev->gfx.rlc.cp_table_ptr);
1608         }
1609         gfx_v9_0_free_microcode(adev);
1610
1611         return 0;
1612 }
1613
1614
1615 static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev)
1616 {
1617         /* TODO */
1618 }
1619
1620 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance)
1621 {
1622         u32 data;
1623
1624         if (instance == 0xffffffff)
1625                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1626         else
1627                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1628
1629         if (se_num == 0xffffffff)
1630                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1631         else
1632                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1633
1634         if (sh_num == 0xffffffff)
1635                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1636         else
1637                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1638
1639         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
1640 }
1641
1642 static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1643 {
1644         u32 data, mask;
1645
1646         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
1647         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
1648
1649         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1650         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1651
1652         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1653                                          adev->gfx.config.max_sh_per_se);
1654
1655         return (~data) & mask;
1656 }
1657
1658 static void gfx_v9_0_setup_rb(struct amdgpu_device *adev)
1659 {
1660         int i, j;
1661         u32 data;
1662         u32 active_rbs = 0;
1663         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1664                                         adev->gfx.config.max_sh_per_se;
1665
1666         mutex_lock(&adev->grbm_idx_mutex);
1667         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1668                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1669                         gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1670                         data = gfx_v9_0_get_rb_active_bitmap(adev);
1671                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1672                                                rb_bitmap_width_per_sh);
1673                 }
1674         }
1675         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1676         mutex_unlock(&adev->grbm_idx_mutex);
1677
1678         adev->gfx.config.backend_enable_mask = active_rbs;
1679         adev->gfx.config.num_rbs = hweight32(active_rbs);
1680 }
1681
1682 #define DEFAULT_SH_MEM_BASES    (0x6000)
1683 #define FIRST_COMPUTE_VMID      (8)
1684 #define LAST_COMPUTE_VMID       (16)
1685 static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
1686 {
1687         int i;
1688         uint32_t sh_mem_config;
1689         uint32_t sh_mem_bases;
1690
1691         /*
1692          * Configure apertures:
1693          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
1694          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
1695          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
1696          */
1697         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1698
1699         sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
1700                         SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1701                         SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
1702
1703         mutex_lock(&adev->srbm_mutex);
1704         for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1705                 soc15_grbm_select(adev, 0, 0, 0, i);
1706                 /* CP and shaders */
1707                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
1708                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
1709         }
1710         soc15_grbm_select(adev, 0, 0, 0, 0);
1711         mutex_unlock(&adev->srbm_mutex);
1712 }
1713
1714 static void gfx_v9_0_gpu_init(struct amdgpu_device *adev)
1715 {
1716         u32 tmp;
1717         int i;
1718
1719         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
1720
1721         gfx_v9_0_tiling_mode_table_init(adev);
1722
1723         gfx_v9_0_setup_rb(adev);
1724         gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);
1725         adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2);
1726
1727         /* XXX SH_MEM regs */
1728         /* where to put LDS, scratch, GPUVM in FSA64 space */
1729         mutex_lock(&adev->srbm_mutex);
1730         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids; i++) {
1731                 soc15_grbm_select(adev, 0, 0, 0, i);
1732                 /* CP and shaders */
1733                 if (i == 0) {
1734                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
1735                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1736                         WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
1737                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0);
1738                 } else {
1739                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
1740                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1741                         WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
1742                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
1743                                 (adev->gmc.private_aperture_start >> 48));
1744                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
1745                                 (adev->gmc.shared_aperture_start >> 48));
1746                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
1747                 }
1748         }
1749         soc15_grbm_select(adev, 0, 0, 0, 0);
1750
1751         mutex_unlock(&adev->srbm_mutex);
1752
1753         gfx_v9_0_init_compute_vmid(adev);
1754
1755         mutex_lock(&adev->grbm_idx_mutex);
1756         /*
1757          * making sure that the following register writes will be broadcasted
1758          * to all the shaders
1759          */
1760         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1761
1762         WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE,
1763                    (adev->gfx.config.sc_prim_fifo_size_frontend <<
1764                         PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1765                    (adev->gfx.config.sc_prim_fifo_size_backend <<
1766                         PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1767                    (adev->gfx.config.sc_hiz_tile_fifo_size <<
1768                         PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1769                    (adev->gfx.config.sc_earlyz_tile_fifo_size <<
1770                         PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
1771         mutex_unlock(&adev->grbm_idx_mutex);
1772
1773 }
1774
1775 static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
1776 {
1777         u32 i, j, k;
1778         u32 mask;
1779
1780         mutex_lock(&adev->grbm_idx_mutex);
1781         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1782                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1783                         gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1784                         for (k = 0; k < adev->usec_timeout; k++) {
1785                                 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0)
1786                                         break;
1787                                 udelay(1);
1788                         }
1789                         if (k == adev->usec_timeout) {
1790                                 gfx_v9_0_select_se_sh(adev, 0xffffffff,
1791                                                       0xffffffff, 0xffffffff);
1792                                 mutex_unlock(&adev->grbm_idx_mutex);
1793                                 DRM_INFO("Timeout wait for RLC serdes %u,%u\n",
1794                                          i, j);
1795                                 return;
1796                         }
1797                 }
1798         }
1799         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1800         mutex_unlock(&adev->grbm_idx_mutex);
1801
1802         mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
1803                 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
1804                 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
1805                 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
1806         for (k = 0; k < adev->usec_timeout; k++) {
1807                 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
1808                         break;
1809                 udelay(1);
1810         }
1811 }
1812
1813 static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1814                                                bool enable)
1815 {
1816         u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
1817
1818         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
1819         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
1820         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
1821         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
1822
1823         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
1824 }
1825
1826 static void gfx_v9_0_init_csb(struct amdgpu_device *adev)
1827 {
1828         /* csib */
1829         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI),
1830                         adev->gfx.rlc.clear_state_gpu_addr >> 32);
1831         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO),
1832                         adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
1833         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH),
1834                         adev->gfx.rlc.clear_state_size);
1835 }
1836
1837 static void gfx_v9_1_parse_ind_reg_list(int *register_list_format,
1838                                 int indirect_offset,
1839                                 int list_size,
1840                                 int *unique_indirect_regs,
1841                                 int unique_indirect_reg_count,
1842                                 int *indirect_start_offsets,
1843                                 int *indirect_start_offsets_count,
1844                                 int max_start_offsets_count)
1845 {
1846         int idx;
1847
1848         for (; indirect_offset < list_size; indirect_offset++) {
1849                 WARN_ON(*indirect_start_offsets_count >= max_start_offsets_count);
1850                 indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset;
1851                 *indirect_start_offsets_count = *indirect_start_offsets_count + 1;
1852
1853                 while (register_list_format[indirect_offset] != 0xFFFFFFFF) {
1854                         indirect_offset += 2;
1855
1856                         /* look for the matching indice */
1857                         for (idx = 0; idx < unique_indirect_reg_count; idx++) {
1858                                 if (unique_indirect_regs[idx] ==
1859                                         register_list_format[indirect_offset] ||
1860                                         !unique_indirect_regs[idx])
1861                                         break;
1862                         }
1863
1864                         BUG_ON(idx >= unique_indirect_reg_count);
1865
1866                         if (!unique_indirect_regs[idx])
1867                                 unique_indirect_regs[idx] = register_list_format[indirect_offset];
1868
1869                         indirect_offset++;
1870                 }
1871         }
1872 }
1873
1874 static int gfx_v9_1_init_rlc_save_restore_list(struct amdgpu_device *adev)
1875 {
1876         int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
1877         int unique_indirect_reg_count = 0;
1878
1879         int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
1880         int indirect_start_offsets_count = 0;
1881
1882         int list_size = 0;
1883         int i = 0, j = 0;
1884         u32 tmp = 0;
1885
1886         u32 *register_list_format =
1887                 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
1888         if (!register_list_format)
1889                 return -ENOMEM;
1890         memcpy(register_list_format, adev->gfx.rlc.register_list_format,
1891                 adev->gfx.rlc.reg_list_format_size_bytes);
1892
1893         /* setup unique_indirect_regs array and indirect_start_offsets array */
1894         unique_indirect_reg_count = ARRAY_SIZE(unique_indirect_regs);
1895         gfx_v9_1_parse_ind_reg_list(register_list_format,
1896                                     adev->gfx.rlc.reg_list_format_direct_reg_list_length,
1897                                     adev->gfx.rlc.reg_list_format_size_bytes >> 2,
1898                                     unique_indirect_regs,
1899                                     unique_indirect_reg_count,
1900                                     indirect_start_offsets,
1901                                     &indirect_start_offsets_count,
1902                                     ARRAY_SIZE(indirect_start_offsets));
1903
1904         /* enable auto inc in case it is disabled */
1905         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
1906         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
1907         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
1908
1909         /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */
1910         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR),
1911                 RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET);
1912         for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
1913                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
1914                         adev->gfx.rlc.register_restore[i]);
1915
1916         /* load indirect register */
1917         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1918                 adev->gfx.rlc.reg_list_format_start);
1919
1920         /* direct register portion */
1921         for (i = 0; i < adev->gfx.rlc.reg_list_format_direct_reg_list_length; i++)
1922                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
1923                         register_list_format[i]);
1924
1925         /* indirect register portion */
1926         while (i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2)) {
1927                 if (register_list_format[i] == 0xFFFFFFFF) {
1928                         WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
1929                         continue;
1930                 }
1931
1932                 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
1933                 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
1934
1935                 for (j = 0; j < unique_indirect_reg_count; j++) {
1936                         if (register_list_format[i] == unique_indirect_regs[j]) {
1937                                 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, j);
1938                                 break;
1939                         }
1940                 }
1941
1942                 BUG_ON(j >= unique_indirect_reg_count);
1943
1944                 i++;
1945         }
1946
1947         /* set save/restore list size */
1948         list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
1949         list_size = list_size >> 1;
1950         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1951                 adev->gfx.rlc.reg_restore_list_size);
1952         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size);
1953
1954         /* write the starting offsets to RLC scratch ram */
1955         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1956                 adev->gfx.rlc.starting_offsets_start);
1957         for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++)
1958                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
1959                        indirect_start_offsets[i]);
1960
1961         /* load unique indirect regs*/
1962         for (i = 0; i < ARRAY_SIZE(unique_indirect_regs); i++) {
1963                 if (unique_indirect_regs[i] != 0) {
1964                         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0)
1965                                + GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[i],
1966                                unique_indirect_regs[i] & 0x3FFFF);
1967
1968                         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0)
1969                                + GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[i],
1970                                unique_indirect_regs[i] >> 20);
1971                 }
1972         }
1973
1974         kfree(register_list_format);
1975         return 0;
1976 }
1977
1978 static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev)
1979 {
1980         WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1);
1981 }
1982
1983 static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev,
1984                                              bool enable)
1985 {
1986         uint32_t data = 0;
1987         uint32_t default_data = 0;
1988
1989         default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS));
1990         if (enable == true) {
1991                 /* enable GFXIP control over CGPG */
1992                 data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
1993                 if(default_data != data)
1994                         WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
1995
1996                 /* update status */
1997                 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK;
1998                 data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT);
1999                 if(default_data != data)
2000                         WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
2001         } else {
2002                 /* restore GFXIP control over GCPG */
2003                 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
2004                 if(default_data != data)
2005                         WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
2006         }
2007 }
2008
2009 static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev)
2010 {
2011         uint32_t data = 0;
2012
2013         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2014                               AMD_PG_SUPPORT_GFX_SMG |
2015                               AMD_PG_SUPPORT_GFX_DMG)) {
2016                 /* init IDLE_POLL_COUNT = 60 */
2017                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));
2018                 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
2019                 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
2020                 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data);
2021
2022                 /* init RLC PG Delay */
2023                 data = 0;
2024                 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT);
2025                 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT);
2026                 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT);
2027                 data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT);
2028                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data);
2029
2030                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2));
2031                 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK;
2032                 data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT);
2033                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data);
2034
2035                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3));
2036                 data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK;
2037                 data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT);
2038                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data);
2039
2040                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL));
2041                 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
2042
2043                 /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */
2044                 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
2045                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data);
2046
2047                 pwr_10_0_gfxip_control_over_cgpg(adev, true);
2048         }
2049 }
2050
2051 static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
2052                                                 bool enable)
2053 {
2054         uint32_t data = 0;
2055         uint32_t default_data = 0;
2056
2057         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2058         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2059                              SMU_CLK_SLOWDOWN_ON_PU_ENABLE,
2060                              enable ? 1 : 0);
2061         if (default_data != data)
2062                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2063 }
2064
2065 static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
2066                                                 bool enable)
2067 {
2068         uint32_t data = 0;
2069         uint32_t default_data = 0;
2070
2071         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2072         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2073                              SMU_CLK_SLOWDOWN_ON_PD_ENABLE,
2074                              enable ? 1 : 0);
2075         if(default_data != data)
2076                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2077 }
2078
2079 static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev,
2080                                         bool enable)
2081 {
2082         uint32_t data = 0;
2083         uint32_t default_data = 0;
2084
2085         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2086         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2087                              CP_PG_DISABLE,
2088                              enable ? 0 : 1);
2089         if(default_data != data)
2090                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2091 }
2092
2093 static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
2094                                                 bool enable)
2095 {
2096         uint32_t data, default_data;
2097
2098         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2099         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2100                              GFX_POWER_GATING_ENABLE,
2101                              enable ? 1 : 0);
2102         if(default_data != data)
2103                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2104 }
2105
2106 static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev,
2107                                                 bool enable)
2108 {
2109         uint32_t data, default_data;
2110
2111         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2112         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2113                              GFX_PIPELINE_PG_ENABLE,
2114                              enable ? 1 : 0);
2115         if(default_data != data)
2116                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2117
2118         if (!enable)
2119                 /* read any GFX register to wake up GFX */
2120                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL));
2121 }
2122
2123 static void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
2124                                                        bool enable)
2125 {
2126         uint32_t data, default_data;
2127
2128         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2129         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2130                              STATIC_PER_CU_PG_ENABLE,
2131                              enable ? 1 : 0);
2132         if(default_data != data)
2133                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2134 }
2135
2136 static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
2137                                                 bool enable)
2138 {
2139         uint32_t data, default_data;
2140
2141         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2142         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2143                              DYN_PER_CU_PG_ENABLE,
2144                              enable ? 1 : 0);
2145         if(default_data != data)
2146                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2147 }
2148
2149 static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
2150 {
2151         if (!adev->gfx.rlc.is_rlc_v2_1)
2152                 return;
2153
2154         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2155                               AMD_PG_SUPPORT_GFX_SMG |
2156                               AMD_PG_SUPPORT_GFX_DMG |
2157                               AMD_PG_SUPPORT_CP |
2158                               AMD_PG_SUPPORT_GDS |
2159                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
2160                 gfx_v9_0_init_csb(adev);
2161                 gfx_v9_1_init_rlc_save_restore_list(adev);
2162                 gfx_v9_0_enable_save_restore_machine(adev);
2163
2164                 WREG32(mmRLC_JUMP_TABLE_RESTORE,
2165                        adev->gfx.rlc.cp_table_gpu_addr >> 8);
2166                 gfx_v9_0_init_gfx_power_gating(adev);
2167         }
2168 }
2169
2170 void gfx_v9_0_rlc_stop(struct amdgpu_device *adev)
2171 {
2172         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0);
2173         gfx_v9_0_enable_gui_idle_interrupt(adev, false);
2174         gfx_v9_0_wait_for_rlc_serdes(adev);
2175 }
2176
2177 static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev)
2178 {
2179         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2180         udelay(50);
2181         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2182         udelay(50);
2183 }
2184
2185 static void gfx_v9_0_rlc_start(struct amdgpu_device *adev)
2186 {
2187 #ifdef AMDGPU_RLC_DEBUG_RETRY
2188         u32 rlc_ucode_ver;
2189 #endif
2190
2191         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
2192
2193         /* carrizo do enable cp interrupt after cp inited */
2194         if (!(adev->flags & AMD_IS_APU))
2195                 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
2196
2197         udelay(50);
2198
2199 #ifdef AMDGPU_RLC_DEBUG_RETRY
2200         /* RLC_GPM_GENERAL_6 : RLC Ucode version */
2201         rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6);
2202         if(rlc_ucode_ver == 0x108) {
2203                 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n",
2204                                 rlc_ucode_ver, adev->gfx.rlc_fw_version);
2205                 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles,
2206                  * default is 0x9C4 to create a 100us interval */
2207                 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4);
2208                 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
2209                  * to disable the page fault retry interrupts, default is
2210                  * 0x100 (256) */
2211                 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100);
2212         }
2213 #endif
2214 }
2215
2216 static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev)
2217 {
2218         const struct rlc_firmware_header_v2_0 *hdr;
2219         const __le32 *fw_data;
2220         unsigned i, fw_size;
2221
2222         if (!adev->gfx.rlc_fw)
2223                 return -EINVAL;
2224
2225         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2226         amdgpu_ucode_print_rlc_hdr(&hdr->header);
2227
2228         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2229                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2230         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2231
2232         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
2233                         RLCG_UCODE_LOADING_START_ADDRESS);
2234         for (i = 0; i < fw_size; i++)
2235                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
2236         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
2237
2238         return 0;
2239 }
2240
2241 static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
2242 {
2243         int r;
2244
2245         if (amdgpu_sriov_vf(adev)) {
2246                 gfx_v9_0_init_csb(adev);
2247                 return 0;
2248         }
2249
2250         gfx_v9_0_rlc_stop(adev);
2251
2252         /* disable CG */
2253         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
2254
2255         /* disable PG */
2256         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
2257
2258         gfx_v9_0_rlc_reset(adev);
2259
2260         gfx_v9_0_init_pg(adev);
2261
2262         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2263                 /* legacy rlc firmware loading */
2264                 r = gfx_v9_0_rlc_load_microcode(adev);
2265                 if (r)
2266                         return r;
2267         }
2268
2269         if (adev->asic_type == CHIP_RAVEN) {
2270                 if (amdgpu_lbpw != 0)
2271                         gfx_v9_0_enable_lbpw(adev, true);
2272                 else
2273                         gfx_v9_0_enable_lbpw(adev, false);
2274         }
2275
2276         gfx_v9_0_rlc_start(adev);
2277
2278         return 0;
2279 }
2280
2281 static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2282 {
2283         int i;
2284         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
2285
2286         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2287         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2288         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
2289         if (!enable) {
2290                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2291                         adev->gfx.gfx_ring[i].ready = false;
2292         }
2293         WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
2294         udelay(50);
2295 }
2296
2297 static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2298 {
2299         const struct gfx_firmware_header_v1_0 *pfp_hdr;
2300         const struct gfx_firmware_header_v1_0 *ce_hdr;
2301         const struct gfx_firmware_header_v1_0 *me_hdr;
2302         const __le32 *fw_data;
2303         unsigned i, fw_size;
2304
2305         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2306                 return -EINVAL;
2307
2308         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2309                 adev->gfx.pfp_fw->data;
2310         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2311                 adev->gfx.ce_fw->data;
2312         me_hdr = (const struct gfx_firmware_header_v1_0 *)
2313                 adev->gfx.me_fw->data;
2314
2315         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2316         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2317         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2318
2319         gfx_v9_0_cp_gfx_enable(adev, false);
2320
2321         /* PFP */
2322         fw_data = (const __le32 *)
2323                 (adev->gfx.pfp_fw->data +
2324                  le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2325         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2326         WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0);
2327         for (i = 0; i < fw_size; i++)
2328                 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2329         WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2330
2331         /* CE */
2332         fw_data = (const __le32 *)
2333                 (adev->gfx.ce_fw->data +
2334                  le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2335         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2336         WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0);
2337         for (i = 0; i < fw_size; i++)
2338                 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2339         WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2340
2341         /* ME */
2342         fw_data = (const __le32 *)
2343                 (adev->gfx.me_fw->data +
2344                  le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2345         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2346         WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0);
2347         for (i = 0; i < fw_size; i++)
2348                 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2349         WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2350
2351         return 0;
2352 }
2353
2354 static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)
2355 {
2356         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2357         const struct cs_section_def *sect = NULL;
2358         const struct cs_extent_def *ext = NULL;
2359         int r, i, tmp;
2360
2361         /* init the CP */
2362         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2363         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
2364
2365         gfx_v9_0_cp_gfx_enable(adev, true);
2366
2367         r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3);
2368         if (r) {
2369                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2370                 return r;
2371         }
2372
2373         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2374         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2375
2376         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2377         amdgpu_ring_write(ring, 0x80000000);
2378         amdgpu_ring_write(ring, 0x80000000);
2379
2380         for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
2381                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2382                         if (sect->id == SECT_CONTEXT) {
2383                                 amdgpu_ring_write(ring,
2384                                        PACKET3(PACKET3_SET_CONTEXT_REG,
2385                                                ext->reg_count));
2386                                 amdgpu_ring_write(ring,
2387                                        ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2388                                 for (i = 0; i < ext->reg_count; i++)
2389                                         amdgpu_ring_write(ring, ext->extent[i]);
2390                         }
2391                 }
2392         }
2393
2394         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2395         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2396
2397         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2398         amdgpu_ring_write(ring, 0);
2399
2400         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2401         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2402         amdgpu_ring_write(ring, 0x8000);
2403         amdgpu_ring_write(ring, 0x8000);
2404
2405         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1));
2406         tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE |
2407                 (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START));
2408         amdgpu_ring_write(ring, tmp);
2409         amdgpu_ring_write(ring, 0);
2410
2411         amdgpu_ring_commit(ring);
2412
2413         return 0;
2414 }
2415
2416 static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
2417 {
2418         struct amdgpu_ring *ring;
2419         u32 tmp;
2420         u32 rb_bufsz;
2421         u64 rb_addr, rptr_addr, wptr_gpu_addr;
2422
2423         /* Set the write pointer delay */
2424         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
2425
2426         /* set the RB to use vmid 0 */
2427         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
2428
2429         /* Set ring buffer size */
2430         ring = &adev->gfx.gfx_ring[0];
2431         rb_bufsz = order_base_2(ring->ring_size / 8);
2432         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2433         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2434 #ifdef __BIG_ENDIAN
2435         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
2436 #endif
2437         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2438
2439         /* Initialize the ring buffer's write pointers */
2440         ring->wptr = 0;
2441         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2442         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
2443
2444         /* set the wb address wether it's enabled or not */
2445         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2446         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2447         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
2448
2449         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2450         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
2451         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
2452
2453         mdelay(1);
2454         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2455
2456         rb_addr = ring->gpu_addr >> 8;
2457         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
2458         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2459
2460         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
2461         if (ring->use_doorbell) {
2462                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2463                                     DOORBELL_OFFSET, ring->doorbell_index);
2464                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2465                                     DOORBELL_EN, 1);
2466         } else {
2467                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
2468         }
2469         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
2470
2471         tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2472                         DOORBELL_RANGE_LOWER, ring->doorbell_index);
2473         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
2474
2475         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
2476                        CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2477
2478
2479         /* start the ring */
2480         gfx_v9_0_cp_gfx_start(adev);
2481         ring->ready = true;
2482
2483         return 0;
2484 }
2485
2486 static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2487 {
2488         int i;
2489
2490         if (enable) {
2491                 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
2492         } else {
2493                 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
2494                         (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2495                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2496                         adev->gfx.compute_ring[i].ready = false;
2497                 adev->gfx.kiq.ring.ready = false;
2498         }
2499         udelay(50);
2500 }
2501
2502 static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2503 {
2504         const struct gfx_firmware_header_v1_0 *mec_hdr;
2505         const __le32 *fw_data;
2506         unsigned i;
2507         u32 tmp;
2508
2509         if (!adev->gfx.mec_fw)
2510                 return -EINVAL;
2511
2512         gfx_v9_0_cp_compute_enable(adev, false);
2513
2514         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2515         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2516
2517         fw_data = (const __le32 *)
2518                 (adev->gfx.mec_fw->data +
2519                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2520         tmp = 0;
2521         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
2522         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
2523         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
2524
2525         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
2526                 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
2527         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
2528                 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
2529
2530         /* MEC1 */
2531         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
2532                          mec_hdr->jt_offset);
2533         for (i = 0; i < mec_hdr->jt_size; i++)
2534                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
2535                         le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
2536
2537         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
2538                         adev->gfx.mec_fw_version);
2539         /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
2540
2541         return 0;
2542 }
2543
2544 /* KIQ functions */
2545 static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
2546 {
2547         uint32_t tmp;
2548         struct amdgpu_device *adev = ring->adev;
2549
2550         /* tell RLC which is KIQ queue */
2551         tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
2552         tmp &= 0xffffff00;
2553         tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
2554         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2555         tmp |= 0x80;
2556         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2557 }
2558
2559 static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev)
2560 {
2561         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
2562         uint32_t scratch, tmp = 0;
2563         uint64_t queue_mask = 0;
2564         int r, i;
2565
2566         for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
2567                 if (!test_bit(i, adev->gfx.mec.queue_bitmap))
2568                         continue;
2569
2570                 /* This situation may be hit in the future if a new HW
2571                  * generation exposes more than 64 queues. If so, the
2572                  * definition of queue_mask needs updating */
2573                 if (WARN_ON(i >= (sizeof(queue_mask)*8))) {
2574                         DRM_ERROR("Invalid KCQ enabled: %d\n", i);
2575                         break;
2576                 }
2577
2578                 queue_mask |= (1ull << i);
2579         }
2580
2581         r = amdgpu_gfx_scratch_get(adev, &scratch);
2582         if (r) {
2583                 DRM_ERROR("Failed to get scratch reg (%d).\n", r);
2584                 return r;
2585         }
2586         WREG32(scratch, 0xCAFEDEAD);
2587
2588         r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 11);
2589         if (r) {
2590                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
2591                 amdgpu_gfx_scratch_free(adev, scratch);
2592                 return r;
2593         }
2594
2595         /* set resources */
2596         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
2597         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
2598                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
2599         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
2600         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
2601         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
2602         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
2603         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
2604         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
2605         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2606                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2607                 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
2608                 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2609
2610                 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
2611                 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
2612                 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
2613                                   PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
2614                                   PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
2615                                   PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
2616                                   PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
2617                                   PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
2618                                   PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
2619                                   PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
2620                                   PACKET3_MAP_QUEUES_ENGINE_SEL(0) | /* engine_sel: compute */
2621                                   PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
2622                 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
2623                 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
2624                 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
2625                 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
2626                 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
2627         }
2628         /* write to scratch for completion */
2629         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2630         amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2631         amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
2632         amdgpu_ring_commit(kiq_ring);
2633
2634         for (i = 0; i < adev->usec_timeout; i++) {
2635                 tmp = RREG32(scratch);
2636                 if (tmp == 0xDEADBEEF)
2637                         break;
2638                 DRM_UDELAY(1);
2639         }
2640         if (i >= adev->usec_timeout) {
2641                 DRM_ERROR("KCQ enable failed (scratch(0x%04X)=0x%08X)\n",
2642                           scratch, tmp);
2643                 r = -EINVAL;
2644         }
2645         amdgpu_gfx_scratch_free(adev, scratch);
2646
2647         return r;
2648 }
2649
2650 static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
2651 {
2652         struct amdgpu_device *adev = ring->adev;
2653         struct v9_mqd *mqd = ring->mqd_ptr;
2654         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
2655         uint32_t tmp;
2656
2657         mqd->header = 0xC0310800;
2658         mqd->compute_pipelinestat_enable = 0x00000001;
2659         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
2660         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
2661         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
2662         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
2663         mqd->compute_misc_reserved = 0x00000003;
2664
2665         mqd->dynamic_cu_mask_addr_lo =
2666                 lower_32_bits(ring->mqd_gpu_addr
2667                               + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
2668         mqd->dynamic_cu_mask_addr_hi =
2669                 upper_32_bits(ring->mqd_gpu_addr
2670                               + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
2671
2672         eop_base_addr = ring->eop_gpu_addr >> 8;
2673         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
2674         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
2675
2676         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2677         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
2678         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
2679                         (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1));
2680
2681         mqd->cp_hqd_eop_control = tmp;
2682
2683         /* enable doorbell? */
2684         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
2685
2686         if (ring->use_doorbell) {
2687                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2688                                     DOORBELL_OFFSET, ring->doorbell_index);
2689                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2690                                     DOORBELL_EN, 1);
2691                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2692                                     DOORBELL_SOURCE, 0);
2693                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2694                                     DOORBELL_HIT, 0);
2695         } else {
2696                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2697                                          DOORBELL_EN, 0);
2698         }
2699
2700         mqd->cp_hqd_pq_doorbell_control = tmp;
2701
2702         /* disable the queue if it's active */
2703         ring->wptr = 0;
2704         mqd->cp_hqd_dequeue_request = 0;
2705         mqd->cp_hqd_pq_rptr = 0;
2706         mqd->cp_hqd_pq_wptr_lo = 0;
2707         mqd->cp_hqd_pq_wptr_hi = 0;
2708
2709         /* set the pointer to the MQD */
2710         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
2711         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
2712
2713         /* set MQD vmid to 0 */
2714         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
2715         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
2716         mqd->cp_mqd_control = tmp;
2717
2718         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2719         hqd_gpu_addr = ring->gpu_addr >> 8;
2720         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
2721         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
2722
2723         /* set up the HQD, this is similar to CP_RB0_CNTL */
2724         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
2725         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
2726                             (order_base_2(ring->ring_size / 4) - 1));
2727         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
2728                         ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
2729 #ifdef __BIG_ENDIAN
2730         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
2731 #endif
2732         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
2733         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
2734         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
2735         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
2736         mqd->cp_hqd_pq_control = tmp;
2737
2738         /* set the wb address whether it's enabled or not */
2739         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2740         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
2741         mqd->cp_hqd_pq_rptr_report_addr_hi =
2742                 upper_32_bits(wb_gpu_addr) & 0xffff;
2743
2744         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2745         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2746         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
2747         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
2748
2749         tmp = 0;
2750         /* enable the doorbell if requested */
2751         if (ring->use_doorbell) {
2752                 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
2753                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2754                                 DOORBELL_OFFSET, ring->doorbell_index);
2755
2756                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2757                                          DOORBELL_EN, 1);
2758                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2759                                          DOORBELL_SOURCE, 0);
2760                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2761                                          DOORBELL_HIT, 0);
2762         }
2763
2764         mqd->cp_hqd_pq_doorbell_control = tmp;
2765
2766         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2767         ring->wptr = 0;
2768         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
2769
2770         /* set the vmid for the queue */
2771         mqd->cp_hqd_vmid = 0;
2772
2773         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
2774         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
2775         mqd->cp_hqd_persistent_state = tmp;
2776
2777         /* set MIN_IB_AVAIL_SIZE */
2778         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
2779         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
2780         mqd->cp_hqd_ib_control = tmp;
2781
2782         /* activate the queue */
2783         mqd->cp_hqd_active = 1;
2784
2785         return 0;
2786 }
2787
2788 static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
2789 {
2790         struct amdgpu_device *adev = ring->adev;
2791         struct v9_mqd *mqd = ring->mqd_ptr;
2792         int j;
2793
2794         /* disable wptr polling */
2795         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
2796
2797         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
2798                mqd->cp_hqd_eop_base_addr_lo);
2799         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
2800                mqd->cp_hqd_eop_base_addr_hi);
2801
2802         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2803         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
2804                mqd->cp_hqd_eop_control);
2805
2806         /* enable doorbell? */
2807         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
2808                mqd->cp_hqd_pq_doorbell_control);
2809
2810         /* disable the queue if it's active */
2811         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
2812                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
2813                 for (j = 0; j < adev->usec_timeout; j++) {
2814                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
2815                                 break;
2816                         udelay(1);
2817                 }
2818                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
2819                        mqd->cp_hqd_dequeue_request);
2820                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
2821                        mqd->cp_hqd_pq_rptr);
2822                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
2823                        mqd->cp_hqd_pq_wptr_lo);
2824                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
2825                        mqd->cp_hqd_pq_wptr_hi);
2826         }
2827
2828         /* set the pointer to the MQD */
2829         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
2830                mqd->cp_mqd_base_addr_lo);
2831         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
2832                mqd->cp_mqd_base_addr_hi);
2833
2834         /* set MQD vmid to 0 */
2835         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
2836                mqd->cp_mqd_control);
2837
2838         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2839         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
2840                mqd->cp_hqd_pq_base_lo);
2841         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
2842                mqd->cp_hqd_pq_base_hi);
2843
2844         /* set up the HQD, this is similar to CP_RB0_CNTL */
2845         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
2846                mqd->cp_hqd_pq_control);
2847
2848         /* set the wb address whether it's enabled or not */
2849         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
2850                                 mqd->cp_hqd_pq_rptr_report_addr_lo);
2851         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
2852                                 mqd->cp_hqd_pq_rptr_report_addr_hi);
2853
2854         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2855         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
2856                mqd->cp_hqd_pq_wptr_poll_addr_lo);
2857         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
2858                mqd->cp_hqd_pq_wptr_poll_addr_hi);
2859
2860         /* enable the doorbell if requested */
2861         if (ring->use_doorbell) {
2862                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
2863                                         (AMDGPU_DOORBELL64_KIQ *2) << 2);
2864                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
2865                                         (AMDGPU_DOORBELL64_USERQUEUE_END * 2) << 2);
2866         }
2867
2868         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
2869                mqd->cp_hqd_pq_doorbell_control);
2870
2871         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2872         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
2873                mqd->cp_hqd_pq_wptr_lo);
2874         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
2875                mqd->cp_hqd_pq_wptr_hi);
2876
2877         /* set the vmid for the queue */
2878         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
2879
2880         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
2881                mqd->cp_hqd_persistent_state);
2882
2883         /* activate the queue */
2884         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
2885                mqd->cp_hqd_active);
2886
2887         if (ring->use_doorbell)
2888                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
2889
2890         return 0;
2891 }
2892
2893 static int gfx_v9_0_kiq_fini_register(struct amdgpu_ring *ring)
2894 {
2895         struct amdgpu_device *adev = ring->adev;
2896         int j;
2897
2898         /* disable the queue if it's active */
2899         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
2900
2901                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
2902
2903                 for (j = 0; j < adev->usec_timeout; j++) {
2904                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
2905                                 break;
2906                         udelay(1);
2907                 }
2908
2909                 if (j == AMDGPU_MAX_USEC_TIMEOUT) {
2910                         DRM_DEBUG("KIQ dequeue request failed.\n");
2911
2912                         /* Manual disable if dequeue request times out */
2913                         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
2914                 }
2915
2916                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
2917                       0);
2918         }
2919
2920         WREG32_SOC15(GC, 0, mmCP_HQD_IQ_TIMER, 0);
2921         WREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL, 0);
2922         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 0);
2923         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000);
2924         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
2925         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 0);
2926         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0);
2927         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 0);
2928
2929         return 0;
2930 }
2931
2932 static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
2933 {
2934         struct amdgpu_device *adev = ring->adev;
2935         struct v9_mqd *mqd = ring->mqd_ptr;
2936         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
2937
2938         gfx_v9_0_kiq_setting(ring);
2939
2940         if (adev->in_gpu_reset) { /* for GPU_RESET case */
2941                 /* reset MQD to a clean status */
2942                 if (adev->gfx.mec.mqd_backup[mqd_idx])
2943                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
2944
2945                 /* reset ring buffer */
2946                 ring->wptr = 0;
2947                 amdgpu_ring_clear_ring(ring);
2948
2949                 mutex_lock(&adev->srbm_mutex);
2950                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2951                 gfx_v9_0_kiq_init_register(ring);
2952                 soc15_grbm_select(adev, 0, 0, 0, 0);
2953                 mutex_unlock(&adev->srbm_mutex);
2954         } else {
2955                 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
2956                 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
2957                 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
2958                 mutex_lock(&adev->srbm_mutex);
2959                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2960                 gfx_v9_0_mqd_init(ring);
2961                 gfx_v9_0_kiq_init_register(ring);
2962                 soc15_grbm_select(adev, 0, 0, 0, 0);
2963                 mutex_unlock(&adev->srbm_mutex);
2964
2965                 if (adev->gfx.mec.mqd_backup[mqd_idx])
2966                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
2967         }
2968
2969         return 0;
2970 }
2971
2972 static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
2973 {
2974         struct amdgpu_device *adev = ring->adev;
2975         struct v9_mqd *mqd = ring->mqd_ptr;
2976         int mqd_idx = ring - &adev->gfx.compute_ring[0];
2977
2978         if (!adev->in_gpu_reset && !adev->gfx.in_suspend) {
2979                 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
2980                 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
2981                 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
2982                 mutex_lock(&adev->srbm_mutex);
2983                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2984                 gfx_v9_0_mqd_init(ring);
2985                 soc15_grbm_select(adev, 0, 0, 0, 0);
2986                 mutex_unlock(&adev->srbm_mutex);
2987
2988                 if (adev->gfx.mec.mqd_backup[mqd_idx])
2989                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
2990         } else if (adev->in_gpu_reset) { /* for GPU_RESET case */
2991                 /* reset MQD to a clean status */
2992                 if (adev->gfx.mec.mqd_backup[mqd_idx])
2993                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
2994
2995                 /* reset ring buffer */
2996                 ring->wptr = 0;
2997                 amdgpu_ring_clear_ring(ring);
2998         } else {
2999                 amdgpu_ring_clear_ring(ring);
3000         }
3001
3002         return 0;
3003 }
3004
3005 static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)
3006 {
3007         struct amdgpu_ring *ring = NULL;
3008         int r = 0, i;
3009
3010         gfx_v9_0_cp_compute_enable(adev, true);
3011
3012         ring = &adev->gfx.kiq.ring;
3013
3014         r = amdgpu_bo_reserve(ring->mqd_obj, false);
3015         if (unlikely(r != 0))
3016                 goto done;
3017
3018         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3019         if (!r) {
3020                 r = gfx_v9_0_kiq_init_queue(ring);
3021                 amdgpu_bo_kunmap(ring->mqd_obj);
3022                 ring->mqd_ptr = NULL;
3023         }
3024         amdgpu_bo_unreserve(ring->mqd_obj);
3025         if (r)
3026                 goto done;
3027
3028         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3029                 ring = &adev->gfx.compute_ring[i];
3030
3031                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3032                 if (unlikely(r != 0))
3033                         goto done;
3034                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3035                 if (!r) {
3036                         r = gfx_v9_0_kcq_init_queue(ring);
3037                         amdgpu_bo_kunmap(ring->mqd_obj);
3038                         ring->mqd_ptr = NULL;
3039                 }
3040                 amdgpu_bo_unreserve(ring->mqd_obj);
3041                 if (r)
3042                         goto done;
3043         }
3044
3045         r = gfx_v9_0_kiq_kcq_enable(adev);
3046 done:
3047         return r;
3048 }
3049
3050 static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
3051 {
3052         int r, i;
3053         struct amdgpu_ring *ring;
3054
3055         if (!(adev->flags & AMD_IS_APU))
3056                 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
3057
3058         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
3059                 /* legacy firmware loading */
3060                 r = gfx_v9_0_cp_gfx_load_microcode(adev);
3061                 if (r)
3062                         return r;
3063
3064                 r = gfx_v9_0_cp_compute_load_microcode(adev);
3065                 if (r)
3066                         return r;
3067         }
3068
3069         r = gfx_v9_0_cp_gfx_resume(adev);
3070         if (r)
3071                 return r;
3072
3073         r = gfx_v9_0_kiq_resume(adev);
3074         if (r)
3075                 return r;
3076
3077         ring = &adev->gfx.gfx_ring[0];
3078         r = amdgpu_ring_test_ring(ring);
3079         if (r) {
3080                 ring->ready = false;
3081                 return r;
3082         }
3083
3084         ring = &adev->gfx.kiq.ring;
3085         ring->ready = true;
3086         r = amdgpu_ring_test_ring(ring);
3087         if (r)
3088                 ring->ready = false;
3089
3090         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3091                 ring = &adev->gfx.compute_ring[i];
3092
3093                 ring->ready = true;
3094                 r = amdgpu_ring_test_ring(ring);
3095                 if (r)
3096                         ring->ready = false;
3097         }
3098
3099         gfx_v9_0_enable_gui_idle_interrupt(adev, true);
3100
3101         return 0;
3102 }
3103
3104 static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
3105 {
3106         gfx_v9_0_cp_gfx_enable(adev, enable);
3107         gfx_v9_0_cp_compute_enable(adev, enable);
3108 }
3109
3110 static int gfx_v9_0_hw_init(void *handle)
3111 {
3112         int r;
3113         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3114
3115         gfx_v9_0_init_golden_registers(adev);
3116
3117         gfx_v9_0_gpu_init(adev);
3118
3119         r = gfx_v9_0_rlc_resume(adev);
3120         if (r)
3121                 return r;
3122
3123         r = gfx_v9_0_cp_resume(adev);
3124         if (r)
3125                 return r;
3126
3127         r = gfx_v9_0_ngg_en(adev);
3128         if (r)
3129                 return r;
3130
3131         return r;
3132 }
3133
3134 static int gfx_v9_0_kcq_disable(struct amdgpu_ring *kiq_ring,struct amdgpu_ring *ring)
3135 {
3136         struct amdgpu_device *adev = kiq_ring->adev;
3137         uint32_t scratch, tmp = 0;
3138         int r, i;
3139
3140         r = amdgpu_gfx_scratch_get(adev, &scratch);
3141         if (r) {
3142                 DRM_ERROR("Failed to get scratch reg (%d).\n", r);
3143                 return r;
3144         }
3145         WREG32(scratch, 0xCAFEDEAD);
3146
3147         r = amdgpu_ring_alloc(kiq_ring, 10);
3148         if (r) {
3149                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
3150                 amdgpu_gfx_scratch_free(adev, scratch);
3151                 return r;
3152         }
3153
3154         /* unmap queues */
3155         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3156         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3157                                                 PACKET3_UNMAP_QUEUES_ACTION(1) | /* RESET_QUEUES */
3158                                                 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3159                                                 PACKET3_UNMAP_QUEUES_ENGINE_SEL(0) |
3160                                                 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3161         amdgpu_ring_write(kiq_ring, PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3162         amdgpu_ring_write(kiq_ring, 0);
3163         amdgpu_ring_write(kiq_ring, 0);
3164         amdgpu_ring_write(kiq_ring, 0);
3165         /* write to scratch for completion */
3166         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3167         amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
3168         amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
3169         amdgpu_ring_commit(kiq_ring);
3170
3171         for (i = 0; i < adev->usec_timeout; i++) {
3172                 tmp = RREG32(scratch);
3173                 if (tmp == 0xDEADBEEF)
3174                         break;
3175                 DRM_UDELAY(1);
3176         }
3177         if (i >= adev->usec_timeout) {
3178                 DRM_ERROR("KCQ disabled failed (scratch(0x%04X)=0x%08X)\n", scratch, tmp);
3179                 r = -EINVAL;
3180         }
3181         amdgpu_gfx_scratch_free(adev, scratch);
3182         return r;
3183 }
3184
3185 static int gfx_v9_0_hw_fini(void *handle)
3186 {
3187         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3188         int i;
3189
3190         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_GFX,
3191                                                AMD_PG_STATE_UNGATE);
3192
3193         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
3194         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
3195
3196         /* disable KCQ to avoid CPC touch memory not valid anymore */
3197         for (i = 0; i < adev->gfx.num_compute_rings; i++)
3198                 gfx_v9_0_kcq_disable(&adev->gfx.kiq.ring, &adev->gfx.compute_ring[i]);
3199
3200         if (amdgpu_sriov_vf(adev)) {
3201                 gfx_v9_0_cp_gfx_enable(adev, false);
3202                 /* must disable polling for SRIOV when hw finished, otherwise
3203                  * CPC engine may still keep fetching WB address which is already
3204                  * invalid after sw finished and trigger DMAR reading error in
3205                  * hypervisor side.
3206                  */
3207                 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3208                 return 0;
3209         }
3210
3211         /* Use deinitialize sequence from CAIL when unbinding device from driver,
3212          * otherwise KIQ is hanging when binding back
3213          */
3214         if (!adev->in_gpu_reset && !adev->gfx.in_suspend) {
3215                 mutex_lock(&adev->srbm_mutex);
3216                 soc15_grbm_select(adev, adev->gfx.kiq.ring.me,
3217                                 adev->gfx.kiq.ring.pipe,
3218                                 adev->gfx.kiq.ring.queue, 0);
3219                 gfx_v9_0_kiq_fini_register(&adev->gfx.kiq.ring);
3220                 soc15_grbm_select(adev, 0, 0, 0, 0);
3221                 mutex_unlock(&adev->srbm_mutex);
3222         }
3223
3224         gfx_v9_0_cp_enable(adev, false);
3225         gfx_v9_0_rlc_stop(adev);
3226
3227         return 0;
3228 }
3229
3230 static int gfx_v9_0_suspend(void *handle)
3231 {
3232         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3233
3234         adev->gfx.in_suspend = true;
3235         return gfx_v9_0_hw_fini(adev);
3236 }
3237
3238 static int gfx_v9_0_resume(void *handle)
3239 {
3240         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3241         int r;
3242
3243         r = gfx_v9_0_hw_init(adev);
3244         adev->gfx.in_suspend = false;
3245         return r;
3246 }
3247
3248 static bool gfx_v9_0_is_idle(void *handle)
3249 {
3250         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3251
3252         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
3253                                 GRBM_STATUS, GUI_ACTIVE))
3254                 return false;
3255         else
3256                 return true;
3257 }
3258
3259 static int gfx_v9_0_wait_for_idle(void *handle)
3260 {
3261         unsigned i;
3262         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3263
3264         for (i = 0; i < adev->usec_timeout; i++) {
3265                 if (gfx_v9_0_is_idle(handle))
3266                         return 0;
3267                 udelay(1);
3268         }
3269         return -ETIMEDOUT;
3270 }
3271
3272 static int gfx_v9_0_soft_reset(void *handle)
3273 {
3274         u32 grbm_soft_reset = 0;
3275         u32 tmp;
3276         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3277
3278         /* GRBM_STATUS */
3279         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
3280         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
3281                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
3282                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
3283                    GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
3284                    GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
3285                    GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
3286                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3287                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3288                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3289                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
3290         }
3291
3292         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
3293                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3294                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3295         }
3296
3297         /* GRBM_STATUS2 */
3298         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
3299         if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
3300                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3301                                                 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
3302
3303
3304         if (grbm_soft_reset) {
3305                 /* stop the rlc */
3306                 gfx_v9_0_rlc_stop(adev);
3307
3308                 /* Disable GFX parsing/prefetching */
3309                 gfx_v9_0_cp_gfx_enable(adev, false);
3310
3311                 /* Disable MEC parsing/prefetching */
3312                 gfx_v9_0_cp_compute_enable(adev, false);
3313
3314                 if (grbm_soft_reset) {
3315                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3316                         tmp |= grbm_soft_reset;
3317                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3318                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3319                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3320
3321                         udelay(50);
3322
3323                         tmp &= ~grbm_soft_reset;
3324                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3325                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3326                 }
3327
3328                 /* Wait a little for things to settle down */
3329                 udelay(50);
3330         }
3331         return 0;
3332 }
3333
3334 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3335 {
3336         uint64_t clock;
3337
3338         mutex_lock(&adev->gfx.gpu_clock_mutex);
3339         WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3340         clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
3341                 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3342         mutex_unlock(&adev->gfx.gpu_clock_mutex);
3343         return clock;
3344 }
3345
3346 static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3347                                           uint32_t vmid,
3348                                           uint32_t gds_base, uint32_t gds_size,
3349                                           uint32_t gws_base, uint32_t gws_size,
3350                                           uint32_t oa_base, uint32_t oa_size)
3351 {
3352         struct amdgpu_device *adev = ring->adev;
3353
3354         gds_base = gds_base >> AMDGPU_GDS_SHIFT;
3355         gds_size = gds_size >> AMDGPU_GDS_SHIFT;
3356
3357         gws_base = gws_base >> AMDGPU_GWS_SHIFT;
3358         gws_size = gws_size >> AMDGPU_GWS_SHIFT;
3359
3360         oa_base = oa_base >> AMDGPU_OA_SHIFT;
3361         oa_size = oa_size >> AMDGPU_OA_SHIFT;
3362
3363         /* GDS Base */
3364         gfx_v9_0_write_data_to_reg(ring, 0, false,
3365                                    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
3366                                    gds_base);
3367
3368         /* GDS Size */
3369         gfx_v9_0_write_data_to_reg(ring, 0, false,
3370                                    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
3371                                    gds_size);
3372
3373         /* GWS */
3374         gfx_v9_0_write_data_to_reg(ring, 0, false,
3375                                    SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
3376                                    gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
3377
3378         /* OA */
3379         gfx_v9_0_write_data_to_reg(ring, 0, false,
3380                                    SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
3381                                    (1 << (oa_size + oa_base)) - (1 << oa_base));
3382 }
3383
3384 static int gfx_v9_0_early_init(void *handle)
3385 {
3386         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3387
3388         adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
3389         adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
3390         gfx_v9_0_set_ring_funcs(adev);
3391         gfx_v9_0_set_irq_funcs(adev);
3392         gfx_v9_0_set_gds_init(adev);
3393         gfx_v9_0_set_rlc_funcs(adev);
3394
3395         return 0;
3396 }
3397
3398 static int gfx_v9_0_late_init(void *handle)
3399 {
3400         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3401         int r;
3402
3403         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
3404         if (r)
3405                 return r;
3406
3407         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
3408         if (r)
3409                 return r;
3410
3411         return 0;
3412 }
3413
3414 static void gfx_v9_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
3415 {
3416         uint32_t rlc_setting, data;
3417         unsigned i;
3418
3419         if (adev->gfx.rlc.in_safe_mode)
3420                 return;
3421
3422         /* if RLC is not enabled, do nothing */
3423         rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
3424         if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3425                 return;
3426
3427         if (adev->cg_flags &
3428             (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG |
3429              AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3430                 data = RLC_SAFE_MODE__CMD_MASK;
3431                 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
3432                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
3433
3434                 /* wait for RLC_SAFE_MODE */
3435                 for (i = 0; i < adev->usec_timeout; i++) {
3436                         if (!REG_GET_FIELD(SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
3437                                 break;
3438                         udelay(1);
3439                 }
3440                 adev->gfx.rlc.in_safe_mode = true;
3441         }
3442 }
3443
3444 static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
3445 {
3446         uint32_t rlc_setting, data;
3447
3448         if (!adev->gfx.rlc.in_safe_mode)
3449                 return;
3450
3451         /* if RLC is not enabled, do nothing */
3452         rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
3453         if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3454                 return;
3455
3456         if (adev->cg_flags &
3457             (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) {
3458                 /*
3459                  * Try to exit safe mode only if it is already in safe
3460                  * mode.
3461                  */
3462                 data = RLC_SAFE_MODE__CMD_MASK;
3463                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
3464                 adev->gfx.rlc.in_safe_mode = false;
3465         }
3466 }
3467
3468 static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
3469                                                 bool enable)
3470 {
3471         gfx_v9_0_enter_rlc_safe_mode(adev);
3472
3473         if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
3474                 gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
3475                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
3476                         gfx_v9_0_enable_gfx_pipeline_powergating(adev, true);
3477         } else {
3478                 gfx_v9_0_enable_gfx_cg_power_gating(adev, false);
3479                 gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);
3480         }
3481
3482         gfx_v9_0_exit_rlc_safe_mode(adev);
3483 }
3484
3485 static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev,
3486                                                 bool enable)
3487 {
3488         /* TODO: double check if we need to perform under safe mode */
3489         /* gfx_v9_0_enter_rlc_safe_mode(adev); */
3490
3491         if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
3492                 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true);
3493         else
3494                 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false);
3495
3496         if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
3497                 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true);
3498         else
3499                 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false);
3500
3501         /* gfx_v9_0_exit_rlc_safe_mode(adev); */
3502 }
3503
3504 static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
3505                                                       bool enable)
3506 {
3507         uint32_t data, def;
3508
3509         /* It is disabled by HW by default */
3510         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3511                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
3512                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3513                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
3514                           RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3515                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3516                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3517
3518                 /* only for Vega10 & Raven1 */
3519                 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
3520
3521                 if (def != data)
3522                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3523
3524                 /* MGLS is a global flag to control all MGLS in GFX */
3525                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3526                         /* 2 - RLC memory Light sleep */
3527                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
3528                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
3529                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3530                                 if (def != data)
3531                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
3532                         }
3533                         /* 3 - CP memory Light sleep */
3534                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
3535                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
3536                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3537                                 if (def != data)
3538                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
3539                         }
3540                 }
3541         } else {
3542                 /* 1 - MGCG_OVERRIDE */
3543                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3544                 data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
3545                          RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
3546                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3547                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3548                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3549                 if (def != data)
3550                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3551
3552                 /* 2 - disable MGLS in RLC */
3553                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
3554                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3555                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3556                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
3557                 }
3558
3559                 /* 3 - disable MGLS in CP */
3560                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
3561                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3562                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3563                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
3564                 }
3565         }
3566 }
3567
3568 static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
3569                                            bool enable)
3570 {
3571         uint32_t data, def;
3572
3573         adev->gfx.rlc.funcs->enter_safe_mode(adev);
3574
3575         /* Enable 3D CGCG/CGLS */
3576         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3577                 /* write cmd to clear cgcg/cgls ov */
3578                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3579                 /* unset CGCG override */
3580                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
3581                 /* update CGCG and CGLS override bits */
3582                 if (def != data)
3583                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3584                 /* enable 3Dcgcg FSM(0x0020003f) */
3585                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
3586                 data = (0x2000 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3587                         RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
3588                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
3589                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3590                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
3591                 if (def != data)
3592                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
3593
3594                 /* set IDLE_POLL_COUNT(0x00900100) */
3595                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
3596                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3597                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3598                 if (def != data)
3599                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
3600         } else {
3601                 /* Disable CGCG/CGLS */
3602                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
3603                 /* disable cgcg, cgls should be disabled */
3604                 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
3605                           RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
3606                 /* disable cgcg and cgls in FSM */
3607                 if (def != data)
3608                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
3609         }
3610
3611         adev->gfx.rlc.funcs->exit_safe_mode(adev);
3612 }
3613
3614 static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
3615                                                       bool enable)
3616 {
3617         uint32_t def, data;
3618
3619         adev->gfx.rlc.funcs->enter_safe_mode(adev);
3620
3621         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
3622                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3623                 /* unset CGCG override */
3624                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
3625                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3626                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3627                 else
3628                         data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3629                 /* update CGCG and CGLS override bits */
3630                 if (def != data)
3631                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3632
3633                 /* enable cgcg FSM(0x0020003F) */
3634                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
3635                 data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3636                         RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
3637                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3638                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3639                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3640                 if (def != data)
3641                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
3642
3643                 /* set IDLE_POLL_COUNT(0x00900100) */
3644                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
3645                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3646                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3647                 if (def != data)
3648                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
3649         } else {
3650                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
3651                 /* reset CGCG/CGLS bits */
3652                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3653                 /* disable cgcg and cgls in FSM */
3654                 if (def != data)
3655                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
3656         }
3657
3658         adev->gfx.rlc.funcs->exit_safe_mode(adev);
3659 }
3660
3661 static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
3662                                             bool enable)
3663 {
3664         if (enable) {
3665                 /* CGCG/CGLS should be enabled after MGCG/MGLS
3666                  * ===  MGCG + MGLS ===
3667                  */
3668                 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3669                 /* ===  CGCG /CGLS for GFX 3D Only === */
3670                 gfx_v9_0_update_3d_clock_gating(adev, enable);
3671                 /* ===  CGCG + CGLS === */
3672                 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3673         } else {
3674                 /* CGCG/CGLS should be disabled before MGCG/MGLS
3675                  * ===  CGCG + CGLS ===
3676                  */
3677                 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3678                 /* ===  CGCG /CGLS for GFX 3D Only === */
3679                 gfx_v9_0_update_3d_clock_gating(adev, enable);
3680                 /* ===  MGCG + MGLS === */
3681                 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3682         }
3683         return 0;
3684 }
3685
3686 static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
3687         .enter_safe_mode = gfx_v9_0_enter_rlc_safe_mode,
3688         .exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode
3689 };
3690
3691 static int gfx_v9_0_set_powergating_state(void *handle,
3692                                           enum amd_powergating_state state)
3693 {
3694         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3695         bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
3696
3697         switch (adev->asic_type) {
3698         case CHIP_RAVEN:
3699                 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
3700                         gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
3701                         gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
3702                 } else {
3703                         gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
3704                         gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
3705                 }
3706
3707                 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
3708                         gfx_v9_0_enable_cp_power_gating(adev, true);
3709                 else
3710                         gfx_v9_0_enable_cp_power_gating(adev, false);
3711
3712                 /* update gfx cgpg state */
3713                 gfx_v9_0_update_gfx_cg_power_gating(adev, enable);
3714
3715                 /* update mgcg state */
3716                 gfx_v9_0_update_gfx_mg_power_gating(adev, enable);
3717                 break;
3718         default:
3719                 break;
3720         }
3721
3722         return 0;
3723 }
3724
3725 static int gfx_v9_0_set_clockgating_state(void *handle,
3726                                           enum amd_clockgating_state state)
3727 {
3728         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3729
3730         if (amdgpu_sriov_vf(adev))
3731                 return 0;
3732
3733         switch (adev->asic_type) {
3734         case CHIP_VEGA10:
3735         case CHIP_VEGA12:
3736         case CHIP_VEGA20:
3737         case CHIP_RAVEN:
3738                 gfx_v9_0_update_gfx_clock_gating(adev,
3739                                                  state == AMD_CG_STATE_GATE ? true : false);
3740                 break;
3741         default:
3742                 break;
3743         }
3744         return 0;
3745 }
3746
3747 static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
3748 {
3749         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3750         int data;
3751
3752         if (amdgpu_sriov_vf(adev))
3753                 *flags = 0;
3754
3755         /* AMD_CG_SUPPORT_GFX_MGCG */
3756         data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3757         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
3758                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
3759
3760         /* AMD_CG_SUPPORT_GFX_CGCG */
3761         data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
3762         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
3763                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
3764
3765         /* AMD_CG_SUPPORT_GFX_CGLS */
3766         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
3767                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
3768
3769         /* AMD_CG_SUPPORT_GFX_RLC_LS */
3770         data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
3771         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
3772                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
3773
3774         /* AMD_CG_SUPPORT_GFX_CP_LS */
3775         data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
3776         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
3777                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
3778
3779         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
3780         data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
3781         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
3782                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
3783
3784         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
3785         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
3786                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
3787 }
3788
3789 static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
3790 {
3791         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/
3792 }
3793
3794 static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
3795 {
3796         struct amdgpu_device *adev = ring->adev;
3797         u64 wptr;
3798
3799         /* XXX check if swapping is necessary on BE */
3800         if (ring->use_doorbell) {
3801                 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
3802         } else {
3803                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
3804                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
3805         }
3806
3807         return wptr;
3808 }
3809
3810 static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
3811 {
3812         struct amdgpu_device *adev = ring->adev;
3813
3814         if (ring->use_doorbell) {
3815                 /* XXX check if swapping is necessary on BE */
3816                 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
3817                 WDOORBELL64(ring->doorbell_index, ring->wptr);
3818         } else {
3819                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
3820                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
3821         }
3822 }
3823
3824 static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
3825 {
3826         struct amdgpu_device *adev = ring->adev;
3827         u32 ref_and_mask, reg_mem_engine;
3828         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;
3829
3830         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
3831                 switch (ring->me) {
3832                 case 1:
3833                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
3834                         break;
3835                 case 2:
3836                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
3837                         break;
3838                 default:
3839                         return;
3840                 }
3841                 reg_mem_engine = 0;
3842         } else {
3843                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
3844                 reg_mem_engine = 1; /* pfp */
3845         }
3846
3847         gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
3848                               adev->nbio_funcs->get_hdp_flush_req_offset(adev),
3849                               adev->nbio_funcs->get_hdp_flush_done_offset(adev),
3850                               ref_and_mask, ref_and_mask, 0x20);
3851 }
3852
3853 static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
3854                                       struct amdgpu_ib *ib,
3855                                       unsigned vmid, bool ctx_switch)
3856 {
3857         u32 header, control = 0;
3858
3859         if (ib->flags & AMDGPU_IB_FLAG_CE)
3860                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3861         else
3862                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3863
3864         control |= ib->length_dw | (vmid << 24);
3865
3866         if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
3867                 control |= INDIRECT_BUFFER_PRE_ENB(1);
3868
3869                 if (!(ib->flags & AMDGPU_IB_FLAG_CE))
3870                         gfx_v9_0_ring_emit_de_meta(ring);
3871         }
3872
3873         amdgpu_ring_write(ring, header);
3874         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3875         amdgpu_ring_write(ring,
3876 #ifdef __BIG_ENDIAN
3877                 (2 << 0) |
3878 #endif
3879                 lower_32_bits(ib->gpu_addr));
3880         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
3881         amdgpu_ring_write(ring, control);
3882 }
3883
3884 static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
3885                                           struct amdgpu_ib *ib,
3886                                           unsigned vmid, bool ctx_switch)
3887 {
3888         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
3889
3890         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3891         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3892         amdgpu_ring_write(ring,
3893 #ifdef __BIG_ENDIAN
3894                                 (2 << 0) |
3895 #endif
3896                                 lower_32_bits(ib->gpu_addr));
3897         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
3898         amdgpu_ring_write(ring, control);
3899 }
3900
3901 static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
3902                                      u64 seq, unsigned flags)
3903 {
3904         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
3905         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
3906         bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY;
3907
3908         /* RELEASE_MEM - flush caches, send int */
3909         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
3910         amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN |
3911                                                EOP_TC_NC_ACTION_EN) :
3912                                               (EOP_TCL1_ACTION_EN |
3913                                                EOP_TC_ACTION_EN |
3914                                                EOP_TC_WB_ACTION_EN |
3915                                                EOP_TC_MD_ACTION_EN)) |
3916                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3917                                  EVENT_INDEX(5)));
3918         amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
3919
3920         /*
3921          * the address should be Qword aligned if 64bit write, Dword
3922          * aligned if only send 32bit data low (discard data high)
3923          */
3924         if (write64bit)
3925                 BUG_ON(addr & 0x7);
3926         else
3927                 BUG_ON(addr & 0x3);
3928         amdgpu_ring_write(ring, lower_32_bits(addr));
3929         amdgpu_ring_write(ring, upper_32_bits(addr));
3930         amdgpu_ring_write(ring, lower_32_bits(seq));
3931         amdgpu_ring_write(ring, upper_32_bits(seq));
3932         amdgpu_ring_write(ring, 0);
3933 }
3934
3935 static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
3936 {
3937         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3938         uint32_t seq = ring->fence_drv.sync_seq;
3939         uint64_t addr = ring->fence_drv.gpu_addr;
3940
3941         gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0,
3942                               lower_32_bits(addr), upper_32_bits(addr),
3943                               seq, 0xffffffff, 4);
3944 }
3945
3946 static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3947                                         unsigned vmid, uint64_t pd_addr)
3948 {
3949         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
3950
3951         /* compute doesn't have PFP */
3952         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
3953                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3954                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3955                 amdgpu_ring_write(ring, 0x0);
3956         }
3957 }
3958
3959 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
3960 {
3961         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */
3962 }
3963
3964 static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
3965 {
3966         u64 wptr;
3967
3968         /* XXX check if swapping is necessary on BE */
3969         if (ring->use_doorbell)
3970                 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
3971         else
3972                 BUG();
3973         return wptr;
3974 }
3975
3976 static void gfx_v9_0_ring_set_pipe_percent(struct amdgpu_ring *ring,
3977                                            bool acquire)
3978 {
3979         struct amdgpu_device *adev = ring->adev;
3980         int pipe_num, tmp, reg;
3981         int pipe_percent = acquire ? SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK : 0x1;
3982
3983         pipe_num = ring->me * adev->gfx.mec.num_pipe_per_mec + ring->pipe;
3984
3985         /* first me only has 2 entries, GFX and HP3D */
3986         if (ring->me > 0)
3987                 pipe_num -= 2;
3988
3989         reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_GFX) + pipe_num;
3990         tmp = RREG32(reg);
3991         tmp = REG_SET_FIELD(tmp, SPI_WCL_PIPE_PERCENT_GFX, VALUE, pipe_percent);
3992         WREG32(reg, tmp);
3993 }
3994
3995 static void gfx_v9_0_pipe_reserve_resources(struct amdgpu_device *adev,
3996                                             struct amdgpu_ring *ring,
3997                                             bool acquire)
3998 {
3999         int i, pipe;
4000         bool reserve;
4001         struct amdgpu_ring *iring;
4002
4003         mutex_lock(&adev->gfx.pipe_reserve_mutex);
4004         pipe = amdgpu_gfx_queue_to_bit(adev, ring->me, ring->pipe, 0);
4005         if (acquire)
4006                 set_bit(pipe, adev->gfx.pipe_reserve_bitmap);
4007         else
4008                 clear_bit(pipe, adev->gfx.pipe_reserve_bitmap);
4009
4010         if (!bitmap_weight(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES)) {
4011                 /* Clear all reservations - everyone reacquires all resources */
4012                 for (i = 0; i < adev->gfx.num_gfx_rings; ++i)
4013                         gfx_v9_0_ring_set_pipe_percent(&adev->gfx.gfx_ring[i],
4014                                                        true);
4015
4016                 for (i = 0; i < adev->gfx.num_compute_rings; ++i)
4017                         gfx_v9_0_ring_set_pipe_percent(&adev->gfx.compute_ring[i],
4018                                                        true);
4019         } else {
4020                 /* Lower all pipes without a current reservation */
4021                 for (i = 0; i < adev->gfx.num_gfx_rings; ++i) {
4022                         iring = &adev->gfx.gfx_ring[i];
4023                         pipe = amdgpu_gfx_queue_to_bit(adev,
4024                                                        iring->me,
4025                                                        iring->pipe,
4026                                                        0);
4027                         reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap);
4028                         gfx_v9_0_ring_set_pipe_percent(iring, reserve);
4029                 }
4030
4031                 for (i = 0; i < adev->gfx.num_compute_rings; ++i) {
4032                         iring = &adev->gfx.compute_ring[i];
4033                         pipe = amdgpu_gfx_queue_to_bit(adev,
4034                                                        iring->me,
4035                                                        iring->pipe,
4036                                                        0);
4037                         reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap);
4038                         gfx_v9_0_ring_set_pipe_percent(iring, reserve);
4039                 }
4040         }
4041
4042         mutex_unlock(&adev->gfx.pipe_reserve_mutex);
4043 }
4044
4045 static void gfx_v9_0_hqd_set_priority(struct amdgpu_device *adev,
4046                                       struct amdgpu_ring *ring,
4047                                       bool acquire)
4048 {
4049         uint32_t pipe_priority = acquire ? 0x2 : 0x0;
4050         uint32_t queue_priority = acquire ? 0xf : 0x0;
4051
4052         mutex_lock(&adev->srbm_mutex);
4053         soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4054
4055         WREG32_SOC15(GC, 0, mmCP_HQD_PIPE_PRIORITY, pipe_priority);
4056         WREG32_SOC15(GC, 0, mmCP_HQD_QUEUE_PRIORITY, queue_priority);
4057
4058         soc15_grbm_select(adev, 0, 0, 0, 0);
4059         mutex_unlock(&adev->srbm_mutex);
4060 }
4061
4062 static void gfx_v9_0_ring_set_priority_compute(struct amdgpu_ring *ring,
4063                                                enum drm_sched_priority priority)
4064 {
4065         struct amdgpu_device *adev = ring->adev;
4066         bool acquire = priority == DRM_SCHED_PRIORITY_HIGH_HW;
4067
4068         if (ring->funcs->type != AMDGPU_RING_TYPE_COMPUTE)
4069                 return;
4070
4071         gfx_v9_0_hqd_set_priority(adev, ring, acquire);
4072         gfx_v9_0_pipe_reserve_resources(adev, ring, acquire);
4073 }
4074
4075 static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
4076 {
4077         struct amdgpu_device *adev = ring->adev;
4078
4079         /* XXX check if swapping is necessary on BE */
4080         if (ring->use_doorbell) {
4081                 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
4082                 WDOORBELL64(ring->doorbell_index, ring->wptr);
4083         } else{
4084                 BUG(); /* only DOORBELL method supported on gfx9 now */
4085         }
4086 }
4087
4088 static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
4089                                          u64 seq, unsigned int flags)
4090 {
4091         struct amdgpu_device *adev = ring->adev;
4092
4093         /* we only allocate 32bit for each seq wb address */
4094         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
4095
4096         /* write fence seq to the "addr" */
4097         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4098         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4099                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
4100         amdgpu_ring_write(ring, lower_32_bits(addr));
4101         amdgpu_ring_write(ring, upper_32_bits(addr));
4102         amdgpu_ring_write(ring, lower_32_bits(seq));
4103
4104         if (flags & AMDGPU_FENCE_FLAG_INT) {
4105                 /* set register to trigger INT */
4106                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4107                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4108                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
4109                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
4110                 amdgpu_ring_write(ring, 0);
4111                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
4112         }
4113 }
4114
4115 static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring)
4116 {
4117         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4118         amdgpu_ring_write(ring, 0);
4119 }
4120
4121 static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
4122 {
4123         struct v9_ce_ib_state ce_payload = {0};
4124         uint64_t csa_addr;
4125         int cnt;
4126
4127         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
4128         csa_addr = amdgpu_csa_vaddr(ring->adev);
4129
4130         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
4131         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
4132                                  WRITE_DATA_DST_SEL(8) |
4133                                  WR_CONFIRM) |
4134                                  WRITE_DATA_CACHE_POLICY(0));
4135         amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
4136         amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
4137         amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2);
4138 }
4139
4140 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring)
4141 {
4142         struct v9_de_ib_state de_payload = {0};
4143         uint64_t csa_addr, gds_addr;
4144         int cnt;
4145
4146         csa_addr = amdgpu_csa_vaddr(ring->adev);
4147         gds_addr = csa_addr + 4096;
4148         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
4149         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
4150
4151         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
4152         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
4153         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
4154                                  WRITE_DATA_DST_SEL(8) |
4155                                  WR_CONFIRM) |
4156                                  WRITE_DATA_CACHE_POLICY(0));
4157         amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
4158         amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
4159         amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2);
4160 }
4161
4162 static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
4163 {
4164         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
4165         amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
4166 }
4167
4168 static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
4169 {
4170         uint32_t dw2 = 0;
4171
4172         if (amdgpu_sriov_vf(ring->adev))
4173                 gfx_v9_0_ring_emit_ce_meta(ring);
4174
4175         gfx_v9_0_ring_emit_tmz(ring, true);
4176
4177         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
4178         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
4179                 /* set load_global_config & load_global_uconfig */
4180                 dw2 |= 0x8001;
4181                 /* set load_cs_sh_regs */
4182                 dw2 |= 0x01000000;
4183                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
4184                 dw2 |= 0x10002;
4185
4186                 /* set load_ce_ram if preamble presented */
4187                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
4188                         dw2 |= 0x10000000;
4189         } else {
4190                 /* still load_ce_ram if this is the first time preamble presented
4191                  * although there is no context switch happens.
4192                  */
4193                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
4194                         dw2 |= 0x10000000;
4195         }
4196
4197         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4198         amdgpu_ring_write(ring, dw2);
4199         amdgpu_ring_write(ring, 0);
4200 }
4201
4202 static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
4203 {
4204         unsigned ret;
4205         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
4206         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
4207         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
4208         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
4209         ret = ring->wptr & ring->buf_mask;
4210         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
4211         return ret;
4212 }
4213
4214 static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
4215 {
4216         unsigned cur;
4217         BUG_ON(offset > ring->buf_mask);
4218         BUG_ON(ring->ring[offset] != 0x55aa55aa);
4219
4220         cur = (ring->wptr & ring->buf_mask) - 1;
4221         if (likely(cur > offset))
4222                 ring->ring[offset] = cur - offset;
4223         else
4224                 ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
4225 }
4226
4227 static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
4228 {
4229         struct amdgpu_device *adev = ring->adev;
4230
4231         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
4232         amdgpu_ring_write(ring, 0 |     /* src: register*/
4233                                 (5 << 8) |      /* dst: memory */
4234                                 (1 << 20));     /* write confirm */
4235         amdgpu_ring_write(ring, reg);
4236         amdgpu_ring_write(ring, 0);
4237         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
4238                                 adev->virt.reg_val_offs * 4));
4239         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
4240                                 adev->virt.reg_val_offs * 4));
4241 }
4242
4243 static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
4244                                     uint32_t val)
4245 {
4246         uint32_t cmd = 0;
4247
4248         switch (ring->funcs->type) {
4249         case AMDGPU_RING_TYPE_GFX:
4250                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
4251                 break;
4252         case AMDGPU_RING_TYPE_KIQ:
4253                 cmd = (1 << 16); /* no inc addr */
4254                 break;
4255         default:
4256                 cmd = WR_CONFIRM;
4257                 break;
4258         }
4259         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4260         amdgpu_ring_write(ring, cmd);
4261         amdgpu_ring_write(ring, reg);
4262         amdgpu_ring_write(ring, 0);
4263         amdgpu_ring_write(ring, val);
4264 }
4265
4266 static void gfx_v9_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
4267                                         uint32_t val, uint32_t mask)
4268 {
4269         gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
4270 }
4271
4272 static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
4273                                                   uint32_t reg0, uint32_t reg1,
4274                                                   uint32_t ref, uint32_t mask)
4275 {
4276         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
4277
4278         if (amdgpu_sriov_vf(ring->adev))
4279                 gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
4280                                       ref, mask, 0x20);
4281         else
4282                 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
4283                                                            ref, mask);
4284 }
4285
4286 static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4287                                                  enum amdgpu_interrupt_state state)
4288 {
4289         switch (state) {
4290         case AMDGPU_IRQ_STATE_DISABLE:
4291         case AMDGPU_IRQ_STATE_ENABLE:
4292                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4293                                TIME_STAMP_INT_ENABLE,
4294                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4295                 break;
4296         default:
4297                 break;
4298         }
4299 }
4300
4301 static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4302                                                      int me, int pipe,
4303                                                      enum amdgpu_interrupt_state state)
4304 {
4305         u32 mec_int_cntl, mec_int_cntl_reg;
4306
4307         /*
4308          * amdgpu controls only the first MEC. That's why this function only
4309          * handles the setting of interrupts for this specific MEC. All other
4310          * pipes' interrupts are set by amdkfd.
4311          */
4312
4313         if (me == 1) {
4314                 switch (pipe) {
4315                 case 0:
4316                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
4317                         break;
4318                 case 1:
4319                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
4320                         break;
4321                 case 2:
4322                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
4323                         break;
4324                 case 3:
4325                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
4326                         break;
4327                 default:
4328                         DRM_DEBUG("invalid pipe %d\n", pipe);
4329                         return;
4330                 }
4331         } else {
4332                 DRM_DEBUG("invalid me %d\n", me);
4333                 return;
4334         }
4335
4336         switch (state) {
4337         case AMDGPU_IRQ_STATE_DISABLE:
4338                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4339                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4340                                              TIME_STAMP_INT_ENABLE, 0);
4341                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4342                 break;
4343         case AMDGPU_IRQ_STATE_ENABLE:
4344                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4345                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4346                                              TIME_STAMP_INT_ENABLE, 1);
4347                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4348                 break;
4349         default:
4350                 break;
4351         }
4352 }
4353
4354 static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4355                                              struct amdgpu_irq_src *source,
4356                                              unsigned type,
4357                                              enum amdgpu_interrupt_state state)
4358 {
4359         switch (state) {
4360         case AMDGPU_IRQ_STATE_DISABLE:
4361         case AMDGPU_IRQ_STATE_ENABLE:
4362                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4363                                PRIV_REG_INT_ENABLE,
4364                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4365                 break;
4366         default:
4367                 break;
4368         }
4369
4370         return 0;
4371 }
4372
4373 static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4374                                               struct amdgpu_irq_src *source,
4375                                               unsigned type,
4376                                               enum amdgpu_interrupt_state state)
4377 {
4378         switch (state) {
4379         case AMDGPU_IRQ_STATE_DISABLE:
4380         case AMDGPU_IRQ_STATE_ENABLE:
4381                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4382                                PRIV_INSTR_INT_ENABLE,
4383                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4384         default:
4385                 break;
4386         }
4387
4388         return 0;
4389 }
4390
4391 static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4392                                             struct amdgpu_irq_src *src,
4393                                             unsigned type,
4394                                             enum amdgpu_interrupt_state state)
4395 {
4396         switch (type) {
4397         case AMDGPU_CP_IRQ_GFX_EOP:
4398                 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
4399                 break;
4400         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4401                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4402                 break;
4403         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4404                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4405                 break;
4406         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4407                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4408                 break;
4409         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4410                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4411                 break;
4412         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4413                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4414                 break;
4415         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4416                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4417                 break;
4418         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4419                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4420                 break;
4421         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4422                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4423                 break;
4424         default:
4425                 break;
4426         }
4427         return 0;
4428 }
4429
4430 static int gfx_v9_0_eop_irq(struct amdgpu_device *adev,
4431                             struct amdgpu_irq_src *source,
4432                             struct amdgpu_iv_entry *entry)
4433 {
4434         int i;
4435         u8 me_id, pipe_id, queue_id;
4436         struct amdgpu_ring *ring;
4437
4438         DRM_DEBUG("IH: CP EOP\n");
4439         me_id = (entry->ring_id & 0x0c) >> 2;
4440         pipe_id = (entry->ring_id & 0x03) >> 0;
4441         queue_id = (entry->ring_id & 0x70) >> 4;
4442
4443         switch (me_id) {
4444         case 0:
4445                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4446                 break;
4447         case 1:
4448         case 2:
4449                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4450                         ring = &adev->gfx.compute_ring[i];
4451                         /* Per-queue interrupt is supported for MEC starting from VI.
4452                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
4453                           */
4454                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4455                                 amdgpu_fence_process(ring);
4456                 }
4457                 break;
4458         }
4459         return 0;
4460 }
4461
4462 static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev,
4463                                  struct amdgpu_irq_src *source,
4464                                  struct amdgpu_iv_entry *entry)
4465 {
4466         DRM_ERROR("Illegal register access in command stream\n");
4467         schedule_work(&adev->reset_work);
4468         return 0;
4469 }
4470
4471 static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
4472                                   struct amdgpu_irq_src *source,
4473                                   struct amdgpu_iv_entry *entry)
4474 {
4475         DRM_ERROR("Illegal instruction in command stream\n");
4476         schedule_work(&adev->reset_work);
4477         return 0;
4478 }
4479
4480 static int gfx_v9_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
4481                                             struct amdgpu_irq_src *src,
4482                                             unsigned int type,
4483                                             enum amdgpu_interrupt_state state)
4484 {
4485         uint32_t tmp, target;
4486         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
4487
4488         if (ring->me == 1)
4489                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
4490         else
4491                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
4492         target += ring->pipe;
4493
4494         switch (type) {
4495         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
4496                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
4497                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
4498                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
4499                                                  GENERIC2_INT_ENABLE, 0);
4500                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
4501
4502                         tmp = RREG32(target);
4503                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
4504                                                  GENERIC2_INT_ENABLE, 0);
4505                         WREG32(target, tmp);
4506                 } else {
4507                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
4508                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
4509                                                  GENERIC2_INT_ENABLE, 1);
4510                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
4511
4512                         tmp = RREG32(target);
4513                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
4514                                                  GENERIC2_INT_ENABLE, 1);
4515                         WREG32(target, tmp);
4516                 }
4517                 break;
4518         default:
4519                 BUG(); /* kiq only support GENERIC2_INT now */
4520                 break;
4521         }
4522         return 0;
4523 }
4524
4525 static int gfx_v9_0_kiq_irq(struct amdgpu_device *adev,
4526                             struct amdgpu_irq_src *source,
4527                             struct amdgpu_iv_entry *entry)
4528 {
4529         u8 me_id, pipe_id, queue_id;
4530         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
4531
4532         me_id = (entry->ring_id & 0x0c) >> 2;
4533         pipe_id = (entry->ring_id & 0x03) >> 0;
4534         queue_id = (entry->ring_id & 0x70) >> 4;
4535         DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
4536                    me_id, pipe_id, queue_id);
4537
4538         amdgpu_fence_process(ring);
4539         return 0;
4540 }
4541
4542 static const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
4543         .name = "gfx_v9_0",
4544         .early_init = gfx_v9_0_early_init,
4545         .late_init = gfx_v9_0_late_init,
4546         .sw_init = gfx_v9_0_sw_init,
4547         .sw_fini = gfx_v9_0_sw_fini,
4548         .hw_init = gfx_v9_0_hw_init,
4549         .hw_fini = gfx_v9_0_hw_fini,
4550         .suspend = gfx_v9_0_suspend,
4551         .resume = gfx_v9_0_resume,
4552         .is_idle = gfx_v9_0_is_idle,
4553         .wait_for_idle = gfx_v9_0_wait_for_idle,
4554         .soft_reset = gfx_v9_0_soft_reset,
4555         .set_clockgating_state = gfx_v9_0_set_clockgating_state,
4556         .set_powergating_state = gfx_v9_0_set_powergating_state,
4557         .get_clockgating_state = gfx_v9_0_get_clockgating_state,
4558 };
4559
4560 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
4561         .type = AMDGPU_RING_TYPE_GFX,
4562         .align_mask = 0xff,
4563         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4564         .support_64bit_ptrs = true,
4565         .vmhub = AMDGPU_GFXHUB,
4566         .get_rptr = gfx_v9_0_ring_get_rptr_gfx,
4567         .get_wptr = gfx_v9_0_ring_get_wptr_gfx,
4568         .set_wptr = gfx_v9_0_ring_set_wptr_gfx,
4569         .emit_frame_size = /* totally 242 maximum if 16 IBs */
4570                 5 +  /* COND_EXEC */
4571                 7 +  /* PIPELINE_SYNC */
4572                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
4573                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
4574                 2 + /* VM_FLUSH */
4575                 8 +  /* FENCE for VM_FLUSH */
4576                 20 + /* GDS switch */
4577                 4 + /* double SWITCH_BUFFER,
4578                        the first COND_EXEC jump to the place just
4579                            prior to this double SWITCH_BUFFER  */
4580                 5 + /* COND_EXEC */
4581                 7 +      /*     HDP_flush */
4582                 4 +      /*     VGT_flush */
4583                 14 + /* CE_META */
4584                 31 + /* DE_META */
4585                 3 + /* CNTX_CTRL */
4586                 5 + /* HDP_INVL */
4587                 8 + 8 + /* FENCE x2 */
4588                 2, /* SWITCH_BUFFER */
4589         .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */
4590         .emit_ib = gfx_v9_0_ring_emit_ib_gfx,
4591         .emit_fence = gfx_v9_0_ring_emit_fence,
4592         .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4593         .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4594         .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4595         .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4596         .test_ring = gfx_v9_0_ring_test_ring,
4597         .test_ib = gfx_v9_0_ring_test_ib,
4598         .insert_nop = amdgpu_ring_insert_nop,
4599         .pad_ib = amdgpu_ring_generic_pad_ib,
4600         .emit_switch_buffer = gfx_v9_ring_emit_sb,
4601         .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,
4602         .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec,
4603         .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec,
4604         .emit_tmz = gfx_v9_0_ring_emit_tmz,
4605         .emit_wreg = gfx_v9_0_ring_emit_wreg,
4606         .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
4607         .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
4608 };
4609
4610 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
4611         .type = AMDGPU_RING_TYPE_COMPUTE,
4612         .align_mask = 0xff,
4613         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4614         .support_64bit_ptrs = true,
4615         .vmhub = AMDGPU_GFXHUB,
4616         .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4617         .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4618         .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4619         .emit_frame_size =
4620                 20 + /* gfx_v9_0_ring_emit_gds_switch */
4621                 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4622                 5 + /* hdp invalidate */
4623                 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
4624                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
4625                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
4626                 2 + /* gfx_v9_0_ring_emit_vm_flush */
4627                 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
4628         .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4629         .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4630         .emit_fence = gfx_v9_0_ring_emit_fence,
4631         .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4632         .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4633         .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4634         .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4635         .test_ring = gfx_v9_0_ring_test_ring,
4636         .test_ib = gfx_v9_0_ring_test_ib,
4637         .insert_nop = amdgpu_ring_insert_nop,
4638         .pad_ib = amdgpu_ring_generic_pad_ib,
4639         .set_priority = gfx_v9_0_ring_set_priority_compute,
4640         .emit_wreg = gfx_v9_0_ring_emit_wreg,
4641         .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
4642         .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
4643 };
4644
4645 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
4646         .type = AMDGPU_RING_TYPE_KIQ,
4647         .align_mask = 0xff,
4648         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4649         .support_64bit_ptrs = true,
4650         .vmhub = AMDGPU_GFXHUB,
4651         .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4652         .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4653         .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4654         .emit_frame_size =
4655                 20 + /* gfx_v9_0_ring_emit_gds_switch */
4656                 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4657                 5 + /* hdp invalidate */
4658                 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
4659                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
4660                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
4661                 2 + /* gfx_v9_0_ring_emit_vm_flush */
4662                 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */
4663         .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4664         .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4665         .emit_fence = gfx_v9_0_ring_emit_fence_kiq,
4666         .test_ring = gfx_v9_0_ring_test_ring,
4667         .test_ib = gfx_v9_0_ring_test_ib,
4668         .insert_nop = amdgpu_ring_insert_nop,
4669         .pad_ib = amdgpu_ring_generic_pad_ib,
4670         .emit_rreg = gfx_v9_0_ring_emit_rreg,
4671         .emit_wreg = gfx_v9_0_ring_emit_wreg,
4672         .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
4673         .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
4674 };
4675
4676 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)
4677 {
4678         int i;
4679
4680         adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq;
4681
4682         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4683                 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx;
4684
4685         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4686                 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute;
4687 }
4688
4689 static const struct amdgpu_irq_src_funcs gfx_v9_0_kiq_irq_funcs = {
4690         .set = gfx_v9_0_kiq_set_interrupt_state,
4691         .process = gfx_v9_0_kiq_irq,
4692 };
4693
4694 static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = {
4695         .set = gfx_v9_0_set_eop_interrupt_state,
4696         .process = gfx_v9_0_eop_irq,
4697 };
4698
4699 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = {
4700         .set = gfx_v9_0_set_priv_reg_fault_state,
4701         .process = gfx_v9_0_priv_reg_irq,
4702 };
4703
4704 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = {
4705         .set = gfx_v9_0_set_priv_inst_fault_state,
4706         .process = gfx_v9_0_priv_inst_irq,
4707 };
4708
4709 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)
4710 {
4711         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4712         adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs;
4713
4714         adev->gfx.priv_reg_irq.num_types = 1;
4715         adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs;
4716
4717         adev->gfx.priv_inst_irq.num_types = 1;
4718         adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs;
4719
4720         adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
4721         adev->gfx.kiq.irq.funcs = &gfx_v9_0_kiq_irq_funcs;
4722 }
4723
4724 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
4725 {
4726         switch (adev->asic_type) {
4727         case CHIP_VEGA10:
4728         case CHIP_VEGA12:
4729         case CHIP_VEGA20:
4730         case CHIP_RAVEN:
4731                 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
4732                 break;
4733         default:
4734                 break;
4735         }
4736 }
4737
4738 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
4739 {
4740         /* init asci gds info */
4741         adev->gds.mem.total_size = RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
4742         adev->gds.gws.total_size = 64;
4743         adev->gds.oa.total_size = 16;
4744
4745         if (adev->gds.mem.total_size == 64 * 1024) {
4746                 adev->gds.mem.gfx_partition_size = 4096;
4747                 adev->gds.mem.cs_partition_size = 4096;
4748
4749                 adev->gds.gws.gfx_partition_size = 4;
4750                 adev->gds.gws.cs_partition_size = 4;
4751
4752                 adev->gds.oa.gfx_partition_size = 4;
4753                 adev->gds.oa.cs_partition_size = 1;
4754         } else {
4755                 adev->gds.mem.gfx_partition_size = 1024;
4756                 adev->gds.mem.cs_partition_size = 1024;
4757
4758                 adev->gds.gws.gfx_partition_size = 16;
4759                 adev->gds.gws.cs_partition_size = 16;
4760
4761                 adev->gds.oa.gfx_partition_size = 4;
4762                 adev->gds.oa.cs_partition_size = 4;
4763         }
4764 }
4765
4766 static void gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
4767                                                  u32 bitmap)
4768 {
4769         u32 data;
4770
4771         if (!bitmap)
4772                 return;
4773
4774         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4775         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4776
4777         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
4778 }
4779
4780 static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)
4781 {
4782         u32 data, mask;
4783
4784         data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
4785         data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
4786
4787         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4788         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4789
4790         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
4791
4792         return (~data) & mask;
4793 }
4794
4795 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
4796                                  struct amdgpu_cu_info *cu_info)
4797 {
4798         int i, j, k, counter, active_cu_number = 0;
4799         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
4800         unsigned disable_masks[4 * 2];
4801
4802         if (!adev || !cu_info)
4803                 return -EINVAL;
4804
4805         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
4806
4807         mutex_lock(&adev->grbm_idx_mutex);
4808         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4809                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4810                         mask = 1;
4811                         ao_bitmap = 0;
4812                         counter = 0;
4813                         gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
4814                         if (i < 4 && j < 2)
4815                                 gfx_v9_0_set_user_cu_inactive_bitmap(
4816                                         adev, disable_masks[i * 2 + j]);
4817                         bitmap = gfx_v9_0_get_cu_active_bitmap(adev);
4818                         cu_info->bitmap[i][j] = bitmap;
4819
4820                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
4821                                 if (bitmap & mask) {
4822                                         if (counter < adev->gfx.config.max_cu_per_sh)
4823                                                 ao_bitmap |= mask;
4824                                         counter ++;
4825                                 }
4826                                 mask <<= 1;
4827                         }
4828                         active_cu_number += counter;
4829                         if (i < 2 && j < 2)
4830                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
4831                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
4832                 }
4833         }
4834         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4835         mutex_unlock(&adev->grbm_idx_mutex);
4836
4837         cu_info->number = active_cu_number;
4838         cu_info->ao_cu_mask = ao_cu_mask;
4839         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
4840
4841         return 0;
4842 }
4843
4844 const struct amdgpu_ip_block_version gfx_v9_0_ip_block =
4845 {
4846         .type = AMD_IP_BLOCK_TYPE_GFX,
4847         .major = 9,
4848         .minor = 0,
4849         .rev = 0,
4850         .funcs = &gfx_v9_0_ip_funcs,
4851 };