drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/kernel.h>
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_gfx.h"
  28 #include "soc15.h"
  29 #include "soc15d.h"
  30 #include "amdgpu_atomfirmware.h"
  31
  32 #include "gc/gc_9_0_offset.h"
  33 #include "gc/gc_9_0_sh_mask.h"
  34 #include "vega10_enum.h"
  35 #include "hdp/hdp_4_0_offset.h"
  36
  37 #include "soc15_common.h"
  38 #include "clearstate_gfx9.h"
  39 #include "v9_structs.h"
  40
  41 #define GFX9_NUM_GFX_RINGS     1
  42 #define GFX9_MEC_HPD_SIZE 2048
  43 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
  44 #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L
  45
  46 #define mmPWR_MISC_CNTL_STATUS                                  0x0183
  47 #define mmPWR_MISC_CNTL_STATUS_BASE_IDX                         0
  48 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT        0x0
  49 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT          0x1
  50 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK          0x00000001L
  51 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK            0x00000006L
  52
  53 MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
  54 MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
  55 MODULE_FIRMWARE("amdgpu/vega10_me.bin");
  56 MODULE_FIRMWARE("amdgpu/vega10_mec.bin");
  57 MODULE_FIRMWARE("amdgpu/vega10_mec2.bin");
  58 MODULE_FIRMWARE("amdgpu/vega10_rlc.bin");
  59
  60 MODULE_FIRMWARE("amdgpu/vega12_ce.bin");
  61 MODULE_FIRMWARE("amdgpu/vega12_pfp.bin");
  62 MODULE_FIRMWARE("amdgpu/vega12_me.bin");
  63 MODULE_FIRMWARE("amdgpu/vega12_mec.bin");
  64 MODULE_FIRMWARE("amdgpu/vega12_mec2.bin");
  65 MODULE_FIRMWARE("amdgpu/vega12_rlc.bin");
  66
  67 MODULE_FIRMWARE("amdgpu/vega20_ce.bin");
  68 MODULE_FIRMWARE("amdgpu/vega20_pfp.bin");
  69 MODULE_FIRMWARE("amdgpu/vega20_me.bin");
  70 MODULE_FIRMWARE("amdgpu/vega20_mec.bin");
  71 MODULE_FIRMWARE("amdgpu/vega20_mec2.bin");
  72 MODULE_FIRMWARE("amdgpu/vega20_rlc.bin");
  73
  74 MODULE_FIRMWARE("amdgpu/raven_ce.bin");
  75 MODULE_FIRMWARE("amdgpu/raven_pfp.bin");
  76 MODULE_FIRMWARE("amdgpu/raven_me.bin");
  77 MODULE_FIRMWARE("amdgpu/raven_mec.bin");
  78 MODULE_FIRMWARE("amdgpu/raven_mec2.bin");
  79 MODULE_FIRMWARE("amdgpu/raven_rlc.bin");
  80
  81 static const struct soc15_reg_golden golden_settings_gc_9_0[] =
  82 {
  83         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420),
  84         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
  85         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
  86         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
  87         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
  88         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000),
  89         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800),
  90         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800),
  91         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87),
  92         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f),
  93         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000),
  94         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
  95         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68),
  96         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197),
  97         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
  98         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff)
  99 };
 100
 101 static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] =
 102 {
 103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0x0000f000, 0x00012107),
 104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
 105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042),
 106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x2a114042),
 107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00008000, 0x00048000),
 108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000),
 109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800)
 110 };
 111
 112 static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] =
 113 {
 114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000),
 115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
 116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x22014042),
 117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x22014042),
 118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0x00003e00, 0x00000400),
 119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xff840000, 0x04040000),
 120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00030000),
 121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff010f, 0x01000107),
 122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x000b0000, 0x000b0000),
 123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01000000, 0x01000000)
 124 };
 125
 126 static const struct soc15_reg_golden golden_settings_gc_9_1[] =
 127 {
 128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
 129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080),
 130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080),
 131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080),
 132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420),
 133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
 134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080),
 135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
 136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
 137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080),
 139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080),
 140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080),
 141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080),
 142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080),
 143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
 144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
 145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120),
 146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
 147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
 148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080)
 149 };
 150
 151 static const struct soc15_reg_golden golden_settings_gc_9_1_rv1[] =
 152 {
 153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
 154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24000042),
 155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24000042),
 156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04048000),
 157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_MODE_CNTL_1, 0x06000000, 0x06000000),
 158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000),
 159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x00000800)
 160 };
 161
 162 static const struct soc15_reg_golden golden_settings_gc_9_x_common[] =
 163 {
 164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_INDEX, 0xffffffff, 0x00000000),
 165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2544c382)
 166 };
 167
 168 static const struct soc15_reg_golden golden_settings_gc_9_2_1[] =
 169 {
 170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420),
 171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
 172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
 173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
 174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000),
 176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800),
 177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800),
 178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87),
 179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f),
 180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000),
 181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
 182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68),
 183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197),
 184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
 185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff)
 186 };
 187
 188 static const struct soc15_reg_golden golden_settings_gc_9_2_1_vg12[] =
 189 {
 190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x00000080, 0x04000080),
 191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
 192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000),
 193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24104041),
 194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24104041),
 195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000),
 196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff03ff, 0x01000107),
 197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
 198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x76325410),
 199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000)
 200 };
 201
 202 static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[] =
 203 {
 204         mmRLC_SRM_INDEX_CNTL_ADDR_0 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 205         mmRLC_SRM_INDEX_CNTL_ADDR_1 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 206         mmRLC_SRM_INDEX_CNTL_ADDR_2 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 207         mmRLC_SRM_INDEX_CNTL_ADDR_3 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 208         mmRLC_SRM_INDEX_CNTL_ADDR_4 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 209         mmRLC_SRM_INDEX_CNTL_ADDR_5 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 210         mmRLC_SRM_INDEX_CNTL_ADDR_6 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 211         mmRLC_SRM_INDEX_CNTL_ADDR_7 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 212 };
 213
 214 static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] =
 215 {
 216         mmRLC_SRM_INDEX_CNTL_DATA_0 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 217         mmRLC_SRM_INDEX_CNTL_DATA_1 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 218         mmRLC_SRM_INDEX_CNTL_DATA_2 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 219         mmRLC_SRM_INDEX_CNTL_DATA_3 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 220         mmRLC_SRM_INDEX_CNTL_DATA_4 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 221         mmRLC_SRM_INDEX_CNTL_DATA_5 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 222         mmRLC_SRM_INDEX_CNTL_DATA_6 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 223         mmRLC_SRM_INDEX_CNTL_DATA_7 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 224 };
 225
 226 #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
 227 #define VEGA12_GB_ADDR_CONFIG_GOLDEN 0x24104041
 228 #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042
 229
 230 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
 231 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
 232 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev);
 233 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
 234 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
 235                                  struct amdgpu_cu_info *cu_info);
 236 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
 237 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
 238 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
 239
 240 static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
 241 {
 242         switch (adev->asic_type) {
 243         case CHIP_VEGA10:
 244                 soc15_program_register_sequence(adev,
 245                                                  golden_settings_gc_9_0,
 246                                                  ARRAY_SIZE(golden_settings_gc_9_0));
 247                 soc15_program_register_sequence(adev,
 248                                                  golden_settings_gc_9_0_vg10,
 249                                                  ARRAY_SIZE(golden_settings_gc_9_0_vg10));
 250                 break;
 251         case CHIP_VEGA12:
 252                 soc15_program_register_sequence(adev,
 253                                                 golden_settings_gc_9_2_1,
 254                                                 ARRAY_SIZE(golden_settings_gc_9_2_1));
 255                 soc15_program_register_sequence(adev,
 256                                                 golden_settings_gc_9_2_1_vg12,
 257                                                 ARRAY_SIZE(golden_settings_gc_9_2_1_vg12));
 258                 break;
 259         case CHIP_VEGA20:
 260                 soc15_program_register_sequence(adev,
 261                                                 golden_settings_gc_9_0,
 262                                                 ARRAY_SIZE(golden_settings_gc_9_0));
 263                 soc15_program_register_sequence(adev,
 264                                                 golden_settings_gc_9_0_vg20,
 265                                                 ARRAY_SIZE(golden_settings_gc_9_0_vg20));
 266                 break;
 267         case CHIP_RAVEN:
 268                 soc15_program_register_sequence(adev,
 269                                                  golden_settings_gc_9_1,
 270                                                  ARRAY_SIZE(golden_settings_gc_9_1));
 271                 soc15_program_register_sequence(adev,
 272                                                  golden_settings_gc_9_1_rv1,
 273                                                  ARRAY_SIZE(golden_settings_gc_9_1_rv1));
 274                 break;
 275         default:
 276                 break;
 277         }
 278
 279         soc15_program_register_sequence(adev, golden_settings_gc_9_x_common,
 280                                         (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common));
 281 }
 282
 283 static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
 284 {
 285         adev->gfx.scratch.num_reg = 8;
 286         adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
 287         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
 288 }
 289
 290 static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
 291                                        bool wc, uint32_t reg, uint32_t val)
 292 {
 293         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
 294         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
 295                                 WRITE_DATA_DST_SEL(0) |
 296                                 (wc ? WR_CONFIRM : 0));
 297         amdgpu_ring_write(ring, reg);
 298         amdgpu_ring_write(ring, 0);
 299         amdgpu_ring_write(ring, val);
 300 }
 301
 302 static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
 303                                   int mem_space, int opt, uint32_t addr0,
 304                                   uint32_t addr1, uint32_t ref, uint32_t mask,
 305                                   uint32_t inv)
 306 {
 307         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
 308         amdgpu_ring_write(ring,
 309                                  /* memory (1) or register (0) */
 310                                  (WAIT_REG_MEM_MEM_SPACE(mem_space) |
 311                                  WAIT_REG_MEM_OPERATION(opt) | /* wait */
 312                                  WAIT_REG_MEM_FUNCTION(3) |  /* equal */
 313                                  WAIT_REG_MEM_ENGINE(eng_sel)));
 314
 315         if (mem_space)
 316                 BUG_ON(addr0 & 0x3); /* Dword align */
 317         amdgpu_ring_write(ring, addr0);
 318         amdgpu_ring_write(ring, addr1);
 319         amdgpu_ring_write(ring, ref);
 320         amdgpu_ring_write(ring, mask);
 321         amdgpu_ring_write(ring, inv); /* poll interval */
 322 }
 323
 324 static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring)
 325 {
 326         struct amdgpu_device *adev = ring->adev;
 327         uint32_t scratch;
 328         uint32_t tmp = 0;
 329         unsigned i;
 330         int r;
 331
 332         r = amdgpu_gfx_scratch_get(adev, &scratch);
 333         if (r) {
 334                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
 335                 return r;
 336         }
 337         WREG32(scratch, 0xCAFEDEAD);
 338         r = amdgpu_ring_alloc(ring, 3);
 339         if (r) {
 340                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 341                           ring->idx, r);
 342                 amdgpu_gfx_scratch_free(adev, scratch);
 343                 return r;
 344         }
 345         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
 346         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
 347         amdgpu_ring_write(ring, 0xDEADBEEF);
 348         amdgpu_ring_commit(ring);
 349
 350         for (i = 0; i < adev->usec_timeout; i++) {
 351                 tmp = RREG32(scratch);
 352                 if (tmp == 0xDEADBEEF)
 353                         break;
 354                 DRM_UDELAY(1);
 355         }
 356         if (i < adev->usec_timeout) {
 357                 DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
 358                          ring->idx, i);
 359         } else {
 360                 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
 361                           ring->idx, scratch, tmp);
 362                 r = -EINVAL;
 363         }
 364         amdgpu_gfx_scratch_free(adev, scratch);
 365         return r;
 366 }
 367
 368 static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 369 {
 370         struct amdgpu_device *adev = ring->adev;
 371         struct amdgpu_ib ib;
 372         struct dma_fence *f = NULL;
 373
 374         unsigned index;
 375         uint64_t gpu_addr;
 376         uint32_t tmp;
 377         long r;
 378
 379         r = amdgpu_device_wb_get(adev, &index);
 380         if (r) {
 381                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 382                 return r;
 383         }
 384
 385         gpu_addr = adev->wb.gpu_addr + (index * 4);
 386         adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
 387         memset(&ib, 0, sizeof(ib));
 388         r = amdgpu_ib_get(adev, NULL, 16, &ib);
 389         if (r) {
 390                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 391                 goto err1;
 392         }
 393         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
 394         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
 395         ib.ptr[2] = lower_32_bits(gpu_addr);
 396         ib.ptr[3] = upper_32_bits(gpu_addr);
 397         ib.ptr[4] = 0xDEADBEEF;
 398         ib.length_dw = 5;
 399
 400         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 401         if (r)
 402                 goto err2;
 403
 404         r = dma_fence_wait_timeout(f, false, timeout);
 405         if (r == 0) {
 406                         DRM_ERROR("amdgpu: IB test timed out.\n");
 407                         r = -ETIMEDOUT;
 408                         goto err2;
 409         } else if (r < 0) {
 410                         DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 411                         goto err2;
 412         }
 413
 414         tmp = adev->wb.wb[index];
 415         if (tmp == 0xDEADBEEF) {
 416                         DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
 417                         r = 0;
 418         } else {
 419                         DRM_ERROR("ib test on ring %d failed\n", ring->idx);
 420                         r = -EINVAL;
 421         }
 422
 423 err2:
 424         amdgpu_ib_free(adev, &ib, NULL);
 425         dma_fence_put(f);
 426 err1:
 427         amdgpu_device_wb_free(adev, index);
 428         return r;
 429 }
 430
 431
 432 static void gfx_v9_0_free_microcode(struct amdgpu_device *adev)
 433 {
 434         release_firmware(adev->gfx.pfp_fw);
 435         adev->gfx.pfp_fw = NULL;
 436         release_firmware(adev->gfx.me_fw);
 437         adev->gfx.me_fw = NULL;
 438         release_firmware(adev->gfx.ce_fw);
 439         adev->gfx.ce_fw = NULL;
 440         release_firmware(adev->gfx.rlc_fw);
 441         adev->gfx.rlc_fw = NULL;
 442         release_firmware(adev->gfx.mec_fw);
 443         adev->gfx.mec_fw = NULL;
 444         release_firmware(adev->gfx.mec2_fw);
 445         adev->gfx.mec2_fw = NULL;
 446
 447         kfree(adev->gfx.rlc.register_list_format);
 448 }
 449
 450 static void gfx_v9_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
 451 {
 452         const struct rlc_firmware_header_v2_1 *rlc_hdr;
 453
 454         rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
 455         adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
 456         adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
 457         adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
 458         adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
 459         adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
 460         adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
 461         adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
 462         adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
 463         adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
 464         adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
 465         adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
 466         adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
 467         adev->gfx.rlc.reg_list_format_direct_reg_list_length =
 468                         le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
 469 }
 470
 471 static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
 472 {
 473         const char *chip_name;
 474         char fw_name[30];
 475         int err;
 476         struct amdgpu_firmware_info *info = NULL;
 477         const struct common_firmware_header *header = NULL;
 478         const struct gfx_firmware_header_v1_0 *cp_hdr;
 479         const struct rlc_firmware_header_v2_0 *rlc_hdr;
 480         unsigned int *tmp = NULL;
 481         unsigned int i = 0;
 482         uint16_t version_major;
 483         uint16_t version_minor;
 484
 485         DRM_DEBUG("\n");
 486
 487         switch (adev->asic_type) {
 488         case CHIP_VEGA10:
 489                 chip_name = "vega10";
 490                 break;
 491         case CHIP_VEGA12:
 492                 chip_name = "vega12";
 493                 break;
 494         case CHIP_VEGA20:
 495                 chip_name = "vega20";
 496                 break;
 497         case CHIP_RAVEN:
 498                 chip_name = "raven";
 499                 break;
 500         default:
 501                 BUG();
 502         }
 503
 504         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
 505         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
 506         if (err)
 507                 goto out;
 508         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
 509         if (err)
 510                 goto out;
 511         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
 512         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 513         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 514
 515         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
 516         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
 517         if (err)
 518                 goto out;
 519         err = amdgpu_ucode_validate(adev->gfx.me_fw);
 520         if (err)
 521                 goto out;
 522         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
 523         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 524         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 525
 526         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
 527         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
 528         if (err)
 529                 goto out;
 530         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
 531         if (err)
 532                 goto out;
 533         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
 534         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 535         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 536
 537         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
 538         err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
 539         if (err)
 540                 goto out;
 541         err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
 542         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
 543
 544         version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
 545         version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
 546         if (version_major == 2 && version_minor == 1)
 547                 adev->gfx.rlc.is_rlc_v2_1 = true;
 548
 549         adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
 550         adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
 551         adev->gfx.rlc.save_and_restore_offset =
 552                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
 553         adev->gfx.rlc.clear_state_descriptor_offset =
 554                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
 555         adev->gfx.rlc.avail_scratch_ram_locations =
 556                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
 557         adev->gfx.rlc.reg_restore_list_size =
 558                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
 559         adev->gfx.rlc.reg_list_format_start =
 560                         le32_to_cpu(rlc_hdr->reg_list_format_start);
 561         adev->gfx.rlc.reg_list_format_separate_start =
 562                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
 563         adev->gfx.rlc.starting_offsets_start =
 564                         le32_to_cpu(rlc_hdr->starting_offsets_start);
 565         adev->gfx.rlc.reg_list_format_size_bytes =
 566                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
 567         adev->gfx.rlc.reg_list_size_bytes =
 568                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
 569         adev->gfx.rlc.register_list_format =
 570                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
 571                                 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
 572         if (!adev->gfx.rlc.register_list_format) {
 573                 err = -ENOMEM;
 574                 goto out;
 575         }
 576
 577         tmp = (unsigned int *)((uintptr_t)rlc_hdr +
 578                         le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
 579         for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
 580                 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
 581
 582         adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
 583
 584         tmp = (unsigned int *)((uintptr_t)rlc_hdr +
 585                         le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
 586         for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
 587                 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
 588
 589         if (adev->gfx.rlc.is_rlc_v2_1)
 590                 gfx_v9_0_init_rlc_ext_microcode(adev);
 591
 592         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
 593         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
 594         if (err)
 595                 goto out;
 596         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
 597         if (err)
 598                 goto out;
 599         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
 600         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 601         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 602
 603
 604         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
 605         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
 606         if (!err) {
 607                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
 608                 if (err)
 609                         goto out;
 610                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
 611                 adev->gfx.mec2_fw->data;
 612                 adev->gfx.mec2_fw_version =
 613                 le32_to_cpu(cp_hdr->header.ucode_version);
 614                 adev->gfx.mec2_feature_version =
 615                 le32_to_cpu(cp_hdr->ucode_feature_version);
 616         } else {
 617                 err = 0;
 618                 adev->gfx.mec2_fw = NULL;
 619         }
 620
 621         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 622                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
 623                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
 624                 info->fw = adev->gfx.pfp_fw;
 625                 header = (const struct common_firmware_header *)info->fw->data;
 626                 adev->firmware.fw_size +=
 627                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 628
 629                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
 630                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
 631                 info->fw = adev->gfx.me_fw;
 632                 header = (const struct common_firmware_header *)info->fw->data;
 633                 adev->firmware.fw_size +=
 634                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 635
 636                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
 637                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
 638                 info->fw = adev->gfx.ce_fw;
 639                 header = (const struct common_firmware_header *)info->fw->data;
 640                 adev->firmware.fw_size +=
 641                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 642
 643                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
 644                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
 645                 info->fw = adev->gfx.rlc_fw;
 646                 header = (const struct common_firmware_header *)info->fw->data;
 647                 adev->firmware.fw_size +=
 648                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 649
 650                 if (adev->gfx.rlc.is_rlc_v2_1) {
 651                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
 652                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
 653                         info->fw = adev->gfx.rlc_fw;
 654                         adev->firmware.fw_size +=
 655                                 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
 656
 657                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
 658                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
 659                         info->fw = adev->gfx.rlc_fw;
 660                         adev->firmware.fw_size +=
 661                                 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
 662
 663                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
 664                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
 665                         info->fw = adev->gfx.rlc_fw;
 666                         adev->firmware.fw_size +=
 667                                 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
 668                 }
 669
 670                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
 671                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
 672                 info->fw = adev->gfx.mec_fw;
 673                 header = (const struct common_firmware_header *)info->fw->data;
 674                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
 675                 adev->firmware.fw_size +=
 676                         ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 677
 678                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
 679                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
 680                 info->fw = adev->gfx.mec_fw;
 681                 adev->firmware.fw_size +=
 682                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 683
 684                 if (adev->gfx.mec2_fw) {
 685                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
 686                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 687                         info->fw = adev->gfx.mec2_fw;
 688                         header = (const struct common_firmware_header *)info->fw->data;
 689                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
 690                         adev->firmware.fw_size +=
 691                                 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 692                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
 693                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
 694                         info->fw = adev->gfx.mec2_fw;
 695                         adev->firmware.fw_size +=
 696                                 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 697                 }
 698
 699         }
 700
 701 out:
 702         if (err) {
 703                 dev_err(adev->dev,
 704                         "gfx9: Failed to load firmware \"%s\"\n",
 705                         fw_name);
 706                 release_firmware(adev->gfx.pfp_fw);
 707                 adev->gfx.pfp_fw = NULL;
 708                 release_firmware(adev->gfx.me_fw);
 709                 adev->gfx.me_fw = NULL;
 710                 release_firmware(adev->gfx.ce_fw);
 711                 adev->gfx.ce_fw = NULL;
 712                 release_firmware(adev->gfx.rlc_fw);
 713                 adev->gfx.rlc_fw = NULL;
 714                 release_firmware(adev->gfx.mec_fw);
 715                 adev->gfx.mec_fw = NULL;
 716                 release_firmware(adev->gfx.mec2_fw);
 717                 adev->gfx.mec2_fw = NULL;
 718         }
 719         return err;
 720 }
 721
 722 static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
 723 {
 724         u32 count = 0;
 725         const struct cs_section_def *sect = NULL;
 726         const struct cs_extent_def *ext = NULL;
 727
 728         /* begin clear state */
 729         count += 2;
 730         /* context control state */
 731         count += 3;
 732
 733         for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
 734                 for (ext = sect->section; ext->extent != NULL; ++ext) {
 735                         if (sect->id == SECT_CONTEXT)
 736                                 count += 2 + ext->reg_count;
 737                         else
 738                                 return 0;
 739                 }
 740         }
 741
 742         /* end clear state */
 743         count += 2;
 744         /* clear state */
 745         count += 2;
 746
 747         return count;
 748 }
 749
 750 static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev,
 751                                     volatile u32 *buffer)
 752 {
 753         u32 count = 0, i;
 754         const struct cs_section_def *sect = NULL;
 755         const struct cs_extent_def *ext = NULL;
 756
 757         if (adev->gfx.rlc.cs_data == NULL)
 758                 return;
 759         if (buffer == NULL)
 760                 return;
 761
 762         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 763         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
 764
 765         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
 766         buffer[count++] = cpu_to_le32(0x80000000);
 767         buffer[count++] = cpu_to_le32(0x80000000);
 768
 769         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
 770                 for (ext = sect->section; ext->extent != NULL; ++ext) {
 771                         if (sect->id == SECT_CONTEXT) {
 772                                 buffer[count++] =
 773                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
 774                                 buffer[count++] = cpu_to_le32(ext->reg_index -
 775                                                 PACKET3_SET_CONTEXT_REG_START);
 776                                 for (i = 0; i < ext->reg_count; i++)
 777                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
 778                         } else {
 779                                 return;
 780                         }
 781                 }
 782         }
 783
 784         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 785         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
 786
 787         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
 788         buffer[count++] = cpu_to_le32(0);
 789 }
 790
 791 static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev)
 792 {
 793         uint32_t data;
 794
 795         /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */
 796         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F);
 797         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7);
 798         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077);
 799         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16));
 800
 801         /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */
 802         WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000);
 803
 804         /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */
 805         WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500);
 806
 807         mutex_lock(&adev->grbm_idx_mutex);
 808         /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/
 809         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 810         WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff);
 811
 812         /* set mmRLC_LB_PARAMS = 0x003F_1006 */
 813         data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003);
 814         data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010);
 815         data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F);
 816         WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data);
 817
 818         /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */
 819         data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7);
 820         data &= 0x0000FFFF;
 821         data |= 0x00C00000;
 822         WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data);
 823
 824         /* set RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF */
 825         WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, 0xFFF);
 826
 827         /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved,
 828          * but used for RLC_LB_CNTL configuration */
 829         data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK;
 830         data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09);
 831         data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000);
 832         WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data);
 833         mutex_unlock(&adev->grbm_idx_mutex);
 834 }
 835
 836 static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
 837 {
 838         WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
 839 }
 840
 841 static void rv_init_cp_jump_table(struct amdgpu_device *adev)
 842 {
 843         const __le32 *fw_data;
 844         volatile u32 *dst_ptr;
 845         int me, i, max_me = 5;
 846         u32 bo_offset = 0;
 847         u32 table_offset, table_size;
 848
 849         /* write the cp table buffer */
 850         dst_ptr = adev->gfx.rlc.cp_table_ptr;
 851         for (me = 0; me < max_me; me++) {
 852                 if (me == 0) {
 853                         const struct gfx_firmware_header_v1_0 *hdr =
 854                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
 855                         fw_data = (const __le32 *)
 856                                 (adev->gfx.ce_fw->data +
 857                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 858                         table_offset = le32_to_cpu(hdr->jt_offset);
 859                         table_size = le32_to_cpu(hdr->jt_size);
 860                 } else if (me == 1) {
 861                         const struct gfx_firmware_header_v1_0 *hdr =
 862                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
 863                         fw_data = (const __le32 *)
 864                                 (adev->gfx.pfp_fw->data +
 865                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 866                         table_offset = le32_to_cpu(hdr->jt_offset);
 867                         table_size = le32_to_cpu(hdr->jt_size);
 868                 } else if (me == 2) {
 869                         const struct gfx_firmware_header_v1_0 *hdr =
 870                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
 871                         fw_data = (const __le32 *)
 872                                 (adev->gfx.me_fw->data +
 873                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 874                         table_offset = le32_to_cpu(hdr->jt_offset);
 875                         table_size = le32_to_cpu(hdr->jt_size);
 876                 } else if (me == 3) {
 877                         const struct gfx_firmware_header_v1_0 *hdr =
 878                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
 879                         fw_data = (const __le32 *)
 880                                 (adev->gfx.mec_fw->data +
 881                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 882                         table_offset = le32_to_cpu(hdr->jt_offset);
 883                         table_size = le32_to_cpu(hdr->jt_size);
 884                 } else  if (me == 4) {
 885                         const struct gfx_firmware_header_v1_0 *hdr =
 886                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
 887                         fw_data = (const __le32 *)
 888                                 (adev->gfx.mec2_fw->data +
 889                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 890                         table_offset = le32_to_cpu(hdr->jt_offset);
 891                         table_size = le32_to_cpu(hdr->jt_size);
 892                 }
 893
 894                 for (i = 0; i < table_size; i ++) {
 895                         dst_ptr[bo_offset + i] =
 896                                 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
 897                 }
 898
 899                 bo_offset += table_size;
 900         }
 901 }
 902
 903 static void gfx_v9_0_rlc_fini(struct amdgpu_device *adev)
 904 {
 905         /* clear state block */
 906         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
 907                         &adev->gfx.rlc.clear_state_gpu_addr,
 908                         (void **)&adev->gfx.rlc.cs_ptr);
 909
 910         /* jump table block */
 911         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
 912                         &adev->gfx.rlc.cp_table_gpu_addr,
 913                         (void **)&adev->gfx.rlc.cp_table_ptr);
 914 }
 915
 916 static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
 917 {
 918         volatile u32 *dst_ptr;
 919         u32 dws;
 920         const struct cs_section_def *cs_data;
 921         int r;
 922
 923         adev->gfx.rlc.cs_data = gfx9_cs_data;
 924
 925         cs_data = adev->gfx.rlc.cs_data;
 926
 927         if (cs_data) {
 928                 /* clear state block */
 929                 adev->gfx.rlc.clear_state_size = dws = gfx_v9_0_get_csb_size(adev);
 930                 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
 931                                               AMDGPU_GEM_DOMAIN_VRAM,
 932                                               &adev->gfx.rlc.clear_state_obj,
 933                                               &adev->gfx.rlc.clear_state_gpu_addr,
 934                                               (void **)&adev->gfx.rlc.cs_ptr);
 935                 if (r) {
 936                         dev_err(adev->dev, "(%d) failed to create rlc csb bo\n",
 937                                 r);
 938                         gfx_v9_0_rlc_fini(adev);
 939                         return r;
 940                 }
 941                 /* set up the cs buffer */
 942                 dst_ptr = adev->gfx.rlc.cs_ptr;
 943                 gfx_v9_0_get_csb_buffer(adev, dst_ptr);
 944                 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
 945                 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
 946         }
 947
 948         if (adev->asic_type == CHIP_RAVEN) {
 949                 /* TODO: double check the cp_table_size for RV */
 950                 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
 951                 r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size,
 952                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 953                                               &adev->gfx.rlc.cp_table_obj,
 954                                               &adev->gfx.rlc.cp_table_gpu_addr,
 955                                               (void **)&adev->gfx.rlc.cp_table_ptr);
 956                 if (r) {
 957                         dev_err(adev->dev,
 958                                 "(%d) failed to create cp table bo\n", r);
 959                         gfx_v9_0_rlc_fini(adev);
 960                         return r;
 961                 }
 962
 963                 rv_init_cp_jump_table(adev);
 964                 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
 965                 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
 966
 967                 gfx_v9_0_init_lbpw(adev);
 968         }
 969
 970         return 0;
 971 }
 972
 973 static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
 974 {
 975         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
 976         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
 977 }
 978
 979 static int gfx_v9_0_mec_init(struct amdgpu_device *adev)
 980 {
 981         int r;
 982         u32 *hpd;
 983         const __le32 *fw_data;
 984         unsigned fw_size;
 985         u32 *fw;
 986         size_t mec_hpd_size;
 987
 988         const struct gfx_firmware_header_v1_0 *mec_hdr;
 989
 990         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
 991
 992         /* take ownership of the relevant compute queues */
 993         amdgpu_gfx_compute_queue_acquire(adev);
 994         mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE;
 995
 996         r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
 997                                       AMDGPU_GEM_DOMAIN_GTT,
 998                                       &adev->gfx.mec.hpd_eop_obj,
 999                                       &adev->gfx.mec.hpd_eop_gpu_addr,
1000                                       (void **)&hpd);
1001         if (r) {
1002                 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
1003                 gfx_v9_0_mec_fini(adev);
1004                 return r;
1005         }
1006
1007         memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
1008
1009         amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
1010         amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1011
1012         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1013
1014         fw_data = (const __le32 *)
1015                 (adev->gfx.mec_fw->data +
1016                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
1017         fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
1018
1019         r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
1020                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
1021                                       &adev->gfx.mec.mec_fw_obj,
1022                                       &adev->gfx.mec.mec_fw_gpu_addr,
1023                                       (void **)&fw);
1024         if (r) {
1025                 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r);
1026                 gfx_v9_0_mec_fini(adev);
1027                 return r;
1028         }
1029
1030         memcpy(fw, fw_data, fw_size);
1031
1032         amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
1033         amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
1034
1035         return 0;
1036 }
1037
1038 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
1039 {
1040         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1041                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1042                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
1043                 (address << SQ_IND_INDEX__INDEX__SHIFT) |
1044                 (SQ_IND_INDEX__FORCE_READ_MASK));
1045         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1046 }
1047
1048 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
1049                            uint32_t wave, uint32_t thread,
1050                            uint32_t regno, uint32_t num, uint32_t *out)
1051 {
1052         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1053                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1054                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
1055                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
1056                 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
1057                 (SQ_IND_INDEX__FORCE_READ_MASK) |
1058                 (SQ_IND_INDEX__AUTO_INCR_MASK));
1059         while (num--)
1060                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1061 }
1062
1063 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
1064 {
1065         /* type 1 wave data */
1066         dst[(*no_fields)++] = 1;
1067         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
1068         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
1069         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
1070         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
1071         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
1072         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
1073         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
1074         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
1075         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
1076         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
1077         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
1078         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
1079         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
1080         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
1081 }
1082
1083 static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
1084                                      uint32_t wave, uint32_t start,
1085                                      uint32_t size, uint32_t *dst)
1086 {
1087         wave_read_regs(
1088                 adev, simd, wave, 0,
1089                 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
1090 }
1091
1092 static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
1093                                      uint32_t wave, uint32_t thread,
1094                                      uint32_t start, uint32_t size,
1095                                      uint32_t *dst)
1096 {
1097         wave_read_regs(
1098                 adev, simd, wave, thread,
1099                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
1100 }
1101
1102 static void gfx_v9_0_select_me_pipe_q(struct amdgpu_device *adev,
1103                                   u32 me, u32 pipe, u32 q)
1104 {
1105         soc15_grbm_select(adev, me, pipe, q, 0);
1106 }
1107
1108 static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
1109         .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
1110         .select_se_sh = &gfx_v9_0_select_se_sh,
1111         .read_wave_data = &gfx_v9_0_read_wave_data,
1112         .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
1113         .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs,
1114         .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q
1115 };
1116
1117 static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
1118 {
1119         u32 gb_addr_config;
1120         int err;
1121
1122         adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
1123
1124         switch (adev->asic_type) {
1125         case CHIP_VEGA10:
1126                 adev->gfx.config.max_hw_contexts = 8;
1127                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1128                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1129                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1130                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1131                 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN;
1132                 break;
1133         case CHIP_VEGA12:
1134                 adev->gfx.config.max_hw_contexts = 8;
1135                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1136                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1137                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1138                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1139                 gb_addr_config = VEGA12_GB_ADDR_CONFIG_GOLDEN;
1140                 DRM_INFO("fix gfx.config for vega12\n");
1141                 break;
1142         case CHIP_VEGA20:
1143                 adev->gfx.config.max_hw_contexts = 8;
1144                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1145                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1146                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1147                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1148                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
1149                 gb_addr_config &= ~0xf3e777ff;
1150                 gb_addr_config |= 0x22014042;
1151                 /* check vbios table if gpu info is not available */
1152                 err = amdgpu_atomfirmware_get_gfx_info(adev);
1153                 if (err)
1154                         return err;
1155                 break;
1156         case CHIP_RAVEN:
1157                 adev->gfx.config.max_hw_contexts = 8;
1158                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1159                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1160                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1161                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1162                 gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
1163                 break;
1164         default:
1165                 BUG();
1166                 break;
1167         }
1168
1169         adev->gfx.config.gb_addr_config = gb_addr_config;
1170
1171         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
1172                         REG_GET_FIELD(
1173                                         adev->gfx.config.gb_addr_config,
1174                                         GB_ADDR_CONFIG,
1175                                         NUM_PIPES);
1176
1177         adev->gfx.config.max_tile_pipes =
1178                 adev->gfx.config.gb_addr_config_fields.num_pipes;
1179
1180         adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
1181                         REG_GET_FIELD(
1182                                         adev->gfx.config.gb_addr_config,
1183                                         GB_ADDR_CONFIG,
1184                                         NUM_BANKS);
1185         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
1186                         REG_GET_FIELD(
1187                                         adev->gfx.config.gb_addr_config,
1188                                         GB_ADDR_CONFIG,
1189                                         MAX_COMPRESSED_FRAGS);
1190         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
1191                         REG_GET_FIELD(
1192                                         adev->gfx.config.gb_addr_config,
1193                                         GB_ADDR_CONFIG,
1194                                         NUM_RB_PER_SE);
1195         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
1196                         REG_GET_FIELD(
1197                                         adev->gfx.config.gb_addr_config,
1198                                         GB_ADDR_CONFIG,
1199                                         NUM_SHADER_ENGINES);
1200         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
1201                         REG_GET_FIELD(
1202                                         adev->gfx.config.gb_addr_config,
1203                                         GB_ADDR_CONFIG,
1204                                         PIPE_INTERLEAVE_SIZE));
1205
1206         return 0;
1207 }
1208
1209 static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev,
1210                                    struct amdgpu_ngg_buf *ngg_buf,
1211                                    int size_se,
1212                                    int default_size_se)
1213 {
1214         int r;
1215
1216         if (size_se < 0) {
1217                 dev_err(adev->dev, "Buffer size is invalid: %d\n", size_se);
1218                 return -EINVAL;
1219         }
1220         size_se = size_se ? size_se : default_size_se;
1221
1222         ngg_buf->size = size_se * adev->gfx.config.max_shader_engines;
1223         r = amdgpu_bo_create_kernel(adev, ngg_buf->size,
1224                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1225                                     &ngg_buf->bo,
1226                                     &ngg_buf->gpu_addr,
1227                                     NULL);
1228         if (r) {
1229                 dev_err(adev->dev, "(%d) failed to create NGG buffer\n", r);
1230                 return r;
1231         }
1232         ngg_buf->bo_size = amdgpu_bo_size(ngg_buf->bo);
1233
1234         return r;
1235 }
1236
1237 static int gfx_v9_0_ngg_fini(struct amdgpu_device *adev)
1238 {
1239         int i;
1240
1241         for (i = 0; i < NGG_BUF_MAX; i++)
1242                 amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo,
1243                                       &adev->gfx.ngg.buf[i].gpu_addr,
1244                                       NULL);
1245
1246         memset(&adev->gfx.ngg.buf[0], 0,
1247                         sizeof(struct amdgpu_ngg_buf) * NGG_BUF_MAX);
1248
1249         adev->gfx.ngg.init = false;
1250
1251         return 0;
1252 }
1253
1254 static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
1255 {
1256         int r;
1257
1258         if (!amdgpu_ngg || adev->gfx.ngg.init == true)
1259                 return 0;
1260
1261         /* GDS reserve memory: 64 bytes alignment */
1262         adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
1263         adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;
1264         adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;
1265         adev->gfx.ngg.gds_reserve_addr = RREG32_SOC15(GC, 0, mmGDS_VMID0_BASE);
1266         adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
1267
1268         /* Primitive Buffer */
1269         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM],
1270                                     amdgpu_prim_buf_per_se,
1271                                     64 * 1024);
1272         if (r) {
1273                 dev_err(adev->dev, "Failed to create Primitive Buffer\n");
1274                 goto err;
1275         }
1276
1277         /* Position Buffer */
1278         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_POS],
1279                                     amdgpu_pos_buf_per_se,
1280                                     256 * 1024);
1281         if (r) {
1282                 dev_err(adev->dev, "Failed to create Position Buffer\n");
1283                 goto err;
1284         }
1285
1286         /* Control Sideband */
1287         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_CNTL],
1288                                     amdgpu_cntl_sb_buf_per_se,
1289                                     256);
1290         if (r) {
1291                 dev_err(adev->dev, "Failed to create Control Sideband Buffer\n");
1292                 goto err;
1293         }
1294
1295         /* Parameter Cache, not created by default */
1296         if (amdgpu_param_buf_per_se <= 0)
1297                 goto out;
1298
1299         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PARAM],
1300                                     amdgpu_param_buf_per_se,
1301                                     512 * 1024);
1302         if (r) {
1303                 dev_err(adev->dev, "Failed to create Parameter Cache\n");
1304                 goto err;
1305         }
1306
1307 out:
1308         adev->gfx.ngg.init = true;
1309         return 0;
1310 err:
1311         gfx_v9_0_ngg_fini(adev);
1312         return r;
1313 }
1314
1315 static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
1316 {
1317         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
1318         int r;
1319         u32 data, base;
1320
1321         if (!amdgpu_ngg)
1322                 return 0;
1323
1324         /* Program buffer size */
1325         data = REG_SET_FIELD(0, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE,
1326                              adev->gfx.ngg.buf[NGG_PRIM].size >> 8);
1327         data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE,
1328                              adev->gfx.ngg.buf[NGG_POS].size >> 8);
1329         WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_1, data);
1330
1331         data = REG_SET_FIELD(0, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE,
1332                              adev->gfx.ngg.buf[NGG_CNTL].size >> 8);
1333         data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE,
1334                              adev->gfx.ngg.buf[NGG_PARAM].size >> 10);
1335         WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_2, data);
1336
1337         /* Program buffer base address */
1338         base = lower_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
1339         data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base);
1340         WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE, data);
1341
1342         base = upper_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
1343         data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base);
1344         WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE_HI, data);
1345
1346         base = lower_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
1347         data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base);
1348         WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE, data);
1349
1350         base = upper_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
1351         data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base);
1352         WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE_HI, data);
1353
1354         base = lower_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
1355         data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base);
1356         WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE, data);
1357
1358         base = upper_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
1359         data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base);
1360         WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI, data);
1361
1362         /* Clear GDS reserved memory */
1363         r = amdgpu_ring_alloc(ring, 17);
1364         if (r) {
1365                 DRM_ERROR("amdgpu: NGG failed to lock ring %d (%d).\n",
1366                           ring->idx, r);
1367                 return r;
1368         }
1369
1370         gfx_v9_0_write_data_to_reg(ring, 0, false,
1371                                    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
1372                                    (adev->gds.mem.total_size +
1373                                     adev->gfx.ngg.gds_reserve_size) >>
1374                                    AMDGPU_GDS_SHIFT);
1375
1376         amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
1377         amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
1378                                 PACKET3_DMA_DATA_DST_SEL(1) |
1379                                 PACKET3_DMA_DATA_SRC_SEL(2)));
1380         amdgpu_ring_write(ring, 0);
1381         amdgpu_ring_write(ring, 0);
1382         amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
1383         amdgpu_ring_write(ring, 0);
1384         amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT |
1385                                 adev->gfx.ngg.gds_reserve_size);
1386
1387         gfx_v9_0_write_data_to_reg(ring, 0, false,
1388                                    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0);
1389
1390         amdgpu_ring_commit(ring);
1391
1392         return 0;
1393 }
1394
1395 static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1396                                       int mec, int pipe, int queue)
1397 {
1398         int r;
1399         unsigned irq_type;
1400         struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1401
1402         ring = &adev->gfx.compute_ring[ring_id];
1403
1404         /* mec0 is me1 */
1405         ring->me = mec + 1;
1406         ring->pipe = pipe;
1407         ring->queue = queue;
1408
1409         ring->ring_obj = NULL;
1410         ring->use_doorbell = true;
1411         ring->doorbell_index = (AMDGPU_DOORBELL_MEC_RING0 + ring_id) << 1;
1412         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1413                                 + (ring_id * GFX9_MEC_HPD_SIZE);
1414         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1415
1416         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1417                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1418                 + ring->pipe;
1419
1420         /* type-2 packets are deprecated on MEC, use type-3 instead */
1421         r = amdgpu_ring_init(adev, ring, 1024,
1422                              &adev->gfx.eop_irq, irq_type);
1423         if (r)
1424                 return r;
1425
1426
1427         return 0;
1428 }
1429
1430 static int gfx_v9_0_sw_init(void *handle)
1431 {
1432         int i, j, k, r, ring_id;
1433         struct amdgpu_ring *ring;
1434         struct amdgpu_kiq *kiq;
1435         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1436
1437         switch (adev->asic_type) {
1438         case CHIP_VEGA10:
1439         case CHIP_VEGA12:
1440         case CHIP_VEGA20:
1441         case CHIP_RAVEN:
1442                 adev->gfx.mec.num_mec = 2;
1443                 break;
1444         default:
1445                 adev->gfx.mec.num_mec = 1;
1446                 break;
1447         }
1448
1449         adev->gfx.mec.num_pipe_per_mec = 4;
1450         adev->gfx.mec.num_queue_per_pipe = 8;
1451
1452         /* KIQ event */
1453         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 178, &adev->gfx.kiq.irq);
1454         if (r)
1455                 return r;
1456
1457         /* EOP Event */
1458         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 181, &adev->gfx.eop_irq);
1459         if (r)
1460                 return r;
1461
1462         /* Privileged reg */
1463         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 184,
1464                               &adev->gfx.priv_reg_irq);
1465         if (r)
1466                 return r;
1467
1468         /* Privileged inst */
1469         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 185,
1470                               &adev->gfx.priv_inst_irq);
1471         if (r)
1472                 return r;
1473
1474         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1475
1476         gfx_v9_0_scratch_init(adev);
1477
1478         r = gfx_v9_0_init_microcode(adev);
1479         if (r) {
1480                 DRM_ERROR("Failed to load gfx firmware!\n");
1481                 return r;
1482         }
1483
1484         r = gfx_v9_0_rlc_init(adev);
1485         if (r) {
1486                 DRM_ERROR("Failed to init rlc BOs!\n");
1487                 return r;
1488         }
1489
1490         r = gfx_v9_0_mec_init(adev);
1491         if (r) {
1492                 DRM_ERROR("Failed to init MEC BOs!\n");
1493                 return r;
1494         }
1495
1496         /* set up the gfx ring */
1497         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
1498                 ring = &adev->gfx.gfx_ring[i];
1499                 ring->ring_obj = NULL;
1500                 if (!i)
1501                         sprintf(ring->name, "gfx");
1502                 else
1503                         sprintf(ring->name, "gfx_%d", i);
1504                 ring->use_doorbell = true;
1505                 ring->doorbell_index = AMDGPU_DOORBELL64_GFX_RING0 << 1;
1506                 r = amdgpu_ring_init(adev, ring, 1024,
1507                                      &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
1508                 if (r)
1509                         return r;
1510         }
1511
1512         /* set up the compute queues - allocate horizontally across pipes */
1513         ring_id = 0;
1514         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1515                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1516                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
1517                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j))
1518                                         continue;
1519
1520                                 r = gfx_v9_0_compute_ring_init(adev,
1521                                                                ring_id,
1522                                                                i, k, j);
1523                                 if (r)
1524                                         return r;
1525
1526                                 ring_id++;
1527                         }
1528                 }
1529         }
1530
1531         r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE);
1532         if (r) {
1533                 DRM_ERROR("Failed to init KIQ BOs!\n");
1534                 return r;
1535         }
1536
1537         kiq = &adev->gfx.kiq;
1538         r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
1539         if (r)
1540                 return r;
1541
1542         /* create MQD for all compute queues as wel as KIQ for SRIOV case */
1543         r = amdgpu_gfx_compute_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation));
1544         if (r)
1545                 return r;
1546
1547         /* reserve GDS, GWS and OA resource for gfx */
1548         r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
1549                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
1550                                     &adev->gds.gds_gfx_bo, NULL, NULL);
1551         if (r)
1552                 return r;
1553
1554         r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
1555                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
1556                                     &adev->gds.gws_gfx_bo, NULL, NULL);
1557         if (r)
1558                 return r;
1559
1560         r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
1561                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
1562                                     &adev->gds.oa_gfx_bo, NULL, NULL);
1563         if (r)
1564                 return r;
1565
1566         adev->gfx.ce_ram_size = 0x8000;
1567
1568         r = gfx_v9_0_gpu_early_init(adev);
1569         if (r)
1570                 return r;
1571
1572         r = gfx_v9_0_ngg_init(adev);
1573         if (r)
1574                 return r;
1575
1576         return 0;
1577 }
1578
1579
1580 static int gfx_v9_0_sw_fini(void *handle)
1581 {
1582         int i;
1583         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1584
1585         amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
1586         amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
1587         amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
1588
1589         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1590                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1591         for (i = 0; i < adev->gfx.num_compute_rings; i++)
1592                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1593
1594         amdgpu_gfx_compute_mqd_sw_fini(adev);
1595         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
1596         amdgpu_gfx_kiq_fini(adev);
1597
1598         gfx_v9_0_mec_fini(adev);
1599         gfx_v9_0_ngg_fini(adev);
1600         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
1601                                 &adev->gfx.rlc.clear_state_gpu_addr,
1602                                 (void **)&adev->gfx.rlc.cs_ptr);
1603         if (adev->asic_type == CHIP_RAVEN) {
1604                 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
1605                                 &adev->gfx.rlc.cp_table_gpu_addr,
1606                                 (void **)&adev->gfx.rlc.cp_table_ptr);
1607         }
1608         gfx_v9_0_free_microcode(adev);
1609
1610         return 0;
1611 }
1612
1613
1614 static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev)
1615 {
1616         /* TODO */
1617 }
1618
1619 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance)
1620 {
1621         u32 data;
1622
1623         if (instance == 0xffffffff)
1624                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1625         else
1626                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1627
1628         if (se_num == 0xffffffff)
1629                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1630         else
1631                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1632
1633         if (sh_num == 0xffffffff)
1634                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1635         else
1636                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1637
1638         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
1639 }
1640
1641 static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1642 {
1643         u32 data, mask;
1644
1645         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
1646         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
1647
1648         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1649         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1650
1651         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1652                                          adev->gfx.config.max_sh_per_se);
1653
1654         return (~data) & mask;
1655 }
1656
1657 static void gfx_v9_0_setup_rb(struct amdgpu_device *adev)
1658 {
1659         int i, j;
1660         u32 data;
1661         u32 active_rbs = 0;
1662         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1663                                         adev->gfx.config.max_sh_per_se;
1664
1665         mutex_lock(&adev->grbm_idx_mutex);
1666         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1667                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1668                         gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1669                         data = gfx_v9_0_get_rb_active_bitmap(adev);
1670                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1671                                                rb_bitmap_width_per_sh);
1672                 }
1673         }
1674         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1675         mutex_unlock(&adev->grbm_idx_mutex);
1676
1677         adev->gfx.config.backend_enable_mask = active_rbs;
1678         adev->gfx.config.num_rbs = hweight32(active_rbs);
1679 }
1680
1681 #define DEFAULT_SH_MEM_BASES    (0x6000)
1682 #define FIRST_COMPUTE_VMID      (8)
1683 #define LAST_COMPUTE_VMID       (16)
1684 static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
1685 {
1686         int i;
1687         uint32_t sh_mem_config;
1688         uint32_t sh_mem_bases;
1689
1690         /*
1691          * Configure apertures:
1692          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
1693          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
1694          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
1695          */
1696         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1697
1698         sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
1699                         SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1700                         SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
1701
1702         mutex_lock(&adev->srbm_mutex);
1703         for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1704                 soc15_grbm_select(adev, 0, 0, 0, i);
1705                 /* CP and shaders */
1706                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
1707                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
1708         }
1709         soc15_grbm_select(adev, 0, 0, 0, 0);
1710         mutex_unlock(&adev->srbm_mutex);
1711 }
1712
1713 static void gfx_v9_0_gpu_init(struct amdgpu_device *adev)
1714 {
1715         u32 tmp;
1716         int i;
1717
1718         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
1719
1720         gfx_v9_0_tiling_mode_table_init(adev);
1721
1722         gfx_v9_0_setup_rb(adev);
1723         gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);
1724         adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2);
1725
1726         /* XXX SH_MEM regs */
1727         /* where to put LDS, scratch, GPUVM in FSA64 space */
1728         mutex_lock(&adev->srbm_mutex);
1729         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids; i++) {
1730                 soc15_grbm_select(adev, 0, 0, 0, i);
1731                 /* CP and shaders */
1732                 if (i == 0) {
1733                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
1734                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1735                         WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
1736                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0);
1737                 } else {
1738                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
1739                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1740                         WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
1741                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
1742                                 (adev->gmc.private_aperture_start >> 48));
1743                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
1744                                 (adev->gmc.shared_aperture_start >> 48));
1745                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
1746                 }
1747         }
1748         soc15_grbm_select(adev, 0, 0, 0, 0);
1749
1750         mutex_unlock(&adev->srbm_mutex);
1751
1752         gfx_v9_0_init_compute_vmid(adev);
1753
1754         mutex_lock(&adev->grbm_idx_mutex);
1755         /*
1756          * making sure that the following register writes will be broadcasted
1757          * to all the shaders
1758          */
1759         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1760
1761         WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE,
1762                    (adev->gfx.config.sc_prim_fifo_size_frontend <<
1763                         PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1764                    (adev->gfx.config.sc_prim_fifo_size_backend <<
1765                         PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1766                    (adev->gfx.config.sc_hiz_tile_fifo_size <<
1767                         PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1768                    (adev->gfx.config.sc_earlyz_tile_fifo_size <<
1769                         PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
1770         mutex_unlock(&adev->grbm_idx_mutex);
1771
1772 }
1773
1774 static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
1775 {
1776         u32 i, j, k;
1777         u32 mask;
1778
1779         mutex_lock(&adev->grbm_idx_mutex);
1780         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1781                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1782                         gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1783                         for (k = 0; k < adev->usec_timeout; k++) {
1784                                 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0)
1785                                         break;
1786                                 udelay(1);
1787                         }
1788                         if (k == adev->usec_timeout) {
1789                                 gfx_v9_0_select_se_sh(adev, 0xffffffff,
1790                                                       0xffffffff, 0xffffffff);
1791                                 mutex_unlock(&adev->grbm_idx_mutex);
1792                                 DRM_INFO("Timeout wait for RLC serdes %u,%u\n",
1793                                          i, j);
1794                                 return;
1795                         }
1796                 }
1797         }
1798         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1799         mutex_unlock(&adev->grbm_idx_mutex);
1800
1801         mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
1802                 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
1803                 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
1804                 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
1805         for (k = 0; k < adev->usec_timeout; k++) {
1806                 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
1807                         break;
1808                 udelay(1);
1809         }
1810 }
1811
1812 static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1813                                                bool enable)
1814 {
1815         u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
1816
1817         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
1818         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
1819         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
1820         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
1821
1822         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
1823 }
1824
1825 static void gfx_v9_0_init_csb(struct amdgpu_device *adev)
1826 {
1827         /* csib */
1828         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI),
1829                         adev->gfx.rlc.clear_state_gpu_addr >> 32);
1830         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO),
1831                         adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
1832         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH),
1833                         adev->gfx.rlc.clear_state_size);
1834 }
1835
1836 static void gfx_v9_1_parse_ind_reg_list(int *register_list_format,
1837                                 int indirect_offset,
1838                                 int list_size,
1839                                 int *unique_indirect_regs,
1840                                 int *unique_indirect_reg_count,
1841                                 int *indirect_start_offsets,
1842                                 int *indirect_start_offsets_count)
1843 {
1844         int idx;
1845
1846         for (; indirect_offset < list_size; indirect_offset++) {
1847                 indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset;
1848                 *indirect_start_offsets_count = *indirect_start_offsets_count + 1;
1849
1850                 while (register_list_format[indirect_offset] != 0xFFFFFFFF) {
1851                         indirect_offset += 2;
1852
1853                         /* look for the matching indice */
1854                         for (idx = 0; idx < *unique_indirect_reg_count; idx++) {
1855                                 if (unique_indirect_regs[idx] ==
1856                                         register_list_format[indirect_offset] ||
1857                                         !unique_indirect_regs[idx])
1858                                         break;
1859                         }
1860
1861                         BUG_ON(idx >= *unique_indirect_reg_count);
1862
1863                         if (!unique_indirect_regs[idx])
1864                                 unique_indirect_regs[idx] = register_list_format[indirect_offset];
1865
1866                         indirect_offset++;
1867                 }
1868         }
1869 }
1870
1871 static int gfx_v9_1_init_rlc_save_restore_list(struct amdgpu_device *adev)
1872 {
1873         int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
1874         int unique_indirect_reg_count = 0;
1875
1876         int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
1877         int indirect_start_offsets_count = 0;
1878
1879         int list_size = 0;
1880         int i = 0, j = 0;
1881         u32 tmp = 0;
1882
1883         u32 *register_list_format =
1884                 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
1885         if (!register_list_format)
1886                 return -ENOMEM;
1887         memcpy(register_list_format, adev->gfx.rlc.register_list_format,
1888                 adev->gfx.rlc.reg_list_format_size_bytes);
1889
1890         /* setup unique_indirect_regs array and indirect_start_offsets array */
1891         unique_indirect_reg_count = ARRAY_SIZE(unique_indirect_regs);
1892         gfx_v9_1_parse_ind_reg_list(register_list_format,
1893                                     adev->gfx.rlc.reg_list_format_direct_reg_list_length,
1894                                     adev->gfx.rlc.reg_list_format_size_bytes >> 2,
1895                                     unique_indirect_regs,
1896                                     &unique_indirect_reg_count,
1897                                     indirect_start_offsets,
1898                                     &indirect_start_offsets_count);
1899
1900         /* enable auto inc in case it is disabled */
1901         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
1902         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
1903         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
1904
1905         /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */
1906         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR),
1907                 RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET);
1908         for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
1909                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
1910                         adev->gfx.rlc.register_restore[i]);
1911
1912         /* load indirect register */
1913         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1914                 adev->gfx.rlc.reg_list_format_start);
1915
1916         /* direct register portion */
1917         for (i = 0; i < adev->gfx.rlc.reg_list_format_direct_reg_list_length; i++)
1918                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
1919                         register_list_format[i]);
1920
1921         /* indirect register portion */
1922         while (i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2)) {
1923                 if (register_list_format[i] == 0xFFFFFFFF) {
1924                         WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
1925                         continue;
1926                 }
1927
1928                 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
1929                 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
1930
1931                 for (j = 0; j < unique_indirect_reg_count; j++) {
1932                         if (register_list_format[i] == unique_indirect_regs[j]) {
1933                                 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, j);
1934                                 break;
1935                         }
1936                 }
1937
1938                 BUG_ON(j >= unique_indirect_reg_count);
1939
1940                 i++;
1941         }
1942
1943         /* set save/restore list size */
1944         list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
1945         list_size = list_size >> 1;
1946         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1947                 adev->gfx.rlc.reg_restore_list_size);
1948         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size);
1949
1950         /* write the starting offsets to RLC scratch ram */
1951         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1952                 adev->gfx.rlc.starting_offsets_start);
1953         for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++)
1954                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
1955                        indirect_start_offsets[i]);
1956
1957         /* load unique indirect regs*/
1958         for (i = 0; i < ARRAY_SIZE(unique_indirect_regs); i++) {
1959                 if (unique_indirect_regs[i] != 0) {
1960                         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0)
1961                                + GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[i],
1962                                unique_indirect_regs[i] & 0x3FFFF);
1963
1964                         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0)
1965                                + GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[i],
1966                                unique_indirect_regs[i] >> 20);
1967                 }
1968         }
1969
1970         kfree(register_list_format);
1971         return 0;
1972 }
1973
1974 static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev)
1975 {
1976         WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1);
1977 }
1978
1979 static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev,
1980                                              bool enable)
1981 {
1982         uint32_t data = 0;
1983         uint32_t default_data = 0;
1984
1985         default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS));
1986         if (enable == true) {
1987                 /* enable GFXIP control over CGPG */
1988                 data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
1989                 if(default_data != data)
1990                         WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
1991
1992                 /* update status */
1993                 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK;
1994                 data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT);
1995                 if(default_data != data)
1996                         WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
1997         } else {
1998                 /* restore GFXIP control over GCPG */
1999                 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
2000                 if(default_data != data)
2001                         WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
2002         }
2003 }
2004
2005 static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev)
2006 {
2007         uint32_t data = 0;
2008
2009         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2010                               AMD_PG_SUPPORT_GFX_SMG |
2011                               AMD_PG_SUPPORT_GFX_DMG)) {
2012                 /* init IDLE_POLL_COUNT = 60 */
2013                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));
2014                 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
2015                 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
2016                 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data);
2017
2018                 /* init RLC PG Delay */
2019                 data = 0;
2020                 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT);
2021                 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT);
2022                 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT);
2023                 data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT);
2024                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data);
2025
2026                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2));
2027                 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK;
2028                 data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT);
2029                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data);
2030
2031                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3));
2032                 data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK;
2033                 data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT);
2034                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data);
2035
2036                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL));
2037                 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
2038
2039                 /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */
2040                 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
2041                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data);
2042
2043                 pwr_10_0_gfxip_control_over_cgpg(adev, true);
2044         }
2045 }
2046
2047 static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
2048                                                 bool enable)
2049 {
2050         uint32_t data = 0;
2051         uint32_t default_data = 0;
2052
2053         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2054         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2055                              SMU_CLK_SLOWDOWN_ON_PU_ENABLE,
2056                              enable ? 1 : 0);
2057         if (default_data != data)
2058                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2059 }
2060
2061 static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
2062                                                 bool enable)
2063 {
2064         uint32_t data = 0;
2065         uint32_t default_data = 0;
2066
2067         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2068         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2069                              SMU_CLK_SLOWDOWN_ON_PD_ENABLE,
2070                              enable ? 1 : 0);
2071         if(default_data != data)
2072                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2073 }
2074
2075 static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev,
2076                                         bool enable)
2077 {
2078         uint32_t data = 0;
2079         uint32_t default_data = 0;
2080
2081         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2082         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2083                              CP_PG_DISABLE,
2084                              enable ? 0 : 1);
2085         if(default_data != data)
2086                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2087 }
2088
2089 static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
2090                                                 bool enable)
2091 {
2092         uint32_t data, default_data;
2093
2094         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2095         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2096                              GFX_POWER_GATING_ENABLE,
2097                              enable ? 1 : 0);
2098         if(default_data != data)
2099                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2100 }
2101
2102 static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev,
2103                                                 bool enable)
2104 {
2105         uint32_t data, default_data;
2106
2107         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2108         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2109                              GFX_PIPELINE_PG_ENABLE,
2110                              enable ? 1 : 0);
2111         if(default_data != data)
2112                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2113
2114         if (!enable)
2115                 /* read any GFX register to wake up GFX */
2116                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL));
2117 }
2118
2119 static void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
2120                                                        bool enable)
2121 {
2122         uint32_t data, default_data;
2123
2124         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2125         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2126                              STATIC_PER_CU_PG_ENABLE,
2127                              enable ? 1 : 0);
2128         if(default_data != data)
2129                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2130 }
2131
2132 static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
2133                                                 bool enable)
2134 {
2135         uint32_t data, default_data;
2136
2137         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2138         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2139                              DYN_PER_CU_PG_ENABLE,
2140                              enable ? 1 : 0);
2141         if(default_data != data)
2142                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2143 }
2144
2145 static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
2146 {
2147         if (!adev->gfx.rlc.is_rlc_v2_1)
2148                 return;
2149
2150         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2151                               AMD_PG_SUPPORT_GFX_SMG |
2152                               AMD_PG_SUPPORT_GFX_DMG |
2153                               AMD_PG_SUPPORT_CP |
2154                               AMD_PG_SUPPORT_GDS |
2155                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
2156                 gfx_v9_0_init_csb(adev);
2157                 gfx_v9_1_init_rlc_save_restore_list(adev);
2158                 gfx_v9_0_enable_save_restore_machine(adev);
2159
2160                 WREG32(mmRLC_JUMP_TABLE_RESTORE,
2161                        adev->gfx.rlc.cp_table_gpu_addr >> 8);
2162                 gfx_v9_0_init_gfx_power_gating(adev);
2163         }
2164 }
2165
2166 void gfx_v9_0_rlc_stop(struct amdgpu_device *adev)
2167 {
2168         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0);
2169         gfx_v9_0_enable_gui_idle_interrupt(adev, false);
2170         gfx_v9_0_wait_for_rlc_serdes(adev);
2171 }
2172
2173 static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev)
2174 {
2175         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2176         udelay(50);
2177         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2178         udelay(50);
2179 }
2180
2181 static void gfx_v9_0_rlc_start(struct amdgpu_device *adev)
2182 {
2183 #ifdef AMDGPU_RLC_DEBUG_RETRY
2184         u32 rlc_ucode_ver;
2185 #endif
2186
2187         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
2188
2189         /* carrizo do enable cp interrupt after cp inited */
2190         if (!(adev->flags & AMD_IS_APU))
2191                 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
2192
2193         udelay(50);
2194
2195 #ifdef AMDGPU_RLC_DEBUG_RETRY
2196         /* RLC_GPM_GENERAL_6 : RLC Ucode version */
2197         rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6);
2198         if(rlc_ucode_ver == 0x108) {
2199                 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n",
2200                                 rlc_ucode_ver, adev->gfx.rlc_fw_version);
2201                 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles,
2202                  * default is 0x9C4 to create a 100us interval */
2203                 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4);
2204                 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
2205                  * to disable the page fault retry interrupts, default is
2206                  * 0x100 (256) */
2207                 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100);
2208         }
2209 #endif
2210 }
2211
2212 static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev)
2213 {
2214         const struct rlc_firmware_header_v2_0 *hdr;
2215         const __le32 *fw_data;
2216         unsigned i, fw_size;
2217
2218         if (!adev->gfx.rlc_fw)
2219                 return -EINVAL;
2220
2221         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2222         amdgpu_ucode_print_rlc_hdr(&hdr->header);
2223
2224         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2225                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2226         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2227
2228         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
2229                         RLCG_UCODE_LOADING_START_ADDRESS);
2230         for (i = 0; i < fw_size; i++)
2231                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
2232         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
2233
2234         return 0;
2235 }
2236
2237 static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
2238 {
2239         int r;
2240
2241         if (amdgpu_sriov_vf(adev)) {
2242                 gfx_v9_0_init_csb(adev);
2243                 return 0;
2244         }
2245
2246         gfx_v9_0_rlc_stop(adev);
2247
2248         /* disable CG */
2249         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
2250
2251         /* disable PG */
2252         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
2253
2254         gfx_v9_0_rlc_reset(adev);
2255
2256         gfx_v9_0_init_pg(adev);
2257
2258         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2259                 /* legacy rlc firmware loading */
2260                 r = gfx_v9_0_rlc_load_microcode(adev);
2261                 if (r)
2262                         return r;
2263         }
2264
2265         if (adev->asic_type == CHIP_RAVEN) {
2266                 if (amdgpu_lbpw != 0)
2267                         gfx_v9_0_enable_lbpw(adev, true);
2268                 else
2269                         gfx_v9_0_enable_lbpw(adev, false);
2270         }
2271
2272         gfx_v9_0_rlc_start(adev);
2273
2274         return 0;
2275 }
2276
2277 static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2278 {
2279         int i;
2280         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
2281
2282         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2283         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2284         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
2285         if (!enable) {
2286                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2287                         adev->gfx.gfx_ring[i].ready = false;
2288         }
2289         WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
2290         udelay(50);
2291 }
2292
2293 static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2294 {
2295         const struct gfx_firmware_header_v1_0 *pfp_hdr;
2296         const struct gfx_firmware_header_v1_0 *ce_hdr;
2297         const struct gfx_firmware_header_v1_0 *me_hdr;
2298         const __le32 *fw_data;
2299         unsigned i, fw_size;
2300
2301         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2302                 return -EINVAL;
2303
2304         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2305                 adev->gfx.pfp_fw->data;
2306         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2307                 adev->gfx.ce_fw->data;
2308         me_hdr = (const struct gfx_firmware_header_v1_0 *)
2309                 adev->gfx.me_fw->data;
2310
2311         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2312         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2313         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2314
2315         gfx_v9_0_cp_gfx_enable(adev, false);
2316
2317         /* PFP */
2318         fw_data = (const __le32 *)
2319                 (adev->gfx.pfp_fw->data +
2320                  le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2321         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2322         WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0);
2323         for (i = 0; i < fw_size; i++)
2324                 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2325         WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2326
2327         /* CE */
2328         fw_data = (const __le32 *)
2329                 (adev->gfx.ce_fw->data +
2330                  le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2331         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2332         WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0);
2333         for (i = 0; i < fw_size; i++)
2334                 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2335         WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2336
2337         /* ME */
2338         fw_data = (const __le32 *)
2339                 (adev->gfx.me_fw->data +
2340                  le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2341         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2342         WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0);
2343         for (i = 0; i < fw_size; i++)
2344                 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2345         WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2346
2347         return 0;
2348 }
2349
2350 static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)
2351 {
2352         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2353         const struct cs_section_def *sect = NULL;
2354         const struct cs_extent_def *ext = NULL;
2355         int r, i, tmp;
2356
2357         /* init the CP */
2358         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2359         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
2360
2361         gfx_v9_0_cp_gfx_enable(adev, true);
2362
2363         r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3);
2364         if (r) {
2365                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2366                 return r;
2367         }
2368
2369         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2370         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2371
2372         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2373         amdgpu_ring_write(ring, 0x80000000);
2374         amdgpu_ring_write(ring, 0x80000000);
2375
2376         for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
2377                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2378                         if (sect->id == SECT_CONTEXT) {
2379                                 amdgpu_ring_write(ring,
2380                                        PACKET3(PACKET3_SET_CONTEXT_REG,
2381                                                ext->reg_count));
2382                                 amdgpu_ring_write(ring,
2383                                        ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2384                                 for (i = 0; i < ext->reg_count; i++)
2385                                         amdgpu_ring_write(ring, ext->extent[i]);
2386                         }
2387                 }
2388         }
2389
2390         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2391         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2392
2393         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2394         amdgpu_ring_write(ring, 0);
2395
2396         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2397         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2398         amdgpu_ring_write(ring, 0x8000);
2399         amdgpu_ring_write(ring, 0x8000);
2400
2401         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1));
2402         tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE |
2403                 (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START));
2404         amdgpu_ring_write(ring, tmp);
2405         amdgpu_ring_write(ring, 0);
2406
2407         amdgpu_ring_commit(ring);
2408
2409         return 0;
2410 }
2411
2412 static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
2413 {
2414         struct amdgpu_ring *ring;
2415         u32 tmp;
2416         u32 rb_bufsz;
2417         u64 rb_addr, rptr_addr, wptr_gpu_addr;
2418
2419         /* Set the write pointer delay */
2420         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
2421
2422         /* set the RB to use vmid 0 */
2423         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
2424
2425         /* Set ring buffer size */
2426         ring = &adev->gfx.gfx_ring[0];
2427         rb_bufsz = order_base_2(ring->ring_size / 8);
2428         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2429         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2430 #ifdef __BIG_ENDIAN
2431         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
2432 #endif
2433         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2434
2435         /* Initialize the ring buffer's write pointers */
2436         ring->wptr = 0;
2437         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2438         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
2439
2440         /* set the wb address wether it's enabled or not */
2441         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2442         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2443         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
2444
2445         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2446         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
2447         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
2448
2449         mdelay(1);
2450         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2451
2452         rb_addr = ring->gpu_addr >> 8;
2453         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
2454         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2455
2456         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
2457         if (ring->use_doorbell) {
2458                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2459                                     DOORBELL_OFFSET, ring->doorbell_index);
2460                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2461                                     DOORBELL_EN, 1);
2462         } else {
2463                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
2464         }
2465         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
2466
2467         tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2468                         DOORBELL_RANGE_LOWER, ring->doorbell_index);
2469         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
2470
2471         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
2472                        CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2473
2474
2475         /* start the ring */
2476         gfx_v9_0_cp_gfx_start(adev);
2477         ring->ready = true;
2478
2479         return 0;
2480 }
2481
2482 static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2483 {
2484         int i;
2485
2486         if (enable) {
2487                 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
2488         } else {
2489                 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
2490                         (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2491                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2492                         adev->gfx.compute_ring[i].ready = false;
2493                 adev->gfx.kiq.ring.ready = false;
2494         }
2495         udelay(50);
2496 }
2497
2498 static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2499 {
2500         const struct gfx_firmware_header_v1_0 *mec_hdr;
2501         const __le32 *fw_data;
2502         unsigned i;
2503         u32 tmp;
2504
2505         if (!adev->gfx.mec_fw)
2506                 return -EINVAL;
2507
2508         gfx_v9_0_cp_compute_enable(adev, false);
2509
2510         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2511         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2512
2513         fw_data = (const __le32 *)
2514                 (adev->gfx.mec_fw->data +
2515                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2516         tmp = 0;
2517         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
2518         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
2519         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
2520
2521         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
2522                 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
2523         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
2524                 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
2525
2526         /* MEC1 */
2527         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
2528                          mec_hdr->jt_offset);
2529         for (i = 0; i < mec_hdr->jt_size; i++)
2530                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
2531                         le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
2532
2533         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
2534                         adev->gfx.mec_fw_version);
2535         /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
2536
2537         return 0;
2538 }
2539
2540 /* KIQ functions */
2541 static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
2542 {
2543         uint32_t tmp;
2544         struct amdgpu_device *adev = ring->adev;
2545
2546         /* tell RLC which is KIQ queue */
2547         tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
2548         tmp &= 0xffffff00;
2549         tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
2550         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2551         tmp |= 0x80;
2552         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2553 }
2554
2555 static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev)
2556 {
2557         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
2558         uint32_t scratch, tmp = 0;
2559         uint64_t queue_mask = 0;
2560         int r, i;
2561
2562         for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
2563                 if (!test_bit(i, adev->gfx.mec.queue_bitmap))
2564                         continue;
2565
2566                 /* This situation may be hit in the future if a new HW
2567                  * generation exposes more than 64 queues. If so, the
2568                  * definition of queue_mask needs updating */
2569                 if (WARN_ON(i >= (sizeof(queue_mask)*8))) {
2570                         DRM_ERROR("Invalid KCQ enabled: %d\n", i);
2571                         break;
2572                 }
2573
2574                 queue_mask |= (1ull << i);
2575         }
2576
2577         r = amdgpu_gfx_scratch_get(adev, &scratch);
2578         if (r) {
2579                 DRM_ERROR("Failed to get scratch reg (%d).\n", r);
2580                 return r;
2581         }
2582         WREG32(scratch, 0xCAFEDEAD);
2583
2584         r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 11);
2585         if (r) {
2586                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
2587                 amdgpu_gfx_scratch_free(adev, scratch);
2588                 return r;
2589         }
2590
2591         /* set resources */
2592         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
2593         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
2594                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
2595         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
2596         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
2597         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
2598         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
2599         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
2600         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
2601         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2602                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2603                 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
2604                 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2605
2606                 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
2607                 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
2608                 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
2609                                   PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
2610                                   PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
2611                                   PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
2612                                   PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
2613                                   PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
2614                                   PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
2615                                   PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
2616                                   PACKET3_MAP_QUEUES_ENGINE_SEL(0) | /* engine_sel: compute */
2617                                   PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
2618                 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
2619                 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
2620                 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
2621                 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
2622                 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
2623         }
2624         /* write to scratch for completion */
2625         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2626         amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2627         amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
2628         amdgpu_ring_commit(kiq_ring);
2629
2630         for (i = 0; i < adev->usec_timeout; i++) {
2631                 tmp = RREG32(scratch);
2632                 if (tmp == 0xDEADBEEF)
2633                         break;
2634                 DRM_UDELAY(1);
2635         }
2636         if (i >= adev->usec_timeout) {
2637                 DRM_ERROR("KCQ enable failed (scratch(0x%04X)=0x%08X)\n",
2638                           scratch, tmp);
2639                 r = -EINVAL;
2640         }
2641         amdgpu_gfx_scratch_free(adev, scratch);
2642
2643         return r;
2644 }
2645
2646 static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
2647 {
2648         struct amdgpu_device *adev = ring->adev;
2649         struct v9_mqd *mqd = ring->mqd_ptr;
2650         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
2651         uint32_t tmp;
2652
2653         mqd->header = 0xC0310800;
2654         mqd->compute_pipelinestat_enable = 0x00000001;
2655         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
2656         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
2657         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
2658         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
2659         mqd->compute_misc_reserved = 0x00000003;
2660
2661         mqd->dynamic_cu_mask_addr_lo =
2662                 lower_32_bits(ring->mqd_gpu_addr
2663                               + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
2664         mqd->dynamic_cu_mask_addr_hi =
2665                 upper_32_bits(ring->mqd_gpu_addr
2666                               + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
2667
2668         eop_base_addr = ring->eop_gpu_addr >> 8;
2669         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
2670         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
2671
2672         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2673         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
2674         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
2675                         (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1));
2676
2677         mqd->cp_hqd_eop_control = tmp;
2678
2679         /* enable doorbell? */
2680         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
2681
2682         if (ring->use_doorbell) {
2683                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2684                                     DOORBELL_OFFSET, ring->doorbell_index);
2685                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2686                                     DOORBELL_EN, 1);
2687                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2688                                     DOORBELL_SOURCE, 0);
2689                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2690                                     DOORBELL_HIT, 0);
2691         } else {
2692                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2693                                          DOORBELL_EN, 0);
2694         }
2695
2696         mqd->cp_hqd_pq_doorbell_control = tmp;
2697
2698         /* disable the queue if it's active */
2699         ring->wptr = 0;
2700         mqd->cp_hqd_dequeue_request = 0;
2701         mqd->cp_hqd_pq_rptr = 0;
2702         mqd->cp_hqd_pq_wptr_lo = 0;
2703         mqd->cp_hqd_pq_wptr_hi = 0;
2704
2705         /* set the pointer to the MQD */
2706         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
2707         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
2708
2709         /* set MQD vmid to 0 */
2710         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
2711         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
2712         mqd->cp_mqd_control = tmp;
2713
2714         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2715         hqd_gpu_addr = ring->gpu_addr >> 8;
2716         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
2717         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
2718
2719         /* set up the HQD, this is similar to CP_RB0_CNTL */
2720         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
2721         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
2722                             (order_base_2(ring->ring_size / 4) - 1));
2723         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
2724                         ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
2725 #ifdef __BIG_ENDIAN
2726         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
2727 #endif
2728         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
2729         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
2730         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
2731         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
2732         mqd->cp_hqd_pq_control = tmp;
2733
2734         /* set the wb address whether it's enabled or not */
2735         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2736         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
2737         mqd->cp_hqd_pq_rptr_report_addr_hi =
2738                 upper_32_bits(wb_gpu_addr) & 0xffff;
2739
2740         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2741         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2742         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
2743         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
2744
2745         tmp = 0;
2746         /* enable the doorbell if requested */
2747         if (ring->use_doorbell) {
2748                 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
2749                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2750                                 DOORBELL_OFFSET, ring->doorbell_index);
2751
2752                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2753                                          DOORBELL_EN, 1);
2754                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2755                                          DOORBELL_SOURCE, 0);
2756                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2757                                          DOORBELL_HIT, 0);
2758         }
2759
2760         mqd->cp_hqd_pq_doorbell_control = tmp;
2761
2762         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2763         ring->wptr = 0;
2764         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
2765
2766         /* set the vmid for the queue */
2767         mqd->cp_hqd_vmid = 0;
2768
2769         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
2770         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
2771         mqd->cp_hqd_persistent_state = tmp;
2772
2773         /* set MIN_IB_AVAIL_SIZE */
2774         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
2775         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
2776         mqd->cp_hqd_ib_control = tmp;
2777
2778         /* activate the queue */
2779         mqd->cp_hqd_active = 1;
2780
2781         return 0;
2782 }
2783
2784 static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
2785 {
2786         struct amdgpu_device *adev = ring->adev;
2787         struct v9_mqd *mqd = ring->mqd_ptr;
2788         int j;
2789
2790         /* disable wptr polling */
2791         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
2792
2793         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
2794                mqd->cp_hqd_eop_base_addr_lo);
2795         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
2796                mqd->cp_hqd_eop_base_addr_hi);
2797
2798         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2799         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
2800                mqd->cp_hqd_eop_control);
2801
2802         /* enable doorbell? */
2803         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
2804                mqd->cp_hqd_pq_doorbell_control);
2805
2806         /* disable the queue if it's active */
2807         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
2808                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
2809                 for (j = 0; j < adev->usec_timeout; j++) {
2810                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
2811                                 break;
2812                         udelay(1);
2813                 }
2814                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
2815                        mqd->cp_hqd_dequeue_request);
2816                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
2817                        mqd->cp_hqd_pq_rptr);
2818                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
2819                        mqd->cp_hqd_pq_wptr_lo);
2820                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
2821                        mqd->cp_hqd_pq_wptr_hi);
2822         }
2823
2824         /* set the pointer to the MQD */
2825         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
2826                mqd->cp_mqd_base_addr_lo);
2827         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
2828                mqd->cp_mqd_base_addr_hi);
2829
2830         /* set MQD vmid to 0 */
2831         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
2832                mqd->cp_mqd_control);
2833
2834         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2835         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
2836                mqd->cp_hqd_pq_base_lo);
2837         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
2838                mqd->cp_hqd_pq_base_hi);
2839
2840         /* set up the HQD, this is similar to CP_RB0_CNTL */
2841         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
2842                mqd->cp_hqd_pq_control);
2843
2844         /* set the wb address whether it's enabled or not */
2845         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
2846                                 mqd->cp_hqd_pq_rptr_report_addr_lo);
2847         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
2848                                 mqd->cp_hqd_pq_rptr_report_addr_hi);
2849
2850         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2851         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
2852                mqd->cp_hqd_pq_wptr_poll_addr_lo);
2853         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
2854                mqd->cp_hqd_pq_wptr_poll_addr_hi);
2855
2856         /* enable the doorbell if requested */
2857         if (ring->use_doorbell) {
2858                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
2859                                         (AMDGPU_DOORBELL64_KIQ *2) << 2);
2860                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
2861                                         (AMDGPU_DOORBELL64_USERQUEUE_END * 2) << 2);
2862         }
2863
2864         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
2865                mqd->cp_hqd_pq_doorbell_control);
2866
2867         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2868         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
2869                mqd->cp_hqd_pq_wptr_lo);
2870         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
2871                mqd->cp_hqd_pq_wptr_hi);
2872
2873         /* set the vmid for the queue */
2874         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
2875
2876         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
2877                mqd->cp_hqd_persistent_state);
2878
2879         /* activate the queue */
2880         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
2881                mqd->cp_hqd_active);
2882
2883         if (ring->use_doorbell)
2884                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
2885
2886         return 0;
2887 }
2888
2889 static int gfx_v9_0_kiq_fini_register(struct amdgpu_ring *ring)
2890 {
2891         struct amdgpu_device *adev = ring->adev;
2892         int j;
2893
2894         /* disable the queue if it's active */
2895         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
2896
2897                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
2898
2899                 for (j = 0; j < adev->usec_timeout; j++) {
2900                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
2901                                 break;
2902                         udelay(1);
2903                 }
2904
2905                 if (j == AMDGPU_MAX_USEC_TIMEOUT) {
2906                         DRM_DEBUG("KIQ dequeue request failed.\n");
2907
2908                         /* Manual disable if dequeue request times out */
2909                         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
2910                 }
2911
2912                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
2913                       0);
2914         }
2915
2916         WREG32_SOC15(GC, 0, mmCP_HQD_IQ_TIMER, 0);
2917         WREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL, 0);
2918         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 0);
2919         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000);
2920         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
2921         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 0);
2922         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0);
2923         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 0);
2924
2925         return 0;
2926 }
2927
2928 static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
2929 {
2930         struct amdgpu_device *adev = ring->adev;
2931         struct v9_mqd *mqd = ring->mqd_ptr;
2932         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
2933
2934         gfx_v9_0_kiq_setting(ring);
2935
2936         if (adev->in_gpu_reset) { /* for GPU_RESET case */
2937                 /* reset MQD to a clean status */
2938                 if (adev->gfx.mec.mqd_backup[mqd_idx])
2939                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
2940
2941                 /* reset ring buffer */
2942                 ring->wptr = 0;
2943                 amdgpu_ring_clear_ring(ring);
2944
2945                 mutex_lock(&adev->srbm_mutex);
2946                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2947                 gfx_v9_0_kiq_init_register(ring);
2948                 soc15_grbm_select(adev, 0, 0, 0, 0);
2949                 mutex_unlock(&adev->srbm_mutex);
2950         } else {
2951                 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
2952                 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
2953                 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
2954                 mutex_lock(&adev->srbm_mutex);
2955                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2956                 gfx_v9_0_mqd_init(ring);
2957                 gfx_v9_0_kiq_init_register(ring);
2958                 soc15_grbm_select(adev, 0, 0, 0, 0);
2959                 mutex_unlock(&adev->srbm_mutex);
2960
2961                 if (adev->gfx.mec.mqd_backup[mqd_idx])
2962                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
2963         }
2964
2965         return 0;
2966 }
2967
2968 static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
2969 {
2970         struct amdgpu_device *adev = ring->adev;
2971         struct v9_mqd *mqd = ring->mqd_ptr;
2972         int mqd_idx = ring - &adev->gfx.compute_ring[0];
2973
2974         if (!adev->in_gpu_reset && !adev->gfx.in_suspend) {
2975                 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
2976                 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
2977                 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
2978                 mutex_lock(&adev->srbm_mutex);
2979                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2980                 gfx_v9_0_mqd_init(ring);
2981                 soc15_grbm_select(adev, 0, 0, 0, 0);
2982                 mutex_unlock(&adev->srbm_mutex);
2983
2984                 if (adev->gfx.mec.mqd_backup[mqd_idx])
2985                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
2986         } else if (adev->in_gpu_reset) { /* for GPU_RESET case */
2987                 /* reset MQD to a clean status */
2988                 if (adev->gfx.mec.mqd_backup[mqd_idx])
2989                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
2990
2991                 /* reset ring buffer */
2992                 ring->wptr = 0;
2993                 amdgpu_ring_clear_ring(ring);
2994         } else {
2995                 amdgpu_ring_clear_ring(ring);
2996         }
2997
2998         return 0;
2999 }
3000
3001 static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)
3002 {
3003         struct amdgpu_ring *ring = NULL;
3004         int r = 0, i;
3005
3006         gfx_v9_0_cp_compute_enable(adev, true);
3007
3008         ring = &adev->gfx.kiq.ring;
3009
3010         r = amdgpu_bo_reserve(ring->mqd_obj, false);
3011         if (unlikely(r != 0))
3012                 goto done;
3013
3014         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3015         if (!r) {
3016                 r = gfx_v9_0_kiq_init_queue(ring);
3017                 amdgpu_bo_kunmap(ring->mqd_obj);
3018                 ring->mqd_ptr = NULL;
3019         }
3020         amdgpu_bo_unreserve(ring->mqd_obj);
3021         if (r)
3022                 goto done;
3023
3024         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3025                 ring = &adev->gfx.compute_ring[i];
3026
3027                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3028                 if (unlikely(r != 0))
3029                         goto done;
3030                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3031                 if (!r) {
3032                         r = gfx_v9_0_kcq_init_queue(ring);
3033                         amdgpu_bo_kunmap(ring->mqd_obj);
3034                         ring->mqd_ptr = NULL;
3035                 }
3036                 amdgpu_bo_unreserve(ring->mqd_obj);
3037                 if (r)
3038                         goto done;
3039         }
3040
3041         r = gfx_v9_0_kiq_kcq_enable(adev);
3042 done:
3043         return r;
3044 }
3045
3046 static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
3047 {
3048         int r, i;
3049         struct amdgpu_ring *ring;
3050
3051         if (!(adev->flags & AMD_IS_APU))
3052                 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
3053
3054         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
3055                 /* legacy firmware loading */
3056                 r = gfx_v9_0_cp_gfx_load_microcode(adev);
3057                 if (r)
3058                         return r;
3059
3060                 r = gfx_v9_0_cp_compute_load_microcode(adev);
3061                 if (r)
3062                         return r;
3063         }
3064
3065         r = gfx_v9_0_cp_gfx_resume(adev);
3066         if (r)
3067                 return r;
3068
3069         r = gfx_v9_0_kiq_resume(adev);
3070         if (r)
3071                 return r;
3072
3073         ring = &adev->gfx.gfx_ring[0];
3074         r = amdgpu_ring_test_ring(ring);
3075         if (r) {
3076                 ring->ready = false;
3077                 return r;
3078         }
3079
3080         ring = &adev->gfx.kiq.ring;
3081         ring->ready = true;
3082         r = amdgpu_ring_test_ring(ring);
3083         if (r)
3084                 ring->ready = false;
3085
3086         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3087                 ring = &adev->gfx.compute_ring[i];
3088
3089                 ring->ready = true;
3090                 r = amdgpu_ring_test_ring(ring);
3091                 if (r)
3092                         ring->ready = false;
3093         }
3094
3095         gfx_v9_0_enable_gui_idle_interrupt(adev, true);
3096
3097         return 0;
3098 }
3099
3100 static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
3101 {
3102         gfx_v9_0_cp_gfx_enable(adev, enable);
3103         gfx_v9_0_cp_compute_enable(adev, enable);
3104 }
3105
3106 static int gfx_v9_0_hw_init(void *handle)
3107 {
3108         int r;
3109         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3110
3111         gfx_v9_0_init_golden_registers(adev);
3112
3113         gfx_v9_0_gpu_init(adev);
3114
3115         r = gfx_v9_0_rlc_resume(adev);
3116         if (r)
3117                 return r;
3118
3119         r = gfx_v9_0_cp_resume(adev);
3120         if (r)
3121                 return r;
3122
3123         r = gfx_v9_0_ngg_en(adev);
3124         if (r)
3125                 return r;
3126
3127         return r;
3128 }
3129
3130 static int gfx_v9_0_kcq_disable(struct amdgpu_ring *kiq_ring,struct amdgpu_ring *ring)
3131 {
3132         struct amdgpu_device *adev = kiq_ring->adev;
3133         uint32_t scratch, tmp = 0;
3134         int r, i;
3135
3136         r = amdgpu_gfx_scratch_get(adev, &scratch);
3137         if (r) {
3138                 DRM_ERROR("Failed to get scratch reg (%d).\n", r);
3139                 return r;
3140         }
3141         WREG32(scratch, 0xCAFEDEAD);
3142
3143         r = amdgpu_ring_alloc(kiq_ring, 10);
3144         if (r) {
3145                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
3146                 amdgpu_gfx_scratch_free(adev, scratch);
3147                 return r;
3148         }
3149
3150         /* unmap queues */
3151         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3152         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3153                                                 PACKET3_UNMAP_QUEUES_ACTION(1) | /* RESET_QUEUES */
3154                                                 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3155                                                 PACKET3_UNMAP_QUEUES_ENGINE_SEL(0) |
3156                                                 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3157         amdgpu_ring_write(kiq_ring, PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3158         amdgpu_ring_write(kiq_ring, 0);
3159         amdgpu_ring_write(kiq_ring, 0);
3160         amdgpu_ring_write(kiq_ring, 0);
3161         /* write to scratch for completion */
3162         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3163         amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
3164         amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
3165         amdgpu_ring_commit(kiq_ring);
3166
3167         for (i = 0; i < adev->usec_timeout; i++) {
3168                 tmp = RREG32(scratch);
3169                 if (tmp == 0xDEADBEEF)
3170                         break;
3171                 DRM_UDELAY(1);
3172         }
3173         if (i >= adev->usec_timeout) {
3174                 DRM_ERROR("KCQ disabled failed (scratch(0x%04X)=0x%08X)\n", scratch, tmp);
3175                 r = -EINVAL;
3176         }
3177         amdgpu_gfx_scratch_free(adev, scratch);
3178         return r;
3179 }
3180
3181 static int gfx_v9_0_hw_fini(void *handle)
3182 {
3183         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3184         int i;
3185
3186         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_GFX,
3187                                                AMD_PG_STATE_UNGATE);
3188
3189         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
3190         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
3191
3192         /* disable KCQ to avoid CPC touch memory not valid anymore */
3193         for (i = 0; i < adev->gfx.num_compute_rings; i++)
3194                 gfx_v9_0_kcq_disable(&adev->gfx.kiq.ring, &adev->gfx.compute_ring[i]);
3195
3196         if (amdgpu_sriov_vf(adev)) {
3197                 gfx_v9_0_cp_gfx_enable(adev, false);
3198                 /* must disable polling for SRIOV when hw finished, otherwise
3199                  * CPC engine may still keep fetching WB address which is already
3200                  * invalid after sw finished and trigger DMAR reading error in
3201                  * hypervisor side.
3202                  */
3203                 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3204                 return 0;
3205         }
3206
3207         /* Use deinitialize sequence from CAIL when unbinding device from driver,
3208          * otherwise KIQ is hanging when binding back
3209          */
3210         if (!adev->in_gpu_reset && !adev->gfx.in_suspend) {
3211                 mutex_lock(&adev->srbm_mutex);
3212                 soc15_grbm_select(adev, adev->gfx.kiq.ring.me,
3213                                 adev->gfx.kiq.ring.pipe,
3214                                 adev->gfx.kiq.ring.queue, 0);
3215                 gfx_v9_0_kiq_fini_register(&adev->gfx.kiq.ring);
3216                 soc15_grbm_select(adev, 0, 0, 0, 0);
3217                 mutex_unlock(&adev->srbm_mutex);
3218         }
3219
3220         gfx_v9_0_cp_enable(adev, false);
3221         gfx_v9_0_rlc_stop(adev);
3222
3223         return 0;
3224 }
3225
3226 static int gfx_v9_0_suspend(void *handle)
3227 {
3228         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3229
3230         adev->gfx.in_suspend = true;
3231         return gfx_v9_0_hw_fini(adev);
3232 }
3233
3234 static int gfx_v9_0_resume(void *handle)
3235 {
3236         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3237         int r;
3238
3239         r = gfx_v9_0_hw_init(adev);
3240         adev->gfx.in_suspend = false;
3241         return r;
3242 }
3243
3244 static bool gfx_v9_0_is_idle(void *handle)
3245 {
3246         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3247
3248         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
3249                                 GRBM_STATUS, GUI_ACTIVE))
3250                 return false;
3251         else
3252                 return true;
3253 }
3254
3255 static int gfx_v9_0_wait_for_idle(void *handle)
3256 {
3257         unsigned i;
3258         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3259
3260         for (i = 0; i < adev->usec_timeout; i++) {
3261                 if (gfx_v9_0_is_idle(handle))
3262                         return 0;
3263                 udelay(1);
3264         }
3265         return -ETIMEDOUT;
3266 }
3267
3268 static int gfx_v9_0_soft_reset(void *handle)
3269 {
3270         u32 grbm_soft_reset = 0;
3271         u32 tmp;
3272         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3273
3274         /* GRBM_STATUS */
3275         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
3276         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
3277                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
3278                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
3279                    GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
3280                    GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
3281                    GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
3282                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3283                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3284                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3285                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
3286         }
3287
3288         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
3289                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3290                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3291         }
3292
3293         /* GRBM_STATUS2 */
3294         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
3295         if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
3296                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3297                                                 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
3298
3299
3300         if (grbm_soft_reset) {
3301                 /* stop the rlc */
3302                 gfx_v9_0_rlc_stop(adev);
3303
3304                 /* Disable GFX parsing/prefetching */
3305                 gfx_v9_0_cp_gfx_enable(adev, false);
3306
3307                 /* Disable MEC parsing/prefetching */
3308                 gfx_v9_0_cp_compute_enable(adev, false);
3309
3310                 if (grbm_soft_reset) {
3311                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3312                         tmp |= grbm_soft_reset;
3313                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3314                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3315                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3316
3317                         udelay(50);
3318
3319                         tmp &= ~grbm_soft_reset;
3320                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3321                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3322                 }
3323
3324                 /* Wait a little for things to settle down */
3325                 udelay(50);
3326         }
3327         return 0;
3328 }
3329
3330 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3331 {
3332         uint64_t clock;
3333
3334         mutex_lock(&adev->gfx.gpu_clock_mutex);
3335         WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3336         clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
3337                 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3338         mutex_unlock(&adev->gfx.gpu_clock_mutex);
3339         return clock;
3340 }
3341
3342 static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3343                                           uint32_t vmid,
3344                                           uint32_t gds_base, uint32_t gds_size,
3345                                           uint32_t gws_base, uint32_t gws_size,
3346                                           uint32_t oa_base, uint32_t oa_size)
3347 {
3348         struct amdgpu_device *adev = ring->adev;
3349
3350         gds_base = gds_base >> AMDGPU_GDS_SHIFT;
3351         gds_size = gds_size >> AMDGPU_GDS_SHIFT;
3352
3353         gws_base = gws_base >> AMDGPU_GWS_SHIFT;
3354         gws_size = gws_size >> AMDGPU_GWS_SHIFT;
3355
3356         oa_base = oa_base >> AMDGPU_OA_SHIFT;
3357         oa_size = oa_size >> AMDGPU_OA_SHIFT;
3358
3359         /* GDS Base */
3360         gfx_v9_0_write_data_to_reg(ring, 0, false,
3361                                    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
3362                                    gds_base);
3363
3364         /* GDS Size */
3365         gfx_v9_0_write_data_to_reg(ring, 0, false,
3366                                    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
3367                                    gds_size);
3368
3369         /* GWS */
3370         gfx_v9_0_write_data_to_reg(ring, 0, false,
3371                                    SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
3372                                    gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
3373
3374         /* OA */
3375         gfx_v9_0_write_data_to_reg(ring, 0, false,
3376                                    SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
3377                                    (1 << (oa_size + oa_base)) - (1 << oa_base));
3378 }
3379
3380 static int gfx_v9_0_early_init(void *handle)
3381 {
3382         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3383
3384         adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
3385         adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
3386         gfx_v9_0_set_ring_funcs(adev);
3387         gfx_v9_0_set_irq_funcs(adev);
3388         gfx_v9_0_set_gds_init(adev);
3389         gfx_v9_0_set_rlc_funcs(adev);
3390
3391         return 0;
3392 }
3393
3394 static int gfx_v9_0_late_init(void *handle)
3395 {
3396         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3397         int r;
3398
3399         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
3400         if (r)
3401                 return r;
3402
3403         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
3404         if (r)
3405                 return r;
3406
3407         r = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_GFX,
3408                                                    AMD_PG_STATE_GATE);
3409         if (r)
3410                 return r;
3411
3412         return 0;
3413 }
3414
3415 static void gfx_v9_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
3416 {
3417         uint32_t rlc_setting, data;
3418         unsigned i;
3419
3420         if (adev->gfx.rlc.in_safe_mode)
3421                 return;
3422
3423         /* if RLC is not enabled, do nothing */
3424         rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
3425         if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3426                 return;
3427
3428         if (adev->cg_flags &
3429             (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG |
3430              AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3431                 data = RLC_SAFE_MODE__CMD_MASK;
3432                 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
3433                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
3434
3435                 /* wait for RLC_SAFE_MODE */
3436                 for (i = 0; i < adev->usec_timeout; i++) {
3437                         if (!REG_GET_FIELD(SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
3438                                 break;
3439                         udelay(1);
3440                 }
3441                 adev->gfx.rlc.in_safe_mode = true;
3442         }
3443 }
3444
3445 static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
3446 {
3447         uint32_t rlc_setting, data;
3448
3449         if (!adev->gfx.rlc.in_safe_mode)
3450                 return;
3451
3452         /* if RLC is not enabled, do nothing */
3453         rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
3454         if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3455                 return;
3456
3457         if (adev->cg_flags &
3458             (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) {
3459                 /*
3460                  * Try to exit safe mode only if it is already in safe
3461                  * mode.
3462                  */
3463                 data = RLC_SAFE_MODE__CMD_MASK;
3464                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
3465                 adev->gfx.rlc.in_safe_mode = false;
3466         }
3467 }
3468
3469 static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
3470                                                 bool enable)
3471 {
3472         gfx_v9_0_enter_rlc_safe_mode(adev);
3473
3474         if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
3475                 gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
3476                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
3477                         gfx_v9_0_enable_gfx_pipeline_powergating(adev, true);
3478         } else {
3479                 gfx_v9_0_enable_gfx_cg_power_gating(adev, false);
3480                 gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);
3481         }
3482
3483         gfx_v9_0_exit_rlc_safe_mode(adev);
3484 }
3485
3486 static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev,
3487                                                 bool enable)
3488 {
3489         /* TODO: double check if we need to perform under safe mode */
3490         /* gfx_v9_0_enter_rlc_safe_mode(adev); */
3491
3492         if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
3493                 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true);
3494         else
3495                 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false);
3496
3497         if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
3498                 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true);
3499         else
3500                 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false);
3501
3502         /* gfx_v9_0_exit_rlc_safe_mode(adev); */
3503 }
3504
3505 static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
3506                                                       bool enable)
3507 {
3508         uint32_t data, def;
3509
3510         /* It is disabled by HW by default */
3511         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3512                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
3513                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3514                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
3515                           RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3516                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3517                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3518
3519                 /* only for Vega10 & Raven1 */
3520                 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
3521
3522                 if (def != data)
3523                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3524
3525                 /* MGLS is a global flag to control all MGLS in GFX */
3526                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3527                         /* 2 - RLC memory Light sleep */
3528                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
3529                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
3530                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3531                                 if (def != data)
3532                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
3533                         }
3534                         /* 3 - CP memory Light sleep */
3535                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
3536                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
3537                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3538                                 if (def != data)
3539                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
3540                         }
3541                 }
3542         } else {
3543                 /* 1 - MGCG_OVERRIDE */
3544                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3545                 data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
3546                          RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
3547                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3548                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3549                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3550                 if (def != data)
3551                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3552
3553                 /* 2 - disable MGLS in RLC */
3554                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
3555                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3556                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3557                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
3558                 }
3559
3560                 /* 3 - disable MGLS in CP */
3561                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
3562                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3563                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3564                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
3565                 }
3566         }
3567 }
3568
3569 static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
3570                                            bool enable)
3571 {
3572         uint32_t data, def;
3573
3574         adev->gfx.rlc.funcs->enter_safe_mode(adev);
3575
3576         /* Enable 3D CGCG/CGLS */
3577         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3578                 /* write cmd to clear cgcg/cgls ov */
3579                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3580                 /* unset CGCG override */
3581                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
3582                 /* update CGCG and CGLS override bits */
3583                 if (def != data)
3584                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3585                 /* enable 3Dcgcg FSM(0x0020003f) */
3586                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
3587                 data = (0x2000 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3588                         RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
3589                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
3590                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3591                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
3592                 if (def != data)
3593                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
3594
3595                 /* set IDLE_POLL_COUNT(0x00900100) */
3596                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
3597                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3598                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3599                 if (def != data)
3600                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
3601         } else {
3602                 /* Disable CGCG/CGLS */
3603                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
3604                 /* disable cgcg, cgls should be disabled */
3605                 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
3606                           RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
3607                 /* disable cgcg and cgls in FSM */
3608                 if (def != data)
3609                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
3610         }
3611
3612         adev->gfx.rlc.funcs->exit_safe_mode(adev);
3613 }
3614
3615 static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
3616                                                       bool enable)
3617 {
3618         uint32_t def, data;
3619
3620         adev->gfx.rlc.funcs->enter_safe_mode(adev);
3621
3622         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
3623                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3624                 /* unset CGCG override */
3625                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
3626                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3627                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3628                 else
3629                         data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3630                 /* update CGCG and CGLS override bits */
3631                 if (def != data)
3632                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3633
3634                 /* enable cgcg FSM(0x0020003F) */
3635                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
3636                 data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3637                         RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
3638                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3639                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3640                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3641                 if (def != data)
3642                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
3643
3644                 /* set IDLE_POLL_COUNT(0x00900100) */
3645                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
3646                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3647                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3648                 if (def != data)
3649                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
3650         } else {
3651                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
3652                 /* reset CGCG/CGLS bits */
3653                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3654                 /* disable cgcg and cgls in FSM */
3655                 if (def != data)
3656                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
3657         }
3658
3659         adev->gfx.rlc.funcs->exit_safe_mode(adev);
3660 }
3661
3662 static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
3663                                             bool enable)
3664 {
3665         if (enable) {
3666                 /* CGCG/CGLS should be enabled after MGCG/MGLS
3667                  * ===  MGCG + MGLS ===
3668                  */
3669                 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3670                 /* ===  CGCG /CGLS for GFX 3D Only === */
3671                 gfx_v9_0_update_3d_clock_gating(adev, enable);
3672                 /* ===  CGCG + CGLS === */
3673                 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3674         } else {
3675                 /* CGCG/CGLS should be disabled before MGCG/MGLS
3676                  * ===  CGCG + CGLS ===
3677                  */
3678                 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3679                 /* ===  CGCG /CGLS for GFX 3D Only === */
3680                 gfx_v9_0_update_3d_clock_gating(adev, enable);
3681                 /* ===  MGCG + MGLS === */
3682                 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3683         }
3684         return 0;
3685 }
3686
3687 static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
3688         .enter_safe_mode = gfx_v9_0_enter_rlc_safe_mode,
3689         .exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode
3690 };
3691
3692 static int gfx_v9_0_set_powergating_state(void *handle,
3693                                           enum amd_powergating_state state)
3694 {
3695         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3696         bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
3697
3698         switch (adev->asic_type) {
3699         case CHIP_RAVEN:
3700                 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
3701                         gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
3702                         gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
3703                 } else {
3704                         gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
3705                         gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
3706                 }
3707
3708                 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
3709                         gfx_v9_0_enable_cp_power_gating(adev, true);
3710                 else
3711                         gfx_v9_0_enable_cp_power_gating(adev, false);
3712
3713                 /* update gfx cgpg state */
3714                 gfx_v9_0_update_gfx_cg_power_gating(adev, enable);
3715
3716                 /* update mgcg state */
3717                 gfx_v9_0_update_gfx_mg_power_gating(adev, enable);
3718                 break;
3719         default:
3720                 break;
3721         }
3722
3723         return 0;
3724 }
3725
3726 static int gfx_v9_0_set_clockgating_state(void *handle,
3727                                           enum amd_clockgating_state state)
3728 {
3729         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3730
3731         if (amdgpu_sriov_vf(adev))
3732                 return 0;
3733
3734         switch (adev->asic_type) {
3735         case CHIP_VEGA10:
3736         case CHIP_VEGA12:
3737         case CHIP_VEGA20:
3738         case CHIP_RAVEN:
3739                 gfx_v9_0_update_gfx_clock_gating(adev,
3740                                                  state == AMD_CG_STATE_GATE ? true : false);
3741                 break;
3742         default:
3743                 break;
3744         }
3745         return 0;
3746 }
3747
3748 static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
3749 {
3750         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3751         int data;
3752
3753         if (amdgpu_sriov_vf(adev))
3754                 *flags = 0;
3755
3756         /* AMD_CG_SUPPORT_GFX_MGCG */
3757         data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3758         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
3759                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
3760
3761         /* AMD_CG_SUPPORT_GFX_CGCG */
3762         data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
3763         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
3764                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
3765
3766         /* AMD_CG_SUPPORT_GFX_CGLS */
3767         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
3768                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
3769
3770         /* AMD_CG_SUPPORT_GFX_RLC_LS */
3771         data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
3772         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
3773                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
3774
3775         /* AMD_CG_SUPPORT_GFX_CP_LS */
3776         data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
3777         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
3778                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
3779
3780         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
3781         data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
3782         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
3783                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
3784
3785         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
3786         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
3787                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
3788 }
3789
3790 static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
3791 {
3792         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/
3793 }
3794
3795 static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
3796 {
3797         struct amdgpu_device *adev = ring->adev;
3798         u64 wptr;
3799
3800         /* XXX check if swapping is necessary on BE */
3801         if (ring->use_doorbell) {
3802                 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
3803         } else {
3804                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
3805                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
3806         }
3807
3808         return wptr;
3809 }
3810
3811 static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
3812 {
3813         struct amdgpu_device *adev = ring->adev;
3814
3815         if (ring->use_doorbell) {
3816                 /* XXX check if swapping is necessary on BE */
3817                 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
3818                 WDOORBELL64(ring->doorbell_index, ring->wptr);
3819         } else {
3820                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
3821                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
3822         }
3823 }
3824
3825 static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
3826 {
3827         struct amdgpu_device *adev = ring->adev;
3828         u32 ref_and_mask, reg_mem_engine;
3829         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;
3830
3831         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
3832                 switch (ring->me) {
3833                 case 1:
3834                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
3835                         break;
3836                 case 2:
3837                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
3838                         break;
3839                 default:
3840                         return;
3841                 }
3842                 reg_mem_engine = 0;
3843         } else {
3844                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
3845                 reg_mem_engine = 1; /* pfp */
3846         }
3847
3848         gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
3849                               adev->nbio_funcs->get_hdp_flush_req_offset(adev),
3850                               adev->nbio_funcs->get_hdp_flush_done_offset(adev),
3851                               ref_and_mask, ref_and_mask, 0x20);
3852 }
3853
3854 static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
3855                                       struct amdgpu_ib *ib,
3856                                       unsigned vmid, bool ctx_switch)
3857 {
3858         u32 header, control = 0;
3859
3860         if (ib->flags & AMDGPU_IB_FLAG_CE)
3861                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3862         else
3863                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3864
3865         control |= ib->length_dw | (vmid << 24);
3866
3867         if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
3868                 control |= INDIRECT_BUFFER_PRE_ENB(1);
3869
3870                 if (!(ib->flags & AMDGPU_IB_FLAG_CE))
3871                         gfx_v9_0_ring_emit_de_meta(ring);
3872         }
3873
3874         amdgpu_ring_write(ring, header);
3875         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3876         amdgpu_ring_write(ring,
3877 #ifdef __BIG_ENDIAN
3878                 (2 << 0) |
3879 #endif
3880                 lower_32_bits(ib->gpu_addr));
3881         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
3882         amdgpu_ring_write(ring, control);
3883 }
3884
3885 static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
3886                                           struct amdgpu_ib *ib,
3887                                           unsigned vmid, bool ctx_switch)
3888 {
3889         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
3890
3891         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3892         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3893         amdgpu_ring_write(ring,
3894 #ifdef __BIG_ENDIAN
3895                                 (2 << 0) |
3896 #endif
3897                                 lower_32_bits(ib->gpu_addr));
3898         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
3899         amdgpu_ring_write(ring, control);
3900 }
3901
3902 static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
3903                                      u64 seq, unsigned flags)
3904 {
3905         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
3906         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
3907         bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY;
3908
3909         /* RELEASE_MEM - flush caches, send int */
3910         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
3911         amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN |
3912                                                EOP_TC_NC_ACTION_EN) :
3913                                               (EOP_TCL1_ACTION_EN |
3914                                                EOP_TC_ACTION_EN |
3915                                                EOP_TC_WB_ACTION_EN |
3916                                                EOP_TC_MD_ACTION_EN)) |
3917                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3918                                  EVENT_INDEX(5)));
3919         amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
3920
3921         /*
3922          * the address should be Qword aligned if 64bit write, Dword
3923          * aligned if only send 32bit data low (discard data high)
3924          */
3925         if (write64bit)
3926                 BUG_ON(addr & 0x7);
3927         else
3928                 BUG_ON(addr & 0x3);
3929         amdgpu_ring_write(ring, lower_32_bits(addr));
3930         amdgpu_ring_write(ring, upper_32_bits(addr));
3931         amdgpu_ring_write(ring, lower_32_bits(seq));
3932         amdgpu_ring_write(ring, upper_32_bits(seq));
3933         amdgpu_ring_write(ring, 0);
3934 }
3935
3936 static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
3937 {
3938         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3939         uint32_t seq = ring->fence_drv.sync_seq;
3940         uint64_t addr = ring->fence_drv.gpu_addr;
3941
3942         gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0,
3943                               lower_32_bits(addr), upper_32_bits(addr),
3944                               seq, 0xffffffff, 4);
3945 }
3946
3947 static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3948                                         unsigned vmid, uint64_t pd_addr)
3949 {
3950         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
3951
3952         /* compute doesn't have PFP */
3953         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
3954                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3955                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3956                 amdgpu_ring_write(ring, 0x0);
3957         }
3958 }
3959
3960 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
3961 {
3962         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */
3963 }
3964
3965 static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
3966 {
3967         u64 wptr;
3968
3969         /* XXX check if swapping is necessary on BE */
3970         if (ring->use_doorbell)
3971                 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
3972         else
3973                 BUG();
3974         return wptr;
3975 }
3976
3977 static void gfx_v9_0_ring_set_pipe_percent(struct amdgpu_ring *ring,
3978                                            bool acquire)
3979 {
3980         struct amdgpu_device *adev = ring->adev;
3981         int pipe_num, tmp, reg;
3982         int pipe_percent = acquire ? SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK : 0x1;
3983
3984         pipe_num = ring->me * adev->gfx.mec.num_pipe_per_mec + ring->pipe;
3985
3986         /* first me only has 2 entries, GFX and HP3D */
3987         if (ring->me > 0)
3988                 pipe_num -= 2;
3989
3990         reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_GFX) + pipe_num;
3991         tmp = RREG32(reg);
3992         tmp = REG_SET_FIELD(tmp, SPI_WCL_PIPE_PERCENT_GFX, VALUE, pipe_percent);
3993         WREG32(reg, tmp);
3994 }
3995
3996 static void gfx_v9_0_pipe_reserve_resources(struct amdgpu_device *adev,
3997                                             struct amdgpu_ring *ring,
3998                                             bool acquire)
3999 {
4000         int i, pipe;
4001         bool reserve;
4002         struct amdgpu_ring *iring;
4003
4004         mutex_lock(&adev->gfx.pipe_reserve_mutex);
4005         pipe = amdgpu_gfx_queue_to_bit(adev, ring->me, ring->pipe, 0);
4006         if (acquire)
4007                 set_bit(pipe, adev->gfx.pipe_reserve_bitmap);
4008         else
4009                 clear_bit(pipe, adev->gfx.pipe_reserve_bitmap);
4010
4011         if (!bitmap_weight(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES)) {
4012                 /* Clear all reservations - everyone reacquires all resources */
4013                 for (i = 0; i < adev->gfx.num_gfx_rings; ++i)
4014                         gfx_v9_0_ring_set_pipe_percent(&adev->gfx.gfx_ring[i],
4015                                                        true);
4016
4017                 for (i = 0; i < adev->gfx.num_compute_rings; ++i)
4018                         gfx_v9_0_ring_set_pipe_percent(&adev->gfx.compute_ring[i],
4019                                                        true);
4020         } else {
4021                 /* Lower all pipes without a current reservation */
4022                 for (i = 0; i < adev->gfx.num_gfx_rings; ++i) {
4023                         iring = &adev->gfx.gfx_ring[i];
4024                         pipe = amdgpu_gfx_queue_to_bit(adev,
4025                                                        iring->me,
4026                                                        iring->pipe,
4027                                                        0);
4028                         reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap);
4029                         gfx_v9_0_ring_set_pipe_percent(iring, reserve);
4030                 }
4031
4032                 for (i = 0; i < adev->gfx.num_compute_rings; ++i) {
4033                         iring = &adev->gfx.compute_ring[i];
4034                         pipe = amdgpu_gfx_queue_to_bit(adev,
4035                                                        iring->me,
4036                                                        iring->pipe,
4037                                                        0);
4038                         reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap);
4039                         gfx_v9_0_ring_set_pipe_percent(iring, reserve);
4040                 }
4041         }
4042
4043         mutex_unlock(&adev->gfx.pipe_reserve_mutex);
4044 }
4045
4046 static void gfx_v9_0_hqd_set_priority(struct amdgpu_device *adev,
4047                                       struct amdgpu_ring *ring,
4048                                       bool acquire)
4049 {
4050         uint32_t pipe_priority = acquire ? 0x2 : 0x0;
4051         uint32_t queue_priority = acquire ? 0xf : 0x0;
4052
4053         mutex_lock(&adev->srbm_mutex);
4054         soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4055
4056         WREG32_SOC15(GC, 0, mmCP_HQD_PIPE_PRIORITY, pipe_priority);
4057         WREG32_SOC15(GC, 0, mmCP_HQD_QUEUE_PRIORITY, queue_priority);
4058
4059         soc15_grbm_select(adev, 0, 0, 0, 0);
4060         mutex_unlock(&adev->srbm_mutex);
4061 }
4062
4063 static void gfx_v9_0_ring_set_priority_compute(struct amdgpu_ring *ring,
4064                                                enum drm_sched_priority priority)
4065 {
4066         struct amdgpu_device *adev = ring->adev;
4067         bool acquire = priority == DRM_SCHED_PRIORITY_HIGH_HW;
4068
4069         if (ring->funcs->type != AMDGPU_RING_TYPE_COMPUTE)
4070                 return;
4071
4072         gfx_v9_0_hqd_set_priority(adev, ring, acquire);
4073         gfx_v9_0_pipe_reserve_resources(adev, ring, acquire);
4074 }
4075
4076 static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
4077 {
4078         struct amdgpu_device *adev = ring->adev;
4079
4080         /* XXX check if swapping is necessary on BE */
4081         if (ring->use_doorbell) {
4082                 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
4083                 WDOORBELL64(ring->doorbell_index, ring->wptr);
4084         } else{
4085                 BUG(); /* only DOORBELL method supported on gfx9 now */
4086         }
4087 }
4088
4089 static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
4090                                          u64 seq, unsigned int flags)
4091 {
4092         struct amdgpu_device *adev = ring->adev;
4093
4094         /* we only allocate 32bit for each seq wb address */
4095         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
4096
4097         /* write fence seq to the "addr" */
4098         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4099         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4100                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
4101         amdgpu_ring_write(ring, lower_32_bits(addr));
4102         amdgpu_ring_write(ring, upper_32_bits(addr));
4103         amdgpu_ring_write(ring, lower_32_bits(seq));
4104
4105         if (flags & AMDGPU_FENCE_FLAG_INT) {
4106                 /* set register to trigger INT */
4107                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4108                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4109                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
4110                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
4111                 amdgpu_ring_write(ring, 0);
4112                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
4113         }
4114 }
4115
4116 static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring)
4117 {
4118         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4119         amdgpu_ring_write(ring, 0);
4120 }
4121
4122 static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
4123 {
4124         struct v9_ce_ib_state ce_payload = {0};
4125         uint64_t csa_addr;
4126         int cnt;
4127
4128         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
4129         csa_addr = amdgpu_csa_vaddr(ring->adev);
4130
4131         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
4132         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
4133                                  WRITE_DATA_DST_SEL(8) |
4134                                  WR_CONFIRM) |
4135                                  WRITE_DATA_CACHE_POLICY(0));
4136         amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
4137         amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
4138         amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2);
4139 }
4140
4141 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring)
4142 {
4143         struct v9_de_ib_state de_payload = {0};
4144         uint64_t csa_addr, gds_addr;
4145         int cnt;
4146
4147         csa_addr = amdgpu_csa_vaddr(ring->adev);
4148         gds_addr = csa_addr + 4096;
4149         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
4150         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
4151
4152         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
4153         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
4154         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
4155                                  WRITE_DATA_DST_SEL(8) |
4156                                  WR_CONFIRM) |
4157                                  WRITE_DATA_CACHE_POLICY(0));
4158         amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
4159         amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
4160         amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2);
4161 }
4162
4163 static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
4164 {
4165         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
4166         amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
4167 }
4168
4169 static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
4170 {
4171         uint32_t dw2 = 0;
4172
4173         if (amdgpu_sriov_vf(ring->adev))
4174                 gfx_v9_0_ring_emit_ce_meta(ring);
4175
4176         gfx_v9_0_ring_emit_tmz(ring, true);
4177
4178         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
4179         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
4180                 /* set load_global_config & load_global_uconfig */
4181                 dw2 |= 0x8001;
4182                 /* set load_cs_sh_regs */
4183                 dw2 |= 0x01000000;
4184                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
4185                 dw2 |= 0x10002;
4186
4187                 /* set load_ce_ram if preamble presented */
4188                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
4189                         dw2 |= 0x10000000;
4190         } else {
4191                 /* still load_ce_ram if this is the first time preamble presented
4192                  * although there is no context switch happens.
4193                  */
4194                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
4195                         dw2 |= 0x10000000;
4196         }
4197
4198         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4199         amdgpu_ring_write(ring, dw2);
4200         amdgpu_ring_write(ring, 0);
4201 }
4202
4203 static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
4204 {
4205         unsigned ret;
4206         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
4207         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
4208         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
4209         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
4210         ret = ring->wptr & ring->buf_mask;
4211         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
4212         return ret;
4213 }
4214
4215 static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
4216 {
4217         unsigned cur;
4218         BUG_ON(offset > ring->buf_mask);
4219         BUG_ON(ring->ring[offset] != 0x55aa55aa);
4220
4221         cur = (ring->wptr & ring->buf_mask) - 1;
4222         if (likely(cur > offset))
4223                 ring->ring[offset] = cur - offset;
4224         else
4225                 ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
4226 }
4227
4228 static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
4229 {
4230         struct amdgpu_device *adev = ring->adev;
4231
4232         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
4233         amdgpu_ring_write(ring, 0 |     /* src: register*/
4234                                 (5 << 8) |      /* dst: memory */
4235                                 (1 << 20));     /* write confirm */
4236         amdgpu_ring_write(ring, reg);
4237         amdgpu_ring_write(ring, 0);
4238         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
4239                                 adev->virt.reg_val_offs * 4));
4240         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
4241                                 adev->virt.reg_val_offs * 4));
4242 }
4243
4244 static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
4245                                     uint32_t val)
4246 {
4247         uint32_t cmd = 0;
4248
4249         switch (ring->funcs->type) {
4250         case AMDGPU_RING_TYPE_GFX:
4251                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
4252                 break;
4253         case AMDGPU_RING_TYPE_KIQ:
4254                 cmd = (1 << 16); /* no inc addr */
4255                 break;
4256         default:
4257                 cmd = WR_CONFIRM;
4258                 break;
4259         }
4260         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4261         amdgpu_ring_write(ring, cmd);
4262         amdgpu_ring_write(ring, reg);
4263         amdgpu_ring_write(ring, 0);
4264         amdgpu_ring_write(ring, val);
4265 }
4266
4267 static void gfx_v9_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
4268                                         uint32_t val, uint32_t mask)
4269 {
4270         gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
4271 }
4272
4273 static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
4274                                                   uint32_t reg0, uint32_t reg1,
4275                                                   uint32_t ref, uint32_t mask)
4276 {
4277         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
4278
4279         if (amdgpu_sriov_vf(ring->adev))
4280                 gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
4281                                       ref, mask, 0x20);
4282         else
4283                 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
4284                                                            ref, mask);
4285 }
4286
4287 static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4288                                                  enum amdgpu_interrupt_state state)
4289 {
4290         switch (state) {
4291         case AMDGPU_IRQ_STATE_DISABLE:
4292         case AMDGPU_IRQ_STATE_ENABLE:
4293                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4294                                TIME_STAMP_INT_ENABLE,
4295                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4296                 break;
4297         default:
4298                 break;
4299         }
4300 }
4301
4302 static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4303                                                      int me, int pipe,
4304                                                      enum amdgpu_interrupt_state state)
4305 {
4306         u32 mec_int_cntl, mec_int_cntl_reg;
4307
4308         /*
4309          * amdgpu controls only the first MEC. That's why this function only
4310          * handles the setting of interrupts for this specific MEC. All other
4311          * pipes' interrupts are set by amdkfd.
4312          */
4313
4314         if (me == 1) {
4315                 switch (pipe) {
4316                 case 0:
4317                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
4318                         break;
4319                 case 1:
4320                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
4321                         break;
4322                 case 2:
4323                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
4324                         break;
4325                 case 3:
4326                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
4327                         break;
4328                 default:
4329                         DRM_DEBUG("invalid pipe %d\n", pipe);
4330                         return;
4331                 }
4332         } else {
4333                 DRM_DEBUG("invalid me %d\n", me);
4334                 return;
4335         }
4336
4337         switch (state) {
4338         case AMDGPU_IRQ_STATE_DISABLE:
4339                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4340                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4341                                              TIME_STAMP_INT_ENABLE, 0);
4342                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4343                 break;
4344         case AMDGPU_IRQ_STATE_ENABLE:
4345                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4346                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4347                                              TIME_STAMP_INT_ENABLE, 1);
4348                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4349                 break;
4350         default:
4351                 break;
4352         }
4353 }
4354
4355 static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4356                                              struct amdgpu_irq_src *source,
4357                                              unsigned type,
4358                                              enum amdgpu_interrupt_state state)
4359 {
4360         switch (state) {
4361         case AMDGPU_IRQ_STATE_DISABLE:
4362         case AMDGPU_IRQ_STATE_ENABLE:
4363                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4364                                PRIV_REG_INT_ENABLE,
4365                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4366                 break;
4367         default:
4368                 break;
4369         }
4370
4371         return 0;
4372 }
4373
4374 static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4375                                               struct amdgpu_irq_src *source,
4376                                               unsigned type,
4377                                               enum amdgpu_interrupt_state state)
4378 {
4379         switch (state) {
4380         case AMDGPU_IRQ_STATE_DISABLE:
4381         case AMDGPU_IRQ_STATE_ENABLE:
4382                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4383                                PRIV_INSTR_INT_ENABLE,
4384                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4385         default:
4386                 break;
4387         }
4388
4389         return 0;
4390 }
4391
4392 static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4393                                             struct amdgpu_irq_src *src,
4394                                             unsigned type,
4395                                             enum amdgpu_interrupt_state state)
4396 {
4397         switch (type) {
4398         case AMDGPU_CP_IRQ_GFX_EOP:
4399                 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
4400                 break;
4401         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4402                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4403                 break;
4404         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4405                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4406                 break;
4407         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4408                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4409                 break;
4410         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4411                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4412                 break;
4413         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4414                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4415                 break;
4416         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4417                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4418                 break;
4419         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4420                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4421                 break;
4422         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4423                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4424                 break;
4425         default:
4426                 break;
4427         }
4428         return 0;
4429 }
4430
4431 static int gfx_v9_0_eop_irq(struct amdgpu_device *adev,
4432                             struct amdgpu_irq_src *source,
4433                             struct amdgpu_iv_entry *entry)
4434 {
4435         int i;
4436         u8 me_id, pipe_id, queue_id;
4437         struct amdgpu_ring *ring;
4438
4439         DRM_DEBUG("IH: CP EOP\n");
4440         me_id = (entry->ring_id & 0x0c) >> 2;
4441         pipe_id = (entry->ring_id & 0x03) >> 0;
4442         queue_id = (entry->ring_id & 0x70) >> 4;
4443
4444         switch (me_id) {
4445         case 0:
4446                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4447                 break;
4448         case 1:
4449         case 2:
4450                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4451                         ring = &adev->gfx.compute_ring[i];
4452                         /* Per-queue interrupt is supported for MEC starting from VI.
4453                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
4454                           */
4455                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4456                                 amdgpu_fence_process(ring);
4457                 }
4458                 break;
4459         }
4460         return 0;
4461 }
4462
4463 static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev,
4464                                  struct amdgpu_irq_src *source,
4465                                  struct amdgpu_iv_entry *entry)
4466 {
4467         DRM_ERROR("Illegal register access in command stream\n");
4468         schedule_work(&adev->reset_work);
4469         return 0;
4470 }
4471
4472 static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
4473                                   struct amdgpu_irq_src *source,
4474                                   struct amdgpu_iv_entry *entry)
4475 {
4476         DRM_ERROR("Illegal instruction in command stream\n");
4477         schedule_work(&adev->reset_work);
4478         return 0;
4479 }
4480
4481 static int gfx_v9_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
4482                                             struct amdgpu_irq_src *src,
4483                                             unsigned int type,
4484                                             enum amdgpu_interrupt_state state)
4485 {
4486         uint32_t tmp, target;
4487         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
4488
4489         if (ring->me == 1)
4490                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
4491         else
4492                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
4493         target += ring->pipe;
4494
4495         switch (type) {
4496         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
4497                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
4498                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
4499                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
4500                                                  GENERIC2_INT_ENABLE, 0);
4501                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
4502
4503                         tmp = RREG32(target);
4504                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
4505                                                  GENERIC2_INT_ENABLE, 0);
4506                         WREG32(target, tmp);
4507                 } else {
4508                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
4509                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
4510                                                  GENERIC2_INT_ENABLE, 1);
4511                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
4512
4513                         tmp = RREG32(target);
4514                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
4515                                                  GENERIC2_INT_ENABLE, 1);
4516                         WREG32(target, tmp);
4517                 }
4518                 break;
4519         default:
4520                 BUG(); /* kiq only support GENERIC2_INT now */
4521                 break;
4522         }
4523         return 0;
4524 }
4525
4526 static int gfx_v9_0_kiq_irq(struct amdgpu_device *adev,
4527                             struct amdgpu_irq_src *source,
4528                             struct amdgpu_iv_entry *entry)
4529 {
4530         u8 me_id, pipe_id, queue_id;
4531         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
4532
4533         me_id = (entry->ring_id & 0x0c) >> 2;
4534         pipe_id = (entry->ring_id & 0x03) >> 0;
4535         queue_id = (entry->ring_id & 0x70) >> 4;
4536         DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
4537                    me_id, pipe_id, queue_id);
4538
4539         amdgpu_fence_process(ring);
4540         return 0;
4541 }
4542
4543 static const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
4544         .name = "gfx_v9_0",
4545         .early_init = gfx_v9_0_early_init,
4546         .late_init = gfx_v9_0_late_init,
4547         .sw_init = gfx_v9_0_sw_init,
4548         .sw_fini = gfx_v9_0_sw_fini,
4549         .hw_init = gfx_v9_0_hw_init,
4550         .hw_fini = gfx_v9_0_hw_fini,
4551         .suspend = gfx_v9_0_suspend,
4552         .resume = gfx_v9_0_resume,
4553         .is_idle = gfx_v9_0_is_idle,
4554         .wait_for_idle = gfx_v9_0_wait_for_idle,
4555         .soft_reset = gfx_v9_0_soft_reset,
4556         .set_clockgating_state = gfx_v9_0_set_clockgating_state,
4557         .set_powergating_state = gfx_v9_0_set_powergating_state,
4558         .get_clockgating_state = gfx_v9_0_get_clockgating_state,
4559 };
4560
4561 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
4562         .type = AMDGPU_RING_TYPE_GFX,
4563         .align_mask = 0xff,
4564         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4565         .support_64bit_ptrs = true,
4566         .vmhub = AMDGPU_GFXHUB,
4567         .get_rptr = gfx_v9_0_ring_get_rptr_gfx,
4568         .get_wptr = gfx_v9_0_ring_get_wptr_gfx,
4569         .set_wptr = gfx_v9_0_ring_set_wptr_gfx,
4570         .emit_frame_size = /* totally 242 maximum if 16 IBs */
4571                 5 +  /* COND_EXEC */
4572                 7 +  /* PIPELINE_SYNC */
4573                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
4574                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
4575                 2 + /* VM_FLUSH */
4576                 8 +  /* FENCE for VM_FLUSH */
4577                 20 + /* GDS switch */
4578                 4 + /* double SWITCH_BUFFER,
4579                        the first COND_EXEC jump to the place just
4580                            prior to this double SWITCH_BUFFER  */
4581                 5 + /* COND_EXEC */
4582                 7 +      /*     HDP_flush */
4583                 4 +      /*     VGT_flush */
4584                 14 + /* CE_META */
4585                 31 + /* DE_META */
4586                 3 + /* CNTX_CTRL */
4587                 5 + /* HDP_INVL */
4588                 8 + 8 + /* FENCE x2 */
4589                 2, /* SWITCH_BUFFER */
4590         .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */
4591         .emit_ib = gfx_v9_0_ring_emit_ib_gfx,
4592         .emit_fence = gfx_v9_0_ring_emit_fence,
4593         .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4594         .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4595         .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4596         .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4597         .test_ring = gfx_v9_0_ring_test_ring,
4598         .test_ib = gfx_v9_0_ring_test_ib,
4599         .insert_nop = amdgpu_ring_insert_nop,
4600         .pad_ib = amdgpu_ring_generic_pad_ib,
4601         .emit_switch_buffer = gfx_v9_ring_emit_sb,
4602         .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,
4603         .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec,
4604         .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec,
4605         .emit_tmz = gfx_v9_0_ring_emit_tmz,
4606         .emit_wreg = gfx_v9_0_ring_emit_wreg,
4607         .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
4608         .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
4609 };
4610
4611 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
4612         .type = AMDGPU_RING_TYPE_COMPUTE,
4613         .align_mask = 0xff,
4614         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4615         .support_64bit_ptrs = true,
4616         .vmhub = AMDGPU_GFXHUB,
4617         .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4618         .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4619         .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4620         .emit_frame_size =
4621                 20 + /* gfx_v9_0_ring_emit_gds_switch */
4622                 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4623                 5 + /* hdp invalidate */
4624                 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
4625                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
4626                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
4627                 2 + /* gfx_v9_0_ring_emit_vm_flush */
4628                 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
4629         .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4630         .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4631         .emit_fence = gfx_v9_0_ring_emit_fence,
4632         .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4633         .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4634         .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4635         .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4636         .test_ring = gfx_v9_0_ring_test_ring,
4637         .test_ib = gfx_v9_0_ring_test_ib,
4638         .insert_nop = amdgpu_ring_insert_nop,
4639         .pad_ib = amdgpu_ring_generic_pad_ib,
4640         .set_priority = gfx_v9_0_ring_set_priority_compute,
4641         .emit_wreg = gfx_v9_0_ring_emit_wreg,
4642         .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
4643         .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
4644 };
4645
4646 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
4647         .type = AMDGPU_RING_TYPE_KIQ,
4648         .align_mask = 0xff,
4649         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4650         .support_64bit_ptrs = true,
4651         .vmhub = AMDGPU_GFXHUB,
4652         .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4653         .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4654         .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4655         .emit_frame_size =
4656                 20 + /* gfx_v9_0_ring_emit_gds_switch */
4657                 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4658                 5 + /* hdp invalidate */
4659                 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
4660                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
4661                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
4662                 2 + /* gfx_v9_0_ring_emit_vm_flush */
4663                 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */
4664         .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4665         .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4666         .emit_fence = gfx_v9_0_ring_emit_fence_kiq,
4667         .test_ring = gfx_v9_0_ring_test_ring,
4668         .test_ib = gfx_v9_0_ring_test_ib,
4669         .insert_nop = amdgpu_ring_insert_nop,
4670         .pad_ib = amdgpu_ring_generic_pad_ib,
4671         .emit_rreg = gfx_v9_0_ring_emit_rreg,
4672         .emit_wreg = gfx_v9_0_ring_emit_wreg,
4673         .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
4674         .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
4675 };
4676
4677 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)
4678 {
4679         int i;
4680
4681         adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq;
4682
4683         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4684                 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx;
4685
4686         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4687                 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute;
4688 }
4689
4690 static const struct amdgpu_irq_src_funcs gfx_v9_0_kiq_irq_funcs = {
4691         .set = gfx_v9_0_kiq_set_interrupt_state,
4692         .process = gfx_v9_0_kiq_irq,
4693 };
4694
4695 static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = {
4696         .set = gfx_v9_0_set_eop_interrupt_state,
4697         .process = gfx_v9_0_eop_irq,
4698 };
4699
4700 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = {
4701         .set = gfx_v9_0_set_priv_reg_fault_state,
4702         .process = gfx_v9_0_priv_reg_irq,
4703 };
4704
4705 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = {
4706         .set = gfx_v9_0_set_priv_inst_fault_state,
4707         .process = gfx_v9_0_priv_inst_irq,
4708 };
4709
4710 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)
4711 {
4712         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4713         adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs;
4714
4715         adev->gfx.priv_reg_irq.num_types = 1;
4716         adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs;
4717
4718         adev->gfx.priv_inst_irq.num_types = 1;
4719         adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs;
4720
4721         adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
4722         adev->gfx.kiq.irq.funcs = &gfx_v9_0_kiq_irq_funcs;
4723 }
4724
4725 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
4726 {
4727         switch (adev->asic_type) {
4728         case CHIP_VEGA10:
4729         case CHIP_VEGA12:
4730         case CHIP_VEGA20:
4731         case CHIP_RAVEN:
4732                 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
4733                 break;
4734         default:
4735                 break;
4736         }
4737 }
4738
4739 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
4740 {
4741         /* init asci gds info */
4742         adev->gds.mem.total_size = RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
4743         adev->gds.gws.total_size = 64;
4744         adev->gds.oa.total_size = 16;
4745
4746         if (adev->gds.mem.total_size == 64 * 1024) {
4747                 adev->gds.mem.gfx_partition_size = 4096;
4748                 adev->gds.mem.cs_partition_size = 4096;
4749
4750                 adev->gds.gws.gfx_partition_size = 4;
4751                 adev->gds.gws.cs_partition_size = 4;
4752
4753                 adev->gds.oa.gfx_partition_size = 4;
4754                 adev->gds.oa.cs_partition_size = 1;
4755         } else {
4756                 adev->gds.mem.gfx_partition_size = 1024;
4757                 adev->gds.mem.cs_partition_size = 1024;
4758
4759                 adev->gds.gws.gfx_partition_size = 16;
4760                 adev->gds.gws.cs_partition_size = 16;
4761
4762                 adev->gds.oa.gfx_partition_size = 4;
4763                 adev->gds.oa.cs_partition_size = 4;
4764         }
4765 }
4766
4767 static void gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
4768                                                  u32 bitmap)
4769 {
4770         u32 data;
4771
4772         if (!bitmap)
4773                 return;
4774
4775         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4776         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4777
4778         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
4779 }
4780
4781 static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)
4782 {
4783         u32 data, mask;
4784
4785         data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
4786         data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
4787
4788         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4789         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4790
4791         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
4792
4793         return (~data) & mask;
4794 }
4795
4796 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
4797                                  struct amdgpu_cu_info *cu_info)
4798 {
4799         int i, j, k, counter, active_cu_number = 0;
4800         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
4801         unsigned disable_masks[4 * 2];
4802
4803         if (!adev || !cu_info)
4804                 return -EINVAL;
4805
4806         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
4807
4808         mutex_lock(&adev->grbm_idx_mutex);
4809         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4810                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4811                         mask = 1;
4812                         ao_bitmap = 0;
4813                         counter = 0;
4814                         gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
4815                         if (i < 4 && j < 2)
4816                                 gfx_v9_0_set_user_cu_inactive_bitmap(
4817                                         adev, disable_masks[i * 2 + j]);
4818                         bitmap = gfx_v9_0_get_cu_active_bitmap(adev);
4819                         cu_info->bitmap[i][j] = bitmap;
4820
4821                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
4822                                 if (bitmap & mask) {
4823                                         if (counter < adev->gfx.config.max_cu_per_sh)
4824                                                 ao_bitmap |= mask;
4825                                         counter ++;
4826                                 }
4827                                 mask <<= 1;
4828                         }
4829                         active_cu_number += counter;
4830                         if (i < 2 && j < 2)
4831                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
4832                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
4833                 }
4834         }
4835         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4836         mutex_unlock(&adev->grbm_idx_mutex);
4837
4838         cu_info->number = active_cu_number;
4839         cu_info->ao_cu_mask = ao_cu_mask;
4840         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
4841
4842         return 0;
4843 }
4844
4845 const struct amdgpu_ip_block_version gfx_v9_0_ip_block =
4846 {
4847         .type = AMD_IP_BLOCK_TYPE_GFX,
4848         .major = 9,
4849         .minor = 0,
4850         .rev = 0,
4851         .funcs = &gfx_v9_0_ip_funcs,
4852 };