drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/kernel.h>
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_gfx.h"
  28 #include "soc15.h"
  29 #include "soc15d.h"
  30 #include "amdgpu_atomfirmware.h"
  31
  32 #include "gc/gc_9_0_offset.h"
  33 #include "gc/gc_9_0_sh_mask.h"
  34 #include "vega10_enum.h"
  35 #include "hdp/hdp_4_0_offset.h"
  36
  37 #include "soc15_common.h"
  38 #include "clearstate_gfx9.h"
  39 #include "v9_structs.h"
  40
  41 #define GFX9_NUM_GFX_RINGS     1
  42 #define GFX9_MEC_HPD_SIZE 2048
  43 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
  44 #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L
  45
  46 #define mmPWR_MISC_CNTL_STATUS                                  0x0183
  47 #define mmPWR_MISC_CNTL_STATUS_BASE_IDX                         0
  48 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT        0x0
  49 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT          0x1
  50 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK          0x00000001L
  51 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK            0x00000006L
  52
  53 MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
  54 MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
  55 MODULE_FIRMWARE("amdgpu/vega10_me.bin");
  56 MODULE_FIRMWARE("amdgpu/vega10_mec.bin");
  57 MODULE_FIRMWARE("amdgpu/vega10_mec2.bin");
  58 MODULE_FIRMWARE("amdgpu/vega10_rlc.bin");
  59
  60 MODULE_FIRMWARE("amdgpu/vega12_ce.bin");
  61 MODULE_FIRMWARE("amdgpu/vega12_pfp.bin");
  62 MODULE_FIRMWARE("amdgpu/vega12_me.bin");
  63 MODULE_FIRMWARE("amdgpu/vega12_mec.bin");
  64 MODULE_FIRMWARE("amdgpu/vega12_mec2.bin");
  65 MODULE_FIRMWARE("amdgpu/vega12_rlc.bin");
  66
  67 MODULE_FIRMWARE("amdgpu/vega20_ce.bin");
  68 MODULE_FIRMWARE("amdgpu/vega20_pfp.bin");
  69 MODULE_FIRMWARE("amdgpu/vega20_me.bin");
  70 MODULE_FIRMWARE("amdgpu/vega20_mec.bin");
  71 MODULE_FIRMWARE("amdgpu/vega20_mec2.bin");
  72 MODULE_FIRMWARE("amdgpu/vega20_rlc.bin");
  73
  74 MODULE_FIRMWARE("amdgpu/raven_ce.bin");
  75 MODULE_FIRMWARE("amdgpu/raven_pfp.bin");
  76 MODULE_FIRMWARE("amdgpu/raven_me.bin");
  77 MODULE_FIRMWARE("amdgpu/raven_mec.bin");
  78 MODULE_FIRMWARE("amdgpu/raven_mec2.bin");
  79 MODULE_FIRMWARE("amdgpu/raven_rlc.bin");
  80
  81 static const struct soc15_reg_golden golden_settings_gc_9_0[] =
  82 {
  83         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420),
  84         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
  85         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
  86         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
  87         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
  88         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000),
  89         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800),
  90         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800),
  91         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87),
  92         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f),
  93         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000),
  94         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
  95         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68),
  96         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197),
  97         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
  98         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff)
  99 };
 100
 101 static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] =
 102 {
 103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0x0000f000, 0x00012107),
 104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
 105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042),
 106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x2a114042),
 107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00008000, 0x00048000),
 108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000),
 109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800)
 110 };
 111
 112 static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] =
 113 {
 114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x0f000080, 0x04000080),
 115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000),
 116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
 117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x22014042),
 118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x22014042),
 119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0x00003e00, 0x00000400),
 120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xff840000, 0x04040000),
 121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00030000),
 122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff010f, 0x01000107),
 123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x000b0000, 0x000b0000),
 124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01000000, 0x01000000)
 125 };
 126
 127 static const struct soc15_reg_golden golden_settings_gc_9_1[] =
 128 {
 129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
 130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080),
 131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080),
 132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080),
 133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420),
 134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
 135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080),
 136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
 137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
 138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080),
 140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080),
 141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080),
 142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080),
 143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080),
 144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
 145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
 146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120),
 147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
 148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
 149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080)
 150 };
 151
 152 static const struct soc15_reg_golden golden_settings_gc_9_1_rv1[] =
 153 {
 154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
 155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24000042),
 156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24000042),
 157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04048000),
 158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_MODE_CNTL_1, 0x06000000, 0x06000000),
 159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000),
 160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x00000800)
 161 };
 162
 163 static const struct soc15_reg_golden golden_settings_gc_9_x_common[] =
 164 {
 165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_INDEX, 0xffffffff, 0x00000000),
 166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2544c382)
 167 };
 168
 169 static const struct soc15_reg_golden golden_settings_gc_9_2_1[] =
 170 {
 171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420),
 172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
 173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
 174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
 175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000),
 177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800),
 178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800),
 179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87),
 180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f),
 181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000),
 182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
 183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68),
 184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197),
 185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
 186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff)
 187 };
 188
 189 static const struct soc15_reg_golden golden_settings_gc_9_2_1_vg12[] =
 190 {
 191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x00000080, 0x04000080),
 192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
 193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000),
 194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24104041),
 195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24104041),
 196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000),
 197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff03ff, 0x01000107),
 198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
 199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x76325410),
 200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000)
 201 };
 202
 203 static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[] =
 204 {
 205         mmRLC_SRM_INDEX_CNTL_ADDR_0 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 206         mmRLC_SRM_INDEX_CNTL_ADDR_1 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 207         mmRLC_SRM_INDEX_CNTL_ADDR_2 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 208         mmRLC_SRM_INDEX_CNTL_ADDR_3 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 209         mmRLC_SRM_INDEX_CNTL_ADDR_4 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 210         mmRLC_SRM_INDEX_CNTL_ADDR_5 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 211         mmRLC_SRM_INDEX_CNTL_ADDR_6 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 212         mmRLC_SRM_INDEX_CNTL_ADDR_7 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 213 };
 214
 215 static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] =
 216 {
 217         mmRLC_SRM_INDEX_CNTL_DATA_0 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 218         mmRLC_SRM_INDEX_CNTL_DATA_1 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 219         mmRLC_SRM_INDEX_CNTL_DATA_2 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 220         mmRLC_SRM_INDEX_CNTL_DATA_3 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 221         mmRLC_SRM_INDEX_CNTL_DATA_4 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 222         mmRLC_SRM_INDEX_CNTL_DATA_5 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 223         mmRLC_SRM_INDEX_CNTL_DATA_6 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 224         mmRLC_SRM_INDEX_CNTL_DATA_7 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 225 };
 226
 227 #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
 228 #define VEGA12_GB_ADDR_CONFIG_GOLDEN 0x24104041
 229 #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042
 230
 231 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
 232 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
 233 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev);
 234 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
 235 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
 236                                  struct amdgpu_cu_info *cu_info);
 237 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
 238 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
 239 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
 240
 241 static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
 242 {
 243         switch (adev->asic_type) {
 244         case CHIP_VEGA10:
 245                 soc15_program_register_sequence(adev,
 246                                                  golden_settings_gc_9_0,
 247                                                  ARRAY_SIZE(golden_settings_gc_9_0));
 248                 soc15_program_register_sequence(adev,
 249                                                  golden_settings_gc_9_0_vg10,
 250                                                  ARRAY_SIZE(golden_settings_gc_9_0_vg10));
 251                 break;
 252         case CHIP_VEGA12:
 253                 soc15_program_register_sequence(adev,
 254                                                 golden_settings_gc_9_2_1,
 255                                                 ARRAY_SIZE(golden_settings_gc_9_2_1));
 256                 soc15_program_register_sequence(adev,
 257                                                 golden_settings_gc_9_2_1_vg12,
 258                                                 ARRAY_SIZE(golden_settings_gc_9_2_1_vg12));
 259                 break;
 260         case CHIP_VEGA20:
 261                 soc15_program_register_sequence(adev,
 262                                                 golden_settings_gc_9_0,
 263                                                 ARRAY_SIZE(golden_settings_gc_9_0));
 264                 soc15_program_register_sequence(adev,
 265                                                 golden_settings_gc_9_0_vg20,
 266                                                 ARRAY_SIZE(golden_settings_gc_9_0_vg20));
 267                 break;
 268         case CHIP_RAVEN:
 269                 soc15_program_register_sequence(adev,
 270                                                  golden_settings_gc_9_1,
 271                                                  ARRAY_SIZE(golden_settings_gc_9_1));
 272                 soc15_program_register_sequence(adev,
 273                                                  golden_settings_gc_9_1_rv1,
 274                                                  ARRAY_SIZE(golden_settings_gc_9_1_rv1));
 275                 break;
 276         default:
 277                 break;
 278         }
 279
 280         soc15_program_register_sequence(adev, golden_settings_gc_9_x_common,
 281                                         (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common));
 282 }
 283
 284 static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
 285 {
 286         adev->gfx.scratch.num_reg = 8;
 287         adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
 288         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
 289 }
 290
 291 static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
 292                                        bool wc, uint32_t reg, uint32_t val)
 293 {
 294         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
 295         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
 296                                 WRITE_DATA_DST_SEL(0) |
 297                                 (wc ? WR_CONFIRM : 0));
 298         amdgpu_ring_write(ring, reg);
 299         amdgpu_ring_write(ring, 0);
 300         amdgpu_ring_write(ring, val);
 301 }
 302
 303 static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
 304                                   int mem_space, int opt, uint32_t addr0,
 305                                   uint32_t addr1, uint32_t ref, uint32_t mask,
 306                                   uint32_t inv)
 307 {
 308         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
 309         amdgpu_ring_write(ring,
 310                                  /* memory (1) or register (0) */
 311                                  (WAIT_REG_MEM_MEM_SPACE(mem_space) |
 312                                  WAIT_REG_MEM_OPERATION(opt) | /* wait */
 313                                  WAIT_REG_MEM_FUNCTION(3) |  /* equal */
 314                                  WAIT_REG_MEM_ENGINE(eng_sel)));
 315
 316         if (mem_space)
 317                 BUG_ON(addr0 & 0x3); /* Dword align */
 318         amdgpu_ring_write(ring, addr0);
 319         amdgpu_ring_write(ring, addr1);
 320         amdgpu_ring_write(ring, ref);
 321         amdgpu_ring_write(ring, mask);
 322         amdgpu_ring_write(ring, inv); /* poll interval */
 323 }
 324
 325 static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring)
 326 {
 327         struct amdgpu_device *adev = ring->adev;
 328         uint32_t scratch;
 329         uint32_t tmp = 0;
 330         unsigned i;
 331         int r;
 332
 333         r = amdgpu_gfx_scratch_get(adev, &scratch);
 334         if (r) {
 335                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
 336                 return r;
 337         }
 338         WREG32(scratch, 0xCAFEDEAD);
 339         r = amdgpu_ring_alloc(ring, 3);
 340         if (r) {
 341                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 342                           ring->idx, r);
 343                 amdgpu_gfx_scratch_free(adev, scratch);
 344                 return r;
 345         }
 346         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
 347         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
 348         amdgpu_ring_write(ring, 0xDEADBEEF);
 349         amdgpu_ring_commit(ring);
 350
 351         for (i = 0; i < adev->usec_timeout; i++) {
 352                 tmp = RREG32(scratch);
 353                 if (tmp == 0xDEADBEEF)
 354                         break;
 355                 DRM_UDELAY(1);
 356         }
 357         if (i < adev->usec_timeout) {
 358                 DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
 359                          ring->idx, i);
 360         } else {
 361                 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
 362                           ring->idx, scratch, tmp);
 363                 r = -EINVAL;
 364         }
 365         amdgpu_gfx_scratch_free(adev, scratch);
 366         return r;
 367 }
 368
 369 static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 370 {
 371         struct amdgpu_device *adev = ring->adev;
 372         struct amdgpu_ib ib;
 373         struct dma_fence *f = NULL;
 374
 375         unsigned index;
 376         uint64_t gpu_addr;
 377         uint32_t tmp;
 378         long r;
 379
 380         r = amdgpu_device_wb_get(adev, &index);
 381         if (r) {
 382                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 383                 return r;
 384         }
 385
 386         gpu_addr = adev->wb.gpu_addr + (index * 4);
 387         adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
 388         memset(&ib, 0, sizeof(ib));
 389         r = amdgpu_ib_get(adev, NULL, 16, &ib);
 390         if (r) {
 391                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 392                 goto err1;
 393         }
 394         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
 395         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
 396         ib.ptr[2] = lower_32_bits(gpu_addr);
 397         ib.ptr[3] = upper_32_bits(gpu_addr);
 398         ib.ptr[4] = 0xDEADBEEF;
 399         ib.length_dw = 5;
 400
 401         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 402         if (r)
 403                 goto err2;
 404
 405         r = dma_fence_wait_timeout(f, false, timeout);
 406         if (r == 0) {
 407                         DRM_ERROR("amdgpu: IB test timed out.\n");
 408                         r = -ETIMEDOUT;
 409                         goto err2;
 410         } else if (r < 0) {
 411                         DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 412                         goto err2;
 413         }
 414
 415         tmp = adev->wb.wb[index];
 416         if (tmp == 0xDEADBEEF) {
 417                         DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
 418                         r = 0;
 419         } else {
 420                         DRM_ERROR("ib test on ring %d failed\n", ring->idx);
 421                         r = -EINVAL;
 422         }
 423
 424 err2:
 425         amdgpu_ib_free(adev, &ib, NULL);
 426         dma_fence_put(f);
 427 err1:
 428         amdgpu_device_wb_free(adev, index);
 429         return r;
 430 }
 431
 432
 433 static void gfx_v9_0_free_microcode(struct amdgpu_device *adev)
 434 {
 435         release_firmware(adev->gfx.pfp_fw);
 436         adev->gfx.pfp_fw = NULL;
 437         release_firmware(adev->gfx.me_fw);
 438         adev->gfx.me_fw = NULL;
 439         release_firmware(adev->gfx.ce_fw);
 440         adev->gfx.ce_fw = NULL;
 441         release_firmware(adev->gfx.rlc_fw);
 442         adev->gfx.rlc_fw = NULL;
 443         release_firmware(adev->gfx.mec_fw);
 444         adev->gfx.mec_fw = NULL;
 445         release_firmware(adev->gfx.mec2_fw);
 446         adev->gfx.mec2_fw = NULL;
 447
 448         kfree(adev->gfx.rlc.register_list_format);
 449 }
 450
 451 static void gfx_v9_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
 452 {
 453         const struct rlc_firmware_header_v2_1 *rlc_hdr;
 454
 455         rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
 456         adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
 457         adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
 458         adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
 459         adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
 460         adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
 461         adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
 462         adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
 463         adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
 464         adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
 465         adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
 466         adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
 467         adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
 468         adev->gfx.rlc.reg_list_format_direct_reg_list_length =
 469                         le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
 470 }
 471
 472 static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
 473 {
 474         const char *chip_name;
 475         char fw_name[30];
 476         int err;
 477         struct amdgpu_firmware_info *info = NULL;
 478         const struct common_firmware_header *header = NULL;
 479         const struct gfx_firmware_header_v1_0 *cp_hdr;
 480         const struct rlc_firmware_header_v2_0 *rlc_hdr;
 481         unsigned int *tmp = NULL;
 482         unsigned int i = 0;
 483         uint16_t version_major;
 484         uint16_t version_minor;
 485
 486         DRM_DEBUG("\n");
 487
 488         switch (adev->asic_type) {
 489         case CHIP_VEGA10:
 490                 chip_name = "vega10";
 491                 break;
 492         case CHIP_VEGA12:
 493                 chip_name = "vega12";
 494                 break;
 495         case CHIP_VEGA20:
 496                 chip_name = "vega20";
 497                 break;
 498         case CHIP_RAVEN:
 499                 chip_name = "raven";
 500                 break;
 501         default:
 502                 BUG();
 503         }
 504
 505         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
 506         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
 507         if (err)
 508                 goto out;
 509         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
 510         if (err)
 511                 goto out;
 512         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
 513         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 514         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 515
 516         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
 517         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
 518         if (err)
 519                 goto out;
 520         err = amdgpu_ucode_validate(adev->gfx.me_fw);
 521         if (err)
 522                 goto out;
 523         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
 524         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 525         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 526
 527         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
 528         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
 529         if (err)
 530                 goto out;
 531         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
 532         if (err)
 533                 goto out;
 534         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
 535         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 536         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 537
 538         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
 539         err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
 540         if (err)
 541                 goto out;
 542         err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
 543         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
 544
 545         version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
 546         version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
 547         if (version_major == 2 && version_minor == 1)
 548                 adev->gfx.rlc.is_rlc_v2_1 = true;
 549
 550         adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
 551         adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
 552         adev->gfx.rlc.save_and_restore_offset =
 553                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
 554         adev->gfx.rlc.clear_state_descriptor_offset =
 555                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
 556         adev->gfx.rlc.avail_scratch_ram_locations =
 557                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
 558         adev->gfx.rlc.reg_restore_list_size =
 559                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
 560         adev->gfx.rlc.reg_list_format_start =
 561                         le32_to_cpu(rlc_hdr->reg_list_format_start);
 562         adev->gfx.rlc.reg_list_format_separate_start =
 563                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
 564         adev->gfx.rlc.starting_offsets_start =
 565                         le32_to_cpu(rlc_hdr->starting_offsets_start);
 566         adev->gfx.rlc.reg_list_format_size_bytes =
 567                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
 568         adev->gfx.rlc.reg_list_size_bytes =
 569                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
 570         adev->gfx.rlc.register_list_format =
 571                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
 572                                 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
 573         if (!adev->gfx.rlc.register_list_format) {
 574                 err = -ENOMEM;
 575                 goto out;
 576         }
 577
 578         tmp = (unsigned int *)((uintptr_t)rlc_hdr +
 579                         le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
 580         for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
 581                 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
 582
 583         adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
 584
 585         tmp = (unsigned int *)((uintptr_t)rlc_hdr +
 586                         le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
 587         for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
 588                 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
 589
 590         if (adev->gfx.rlc.is_rlc_v2_1)
 591                 gfx_v9_0_init_rlc_ext_microcode(adev);
 592
 593         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
 594         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
 595         if (err)
 596                 goto out;
 597         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
 598         if (err)
 599                 goto out;
 600         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
 601         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 602         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 603
 604
 605         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
 606         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
 607         if (!err) {
 608                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
 609                 if (err)
 610                         goto out;
 611                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
 612                 adev->gfx.mec2_fw->data;
 613                 adev->gfx.mec2_fw_version =
 614                 le32_to_cpu(cp_hdr->header.ucode_version);
 615                 adev->gfx.mec2_feature_version =
 616                 le32_to_cpu(cp_hdr->ucode_feature_version);
 617         } else {
 618                 err = 0;
 619                 adev->gfx.mec2_fw = NULL;
 620         }
 621
 622         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 623                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
 624                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
 625                 info->fw = adev->gfx.pfp_fw;
 626                 header = (const struct common_firmware_header *)info->fw->data;
 627                 adev->firmware.fw_size +=
 628                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 629
 630                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
 631                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
 632                 info->fw = adev->gfx.me_fw;
 633                 header = (const struct common_firmware_header *)info->fw->data;
 634                 adev->firmware.fw_size +=
 635                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 636
 637                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
 638                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
 639                 info->fw = adev->gfx.ce_fw;
 640                 header = (const struct common_firmware_header *)info->fw->data;
 641                 adev->firmware.fw_size +=
 642                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 643
 644                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
 645                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
 646                 info->fw = adev->gfx.rlc_fw;
 647                 header = (const struct common_firmware_header *)info->fw->data;
 648                 adev->firmware.fw_size +=
 649                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 650
 651                 if (adev->gfx.rlc.is_rlc_v2_1) {
 652                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
 653                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
 654                         info->fw = adev->gfx.rlc_fw;
 655                         adev->firmware.fw_size +=
 656                                 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
 657
 658                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
 659                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
 660                         info->fw = adev->gfx.rlc_fw;
 661                         adev->firmware.fw_size +=
 662                                 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
 663
 664                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
 665                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
 666                         info->fw = adev->gfx.rlc_fw;
 667                         adev->firmware.fw_size +=
 668                                 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
 669                 }
 670
 671                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
 672                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
 673                 info->fw = adev->gfx.mec_fw;
 674                 header = (const struct common_firmware_header *)info->fw->data;
 675                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
 676                 adev->firmware.fw_size +=
 677                         ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 678
 679                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
 680                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
 681                 info->fw = adev->gfx.mec_fw;
 682                 adev->firmware.fw_size +=
 683                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 684
 685                 if (adev->gfx.mec2_fw) {
 686                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
 687                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 688                         info->fw = adev->gfx.mec2_fw;
 689                         header = (const struct common_firmware_header *)info->fw->data;
 690                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
 691                         adev->firmware.fw_size +=
 692                                 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 693                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
 694                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
 695                         info->fw = adev->gfx.mec2_fw;
 696                         adev->firmware.fw_size +=
 697                                 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 698                 }
 699
 700         }
 701
 702 out:
 703         if (err) {
 704                 dev_err(adev->dev,
 705                         "gfx9: Failed to load firmware \"%s\"\n",
 706                         fw_name);
 707                 release_firmware(adev->gfx.pfp_fw);
 708                 adev->gfx.pfp_fw = NULL;
 709                 release_firmware(adev->gfx.me_fw);
 710                 adev->gfx.me_fw = NULL;
 711                 release_firmware(adev->gfx.ce_fw);
 712                 adev->gfx.ce_fw = NULL;
 713                 release_firmware(adev->gfx.rlc_fw);
 714                 adev->gfx.rlc_fw = NULL;
 715                 release_firmware(adev->gfx.mec_fw);
 716                 adev->gfx.mec_fw = NULL;
 717                 release_firmware(adev->gfx.mec2_fw);
 718                 adev->gfx.mec2_fw = NULL;
 719         }
 720         return err;
 721 }
 722
 723 static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
 724 {
 725         u32 count = 0;
 726         const struct cs_section_def *sect = NULL;
 727         const struct cs_extent_def *ext = NULL;
 728
 729         /* begin clear state */
 730         count += 2;
 731         /* context control state */
 732         count += 3;
 733
 734         for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
 735                 for (ext = sect->section; ext->extent != NULL; ++ext) {
 736                         if (sect->id == SECT_CONTEXT)
 737                                 count += 2 + ext->reg_count;
 738                         else
 739                                 return 0;
 740                 }
 741         }
 742
 743         /* end clear state */
 744         count += 2;
 745         /* clear state */
 746         count += 2;
 747
 748         return count;
 749 }
 750
 751 static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev,
 752                                     volatile u32 *buffer)
 753 {
 754         u32 count = 0, i;
 755         const struct cs_section_def *sect = NULL;
 756         const struct cs_extent_def *ext = NULL;
 757
 758         if (adev->gfx.rlc.cs_data == NULL)
 759                 return;
 760         if (buffer == NULL)
 761                 return;
 762
 763         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 764         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
 765
 766         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
 767         buffer[count++] = cpu_to_le32(0x80000000);
 768         buffer[count++] = cpu_to_le32(0x80000000);
 769
 770         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
 771                 for (ext = sect->section; ext->extent != NULL; ++ext) {
 772                         if (sect->id == SECT_CONTEXT) {
 773                                 buffer[count++] =
 774                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
 775                                 buffer[count++] = cpu_to_le32(ext->reg_index -
 776                                                 PACKET3_SET_CONTEXT_REG_START);
 777                                 for (i = 0; i < ext->reg_count; i++)
 778                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
 779                         } else {
 780                                 return;
 781                         }
 782                 }
 783         }
 784
 785         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 786         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
 787
 788         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
 789         buffer[count++] = cpu_to_le32(0);
 790 }
 791
 792 static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev)
 793 {
 794         uint32_t data;
 795
 796         /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */
 797         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F);
 798         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7);
 799         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077);
 800         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16));
 801
 802         /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */
 803         WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000);
 804
 805         /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */
 806         WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500);
 807
 808         mutex_lock(&adev->grbm_idx_mutex);
 809         /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/
 810         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 811         WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff);
 812
 813         /* set mmRLC_LB_PARAMS = 0x003F_1006 */
 814         data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003);
 815         data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010);
 816         data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F);
 817         WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data);
 818
 819         /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */
 820         data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7);
 821         data &= 0x0000FFFF;
 822         data |= 0x00C00000;
 823         WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data);
 824
 825         /* set RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF */
 826         WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, 0xFFF);
 827
 828         /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved,
 829          * but used for RLC_LB_CNTL configuration */
 830         data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK;
 831         data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09);
 832         data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000);
 833         WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data);
 834         mutex_unlock(&adev->grbm_idx_mutex);
 835 }
 836
 837 static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
 838 {
 839         WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
 840 }
 841
 842 static void rv_init_cp_jump_table(struct amdgpu_device *adev)
 843 {
 844         const __le32 *fw_data;
 845         volatile u32 *dst_ptr;
 846         int me, i, max_me = 5;
 847         u32 bo_offset = 0;
 848         u32 table_offset, table_size;
 849
 850         /* write the cp table buffer */
 851         dst_ptr = adev->gfx.rlc.cp_table_ptr;
 852         for (me = 0; me < max_me; me++) {
 853                 if (me == 0) {
 854                         const struct gfx_firmware_header_v1_0 *hdr =
 855                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
 856                         fw_data = (const __le32 *)
 857                                 (adev->gfx.ce_fw->data +
 858                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 859                         table_offset = le32_to_cpu(hdr->jt_offset);
 860                         table_size = le32_to_cpu(hdr->jt_size);
 861                 } else if (me == 1) {
 862                         const struct gfx_firmware_header_v1_0 *hdr =
 863                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
 864                         fw_data = (const __le32 *)
 865                                 (adev->gfx.pfp_fw->data +
 866                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 867                         table_offset = le32_to_cpu(hdr->jt_offset);
 868                         table_size = le32_to_cpu(hdr->jt_size);
 869                 } else if (me == 2) {
 870                         const struct gfx_firmware_header_v1_0 *hdr =
 871                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
 872                         fw_data = (const __le32 *)
 873                                 (adev->gfx.me_fw->data +
 874                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 875                         table_offset = le32_to_cpu(hdr->jt_offset);
 876                         table_size = le32_to_cpu(hdr->jt_size);
 877                 } else if (me == 3) {
 878                         const struct gfx_firmware_header_v1_0 *hdr =
 879                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
 880                         fw_data = (const __le32 *)
 881                                 (adev->gfx.mec_fw->data +
 882                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 883                         table_offset = le32_to_cpu(hdr->jt_offset);
 884                         table_size = le32_to_cpu(hdr->jt_size);
 885                 } else  if (me == 4) {
 886                         const struct gfx_firmware_header_v1_0 *hdr =
 887                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
 888                         fw_data = (const __le32 *)
 889                                 (adev->gfx.mec2_fw->data +
 890                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 891                         table_offset = le32_to_cpu(hdr->jt_offset);
 892                         table_size = le32_to_cpu(hdr->jt_size);
 893                 }
 894
 895                 for (i = 0; i < table_size; i ++) {
 896                         dst_ptr[bo_offset + i] =
 897                                 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
 898                 }
 899
 900                 bo_offset += table_size;
 901         }
 902 }
 903
 904 static void gfx_v9_0_rlc_fini(struct amdgpu_device *adev)
 905 {
 906         /* clear state block */
 907         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
 908                         &adev->gfx.rlc.clear_state_gpu_addr,
 909                         (void **)&adev->gfx.rlc.cs_ptr);
 910
 911         /* jump table block */
 912         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
 913                         &adev->gfx.rlc.cp_table_gpu_addr,
 914                         (void **)&adev->gfx.rlc.cp_table_ptr);
 915 }
 916
 917 static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
 918 {
 919         volatile u32 *dst_ptr;
 920         u32 dws;
 921         const struct cs_section_def *cs_data;
 922         int r;
 923
 924         adev->gfx.rlc.cs_data = gfx9_cs_data;
 925
 926         cs_data = adev->gfx.rlc.cs_data;
 927
 928         if (cs_data) {
 929                 /* clear state block */
 930                 adev->gfx.rlc.clear_state_size = dws = gfx_v9_0_get_csb_size(adev);
 931                 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
 932                                               AMDGPU_GEM_DOMAIN_VRAM,
 933                                               &adev->gfx.rlc.clear_state_obj,
 934                                               &adev->gfx.rlc.clear_state_gpu_addr,
 935                                               (void **)&adev->gfx.rlc.cs_ptr);
 936                 if (r) {
 937                         dev_err(adev->dev, "(%d) failed to create rlc csb bo\n",
 938                                 r);
 939                         gfx_v9_0_rlc_fini(adev);
 940                         return r;
 941                 }
 942                 /* set up the cs buffer */
 943                 dst_ptr = adev->gfx.rlc.cs_ptr;
 944                 gfx_v9_0_get_csb_buffer(adev, dst_ptr);
 945                 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
 946                 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
 947                 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
 948         }
 949
 950         if (adev->asic_type == CHIP_RAVEN) {
 951                 /* TODO: double check the cp_table_size for RV */
 952                 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
 953                 r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size,
 954                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 955                                               &adev->gfx.rlc.cp_table_obj,
 956                                               &adev->gfx.rlc.cp_table_gpu_addr,
 957                                               (void **)&adev->gfx.rlc.cp_table_ptr);
 958                 if (r) {
 959                         dev_err(adev->dev,
 960                                 "(%d) failed to create cp table bo\n", r);
 961                         gfx_v9_0_rlc_fini(adev);
 962                         return r;
 963                 }
 964
 965                 rv_init_cp_jump_table(adev);
 966                 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
 967                 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
 968
 969                 gfx_v9_0_init_lbpw(adev);
 970         }
 971
 972         return 0;
 973 }
 974
 975 static int gfx_v9_0_csb_vram_pin(struct amdgpu_device *adev)
 976 {
 977         int r;
 978
 979         r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
 980         if (unlikely(r != 0))
 981                 return r;
 982
 983         r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj,
 984                         AMDGPU_GEM_DOMAIN_VRAM);
 985         if (!r)
 986                 adev->gfx.rlc.clear_state_gpu_addr =
 987                         amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj);
 988
 989         amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
 990
 991         return r;
 992 }
 993
 994 static void gfx_v9_0_csb_vram_unpin(struct amdgpu_device *adev)
 995 {
 996         int r;
 997
 998         if (!adev->gfx.rlc.clear_state_obj)
 999                 return;
1000
1001         r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
1002         if (likely(r == 0)) {
1003                 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
1004                 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1005         }
1006 }
1007
1008 static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
1009 {
1010         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
1011         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
1012 }
1013
1014 static int gfx_v9_0_mec_init(struct amdgpu_device *adev)
1015 {
1016         int r;
1017         u32 *hpd;
1018         const __le32 *fw_data;
1019         unsigned fw_size;
1020         u32 *fw;
1021         size_t mec_hpd_size;
1022
1023         const struct gfx_firmware_header_v1_0 *mec_hdr;
1024
1025         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
1026
1027         /* take ownership of the relevant compute queues */
1028         amdgpu_gfx_compute_queue_acquire(adev);
1029         mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE;
1030
1031         r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
1032                                       AMDGPU_GEM_DOMAIN_GTT,
1033                                       &adev->gfx.mec.hpd_eop_obj,
1034                                       &adev->gfx.mec.hpd_eop_gpu_addr,
1035                                       (void **)&hpd);
1036         if (r) {
1037                 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
1038                 gfx_v9_0_mec_fini(adev);
1039                 return r;
1040         }
1041
1042         memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
1043
1044         amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
1045         amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1046
1047         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1048
1049         fw_data = (const __le32 *)
1050                 (adev->gfx.mec_fw->data +
1051                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
1052         fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
1053
1054         r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
1055                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
1056                                       &adev->gfx.mec.mec_fw_obj,
1057                                       &adev->gfx.mec.mec_fw_gpu_addr,
1058                                       (void **)&fw);
1059         if (r) {
1060                 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r);
1061                 gfx_v9_0_mec_fini(adev);
1062                 return r;
1063         }
1064
1065         memcpy(fw, fw_data, fw_size);
1066
1067         amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
1068         amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
1069
1070         return 0;
1071 }
1072
1073 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
1074 {
1075         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1076                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1077                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
1078                 (address << SQ_IND_INDEX__INDEX__SHIFT) |
1079                 (SQ_IND_INDEX__FORCE_READ_MASK));
1080         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1081 }
1082
1083 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
1084                            uint32_t wave, uint32_t thread,
1085                            uint32_t regno, uint32_t num, uint32_t *out)
1086 {
1087         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1088                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1089                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
1090                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
1091                 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
1092                 (SQ_IND_INDEX__FORCE_READ_MASK) |
1093                 (SQ_IND_INDEX__AUTO_INCR_MASK));
1094         while (num--)
1095                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1096 }
1097
1098 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
1099 {
1100         /* type 1 wave data */
1101         dst[(*no_fields)++] = 1;
1102         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
1103         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
1104         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
1105         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
1106         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
1107         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
1108         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
1109         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
1110         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
1111         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
1112         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
1113         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
1114         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
1115         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
1116 }
1117
1118 static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
1119                                      uint32_t wave, uint32_t start,
1120                                      uint32_t size, uint32_t *dst)
1121 {
1122         wave_read_regs(
1123                 adev, simd, wave, 0,
1124                 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
1125 }
1126
1127 static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
1128                                      uint32_t wave, uint32_t thread,
1129                                      uint32_t start, uint32_t size,
1130                                      uint32_t *dst)
1131 {
1132         wave_read_regs(
1133                 adev, simd, wave, thread,
1134                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
1135 }
1136
1137 static void gfx_v9_0_select_me_pipe_q(struct amdgpu_device *adev,
1138                                   u32 me, u32 pipe, u32 q)
1139 {
1140         soc15_grbm_select(adev, me, pipe, q, 0);
1141 }
1142
1143 static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
1144         .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
1145         .select_se_sh = &gfx_v9_0_select_se_sh,
1146         .read_wave_data = &gfx_v9_0_read_wave_data,
1147         .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
1148         .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs,
1149         .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q
1150 };
1151
1152 static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
1153 {
1154         u32 gb_addr_config;
1155         int err;
1156
1157         adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
1158
1159         switch (adev->asic_type) {
1160         case CHIP_VEGA10:
1161                 adev->gfx.config.max_hw_contexts = 8;
1162                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1163                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1164                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1165                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1166                 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN;
1167                 break;
1168         case CHIP_VEGA12:
1169                 adev->gfx.config.max_hw_contexts = 8;
1170                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1171                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1172                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1173                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1174                 gb_addr_config = VEGA12_GB_ADDR_CONFIG_GOLDEN;
1175                 DRM_INFO("fix gfx.config for vega12\n");
1176                 break;
1177         case CHIP_VEGA20:
1178                 adev->gfx.config.max_hw_contexts = 8;
1179                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1180                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1181                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1182                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1183                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
1184                 gb_addr_config &= ~0xf3e777ff;
1185                 gb_addr_config |= 0x22014042;
1186                 /* check vbios table if gpu info is not available */
1187                 err = amdgpu_atomfirmware_get_gfx_info(adev);
1188                 if (err)
1189                         return err;
1190                 break;
1191         case CHIP_RAVEN:
1192                 adev->gfx.config.max_hw_contexts = 8;
1193                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1194                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1195                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1196                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1197                 gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
1198                 break;
1199         default:
1200                 BUG();
1201                 break;
1202         }
1203
1204         adev->gfx.config.gb_addr_config = gb_addr_config;
1205
1206         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
1207                         REG_GET_FIELD(
1208                                         adev->gfx.config.gb_addr_config,
1209                                         GB_ADDR_CONFIG,
1210                                         NUM_PIPES);
1211
1212         adev->gfx.config.max_tile_pipes =
1213                 adev->gfx.config.gb_addr_config_fields.num_pipes;
1214
1215         adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
1216                         REG_GET_FIELD(
1217                                         adev->gfx.config.gb_addr_config,
1218                                         GB_ADDR_CONFIG,
1219                                         NUM_BANKS);
1220         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
1221                         REG_GET_FIELD(
1222                                         adev->gfx.config.gb_addr_config,
1223                                         GB_ADDR_CONFIG,
1224                                         MAX_COMPRESSED_FRAGS);
1225         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
1226                         REG_GET_FIELD(
1227                                         adev->gfx.config.gb_addr_config,
1228                                         GB_ADDR_CONFIG,
1229                                         NUM_RB_PER_SE);
1230         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
1231                         REG_GET_FIELD(
1232                                         adev->gfx.config.gb_addr_config,
1233                                         GB_ADDR_CONFIG,
1234                                         NUM_SHADER_ENGINES);
1235         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
1236                         REG_GET_FIELD(
1237                                         adev->gfx.config.gb_addr_config,
1238                                         GB_ADDR_CONFIG,
1239                                         PIPE_INTERLEAVE_SIZE));
1240
1241         return 0;
1242 }
1243
1244 static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev,
1245                                    struct amdgpu_ngg_buf *ngg_buf,
1246                                    int size_se,
1247                                    int default_size_se)
1248 {
1249         int r;
1250
1251         if (size_se < 0) {
1252                 dev_err(adev->dev, "Buffer size is invalid: %d\n", size_se);
1253                 return -EINVAL;
1254         }
1255         size_se = size_se ? size_se : default_size_se;
1256
1257         ngg_buf->size = size_se * adev->gfx.config.max_shader_engines;
1258         r = amdgpu_bo_create_kernel(adev, ngg_buf->size,
1259                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1260                                     &ngg_buf->bo,
1261                                     &ngg_buf->gpu_addr,
1262                                     NULL);
1263         if (r) {
1264                 dev_err(adev->dev, "(%d) failed to create NGG buffer\n", r);
1265                 return r;
1266         }
1267         ngg_buf->bo_size = amdgpu_bo_size(ngg_buf->bo);
1268
1269         return r;
1270 }
1271
1272 static int gfx_v9_0_ngg_fini(struct amdgpu_device *adev)
1273 {
1274         int i;
1275
1276         for (i = 0; i < NGG_BUF_MAX; i++)
1277                 amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo,
1278                                       &adev->gfx.ngg.buf[i].gpu_addr,
1279                                       NULL);
1280
1281         memset(&adev->gfx.ngg.buf[0], 0,
1282                         sizeof(struct amdgpu_ngg_buf) * NGG_BUF_MAX);
1283
1284         adev->gfx.ngg.init = false;
1285
1286         return 0;
1287 }
1288
1289 static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
1290 {
1291         int r;
1292
1293         if (!amdgpu_ngg || adev->gfx.ngg.init == true)
1294                 return 0;
1295
1296         /* GDS reserve memory: 64 bytes alignment */
1297         adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
1298         adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;
1299         adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;
1300         adev->gfx.ngg.gds_reserve_addr = RREG32_SOC15(GC, 0, mmGDS_VMID0_BASE);
1301         adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
1302
1303         /* Primitive Buffer */
1304         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM],
1305                                     amdgpu_prim_buf_per_se,
1306                                     64 * 1024);
1307         if (r) {
1308                 dev_err(adev->dev, "Failed to create Primitive Buffer\n");
1309                 goto err;
1310         }
1311
1312         /* Position Buffer */
1313         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_POS],
1314                                     amdgpu_pos_buf_per_se,
1315                                     256 * 1024);
1316         if (r) {
1317                 dev_err(adev->dev, "Failed to create Position Buffer\n");
1318                 goto err;
1319         }
1320
1321         /* Control Sideband */
1322         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_CNTL],
1323                                     amdgpu_cntl_sb_buf_per_se,
1324                                     256);
1325         if (r) {
1326                 dev_err(adev->dev, "Failed to create Control Sideband Buffer\n");
1327                 goto err;
1328         }
1329
1330         /* Parameter Cache, not created by default */
1331         if (amdgpu_param_buf_per_se <= 0)
1332                 goto out;
1333
1334         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PARAM],
1335                                     amdgpu_param_buf_per_se,
1336                                     512 * 1024);
1337         if (r) {
1338                 dev_err(adev->dev, "Failed to create Parameter Cache\n");
1339                 goto err;
1340         }
1341
1342 out:
1343         adev->gfx.ngg.init = true;
1344         return 0;
1345 err:
1346         gfx_v9_0_ngg_fini(adev);
1347         return r;
1348 }
1349
1350 static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
1351 {
1352         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
1353         int r;
1354         u32 data, base;
1355
1356         if (!amdgpu_ngg)
1357                 return 0;
1358
1359         /* Program buffer size */
1360         data = REG_SET_FIELD(0, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE,
1361                              adev->gfx.ngg.buf[NGG_PRIM].size >> 8);
1362         data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE,
1363                              adev->gfx.ngg.buf[NGG_POS].size >> 8);
1364         WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_1, data);
1365
1366         data = REG_SET_FIELD(0, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE,
1367                              adev->gfx.ngg.buf[NGG_CNTL].size >> 8);
1368         data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE,
1369                              adev->gfx.ngg.buf[NGG_PARAM].size >> 10);
1370         WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_2, data);
1371
1372         /* Program buffer base address */
1373         base = lower_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
1374         data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base);
1375         WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE, data);
1376
1377         base = upper_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
1378         data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base);
1379         WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE_HI, data);
1380
1381         base = lower_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
1382         data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base);
1383         WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE, data);
1384
1385         base = upper_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
1386         data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base);
1387         WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE_HI, data);
1388
1389         base = lower_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
1390         data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base);
1391         WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE, data);
1392
1393         base = upper_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
1394         data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base);
1395         WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI, data);
1396
1397         /* Clear GDS reserved memory */
1398         r = amdgpu_ring_alloc(ring, 17);
1399         if (r) {
1400                 DRM_ERROR("amdgpu: NGG failed to lock ring %d (%d).\n",
1401                           ring->idx, r);
1402                 return r;
1403         }
1404
1405         gfx_v9_0_write_data_to_reg(ring, 0, false,
1406                                    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
1407                                    (adev->gds.mem.total_size +
1408                                     adev->gfx.ngg.gds_reserve_size) >>
1409                                    AMDGPU_GDS_SHIFT);
1410
1411         amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
1412         amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
1413                                 PACKET3_DMA_DATA_DST_SEL(1) |
1414                                 PACKET3_DMA_DATA_SRC_SEL(2)));
1415         amdgpu_ring_write(ring, 0);
1416         amdgpu_ring_write(ring, 0);
1417         amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
1418         amdgpu_ring_write(ring, 0);
1419         amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT |
1420                                 adev->gfx.ngg.gds_reserve_size);
1421
1422         gfx_v9_0_write_data_to_reg(ring, 0, false,
1423                                    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0);
1424
1425         amdgpu_ring_commit(ring);
1426
1427         return 0;
1428 }
1429
1430 static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1431                                       int mec, int pipe, int queue)
1432 {
1433         int r;
1434         unsigned irq_type;
1435         struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1436
1437         ring = &adev->gfx.compute_ring[ring_id];
1438
1439         /* mec0 is me1 */
1440         ring->me = mec + 1;
1441         ring->pipe = pipe;
1442         ring->queue = queue;
1443
1444         ring->ring_obj = NULL;
1445         ring->use_doorbell = true;
1446         ring->doorbell_index = (AMDGPU_DOORBELL_MEC_RING0 + ring_id) << 1;
1447         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1448                                 + (ring_id * GFX9_MEC_HPD_SIZE);
1449         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1450
1451         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1452                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1453                 + ring->pipe;
1454
1455         /* type-2 packets are deprecated on MEC, use type-3 instead */
1456         r = amdgpu_ring_init(adev, ring, 1024,
1457                              &adev->gfx.eop_irq, irq_type);
1458         if (r)
1459                 return r;
1460
1461
1462         return 0;
1463 }
1464
1465 static int gfx_v9_0_sw_init(void *handle)
1466 {
1467         int i, j, k, r, ring_id;
1468         struct amdgpu_ring *ring;
1469         struct amdgpu_kiq *kiq;
1470         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1471
1472         switch (adev->asic_type) {
1473         case CHIP_VEGA10:
1474         case CHIP_VEGA12:
1475         case CHIP_VEGA20:
1476         case CHIP_RAVEN:
1477                 adev->gfx.mec.num_mec = 2;
1478                 break;
1479         default:
1480                 adev->gfx.mec.num_mec = 1;
1481                 break;
1482         }
1483
1484         adev->gfx.mec.num_pipe_per_mec = 4;
1485         adev->gfx.mec.num_queue_per_pipe = 8;
1486
1487         /* KIQ event */
1488         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 178, &adev->gfx.kiq.irq);
1489         if (r)
1490                 return r;
1491
1492         /* EOP Event */
1493         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 181, &adev->gfx.eop_irq);
1494         if (r)
1495                 return r;
1496
1497         /* Privileged reg */
1498         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 184,
1499                               &adev->gfx.priv_reg_irq);
1500         if (r)
1501                 return r;
1502
1503         /* Privileged inst */
1504         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 185,
1505                               &adev->gfx.priv_inst_irq);
1506         if (r)
1507                 return r;
1508
1509         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1510
1511         gfx_v9_0_scratch_init(adev);
1512
1513         r = gfx_v9_0_init_microcode(adev);
1514         if (r) {
1515                 DRM_ERROR("Failed to load gfx firmware!\n");
1516                 return r;
1517         }
1518
1519         r = gfx_v9_0_rlc_init(adev);
1520         if (r) {
1521                 DRM_ERROR("Failed to init rlc BOs!\n");
1522                 return r;
1523         }
1524
1525         r = gfx_v9_0_mec_init(adev);
1526         if (r) {
1527                 DRM_ERROR("Failed to init MEC BOs!\n");
1528                 return r;
1529         }
1530
1531         /* set up the gfx ring */
1532         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
1533                 ring = &adev->gfx.gfx_ring[i];
1534                 ring->ring_obj = NULL;
1535                 if (!i)
1536                         sprintf(ring->name, "gfx");
1537                 else
1538                         sprintf(ring->name, "gfx_%d", i);
1539                 ring->use_doorbell = true;
1540                 ring->doorbell_index = AMDGPU_DOORBELL64_GFX_RING0 << 1;
1541                 r = amdgpu_ring_init(adev, ring, 1024,
1542                                      &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
1543                 if (r)
1544                         return r;
1545         }
1546
1547         /* set up the compute queues - allocate horizontally across pipes */
1548         ring_id = 0;
1549         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1550                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1551                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
1552                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j))
1553                                         continue;
1554
1555                                 r = gfx_v9_0_compute_ring_init(adev,
1556                                                                ring_id,
1557                                                                i, k, j);
1558                                 if (r)
1559                                         return r;
1560
1561                                 ring_id++;
1562                         }
1563                 }
1564         }
1565
1566         r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE);
1567         if (r) {
1568                 DRM_ERROR("Failed to init KIQ BOs!\n");
1569                 return r;
1570         }
1571
1572         kiq = &adev->gfx.kiq;
1573         r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
1574         if (r)
1575                 return r;
1576
1577         /* create MQD for all compute queues as wel as KIQ for SRIOV case */
1578         r = amdgpu_gfx_compute_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation));
1579         if (r)
1580                 return r;
1581
1582         /* reserve GDS, GWS and OA resource for gfx */
1583         r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
1584                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
1585                                     &adev->gds.gds_gfx_bo, NULL, NULL);
1586         if (r)
1587                 return r;
1588
1589         r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
1590                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
1591                                     &adev->gds.gws_gfx_bo, NULL, NULL);
1592         if (r)
1593                 return r;
1594
1595         r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
1596                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
1597                                     &adev->gds.oa_gfx_bo, NULL, NULL);
1598         if (r)
1599                 return r;
1600
1601         adev->gfx.ce_ram_size = 0x8000;
1602
1603         r = gfx_v9_0_gpu_early_init(adev);
1604         if (r)
1605                 return r;
1606
1607         r = gfx_v9_0_ngg_init(adev);
1608         if (r)
1609                 return r;
1610
1611         return 0;
1612 }
1613
1614
1615 static int gfx_v9_0_sw_fini(void *handle)
1616 {
1617         int i;
1618         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1619
1620         amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
1621         amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
1622         amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
1623
1624         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1625                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1626         for (i = 0; i < adev->gfx.num_compute_rings; i++)
1627                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1628
1629         amdgpu_gfx_compute_mqd_sw_fini(adev);
1630         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
1631         amdgpu_gfx_kiq_fini(adev);
1632
1633         gfx_v9_0_mec_fini(adev);
1634         gfx_v9_0_ngg_fini(adev);
1635         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
1636                                 &adev->gfx.rlc.clear_state_gpu_addr,
1637                                 (void **)&adev->gfx.rlc.cs_ptr);
1638         if (adev->asic_type == CHIP_RAVEN) {
1639                 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
1640                                 &adev->gfx.rlc.cp_table_gpu_addr,
1641                                 (void **)&adev->gfx.rlc.cp_table_ptr);
1642         }
1643         gfx_v9_0_free_microcode(adev);
1644
1645         return 0;
1646 }
1647
1648
1649 static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev)
1650 {
1651         /* TODO */
1652 }
1653
1654 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance)
1655 {
1656         u32 data;
1657
1658         if (instance == 0xffffffff)
1659                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1660         else
1661                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1662
1663         if (se_num == 0xffffffff)
1664                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1665         else
1666                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1667
1668         if (sh_num == 0xffffffff)
1669                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1670         else
1671                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1672
1673         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
1674 }
1675
1676 static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1677 {
1678         u32 data, mask;
1679
1680         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
1681         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
1682
1683         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1684         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1685
1686         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1687                                          adev->gfx.config.max_sh_per_se);
1688
1689         return (~data) & mask;
1690 }
1691
1692 static void gfx_v9_0_setup_rb(struct amdgpu_device *adev)
1693 {
1694         int i, j;
1695         u32 data;
1696         u32 active_rbs = 0;
1697         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1698                                         adev->gfx.config.max_sh_per_se;
1699
1700         mutex_lock(&adev->grbm_idx_mutex);
1701         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1702                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1703                         gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1704                         data = gfx_v9_0_get_rb_active_bitmap(adev);
1705                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1706                                                rb_bitmap_width_per_sh);
1707                 }
1708         }
1709         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1710         mutex_unlock(&adev->grbm_idx_mutex);
1711
1712         adev->gfx.config.backend_enable_mask = active_rbs;
1713         adev->gfx.config.num_rbs = hweight32(active_rbs);
1714 }
1715
1716 #define DEFAULT_SH_MEM_BASES    (0x6000)
1717 #define FIRST_COMPUTE_VMID      (8)
1718 #define LAST_COMPUTE_VMID       (16)
1719 static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
1720 {
1721         int i;
1722         uint32_t sh_mem_config;
1723         uint32_t sh_mem_bases;
1724
1725         /*
1726          * Configure apertures:
1727          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
1728          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
1729          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
1730          */
1731         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1732
1733         sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
1734                         SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1735                         SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
1736
1737         mutex_lock(&adev->srbm_mutex);
1738         for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1739                 soc15_grbm_select(adev, 0, 0, 0, i);
1740                 /* CP and shaders */
1741                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
1742                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
1743         }
1744         soc15_grbm_select(adev, 0, 0, 0, 0);
1745         mutex_unlock(&adev->srbm_mutex);
1746 }
1747
1748 static void gfx_v9_0_gpu_init(struct amdgpu_device *adev)
1749 {
1750         u32 tmp;
1751         int i;
1752
1753         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
1754
1755         gfx_v9_0_tiling_mode_table_init(adev);
1756
1757         gfx_v9_0_setup_rb(adev);
1758         gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);
1759         adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2);
1760
1761         /* XXX SH_MEM regs */
1762         /* where to put LDS, scratch, GPUVM in FSA64 space */
1763         mutex_lock(&adev->srbm_mutex);
1764         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids; i++) {
1765                 soc15_grbm_select(adev, 0, 0, 0, i);
1766                 /* CP and shaders */
1767                 if (i == 0) {
1768                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
1769                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1770                         WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
1771                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0);
1772                 } else {
1773                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
1774                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1775                         WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
1776                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
1777                                 (adev->gmc.private_aperture_start >> 48));
1778                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
1779                                 (adev->gmc.shared_aperture_start >> 48));
1780                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
1781                 }
1782         }
1783         soc15_grbm_select(adev, 0, 0, 0, 0);
1784
1785         mutex_unlock(&adev->srbm_mutex);
1786
1787         gfx_v9_0_init_compute_vmid(adev);
1788
1789         mutex_lock(&adev->grbm_idx_mutex);
1790         /*
1791          * making sure that the following register writes will be broadcasted
1792          * to all the shaders
1793          */
1794         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1795
1796         WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE,
1797                    (adev->gfx.config.sc_prim_fifo_size_frontend <<
1798                         PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1799                    (adev->gfx.config.sc_prim_fifo_size_backend <<
1800                         PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1801                    (adev->gfx.config.sc_hiz_tile_fifo_size <<
1802                         PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1803                    (adev->gfx.config.sc_earlyz_tile_fifo_size <<
1804                         PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
1805         mutex_unlock(&adev->grbm_idx_mutex);
1806
1807 }
1808
1809 static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
1810 {
1811         u32 i, j, k;
1812         u32 mask;
1813
1814         mutex_lock(&adev->grbm_idx_mutex);
1815         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1816                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1817                         gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1818                         for (k = 0; k < adev->usec_timeout; k++) {
1819                                 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0)
1820                                         break;
1821                                 udelay(1);
1822                         }
1823                         if (k == adev->usec_timeout) {
1824                                 gfx_v9_0_select_se_sh(adev, 0xffffffff,
1825                                                       0xffffffff, 0xffffffff);
1826                                 mutex_unlock(&adev->grbm_idx_mutex);
1827                                 DRM_INFO("Timeout wait for RLC serdes %u,%u\n",
1828                                          i, j);
1829                                 return;
1830                         }
1831                 }
1832         }
1833         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1834         mutex_unlock(&adev->grbm_idx_mutex);
1835
1836         mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
1837                 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
1838                 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
1839                 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
1840         for (k = 0; k < adev->usec_timeout; k++) {
1841                 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
1842                         break;
1843                 udelay(1);
1844         }
1845 }
1846
1847 static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1848                                                bool enable)
1849 {
1850         u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
1851
1852         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
1853         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
1854         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
1855         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
1856
1857         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
1858 }
1859
1860 static void gfx_v9_0_init_csb(struct amdgpu_device *adev)
1861 {
1862         /* csib */
1863         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI),
1864                         adev->gfx.rlc.clear_state_gpu_addr >> 32);
1865         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO),
1866                         adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
1867         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH),
1868                         adev->gfx.rlc.clear_state_size);
1869 }
1870
1871 static void gfx_v9_1_parse_ind_reg_list(int *register_list_format,
1872                                 int indirect_offset,
1873                                 int list_size,
1874                                 int *unique_indirect_regs,
1875                                 int unique_indirect_reg_count,
1876                                 int *indirect_start_offsets,
1877                                 int *indirect_start_offsets_count,
1878                                 int max_start_offsets_count)
1879 {
1880         int idx;
1881
1882         for (; indirect_offset < list_size; indirect_offset++) {
1883                 WARN_ON(*indirect_start_offsets_count >= max_start_offsets_count);
1884                 indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset;
1885                 *indirect_start_offsets_count = *indirect_start_offsets_count + 1;
1886
1887                 while (register_list_format[indirect_offset] != 0xFFFFFFFF) {
1888                         indirect_offset += 2;
1889
1890                         /* look for the matching indice */
1891                         for (idx = 0; idx < unique_indirect_reg_count; idx++) {
1892                                 if (unique_indirect_regs[idx] ==
1893                                         register_list_format[indirect_offset] ||
1894                                         !unique_indirect_regs[idx])
1895                                         break;
1896                         }
1897
1898                         BUG_ON(idx >= unique_indirect_reg_count);
1899
1900                         if (!unique_indirect_regs[idx])
1901                                 unique_indirect_regs[idx] = register_list_format[indirect_offset];
1902
1903                         indirect_offset++;
1904                 }
1905         }
1906 }
1907
1908 static int gfx_v9_1_init_rlc_save_restore_list(struct amdgpu_device *adev)
1909 {
1910         int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
1911         int unique_indirect_reg_count = 0;
1912
1913         int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
1914         int indirect_start_offsets_count = 0;
1915
1916         int list_size = 0;
1917         int i = 0, j = 0;
1918         u32 tmp = 0;
1919
1920         u32 *register_list_format =
1921                 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
1922         if (!register_list_format)
1923                 return -ENOMEM;
1924         memcpy(register_list_format, adev->gfx.rlc.register_list_format,
1925                 adev->gfx.rlc.reg_list_format_size_bytes);
1926
1927         /* setup unique_indirect_regs array and indirect_start_offsets array */
1928         unique_indirect_reg_count = ARRAY_SIZE(unique_indirect_regs);
1929         gfx_v9_1_parse_ind_reg_list(register_list_format,
1930                                     adev->gfx.rlc.reg_list_format_direct_reg_list_length,
1931                                     adev->gfx.rlc.reg_list_format_size_bytes >> 2,
1932                                     unique_indirect_regs,
1933                                     unique_indirect_reg_count,
1934                                     indirect_start_offsets,
1935                                     &indirect_start_offsets_count,
1936                                     ARRAY_SIZE(indirect_start_offsets));
1937
1938         /* enable auto inc in case it is disabled */
1939         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
1940         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
1941         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
1942
1943         /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */
1944         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR),
1945                 RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET);
1946         for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
1947                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
1948                         adev->gfx.rlc.register_restore[i]);
1949
1950         /* load indirect register */
1951         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1952                 adev->gfx.rlc.reg_list_format_start);
1953
1954         /* direct register portion */
1955         for (i = 0; i < adev->gfx.rlc.reg_list_format_direct_reg_list_length; i++)
1956                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
1957                         register_list_format[i]);
1958
1959         /* indirect register portion */
1960         while (i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2)) {
1961                 if (register_list_format[i] == 0xFFFFFFFF) {
1962                         WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
1963                         continue;
1964                 }
1965
1966                 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
1967                 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
1968
1969                 for (j = 0; j < unique_indirect_reg_count; j++) {
1970                         if (register_list_format[i] == unique_indirect_regs[j]) {
1971                                 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, j);
1972                                 break;
1973                         }
1974                 }
1975
1976                 BUG_ON(j >= unique_indirect_reg_count);
1977
1978                 i++;
1979         }
1980
1981         /* set save/restore list size */
1982         list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
1983         list_size = list_size >> 1;
1984         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1985                 adev->gfx.rlc.reg_restore_list_size);
1986         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size);
1987
1988         /* write the starting offsets to RLC scratch ram */
1989         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1990                 adev->gfx.rlc.starting_offsets_start);
1991         for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++)
1992                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
1993                        indirect_start_offsets[i]);
1994
1995         /* load unique indirect regs*/
1996         for (i = 0; i < ARRAY_SIZE(unique_indirect_regs); i++) {
1997                 if (unique_indirect_regs[i] != 0) {
1998                         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0)
1999                                + GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[i],
2000                                unique_indirect_regs[i] & 0x3FFFF);
2001
2002                         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0)
2003                                + GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[i],
2004                                unique_indirect_regs[i] >> 20);
2005                 }
2006         }
2007
2008         kfree(register_list_format);
2009         return 0;
2010 }
2011
2012 static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev)
2013 {
2014         WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1);
2015 }
2016
2017 static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev,
2018                                              bool enable)
2019 {
2020         uint32_t data = 0;
2021         uint32_t default_data = 0;
2022
2023         default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS));
2024         if (enable == true) {
2025                 /* enable GFXIP control over CGPG */
2026                 data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
2027                 if(default_data != data)
2028                         WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
2029
2030                 /* update status */
2031                 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK;
2032                 data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT);
2033                 if(default_data != data)
2034                         WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
2035         } else {
2036                 /* restore GFXIP control over GCPG */
2037                 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
2038                 if(default_data != data)
2039                         WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
2040         }
2041 }
2042
2043 static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev)
2044 {
2045         uint32_t data = 0;
2046
2047         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2048                               AMD_PG_SUPPORT_GFX_SMG |
2049                               AMD_PG_SUPPORT_GFX_DMG)) {
2050                 /* init IDLE_POLL_COUNT = 60 */
2051                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));
2052                 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
2053                 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
2054                 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data);
2055
2056                 /* init RLC PG Delay */
2057                 data = 0;
2058                 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT);
2059                 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT);
2060                 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT);
2061                 data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT);
2062                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data);
2063
2064                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2));
2065                 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK;
2066                 data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT);
2067                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data);
2068
2069                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3));
2070                 data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK;
2071                 data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT);
2072                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data);
2073
2074                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL));
2075                 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
2076
2077                 /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */
2078                 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
2079                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data);
2080
2081                 pwr_10_0_gfxip_control_over_cgpg(adev, true);
2082         }
2083 }
2084
2085 static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
2086                                                 bool enable)
2087 {
2088         uint32_t data = 0;
2089         uint32_t default_data = 0;
2090
2091         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2092         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2093                              SMU_CLK_SLOWDOWN_ON_PU_ENABLE,
2094                              enable ? 1 : 0);
2095         if (default_data != data)
2096                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2097 }
2098
2099 static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
2100                                                 bool enable)
2101 {
2102         uint32_t data = 0;
2103         uint32_t default_data = 0;
2104
2105         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2106         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2107                              SMU_CLK_SLOWDOWN_ON_PD_ENABLE,
2108                              enable ? 1 : 0);
2109         if(default_data != data)
2110                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2111 }
2112
2113 static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev,
2114                                         bool enable)
2115 {
2116         uint32_t data = 0;
2117         uint32_t default_data = 0;
2118
2119         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2120         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2121                              CP_PG_DISABLE,
2122                              enable ? 0 : 1);
2123         if(default_data != data)
2124                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2125 }
2126
2127 static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
2128                                                 bool enable)
2129 {
2130         uint32_t data, default_data;
2131
2132         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2133         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2134                              GFX_POWER_GATING_ENABLE,
2135                              enable ? 1 : 0);
2136         if(default_data != data)
2137                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2138 }
2139
2140 static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev,
2141                                                 bool enable)
2142 {
2143         uint32_t data, default_data;
2144
2145         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2146         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2147                              GFX_PIPELINE_PG_ENABLE,
2148                              enable ? 1 : 0);
2149         if(default_data != data)
2150                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2151
2152         if (!enable)
2153                 /* read any GFX register to wake up GFX */
2154                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL));
2155 }
2156
2157 static void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
2158                                                        bool enable)
2159 {
2160         uint32_t data, default_data;
2161
2162         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2163         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2164                              STATIC_PER_CU_PG_ENABLE,
2165                              enable ? 1 : 0);
2166         if(default_data != data)
2167                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2168 }
2169
2170 static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
2171                                                 bool enable)
2172 {
2173         uint32_t data, default_data;
2174
2175         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2176         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2177                              DYN_PER_CU_PG_ENABLE,
2178                              enable ? 1 : 0);
2179         if(default_data != data)
2180                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2181 }
2182
2183 static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
2184 {
2185         gfx_v9_0_init_csb(adev);
2186
2187         if (!adev->gfx.rlc.is_rlc_v2_1)
2188                 return;
2189
2190         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2191                               AMD_PG_SUPPORT_GFX_SMG |
2192                               AMD_PG_SUPPORT_GFX_DMG |
2193                               AMD_PG_SUPPORT_CP |
2194                               AMD_PG_SUPPORT_GDS |
2195                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
2196                 gfx_v9_1_init_rlc_save_restore_list(adev);
2197                 gfx_v9_0_enable_save_restore_machine(adev);
2198
2199                 WREG32(mmRLC_JUMP_TABLE_RESTORE,
2200                        adev->gfx.rlc.cp_table_gpu_addr >> 8);
2201                 gfx_v9_0_init_gfx_power_gating(adev);
2202         }
2203 }
2204
2205 void gfx_v9_0_rlc_stop(struct amdgpu_device *adev)
2206 {
2207         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0);
2208         gfx_v9_0_enable_gui_idle_interrupt(adev, false);
2209         gfx_v9_0_wait_for_rlc_serdes(adev);
2210 }
2211
2212 static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev)
2213 {
2214         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2215         udelay(50);
2216         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2217         udelay(50);
2218 }
2219
2220 static void gfx_v9_0_rlc_start(struct amdgpu_device *adev)
2221 {
2222 #ifdef AMDGPU_RLC_DEBUG_RETRY
2223         u32 rlc_ucode_ver;
2224 #endif
2225
2226         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
2227
2228         /* carrizo do enable cp interrupt after cp inited */
2229         if (!(adev->flags & AMD_IS_APU))
2230                 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
2231
2232         udelay(50);
2233
2234 #ifdef AMDGPU_RLC_DEBUG_RETRY
2235         /* RLC_GPM_GENERAL_6 : RLC Ucode version */
2236         rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6);
2237         if(rlc_ucode_ver == 0x108) {
2238                 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n",
2239                                 rlc_ucode_ver, adev->gfx.rlc_fw_version);
2240                 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles,
2241                  * default is 0x9C4 to create a 100us interval */
2242                 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4);
2243                 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
2244                  * to disable the page fault retry interrupts, default is
2245                  * 0x100 (256) */
2246                 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100);
2247         }
2248 #endif
2249 }
2250
2251 static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev)
2252 {
2253         const struct rlc_firmware_header_v2_0 *hdr;
2254         const __le32 *fw_data;
2255         unsigned i, fw_size;
2256
2257         if (!adev->gfx.rlc_fw)
2258                 return -EINVAL;
2259
2260         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2261         amdgpu_ucode_print_rlc_hdr(&hdr->header);
2262
2263         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2264                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2265         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2266
2267         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
2268                         RLCG_UCODE_LOADING_START_ADDRESS);
2269         for (i = 0; i < fw_size; i++)
2270                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
2271         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
2272
2273         return 0;
2274 }
2275
2276 static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
2277 {
2278         int r;
2279
2280         if (amdgpu_sriov_vf(adev)) {
2281                 gfx_v9_0_init_csb(adev);
2282                 return 0;
2283         }
2284
2285         gfx_v9_0_rlc_stop(adev);
2286
2287         /* disable CG */
2288         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
2289
2290         /* disable PG */
2291         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
2292
2293         gfx_v9_0_rlc_reset(adev);
2294
2295         gfx_v9_0_init_pg(adev);
2296
2297         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2298                 /* legacy rlc firmware loading */
2299                 r = gfx_v9_0_rlc_load_microcode(adev);
2300                 if (r)
2301                         return r;
2302         }
2303
2304         if (adev->asic_type == CHIP_RAVEN) {
2305                 if (amdgpu_lbpw != 0)
2306                         gfx_v9_0_enable_lbpw(adev, true);
2307                 else
2308                         gfx_v9_0_enable_lbpw(adev, false);
2309         }
2310
2311         gfx_v9_0_rlc_start(adev);
2312
2313         return 0;
2314 }
2315
2316 static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2317 {
2318         int i;
2319         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
2320
2321         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2322         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2323         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
2324         if (!enable) {
2325                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2326                         adev->gfx.gfx_ring[i].ready = false;
2327         }
2328         WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
2329         udelay(50);
2330 }
2331
2332 static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2333 {
2334         const struct gfx_firmware_header_v1_0 *pfp_hdr;
2335         const struct gfx_firmware_header_v1_0 *ce_hdr;
2336         const struct gfx_firmware_header_v1_0 *me_hdr;
2337         const __le32 *fw_data;
2338         unsigned i, fw_size;
2339
2340         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2341                 return -EINVAL;
2342
2343         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2344                 adev->gfx.pfp_fw->data;
2345         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2346                 adev->gfx.ce_fw->data;
2347         me_hdr = (const struct gfx_firmware_header_v1_0 *)
2348                 adev->gfx.me_fw->data;
2349
2350         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2351         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2352         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2353
2354         gfx_v9_0_cp_gfx_enable(adev, false);
2355
2356         /* PFP */
2357         fw_data = (const __le32 *)
2358                 (adev->gfx.pfp_fw->data +
2359                  le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2360         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2361         WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0);
2362         for (i = 0; i < fw_size; i++)
2363                 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2364         WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2365
2366         /* CE */
2367         fw_data = (const __le32 *)
2368                 (adev->gfx.ce_fw->data +
2369                  le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2370         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2371         WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0);
2372         for (i = 0; i < fw_size; i++)
2373                 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2374         WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2375
2376         /* ME */
2377         fw_data = (const __le32 *)
2378                 (adev->gfx.me_fw->data +
2379                  le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2380         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2381         WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0);
2382         for (i = 0; i < fw_size; i++)
2383                 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2384         WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2385
2386         return 0;
2387 }
2388
2389 static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)
2390 {
2391         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2392         const struct cs_section_def *sect = NULL;
2393         const struct cs_extent_def *ext = NULL;
2394         int r, i, tmp;
2395
2396         /* init the CP */
2397         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2398         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
2399
2400         gfx_v9_0_cp_gfx_enable(adev, true);
2401
2402         r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3);
2403         if (r) {
2404                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2405                 return r;
2406         }
2407
2408         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2409         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2410
2411         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2412         amdgpu_ring_write(ring, 0x80000000);
2413         amdgpu_ring_write(ring, 0x80000000);
2414
2415         for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
2416                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2417                         if (sect->id == SECT_CONTEXT) {
2418                                 amdgpu_ring_write(ring,
2419                                        PACKET3(PACKET3_SET_CONTEXT_REG,
2420                                                ext->reg_count));
2421                                 amdgpu_ring_write(ring,
2422                                        ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2423                                 for (i = 0; i < ext->reg_count; i++)
2424                                         amdgpu_ring_write(ring, ext->extent[i]);
2425                         }
2426                 }
2427         }
2428
2429         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2430         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2431
2432         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2433         amdgpu_ring_write(ring, 0);
2434
2435         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2436         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2437         amdgpu_ring_write(ring, 0x8000);
2438         amdgpu_ring_write(ring, 0x8000);
2439
2440         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1));
2441         tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE |
2442                 (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START));
2443         amdgpu_ring_write(ring, tmp);
2444         amdgpu_ring_write(ring, 0);
2445
2446         amdgpu_ring_commit(ring);
2447
2448         return 0;
2449 }
2450
2451 static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
2452 {
2453         struct amdgpu_ring *ring;
2454         u32 tmp;
2455         u32 rb_bufsz;
2456         u64 rb_addr, rptr_addr, wptr_gpu_addr;
2457
2458         /* Set the write pointer delay */
2459         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
2460
2461         /* set the RB to use vmid 0 */
2462         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
2463
2464         /* Set ring buffer size */
2465         ring = &adev->gfx.gfx_ring[0];
2466         rb_bufsz = order_base_2(ring->ring_size / 8);
2467         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2468         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2469 #ifdef __BIG_ENDIAN
2470         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
2471 #endif
2472         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2473
2474         /* Initialize the ring buffer's write pointers */
2475         ring->wptr = 0;
2476         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2477         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
2478
2479         /* set the wb address wether it's enabled or not */
2480         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2481         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2482         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
2483
2484         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2485         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
2486         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
2487
2488         mdelay(1);
2489         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2490
2491         rb_addr = ring->gpu_addr >> 8;
2492         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
2493         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2494
2495         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
2496         if (ring->use_doorbell) {
2497                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2498                                     DOORBELL_OFFSET, ring->doorbell_index);
2499                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2500                                     DOORBELL_EN, 1);
2501         } else {
2502                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
2503         }
2504         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
2505
2506         tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2507                         DOORBELL_RANGE_LOWER, ring->doorbell_index);
2508         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
2509
2510         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
2511                        CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2512
2513
2514         /* start the ring */
2515         gfx_v9_0_cp_gfx_start(adev);
2516         ring->ready = true;
2517
2518         return 0;
2519 }
2520
2521 static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2522 {
2523         int i;
2524
2525         if (enable) {
2526                 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
2527         } else {
2528                 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
2529                         (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2530                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2531                         adev->gfx.compute_ring[i].ready = false;
2532                 adev->gfx.kiq.ring.ready = false;
2533         }
2534         udelay(50);
2535 }
2536
2537 static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2538 {
2539         const struct gfx_firmware_header_v1_0 *mec_hdr;
2540         const __le32 *fw_data;
2541         unsigned i;
2542         u32 tmp;
2543
2544         if (!adev->gfx.mec_fw)
2545                 return -EINVAL;
2546
2547         gfx_v9_0_cp_compute_enable(adev, false);
2548
2549         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2550         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2551
2552         fw_data = (const __le32 *)
2553                 (adev->gfx.mec_fw->data +
2554                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2555         tmp = 0;
2556         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
2557         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
2558         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
2559
2560         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
2561                 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
2562         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
2563                 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
2564
2565         /* MEC1 */
2566         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
2567                          mec_hdr->jt_offset);
2568         for (i = 0; i < mec_hdr->jt_size; i++)
2569                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
2570                         le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
2571
2572         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
2573                         adev->gfx.mec_fw_version);
2574         /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
2575
2576         return 0;
2577 }
2578
2579 /* KIQ functions */
2580 static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
2581 {
2582         uint32_t tmp;
2583         struct amdgpu_device *adev = ring->adev;
2584
2585         /* tell RLC which is KIQ queue */
2586         tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
2587         tmp &= 0xffffff00;
2588         tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
2589         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2590         tmp |= 0x80;
2591         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2592 }
2593
2594 static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev)
2595 {
2596         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
2597         uint32_t scratch, tmp = 0;
2598         uint64_t queue_mask = 0;
2599         int r, i;
2600
2601         for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
2602                 if (!test_bit(i, adev->gfx.mec.queue_bitmap))
2603                         continue;
2604
2605                 /* This situation may be hit in the future if a new HW
2606                  * generation exposes more than 64 queues. If so, the
2607                  * definition of queue_mask needs updating */
2608                 if (WARN_ON(i >= (sizeof(queue_mask)*8))) {
2609                         DRM_ERROR("Invalid KCQ enabled: %d\n", i);
2610                         break;
2611                 }
2612
2613                 queue_mask |= (1ull << i);
2614         }
2615
2616         r = amdgpu_gfx_scratch_get(adev, &scratch);
2617         if (r) {
2618                 DRM_ERROR("Failed to get scratch reg (%d).\n", r);
2619                 return r;
2620         }
2621         WREG32(scratch, 0xCAFEDEAD);
2622
2623         r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 11);
2624         if (r) {
2625                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
2626                 amdgpu_gfx_scratch_free(adev, scratch);
2627                 return r;
2628         }
2629
2630         /* set resources */
2631         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
2632         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
2633                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
2634         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
2635         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
2636         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
2637         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
2638         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
2639         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
2640         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2641                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2642                 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
2643                 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2644
2645                 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
2646                 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
2647                 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
2648                                   PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
2649                                   PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
2650                                   PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
2651                                   PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
2652                                   PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
2653                                   PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
2654                                   PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
2655                                   PACKET3_MAP_QUEUES_ENGINE_SEL(0) | /* engine_sel: compute */
2656                                   PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
2657                 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
2658                 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
2659                 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
2660                 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
2661                 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
2662         }
2663         /* write to scratch for completion */
2664         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2665         amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2666         amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
2667         amdgpu_ring_commit(kiq_ring);
2668
2669         for (i = 0; i < adev->usec_timeout; i++) {
2670                 tmp = RREG32(scratch);
2671                 if (tmp == 0xDEADBEEF)
2672                         break;
2673                 DRM_UDELAY(1);
2674         }
2675         if (i >= adev->usec_timeout) {
2676                 DRM_ERROR("KCQ enable failed (scratch(0x%04X)=0x%08X)\n",
2677                           scratch, tmp);
2678                 r = -EINVAL;
2679         }
2680         amdgpu_gfx_scratch_free(adev, scratch);
2681
2682         return r;
2683 }
2684
2685 static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
2686 {
2687         struct amdgpu_device *adev = ring->adev;
2688         struct v9_mqd *mqd = ring->mqd_ptr;
2689         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
2690         uint32_t tmp;
2691
2692         mqd->header = 0xC0310800;
2693         mqd->compute_pipelinestat_enable = 0x00000001;
2694         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
2695         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
2696         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
2697         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
2698         mqd->compute_misc_reserved = 0x00000003;
2699
2700         mqd->dynamic_cu_mask_addr_lo =
2701                 lower_32_bits(ring->mqd_gpu_addr
2702                               + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
2703         mqd->dynamic_cu_mask_addr_hi =
2704                 upper_32_bits(ring->mqd_gpu_addr
2705                               + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
2706
2707         eop_base_addr = ring->eop_gpu_addr >> 8;
2708         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
2709         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
2710
2711         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2712         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
2713         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
2714                         (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1));
2715
2716         mqd->cp_hqd_eop_control = tmp;
2717
2718         /* enable doorbell? */
2719         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
2720
2721         if (ring->use_doorbell) {
2722                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2723                                     DOORBELL_OFFSET, ring->doorbell_index);
2724                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2725                                     DOORBELL_EN, 1);
2726                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2727                                     DOORBELL_SOURCE, 0);
2728                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2729                                     DOORBELL_HIT, 0);
2730         } else {
2731                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2732                                          DOORBELL_EN, 0);
2733         }
2734
2735         mqd->cp_hqd_pq_doorbell_control = tmp;
2736
2737         /* disable the queue if it's active */
2738         ring->wptr = 0;
2739         mqd->cp_hqd_dequeue_request = 0;
2740         mqd->cp_hqd_pq_rptr = 0;
2741         mqd->cp_hqd_pq_wptr_lo = 0;
2742         mqd->cp_hqd_pq_wptr_hi = 0;
2743
2744         /* set the pointer to the MQD */
2745         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
2746         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
2747
2748         /* set MQD vmid to 0 */
2749         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
2750         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
2751         mqd->cp_mqd_control = tmp;
2752
2753         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2754         hqd_gpu_addr = ring->gpu_addr >> 8;
2755         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
2756         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
2757
2758         /* set up the HQD, this is similar to CP_RB0_CNTL */
2759         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
2760         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
2761                             (order_base_2(ring->ring_size / 4) - 1));
2762         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
2763                         ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
2764 #ifdef __BIG_ENDIAN
2765         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
2766 #endif
2767         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
2768         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
2769         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
2770         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
2771         mqd->cp_hqd_pq_control = tmp;
2772
2773         /* set the wb address whether it's enabled or not */
2774         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2775         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
2776         mqd->cp_hqd_pq_rptr_report_addr_hi =
2777                 upper_32_bits(wb_gpu_addr) & 0xffff;
2778
2779         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2780         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2781         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
2782         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
2783
2784         tmp = 0;
2785         /* enable the doorbell if requested */
2786         if (ring->use_doorbell) {
2787                 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
2788                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2789                                 DOORBELL_OFFSET, ring->doorbell_index);
2790
2791                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2792                                          DOORBELL_EN, 1);
2793                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2794                                          DOORBELL_SOURCE, 0);
2795                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2796                                          DOORBELL_HIT, 0);
2797         }
2798
2799         mqd->cp_hqd_pq_doorbell_control = tmp;
2800
2801         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2802         ring->wptr = 0;
2803         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
2804
2805         /* set the vmid for the queue */
2806         mqd->cp_hqd_vmid = 0;
2807
2808         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
2809         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
2810         mqd->cp_hqd_persistent_state = tmp;
2811
2812         /* set MIN_IB_AVAIL_SIZE */
2813         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
2814         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
2815         mqd->cp_hqd_ib_control = tmp;
2816
2817         /* activate the queue */
2818         mqd->cp_hqd_active = 1;
2819
2820         return 0;
2821 }
2822
2823 static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
2824 {
2825         struct amdgpu_device *adev = ring->adev;
2826         struct v9_mqd *mqd = ring->mqd_ptr;
2827         int j;
2828
2829         /* disable wptr polling */
2830         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
2831
2832         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
2833                mqd->cp_hqd_eop_base_addr_lo);
2834         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
2835                mqd->cp_hqd_eop_base_addr_hi);
2836
2837         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2838         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
2839                mqd->cp_hqd_eop_control);
2840
2841         /* enable doorbell? */
2842         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
2843                mqd->cp_hqd_pq_doorbell_control);
2844
2845         /* disable the queue if it's active */
2846         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
2847                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
2848                 for (j = 0; j < adev->usec_timeout; j++) {
2849                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
2850                                 break;
2851                         udelay(1);
2852                 }
2853                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
2854                        mqd->cp_hqd_dequeue_request);
2855                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
2856                        mqd->cp_hqd_pq_rptr);
2857                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
2858                        mqd->cp_hqd_pq_wptr_lo);
2859                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
2860                        mqd->cp_hqd_pq_wptr_hi);
2861         }
2862
2863         /* set the pointer to the MQD */
2864         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
2865                mqd->cp_mqd_base_addr_lo);
2866         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
2867                mqd->cp_mqd_base_addr_hi);
2868
2869         /* set MQD vmid to 0 */
2870         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
2871                mqd->cp_mqd_control);
2872
2873         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2874         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
2875                mqd->cp_hqd_pq_base_lo);
2876         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
2877                mqd->cp_hqd_pq_base_hi);
2878
2879         /* set up the HQD, this is similar to CP_RB0_CNTL */
2880         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
2881                mqd->cp_hqd_pq_control);
2882
2883         /* set the wb address whether it's enabled or not */
2884         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
2885                                 mqd->cp_hqd_pq_rptr_report_addr_lo);
2886         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
2887                                 mqd->cp_hqd_pq_rptr_report_addr_hi);
2888
2889         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2890         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
2891                mqd->cp_hqd_pq_wptr_poll_addr_lo);
2892         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
2893                mqd->cp_hqd_pq_wptr_poll_addr_hi);
2894
2895         /* enable the doorbell if requested */
2896         if (ring->use_doorbell) {
2897                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
2898                                         (AMDGPU_DOORBELL64_KIQ *2) << 2);
2899                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
2900                                         (AMDGPU_DOORBELL64_USERQUEUE_END * 2) << 2);
2901         }
2902
2903         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
2904                mqd->cp_hqd_pq_doorbell_control);
2905
2906         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2907         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
2908                mqd->cp_hqd_pq_wptr_lo);
2909         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
2910                mqd->cp_hqd_pq_wptr_hi);
2911
2912         /* set the vmid for the queue */
2913         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
2914
2915         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
2916                mqd->cp_hqd_persistent_state);
2917
2918         /* activate the queue */
2919         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
2920                mqd->cp_hqd_active);
2921
2922         if (ring->use_doorbell)
2923                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
2924
2925         return 0;
2926 }
2927
2928 static int gfx_v9_0_kiq_fini_register(struct amdgpu_ring *ring)
2929 {
2930         struct amdgpu_device *adev = ring->adev;
2931         int j;
2932
2933         /* disable the queue if it's active */
2934         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
2935
2936                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
2937
2938                 for (j = 0; j < adev->usec_timeout; j++) {
2939                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
2940                                 break;
2941                         udelay(1);
2942                 }
2943
2944                 if (j == AMDGPU_MAX_USEC_TIMEOUT) {
2945                         DRM_DEBUG("KIQ dequeue request failed.\n");
2946
2947                         /* Manual disable if dequeue request times out */
2948                         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
2949                 }
2950
2951                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
2952                       0);
2953         }
2954
2955         WREG32_SOC15(GC, 0, mmCP_HQD_IQ_TIMER, 0);
2956         WREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL, 0);
2957         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 0);
2958         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000);
2959         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
2960         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 0);
2961         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0);
2962         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 0);
2963
2964         return 0;
2965 }
2966
2967 static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
2968 {
2969         struct amdgpu_device *adev = ring->adev;
2970         struct v9_mqd *mqd = ring->mqd_ptr;
2971         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
2972
2973         gfx_v9_0_kiq_setting(ring);
2974
2975         if (adev->in_gpu_reset) { /* for GPU_RESET case */
2976                 /* reset MQD to a clean status */
2977                 if (adev->gfx.mec.mqd_backup[mqd_idx])
2978                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
2979
2980                 /* reset ring buffer */
2981                 ring->wptr = 0;
2982                 amdgpu_ring_clear_ring(ring);
2983
2984                 mutex_lock(&adev->srbm_mutex);
2985                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2986                 gfx_v9_0_kiq_init_register(ring);
2987                 soc15_grbm_select(adev, 0, 0, 0, 0);
2988                 mutex_unlock(&adev->srbm_mutex);
2989         } else {
2990                 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
2991                 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
2992                 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
2993                 mutex_lock(&adev->srbm_mutex);
2994                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2995                 gfx_v9_0_mqd_init(ring);
2996                 gfx_v9_0_kiq_init_register(ring);
2997                 soc15_grbm_select(adev, 0, 0, 0, 0);
2998                 mutex_unlock(&adev->srbm_mutex);
2999
3000                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3001                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
3002         }
3003
3004         return 0;
3005 }
3006
3007 static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
3008 {
3009         struct amdgpu_device *adev = ring->adev;
3010         struct v9_mqd *mqd = ring->mqd_ptr;
3011         int mqd_idx = ring - &adev->gfx.compute_ring[0];
3012
3013         if (!adev->in_gpu_reset && !adev->gfx.in_suspend) {
3014                 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
3015                 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
3016                 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
3017                 mutex_lock(&adev->srbm_mutex);
3018                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3019                 gfx_v9_0_mqd_init(ring);
3020                 soc15_grbm_select(adev, 0, 0, 0, 0);
3021                 mutex_unlock(&adev->srbm_mutex);
3022
3023                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3024                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
3025         } else if (adev->in_gpu_reset) { /* for GPU_RESET case */
3026                 /* reset MQD to a clean status */
3027                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3028                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
3029
3030                 /* reset ring buffer */
3031                 ring->wptr = 0;
3032                 amdgpu_ring_clear_ring(ring);
3033         } else {
3034                 amdgpu_ring_clear_ring(ring);
3035         }
3036
3037         return 0;
3038 }
3039
3040 static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)
3041 {
3042         struct amdgpu_ring *ring = NULL;
3043         int r = 0, i;
3044
3045         gfx_v9_0_cp_compute_enable(adev, true);
3046
3047         ring = &adev->gfx.kiq.ring;
3048
3049         r = amdgpu_bo_reserve(ring->mqd_obj, false);
3050         if (unlikely(r != 0))
3051                 goto done;
3052
3053         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3054         if (!r) {
3055                 r = gfx_v9_0_kiq_init_queue(ring);
3056                 amdgpu_bo_kunmap(ring->mqd_obj);
3057                 ring->mqd_ptr = NULL;
3058         }
3059         amdgpu_bo_unreserve(ring->mqd_obj);
3060         if (r)
3061                 goto done;
3062
3063         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3064                 ring = &adev->gfx.compute_ring[i];
3065
3066                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3067                 if (unlikely(r != 0))
3068                         goto done;
3069                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3070                 if (!r) {
3071                         r = gfx_v9_0_kcq_init_queue(ring);
3072                         amdgpu_bo_kunmap(ring->mqd_obj);
3073                         ring->mqd_ptr = NULL;
3074                 }
3075                 amdgpu_bo_unreserve(ring->mqd_obj);
3076                 if (r)
3077                         goto done;
3078         }
3079
3080         r = gfx_v9_0_kiq_kcq_enable(adev);
3081 done:
3082         return r;
3083 }
3084
3085 static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
3086 {
3087         int r, i;
3088         struct amdgpu_ring *ring;
3089
3090         if (!(adev->flags & AMD_IS_APU))
3091                 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
3092
3093         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
3094                 /* legacy firmware loading */
3095                 r = gfx_v9_0_cp_gfx_load_microcode(adev);
3096                 if (r)
3097                         return r;
3098
3099                 r = gfx_v9_0_cp_compute_load_microcode(adev);
3100                 if (r)
3101                         return r;
3102         }
3103
3104         r = gfx_v9_0_cp_gfx_resume(adev);
3105         if (r)
3106                 return r;
3107
3108         r = gfx_v9_0_kiq_resume(adev);
3109         if (r)
3110                 return r;
3111
3112         ring = &adev->gfx.gfx_ring[0];
3113         r = amdgpu_ring_test_ring(ring);
3114         if (r) {
3115                 ring->ready = false;
3116                 return r;
3117         }
3118
3119         ring = &adev->gfx.kiq.ring;
3120         ring->ready = true;
3121         r = amdgpu_ring_test_ring(ring);
3122         if (r)
3123                 ring->ready = false;
3124
3125         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3126                 ring = &adev->gfx.compute_ring[i];
3127
3128                 ring->ready = true;
3129                 r = amdgpu_ring_test_ring(ring);
3130                 if (r)
3131                         ring->ready = false;
3132         }
3133
3134         gfx_v9_0_enable_gui_idle_interrupt(adev, true);
3135
3136         return 0;
3137 }
3138
3139 static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
3140 {
3141         gfx_v9_0_cp_gfx_enable(adev, enable);
3142         gfx_v9_0_cp_compute_enable(adev, enable);
3143 }
3144
3145 static int gfx_v9_0_hw_init(void *handle)
3146 {
3147         int r;
3148         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3149
3150         gfx_v9_0_init_golden_registers(adev);
3151
3152         gfx_v9_0_gpu_init(adev);
3153
3154         r = gfx_v9_0_csb_vram_pin(adev);
3155         if (r)
3156                 return r;
3157
3158         r = gfx_v9_0_rlc_resume(adev);
3159         if (r)
3160                 return r;
3161
3162         r = gfx_v9_0_cp_resume(adev);
3163         if (r)
3164                 return r;
3165
3166         r = gfx_v9_0_ngg_en(adev);
3167         if (r)
3168                 return r;
3169
3170         return r;
3171 }
3172
3173 static int gfx_v9_0_kcq_disable(struct amdgpu_ring *kiq_ring,struct amdgpu_ring *ring)
3174 {
3175         struct amdgpu_device *adev = kiq_ring->adev;
3176         uint32_t scratch, tmp = 0;
3177         int r, i;
3178
3179         r = amdgpu_gfx_scratch_get(adev, &scratch);
3180         if (r) {
3181                 DRM_ERROR("Failed to get scratch reg (%d).\n", r);
3182                 return r;
3183         }
3184         WREG32(scratch, 0xCAFEDEAD);
3185
3186         r = amdgpu_ring_alloc(kiq_ring, 10);
3187         if (r) {
3188                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
3189                 amdgpu_gfx_scratch_free(adev, scratch);
3190                 return r;
3191         }
3192
3193         /* unmap queues */
3194         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3195         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3196                                                 PACKET3_UNMAP_QUEUES_ACTION(1) | /* RESET_QUEUES */
3197                                                 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3198                                                 PACKET3_UNMAP_QUEUES_ENGINE_SEL(0) |
3199                                                 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3200         amdgpu_ring_write(kiq_ring, PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3201         amdgpu_ring_write(kiq_ring, 0);
3202         amdgpu_ring_write(kiq_ring, 0);
3203         amdgpu_ring_write(kiq_ring, 0);
3204         /* write to scratch for completion */
3205         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3206         amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
3207         amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
3208         amdgpu_ring_commit(kiq_ring);
3209
3210         for (i = 0; i < adev->usec_timeout; i++) {
3211                 tmp = RREG32(scratch);
3212                 if (tmp == 0xDEADBEEF)
3213                         break;
3214                 DRM_UDELAY(1);
3215         }
3216         if (i >= adev->usec_timeout) {
3217                 DRM_ERROR("KCQ disabled failed (scratch(0x%04X)=0x%08X)\n", scratch, tmp);
3218                 r = -EINVAL;
3219         }
3220         amdgpu_gfx_scratch_free(adev, scratch);
3221         return r;
3222 }
3223
3224 static int gfx_v9_0_hw_fini(void *handle)
3225 {
3226         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3227         int i;
3228
3229         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_GFX,
3230                                                AMD_PG_STATE_UNGATE);
3231
3232         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
3233         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
3234
3235         /* disable KCQ to avoid CPC touch memory not valid anymore */
3236         for (i = 0; i < adev->gfx.num_compute_rings; i++)
3237                 gfx_v9_0_kcq_disable(&adev->gfx.kiq.ring, &adev->gfx.compute_ring[i]);
3238
3239         if (amdgpu_sriov_vf(adev)) {
3240                 gfx_v9_0_cp_gfx_enable(adev, false);
3241                 /* must disable polling for SRIOV when hw finished, otherwise
3242                  * CPC engine may still keep fetching WB address which is already
3243                  * invalid after sw finished and trigger DMAR reading error in
3244                  * hypervisor side.
3245                  */
3246                 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3247                 return 0;
3248         }
3249
3250         /* Use deinitialize sequence from CAIL when unbinding device from driver,
3251          * otherwise KIQ is hanging when binding back
3252          */
3253         if (!adev->in_gpu_reset && !adev->gfx.in_suspend) {
3254                 mutex_lock(&adev->srbm_mutex);
3255                 soc15_grbm_select(adev, adev->gfx.kiq.ring.me,
3256                                 adev->gfx.kiq.ring.pipe,
3257                                 adev->gfx.kiq.ring.queue, 0);
3258                 gfx_v9_0_kiq_fini_register(&adev->gfx.kiq.ring);
3259                 soc15_grbm_select(adev, 0, 0, 0, 0);
3260                 mutex_unlock(&adev->srbm_mutex);
3261         }
3262
3263         gfx_v9_0_cp_enable(adev, false);
3264         gfx_v9_0_rlc_stop(adev);
3265
3266         gfx_v9_0_csb_vram_unpin(adev);
3267
3268         return 0;
3269 }
3270
3271 static int gfx_v9_0_suspend(void *handle)
3272 {
3273         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3274
3275         adev->gfx.in_suspend = true;
3276         return gfx_v9_0_hw_fini(adev);
3277 }
3278
3279 static int gfx_v9_0_resume(void *handle)
3280 {
3281         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3282         int r;
3283
3284         r = gfx_v9_0_hw_init(adev);
3285         adev->gfx.in_suspend = false;
3286         return r;
3287 }
3288
3289 static bool gfx_v9_0_is_idle(void *handle)
3290 {
3291         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3292
3293         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
3294                                 GRBM_STATUS, GUI_ACTIVE))
3295                 return false;
3296         else
3297                 return true;
3298 }
3299
3300 static int gfx_v9_0_wait_for_idle(void *handle)
3301 {
3302         unsigned i;
3303         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3304
3305         for (i = 0; i < adev->usec_timeout; i++) {
3306                 if (gfx_v9_0_is_idle(handle))
3307                         return 0;
3308                 udelay(1);
3309         }
3310         return -ETIMEDOUT;
3311 }
3312
3313 static int gfx_v9_0_soft_reset(void *handle)
3314 {
3315         u32 grbm_soft_reset = 0;
3316         u32 tmp;
3317         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3318
3319         /* GRBM_STATUS */
3320         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
3321         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
3322                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
3323                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
3324                    GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
3325                    GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
3326                    GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
3327                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3328                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3329                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3330                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
3331         }
3332
3333         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
3334                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3335                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3336         }
3337
3338         /* GRBM_STATUS2 */
3339         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
3340         if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
3341                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3342                                                 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
3343
3344
3345         if (grbm_soft_reset) {
3346                 /* stop the rlc */
3347                 gfx_v9_0_rlc_stop(adev);
3348
3349                 /* Disable GFX parsing/prefetching */
3350                 gfx_v9_0_cp_gfx_enable(adev, false);
3351
3352                 /* Disable MEC parsing/prefetching */
3353                 gfx_v9_0_cp_compute_enable(adev, false);
3354
3355                 if (grbm_soft_reset) {
3356                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3357                         tmp |= grbm_soft_reset;
3358                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3359                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3360                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3361
3362                         udelay(50);
3363
3364                         tmp &= ~grbm_soft_reset;
3365                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3366                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3367                 }
3368
3369                 /* Wait a little for things to settle down */
3370                 udelay(50);
3371         }
3372         return 0;
3373 }
3374
3375 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3376 {
3377         uint64_t clock;
3378
3379         mutex_lock(&adev->gfx.gpu_clock_mutex);
3380         WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3381         clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
3382                 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3383         mutex_unlock(&adev->gfx.gpu_clock_mutex);
3384         return clock;
3385 }
3386
3387 static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3388                                           uint32_t vmid,
3389                                           uint32_t gds_base, uint32_t gds_size,
3390                                           uint32_t gws_base, uint32_t gws_size,
3391                                           uint32_t oa_base, uint32_t oa_size)
3392 {
3393         struct amdgpu_device *adev = ring->adev;
3394
3395         gds_base = gds_base >> AMDGPU_GDS_SHIFT;
3396         gds_size = gds_size >> AMDGPU_GDS_SHIFT;
3397
3398         gws_base = gws_base >> AMDGPU_GWS_SHIFT;
3399         gws_size = gws_size >> AMDGPU_GWS_SHIFT;
3400
3401         oa_base = oa_base >> AMDGPU_OA_SHIFT;
3402         oa_size = oa_size >> AMDGPU_OA_SHIFT;
3403
3404         /* GDS Base */
3405         gfx_v9_0_write_data_to_reg(ring, 0, false,
3406                                    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
3407                                    gds_base);
3408
3409         /* GDS Size */
3410         gfx_v9_0_write_data_to_reg(ring, 0, false,
3411                                    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
3412                                    gds_size);
3413
3414         /* GWS */
3415         gfx_v9_0_write_data_to_reg(ring, 0, false,
3416                                    SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
3417                                    gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
3418
3419         /* OA */
3420         gfx_v9_0_write_data_to_reg(ring, 0, false,
3421                                    SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
3422                                    (1 << (oa_size + oa_base)) - (1 << oa_base));
3423 }
3424
3425 static int gfx_v9_0_early_init(void *handle)
3426 {
3427         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3428
3429         adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
3430         adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
3431         gfx_v9_0_set_ring_funcs(adev);
3432         gfx_v9_0_set_irq_funcs(adev);
3433         gfx_v9_0_set_gds_init(adev);
3434         gfx_v9_0_set_rlc_funcs(adev);
3435
3436         return 0;
3437 }
3438
3439 static int gfx_v9_0_late_init(void *handle)
3440 {
3441         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3442         int r;
3443
3444         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
3445         if (r)
3446                 return r;
3447
3448         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
3449         if (r)
3450                 return r;
3451
3452         return 0;
3453 }
3454
3455 static void gfx_v9_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
3456 {
3457         uint32_t rlc_setting, data;
3458         unsigned i;
3459
3460         if (adev->gfx.rlc.in_safe_mode)
3461                 return;
3462
3463         /* if RLC is not enabled, do nothing */
3464         rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
3465         if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3466                 return;
3467
3468         if (adev->cg_flags &
3469             (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG |
3470              AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3471                 data = RLC_SAFE_MODE__CMD_MASK;
3472                 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
3473                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
3474
3475                 /* wait for RLC_SAFE_MODE */
3476                 for (i = 0; i < adev->usec_timeout; i++) {
3477                         if (!REG_GET_FIELD(SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
3478                                 break;
3479                         udelay(1);
3480                 }
3481                 adev->gfx.rlc.in_safe_mode = true;
3482         }
3483 }
3484
3485 static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
3486 {
3487         uint32_t rlc_setting, data;
3488
3489         if (!adev->gfx.rlc.in_safe_mode)
3490                 return;
3491
3492         /* if RLC is not enabled, do nothing */
3493         rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
3494         if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3495                 return;
3496
3497         if (adev->cg_flags &
3498             (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) {
3499                 /*
3500                  * Try to exit safe mode only if it is already in safe
3501                  * mode.
3502                  */
3503                 data = RLC_SAFE_MODE__CMD_MASK;
3504                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
3505                 adev->gfx.rlc.in_safe_mode = false;
3506         }
3507 }
3508
3509 static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
3510                                                 bool enable)
3511 {
3512         gfx_v9_0_enter_rlc_safe_mode(adev);
3513
3514         if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
3515                 gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
3516                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
3517                         gfx_v9_0_enable_gfx_pipeline_powergating(adev, true);
3518         } else {
3519                 gfx_v9_0_enable_gfx_cg_power_gating(adev, false);
3520                 gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);
3521         }
3522
3523         gfx_v9_0_exit_rlc_safe_mode(adev);
3524 }
3525
3526 static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev,
3527                                                 bool enable)
3528 {
3529         /* TODO: double check if we need to perform under safe mode */
3530         /* gfx_v9_0_enter_rlc_safe_mode(adev); */
3531
3532         if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
3533                 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true);
3534         else
3535                 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false);
3536
3537         if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
3538                 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true);
3539         else
3540                 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false);
3541
3542         /* gfx_v9_0_exit_rlc_safe_mode(adev); */
3543 }
3544
3545 static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
3546                                                       bool enable)
3547 {
3548         uint32_t data, def;
3549
3550         /* It is disabled by HW by default */
3551         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3552                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
3553                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3554                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
3555                           RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3556                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3557                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3558
3559                 /* only for Vega10 & Raven1 */
3560                 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
3561
3562                 if (def != data)
3563                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3564
3565                 /* MGLS is a global flag to control all MGLS in GFX */
3566                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3567                         /* 2 - RLC memory Light sleep */
3568                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
3569                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
3570                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3571                                 if (def != data)
3572                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
3573                         }
3574                         /* 3 - CP memory Light sleep */
3575                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
3576                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
3577                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3578                                 if (def != data)
3579                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
3580                         }
3581                 }
3582         } else {
3583                 /* 1 - MGCG_OVERRIDE */
3584                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3585                 data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
3586                          RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
3587                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3588                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3589                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3590                 if (def != data)
3591                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3592
3593                 /* 2 - disable MGLS in RLC */
3594                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
3595                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3596                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3597                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
3598                 }
3599
3600                 /* 3 - disable MGLS in CP */
3601                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
3602                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3603                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3604                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
3605                 }
3606         }
3607 }
3608
3609 static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
3610                                            bool enable)
3611 {
3612         uint32_t data, def;
3613
3614         adev->gfx.rlc.funcs->enter_safe_mode(adev);
3615
3616         /* Enable 3D CGCG/CGLS */
3617         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3618                 /* write cmd to clear cgcg/cgls ov */
3619                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3620                 /* unset CGCG override */
3621                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
3622                 /* update CGCG and CGLS override bits */
3623                 if (def != data)
3624                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3625                 /* enable 3Dcgcg FSM(0x0020003f) */
3626                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
3627                 data = (0x2000 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3628                         RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
3629                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
3630                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3631                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
3632                 if (def != data)
3633                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
3634
3635                 /* set IDLE_POLL_COUNT(0x00900100) */
3636                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
3637                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3638                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3639                 if (def != data)
3640                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
3641         } else {
3642                 /* Disable CGCG/CGLS */
3643                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
3644                 /* disable cgcg, cgls should be disabled */
3645                 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
3646                           RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
3647                 /* disable cgcg and cgls in FSM */
3648                 if (def != data)
3649                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
3650         }
3651
3652         adev->gfx.rlc.funcs->exit_safe_mode(adev);
3653 }
3654
3655 static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
3656                                                       bool enable)
3657 {
3658         uint32_t def, data;
3659
3660         adev->gfx.rlc.funcs->enter_safe_mode(adev);
3661
3662         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
3663                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3664                 /* unset CGCG override */
3665                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
3666                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3667                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3668                 else
3669                         data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3670                 /* update CGCG and CGLS override bits */
3671                 if (def != data)
3672                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3673
3674                 /* enable cgcg FSM(0x0020003F) */
3675                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
3676                 data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3677                         RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
3678                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3679                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3680                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3681                 if (def != data)
3682                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
3683
3684                 /* set IDLE_POLL_COUNT(0x00900100) */
3685                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
3686                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3687                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3688                 if (def != data)
3689                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
3690         } else {
3691                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
3692                 /* reset CGCG/CGLS bits */
3693                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3694                 /* disable cgcg and cgls in FSM */
3695                 if (def != data)
3696                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
3697         }
3698
3699         adev->gfx.rlc.funcs->exit_safe_mode(adev);
3700 }
3701
3702 static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
3703                                             bool enable)
3704 {
3705         if (enable) {
3706                 /* CGCG/CGLS should be enabled after MGCG/MGLS
3707                  * ===  MGCG + MGLS ===
3708                  */
3709                 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3710                 /* ===  CGCG /CGLS for GFX 3D Only === */
3711                 gfx_v9_0_update_3d_clock_gating(adev, enable);
3712                 /* ===  CGCG + CGLS === */
3713                 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3714         } else {
3715                 /* CGCG/CGLS should be disabled before MGCG/MGLS
3716                  * ===  CGCG + CGLS ===
3717                  */
3718                 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3719                 /* ===  CGCG /CGLS for GFX 3D Only === */
3720                 gfx_v9_0_update_3d_clock_gating(adev, enable);
3721                 /* ===  MGCG + MGLS === */
3722                 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3723         }
3724         return 0;
3725 }
3726
3727 static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
3728         .enter_safe_mode = gfx_v9_0_enter_rlc_safe_mode,
3729         .exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode
3730 };
3731
3732 static int gfx_v9_0_set_powergating_state(void *handle,
3733                                           enum amd_powergating_state state)
3734 {
3735         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3736         bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
3737
3738         switch (adev->asic_type) {
3739         case CHIP_RAVEN:
3740                 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
3741                         gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
3742                         gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
3743                 } else {
3744                         gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
3745                         gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
3746                 }
3747
3748                 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
3749                         gfx_v9_0_enable_cp_power_gating(adev, true);
3750                 else
3751                         gfx_v9_0_enable_cp_power_gating(adev, false);
3752
3753                 /* update gfx cgpg state */
3754                 gfx_v9_0_update_gfx_cg_power_gating(adev, enable);
3755
3756                 /* update mgcg state */
3757                 gfx_v9_0_update_gfx_mg_power_gating(adev, enable);
3758
3759                 /* set gfx off through smu */
3760                 if (enable && adev->powerplay.pp_funcs->set_powergating_by_smu)
3761                         amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true);
3762                 break;
3763         default:
3764                 break;
3765         }
3766
3767         return 0;
3768 }
3769
3770 static int gfx_v9_0_set_clockgating_state(void *handle,
3771                                           enum amd_clockgating_state state)
3772 {
3773         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3774
3775         if (amdgpu_sriov_vf(adev))
3776                 return 0;
3777
3778         switch (adev->asic_type) {
3779         case CHIP_VEGA10:
3780         case CHIP_VEGA12:
3781         case CHIP_VEGA20:
3782         case CHIP_RAVEN:
3783                 gfx_v9_0_update_gfx_clock_gating(adev,
3784                                                  state == AMD_CG_STATE_GATE ? true : false);
3785                 break;
3786         default:
3787                 break;
3788         }
3789         return 0;
3790 }
3791
3792 static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
3793 {
3794         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3795         int data;
3796
3797         if (amdgpu_sriov_vf(adev))
3798                 *flags = 0;
3799
3800         /* AMD_CG_SUPPORT_GFX_MGCG */
3801         data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3802         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
3803                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
3804
3805         /* AMD_CG_SUPPORT_GFX_CGCG */
3806         data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
3807         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
3808                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
3809
3810         /* AMD_CG_SUPPORT_GFX_CGLS */
3811         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
3812                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
3813
3814         /* AMD_CG_SUPPORT_GFX_RLC_LS */
3815         data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
3816         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
3817                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
3818
3819         /* AMD_CG_SUPPORT_GFX_CP_LS */
3820         data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
3821         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
3822                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
3823
3824         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
3825         data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
3826         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
3827                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
3828
3829         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
3830         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
3831                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
3832 }
3833
3834 static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
3835 {
3836         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/
3837 }
3838
3839 static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
3840 {
3841         struct amdgpu_device *adev = ring->adev;
3842         u64 wptr;
3843
3844         /* XXX check if swapping is necessary on BE */
3845         if (ring->use_doorbell) {
3846                 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
3847         } else {
3848                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
3849                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
3850         }
3851
3852         return wptr;
3853 }
3854
3855 static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
3856 {
3857         struct amdgpu_device *adev = ring->adev;
3858
3859         if (ring->use_doorbell) {
3860                 /* XXX check if swapping is necessary on BE */
3861                 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
3862                 WDOORBELL64(ring->doorbell_index, ring->wptr);
3863         } else {
3864                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
3865                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
3866         }
3867 }
3868
3869 static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
3870 {
3871         struct amdgpu_device *adev = ring->adev;
3872         u32 ref_and_mask, reg_mem_engine;
3873         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;
3874
3875         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
3876                 switch (ring->me) {
3877                 case 1:
3878                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
3879                         break;
3880                 case 2:
3881                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
3882                         break;
3883                 default:
3884                         return;
3885                 }
3886                 reg_mem_engine = 0;
3887         } else {
3888                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
3889                 reg_mem_engine = 1; /* pfp */
3890         }
3891
3892         gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
3893                               adev->nbio_funcs->get_hdp_flush_req_offset(adev),
3894                               adev->nbio_funcs->get_hdp_flush_done_offset(adev),
3895                               ref_and_mask, ref_and_mask, 0x20);
3896 }
3897
3898 static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
3899                                       struct amdgpu_ib *ib,
3900                                       unsigned vmid, bool ctx_switch)
3901 {
3902         u32 header, control = 0;
3903
3904         if (ib->flags & AMDGPU_IB_FLAG_CE)
3905                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3906         else
3907                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3908
3909         control |= ib->length_dw | (vmid << 24);
3910
3911         if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
3912                 control |= INDIRECT_BUFFER_PRE_ENB(1);
3913
3914                 if (!(ib->flags & AMDGPU_IB_FLAG_CE))
3915                         gfx_v9_0_ring_emit_de_meta(ring);
3916         }
3917
3918         amdgpu_ring_write(ring, header);
3919         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3920         amdgpu_ring_write(ring,
3921 #ifdef __BIG_ENDIAN
3922                 (2 << 0) |
3923 #endif
3924                 lower_32_bits(ib->gpu_addr));
3925         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
3926         amdgpu_ring_write(ring, control);
3927 }
3928
3929 static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
3930                                           struct amdgpu_ib *ib,
3931                                           unsigned vmid, bool ctx_switch)
3932 {
3933         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
3934
3935         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3936         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3937         amdgpu_ring_write(ring,
3938 #ifdef __BIG_ENDIAN
3939                                 (2 << 0) |
3940 #endif
3941                                 lower_32_bits(ib->gpu_addr));
3942         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
3943         amdgpu_ring_write(ring, control);
3944 }
3945
3946 static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
3947                                      u64 seq, unsigned flags)
3948 {
3949         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
3950         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
3951         bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY;
3952
3953         /* RELEASE_MEM - flush caches, send int */
3954         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
3955         amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN |
3956                                                EOP_TC_NC_ACTION_EN) :
3957                                               (EOP_TCL1_ACTION_EN |
3958                                                EOP_TC_ACTION_EN |
3959                                                EOP_TC_WB_ACTION_EN |
3960                                                EOP_TC_MD_ACTION_EN)) |
3961                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3962                                  EVENT_INDEX(5)));
3963         amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
3964
3965         /*
3966          * the address should be Qword aligned if 64bit write, Dword
3967          * aligned if only send 32bit data low (discard data high)
3968          */
3969         if (write64bit)
3970                 BUG_ON(addr & 0x7);
3971         else
3972                 BUG_ON(addr & 0x3);
3973         amdgpu_ring_write(ring, lower_32_bits(addr));
3974         amdgpu_ring_write(ring, upper_32_bits(addr));
3975         amdgpu_ring_write(ring, lower_32_bits(seq));
3976         amdgpu_ring_write(ring, upper_32_bits(seq));
3977         amdgpu_ring_write(ring, 0);
3978 }
3979
3980 static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
3981 {
3982         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3983         uint32_t seq = ring->fence_drv.sync_seq;
3984         uint64_t addr = ring->fence_drv.gpu_addr;
3985
3986         gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0,
3987                               lower_32_bits(addr), upper_32_bits(addr),
3988                               seq, 0xffffffff, 4);
3989 }
3990
3991 static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3992                                         unsigned vmid, uint64_t pd_addr)
3993 {
3994         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
3995
3996         /* compute doesn't have PFP */
3997         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
3998                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3999                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
4000                 amdgpu_ring_write(ring, 0x0);
4001         }
4002 }
4003
4004 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
4005 {
4006         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */
4007 }
4008
4009 static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
4010 {
4011         u64 wptr;
4012
4013         /* XXX check if swapping is necessary on BE */
4014         if (ring->use_doorbell)
4015                 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
4016         else
4017                 BUG();
4018         return wptr;
4019 }
4020
4021 static void gfx_v9_0_ring_set_pipe_percent(struct amdgpu_ring *ring,
4022                                            bool acquire)
4023 {
4024         struct amdgpu_device *adev = ring->adev;
4025         int pipe_num, tmp, reg;
4026         int pipe_percent = acquire ? SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK : 0x1;
4027
4028         pipe_num = ring->me * adev->gfx.mec.num_pipe_per_mec + ring->pipe;
4029
4030         /* first me only has 2 entries, GFX and HP3D */
4031         if (ring->me > 0)
4032                 pipe_num -= 2;
4033
4034         reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_GFX) + pipe_num;
4035         tmp = RREG32(reg);
4036         tmp = REG_SET_FIELD(tmp, SPI_WCL_PIPE_PERCENT_GFX, VALUE, pipe_percent);
4037         WREG32(reg, tmp);
4038 }
4039
4040 static void gfx_v9_0_pipe_reserve_resources(struct amdgpu_device *adev,
4041                                             struct amdgpu_ring *ring,
4042                                             bool acquire)
4043 {
4044         int i, pipe;
4045         bool reserve;
4046         struct amdgpu_ring *iring;
4047
4048         mutex_lock(&adev->gfx.pipe_reserve_mutex);
4049         pipe = amdgpu_gfx_queue_to_bit(adev, ring->me, ring->pipe, 0);
4050         if (acquire)
4051                 set_bit(pipe, adev->gfx.pipe_reserve_bitmap);
4052         else
4053                 clear_bit(pipe, adev->gfx.pipe_reserve_bitmap);
4054
4055         if (!bitmap_weight(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES)) {
4056                 /* Clear all reservations - everyone reacquires all resources */
4057                 for (i = 0; i < adev->gfx.num_gfx_rings; ++i)
4058                         gfx_v9_0_ring_set_pipe_percent(&adev->gfx.gfx_ring[i],
4059                                                        true);
4060
4061                 for (i = 0; i < adev->gfx.num_compute_rings; ++i)
4062                         gfx_v9_0_ring_set_pipe_percent(&adev->gfx.compute_ring[i],
4063                                                        true);
4064         } else {
4065                 /* Lower all pipes without a current reservation */
4066                 for (i = 0; i < adev->gfx.num_gfx_rings; ++i) {
4067                         iring = &adev->gfx.gfx_ring[i];
4068                         pipe = amdgpu_gfx_queue_to_bit(adev,
4069                                                        iring->me,
4070                                                        iring->pipe,
4071                                                        0);
4072                         reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap);
4073                         gfx_v9_0_ring_set_pipe_percent(iring, reserve);
4074                 }
4075
4076                 for (i = 0; i < adev->gfx.num_compute_rings; ++i) {
4077                         iring = &adev->gfx.compute_ring[i];
4078                         pipe = amdgpu_gfx_queue_to_bit(adev,
4079                                                        iring->me,
4080                                                        iring->pipe,
4081                                                        0);
4082                         reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap);
4083                         gfx_v9_0_ring_set_pipe_percent(iring, reserve);
4084                 }
4085         }
4086
4087         mutex_unlock(&adev->gfx.pipe_reserve_mutex);
4088 }
4089
4090 static void gfx_v9_0_hqd_set_priority(struct amdgpu_device *adev,
4091                                       struct amdgpu_ring *ring,
4092                                       bool acquire)
4093 {
4094         uint32_t pipe_priority = acquire ? 0x2 : 0x0;
4095         uint32_t queue_priority = acquire ? 0xf : 0x0;
4096
4097         mutex_lock(&adev->srbm_mutex);
4098         soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4099
4100         WREG32_SOC15(GC, 0, mmCP_HQD_PIPE_PRIORITY, pipe_priority);
4101         WREG32_SOC15(GC, 0, mmCP_HQD_QUEUE_PRIORITY, queue_priority);
4102
4103         soc15_grbm_select(adev, 0, 0, 0, 0);
4104         mutex_unlock(&adev->srbm_mutex);
4105 }
4106
4107 static void gfx_v9_0_ring_set_priority_compute(struct amdgpu_ring *ring,
4108                                                enum drm_sched_priority priority)
4109 {
4110         struct amdgpu_device *adev = ring->adev;
4111         bool acquire = priority == DRM_SCHED_PRIORITY_HIGH_HW;
4112
4113         if (ring->funcs->type != AMDGPU_RING_TYPE_COMPUTE)
4114                 return;
4115
4116         gfx_v9_0_hqd_set_priority(adev, ring, acquire);
4117         gfx_v9_0_pipe_reserve_resources(adev, ring, acquire);
4118 }
4119
4120 static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
4121 {
4122         struct amdgpu_device *adev = ring->adev;
4123
4124         /* XXX check if swapping is necessary on BE */
4125         if (ring->use_doorbell) {
4126                 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
4127                 WDOORBELL64(ring->doorbell_index, ring->wptr);
4128         } else{
4129                 BUG(); /* only DOORBELL method supported on gfx9 now */
4130         }
4131 }
4132
4133 static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
4134                                          u64 seq, unsigned int flags)
4135 {
4136         struct amdgpu_device *adev = ring->adev;
4137
4138         /* we only allocate 32bit for each seq wb address */
4139         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
4140
4141         /* write fence seq to the "addr" */
4142         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4143         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4144                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
4145         amdgpu_ring_write(ring, lower_32_bits(addr));
4146         amdgpu_ring_write(ring, upper_32_bits(addr));
4147         amdgpu_ring_write(ring, lower_32_bits(seq));
4148
4149         if (flags & AMDGPU_FENCE_FLAG_INT) {
4150                 /* set register to trigger INT */
4151                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4152                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4153                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
4154                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
4155                 amdgpu_ring_write(ring, 0);
4156                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
4157         }
4158 }
4159
4160 static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring)
4161 {
4162         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4163         amdgpu_ring_write(ring, 0);
4164 }
4165
4166 static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
4167 {
4168         struct v9_ce_ib_state ce_payload = {0};
4169         uint64_t csa_addr;
4170         int cnt;
4171
4172         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
4173         csa_addr = amdgpu_csa_vaddr(ring->adev);
4174
4175         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
4176         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
4177                                  WRITE_DATA_DST_SEL(8) |
4178                                  WR_CONFIRM) |
4179                                  WRITE_DATA_CACHE_POLICY(0));
4180         amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
4181         amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
4182         amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2);
4183 }
4184
4185 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring)
4186 {
4187         struct v9_de_ib_state de_payload = {0};
4188         uint64_t csa_addr, gds_addr;
4189         int cnt;
4190
4191         csa_addr = amdgpu_csa_vaddr(ring->adev);
4192         gds_addr = csa_addr + 4096;
4193         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
4194         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
4195
4196         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
4197         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
4198         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
4199                                  WRITE_DATA_DST_SEL(8) |
4200                                  WR_CONFIRM) |
4201                                  WRITE_DATA_CACHE_POLICY(0));
4202         amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
4203         amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
4204         amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2);
4205 }
4206
4207 static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
4208 {
4209         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
4210         amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
4211 }
4212
4213 static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
4214 {
4215         uint32_t dw2 = 0;
4216
4217         if (amdgpu_sriov_vf(ring->adev))
4218                 gfx_v9_0_ring_emit_ce_meta(ring);
4219
4220         gfx_v9_0_ring_emit_tmz(ring, true);
4221
4222         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
4223         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
4224                 /* set load_global_config & load_global_uconfig */
4225                 dw2 |= 0x8001;
4226                 /* set load_cs_sh_regs */
4227                 dw2 |= 0x01000000;
4228                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
4229                 dw2 |= 0x10002;
4230
4231                 /* set load_ce_ram if preamble presented */
4232                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
4233                         dw2 |= 0x10000000;
4234         } else {
4235                 /* still load_ce_ram if this is the first time preamble presented
4236                  * although there is no context switch happens.
4237                  */
4238                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
4239                         dw2 |= 0x10000000;
4240         }
4241
4242         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4243         amdgpu_ring_write(ring, dw2);
4244         amdgpu_ring_write(ring, 0);
4245 }
4246
4247 static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
4248 {
4249         unsigned ret;
4250         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
4251         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
4252         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
4253         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
4254         ret = ring->wptr & ring->buf_mask;
4255         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
4256         return ret;
4257 }
4258
4259 static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
4260 {
4261         unsigned cur;
4262         BUG_ON(offset > ring->buf_mask);
4263         BUG_ON(ring->ring[offset] != 0x55aa55aa);
4264
4265         cur = (ring->wptr & ring->buf_mask) - 1;
4266         if (likely(cur > offset))
4267                 ring->ring[offset] = cur - offset;
4268         else
4269                 ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
4270 }
4271
4272 static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
4273 {
4274         struct amdgpu_device *adev = ring->adev;
4275
4276         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
4277         amdgpu_ring_write(ring, 0 |     /* src: register*/
4278                                 (5 << 8) |      /* dst: memory */
4279                                 (1 << 20));     /* write confirm */
4280         amdgpu_ring_write(ring, reg);
4281         amdgpu_ring_write(ring, 0);
4282         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
4283                                 adev->virt.reg_val_offs * 4));
4284         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
4285                                 adev->virt.reg_val_offs * 4));
4286 }
4287
4288 static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
4289                                     uint32_t val)
4290 {
4291         uint32_t cmd = 0;
4292
4293         switch (ring->funcs->type) {
4294         case AMDGPU_RING_TYPE_GFX:
4295                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
4296                 break;
4297         case AMDGPU_RING_TYPE_KIQ:
4298                 cmd = (1 << 16); /* no inc addr */
4299                 break;
4300         default:
4301                 cmd = WR_CONFIRM;
4302                 break;
4303         }
4304         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4305         amdgpu_ring_write(ring, cmd);
4306         amdgpu_ring_write(ring, reg);
4307         amdgpu_ring_write(ring, 0);
4308         amdgpu_ring_write(ring, val);
4309 }
4310
4311 static void gfx_v9_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
4312                                         uint32_t val, uint32_t mask)
4313 {
4314         gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
4315 }
4316
4317 static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
4318                                                   uint32_t reg0, uint32_t reg1,
4319                                                   uint32_t ref, uint32_t mask)
4320 {
4321         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
4322
4323         if (amdgpu_sriov_vf(ring->adev))
4324                 gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
4325                                       ref, mask, 0x20);
4326         else
4327                 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
4328                                                            ref, mask);
4329 }
4330
4331 static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4332                                                  enum amdgpu_interrupt_state state)
4333 {
4334         switch (state) {
4335         case AMDGPU_IRQ_STATE_DISABLE:
4336         case AMDGPU_IRQ_STATE_ENABLE:
4337                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4338                                TIME_STAMP_INT_ENABLE,
4339                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4340                 break;
4341         default:
4342                 break;
4343         }
4344 }
4345
4346 static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4347                                                      int me, int pipe,
4348                                                      enum amdgpu_interrupt_state state)
4349 {
4350         u32 mec_int_cntl, mec_int_cntl_reg;
4351
4352         /*
4353          * amdgpu controls only the first MEC. That's why this function only
4354          * handles the setting of interrupts for this specific MEC. All other
4355          * pipes' interrupts are set by amdkfd.
4356          */
4357
4358         if (me == 1) {
4359                 switch (pipe) {
4360                 case 0:
4361                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
4362                         break;
4363                 case 1:
4364                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
4365                         break;
4366                 case 2:
4367                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
4368                         break;
4369                 case 3:
4370                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
4371                         break;
4372                 default:
4373                         DRM_DEBUG("invalid pipe %d\n", pipe);
4374                         return;
4375                 }
4376         } else {
4377                 DRM_DEBUG("invalid me %d\n", me);
4378                 return;
4379         }
4380
4381         switch (state) {
4382         case AMDGPU_IRQ_STATE_DISABLE:
4383                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4384                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4385                                              TIME_STAMP_INT_ENABLE, 0);
4386                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4387                 break;
4388         case AMDGPU_IRQ_STATE_ENABLE:
4389                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4390                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4391                                              TIME_STAMP_INT_ENABLE, 1);
4392                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4393                 break;
4394         default:
4395                 break;
4396         }
4397 }
4398
4399 static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4400                                              struct amdgpu_irq_src *source,
4401                                              unsigned type,
4402                                              enum amdgpu_interrupt_state state)
4403 {
4404         switch (state) {
4405         case AMDGPU_IRQ_STATE_DISABLE:
4406         case AMDGPU_IRQ_STATE_ENABLE:
4407                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4408                                PRIV_REG_INT_ENABLE,
4409                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4410                 break;
4411         default:
4412                 break;
4413         }
4414
4415         return 0;
4416 }
4417
4418 static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4419                                               struct amdgpu_irq_src *source,
4420                                               unsigned type,
4421                                               enum amdgpu_interrupt_state state)
4422 {
4423         switch (state) {
4424         case AMDGPU_IRQ_STATE_DISABLE:
4425         case AMDGPU_IRQ_STATE_ENABLE:
4426                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4427                                PRIV_INSTR_INT_ENABLE,
4428                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4429         default:
4430                 break;
4431         }
4432
4433         return 0;
4434 }
4435
4436 static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4437                                             struct amdgpu_irq_src *src,
4438                                             unsigned type,
4439                                             enum amdgpu_interrupt_state state)
4440 {
4441         switch (type) {
4442         case AMDGPU_CP_IRQ_GFX_EOP:
4443                 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
4444                 break;
4445         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4446                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4447                 break;
4448         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4449                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4450                 break;
4451         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4452                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4453                 break;
4454         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4455                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4456                 break;
4457         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4458                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4459                 break;
4460         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4461                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4462                 break;
4463         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4464                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4465                 break;
4466         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4467                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4468                 break;
4469         default:
4470                 break;
4471         }
4472         return 0;
4473 }
4474
4475 static int gfx_v9_0_eop_irq(struct amdgpu_device *adev,
4476                             struct amdgpu_irq_src *source,
4477                             struct amdgpu_iv_entry *entry)
4478 {
4479         int i;
4480         u8 me_id, pipe_id, queue_id;
4481         struct amdgpu_ring *ring;
4482
4483         DRM_DEBUG("IH: CP EOP\n");
4484         me_id = (entry->ring_id & 0x0c) >> 2;
4485         pipe_id = (entry->ring_id & 0x03) >> 0;
4486         queue_id = (entry->ring_id & 0x70) >> 4;
4487
4488         switch (me_id) {
4489         case 0:
4490                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4491                 break;
4492         case 1:
4493         case 2:
4494                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4495                         ring = &adev->gfx.compute_ring[i];
4496                         /* Per-queue interrupt is supported for MEC starting from VI.
4497                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
4498                           */
4499                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4500                                 amdgpu_fence_process(ring);
4501                 }
4502                 break;
4503         }
4504         return 0;
4505 }
4506
4507 static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev,
4508                                  struct amdgpu_irq_src *source,
4509                                  struct amdgpu_iv_entry *entry)
4510 {
4511         DRM_ERROR("Illegal register access in command stream\n");
4512         schedule_work(&adev->reset_work);
4513         return 0;
4514 }
4515
4516 static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
4517                                   struct amdgpu_irq_src *source,
4518                                   struct amdgpu_iv_entry *entry)
4519 {
4520         DRM_ERROR("Illegal instruction in command stream\n");
4521         schedule_work(&adev->reset_work);
4522         return 0;
4523 }
4524
4525 static int gfx_v9_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
4526                                             struct amdgpu_irq_src *src,
4527                                             unsigned int type,
4528                                             enum amdgpu_interrupt_state state)
4529 {
4530         uint32_t tmp, target;
4531         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
4532
4533         if (ring->me == 1)
4534                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
4535         else
4536                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
4537         target += ring->pipe;
4538
4539         switch (type) {
4540         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
4541                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
4542                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
4543                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
4544                                                  GENERIC2_INT_ENABLE, 0);
4545                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
4546
4547                         tmp = RREG32(target);
4548                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
4549                                                  GENERIC2_INT_ENABLE, 0);
4550                         WREG32(target, tmp);
4551                 } else {
4552                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
4553                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
4554                                                  GENERIC2_INT_ENABLE, 1);
4555                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
4556
4557                         tmp = RREG32(target);
4558                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
4559                                                  GENERIC2_INT_ENABLE, 1);
4560                         WREG32(target, tmp);
4561                 }
4562                 break;
4563         default:
4564                 BUG(); /* kiq only support GENERIC2_INT now */
4565                 break;
4566         }
4567         return 0;
4568 }
4569
4570 static int gfx_v9_0_kiq_irq(struct amdgpu_device *adev,
4571                             struct amdgpu_irq_src *source,
4572                             struct amdgpu_iv_entry *entry)
4573 {
4574         u8 me_id, pipe_id, queue_id;
4575         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
4576
4577         me_id = (entry->ring_id & 0x0c) >> 2;
4578         pipe_id = (entry->ring_id & 0x03) >> 0;
4579         queue_id = (entry->ring_id & 0x70) >> 4;
4580         DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
4581                    me_id, pipe_id, queue_id);
4582
4583         amdgpu_fence_process(ring);
4584         return 0;
4585 }
4586
4587 static const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
4588         .name = "gfx_v9_0",
4589         .early_init = gfx_v9_0_early_init,
4590         .late_init = gfx_v9_0_late_init,
4591         .sw_init = gfx_v9_0_sw_init,
4592         .sw_fini = gfx_v9_0_sw_fini,
4593         .hw_init = gfx_v9_0_hw_init,
4594         .hw_fini = gfx_v9_0_hw_fini,
4595         .suspend = gfx_v9_0_suspend,
4596         .resume = gfx_v9_0_resume,
4597         .is_idle = gfx_v9_0_is_idle,
4598         .wait_for_idle = gfx_v9_0_wait_for_idle,
4599         .soft_reset = gfx_v9_0_soft_reset,
4600         .set_clockgating_state = gfx_v9_0_set_clockgating_state,
4601         .set_powergating_state = gfx_v9_0_set_powergating_state,
4602         .get_clockgating_state = gfx_v9_0_get_clockgating_state,
4603 };
4604
4605 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
4606         .type = AMDGPU_RING_TYPE_GFX,
4607         .align_mask = 0xff,
4608         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4609         .support_64bit_ptrs = true,
4610         .vmhub = AMDGPU_GFXHUB,
4611         .get_rptr = gfx_v9_0_ring_get_rptr_gfx,
4612         .get_wptr = gfx_v9_0_ring_get_wptr_gfx,
4613         .set_wptr = gfx_v9_0_ring_set_wptr_gfx,
4614         .emit_frame_size = /* totally 242 maximum if 16 IBs */
4615                 5 +  /* COND_EXEC */
4616                 7 +  /* PIPELINE_SYNC */
4617                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
4618                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
4619                 2 + /* VM_FLUSH */
4620                 8 +  /* FENCE for VM_FLUSH */
4621                 20 + /* GDS switch */
4622                 4 + /* double SWITCH_BUFFER,
4623                        the first COND_EXEC jump to the place just
4624                            prior to this double SWITCH_BUFFER  */
4625                 5 + /* COND_EXEC */
4626                 7 +      /*     HDP_flush */
4627                 4 +      /*     VGT_flush */
4628                 14 + /* CE_META */
4629                 31 + /* DE_META */
4630                 3 + /* CNTX_CTRL */
4631                 5 + /* HDP_INVL */
4632                 8 + 8 + /* FENCE x2 */
4633                 2, /* SWITCH_BUFFER */
4634         .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */
4635         .emit_ib = gfx_v9_0_ring_emit_ib_gfx,
4636         .emit_fence = gfx_v9_0_ring_emit_fence,
4637         .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4638         .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4639         .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4640         .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4641         .test_ring = gfx_v9_0_ring_test_ring,
4642         .test_ib = gfx_v9_0_ring_test_ib,
4643         .insert_nop = amdgpu_ring_insert_nop,
4644         .pad_ib = amdgpu_ring_generic_pad_ib,
4645         .emit_switch_buffer = gfx_v9_ring_emit_sb,
4646         .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,
4647         .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec,
4648         .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec,
4649         .emit_tmz = gfx_v9_0_ring_emit_tmz,
4650         .emit_wreg = gfx_v9_0_ring_emit_wreg,
4651         .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
4652         .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
4653 };
4654
4655 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
4656         .type = AMDGPU_RING_TYPE_COMPUTE,
4657         .align_mask = 0xff,
4658         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4659         .support_64bit_ptrs = true,
4660         .vmhub = AMDGPU_GFXHUB,
4661         .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4662         .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4663         .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4664         .emit_frame_size =
4665                 20 + /* gfx_v9_0_ring_emit_gds_switch */
4666                 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4667                 5 + /* hdp invalidate */
4668                 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
4669                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
4670                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
4671                 2 + /* gfx_v9_0_ring_emit_vm_flush */
4672                 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
4673         .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4674         .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4675         .emit_fence = gfx_v9_0_ring_emit_fence,
4676         .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4677         .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4678         .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4679         .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4680         .test_ring = gfx_v9_0_ring_test_ring,
4681         .test_ib = gfx_v9_0_ring_test_ib,
4682         .insert_nop = amdgpu_ring_insert_nop,
4683         .pad_ib = amdgpu_ring_generic_pad_ib,
4684         .set_priority = gfx_v9_0_ring_set_priority_compute,
4685         .emit_wreg = gfx_v9_0_ring_emit_wreg,
4686         .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
4687         .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
4688 };
4689
4690 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
4691         .type = AMDGPU_RING_TYPE_KIQ,
4692         .align_mask = 0xff,
4693         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4694         .support_64bit_ptrs = true,
4695         .vmhub = AMDGPU_GFXHUB,
4696         .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4697         .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4698         .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4699         .emit_frame_size =
4700                 20 + /* gfx_v9_0_ring_emit_gds_switch */
4701                 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4702                 5 + /* hdp invalidate */
4703                 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
4704                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
4705                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
4706                 2 + /* gfx_v9_0_ring_emit_vm_flush */
4707                 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */
4708         .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4709         .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4710         .emit_fence = gfx_v9_0_ring_emit_fence_kiq,
4711         .test_ring = gfx_v9_0_ring_test_ring,
4712         .test_ib = gfx_v9_0_ring_test_ib,
4713         .insert_nop = amdgpu_ring_insert_nop,
4714         .pad_ib = amdgpu_ring_generic_pad_ib,
4715         .emit_rreg = gfx_v9_0_ring_emit_rreg,
4716         .emit_wreg = gfx_v9_0_ring_emit_wreg,
4717         .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
4718         .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
4719 };
4720
4721 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)
4722 {
4723         int i;
4724
4725         adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq;
4726
4727         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4728                 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx;
4729
4730         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4731                 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute;
4732 }
4733
4734 static const struct amdgpu_irq_src_funcs gfx_v9_0_kiq_irq_funcs = {
4735         .set = gfx_v9_0_kiq_set_interrupt_state,
4736         .process = gfx_v9_0_kiq_irq,
4737 };
4738
4739 static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = {
4740         .set = gfx_v9_0_set_eop_interrupt_state,
4741         .process = gfx_v9_0_eop_irq,
4742 };
4743
4744 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = {
4745         .set = gfx_v9_0_set_priv_reg_fault_state,
4746         .process = gfx_v9_0_priv_reg_irq,
4747 };
4748
4749 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = {
4750         .set = gfx_v9_0_set_priv_inst_fault_state,
4751         .process = gfx_v9_0_priv_inst_irq,
4752 };
4753
4754 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)
4755 {
4756         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4757         adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs;
4758
4759         adev->gfx.priv_reg_irq.num_types = 1;
4760         adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs;
4761
4762         adev->gfx.priv_inst_irq.num_types = 1;
4763         adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs;
4764
4765         adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
4766         adev->gfx.kiq.irq.funcs = &gfx_v9_0_kiq_irq_funcs;
4767 }
4768
4769 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
4770 {
4771         switch (adev->asic_type) {
4772         case CHIP_VEGA10:
4773         case CHIP_VEGA12:
4774         case CHIP_VEGA20:
4775         case CHIP_RAVEN:
4776                 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
4777                 break;
4778         default:
4779                 break;
4780         }
4781 }
4782
4783 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
4784 {
4785         /* init asci gds info */
4786         adev->gds.mem.total_size = RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
4787         adev->gds.gws.total_size = 64;
4788         adev->gds.oa.total_size = 16;
4789
4790         if (adev->gds.mem.total_size == 64 * 1024) {
4791                 adev->gds.mem.gfx_partition_size = 4096;
4792                 adev->gds.mem.cs_partition_size = 4096;
4793
4794                 adev->gds.gws.gfx_partition_size = 4;
4795                 adev->gds.gws.cs_partition_size = 4;
4796
4797                 adev->gds.oa.gfx_partition_size = 4;
4798                 adev->gds.oa.cs_partition_size = 1;
4799         } else {
4800                 adev->gds.mem.gfx_partition_size = 1024;
4801                 adev->gds.mem.cs_partition_size = 1024;
4802
4803                 adev->gds.gws.gfx_partition_size = 16;
4804                 adev->gds.gws.cs_partition_size = 16;
4805
4806                 adev->gds.oa.gfx_partition_size = 4;
4807                 adev->gds.oa.cs_partition_size = 4;
4808         }
4809 }
4810
4811 static void gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
4812                                                  u32 bitmap)
4813 {
4814         u32 data;
4815
4816         if (!bitmap)
4817                 return;
4818
4819         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4820         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4821
4822         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
4823 }
4824
4825 static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)
4826 {
4827         u32 data, mask;
4828
4829         data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
4830         data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
4831
4832         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4833         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4834
4835         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
4836
4837         return (~data) & mask;
4838 }
4839
4840 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
4841                                  struct amdgpu_cu_info *cu_info)
4842 {
4843         int i, j, k, counter, active_cu_number = 0;
4844         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
4845         unsigned disable_masks[4 * 2];
4846
4847         if (!adev || !cu_info)
4848                 return -EINVAL;
4849
4850         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
4851
4852         mutex_lock(&adev->grbm_idx_mutex);
4853         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4854                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4855                         mask = 1;
4856                         ao_bitmap = 0;
4857                         counter = 0;
4858                         gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
4859                         if (i < 4 && j < 2)
4860                                 gfx_v9_0_set_user_cu_inactive_bitmap(
4861                                         adev, disable_masks[i * 2 + j]);
4862                         bitmap = gfx_v9_0_get_cu_active_bitmap(adev);
4863                         cu_info->bitmap[i][j] = bitmap;
4864
4865                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
4866                                 if (bitmap & mask) {
4867                                         if (counter < adev->gfx.config.max_cu_per_sh)
4868                                                 ao_bitmap |= mask;
4869                                         counter ++;
4870                                 }
4871                                 mask <<= 1;
4872                         }
4873                         active_cu_number += counter;
4874                         if (i < 2 && j < 2)
4875                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
4876                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
4877                 }
4878         }
4879         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4880         mutex_unlock(&adev->grbm_idx_mutex);
4881
4882         cu_info->number = active_cu_number;
4883         cu_info->ao_cu_mask = ao_cu_mask;
4884         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
4885
4886         return 0;
4887 }
4888
4889 const struct amdgpu_ip_block_version gfx_v9_0_ip_block =
4890 {
4891         .type = AMD_IP_BLOCK_TYPE_GFX,
4892         .major = 9,
4893         .minor = 0,
4894         .rev = 0,
4895         .funcs = &gfx_v9_0_ip_funcs,
4896 };