drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include "drmP.h"
  25 #include "amdgpu.h"
  26 #include "amdgpu_gfx.h"
  27 #include "soc15.h"
  28 #include "soc15d.h"
  29
  30 #include "vega10/soc15ip.h"
  31 #include "vega10/GC/gc_9_0_offset.h"
  32 #include "vega10/GC/gc_9_0_sh_mask.h"
  33 #include "vega10/vega10_enum.h"
  34 #include "vega10/HDP/hdp_4_0_offset.h"
  35
  36 #include "soc15_common.h"
  37 #include "clearstate_gfx9.h"
  38 #include "v9_structs.h"
  39
  40 #define GFX9_NUM_GFX_RINGS     1
  41 #define GFX9_MEC_HPD_SIZE 2048
  42 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
  43 #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L
  44 #define GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH 34
  45
  46 #define mmPWR_MISC_CNTL_STATUS                                  0x0183
  47 #define mmPWR_MISC_CNTL_STATUS_BASE_IDX                         0
  48 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT        0x0
  49 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT          0x1
  50 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK          0x00000001L
  51 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK            0x00000006L
  52
  53 MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
  54 MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
  55 MODULE_FIRMWARE("amdgpu/vega10_me.bin");
  56 MODULE_FIRMWARE("amdgpu/vega10_mec.bin");
  57 MODULE_FIRMWARE("amdgpu/vega10_mec2.bin");
  58 MODULE_FIRMWARE("amdgpu/vega10_rlc.bin");
  59
  60 MODULE_FIRMWARE("amdgpu/raven_ce.bin");
  61 MODULE_FIRMWARE("amdgpu/raven_pfp.bin");
  62 MODULE_FIRMWARE("amdgpu/raven_me.bin");
  63 MODULE_FIRMWARE("amdgpu/raven_mec.bin");
  64 MODULE_FIRMWARE("amdgpu/raven_mec2.bin");
  65 MODULE_FIRMWARE("amdgpu/raven_rlc.bin");
  66
  67 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
  68 {
  69         {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
  70                 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0)},
  71         {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE),
  72                 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1)},
  73         {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE),
  74                 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2)},
  75         {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE),
  76                 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3)},
  77         {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE),
  78                 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4)},
  79         {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE),
  80                 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5)},
  81         {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE),
  82                 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6)},
  83         {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE),
  84                 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7)},
  85         {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE),
  86                 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8)},
  87         {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE),
  88                 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9)},
  89         {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE),
  90                 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID10)},
  91         {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_SIZE),
  92                 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID11), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID11)},
  93         {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_SIZE),
  94                 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID12), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID12)},
  95         {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_SIZE),
  96                 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID13), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID13)},
  97         {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_SIZE),
  98                 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID14), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID14)},
  99         {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_SIZE),
 100                 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID15), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID15)}
 101 };
 102
 103 static const u32 golden_settings_gc_9_0[] =
 104 {
 105         SOC15_REG_OFFSET(GC, 0, mmCPC_UTCL1_CNTL), 0x08000000, 0x08000080,
 106         SOC15_REG_OFFSET(GC, 0, mmCPF_UTCL1_CNTL), 0x08000000, 0x08000080,
 107         SOC15_REG_OFFSET(GC, 0, mmCPG_UTCL1_CNTL), 0x08000000, 0x08000080,
 108         SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420,
 109         SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000,
 110         SOC15_REG_OFFSET(GC, 0, mmIA_UTCL1_CNTL), 0x08000000, 0x08000080,
 111         SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
 112         SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
 113         SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
 114         SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_0), 0x08000000, 0x08000080,
 115         SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_1), 0x08000000, 0x08000080,
 116         SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_2), 0x08000000, 0x08000080,
 117         SOC15_REG_OFFSET(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL), 0x08000000, 0x08000080,
 118         SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x08000000, 0x08000080,
 119         SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1), 0x0000000f, 0x01000107,
 120         SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000,
 121         SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x4a2c0e68,
 122         SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0xb5d3f197,
 123         SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION), 0x3fff3af3, 0x19200000,
 124         SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000003ff,
 125         SOC15_REG_OFFSET(GC, 0, mmWD_UTCL1_CNTL), 0x08000000, 0x08000080
 126 };
 127
 128 static const u32 golden_settings_gc_9_0_vg10[] =
 129 {
 130         SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0x0000f000, 0x00012107,
 131         SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000,
 132         SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x2a114042,
 133         SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x2a114042,
 134         SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0x00008000, 0x00048000,
 135         SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000,
 136         SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x00001800, 0x00000800
 137 };
 138
 139 static const u32 golden_settings_gc_9_1[] =
 140 {
 141         SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0xfffdf3cf, 0x00014104,
 142         SOC15_REG_OFFSET(GC, 0, mmCPC_UTCL1_CNTL), 0x08000000, 0x08000080,
 143         SOC15_REG_OFFSET(GC, 0, mmCPF_UTCL1_CNTL), 0x08000000, 0x08000080,
 144         SOC15_REG_OFFSET(GC, 0, mmCPG_UTCL1_CNTL), 0x08000000, 0x08000080,
 145         SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420,
 146         SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000,
 147         SOC15_REG_OFFSET(GC, 0, mmIA_UTCL1_CNTL), 0x08000000, 0x08000080,
 148         SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
 149         SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
 150         SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
 151         SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_0), 0x08000000, 0x08000080,
 152         SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_1), 0x08000000, 0x08000080,
 153         SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_2), 0x08000000, 0x08000080,
 154         SOC15_REG_OFFSET(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL), 0x08000000, 0x08000080,
 155         SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x08000000, 0x08000080,
 156         SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000,
 157         SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x00000000,
 158         SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0x00003120,
 159         SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION), 0x3fff3af3, 0x19200000,
 160         SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000000ff,
 161         SOC15_REG_OFFSET(GC, 0, mmWD_UTCL1_CNTL), 0x08000000, 0x08000080
 162 };
 163
 164 static const u32 golden_settings_gc_9_1_rv1[] =
 165 {
 166         SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000,
 167         SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x24000042,
 168         SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x24000042,
 169         SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0xffffffff, 0x04048000,
 170         SOC15_REG_OFFSET(GC, 0, mmPA_SC_MODE_CNTL_1), 0x06000000, 0x06000000,
 171         SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000,
 172         SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x01bd9f33, 0x00000800
 173 };
 174
 175 #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
 176 #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042
 177
 178 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
 179 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
 180 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev);
 181 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
 182 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
 183                                  struct amdgpu_cu_info *cu_info);
 184 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
 185 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
 186 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
 187
 188 static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
 189 {
 190         switch (adev->asic_type) {
 191         case CHIP_VEGA10:
 192                 amdgpu_program_register_sequence(adev,
 193                                                  golden_settings_gc_9_0,
 194                                                  (const u32)ARRAY_SIZE(golden_settings_gc_9_0));
 195                 amdgpu_program_register_sequence(adev,
 196                                                  golden_settings_gc_9_0_vg10,
 197                                                  (const u32)ARRAY_SIZE(golden_settings_gc_9_0_vg10));
 198                 break;
 199         case CHIP_RAVEN:
 200                 amdgpu_program_register_sequence(adev,
 201                                                  golden_settings_gc_9_1,
 202                                                  (const u32)ARRAY_SIZE(golden_settings_gc_9_1));
 203                 amdgpu_program_register_sequence(adev,
 204                                                  golden_settings_gc_9_1_rv1,
 205                                                  (const u32)ARRAY_SIZE(golden_settings_gc_9_1_rv1));
 206                 break;
 207         default:
 208                 break;
 209         }
 210 }
 211
 212 static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
 213 {
 214         adev->gfx.scratch.num_reg = 7;
 215         adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
 216         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
 217 }
 218
 219 static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
 220                                        bool wc, uint32_t reg, uint32_t val)
 221 {
 222         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
 223         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
 224                                 WRITE_DATA_DST_SEL(0) |
 225                                 (wc ? WR_CONFIRM : 0));
 226         amdgpu_ring_write(ring, reg);
 227         amdgpu_ring_write(ring, 0);
 228         amdgpu_ring_write(ring, val);
 229 }
 230
 231 static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
 232                                   int mem_space, int opt, uint32_t addr0,
 233                                   uint32_t addr1, uint32_t ref, uint32_t mask,
 234                                   uint32_t inv)
 235 {
 236         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
 237         amdgpu_ring_write(ring,
 238                                  /* memory (1) or register (0) */
 239                                  (WAIT_REG_MEM_MEM_SPACE(mem_space) |
 240                                  WAIT_REG_MEM_OPERATION(opt) | /* wait */
 241                                  WAIT_REG_MEM_FUNCTION(3) |  /* equal */
 242                                  WAIT_REG_MEM_ENGINE(eng_sel)));
 243
 244         if (mem_space)
 245                 BUG_ON(addr0 & 0x3); /* Dword align */
 246         amdgpu_ring_write(ring, addr0);
 247         amdgpu_ring_write(ring, addr1);
 248         amdgpu_ring_write(ring, ref);
 249         amdgpu_ring_write(ring, mask);
 250         amdgpu_ring_write(ring, inv); /* poll interval */
 251 }
 252
 253 static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring)
 254 {
 255         struct amdgpu_device *adev = ring->adev;
 256         uint32_t scratch;
 257         uint32_t tmp = 0;
 258         unsigned i;
 259         int r;
 260
 261         r = amdgpu_gfx_scratch_get(adev, &scratch);
 262         if (r) {
 263                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
 264                 return r;
 265         }
 266         WREG32(scratch, 0xCAFEDEAD);
 267         r = amdgpu_ring_alloc(ring, 3);
 268         if (r) {
 269                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 270                           ring->idx, r);
 271                 amdgpu_gfx_scratch_free(adev, scratch);
 272                 return r;
 273         }
 274         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
 275         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
 276         amdgpu_ring_write(ring, 0xDEADBEEF);
 277         amdgpu_ring_commit(ring);
 278
 279         for (i = 0; i < adev->usec_timeout; i++) {
 280                 tmp = RREG32(scratch);
 281                 if (tmp == 0xDEADBEEF)
 282                         break;
 283                 DRM_UDELAY(1);
 284         }
 285         if (i < adev->usec_timeout) {
 286                 DRM_INFO("ring test on %d succeeded in %d usecs\n",
 287                          ring->idx, i);
 288         } else {
 289                 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
 290                           ring->idx, scratch, tmp);
 291                 r = -EINVAL;
 292         }
 293         amdgpu_gfx_scratch_free(adev, scratch);
 294         return r;
 295 }
 296
 297 static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 298 {
 299         struct amdgpu_device *adev = ring->adev;
 300         struct amdgpu_ib ib;
 301         struct dma_fence *f = NULL;
 302         uint32_t scratch;
 303         uint32_t tmp = 0;
 304         long r;
 305
 306         r = amdgpu_gfx_scratch_get(adev, &scratch);
 307         if (r) {
 308                 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
 309                 return r;
 310         }
 311         WREG32(scratch, 0xCAFEDEAD);
 312         memset(&ib, 0, sizeof(ib));
 313         r = amdgpu_ib_get(adev, NULL, 256, &ib);
 314         if (r) {
 315                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 316                 goto err1;
 317         }
 318         ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
 319         ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
 320         ib.ptr[2] = 0xDEADBEEF;
 321         ib.length_dw = 3;
 322
 323         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 324         if (r)
 325                 goto err2;
 326
 327         r = dma_fence_wait_timeout(f, false, timeout);
 328         if (r == 0) {
 329                 DRM_ERROR("amdgpu: IB test timed out.\n");
 330                 r = -ETIMEDOUT;
 331                 goto err2;
 332         } else if (r < 0) {
 333                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 334                 goto err2;
 335         }
 336         tmp = RREG32(scratch);
 337         if (tmp == 0xDEADBEEF) {
 338                 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
 339                 r = 0;
 340         } else {
 341                 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
 342                           scratch, tmp);
 343                 r = -EINVAL;
 344         }
 345 err2:
 346         amdgpu_ib_free(adev, &ib, NULL);
 347         dma_fence_put(f);
 348 err1:
 349         amdgpu_gfx_scratch_free(adev, scratch);
 350         return r;
 351 }
 352
 353 static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
 354 {
 355         const char *chip_name;
 356         char fw_name[30];
 357         int err;
 358         struct amdgpu_firmware_info *info = NULL;
 359         const struct common_firmware_header *header = NULL;
 360         const struct gfx_firmware_header_v1_0 *cp_hdr;
 361         const struct rlc_firmware_header_v2_0 *rlc_hdr;
 362         unsigned int *tmp = NULL;
 363         unsigned int i = 0;
 364
 365         DRM_DEBUG("\n");
 366
 367         switch (adev->asic_type) {
 368         case CHIP_VEGA10:
 369                 chip_name = "vega10";
 370                 break;
 371         case CHIP_RAVEN:
 372                 chip_name = "raven";
 373                 break;
 374         default:
 375                 BUG();
 376         }
 377
 378         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
 379         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
 380         if (err)
 381                 goto out;
 382         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
 383         if (err)
 384                 goto out;
 385         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
 386         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 387         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 388
 389         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
 390         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
 391         if (err)
 392                 goto out;
 393         err = amdgpu_ucode_validate(adev->gfx.me_fw);
 394         if (err)
 395                 goto out;
 396         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
 397         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 398         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 399
 400         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
 401         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
 402         if (err)
 403                 goto out;
 404         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
 405         if (err)
 406                 goto out;
 407         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
 408         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 409         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 410
 411         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
 412         err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
 413         if (err)
 414                 goto out;
 415         err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
 416         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
 417         adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
 418         adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
 419         adev->gfx.rlc.save_and_restore_offset =
 420                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
 421         adev->gfx.rlc.clear_state_descriptor_offset =
 422                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
 423         adev->gfx.rlc.avail_scratch_ram_locations =
 424                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
 425         adev->gfx.rlc.reg_restore_list_size =
 426                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
 427         adev->gfx.rlc.reg_list_format_start =
 428                         le32_to_cpu(rlc_hdr->reg_list_format_start);
 429         adev->gfx.rlc.reg_list_format_separate_start =
 430                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
 431         adev->gfx.rlc.starting_offsets_start =
 432                         le32_to_cpu(rlc_hdr->starting_offsets_start);
 433         adev->gfx.rlc.reg_list_format_size_bytes =
 434                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
 435         adev->gfx.rlc.reg_list_size_bytes =
 436                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
 437         adev->gfx.rlc.register_list_format =
 438                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
 439                                 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
 440         if (!adev->gfx.rlc.register_list_format) {
 441                 err = -ENOMEM;
 442                 goto out;
 443         }
 444
 445         tmp = (unsigned int *)((uintptr_t)rlc_hdr +
 446                         le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
 447         for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
 448                 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
 449
 450         adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
 451
 452         tmp = (unsigned int *)((uintptr_t)rlc_hdr +
 453                         le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
 454         for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
 455                 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
 456
 457         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
 458         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
 459         if (err)
 460                 goto out;
 461         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
 462         if (err)
 463                 goto out;
 464         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
 465         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 466         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 467
 468
 469         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
 470         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
 471         if (!err) {
 472                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
 473                 if (err)
 474                         goto out;
 475                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
 476                 adev->gfx.mec2_fw->data;
 477                 adev->gfx.mec2_fw_version =
 478                 le32_to_cpu(cp_hdr->header.ucode_version);
 479                 adev->gfx.mec2_feature_version =
 480                 le32_to_cpu(cp_hdr->ucode_feature_version);
 481         } else {
 482                 err = 0;
 483                 adev->gfx.mec2_fw = NULL;
 484         }
 485
 486         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 487                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
 488                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
 489                 info->fw = adev->gfx.pfp_fw;
 490                 header = (const struct common_firmware_header *)info->fw->data;
 491                 adev->firmware.fw_size +=
 492                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 493
 494                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
 495                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
 496                 info->fw = adev->gfx.me_fw;
 497                 header = (const struct common_firmware_header *)info->fw->data;
 498                 adev->firmware.fw_size +=
 499                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 500
 501                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
 502                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
 503                 info->fw = adev->gfx.ce_fw;
 504                 header = (const struct common_firmware_header *)info->fw->data;
 505                 adev->firmware.fw_size +=
 506                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 507
 508                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
 509                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
 510                 info->fw = adev->gfx.rlc_fw;
 511                 header = (const struct common_firmware_header *)info->fw->data;
 512                 adev->firmware.fw_size +=
 513                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 514
 515                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
 516                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
 517                 info->fw = adev->gfx.mec_fw;
 518                 header = (const struct common_firmware_header *)info->fw->data;
 519                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
 520                 adev->firmware.fw_size +=
 521                         ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 522
 523                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
 524                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
 525                 info->fw = adev->gfx.mec_fw;
 526                 adev->firmware.fw_size +=
 527                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 528
 529                 if (adev->gfx.mec2_fw) {
 530                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
 531                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 532                         info->fw = adev->gfx.mec2_fw;
 533                         header = (const struct common_firmware_header *)info->fw->data;
 534                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
 535                         adev->firmware.fw_size +=
 536                                 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 537                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
 538                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
 539                         info->fw = adev->gfx.mec2_fw;
 540                         adev->firmware.fw_size +=
 541                                 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 542                 }
 543
 544         }
 545
 546 out:
 547         if (err) {
 548                 dev_err(adev->dev,
 549                         "gfx9: Failed to load firmware \"%s\"\n",
 550                         fw_name);
 551                 release_firmware(adev->gfx.pfp_fw);
 552                 adev->gfx.pfp_fw = NULL;
 553                 release_firmware(adev->gfx.me_fw);
 554                 adev->gfx.me_fw = NULL;
 555                 release_firmware(adev->gfx.ce_fw);
 556                 adev->gfx.ce_fw = NULL;
 557                 release_firmware(adev->gfx.rlc_fw);
 558                 adev->gfx.rlc_fw = NULL;
 559                 release_firmware(adev->gfx.mec_fw);
 560                 adev->gfx.mec_fw = NULL;
 561                 release_firmware(adev->gfx.mec2_fw);
 562                 adev->gfx.mec2_fw = NULL;
 563         }
 564         return err;
 565 }
 566
 567 static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
 568 {
 569         u32 count = 0;
 570         const struct cs_section_def *sect = NULL;
 571         const struct cs_extent_def *ext = NULL;
 572
 573         /* begin clear state */
 574         count += 2;
 575         /* context control state */
 576         count += 3;
 577
 578         for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
 579                 for (ext = sect->section; ext->extent != NULL; ++ext) {
 580                         if (sect->id == SECT_CONTEXT)
 581                                 count += 2 + ext->reg_count;
 582                         else
 583                                 return 0;
 584                 }
 585         }
 586
 587         /* end clear state */
 588         count += 2;
 589         /* clear state */
 590         count += 2;
 591
 592         return count;
 593 }
 594
 595 static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev,
 596                                     volatile u32 *buffer)
 597 {
 598         u32 count = 0, i;
 599         const struct cs_section_def *sect = NULL;
 600         const struct cs_extent_def *ext = NULL;
 601
 602         if (adev->gfx.rlc.cs_data == NULL)
 603                 return;
 604         if (buffer == NULL)
 605                 return;
 606
 607         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 608         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
 609
 610         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
 611         buffer[count++] = cpu_to_le32(0x80000000);
 612         buffer[count++] = cpu_to_le32(0x80000000);
 613
 614         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
 615                 for (ext = sect->section; ext->extent != NULL; ++ext) {
 616                         if (sect->id == SECT_CONTEXT) {
 617                                 buffer[count++] =
 618                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
 619                                 buffer[count++] = cpu_to_le32(ext->reg_index -
 620                                                 PACKET3_SET_CONTEXT_REG_START);
 621                                 for (i = 0; i < ext->reg_count; i++)
 622                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
 623                         } else {
 624                                 return;
 625                         }
 626                 }
 627         }
 628
 629         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 630         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
 631
 632         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
 633         buffer[count++] = cpu_to_le32(0);
 634 }
 635
 636 static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev)
 637 {
 638         uint32_t data = 0;
 639
 640         /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */
 641         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F);
 642         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7);
 643         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077);
 644         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16));
 645
 646         /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */
 647         WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000);
 648
 649         /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */
 650         WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500);
 651
 652         mutex_lock(&adev->grbm_idx_mutex);
 653         /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/
 654         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 655         WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff);
 656
 657         /* set mmRLC_LB_PARAMS = 0x003F_1006 */
 658         data |= (0x0003 << RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT) &
 659                 RLC_LB_PARAMS__FIFO_SAMPLES_MASK;
 660         data |= (0x0010 << RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT) &
 661                 RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK;
 662         data |= (0x033F << RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT) &
 663                 RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK;
 664         WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data);
 665
 666         /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */
 667         data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7);
 668         data &= 0x0000FFFF;
 669         data |= 0x00C00000;
 670         WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data);
 671
 672         /* set RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF */
 673         WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, 0xFFF);
 674
 675         /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved,
 676          * but used for RLC_LB_CNTL configuration */
 677         data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK;
 678         data |= (0x09 << RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT) &
 679                 RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK;
 680         data |= (0x80000 << RLC_LB_CNTL__RESERVED__SHIFT) &
 681                 RLC_LB_CNTL__RESERVED_MASK;
 682         WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data);
 683         mutex_unlock(&adev->grbm_idx_mutex);
 684 }
 685
 686 static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
 687 {
 688         uint32_t data = 0;
 689
 690         data = RREG32_SOC15(GC, 0, mmRLC_LB_CNTL);
 691         if (enable)
 692                 data |= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
 693         else
 694                 data &= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
 695         WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data);
 696 }
 697
 698 static void rv_init_cp_jump_table(struct amdgpu_device *adev)
 699 {
 700         const __le32 *fw_data;
 701         volatile u32 *dst_ptr;
 702         int me, i, max_me = 5;
 703         u32 bo_offset = 0;
 704         u32 table_offset, table_size;
 705
 706         /* write the cp table buffer */
 707         dst_ptr = adev->gfx.rlc.cp_table_ptr;
 708         for (me = 0; me < max_me; me++) {
 709                 if (me == 0) {
 710                         const struct gfx_firmware_header_v1_0 *hdr =
 711                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
 712                         fw_data = (const __le32 *)
 713                                 (adev->gfx.ce_fw->data +
 714                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 715                         table_offset = le32_to_cpu(hdr->jt_offset);
 716                         table_size = le32_to_cpu(hdr->jt_size);
 717                 } else if (me == 1) {
 718                         const struct gfx_firmware_header_v1_0 *hdr =
 719                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
 720                         fw_data = (const __le32 *)
 721                                 (adev->gfx.pfp_fw->data +
 722                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 723                         table_offset = le32_to_cpu(hdr->jt_offset);
 724                         table_size = le32_to_cpu(hdr->jt_size);
 725                 } else if (me == 2) {
 726                         const struct gfx_firmware_header_v1_0 *hdr =
 727                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
 728                         fw_data = (const __le32 *)
 729                                 (adev->gfx.me_fw->data +
 730                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 731                         table_offset = le32_to_cpu(hdr->jt_offset);
 732                         table_size = le32_to_cpu(hdr->jt_size);
 733                 } else if (me == 3) {
 734                         const struct gfx_firmware_header_v1_0 *hdr =
 735                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
 736                         fw_data = (const __le32 *)
 737                                 (adev->gfx.mec_fw->data +
 738                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 739                         table_offset = le32_to_cpu(hdr->jt_offset);
 740                         table_size = le32_to_cpu(hdr->jt_size);
 741                 } else  if (me == 4) {
 742                         const struct gfx_firmware_header_v1_0 *hdr =
 743                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
 744                         fw_data = (const __le32 *)
 745                                 (adev->gfx.mec2_fw->data +
 746                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 747                         table_offset = le32_to_cpu(hdr->jt_offset);
 748                         table_size = le32_to_cpu(hdr->jt_size);
 749                 }
 750
 751                 for (i = 0; i < table_size; i ++) {
 752                         dst_ptr[bo_offset + i] =
 753                                 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
 754                 }
 755
 756                 bo_offset += table_size;
 757         }
 758 }
 759
 760 static void gfx_v9_0_rlc_fini(struct amdgpu_device *adev)
 761 {
 762         /* clear state block */
 763         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
 764                         &adev->gfx.rlc.clear_state_gpu_addr,
 765                         (void **)&adev->gfx.rlc.cs_ptr);
 766
 767         /* jump table block */
 768         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
 769                         &adev->gfx.rlc.cp_table_gpu_addr,
 770                         (void **)&adev->gfx.rlc.cp_table_ptr);
 771 }
 772
 773 static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
 774 {
 775         volatile u32 *dst_ptr;
 776         u32 dws;
 777         const struct cs_section_def *cs_data;
 778         int r;
 779
 780         adev->gfx.rlc.cs_data = gfx9_cs_data;
 781
 782         cs_data = adev->gfx.rlc.cs_data;
 783
 784         if (cs_data) {
 785                 /* clear state block */
 786                 adev->gfx.rlc.clear_state_size = dws = gfx_v9_0_get_csb_size(adev);
 787                 if (adev->gfx.rlc.clear_state_obj == NULL) {
 788                         r = amdgpu_bo_create_kernel(adev, dws * 4, PAGE_SIZE,
 789                                                 AMDGPU_GEM_DOMAIN_VRAM,
 790                                                 &adev->gfx.rlc.clear_state_obj,
 791                                                 &adev->gfx.rlc.clear_state_gpu_addr,
 792                                                 (void **)&adev->gfx.rlc.cs_ptr);
 793                         if (r) {
 794                                 dev_err(adev->dev,
 795                                         "(%d) failed to create rlc csb bo\n", r);
 796                                 gfx_v9_0_rlc_fini(adev);
 797                                 return r;
 798                         }
 799                 }
 800                 /* set up the cs buffer */
 801                 dst_ptr = adev->gfx.rlc.cs_ptr;
 802                 gfx_v9_0_get_csb_buffer(adev, dst_ptr);
 803                 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
 804                 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
 805         }
 806
 807         if (adev->asic_type == CHIP_RAVEN) {
 808                 /* TODO: double check the cp_table_size for RV */
 809                 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
 810                 if (adev->gfx.rlc.cp_table_obj == NULL) {
 811                         r = amdgpu_bo_create_kernel(adev, adev->gfx.rlc.cp_table_size,
 812                                                 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 813                                                 &adev->gfx.rlc.cp_table_obj,
 814                                                 &adev->gfx.rlc.cp_table_gpu_addr,
 815                                                 (void **)&adev->gfx.rlc.cp_table_ptr);
 816                         if (r) {
 817                                 dev_err(adev->dev,
 818                                         "(%d) failed to create cp table bo\n", r);
 819                                 gfx_v9_0_rlc_fini(adev);
 820                                 return r;
 821                         }
 822                 }
 823
 824                 rv_init_cp_jump_table(adev);
 825                 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
 826                 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
 827
 828                 gfx_v9_0_init_lbpw(adev);
 829         }
 830
 831         return 0;
 832 }
 833
 834 static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
 835 {
 836         int r;
 837
 838         if (adev->gfx.mec.hpd_eop_obj) {
 839                 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, true);
 840                 if (unlikely(r != 0))
 841                         dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
 842                 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
 843                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
 844
 845                 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
 846                 adev->gfx.mec.hpd_eop_obj = NULL;
 847         }
 848         if (adev->gfx.mec.mec_fw_obj) {
 849                 r = amdgpu_bo_reserve(adev->gfx.mec.mec_fw_obj, true);
 850                 if (unlikely(r != 0))
 851                         dev_warn(adev->dev, "(%d) reserve mec firmware bo failed\n", r);
 852                 amdgpu_bo_unpin(adev->gfx.mec.mec_fw_obj);
 853                 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
 854
 855                 amdgpu_bo_unref(&adev->gfx.mec.mec_fw_obj);
 856                 adev->gfx.mec.mec_fw_obj = NULL;
 857         }
 858 }
 859
 860 static int gfx_v9_0_mec_init(struct amdgpu_device *adev)
 861 {
 862         int r;
 863         u32 *hpd;
 864         const __le32 *fw_data;
 865         unsigned fw_size;
 866         u32 *fw;
 867         size_t mec_hpd_size;
 868
 869         const struct gfx_firmware_header_v1_0 *mec_hdr;
 870
 871         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
 872
 873         switch (adev->asic_type) {
 874         case CHIP_VEGA10:
 875         case CHIP_RAVEN:
 876                 adev->gfx.mec.num_mec = 2;
 877                 break;
 878         default:
 879                 adev->gfx.mec.num_mec = 1;
 880                 break;
 881         }
 882
 883         adev->gfx.mec.num_pipe_per_mec = 4;
 884         adev->gfx.mec.num_queue_per_pipe = 8;
 885
 886         /* take ownership of the relevant compute queues */
 887         amdgpu_gfx_compute_queue_acquire(adev);
 888         mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE;
 889
 890         if (adev->gfx.mec.hpd_eop_obj == NULL) {
 891                 r = amdgpu_bo_create(adev,
 892                                      mec_hpd_size,
 893                                      PAGE_SIZE, true,
 894                                      AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
 895                                      &adev->gfx.mec.hpd_eop_obj);
 896                 if (r) {
 897                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
 898                         return r;
 899                 }
 900         }
 901
 902         r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
 903         if (unlikely(r != 0)) {
 904                 gfx_v9_0_mec_fini(adev);
 905                 return r;
 906         }
 907         r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
 908                           &adev->gfx.mec.hpd_eop_gpu_addr);
 909         if (r) {
 910                 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
 911                 gfx_v9_0_mec_fini(adev);
 912                 return r;
 913         }
 914         r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
 915         if (r) {
 916                 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
 917                 gfx_v9_0_mec_fini(adev);
 918                 return r;
 919         }
 920
 921         memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
 922
 923         amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
 924         amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
 925
 926         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
 927
 928         fw_data = (const __le32 *)
 929                 (adev->gfx.mec_fw->data +
 930                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
 931         fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
 932
 933         if (adev->gfx.mec.mec_fw_obj == NULL) {
 934                 r = amdgpu_bo_create(adev,
 935                         mec_hdr->header.ucode_size_bytes,
 936                         PAGE_SIZE, true,
 937                         AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
 938                         &adev->gfx.mec.mec_fw_obj);
 939                 if (r) {
 940                         dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r);
 941                         return r;
 942                 }
 943         }
 944
 945         r = amdgpu_bo_reserve(adev->gfx.mec.mec_fw_obj, false);
 946         if (unlikely(r != 0)) {
 947                 gfx_v9_0_mec_fini(adev);
 948                 return r;
 949         }
 950         r = amdgpu_bo_pin(adev->gfx.mec.mec_fw_obj, AMDGPU_GEM_DOMAIN_GTT,
 951                         &adev->gfx.mec.mec_fw_gpu_addr);
 952         if (r) {
 953                 dev_warn(adev->dev, "(%d) pin mec firmware bo failed\n", r);
 954                 gfx_v9_0_mec_fini(adev);
 955                 return r;
 956         }
 957         r = amdgpu_bo_kmap(adev->gfx.mec.mec_fw_obj, (void **)&fw);
 958         if (r) {
 959                 dev_warn(adev->dev, "(%d) map firmware bo failed\n", r);
 960                 gfx_v9_0_mec_fini(adev);
 961                 return r;
 962         }
 963         memcpy(fw, fw_data, fw_size);
 964
 965         amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
 966         amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
 967
 968
 969         return 0;
 970 }
 971
 972 static void gfx_v9_0_kiq_fini(struct amdgpu_device *adev)
 973 {
 974         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
 975
 976         amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq->eop_gpu_addr, NULL);
 977 }
 978
 979 static int gfx_v9_0_kiq_init(struct amdgpu_device *adev)
 980 {
 981         int r;
 982         u32 *hpd;
 983         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
 984
 985         r = amdgpu_bo_create_kernel(adev, GFX9_MEC_HPD_SIZE, PAGE_SIZE,
 986                                     AMDGPU_GEM_DOMAIN_GTT, &kiq->eop_obj,
 987                                     &kiq->eop_gpu_addr, (void **)&hpd);
 988         if (r) {
 989                 dev_warn(adev->dev, "failed to create KIQ bo (%d).\n", r);
 990                 return r;
 991         }
 992
 993         memset(hpd, 0, GFX9_MEC_HPD_SIZE);
 994
 995         r = amdgpu_bo_reserve(kiq->eop_obj, true);
 996         if (unlikely(r != 0))
 997                 dev_warn(adev->dev, "(%d) reserve kiq eop bo failed\n", r);
 998         amdgpu_bo_kunmap(kiq->eop_obj);
 999         amdgpu_bo_unreserve(kiq->eop_obj);
1000
1001         return 0;
1002 }
1003
1004 static int gfx_v9_0_kiq_acquire(struct amdgpu_device *adev,
1005                                  struct amdgpu_ring *ring)
1006 {
1007         int queue_bit;
1008         int mec, pipe, queue;
1009
1010         queue_bit = adev->gfx.mec.num_mec
1011                     * adev->gfx.mec.num_pipe_per_mec
1012                     * adev->gfx.mec.num_queue_per_pipe;
1013
1014         while (queue_bit-- >= 0) {
1015                 if (test_bit(queue_bit, adev->gfx.mec.queue_bitmap))
1016                         continue;
1017
1018                 amdgpu_bit_to_queue(adev, queue_bit, &mec, &pipe, &queue);
1019
1020                 /* Using pipes 2/3 from MEC 2 seems cause problems */
1021                 if (mec == 1 && pipe > 1)
1022                         continue;
1023
1024                 ring->me = mec + 1;
1025                 ring->pipe = pipe;
1026                 ring->queue = queue;
1027
1028                 return 0;
1029         }
1030
1031         dev_err(adev->dev, "Failed to find a queue for KIQ\n");
1032         return -EINVAL;
1033 }
1034
1035 static int gfx_v9_0_kiq_init_ring(struct amdgpu_device *adev,
1036                                   struct amdgpu_ring *ring,
1037                                   struct amdgpu_irq_src *irq)
1038 {
1039         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
1040         int r = 0;
1041
1042         mutex_init(&kiq->ring_mutex);
1043
1044         r = amdgpu_wb_get(adev, &adev->virt.reg_val_offs);
1045         if (r)
1046                 return r;
1047
1048         ring->adev = NULL;
1049         ring->ring_obj = NULL;
1050         ring->use_doorbell = true;
1051         ring->doorbell_index = AMDGPU_DOORBELL_KIQ;
1052
1053         r = gfx_v9_0_kiq_acquire(adev, ring);
1054         if (r)
1055                 return r;
1056
1057         ring->queue = 0;
1058         ring->eop_gpu_addr = kiq->eop_gpu_addr;
1059         sprintf(ring->name, "kiq %d.%d.%d", ring->me, ring->pipe, ring->queue);
1060         r = amdgpu_ring_init(adev, ring, 1024,
1061                              irq, AMDGPU_CP_KIQ_IRQ_DRIVER0);
1062         if (r)
1063                 dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r);
1064
1065         return r;
1066 }
1067 static void gfx_v9_0_kiq_free_ring(struct amdgpu_ring *ring,
1068                                    struct amdgpu_irq_src *irq)
1069 {
1070         amdgpu_wb_free(ring->adev, ring->adev->virt.reg_val_offs);
1071         amdgpu_ring_fini(ring);
1072 }
1073
1074 /* create MQD for each compute queue */
1075 static int gfx_v9_0_compute_mqd_sw_init(struct amdgpu_device *adev)
1076 {
1077         struct amdgpu_ring *ring = NULL;
1078         int r, i;
1079
1080         /* create MQD for KIQ */
1081         ring = &adev->gfx.kiq.ring;
1082         if (!ring->mqd_obj) {
1083                 r = amdgpu_bo_create_kernel(adev, sizeof(struct v9_mqd), PAGE_SIZE,
1084                                             AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
1085                                             &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr);
1086                 if (r) {
1087                         dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
1088                         return r;
1089                 }
1090
1091                 /* prepare MQD backup */
1092                 adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS] = kmalloc(sizeof(struct v9_mqd), GFP_KERNEL);
1093                 if (!adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS])
1094                         dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
1095         }
1096
1097         /* create MQD for each KCQ */
1098         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1099                 ring = &adev->gfx.compute_ring[i];
1100                 if (!ring->mqd_obj) {
1101                         r = amdgpu_bo_create_kernel(adev, sizeof(struct v9_mqd), PAGE_SIZE,
1102                                                     AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
1103                                                     &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr);
1104                         if (r) {
1105                                 dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
1106                                 return r;
1107                         }
1108
1109                         /* prepare MQD backup */
1110                         adev->gfx.mec.mqd_backup[i] = kmalloc(sizeof(struct v9_mqd), GFP_KERNEL);
1111                         if (!adev->gfx.mec.mqd_backup[i])
1112                                 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
1113                 }
1114         }
1115
1116         return 0;
1117 }
1118
1119 static void gfx_v9_0_compute_mqd_sw_fini(struct amdgpu_device *adev)
1120 {
1121         struct amdgpu_ring *ring = NULL;
1122         int i;
1123
1124         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1125                 ring = &adev->gfx.compute_ring[i];
1126                 kfree(adev->gfx.mec.mqd_backup[i]);
1127                 amdgpu_bo_free_kernel(&ring->mqd_obj, &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr);
1128         }
1129
1130         ring = &adev->gfx.kiq.ring;
1131         kfree(adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS]);
1132         amdgpu_bo_free_kernel(&ring->mqd_obj, &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr);
1133 }
1134
1135 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
1136 {
1137         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1138                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1139                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
1140                 (address << SQ_IND_INDEX__INDEX__SHIFT) |
1141                 (SQ_IND_INDEX__FORCE_READ_MASK));
1142         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1143 }
1144
1145 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
1146                            uint32_t wave, uint32_t thread,
1147                            uint32_t regno, uint32_t num, uint32_t *out)
1148 {
1149         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1150                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1151                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
1152                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
1153                 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
1154                 (SQ_IND_INDEX__FORCE_READ_MASK) |
1155                 (SQ_IND_INDEX__AUTO_INCR_MASK));
1156         while (num--)
1157                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1158 }
1159
1160 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
1161 {
1162         /* type 1 wave data */
1163         dst[(*no_fields)++] = 1;
1164         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
1165         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
1166         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
1167         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
1168         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
1169         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
1170         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
1171         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
1172         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
1173         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
1174         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
1175         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
1176         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
1177         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
1178 }
1179
1180 static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
1181                                      uint32_t wave, uint32_t start,
1182                                      uint32_t size, uint32_t *dst)
1183 {
1184         wave_read_regs(
1185                 adev, simd, wave, 0,
1186                 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
1187 }
1188
1189
1190 static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
1191         .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
1192         .select_se_sh = &gfx_v9_0_select_se_sh,
1193         .read_wave_data = &gfx_v9_0_read_wave_data,
1194         .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
1195 };
1196
1197 static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
1198 {
1199         u32 gb_addr_config;
1200
1201         adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
1202
1203         switch (adev->asic_type) {
1204         case CHIP_VEGA10:
1205                 adev->gfx.config.max_hw_contexts = 8;
1206                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1207                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1208                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1209                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1210                 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN;
1211                 break;
1212         case CHIP_RAVEN:
1213                 adev->gfx.config.max_hw_contexts = 8;
1214                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1215                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1216                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1217                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1218                 gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
1219                 break;
1220         default:
1221                 BUG();
1222                 break;
1223         }
1224
1225         adev->gfx.config.gb_addr_config = gb_addr_config;
1226
1227         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
1228                         REG_GET_FIELD(
1229                                         adev->gfx.config.gb_addr_config,
1230                                         GB_ADDR_CONFIG,
1231                                         NUM_PIPES);
1232
1233         adev->gfx.config.max_tile_pipes =
1234                 adev->gfx.config.gb_addr_config_fields.num_pipes;
1235
1236         adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
1237                         REG_GET_FIELD(
1238                                         adev->gfx.config.gb_addr_config,
1239                                         GB_ADDR_CONFIG,
1240                                         NUM_BANKS);
1241         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
1242                         REG_GET_FIELD(
1243                                         adev->gfx.config.gb_addr_config,
1244                                         GB_ADDR_CONFIG,
1245                                         MAX_COMPRESSED_FRAGS);
1246         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
1247                         REG_GET_FIELD(
1248                                         adev->gfx.config.gb_addr_config,
1249                                         GB_ADDR_CONFIG,
1250                                         NUM_RB_PER_SE);
1251         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
1252                         REG_GET_FIELD(
1253                                         adev->gfx.config.gb_addr_config,
1254                                         GB_ADDR_CONFIG,
1255                                         NUM_SHADER_ENGINES);
1256         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
1257                         REG_GET_FIELD(
1258                                         adev->gfx.config.gb_addr_config,
1259                                         GB_ADDR_CONFIG,
1260                                         PIPE_INTERLEAVE_SIZE));
1261 }
1262
1263 static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev,
1264                                    struct amdgpu_ngg_buf *ngg_buf,
1265                                    int size_se,
1266                                    int default_size_se)
1267 {
1268         int r;
1269
1270         if (size_se < 0) {
1271                 dev_err(adev->dev, "Buffer size is invalid: %d\n", size_se);
1272                 return -EINVAL;
1273         }
1274         size_se = size_se ? size_se : default_size_se;
1275
1276         ngg_buf->size = size_se * adev->gfx.config.max_shader_engines;
1277         r = amdgpu_bo_create_kernel(adev, ngg_buf->size,
1278                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1279                                     &ngg_buf->bo,
1280                                     &ngg_buf->gpu_addr,
1281                                     NULL);
1282         if (r) {
1283                 dev_err(adev->dev, "(%d) failed to create NGG buffer\n", r);
1284                 return r;
1285         }
1286         ngg_buf->bo_size = amdgpu_bo_size(ngg_buf->bo);
1287
1288         return r;
1289 }
1290
1291 static int gfx_v9_0_ngg_fini(struct amdgpu_device *adev)
1292 {
1293         int i;
1294
1295         for (i = 0; i < NGG_BUF_MAX; i++)
1296                 amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo,
1297                                       &adev->gfx.ngg.buf[i].gpu_addr,
1298                                       NULL);
1299
1300         memset(&adev->gfx.ngg.buf[0], 0,
1301                         sizeof(struct amdgpu_ngg_buf) * NGG_BUF_MAX);
1302
1303         adev->gfx.ngg.init = false;
1304
1305         return 0;
1306 }
1307
1308 static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
1309 {
1310         int r;
1311
1312         if (!amdgpu_ngg || adev->gfx.ngg.init == true)
1313                 return 0;
1314
1315         /* GDS reserve memory: 64 bytes alignment */
1316         adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
1317         adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;
1318         adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;
1319         adev->gfx.ngg.gds_reserve_addr = amdgpu_gds_reg_offset[0].mem_base;
1320         adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size;
1321
1322         /* Primitive Buffer */
1323         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM],
1324                                     amdgpu_prim_buf_per_se,
1325                                     64 * 1024);
1326         if (r) {
1327                 dev_err(adev->dev, "Failed to create Primitive Buffer\n");
1328                 goto err;
1329         }
1330
1331         /* Position Buffer */
1332         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_POS],
1333                                     amdgpu_pos_buf_per_se,
1334                                     256 * 1024);
1335         if (r) {
1336                 dev_err(adev->dev, "Failed to create Position Buffer\n");
1337                 goto err;
1338         }
1339
1340         /* Control Sideband */
1341         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_CNTL],
1342                                     amdgpu_cntl_sb_buf_per_se,
1343                                     256);
1344         if (r) {
1345                 dev_err(adev->dev, "Failed to create Control Sideband Buffer\n");
1346                 goto err;
1347         }
1348
1349         /* Parameter Cache, not created by default */
1350         if (amdgpu_param_buf_per_se <= 0)
1351                 goto out;
1352
1353         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PARAM],
1354                                     amdgpu_param_buf_per_se,
1355                                     512 * 1024);
1356         if (r) {
1357                 dev_err(adev->dev, "Failed to create Parameter Cache\n");
1358                 goto err;
1359         }
1360
1361 out:
1362         adev->gfx.ngg.init = true;
1363         return 0;
1364 err:
1365         gfx_v9_0_ngg_fini(adev);
1366         return r;
1367 }
1368
1369 static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
1370 {
1371         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
1372         int r;
1373         u32 data;
1374         u32 size;
1375         u32 base;
1376
1377         if (!amdgpu_ngg)
1378                 return 0;
1379
1380         /* Program buffer size */
1381         data = 0;
1382         size = adev->gfx.ngg.buf[NGG_PRIM].size / 256;
1383         data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE, size);
1384
1385         size = adev->gfx.ngg.buf[NGG_POS].size / 256;
1386         data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE, size);
1387
1388         WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_1, data);
1389
1390         data = 0;
1391         size = adev->gfx.ngg.buf[NGG_CNTL].size / 256;
1392         data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE, size);
1393
1394         size = adev->gfx.ngg.buf[NGG_PARAM].size / 1024;
1395         data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE, size);
1396
1397         WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_2, data);
1398
1399         /* Program buffer base address */
1400         base = lower_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
1401         data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base);
1402         WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE, data);
1403
1404         base = upper_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
1405         data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base);
1406         WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE_HI, data);
1407
1408         base = lower_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
1409         data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base);
1410         WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE, data);
1411
1412         base = upper_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
1413         data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base);
1414         WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE_HI, data);
1415
1416         base = lower_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
1417         data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base);
1418         WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE, data);
1419
1420         base = upper_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
1421         data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base);
1422         WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI, data);
1423
1424         /* Clear GDS reserved memory */
1425         r = amdgpu_ring_alloc(ring, 17);
1426         if (r) {
1427                 DRM_ERROR("amdgpu: NGG failed to lock ring %d (%d).\n",
1428                           ring->idx, r);
1429                 return r;
1430         }
1431
1432         gfx_v9_0_write_data_to_reg(ring, 0, false,
1433                                    amdgpu_gds_reg_offset[0].mem_size,
1434                                    (adev->gds.mem.total_size +
1435                                     adev->gfx.ngg.gds_reserve_size) >>
1436                                    AMDGPU_GDS_SHIFT);
1437
1438         amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
1439         amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
1440                                 PACKET3_DMA_DATA_SRC_SEL(2)));
1441         amdgpu_ring_write(ring, 0);
1442         amdgpu_ring_write(ring, 0);
1443         amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
1444         amdgpu_ring_write(ring, 0);
1445         amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size);
1446
1447
1448         gfx_v9_0_write_data_to_reg(ring, 0, false,
1449                                    amdgpu_gds_reg_offset[0].mem_size, 0);
1450
1451         amdgpu_ring_commit(ring);
1452
1453         return 0;
1454 }
1455
1456 static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1457                                       int mec, int pipe, int queue)
1458 {
1459         int r;
1460         unsigned irq_type;
1461         struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1462
1463         ring = &adev->gfx.compute_ring[ring_id];
1464
1465         /* mec0 is me1 */
1466         ring->me = mec + 1;
1467         ring->pipe = pipe;
1468         ring->queue = queue;
1469
1470         ring->ring_obj = NULL;
1471         ring->use_doorbell = true;
1472         ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + ring_id;
1473         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1474                                 + (ring_id * GFX9_MEC_HPD_SIZE);
1475         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1476
1477         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1478                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1479                 + ring->pipe;
1480
1481         /* type-2 packets are deprecated on MEC, use type-3 instead */
1482         r = amdgpu_ring_init(adev, ring, 1024,
1483                              &adev->gfx.eop_irq, irq_type);
1484         if (r)
1485                 return r;
1486
1487
1488         return 0;
1489 }
1490
1491 static int gfx_v9_0_sw_init(void *handle)
1492 {
1493         int i, j, k, r, ring_id;
1494         struct amdgpu_ring *ring;
1495         struct amdgpu_kiq *kiq;
1496         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1497
1498         /* KIQ event */
1499         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 178, &adev->gfx.kiq.irq);
1500         if (r)
1501                 return r;
1502
1503         /* EOP Event */
1504         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 181, &adev->gfx.eop_irq);
1505         if (r)
1506                 return r;
1507
1508         /* Privileged reg */
1509         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 184,
1510                               &adev->gfx.priv_reg_irq);
1511         if (r)
1512                 return r;
1513
1514         /* Privileged inst */
1515         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 185,
1516                               &adev->gfx.priv_inst_irq);
1517         if (r)
1518                 return r;
1519
1520         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1521
1522         gfx_v9_0_scratch_init(adev);
1523
1524         r = gfx_v9_0_init_microcode(adev);
1525         if (r) {
1526                 DRM_ERROR("Failed to load gfx firmware!\n");
1527                 return r;
1528         }
1529
1530         r = gfx_v9_0_rlc_init(adev);
1531         if (r) {
1532                 DRM_ERROR("Failed to init rlc BOs!\n");
1533                 return r;
1534         }
1535
1536         r = gfx_v9_0_mec_init(adev);
1537         if (r) {
1538                 DRM_ERROR("Failed to init MEC BOs!\n");
1539                 return r;
1540         }
1541
1542         /* set up the gfx ring */
1543         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
1544                 ring = &adev->gfx.gfx_ring[i];
1545                 ring->ring_obj = NULL;
1546                 sprintf(ring->name, "gfx");
1547                 ring->use_doorbell = true;
1548                 ring->doorbell_index = AMDGPU_DOORBELL64_GFX_RING0 << 1;
1549                 r = amdgpu_ring_init(adev, ring, 1024,
1550                                      &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
1551                 if (r)
1552                         return r;
1553         }
1554
1555         /* set up the compute queues - allocate horizontally across pipes */
1556         ring_id = 0;
1557         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1558                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1559                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
1560                                 if (!amdgpu_is_mec_queue_enabled(adev, i, k, j))
1561                                         continue;
1562
1563                                 r = gfx_v9_0_compute_ring_init(adev,
1564                                                                ring_id,
1565                                                                i, k, j);
1566                                 if (r)
1567                                         return r;
1568
1569                                 ring_id++;
1570                         }
1571                 }
1572         }
1573
1574         r = gfx_v9_0_kiq_init(adev);
1575         if (r) {
1576                 DRM_ERROR("Failed to init KIQ BOs!\n");
1577                 return r;
1578         }
1579
1580         kiq = &adev->gfx.kiq;
1581         r = gfx_v9_0_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
1582         if (r)
1583                 return r;
1584
1585         /* create MQD for all compute queues as wel as KIQ for SRIOV case */
1586         r = gfx_v9_0_compute_mqd_sw_init(adev);
1587         if (r)
1588                 return r;
1589
1590         /* reserve GDS, GWS and OA resource for gfx */
1591         r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
1592                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
1593                                     &adev->gds.gds_gfx_bo, NULL, NULL);
1594         if (r)
1595                 return r;
1596
1597         r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
1598                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
1599                                     &adev->gds.gws_gfx_bo, NULL, NULL);
1600         if (r)
1601                 return r;
1602
1603         r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
1604                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
1605                                     &adev->gds.oa_gfx_bo, NULL, NULL);
1606         if (r)
1607                 return r;
1608
1609         adev->gfx.ce_ram_size = 0x8000;
1610
1611         gfx_v9_0_gpu_early_init(adev);
1612
1613         r = gfx_v9_0_ngg_init(adev);
1614         if (r)
1615                 return r;
1616
1617         return 0;
1618 }
1619
1620
1621 static int gfx_v9_0_sw_fini(void *handle)
1622 {
1623         int i;
1624         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1625
1626         amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
1627         amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
1628         amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
1629
1630         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1631                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1632         for (i = 0; i < adev->gfx.num_compute_rings; i++)
1633                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1634
1635         gfx_v9_0_compute_mqd_sw_fini(adev);
1636         gfx_v9_0_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
1637         gfx_v9_0_kiq_fini(adev);
1638
1639         gfx_v9_0_mec_fini(adev);
1640         gfx_v9_0_ngg_fini(adev);
1641
1642         return 0;
1643 }
1644
1645
1646 static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev)
1647 {
1648         /* TODO */
1649 }
1650
1651 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance)
1652 {
1653         u32 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1654
1655         if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) {
1656                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1657                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1658         } else if (se_num == 0xffffffff) {
1659                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1660                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1661         } else if (sh_num == 0xffffffff) {
1662                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1663                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1664         } else {
1665                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1666                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1667         }
1668         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
1669 }
1670
1671 static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1672 {
1673         u32 data, mask;
1674
1675         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
1676         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
1677
1678         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1679         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1680
1681         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1682                                          adev->gfx.config.max_sh_per_se);
1683
1684         return (~data) & mask;
1685 }
1686
1687 static void gfx_v9_0_setup_rb(struct amdgpu_device *adev)
1688 {
1689         int i, j;
1690         u32 data;
1691         u32 active_rbs = 0;
1692         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1693                                         adev->gfx.config.max_sh_per_se;
1694
1695         mutex_lock(&adev->grbm_idx_mutex);
1696         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1697                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1698                         gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1699                         data = gfx_v9_0_get_rb_active_bitmap(adev);
1700                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1701                                                rb_bitmap_width_per_sh);
1702                 }
1703         }
1704         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1705         mutex_unlock(&adev->grbm_idx_mutex);
1706
1707         adev->gfx.config.backend_enable_mask = active_rbs;
1708         adev->gfx.config.num_rbs = hweight32(active_rbs);
1709 }
1710
1711 #define DEFAULT_SH_MEM_BASES    (0x6000)
1712 #define FIRST_COMPUTE_VMID      (8)
1713 #define LAST_COMPUTE_VMID       (16)
1714 static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
1715 {
1716         int i;
1717         uint32_t sh_mem_config;
1718         uint32_t sh_mem_bases;
1719
1720         /*
1721          * Configure apertures:
1722          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
1723          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
1724          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
1725          */
1726         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1727
1728         sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
1729                         SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1730                         SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
1731
1732         mutex_lock(&adev->srbm_mutex);
1733         for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1734                 soc15_grbm_select(adev, 0, 0, 0, i);
1735                 /* CP and shaders */
1736                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
1737                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
1738         }
1739         soc15_grbm_select(adev, 0, 0, 0, 0);
1740         mutex_unlock(&adev->srbm_mutex);
1741 }
1742
1743 static void gfx_v9_0_gpu_init(struct amdgpu_device *adev)
1744 {
1745         u32 tmp;
1746         int i;
1747
1748         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
1749
1750         gfx_v9_0_tiling_mode_table_init(adev);
1751
1752         gfx_v9_0_setup_rb(adev);
1753         gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);
1754
1755         /* XXX SH_MEM regs */
1756         /* where to put LDS, scratch, GPUVM in FSA64 space */
1757         mutex_lock(&adev->srbm_mutex);
1758         for (i = 0; i < 16; i++) {
1759                 soc15_grbm_select(adev, 0, 0, 0, i);
1760                 /* CP and shaders */
1761                 tmp = 0;
1762                 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
1763                                     SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1764                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
1765                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0);
1766         }
1767         soc15_grbm_select(adev, 0, 0, 0, 0);
1768
1769         mutex_unlock(&adev->srbm_mutex);
1770
1771         gfx_v9_0_init_compute_vmid(adev);
1772
1773         mutex_lock(&adev->grbm_idx_mutex);
1774         /*
1775          * making sure that the following register writes will be broadcasted
1776          * to all the shaders
1777          */
1778         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1779
1780         WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE,
1781                    (adev->gfx.config.sc_prim_fifo_size_frontend <<
1782                         PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1783                    (adev->gfx.config.sc_prim_fifo_size_backend <<
1784                         PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1785                    (adev->gfx.config.sc_hiz_tile_fifo_size <<
1786                         PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1787                    (adev->gfx.config.sc_earlyz_tile_fifo_size <<
1788                         PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
1789         mutex_unlock(&adev->grbm_idx_mutex);
1790
1791 }
1792
1793 static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
1794 {
1795         u32 i, j, k;
1796         u32 mask;
1797
1798         mutex_lock(&adev->grbm_idx_mutex);
1799         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1800                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1801                         gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1802                         for (k = 0; k < adev->usec_timeout; k++) {
1803                                 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0)
1804                                         break;
1805                                 udelay(1);
1806                         }
1807                 }
1808         }
1809         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1810         mutex_unlock(&adev->grbm_idx_mutex);
1811
1812         mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
1813                 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
1814                 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
1815                 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
1816         for (k = 0; k < adev->usec_timeout; k++) {
1817                 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
1818                         break;
1819                 udelay(1);
1820         }
1821 }
1822
1823 static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1824                                                bool enable)
1825 {
1826         u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
1827
1828         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
1829         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
1830         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
1831         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
1832
1833         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
1834 }
1835
1836 static void gfx_v9_0_init_csb(struct amdgpu_device *adev)
1837 {
1838         /* csib */
1839         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI),
1840                         adev->gfx.rlc.clear_state_gpu_addr >> 32);
1841         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO),
1842                         adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
1843         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH),
1844                         adev->gfx.rlc.clear_state_size);
1845 }
1846
1847 static void gfx_v9_0_parse_ind_reg_list(int *register_list_format,
1848                                 int indirect_offset,
1849                                 int list_size,
1850                                 int *unique_indirect_regs,
1851                                 int *unique_indirect_reg_count,
1852                                 int max_indirect_reg_count,
1853                                 int *indirect_start_offsets,
1854                                 int *indirect_start_offsets_count,
1855                                 int max_indirect_start_offsets_count)
1856 {
1857         int idx;
1858         bool new_entry = true;
1859
1860         for (; indirect_offset < list_size; indirect_offset++) {
1861
1862                 if (new_entry) {
1863                         new_entry = false;
1864                         indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset;
1865                         *indirect_start_offsets_count = *indirect_start_offsets_count + 1;
1866                         BUG_ON(*indirect_start_offsets_count >= max_indirect_start_offsets_count);
1867                 }
1868
1869                 if (register_list_format[indirect_offset] == 0xFFFFFFFF) {
1870                         new_entry = true;
1871                         continue;
1872                 }
1873
1874                 indirect_offset += 2;
1875
1876                 /* look for the matching indice */
1877                 for (idx = 0; idx < *unique_indirect_reg_count; idx++) {
1878                         if (unique_indirect_regs[idx] ==
1879                                 register_list_format[indirect_offset])
1880                                 break;
1881                 }
1882
1883                 if (idx >= *unique_indirect_reg_count) {
1884                         unique_indirect_regs[*unique_indirect_reg_count] =
1885                                 register_list_format[indirect_offset];
1886                         idx = *unique_indirect_reg_count;
1887                         *unique_indirect_reg_count = *unique_indirect_reg_count + 1;
1888                         BUG_ON(*unique_indirect_reg_count >= max_indirect_reg_count);
1889                 }
1890
1891                 register_list_format[indirect_offset] = idx;
1892         }
1893 }
1894
1895 static int gfx_v9_0_init_rlc_save_restore_list(struct amdgpu_device *adev)
1896 {
1897         int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
1898         int unique_indirect_reg_count = 0;
1899
1900         int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
1901         int indirect_start_offsets_count = 0;
1902
1903         int list_size = 0;
1904         int i = 0;
1905         u32 tmp = 0;
1906
1907         u32 *register_list_format =
1908                 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
1909         if (!register_list_format)
1910                 return -ENOMEM;
1911         memcpy(register_list_format, adev->gfx.rlc.register_list_format,
1912                 adev->gfx.rlc.reg_list_format_size_bytes);
1913
1914         /* setup unique_indirect_regs array and indirect_start_offsets array */
1915         gfx_v9_0_parse_ind_reg_list(register_list_format,
1916                                 GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH,
1917                                 adev->gfx.rlc.reg_list_format_size_bytes >> 2,
1918                                 unique_indirect_regs,
1919                                 &unique_indirect_reg_count,
1920                                 sizeof(unique_indirect_regs)/sizeof(int),
1921                                 indirect_start_offsets,
1922                                 &indirect_start_offsets_count,
1923                                 sizeof(indirect_start_offsets)/sizeof(int));
1924
1925         /* enable auto inc in case it is disabled */
1926         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
1927         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
1928         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
1929
1930         /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */
1931         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR),
1932                 RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET);
1933         for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
1934                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
1935                         adev->gfx.rlc.register_restore[i]);
1936
1937         /* load direct register */
1938         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR), 0);
1939         for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
1940                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
1941                         adev->gfx.rlc.register_restore[i]);
1942
1943         /* load indirect register */
1944         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1945                 adev->gfx.rlc.reg_list_format_start);
1946         for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++)
1947                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
1948                         register_list_format[i]);
1949
1950         /* set save/restore list size */
1951         list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
1952         list_size = list_size >> 1;
1953         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1954                 adev->gfx.rlc.reg_restore_list_size);
1955         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size);
1956
1957         /* write the starting offsets to RLC scratch ram */
1958         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
1959                 adev->gfx.rlc.starting_offsets_start);
1960         for (i = 0; i < sizeof(indirect_start_offsets)/sizeof(int); i++)
1961                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
1962                         indirect_start_offsets[i]);
1963
1964         /* load unique indirect regs*/
1965         for (i = 0; i < sizeof(unique_indirect_regs)/sizeof(int); i++) {
1966                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0) + i,
1967                         unique_indirect_regs[i] & 0x3FFFF);
1968                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0) + i,
1969                         unique_indirect_regs[i] >> 20);
1970         }
1971
1972         kfree(register_list_format);
1973         return 0;
1974 }
1975
1976 static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev)
1977 {
1978         u32 tmp = 0;
1979
1980         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
1981         tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
1982         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
1983 }
1984
1985 static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev,
1986                                              bool enable)
1987 {
1988         uint32_t data = 0;
1989         uint32_t default_data = 0;
1990
1991         default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS));
1992         if (enable == true) {
1993                 /* enable GFXIP control over CGPG */
1994                 data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
1995                 if(default_data != data)
1996                         WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
1997
1998                 /* update status */
1999                 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK;
2000                 data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT);
2001                 if(default_data != data)
2002                         WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
2003         } else {
2004                 /* restore GFXIP control over GCPG */
2005                 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
2006                 if(default_data != data)
2007                         WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
2008         }
2009 }
2010
2011 static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev)
2012 {
2013         uint32_t data = 0;
2014
2015         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2016                               AMD_PG_SUPPORT_GFX_SMG |
2017                               AMD_PG_SUPPORT_GFX_DMG)) {
2018                 /* init IDLE_POLL_COUNT = 60 */
2019                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));
2020                 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
2021                 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
2022                 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data);
2023
2024                 /* init RLC PG Delay */
2025                 data = 0;
2026                 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT);
2027                 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT);
2028                 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT);
2029                 data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT);
2030                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data);
2031
2032                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2));
2033                 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK;
2034                 data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT);
2035                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data);
2036
2037                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3));
2038                 data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK;
2039                 data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT);
2040                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data);
2041
2042                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL));
2043                 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
2044
2045                 /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */
2046                 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
2047                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data);
2048
2049                 pwr_10_0_gfxip_control_over_cgpg(adev, true);
2050         }
2051 }
2052
2053 static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
2054                                                 bool enable)
2055 {
2056         uint32_t data = 0;
2057         uint32_t default_data = 0;
2058
2059         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2060
2061         if (enable == true) {
2062                 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
2063                 if (default_data != data)
2064                         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2065         } else {
2066                 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
2067                 if(default_data != data)
2068                         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2069         }
2070 }
2071
2072 static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
2073                                                 bool enable)
2074 {
2075         uint32_t data = 0;
2076         uint32_t default_data = 0;
2077
2078         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2079
2080         if (enable == true) {
2081                 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
2082                 if(default_data != data)
2083                         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2084         } else {
2085                 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
2086                 if(default_data != data)
2087                         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2088         }
2089 }
2090
2091 static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev,
2092                                         bool enable)
2093 {
2094         uint32_t data = 0;
2095         uint32_t default_data = 0;
2096
2097         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2098
2099         if (enable == true) {
2100                 data &= ~RLC_PG_CNTL__CP_PG_DISABLE_MASK;
2101                 if(default_data != data)
2102                         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2103         } else {
2104                 data |= RLC_PG_CNTL__CP_PG_DISABLE_MASK;
2105                 if(default_data != data)
2106                         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2107         }
2108 }
2109
2110 static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
2111                                                 bool enable)
2112 {
2113         uint32_t data, default_data;
2114
2115         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2116         if (enable == true)
2117                 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
2118         else
2119                 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
2120         if(default_data != data)
2121                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2122 }
2123
2124 static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev,
2125                                                 bool enable)
2126 {
2127         uint32_t data, default_data;
2128
2129         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2130         if (enable == true)
2131                 data |= RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK;
2132         else
2133                 data &= ~RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK;
2134         if(default_data != data)
2135                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2136
2137         if (!enable)
2138                 /* read any GFX register to wake up GFX */
2139                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL));
2140 }
2141
2142 void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
2143                                                 bool enable)
2144 {
2145         uint32_t data, default_data;
2146
2147         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2148         if (enable == true)
2149                 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2150         else
2151                 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2152         if(default_data != data)
2153                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2154 }
2155
2156 void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
2157                                                 bool enable)
2158 {
2159         uint32_t data, default_data;
2160
2161         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2162         if (enable == true)
2163                 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2164         else
2165                 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2166         if(default_data != data)
2167                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2168 }
2169
2170 static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
2171 {
2172         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2173                               AMD_PG_SUPPORT_GFX_SMG |
2174                               AMD_PG_SUPPORT_GFX_DMG |
2175                               AMD_PG_SUPPORT_CP |
2176                               AMD_PG_SUPPORT_GDS |
2177                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
2178                 gfx_v9_0_init_csb(adev);
2179                 gfx_v9_0_init_rlc_save_restore_list(adev);
2180                 gfx_v9_0_enable_save_restore_machine(adev);
2181
2182                 if (adev->asic_type == CHIP_RAVEN) {
2183                         WREG32(mmRLC_JUMP_TABLE_RESTORE,
2184                                 adev->gfx.rlc.cp_table_gpu_addr >> 8);
2185                         gfx_v9_0_init_gfx_power_gating(adev);
2186
2187                         if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
2188                                 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
2189                                 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
2190                         } else {
2191                                 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
2192                                 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
2193                         }
2194
2195                         if (adev->pg_flags & AMD_PG_SUPPORT_CP)
2196                                 gfx_v9_0_enable_cp_power_gating(adev, true);
2197                         else
2198                                 gfx_v9_0_enable_cp_power_gating(adev, false);
2199                 }
2200         }
2201 }
2202
2203 void gfx_v9_0_rlc_stop(struct amdgpu_device *adev)
2204 {
2205         u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
2206
2207         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
2208         WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
2209
2210         gfx_v9_0_enable_gui_idle_interrupt(adev, false);
2211
2212         gfx_v9_0_wait_for_rlc_serdes(adev);
2213 }
2214
2215 static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev)
2216 {
2217         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2218         udelay(50);
2219         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2220         udelay(50);
2221 }
2222
2223 static void gfx_v9_0_rlc_start(struct amdgpu_device *adev)
2224 {
2225 #ifdef AMDGPU_RLC_DEBUG_RETRY
2226         u32 rlc_ucode_ver;
2227 #endif
2228
2229         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
2230
2231         /* carrizo do enable cp interrupt after cp inited */
2232         if (!(adev->flags & AMD_IS_APU))
2233                 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
2234
2235         udelay(50);
2236
2237 #ifdef AMDGPU_RLC_DEBUG_RETRY
2238         /* RLC_GPM_GENERAL_6 : RLC Ucode version */
2239         rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6);
2240         if(rlc_ucode_ver == 0x108) {
2241                 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n",
2242                                 rlc_ucode_ver, adev->gfx.rlc_fw_version);
2243                 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles,
2244                  * default is 0x9C4 to create a 100us interval */
2245                 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4);
2246                 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
2247                  * to disable the page fault retry interrupts, default is
2248                  * 0x100 (256) */
2249                 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100);
2250         }
2251 #endif
2252 }
2253
2254 static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev)
2255 {
2256         const struct rlc_firmware_header_v2_0 *hdr;
2257         const __le32 *fw_data;
2258         unsigned i, fw_size;
2259
2260         if (!adev->gfx.rlc_fw)
2261                 return -EINVAL;
2262
2263         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2264         amdgpu_ucode_print_rlc_hdr(&hdr->header);
2265
2266         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2267                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2268         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2269
2270         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
2271                         RLCG_UCODE_LOADING_START_ADDRESS);
2272         for (i = 0; i < fw_size; i++)
2273                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
2274         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
2275
2276         return 0;
2277 }
2278
2279 static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
2280 {
2281         int r;
2282
2283         if (amdgpu_sriov_vf(adev))
2284                 return 0;
2285
2286         gfx_v9_0_rlc_stop(adev);
2287
2288         /* disable CG */
2289         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
2290
2291         /* disable PG */
2292         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
2293
2294         gfx_v9_0_rlc_reset(adev);
2295
2296         gfx_v9_0_init_pg(adev);
2297
2298         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2299                 /* legacy rlc firmware loading */
2300                 r = gfx_v9_0_rlc_load_microcode(adev);
2301                 if (r)
2302                         return r;
2303         }
2304
2305         if (adev->asic_type == CHIP_RAVEN) {
2306                 if (amdgpu_lbpw != 0)
2307                         gfx_v9_0_enable_lbpw(adev, true);
2308                 else
2309                         gfx_v9_0_enable_lbpw(adev, false);
2310         }
2311
2312         gfx_v9_0_rlc_start(adev);
2313
2314         return 0;
2315 }
2316
2317 static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2318 {
2319         int i;
2320         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
2321
2322         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2323         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2324         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
2325         if (!enable) {
2326                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2327                         adev->gfx.gfx_ring[i].ready = false;
2328         }
2329         WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
2330         udelay(50);
2331 }
2332
2333 static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2334 {
2335         const struct gfx_firmware_header_v1_0 *pfp_hdr;
2336         const struct gfx_firmware_header_v1_0 *ce_hdr;
2337         const struct gfx_firmware_header_v1_0 *me_hdr;
2338         const __le32 *fw_data;
2339         unsigned i, fw_size;
2340
2341         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2342                 return -EINVAL;
2343
2344         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2345                 adev->gfx.pfp_fw->data;
2346         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2347                 adev->gfx.ce_fw->data;
2348         me_hdr = (const struct gfx_firmware_header_v1_0 *)
2349                 adev->gfx.me_fw->data;
2350
2351         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2352         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2353         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2354
2355         gfx_v9_0_cp_gfx_enable(adev, false);
2356
2357         /* PFP */
2358         fw_data = (const __le32 *)
2359                 (adev->gfx.pfp_fw->data +
2360                  le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2361         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2362         WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0);
2363         for (i = 0; i < fw_size; i++)
2364                 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2365         WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2366
2367         /* CE */
2368         fw_data = (const __le32 *)
2369                 (adev->gfx.ce_fw->data +
2370                  le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2371         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2372         WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0);
2373         for (i = 0; i < fw_size; i++)
2374                 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2375         WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2376
2377         /* ME */
2378         fw_data = (const __le32 *)
2379                 (adev->gfx.me_fw->data +
2380                  le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2381         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2382         WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0);
2383         for (i = 0; i < fw_size; i++)
2384                 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2385         WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2386
2387         return 0;
2388 }
2389
2390 static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)
2391 {
2392         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2393         const struct cs_section_def *sect = NULL;
2394         const struct cs_extent_def *ext = NULL;
2395         int r, i;
2396
2397         /* init the CP */
2398         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2399         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
2400
2401         gfx_v9_0_cp_gfx_enable(adev, true);
2402
2403         r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4);
2404         if (r) {
2405                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2406                 return r;
2407         }
2408
2409         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2410         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2411
2412         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2413         amdgpu_ring_write(ring, 0x80000000);
2414         amdgpu_ring_write(ring, 0x80000000);
2415
2416         for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
2417                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2418                         if (sect->id == SECT_CONTEXT) {
2419                                 amdgpu_ring_write(ring,
2420                                        PACKET3(PACKET3_SET_CONTEXT_REG,
2421                                                ext->reg_count));
2422                                 amdgpu_ring_write(ring,
2423                                        ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2424                                 for (i = 0; i < ext->reg_count; i++)
2425                                         amdgpu_ring_write(ring, ext->extent[i]);
2426                         }
2427                 }
2428         }
2429
2430         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2431         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2432
2433         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2434         amdgpu_ring_write(ring, 0);
2435
2436         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2437         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2438         amdgpu_ring_write(ring, 0x8000);
2439         amdgpu_ring_write(ring, 0x8000);
2440
2441         amdgpu_ring_commit(ring);
2442
2443         return 0;
2444 }
2445
2446 static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
2447 {
2448         struct amdgpu_ring *ring;
2449         u32 tmp;
2450         u32 rb_bufsz;
2451         u64 rb_addr, rptr_addr, wptr_gpu_addr;
2452
2453         /* Set the write pointer delay */
2454         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
2455
2456         /* set the RB to use vmid 0 */
2457         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
2458
2459         /* Set ring buffer size */
2460         ring = &adev->gfx.gfx_ring[0];
2461         rb_bufsz = order_base_2(ring->ring_size / 8);
2462         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2463         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2464 #ifdef __BIG_ENDIAN
2465         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
2466 #endif
2467         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2468
2469         /* Initialize the ring buffer's write pointers */
2470         ring->wptr = 0;
2471         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2472         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
2473
2474         /* set the wb address wether it's enabled or not */
2475         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2476         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2477         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
2478
2479         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2480         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
2481         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
2482
2483         mdelay(1);
2484         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2485
2486         rb_addr = ring->gpu_addr >> 8;
2487         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
2488         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2489
2490         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
2491         if (ring->use_doorbell) {
2492                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2493                                     DOORBELL_OFFSET, ring->doorbell_index);
2494                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2495                                     DOORBELL_EN, 1);
2496         } else {
2497                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
2498         }
2499         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
2500
2501         tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2502                         DOORBELL_RANGE_LOWER, ring->doorbell_index);
2503         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
2504
2505         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
2506                        CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2507
2508
2509         /* start the ring */
2510         gfx_v9_0_cp_gfx_start(adev);
2511         ring->ready = true;
2512
2513         return 0;
2514 }
2515
2516 static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2517 {
2518         int i;
2519
2520         if (enable) {
2521                 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
2522         } else {
2523                 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
2524                         (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2525                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2526                         adev->gfx.compute_ring[i].ready = false;
2527                 adev->gfx.kiq.ring.ready = false;
2528         }
2529         udelay(50);
2530 }
2531
2532 static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2533 {
2534         const struct gfx_firmware_header_v1_0 *mec_hdr;
2535         const __le32 *fw_data;
2536         unsigned i;
2537         u32 tmp;
2538
2539         if (!adev->gfx.mec_fw)
2540                 return -EINVAL;
2541
2542         gfx_v9_0_cp_compute_enable(adev, false);
2543
2544         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2545         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2546
2547         fw_data = (const __le32 *)
2548                 (adev->gfx.mec_fw->data +
2549                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2550         tmp = 0;
2551         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
2552         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
2553         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
2554
2555         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
2556                 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
2557         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
2558                 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
2559
2560         /* MEC1 */
2561         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
2562                          mec_hdr->jt_offset);
2563         for (i = 0; i < mec_hdr->jt_size; i++)
2564                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
2565                         le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
2566
2567         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
2568                         adev->gfx.mec_fw_version);
2569         /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
2570
2571         return 0;
2572 }
2573
2574 /* KIQ functions */
2575 static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
2576 {
2577         uint32_t tmp;
2578         struct amdgpu_device *adev = ring->adev;
2579
2580         /* tell RLC which is KIQ queue */
2581         tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
2582         tmp &= 0xffffff00;
2583         tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
2584         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2585         tmp |= 0x80;
2586         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2587 }
2588
2589 static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev)
2590 {
2591         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
2592         uint32_t scratch, tmp = 0;
2593         uint64_t queue_mask = 0;
2594         int r, i;
2595
2596         for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
2597                 if (!test_bit(i, adev->gfx.mec.queue_bitmap))
2598                         continue;
2599
2600                 /* This situation may be hit in the future if a new HW
2601                  * generation exposes more than 64 queues. If so, the
2602                  * definition of queue_mask needs updating */
2603                 if (WARN_ON(i > (sizeof(queue_mask)*8))) {
2604                         DRM_ERROR("Invalid KCQ enabled: %d\n", i);
2605                         break;
2606                 }
2607
2608                 queue_mask |= (1ull << i);
2609         }
2610
2611         r = amdgpu_gfx_scratch_get(adev, &scratch);
2612         if (r) {
2613                 DRM_ERROR("Failed to get scratch reg (%d).\n", r);
2614                 return r;
2615         }
2616         WREG32(scratch, 0xCAFEDEAD);
2617
2618         r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 11);
2619         if (r) {
2620                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
2621                 amdgpu_gfx_scratch_free(adev, scratch);
2622                 return r;
2623         }
2624
2625         /* set resources */
2626         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
2627         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
2628                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
2629         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
2630         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
2631         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
2632         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
2633         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
2634         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
2635         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2636                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2637                 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
2638                 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2639
2640                 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
2641                 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
2642                 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
2643                                   PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
2644                                   PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
2645                                   PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
2646                                   PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
2647                                   PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
2648                                   PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
2649                                   PACKET3_MAP_QUEUES_ALLOC_FORMAT(1) | /* alloc format: all_on_one_pipe */
2650                                   PACKET3_MAP_QUEUES_ENGINE_SEL(0) | /* engine_sel: compute */
2651                                   PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
2652                 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
2653                 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
2654                 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
2655                 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
2656                 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
2657         }
2658         /* write to scratch for completion */
2659         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2660         amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2661         amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
2662         amdgpu_ring_commit(kiq_ring);
2663
2664         for (i = 0; i < adev->usec_timeout; i++) {
2665                 tmp = RREG32(scratch);
2666                 if (tmp == 0xDEADBEEF)
2667                         break;
2668                 DRM_UDELAY(1);
2669         }
2670         if (i >= adev->usec_timeout) {
2671                 DRM_ERROR("KCQ enable failed (scratch(0x%04X)=0x%08X)\n",
2672                           scratch, tmp);
2673                 r = -EINVAL;
2674         }
2675         amdgpu_gfx_scratch_free(adev, scratch);
2676
2677         return r;
2678 }
2679
2680 static int gfx_v9_0_kiq_kcq_disable(struct amdgpu_device *adev)
2681 {
2682         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
2683         uint32_t scratch, tmp = 0;
2684         int r, i;
2685
2686         r = amdgpu_gfx_scratch_get(adev, &scratch);
2687         if (r) {
2688                 DRM_ERROR("Failed to get scratch reg (%d).\n", r);
2689                 return r;
2690         }
2691         WREG32(scratch, 0xCAFEDEAD);
2692
2693         r = amdgpu_ring_alloc(kiq_ring, 6 + 3);
2694         if (r) {
2695                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
2696                 amdgpu_gfx_scratch_free(adev, scratch);
2697                 return r;
2698         }
2699         /* unmap queues */
2700         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
2701         amdgpu_ring_write(kiq_ring,
2702                           PACKET3_UNMAP_QUEUES_ACTION(1)| /* RESET_QUEUES */
2703                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(2)); /* select all queues */
2704         amdgpu_ring_write(kiq_ring, 0);
2705         amdgpu_ring_write(kiq_ring, 0);
2706         amdgpu_ring_write(kiq_ring, 0);
2707         amdgpu_ring_write(kiq_ring, 0);
2708         /* write to scratch for completion */
2709         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2710         amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2711         amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
2712         amdgpu_ring_commit(kiq_ring);
2713
2714         for (i = 0; i < adev->usec_timeout; i++) {
2715                 tmp = RREG32(scratch);
2716                 if (tmp == 0xDEADBEEF)
2717                         break;
2718                 DRM_UDELAY(1);
2719         }
2720         if (i >= adev->usec_timeout) {
2721                 DRM_ERROR("KCQ disable failed (scratch(0x%04X)=0x%08X)\n",
2722                           scratch, tmp);
2723                 r = -EINVAL;
2724         }
2725         amdgpu_gfx_scratch_free(adev, scratch);
2726
2727         return r;
2728 }
2729
2730 static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
2731 {
2732         struct amdgpu_device *adev = ring->adev;
2733         struct v9_mqd *mqd = ring->mqd_ptr;
2734         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
2735         uint32_t tmp;
2736
2737         mqd->header = 0xC0310800;
2738         mqd->compute_pipelinestat_enable = 0x00000001;
2739         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
2740         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
2741         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
2742         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
2743         mqd->compute_misc_reserved = 0x00000003;
2744
2745         eop_base_addr = ring->eop_gpu_addr >> 8;
2746         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
2747         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
2748
2749         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2750         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
2751         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
2752                         (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1));
2753
2754         mqd->cp_hqd_eop_control = tmp;
2755
2756         /* enable doorbell? */
2757         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
2758
2759         if (ring->use_doorbell) {
2760                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2761                                     DOORBELL_OFFSET, ring->doorbell_index);
2762                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2763                                     DOORBELL_EN, 1);
2764                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2765                                     DOORBELL_SOURCE, 0);
2766                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2767                                     DOORBELL_HIT, 0);
2768         }
2769         else
2770                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2771                                          DOORBELL_EN, 0);
2772
2773         mqd->cp_hqd_pq_doorbell_control = tmp;
2774
2775         /* disable the queue if it's active */
2776         ring->wptr = 0;
2777         mqd->cp_hqd_dequeue_request = 0;
2778         mqd->cp_hqd_pq_rptr = 0;
2779         mqd->cp_hqd_pq_wptr_lo = 0;
2780         mqd->cp_hqd_pq_wptr_hi = 0;
2781
2782         /* set the pointer to the MQD */
2783         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
2784         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
2785
2786         /* set MQD vmid to 0 */
2787         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
2788         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
2789         mqd->cp_mqd_control = tmp;
2790
2791         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2792         hqd_gpu_addr = ring->gpu_addr >> 8;
2793         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
2794         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
2795
2796         /* set up the HQD, this is similar to CP_RB0_CNTL */
2797         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
2798         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
2799                             (order_base_2(ring->ring_size / 4) - 1));
2800         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
2801                         ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
2802 #ifdef __BIG_ENDIAN
2803         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
2804 #endif
2805         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
2806         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
2807         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
2808         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
2809         mqd->cp_hqd_pq_control = tmp;
2810
2811         /* set the wb address whether it's enabled or not */
2812         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2813         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
2814         mqd->cp_hqd_pq_rptr_report_addr_hi =
2815                 upper_32_bits(wb_gpu_addr) & 0xffff;
2816
2817         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2818         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2819         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
2820         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
2821
2822         tmp = 0;
2823         /* enable the doorbell if requested */
2824         if (ring->use_doorbell) {
2825                 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
2826                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2827                                 DOORBELL_OFFSET, ring->doorbell_index);
2828
2829                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2830                                          DOORBELL_EN, 1);
2831                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2832                                          DOORBELL_SOURCE, 0);
2833                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2834                                          DOORBELL_HIT, 0);
2835         }
2836
2837         mqd->cp_hqd_pq_doorbell_control = tmp;
2838
2839         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2840         ring->wptr = 0;
2841         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
2842
2843         /* set the vmid for the queue */
2844         mqd->cp_hqd_vmid = 0;
2845
2846         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
2847         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
2848         mqd->cp_hqd_persistent_state = tmp;
2849
2850         /* set MIN_IB_AVAIL_SIZE */
2851         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
2852         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
2853         mqd->cp_hqd_ib_control = tmp;
2854
2855         /* activate the queue */
2856         mqd->cp_hqd_active = 1;
2857
2858         return 0;
2859 }
2860
2861 static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
2862 {
2863         struct amdgpu_device *adev = ring->adev;
2864         struct v9_mqd *mqd = ring->mqd_ptr;
2865         int j;
2866
2867         /* disable wptr polling */
2868         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
2869
2870         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
2871                mqd->cp_hqd_eop_base_addr_lo);
2872         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
2873                mqd->cp_hqd_eop_base_addr_hi);
2874
2875         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2876         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
2877                mqd->cp_hqd_eop_control);
2878
2879         /* enable doorbell? */
2880         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
2881                mqd->cp_hqd_pq_doorbell_control);
2882
2883         /* disable the queue if it's active */
2884         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
2885                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
2886                 for (j = 0; j < adev->usec_timeout; j++) {
2887                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
2888                                 break;
2889                         udelay(1);
2890                 }
2891                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
2892                        mqd->cp_hqd_dequeue_request);
2893                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
2894                        mqd->cp_hqd_pq_rptr);
2895                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
2896                        mqd->cp_hqd_pq_wptr_lo);
2897                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
2898                        mqd->cp_hqd_pq_wptr_hi);
2899         }
2900
2901         /* set the pointer to the MQD */
2902         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
2903                mqd->cp_mqd_base_addr_lo);
2904         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
2905                mqd->cp_mqd_base_addr_hi);
2906
2907         /* set MQD vmid to 0 */
2908         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
2909                mqd->cp_mqd_control);
2910
2911         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2912         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
2913                mqd->cp_hqd_pq_base_lo);
2914         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
2915                mqd->cp_hqd_pq_base_hi);
2916
2917         /* set up the HQD, this is similar to CP_RB0_CNTL */
2918         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
2919                mqd->cp_hqd_pq_control);
2920
2921         /* set the wb address whether it's enabled or not */
2922         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
2923                                 mqd->cp_hqd_pq_rptr_report_addr_lo);
2924         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
2925                                 mqd->cp_hqd_pq_rptr_report_addr_hi);
2926
2927         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2928         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
2929                mqd->cp_hqd_pq_wptr_poll_addr_lo);
2930         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
2931                mqd->cp_hqd_pq_wptr_poll_addr_hi);
2932
2933         /* enable the doorbell if requested */
2934         if (ring->use_doorbell) {
2935                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
2936                                         (AMDGPU_DOORBELL64_KIQ *2) << 2);
2937                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
2938                                         (AMDGPU_DOORBELL64_USERQUEUE_END * 2) << 2);
2939         }
2940
2941         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
2942                mqd->cp_hqd_pq_doorbell_control);
2943
2944         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2945         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
2946                mqd->cp_hqd_pq_wptr_lo);
2947         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
2948                mqd->cp_hqd_pq_wptr_hi);
2949
2950         /* set the vmid for the queue */
2951         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
2952
2953         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
2954                mqd->cp_hqd_persistent_state);
2955
2956         /* activate the queue */
2957         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
2958                mqd->cp_hqd_active);
2959
2960         if (ring->use_doorbell)
2961                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
2962
2963         return 0;
2964 }
2965
2966 static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
2967 {
2968         struct amdgpu_device *adev = ring->adev;
2969         struct v9_mqd *mqd = ring->mqd_ptr;
2970         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
2971
2972         gfx_v9_0_kiq_setting(ring);
2973
2974         if (adev->gfx.in_reset) { /* for GPU_RESET case */
2975                 /* reset MQD to a clean status */
2976                 if (adev->gfx.mec.mqd_backup[mqd_idx])
2977                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
2978
2979                 /* reset ring buffer */
2980                 ring->wptr = 0;
2981                 amdgpu_ring_clear_ring(ring);
2982
2983                 mutex_lock(&adev->srbm_mutex);
2984                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2985                 gfx_v9_0_kiq_init_register(ring);
2986                 soc15_grbm_select(adev, 0, 0, 0, 0);
2987                 mutex_unlock(&adev->srbm_mutex);
2988         } else {
2989                 memset((void *)mqd, 0, sizeof(*mqd));
2990                 mutex_lock(&adev->srbm_mutex);
2991                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2992                 gfx_v9_0_mqd_init(ring);
2993                 gfx_v9_0_kiq_init_register(ring);
2994                 soc15_grbm_select(adev, 0, 0, 0, 0);
2995                 mutex_unlock(&adev->srbm_mutex);
2996
2997                 if (adev->gfx.mec.mqd_backup[mqd_idx])
2998                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
2999         }
3000
3001         return 0;
3002 }
3003
3004 static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
3005 {
3006         struct amdgpu_device *adev = ring->adev;
3007         struct v9_mqd *mqd = ring->mqd_ptr;
3008         int mqd_idx = ring - &adev->gfx.compute_ring[0];
3009
3010         if (!adev->gfx.in_reset && !adev->gfx.in_suspend) {
3011                 memset((void *)mqd, 0, sizeof(*mqd));
3012                 mutex_lock(&adev->srbm_mutex);
3013                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3014                 gfx_v9_0_mqd_init(ring);
3015                 soc15_grbm_select(adev, 0, 0, 0, 0);
3016                 mutex_unlock(&adev->srbm_mutex);
3017
3018                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3019                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
3020         } else if (adev->gfx.in_reset) { /* for GPU_RESET case */
3021                 /* reset MQD to a clean status */
3022                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3023                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
3024
3025                 /* reset ring buffer */
3026                 ring->wptr = 0;
3027                 amdgpu_ring_clear_ring(ring);
3028         } else {
3029                 amdgpu_ring_clear_ring(ring);
3030         }
3031
3032         return 0;
3033 }
3034
3035 static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)
3036 {
3037         struct amdgpu_ring *ring = NULL;
3038         int r = 0, i;
3039
3040         gfx_v9_0_cp_compute_enable(adev, true);
3041
3042         ring = &adev->gfx.kiq.ring;
3043
3044         r = amdgpu_bo_reserve(ring->mqd_obj, false);
3045         if (unlikely(r != 0))
3046                 goto done;
3047
3048         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3049         if (!r) {
3050                 r = gfx_v9_0_kiq_init_queue(ring);
3051                 amdgpu_bo_kunmap(ring->mqd_obj);
3052                 ring->mqd_ptr = NULL;
3053         }
3054         amdgpu_bo_unreserve(ring->mqd_obj);
3055         if (r)
3056                 goto done;
3057
3058         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3059                 ring = &adev->gfx.compute_ring[i];
3060
3061                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3062                 if (unlikely(r != 0))
3063                         goto done;
3064                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3065                 if (!r) {
3066                         r = gfx_v9_0_kcq_init_queue(ring);
3067                         amdgpu_bo_kunmap(ring->mqd_obj);
3068                         ring->mqd_ptr = NULL;
3069                 }
3070                 amdgpu_bo_unreserve(ring->mqd_obj);
3071                 if (r)
3072                         goto done;
3073         }
3074
3075         r = gfx_v9_0_kiq_kcq_enable(adev);
3076 done:
3077         return r;
3078 }
3079
3080 static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
3081 {
3082         int r, i;
3083         struct amdgpu_ring *ring;
3084
3085         if (!(adev->flags & AMD_IS_APU))
3086                 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
3087
3088         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
3089                 /* legacy firmware loading */
3090                 r = gfx_v9_0_cp_gfx_load_microcode(adev);
3091                 if (r)
3092                         return r;
3093
3094                 r = gfx_v9_0_cp_compute_load_microcode(adev);
3095                 if (r)
3096                         return r;
3097         }
3098
3099         r = gfx_v9_0_cp_gfx_resume(adev);
3100         if (r)
3101                 return r;
3102
3103         r = gfx_v9_0_kiq_resume(adev);
3104         if (r)
3105                 return r;
3106
3107         ring = &adev->gfx.gfx_ring[0];
3108         r = amdgpu_ring_test_ring(ring);
3109         if (r) {
3110                 ring->ready = false;
3111                 return r;
3112         }
3113
3114         ring = &adev->gfx.kiq.ring;
3115         ring->ready = true;
3116         r = amdgpu_ring_test_ring(ring);
3117         if (r)
3118                 ring->ready = false;
3119
3120         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3121                 ring = &adev->gfx.compute_ring[i];
3122
3123                 ring->ready = true;
3124                 r = amdgpu_ring_test_ring(ring);
3125                 if (r)
3126                         ring->ready = false;
3127         }
3128
3129         gfx_v9_0_enable_gui_idle_interrupt(adev, true);
3130
3131         return 0;
3132 }
3133
3134 static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
3135 {
3136         gfx_v9_0_cp_gfx_enable(adev, enable);
3137         gfx_v9_0_cp_compute_enable(adev, enable);
3138 }
3139
3140 static int gfx_v9_0_hw_init(void *handle)
3141 {
3142         int r;
3143         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3144
3145         gfx_v9_0_init_golden_registers(adev);
3146
3147         gfx_v9_0_gpu_init(adev);
3148
3149         r = gfx_v9_0_rlc_resume(adev);
3150         if (r)
3151                 return r;
3152
3153         r = gfx_v9_0_cp_resume(adev);
3154         if (r)
3155                 return r;
3156
3157         r = gfx_v9_0_ngg_en(adev);
3158         if (r)
3159                 return r;
3160
3161         return r;
3162 }
3163
3164 static int gfx_v9_0_hw_fini(void *handle)
3165 {
3166         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3167
3168         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
3169         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
3170         if (amdgpu_sriov_vf(adev)) {
3171                 pr_debug("For SRIOV client, shouldn't do anything.\n");
3172                 return 0;
3173         }
3174         gfx_v9_0_kiq_kcq_disable(adev);
3175         gfx_v9_0_cp_enable(adev, false);
3176         gfx_v9_0_rlc_stop(adev);
3177
3178         return 0;
3179 }
3180
3181 static int gfx_v9_0_suspend(void *handle)
3182 {
3183         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3184
3185         adev->gfx.in_suspend = true;
3186         return gfx_v9_0_hw_fini(adev);
3187 }
3188
3189 static int gfx_v9_0_resume(void *handle)
3190 {
3191         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3192         int r;
3193
3194         r = gfx_v9_0_hw_init(adev);
3195         adev->gfx.in_suspend = false;
3196         return r;
3197 }
3198
3199 static bool gfx_v9_0_is_idle(void *handle)
3200 {
3201         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3202
3203         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
3204                                 GRBM_STATUS, GUI_ACTIVE))
3205                 return false;
3206         else
3207                 return true;
3208 }
3209
3210 static int gfx_v9_0_wait_for_idle(void *handle)
3211 {
3212         unsigned i;
3213         u32 tmp;
3214         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3215
3216         for (i = 0; i < adev->usec_timeout; i++) {
3217                 /* read MC_STATUS */
3218                 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
3219                         GRBM_STATUS__GUI_ACTIVE_MASK;
3220
3221                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
3222                         return 0;
3223                 udelay(1);
3224         }
3225         return -ETIMEDOUT;
3226 }
3227
3228 static int gfx_v9_0_soft_reset(void *handle)
3229 {
3230         u32 grbm_soft_reset = 0;
3231         u32 tmp;
3232         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3233
3234         /* GRBM_STATUS */
3235         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
3236         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
3237                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
3238                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
3239                    GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
3240                    GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
3241                    GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
3242                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3243                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3244                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3245                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
3246         }
3247
3248         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
3249                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3250                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3251         }
3252
3253         /* GRBM_STATUS2 */
3254         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
3255         if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
3256                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3257                                                 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
3258
3259
3260         if (grbm_soft_reset) {
3261                 /* stop the rlc */
3262                 gfx_v9_0_rlc_stop(adev);
3263
3264                 /* Disable GFX parsing/prefetching */
3265                 gfx_v9_0_cp_gfx_enable(adev, false);
3266
3267                 /* Disable MEC parsing/prefetching */
3268                 gfx_v9_0_cp_compute_enable(adev, false);
3269
3270                 if (grbm_soft_reset) {
3271                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3272                         tmp |= grbm_soft_reset;
3273                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3274                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3275                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3276
3277                         udelay(50);
3278
3279                         tmp &= ~grbm_soft_reset;
3280                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3281                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3282                 }
3283
3284                 /* Wait a little for things to settle down */
3285                 udelay(50);
3286         }
3287         return 0;
3288 }
3289
3290 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3291 {
3292         uint64_t clock;
3293
3294         mutex_lock(&adev->gfx.gpu_clock_mutex);
3295         WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3296         clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
3297                 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3298         mutex_unlock(&adev->gfx.gpu_clock_mutex);
3299         return clock;
3300 }
3301
3302 static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3303                                           uint32_t vmid,
3304                                           uint32_t gds_base, uint32_t gds_size,
3305                                           uint32_t gws_base, uint32_t gws_size,
3306                                           uint32_t oa_base, uint32_t oa_size)
3307 {
3308         gds_base = gds_base >> AMDGPU_GDS_SHIFT;
3309         gds_size = gds_size >> AMDGPU_GDS_SHIFT;
3310
3311         gws_base = gws_base >> AMDGPU_GWS_SHIFT;
3312         gws_size = gws_size >> AMDGPU_GWS_SHIFT;
3313
3314         oa_base = oa_base >> AMDGPU_OA_SHIFT;
3315         oa_size = oa_size >> AMDGPU_OA_SHIFT;
3316
3317         /* GDS Base */
3318         gfx_v9_0_write_data_to_reg(ring, 0, false,
3319                                    amdgpu_gds_reg_offset[vmid].mem_base,
3320                                    gds_base);
3321
3322         /* GDS Size */
3323         gfx_v9_0_write_data_to_reg(ring, 0, false,
3324                                    amdgpu_gds_reg_offset[vmid].mem_size,
3325                                    gds_size);
3326
3327         /* GWS */
3328         gfx_v9_0_write_data_to_reg(ring, 0, false,
3329                                    amdgpu_gds_reg_offset[vmid].gws,
3330                                    gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
3331
3332         /* OA */
3333         gfx_v9_0_write_data_to_reg(ring, 0, false,
3334                                    amdgpu_gds_reg_offset[vmid].oa,
3335                                    (1 << (oa_size + oa_base)) - (1 << oa_base));
3336 }
3337
3338 static int gfx_v9_0_early_init(void *handle)
3339 {
3340         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3341
3342         adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
3343         adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
3344         gfx_v9_0_set_ring_funcs(adev);
3345         gfx_v9_0_set_irq_funcs(adev);
3346         gfx_v9_0_set_gds_init(adev);
3347         gfx_v9_0_set_rlc_funcs(adev);
3348
3349         return 0;
3350 }
3351
3352 static int gfx_v9_0_late_init(void *handle)
3353 {
3354         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3355         int r;
3356
3357         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
3358         if (r)
3359                 return r;
3360
3361         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
3362         if (r)
3363                 return r;
3364
3365         return 0;
3366 }
3367
3368 static void gfx_v9_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
3369 {
3370         uint32_t rlc_setting, data;
3371         unsigned i;
3372
3373         if (adev->gfx.rlc.in_safe_mode)
3374                 return;
3375
3376         /* if RLC is not enabled, do nothing */
3377         rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
3378         if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3379                 return;
3380
3381         if (adev->cg_flags &
3382             (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG |
3383              AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3384                 data = RLC_SAFE_MODE__CMD_MASK;
3385                 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
3386                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
3387
3388                 /* wait for RLC_SAFE_MODE */
3389                 for (i = 0; i < adev->usec_timeout; i++) {
3390                         if (!REG_GET_FIELD(SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
3391                                 break;
3392                         udelay(1);
3393                 }
3394                 adev->gfx.rlc.in_safe_mode = true;
3395         }
3396 }
3397
3398 static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
3399 {
3400         uint32_t rlc_setting, data;
3401
3402         if (!adev->gfx.rlc.in_safe_mode)
3403                 return;
3404
3405         /* if RLC is not enabled, do nothing */
3406         rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
3407         if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3408                 return;
3409
3410         if (adev->cg_flags &
3411             (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) {
3412                 /*
3413                  * Try to exit safe mode only if it is already in safe
3414                  * mode.
3415                  */
3416                 data = RLC_SAFE_MODE__CMD_MASK;
3417                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
3418                 adev->gfx.rlc.in_safe_mode = false;
3419         }
3420 }
3421
3422 static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
3423                                                 bool enable)
3424 {
3425         /* TODO: double check if we need to perform under safe mdoe */
3426         /* gfx_v9_0_enter_rlc_safe_mode(adev); */
3427
3428         if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
3429                 gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
3430                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
3431                         gfx_v9_0_enable_gfx_pipeline_powergating(adev, true);
3432         } else {
3433                 gfx_v9_0_enable_gfx_cg_power_gating(adev, false);
3434                 gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);
3435         }
3436
3437         /* gfx_v9_0_exit_rlc_safe_mode(adev); */
3438 }
3439
3440 static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev,
3441                                                 bool enable)
3442 {
3443         /* TODO: double check if we need to perform under safe mode */
3444         /* gfx_v9_0_enter_rlc_safe_mode(adev); */
3445
3446         if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
3447                 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true);
3448         else
3449                 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false);
3450
3451         if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
3452                 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true);
3453         else
3454                 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false);
3455
3456         /* gfx_v9_0_exit_rlc_safe_mode(adev); */
3457 }
3458
3459 static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
3460                                                       bool enable)
3461 {
3462         uint32_t data, def;
3463
3464         /* It is disabled by HW by default */
3465         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3466                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
3467                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3468                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
3469                           RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3470                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3471                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3472
3473                 /* only for Vega10 & Raven1 */
3474                 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
3475
3476                 if (def != data)
3477                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3478
3479                 /* MGLS is a global flag to control all MGLS in GFX */
3480                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3481                         /* 2 - RLC memory Light sleep */
3482                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
3483                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
3484                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3485                                 if (def != data)
3486                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
3487                         }
3488                         /* 3 - CP memory Light sleep */
3489                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
3490                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
3491                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3492                                 if (def != data)
3493                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
3494                         }
3495                 }
3496         } else {
3497                 /* 1 - MGCG_OVERRIDE */
3498                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3499                 data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
3500                          RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
3501                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3502                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3503                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3504                 if (def != data)
3505                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3506
3507                 /* 2 - disable MGLS in RLC */
3508                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
3509                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3510                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3511                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
3512                 }
3513
3514                 /* 3 - disable MGLS in CP */
3515                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
3516                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3517                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3518                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
3519                 }
3520         }
3521 }
3522
3523 static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
3524                                            bool enable)
3525 {
3526         uint32_t data, def;
3527
3528         adev->gfx.rlc.funcs->enter_safe_mode(adev);
3529
3530         /* Enable 3D CGCG/CGLS */
3531         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3532                 /* write cmd to clear cgcg/cgls ov */
3533                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3534                 /* unset CGCG override */
3535                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
3536                 /* update CGCG and CGLS override bits */
3537                 if (def != data)
3538                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3539                 /* enable 3Dcgcg FSM(0x0020003f) */
3540                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
3541                 data = (0x2000 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3542                         RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
3543                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
3544                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3545                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
3546                 if (def != data)
3547                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
3548
3549                 /* set IDLE_POLL_COUNT(0x00900100) */
3550                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
3551                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3552                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3553                 if (def != data)
3554                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
3555         } else {
3556                 /* Disable CGCG/CGLS */
3557                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
3558                 /* disable cgcg, cgls should be disabled */
3559                 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
3560                           RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
3561                 /* disable cgcg and cgls in FSM */
3562                 if (def != data)
3563                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
3564         }
3565
3566         adev->gfx.rlc.funcs->exit_safe_mode(adev);
3567 }
3568
3569 static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
3570                                                       bool enable)
3571 {
3572         uint32_t def, data;
3573
3574         adev->gfx.rlc.funcs->enter_safe_mode(adev);
3575
3576         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
3577                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3578                 /* unset CGCG override */
3579                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
3580                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3581                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3582                 else
3583                         data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3584                 /* update CGCG and CGLS override bits */
3585                 if (def != data)
3586                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3587
3588                 /* enable cgcg FSM(0x0020003F) */
3589                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
3590                 data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3591                         RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
3592                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3593                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3594                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3595                 if (def != data)
3596                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
3597
3598                 /* set IDLE_POLL_COUNT(0x00900100) */
3599                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
3600                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3601                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3602                 if (def != data)
3603                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
3604         } else {
3605                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
3606                 /* reset CGCG/CGLS bits */
3607                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3608                 /* disable cgcg and cgls in FSM */
3609                 if (def != data)
3610                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
3611         }
3612
3613         adev->gfx.rlc.funcs->exit_safe_mode(adev);
3614 }
3615
3616 static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
3617                                             bool enable)
3618 {
3619         if (enable) {
3620                 /* CGCG/CGLS should be enabled after MGCG/MGLS
3621                  * ===  MGCG + MGLS ===
3622                  */
3623                 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3624                 /* ===  CGCG /CGLS for GFX 3D Only === */
3625                 gfx_v9_0_update_3d_clock_gating(adev, enable);
3626                 /* ===  CGCG + CGLS === */
3627                 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3628         } else {
3629                 /* CGCG/CGLS should be disabled before MGCG/MGLS
3630                  * ===  CGCG + CGLS ===
3631                  */
3632                 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3633                 /* ===  CGCG /CGLS for GFX 3D Only === */
3634                 gfx_v9_0_update_3d_clock_gating(adev, enable);
3635                 /* ===  MGCG + MGLS === */
3636                 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3637         }
3638         return 0;
3639 }
3640
3641 static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
3642         .enter_safe_mode = gfx_v9_0_enter_rlc_safe_mode,
3643         .exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode
3644 };
3645
3646 static int gfx_v9_0_set_powergating_state(void *handle,
3647                                           enum amd_powergating_state state)
3648 {
3649         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3650         bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
3651
3652         switch (adev->asic_type) {
3653         case CHIP_RAVEN:
3654                 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
3655                         gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
3656                         gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
3657                 } else {
3658                         gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
3659                         gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
3660                 }
3661
3662                 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
3663                         gfx_v9_0_enable_cp_power_gating(adev, true);
3664                 else
3665                         gfx_v9_0_enable_cp_power_gating(adev, false);
3666
3667                 /* update gfx cgpg state */
3668                 gfx_v9_0_update_gfx_cg_power_gating(adev, enable);
3669
3670                 /* update mgcg state */
3671                 gfx_v9_0_update_gfx_mg_power_gating(adev, enable);
3672                 break;
3673         default:
3674                 break;
3675         }
3676
3677         return 0;
3678 }
3679
3680 static int gfx_v9_0_set_clockgating_state(void *handle,
3681                                           enum amd_clockgating_state state)
3682 {
3683         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3684
3685         if (amdgpu_sriov_vf(adev))
3686                 return 0;
3687
3688         switch (adev->asic_type) {
3689         case CHIP_VEGA10:
3690         case CHIP_RAVEN:
3691                 gfx_v9_0_update_gfx_clock_gating(adev,
3692                                                  state == AMD_CG_STATE_GATE ? true : false);
3693                 break;
3694         default:
3695                 break;
3696         }
3697         return 0;
3698 }
3699
3700 static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
3701 {
3702         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3703         int data;
3704
3705         if (amdgpu_sriov_vf(adev))
3706                 *flags = 0;
3707
3708         /* AMD_CG_SUPPORT_GFX_MGCG */
3709         data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3710         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
3711                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
3712
3713         /* AMD_CG_SUPPORT_GFX_CGCG */
3714         data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
3715         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
3716                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
3717
3718         /* AMD_CG_SUPPORT_GFX_CGLS */
3719         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
3720                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
3721
3722         /* AMD_CG_SUPPORT_GFX_RLC_LS */
3723         data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
3724         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
3725                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
3726
3727         /* AMD_CG_SUPPORT_GFX_CP_LS */
3728         data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
3729         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
3730                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
3731
3732         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
3733         data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
3734         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
3735                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
3736
3737         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
3738         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
3739                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
3740 }
3741
3742 static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
3743 {
3744         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/
3745 }
3746
3747 static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
3748 {
3749         struct amdgpu_device *adev = ring->adev;
3750         u64 wptr;
3751
3752         /* XXX check if swapping is necessary on BE */
3753         if (ring->use_doorbell) {
3754                 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
3755         } else {
3756                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
3757                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
3758         }
3759
3760         return wptr;
3761 }
3762
3763 static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
3764 {
3765         struct amdgpu_device *adev = ring->adev;
3766
3767         if (ring->use_doorbell) {
3768                 /* XXX check if swapping is necessary on BE */
3769                 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
3770                 WDOORBELL64(ring->doorbell_index, ring->wptr);
3771         } else {
3772                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
3773                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
3774         }
3775 }
3776
3777 static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
3778 {
3779         u32 ref_and_mask, reg_mem_engine;
3780         struct nbio_hdp_flush_reg *nbio_hf_reg;
3781
3782         if (ring->adev->asic_type == CHIP_VEGA10)
3783                 nbio_hf_reg = &nbio_v6_1_hdp_flush_reg;
3784
3785         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
3786                 switch (ring->me) {
3787                 case 1:
3788                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
3789                         break;
3790                 case 2:
3791                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
3792                         break;
3793                 default:
3794                         return;
3795                 }
3796                 reg_mem_engine = 0;
3797         } else {
3798                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
3799                 reg_mem_engine = 1; /* pfp */
3800         }
3801
3802         gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
3803                               nbio_hf_reg->hdp_flush_req_offset,
3804                               nbio_hf_reg->hdp_flush_done_offset,
3805                               ref_and_mask, ref_and_mask, 0x20);
3806 }
3807
3808 static void gfx_v9_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
3809 {
3810         gfx_v9_0_write_data_to_reg(ring, 0, true,
3811                                    SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0), 1);
3812 }
3813
3814 static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
3815                                       struct amdgpu_ib *ib,
3816                                       unsigned vm_id, bool ctx_switch)
3817 {
3818         u32 header, control = 0;
3819
3820         if (ib->flags & AMDGPU_IB_FLAG_CE)
3821                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3822         else
3823                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3824
3825         control |= ib->length_dw | (vm_id << 24);
3826
3827         if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
3828                 control |= INDIRECT_BUFFER_PRE_ENB(1);
3829
3830                 if (!(ib->flags & AMDGPU_IB_FLAG_CE))
3831                         gfx_v9_0_ring_emit_de_meta(ring);
3832         }
3833
3834         amdgpu_ring_write(ring, header);
3835 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3836         amdgpu_ring_write(ring,
3837 #ifdef __BIG_ENDIAN
3838                 (2 << 0) |
3839 #endif
3840                 lower_32_bits(ib->gpu_addr));
3841         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
3842         amdgpu_ring_write(ring, control);
3843 }
3844
3845 static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
3846                                           struct amdgpu_ib *ib,
3847                                           unsigned vm_id, bool ctx_switch)
3848 {
3849         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24);
3850
3851         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3852         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3853         amdgpu_ring_write(ring,
3854 #ifdef __BIG_ENDIAN
3855                                 (2 << 0) |
3856 #endif
3857                                 lower_32_bits(ib->gpu_addr));
3858         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
3859         amdgpu_ring_write(ring, control);
3860 }
3861
3862 static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
3863                                      u64 seq, unsigned flags)
3864 {
3865         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
3866         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
3867
3868         /* RELEASE_MEM - flush caches, send int */
3869         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
3870         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
3871                                  EOP_TC_ACTION_EN |
3872                                  EOP_TC_WB_ACTION_EN |
3873                                  EOP_TC_MD_ACTION_EN |
3874                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3875                                  EVENT_INDEX(5)));
3876         amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
3877
3878         /*
3879          * the address should be Qword aligned if 64bit write, Dword
3880          * aligned if only send 32bit data low (discard data high)
3881          */
3882         if (write64bit)
3883                 BUG_ON(addr & 0x7);
3884         else
3885                 BUG_ON(addr & 0x3);
3886         amdgpu_ring_write(ring, lower_32_bits(addr));
3887         amdgpu_ring_write(ring, upper_32_bits(addr));
3888         amdgpu_ring_write(ring, lower_32_bits(seq));
3889         amdgpu_ring_write(ring, upper_32_bits(seq));
3890         amdgpu_ring_write(ring, 0);
3891 }
3892
3893 static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
3894 {
3895         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3896         uint32_t seq = ring->fence_drv.sync_seq;
3897         uint64_t addr = ring->fence_drv.gpu_addr;
3898
3899         gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0,
3900                               lower_32_bits(addr), upper_32_bits(addr),
3901                               seq, 0xffffffff, 4);
3902 }
3903
3904 static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3905                                         unsigned vm_id, uint64_t pd_addr)
3906 {
3907         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
3908         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3909         uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
3910         unsigned eng = ring->vm_inv_eng;
3911
3912         pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr);
3913         pd_addr |= AMDGPU_PTE_VALID;
3914
3915         gfx_v9_0_write_data_to_reg(ring, usepfp, true,
3916                                    hub->ctx0_ptb_addr_lo32 + (2 * vm_id),
3917                                    lower_32_bits(pd_addr));
3918
3919         gfx_v9_0_write_data_to_reg(ring, usepfp, true,
3920                                    hub->ctx0_ptb_addr_hi32 + (2 * vm_id),
3921                                    upper_32_bits(pd_addr));
3922
3923         gfx_v9_0_write_data_to_reg(ring, usepfp, true,
3924                                    hub->vm_inv_eng0_req + eng, req);
3925
3926         /* wait for the invalidate to complete */
3927         gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, hub->vm_inv_eng0_ack +
3928                               eng, 0, 1 << vm_id, 1 << vm_id, 0x20);
3929
3930         /* compute doesn't have PFP */
3931         if (usepfp) {
3932                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3933                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3934                 amdgpu_ring_write(ring, 0x0);
3935         }
3936 }
3937
3938 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
3939 {
3940         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */
3941 }
3942
3943 static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
3944 {
3945         u64 wptr;
3946
3947         /* XXX check if swapping is necessary on BE */
3948         if (ring->use_doorbell)
3949                 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
3950         else
3951                 BUG();
3952         return wptr;
3953 }
3954
3955 static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
3956 {
3957         struct amdgpu_device *adev = ring->adev;
3958
3959         /* XXX check if swapping is necessary on BE */
3960         if (ring->use_doorbell) {
3961                 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
3962                 WDOORBELL64(ring->doorbell_index, ring->wptr);
3963         } else{
3964                 BUG(); /* only DOORBELL method supported on gfx9 now */
3965         }
3966 }
3967
3968 static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
3969                                          u64 seq, unsigned int flags)
3970 {
3971         /* we only allocate 32bit for each seq wb address */
3972         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
3973
3974         /* write fence seq to the "addr" */
3975         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3976         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3977                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
3978         amdgpu_ring_write(ring, lower_32_bits(addr));
3979         amdgpu_ring_write(ring, upper_32_bits(addr));
3980         amdgpu_ring_write(ring, lower_32_bits(seq));
3981
3982         if (flags & AMDGPU_FENCE_FLAG_INT) {
3983                 /* set register to trigger INT */
3984                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3985                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3986                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
3987                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
3988                 amdgpu_ring_write(ring, 0);
3989                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
3990         }
3991 }
3992
3993 static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring)
3994 {
3995         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3996         amdgpu_ring_write(ring, 0);
3997 }
3998
3999 static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
4000 {
4001         static struct v9_ce_ib_state ce_payload = {0};
4002         uint64_t csa_addr;
4003         int cnt;
4004
4005         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
4006         csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096;
4007
4008         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
4009         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
4010                                  WRITE_DATA_DST_SEL(8) |
4011                                  WR_CONFIRM) |
4012                                  WRITE_DATA_CACHE_POLICY(0));
4013         amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
4014         amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
4015         amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2);
4016 }
4017
4018 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring)
4019 {
4020         static struct v9_de_ib_state de_payload = {0};
4021         uint64_t csa_addr, gds_addr;
4022         int cnt;
4023
4024         csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096;
4025         gds_addr = csa_addr + 4096;
4026         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
4027         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
4028
4029         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
4030         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
4031         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
4032                                  WRITE_DATA_DST_SEL(8) |
4033                                  WR_CONFIRM) |
4034                                  WRITE_DATA_CACHE_POLICY(0));
4035         amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
4036         amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
4037         amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2);
4038 }
4039
4040 static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
4041 {
4042         uint32_t dw2 = 0;
4043
4044         if (amdgpu_sriov_vf(ring->adev))
4045                 gfx_v9_0_ring_emit_ce_meta(ring);
4046
4047         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
4048         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
4049                 /* set load_global_config & load_global_uconfig */
4050                 dw2 |= 0x8001;
4051                 /* set load_cs_sh_regs */
4052                 dw2 |= 0x01000000;
4053                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
4054                 dw2 |= 0x10002;
4055
4056                 /* set load_ce_ram if preamble presented */
4057                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
4058                         dw2 |= 0x10000000;
4059         } else {
4060                 /* still load_ce_ram if this is the first time preamble presented
4061                  * although there is no context switch happens.
4062                  */
4063                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
4064                         dw2 |= 0x10000000;
4065         }
4066
4067         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4068         amdgpu_ring_write(ring, dw2);
4069         amdgpu_ring_write(ring, 0);
4070 }
4071
4072 static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
4073 {
4074         unsigned ret;
4075         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
4076         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
4077         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
4078         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
4079         ret = ring->wptr & ring->buf_mask;
4080         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
4081         return ret;
4082 }
4083
4084 static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
4085 {
4086         unsigned cur;
4087         BUG_ON(offset > ring->buf_mask);
4088         BUG_ON(ring->ring[offset] != 0x55aa55aa);
4089
4090         cur = (ring->wptr & ring->buf_mask) - 1;
4091         if (likely(cur > offset))
4092                 ring->ring[offset] = cur - offset;
4093         else
4094                 ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
4095 }
4096
4097 static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
4098 {
4099         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
4100         amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
4101 }
4102
4103 static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
4104 {
4105         struct amdgpu_device *adev = ring->adev;
4106
4107         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
4108         amdgpu_ring_write(ring, 0 |     /* src: register*/
4109                                 (5 << 8) |      /* dst: memory */
4110                                 (1 << 20));     /* write confirm */
4111         amdgpu_ring_write(ring, reg);
4112         amdgpu_ring_write(ring, 0);
4113         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
4114                                 adev->virt.reg_val_offs * 4));
4115         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
4116                                 adev->virt.reg_val_offs * 4));
4117 }
4118
4119 static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
4120                                   uint32_t val)
4121 {
4122         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4123         amdgpu_ring_write(ring, (1 << 16)); /* no inc addr */
4124         amdgpu_ring_write(ring, reg);
4125         amdgpu_ring_write(ring, 0);
4126         amdgpu_ring_write(ring, val);
4127 }
4128
4129 static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4130                                                  enum amdgpu_interrupt_state state)
4131 {
4132         switch (state) {
4133         case AMDGPU_IRQ_STATE_DISABLE:
4134         case AMDGPU_IRQ_STATE_ENABLE:
4135                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4136                                TIME_STAMP_INT_ENABLE,
4137                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4138                 break;
4139         default:
4140                 break;
4141         }
4142 }
4143
4144 static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4145                                                      int me, int pipe,
4146                                                      enum amdgpu_interrupt_state state)
4147 {
4148         /* Me 0 is reserved for graphics */
4149         if (me < 1 || me > adev->gfx.mec.num_mec) {
4150                 DRM_ERROR("Ignoring request to enable interrupts for invalid me:%d\n", me);
4151                 return;
4152         }
4153
4154         if (pipe >= adev->gfx.mec.num_pipe_per_mec) {
4155                 DRM_ERROR("Ignoring request to enable interrupts for invalid "
4156                                 "me:%d pipe:%d\n", pipe, me);
4157                 return;
4158         }
4159
4160         mutex_lock(&adev->srbm_mutex);
4161         soc15_grbm_select(adev, me, pipe, 0, 0);
4162
4163         WREG32_FIELD(CPC_INT_CNTL, TIME_STAMP_INT_ENABLE,
4164                         state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
4165
4166         soc15_grbm_select(adev, 0, 0, 0, 0);
4167         mutex_unlock(&adev->srbm_mutex);
4168 }
4169
4170 static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4171                                              struct amdgpu_irq_src *source,
4172                                              unsigned type,
4173                                              enum amdgpu_interrupt_state state)
4174 {
4175         switch (state) {
4176         case AMDGPU_IRQ_STATE_DISABLE:
4177         case AMDGPU_IRQ_STATE_ENABLE:
4178                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4179                                PRIV_REG_INT_ENABLE,
4180                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4181                 break;
4182         default:
4183                 break;
4184         }
4185
4186         return 0;
4187 }
4188
4189 static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4190                                               struct amdgpu_irq_src *source,
4191                                               unsigned type,
4192                                               enum amdgpu_interrupt_state state)
4193 {
4194         switch (state) {
4195         case AMDGPU_IRQ_STATE_DISABLE:
4196         case AMDGPU_IRQ_STATE_ENABLE:
4197                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4198                                PRIV_INSTR_INT_ENABLE,
4199                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4200         default:
4201                 break;
4202         }
4203
4204         return 0;
4205 }
4206
4207 static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4208                                             struct amdgpu_irq_src *src,
4209                                             unsigned type,
4210                                             enum amdgpu_interrupt_state state)
4211 {
4212         switch (type) {
4213         case AMDGPU_CP_IRQ_GFX_EOP:
4214                 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
4215                 break;
4216         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4217                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4218                 break;
4219         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4220                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4221                 break;
4222         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4223                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4224                 break;
4225         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4226                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4227                 break;
4228         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4229                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4230                 break;
4231         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4232                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4233                 break;
4234         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4235                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4236                 break;
4237         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4238                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4239                 break;
4240         default:
4241                 break;
4242         }
4243         return 0;
4244 }
4245
4246 static int gfx_v9_0_eop_irq(struct amdgpu_device *adev,
4247                             struct amdgpu_irq_src *source,
4248                             struct amdgpu_iv_entry *entry)
4249 {
4250         int i;
4251         u8 me_id, pipe_id, queue_id;
4252         struct amdgpu_ring *ring;
4253
4254         DRM_DEBUG("IH: CP EOP\n");
4255         me_id = (entry->ring_id & 0x0c) >> 2;
4256         pipe_id = (entry->ring_id & 0x03) >> 0;
4257         queue_id = (entry->ring_id & 0x70) >> 4;
4258
4259         switch (me_id) {
4260         case 0:
4261                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4262                 break;
4263         case 1:
4264         case 2:
4265                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4266                         ring = &adev->gfx.compute_ring[i];
4267                         /* Per-queue interrupt is supported for MEC starting from VI.
4268                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
4269                           */
4270                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4271                                 amdgpu_fence_process(ring);
4272                 }
4273                 break;
4274         }
4275         return 0;
4276 }
4277
4278 static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev,
4279                                  struct amdgpu_irq_src *source,
4280                                  struct amdgpu_iv_entry *entry)
4281 {
4282         DRM_ERROR("Illegal register access in command stream\n");
4283         schedule_work(&adev->reset_work);
4284         return 0;
4285 }
4286
4287 static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
4288                                   struct amdgpu_irq_src *source,
4289                                   struct amdgpu_iv_entry *entry)
4290 {
4291         DRM_ERROR("Illegal instruction in command stream\n");
4292         schedule_work(&adev->reset_work);
4293         return 0;
4294 }
4295
4296 static int gfx_v9_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
4297                                             struct amdgpu_irq_src *src,
4298                                             unsigned int type,
4299                                             enum amdgpu_interrupt_state state)
4300 {
4301         uint32_t tmp, target;
4302         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
4303
4304         if (ring->me == 1)
4305                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
4306         else
4307                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
4308         target += ring->pipe;
4309
4310         switch (type) {
4311         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
4312                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
4313                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
4314                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
4315                                                  GENERIC2_INT_ENABLE, 0);
4316                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
4317
4318                         tmp = RREG32(target);
4319                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
4320                                                  GENERIC2_INT_ENABLE, 0);
4321                         WREG32(target, tmp);
4322                 } else {
4323                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
4324                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
4325                                                  GENERIC2_INT_ENABLE, 1);
4326                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
4327
4328                         tmp = RREG32(target);
4329                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
4330                                                  GENERIC2_INT_ENABLE, 1);
4331                         WREG32(target, tmp);
4332                 }
4333                 break;
4334         default:
4335                 BUG(); /* kiq only support GENERIC2_INT now */
4336                 break;
4337         }
4338         return 0;
4339 }
4340
4341 static int gfx_v9_0_kiq_irq(struct amdgpu_device *adev,
4342                             struct amdgpu_irq_src *source,
4343                             struct amdgpu_iv_entry *entry)
4344 {
4345         u8 me_id, pipe_id, queue_id;
4346         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
4347
4348         me_id = (entry->ring_id & 0x0c) >> 2;
4349         pipe_id = (entry->ring_id & 0x03) >> 0;
4350         queue_id = (entry->ring_id & 0x70) >> 4;
4351         DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
4352                    me_id, pipe_id, queue_id);
4353
4354         amdgpu_fence_process(ring);
4355         return 0;
4356 }
4357
4358 const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
4359         .name = "gfx_v9_0",
4360         .early_init = gfx_v9_0_early_init,
4361         .late_init = gfx_v9_0_late_init,
4362         .sw_init = gfx_v9_0_sw_init,
4363         .sw_fini = gfx_v9_0_sw_fini,
4364         .hw_init = gfx_v9_0_hw_init,
4365         .hw_fini = gfx_v9_0_hw_fini,
4366         .suspend = gfx_v9_0_suspend,
4367         .resume = gfx_v9_0_resume,
4368         .is_idle = gfx_v9_0_is_idle,
4369         .wait_for_idle = gfx_v9_0_wait_for_idle,
4370         .soft_reset = gfx_v9_0_soft_reset,
4371         .set_clockgating_state = gfx_v9_0_set_clockgating_state,
4372         .set_powergating_state = gfx_v9_0_set_powergating_state,
4373         .get_clockgating_state = gfx_v9_0_get_clockgating_state,
4374 };
4375
4376 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
4377         .type = AMDGPU_RING_TYPE_GFX,
4378         .align_mask = 0xff,
4379         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4380         .support_64bit_ptrs = true,
4381         .vmhub = AMDGPU_GFXHUB,
4382         .get_rptr = gfx_v9_0_ring_get_rptr_gfx,
4383         .get_wptr = gfx_v9_0_ring_get_wptr_gfx,
4384         .set_wptr = gfx_v9_0_ring_set_wptr_gfx,
4385         .emit_frame_size = /* totally 242 maximum if 16 IBs */
4386                 5 +  /* COND_EXEC */
4387                 7 +  /* PIPELINE_SYNC */
4388                 24 + /* VM_FLUSH */
4389                 8 +  /* FENCE for VM_FLUSH */
4390                 20 + /* GDS switch */
4391                 4 + /* double SWITCH_BUFFER,
4392                        the first COND_EXEC jump to the place just
4393                            prior to this double SWITCH_BUFFER  */
4394                 5 + /* COND_EXEC */
4395                 7 +      /*     HDP_flush */
4396                 4 +      /*     VGT_flush */
4397                 14 + /* CE_META */
4398                 31 + /* DE_META */
4399                 3 + /* CNTX_CTRL */
4400                 5 + /* HDP_INVL */
4401                 8 + 8 + /* FENCE x2 */
4402                 2, /* SWITCH_BUFFER */
4403         .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */
4404         .emit_ib = gfx_v9_0_ring_emit_ib_gfx,
4405         .emit_fence = gfx_v9_0_ring_emit_fence,
4406         .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4407         .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4408         .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4409         .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4410         .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
4411         .test_ring = gfx_v9_0_ring_test_ring,
4412         .test_ib = gfx_v9_0_ring_test_ib,
4413         .insert_nop = amdgpu_ring_insert_nop,
4414         .pad_ib = amdgpu_ring_generic_pad_ib,
4415         .emit_switch_buffer = gfx_v9_ring_emit_sb,
4416         .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,
4417         .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec,
4418         .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec,
4419         .emit_tmz = gfx_v9_0_ring_emit_tmz,
4420 };
4421
4422 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
4423         .type = AMDGPU_RING_TYPE_COMPUTE,
4424         .align_mask = 0xff,
4425         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4426         .support_64bit_ptrs = true,
4427         .vmhub = AMDGPU_GFXHUB,
4428         .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4429         .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4430         .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4431         .emit_frame_size =
4432                 20 + /* gfx_v9_0_ring_emit_gds_switch */
4433                 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4434                 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
4435                 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
4436                 24 + /* gfx_v9_0_ring_emit_vm_flush */
4437                 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
4438         .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4439         .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4440         .emit_fence = gfx_v9_0_ring_emit_fence,
4441         .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4442         .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4443         .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4444         .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4445         .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
4446         .test_ring = gfx_v9_0_ring_test_ring,
4447         .test_ib = gfx_v9_0_ring_test_ib,
4448         .insert_nop = amdgpu_ring_insert_nop,
4449         .pad_ib = amdgpu_ring_generic_pad_ib,
4450 };
4451
4452 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
4453         .type = AMDGPU_RING_TYPE_KIQ,
4454         .align_mask = 0xff,
4455         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4456         .support_64bit_ptrs = true,
4457         .vmhub = AMDGPU_GFXHUB,
4458         .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4459         .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4460         .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4461         .emit_frame_size =
4462                 20 + /* gfx_v9_0_ring_emit_gds_switch */
4463                 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4464                 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
4465                 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
4466                 24 + /* gfx_v9_0_ring_emit_vm_flush */
4467                 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */
4468         .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4469         .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4470         .emit_fence = gfx_v9_0_ring_emit_fence_kiq,
4471         .test_ring = gfx_v9_0_ring_test_ring,
4472         .test_ib = gfx_v9_0_ring_test_ib,
4473         .insert_nop = amdgpu_ring_insert_nop,
4474         .pad_ib = amdgpu_ring_generic_pad_ib,
4475         .emit_rreg = gfx_v9_0_ring_emit_rreg,
4476         .emit_wreg = gfx_v9_0_ring_emit_wreg,
4477 };
4478
4479 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)
4480 {
4481         int i;
4482
4483         adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq;
4484
4485         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4486                 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx;
4487
4488         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4489                 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute;
4490 }
4491
4492 static const struct amdgpu_irq_src_funcs gfx_v9_0_kiq_irq_funcs = {
4493         .set = gfx_v9_0_kiq_set_interrupt_state,
4494         .process = gfx_v9_0_kiq_irq,
4495 };
4496
4497 static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = {
4498         .set = gfx_v9_0_set_eop_interrupt_state,
4499         .process = gfx_v9_0_eop_irq,
4500 };
4501
4502 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = {
4503         .set = gfx_v9_0_set_priv_reg_fault_state,
4504         .process = gfx_v9_0_priv_reg_irq,
4505 };
4506
4507 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = {
4508         .set = gfx_v9_0_set_priv_inst_fault_state,
4509         .process = gfx_v9_0_priv_inst_irq,
4510 };
4511
4512 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)
4513 {
4514         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4515         adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs;
4516
4517         adev->gfx.priv_reg_irq.num_types = 1;
4518         adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs;
4519
4520         adev->gfx.priv_inst_irq.num_types = 1;
4521         adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs;
4522
4523         adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
4524         adev->gfx.kiq.irq.funcs = &gfx_v9_0_kiq_irq_funcs;
4525 }
4526
4527 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
4528 {
4529         switch (adev->asic_type) {
4530         case CHIP_VEGA10:
4531         case CHIP_RAVEN:
4532                 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
4533                 break;
4534         default:
4535                 break;
4536         }
4537 }
4538
4539 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
4540 {
4541         /* init asci gds info */
4542         adev->gds.mem.total_size = RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
4543         adev->gds.gws.total_size = 64;
4544         adev->gds.oa.total_size = 16;
4545
4546         if (adev->gds.mem.total_size == 64 * 1024) {
4547                 adev->gds.mem.gfx_partition_size = 4096;
4548                 adev->gds.mem.cs_partition_size = 4096;
4549
4550                 adev->gds.gws.gfx_partition_size = 4;
4551                 adev->gds.gws.cs_partition_size = 4;
4552
4553                 adev->gds.oa.gfx_partition_size = 4;
4554                 adev->gds.oa.cs_partition_size = 1;
4555         } else {
4556                 adev->gds.mem.gfx_partition_size = 1024;
4557                 adev->gds.mem.cs_partition_size = 1024;
4558
4559                 adev->gds.gws.gfx_partition_size = 16;
4560                 adev->gds.gws.cs_partition_size = 16;
4561
4562                 adev->gds.oa.gfx_partition_size = 4;
4563                 adev->gds.oa.cs_partition_size = 4;
4564         }
4565 }
4566
4567 static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)
4568 {
4569         u32 data, mask;
4570
4571         data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
4572         data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
4573
4574         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4575         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4576
4577         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
4578
4579         return (~data) & mask;
4580 }
4581
4582 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
4583                                  struct amdgpu_cu_info *cu_info)
4584 {
4585         int i, j, k, counter, active_cu_number = 0;
4586         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
4587
4588         if (!adev || !cu_info)
4589                 return -EINVAL;
4590
4591         memset(cu_info, 0, sizeof(*cu_info));
4592
4593         mutex_lock(&adev->grbm_idx_mutex);
4594         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4595                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4596                         mask = 1;
4597                         ao_bitmap = 0;
4598                         counter = 0;
4599                         gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
4600                         bitmap = gfx_v9_0_get_cu_active_bitmap(adev);
4601                         cu_info->bitmap[i][j] = bitmap;
4602
4603                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
4604                                 if (bitmap & mask) {
4605                                         if (counter < adev->gfx.config.max_cu_per_sh)
4606                                                 ao_bitmap |= mask;
4607                                         counter ++;
4608                                 }
4609                                 mask <<= 1;
4610                         }
4611                         active_cu_number += counter;
4612                         ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
4613                 }
4614         }
4615         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4616         mutex_unlock(&adev->grbm_idx_mutex);
4617
4618         cu_info->number = active_cu_number;
4619         cu_info->ao_cu_mask = ao_cu_mask;
4620
4621         return 0;
4622 }
4623
4624 const struct amdgpu_ip_block_version gfx_v9_0_ip_block =
4625 {
4626         .type = AMD_IP_BLOCK_TYPE_GFX,
4627         .major = 9,
4628         .minor = 0,
4629         .rev = 0,
4630         .funcs = &gfx_v9_0_ip_funcs,
4631 };