2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
25 #include "amdgpu_ih.h"
26 #include "amdgpu_gfx.h"
27 #include "amdgpu_ucode.h"
28 #include "clearstate_si.h"
29 #include "bif/bif_3_0_d.h"
30 #include "bif/bif_3_0_sh_mask.h"
31 #include "oss/oss_1_0_d.h"
32 #include "oss/oss_1_0_sh_mask.h"
33 #include "gca/gfx_6_0_d.h"
34 #include "gca/gfx_6_0_sh_mask.h"
35 #include "gmc/gmc_6_0_d.h"
36 #include "gmc/gmc_6_0_sh_mask.h"
37 #include "dce/dce_6_0_d.h"
38 #include "dce/dce_6_0_sh_mask.h"
39 #include "gca/gfx_7_2_enum.h"
43 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev);
44 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev);
45 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev);
47 MODULE_FIRMWARE("radeon/tahiti_pfp.bin");
48 MODULE_FIRMWARE("radeon/tahiti_me.bin");
49 MODULE_FIRMWARE("radeon/tahiti_ce.bin");
50 MODULE_FIRMWARE("radeon/tahiti_rlc.bin");
52 MODULE_FIRMWARE("radeon/pitcairn_pfp.bin");
53 MODULE_FIRMWARE("radeon/pitcairn_me.bin");
54 MODULE_FIRMWARE("radeon/pitcairn_ce.bin");
55 MODULE_FIRMWARE("radeon/pitcairn_rlc.bin");
57 MODULE_FIRMWARE("radeon/verde_pfp.bin");
58 MODULE_FIRMWARE("radeon/verde_me.bin");
59 MODULE_FIRMWARE("radeon/verde_ce.bin");
60 MODULE_FIRMWARE("radeon/verde_rlc.bin");
62 MODULE_FIRMWARE("radeon/oland_pfp.bin");
63 MODULE_FIRMWARE("radeon/oland_me.bin");
64 MODULE_FIRMWARE("radeon/oland_ce.bin");
65 MODULE_FIRMWARE("radeon/oland_rlc.bin");
67 MODULE_FIRMWARE("radeon/hainan_pfp.bin");
68 MODULE_FIRMWARE("radeon/hainan_me.bin");
69 MODULE_FIRMWARE("radeon/hainan_ce.bin");
70 MODULE_FIRMWARE("radeon/hainan_rlc.bin");
72 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev);
73 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
74 //static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev);
75 static void gfx_v6_0_init_pg(struct amdgpu_device *adev);
77 #define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
78 #define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
79 #define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
80 #define MICRO_TILE_MODE(x) ((x) << 0)
81 #define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
82 #define BANK_WIDTH(x) ((x) << 14)
83 #define BANK_HEIGHT(x) ((x) << 16)
84 #define MACRO_TILE_ASPECT(x) ((x) << 18)
85 #define NUM_BANKS(x) ((x) << 20)
87 static const u32 verde_rlc_save_restore_register_list[] =
89 (0x8000 << 16) | (0x98f4 >> 2),
91 (0x8040 << 16) | (0x98f4 >> 2),
93 (0x8000 << 16) | (0xe80 >> 2),
95 (0x8040 << 16) | (0xe80 >> 2),
97 (0x8000 << 16) | (0x89bc >> 2),
99 (0x8040 << 16) | (0x89bc >> 2),
101 (0x8000 << 16) | (0x8c1c >> 2),
103 (0x8040 << 16) | (0x8c1c >> 2),
105 (0x9c00 << 16) | (0x98f0 >> 2),
107 (0x9c00 << 16) | (0xe7c >> 2),
109 (0x8000 << 16) | (0x9148 >> 2),
111 (0x8040 << 16) | (0x9148 >> 2),
113 (0x9c00 << 16) | (0x9150 >> 2),
115 (0x9c00 << 16) | (0x897c >> 2),
117 (0x9c00 << 16) | (0x8d8c >> 2),
119 (0x9c00 << 16) | (0xac54 >> 2),
122 (0x9c00 << 16) | (0x98f8 >> 2),
124 (0x9c00 << 16) | (0x9910 >> 2),
126 (0x9c00 << 16) | (0x9914 >> 2),
128 (0x9c00 << 16) | (0x9918 >> 2),
130 (0x9c00 << 16) | (0x991c >> 2),
132 (0x9c00 << 16) | (0x9920 >> 2),
134 (0x9c00 << 16) | (0x9924 >> 2),
136 (0x9c00 << 16) | (0x9928 >> 2),
138 (0x9c00 << 16) | (0x992c >> 2),
140 (0x9c00 << 16) | (0x9930 >> 2),
142 (0x9c00 << 16) | (0x9934 >> 2),
144 (0x9c00 << 16) | (0x9938 >> 2),
146 (0x9c00 << 16) | (0x993c >> 2),
148 (0x9c00 << 16) | (0x9940 >> 2),
150 (0x9c00 << 16) | (0x9944 >> 2),
152 (0x9c00 << 16) | (0x9948 >> 2),
154 (0x9c00 << 16) | (0x994c >> 2),
156 (0x9c00 << 16) | (0x9950 >> 2),
158 (0x9c00 << 16) | (0x9954 >> 2),
160 (0x9c00 << 16) | (0x9958 >> 2),
162 (0x9c00 << 16) | (0x995c >> 2),
164 (0x9c00 << 16) | (0x9960 >> 2),
166 (0x9c00 << 16) | (0x9964 >> 2),
168 (0x9c00 << 16) | (0x9968 >> 2),
170 (0x9c00 << 16) | (0x996c >> 2),
172 (0x9c00 << 16) | (0x9970 >> 2),
174 (0x9c00 << 16) | (0x9974 >> 2),
176 (0x9c00 << 16) | (0x9978 >> 2),
178 (0x9c00 << 16) | (0x997c >> 2),
180 (0x9c00 << 16) | (0x9980 >> 2),
182 (0x9c00 << 16) | (0x9984 >> 2),
184 (0x9c00 << 16) | (0x9988 >> 2),
186 (0x9c00 << 16) | (0x998c >> 2),
188 (0x9c00 << 16) | (0x8c00 >> 2),
190 (0x9c00 << 16) | (0x8c14 >> 2),
192 (0x9c00 << 16) | (0x8c04 >> 2),
194 (0x9c00 << 16) | (0x8c08 >> 2),
196 (0x8000 << 16) | (0x9b7c >> 2),
198 (0x8040 << 16) | (0x9b7c >> 2),
200 (0x8000 << 16) | (0xe84 >> 2),
202 (0x8040 << 16) | (0xe84 >> 2),
204 (0x8000 << 16) | (0x89c0 >> 2),
206 (0x8040 << 16) | (0x89c0 >> 2),
208 (0x8000 << 16) | (0x914c >> 2),
210 (0x8040 << 16) | (0x914c >> 2),
212 (0x8000 << 16) | (0x8c20 >> 2),
214 (0x8040 << 16) | (0x8c20 >> 2),
216 (0x8000 << 16) | (0x9354 >> 2),
218 (0x8040 << 16) | (0x9354 >> 2),
220 (0x9c00 << 16) | (0x9060 >> 2),
222 (0x9c00 << 16) | (0x9364 >> 2),
224 (0x9c00 << 16) | (0x9100 >> 2),
226 (0x9c00 << 16) | (0x913c >> 2),
228 (0x8000 << 16) | (0x90e0 >> 2),
230 (0x8000 << 16) | (0x90e4 >> 2),
232 (0x8000 << 16) | (0x90e8 >> 2),
234 (0x8040 << 16) | (0x90e0 >> 2),
236 (0x8040 << 16) | (0x90e4 >> 2),
238 (0x8040 << 16) | (0x90e8 >> 2),
240 (0x9c00 << 16) | (0x8bcc >> 2),
242 (0x9c00 << 16) | (0x8b24 >> 2),
244 (0x9c00 << 16) | (0x88c4 >> 2),
246 (0x9c00 << 16) | (0x8e50 >> 2),
248 (0x9c00 << 16) | (0x8c0c >> 2),
250 (0x9c00 << 16) | (0x8e58 >> 2),
252 (0x9c00 << 16) | (0x8e5c >> 2),
254 (0x9c00 << 16) | (0x9508 >> 2),
256 (0x9c00 << 16) | (0x950c >> 2),
258 (0x9c00 << 16) | (0x9494 >> 2),
260 (0x9c00 << 16) | (0xac0c >> 2),
262 (0x9c00 << 16) | (0xac10 >> 2),
264 (0x9c00 << 16) | (0xac14 >> 2),
266 (0x9c00 << 16) | (0xae00 >> 2),
268 (0x9c00 << 16) | (0xac08 >> 2),
270 (0x9c00 << 16) | (0x88d4 >> 2),
272 (0x9c00 << 16) | (0x88c8 >> 2),
274 (0x9c00 << 16) | (0x88cc >> 2),
276 (0x9c00 << 16) | (0x89b0 >> 2),
278 (0x9c00 << 16) | (0x8b10 >> 2),
280 (0x9c00 << 16) | (0x8a14 >> 2),
282 (0x9c00 << 16) | (0x9830 >> 2),
284 (0x9c00 << 16) | (0x9834 >> 2),
286 (0x9c00 << 16) | (0x9838 >> 2),
288 (0x9c00 << 16) | (0x9a10 >> 2),
290 (0x8000 << 16) | (0x9870 >> 2),
292 (0x8000 << 16) | (0x9874 >> 2),
294 (0x8001 << 16) | (0x9870 >> 2),
296 (0x8001 << 16) | (0x9874 >> 2),
298 (0x8040 << 16) | (0x9870 >> 2),
300 (0x8040 << 16) | (0x9874 >> 2),
302 (0x8041 << 16) | (0x9870 >> 2),
304 (0x8041 << 16) | (0x9874 >> 2),
309 static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)
311 const char *chip_name;
314 const struct gfx_firmware_header_v1_0 *cp_hdr;
315 const struct rlc_firmware_header_v1_0 *rlc_hdr;
319 switch (adev->asic_type) {
321 chip_name = "tahiti";
324 chip_name = "pitcairn";
333 chip_name = "hainan";
338 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
339 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
342 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
345 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
346 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
347 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
349 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
350 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
353 err = amdgpu_ucode_validate(adev->gfx.me_fw);
356 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
357 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
358 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
360 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
361 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
364 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
367 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
368 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
369 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
371 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
372 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
375 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
376 rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
377 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
378 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
382 pr_err("gfx6: Failed to load firmware \"%s\"\n", fw_name);
383 release_firmware(adev->gfx.pfp_fw);
384 adev->gfx.pfp_fw = NULL;
385 release_firmware(adev->gfx.me_fw);
386 adev->gfx.me_fw = NULL;
387 release_firmware(adev->gfx.ce_fw);
388 adev->gfx.ce_fw = NULL;
389 release_firmware(adev->gfx.rlc_fw);
390 adev->gfx.rlc_fw = NULL;
395 static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
397 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);
398 u32 reg_offset, split_equal_to_row_size, *tilemode;
400 memset(adev->gfx.config.tile_mode_array, 0, sizeof(adev->gfx.config.tile_mode_array));
401 tilemode = adev->gfx.config.tile_mode_array;
403 switch (adev->gfx.config.mem_row_size_in_kb) {
405 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
409 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
412 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
416 if (adev->asic_type == CHIP_VERDE) {
417 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
418 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
419 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
420 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
421 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
422 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
423 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
424 NUM_BANKS(ADDR_SURF_16_BANK);
425 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
426 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
427 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
428 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
429 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
430 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
431 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
432 NUM_BANKS(ADDR_SURF_16_BANK);
433 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
434 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
435 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
436 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
437 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
438 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
439 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
440 NUM_BANKS(ADDR_SURF_16_BANK);
441 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
442 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
443 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
444 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
445 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
446 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
447 NUM_BANKS(ADDR_SURF_8_BANK) |
448 TILE_SPLIT(split_equal_to_row_size);
449 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
450 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
451 PIPE_CONFIG(ADDR_SURF_P4_8x16);
452 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
453 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
454 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
455 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
456 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
457 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
458 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
459 NUM_BANKS(ADDR_SURF_4_BANK);
460 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
461 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
462 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
463 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
464 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
465 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
466 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
467 NUM_BANKS(ADDR_SURF_4_BANK);
468 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
469 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
470 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
471 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
472 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
473 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
474 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
475 NUM_BANKS(ADDR_SURF_2_BANK);
476 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
477 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
478 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
479 PIPE_CONFIG(ADDR_SURF_P4_8x16);
480 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
481 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
482 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
483 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
484 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
485 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
486 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
487 NUM_BANKS(ADDR_SURF_16_BANK);
488 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
489 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
490 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
491 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
492 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
493 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
494 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
495 NUM_BANKS(ADDR_SURF_16_BANK);
496 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
497 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
498 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
499 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
500 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
501 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
502 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
503 NUM_BANKS(ADDR_SURF_16_BANK);
504 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
505 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
506 PIPE_CONFIG(ADDR_SURF_P4_8x16);
507 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
508 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
509 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
510 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
511 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
512 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
513 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
514 NUM_BANKS(ADDR_SURF_16_BANK);
515 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
516 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
517 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
518 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
519 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
520 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
521 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
522 NUM_BANKS(ADDR_SURF_16_BANK);
523 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
524 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
525 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
526 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
527 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
528 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
529 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
530 NUM_BANKS(ADDR_SURF_16_BANK);
531 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
532 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
533 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
534 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
535 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
536 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
537 NUM_BANKS(ADDR_SURF_16_BANK) |
538 TILE_SPLIT(split_equal_to_row_size);
539 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
540 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
541 PIPE_CONFIG(ADDR_SURF_P4_8x16);
542 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
543 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
544 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
545 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
546 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
547 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
548 NUM_BANKS(ADDR_SURF_16_BANK) |
549 TILE_SPLIT(split_equal_to_row_size);
550 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
551 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
552 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
553 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
554 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
555 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
556 NUM_BANKS(ADDR_SURF_16_BANK) |
557 TILE_SPLIT(split_equal_to_row_size);
558 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
559 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
560 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
561 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
562 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
563 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
564 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
565 NUM_BANKS(ADDR_SURF_8_BANK);
566 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
567 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
568 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
569 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
570 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
571 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
572 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
573 NUM_BANKS(ADDR_SURF_8_BANK);
574 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
575 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
576 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
577 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
578 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
579 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
580 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
581 NUM_BANKS(ADDR_SURF_4_BANK);
582 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
583 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
584 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
585 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
586 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
587 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
588 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
589 NUM_BANKS(ADDR_SURF_4_BANK);
590 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
591 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
592 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
593 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
594 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
595 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
596 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
597 NUM_BANKS(ADDR_SURF_2_BANK);
598 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
599 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
600 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
601 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
602 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
603 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
604 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
605 NUM_BANKS(ADDR_SURF_2_BANK);
606 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
607 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
608 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
609 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
610 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
611 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
612 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
613 NUM_BANKS(ADDR_SURF_2_BANK);
614 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
615 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
616 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
617 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
618 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
619 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
620 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
621 NUM_BANKS(ADDR_SURF_2_BANK);
622 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
623 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
624 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
625 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
626 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
627 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
628 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
629 NUM_BANKS(ADDR_SURF_2_BANK);
630 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
631 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
632 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
633 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
634 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
635 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
636 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
637 NUM_BANKS(ADDR_SURF_2_BANK);
638 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
639 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
640 } else if (adev->asic_type == CHIP_OLAND) {
641 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
642 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
643 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
644 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
645 NUM_BANKS(ADDR_SURF_16_BANK) |
646 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
647 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
648 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
649 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
650 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
651 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
652 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
653 NUM_BANKS(ADDR_SURF_16_BANK) |
654 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
655 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
656 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
657 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
658 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
659 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
660 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
661 NUM_BANKS(ADDR_SURF_16_BANK) |
662 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
663 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
664 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
665 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
666 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
667 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
668 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
669 NUM_BANKS(ADDR_SURF_16_BANK) |
670 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
671 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
672 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
673 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
674 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
675 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
676 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
677 NUM_BANKS(ADDR_SURF_16_BANK) |
678 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
679 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
680 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
681 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
682 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
683 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
684 TILE_SPLIT(split_equal_to_row_size) |
685 NUM_BANKS(ADDR_SURF_16_BANK) |
686 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
687 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
688 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
689 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
690 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
691 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
692 TILE_SPLIT(split_equal_to_row_size) |
693 NUM_BANKS(ADDR_SURF_16_BANK) |
694 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
695 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
696 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
697 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
698 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
699 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
700 TILE_SPLIT(split_equal_to_row_size) |
701 NUM_BANKS(ADDR_SURF_16_BANK) |
702 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
703 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
704 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
705 tilemode[8] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
706 ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
707 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
708 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
709 NUM_BANKS(ADDR_SURF_16_BANK) |
710 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
711 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
712 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
713 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
714 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
715 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
716 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
717 NUM_BANKS(ADDR_SURF_16_BANK) |
718 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
719 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
720 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
721 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
722 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
723 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
724 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
725 NUM_BANKS(ADDR_SURF_16_BANK) |
726 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
727 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
728 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
729 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
730 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
731 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
732 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
733 NUM_BANKS(ADDR_SURF_16_BANK) |
734 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
735 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
736 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
737 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
738 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
739 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
740 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
741 NUM_BANKS(ADDR_SURF_16_BANK) |
742 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
743 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
744 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
745 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
746 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
747 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
748 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
749 NUM_BANKS(ADDR_SURF_16_BANK) |
750 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
751 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
752 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
753 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
754 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
755 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
756 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
757 NUM_BANKS(ADDR_SURF_16_BANK) |
758 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
759 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
760 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
761 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
762 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
763 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
764 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
765 NUM_BANKS(ADDR_SURF_16_BANK) |
766 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
767 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
768 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
769 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
770 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
771 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
772 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
773 NUM_BANKS(ADDR_SURF_16_BANK) |
774 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
775 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
776 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
777 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
778 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
779 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
780 TILE_SPLIT(split_equal_to_row_size) |
781 NUM_BANKS(ADDR_SURF_16_BANK) |
782 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
783 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
784 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
785 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
786 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
787 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
788 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
789 NUM_BANKS(ADDR_SURF_16_BANK) |
790 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
791 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
792 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
793 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
794 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
795 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
796 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
797 NUM_BANKS(ADDR_SURF_16_BANK) |
798 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
799 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
800 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
801 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
802 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
803 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
804 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
805 NUM_BANKS(ADDR_SURF_16_BANK) |
806 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
807 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
808 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
809 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
810 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
811 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
812 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
813 NUM_BANKS(ADDR_SURF_16_BANK) |
814 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
815 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
816 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
817 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
818 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
819 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
820 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
821 NUM_BANKS(ADDR_SURF_8_BANK) |
822 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
823 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
824 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1);
825 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
826 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
827 } else if (adev->asic_type == CHIP_HAINAN) {
828 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
829 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
830 PIPE_CONFIG(ADDR_SURF_P2) |
831 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
832 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
833 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
834 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
835 NUM_BANKS(ADDR_SURF_16_BANK);
836 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
837 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
838 PIPE_CONFIG(ADDR_SURF_P2) |
839 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
840 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
841 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
842 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
843 NUM_BANKS(ADDR_SURF_16_BANK);
844 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
845 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
846 PIPE_CONFIG(ADDR_SURF_P2) |
847 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
848 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
849 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
850 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
851 NUM_BANKS(ADDR_SURF_16_BANK);
852 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
853 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
854 PIPE_CONFIG(ADDR_SURF_P2) |
855 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
856 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
857 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
858 NUM_BANKS(ADDR_SURF_8_BANK) |
859 TILE_SPLIT(split_equal_to_row_size);
860 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
861 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
862 PIPE_CONFIG(ADDR_SURF_P2);
863 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
864 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
865 PIPE_CONFIG(ADDR_SURF_P2) |
866 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
867 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
868 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
869 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
870 NUM_BANKS(ADDR_SURF_8_BANK);
871 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
872 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
873 PIPE_CONFIG(ADDR_SURF_P2) |
874 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
875 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
876 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
877 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
878 NUM_BANKS(ADDR_SURF_8_BANK);
879 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
880 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
881 PIPE_CONFIG(ADDR_SURF_P2) |
882 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
883 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
884 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
885 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
886 NUM_BANKS(ADDR_SURF_4_BANK);
887 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
888 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
889 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
890 PIPE_CONFIG(ADDR_SURF_P2);
891 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
892 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
893 PIPE_CONFIG(ADDR_SURF_P2) |
894 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
895 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
896 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
897 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
898 NUM_BANKS(ADDR_SURF_16_BANK);
899 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
900 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
901 PIPE_CONFIG(ADDR_SURF_P2) |
902 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
903 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
904 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
905 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
906 NUM_BANKS(ADDR_SURF_16_BANK);
907 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
908 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
909 PIPE_CONFIG(ADDR_SURF_P2) |
910 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
911 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
912 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
913 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
914 NUM_BANKS(ADDR_SURF_16_BANK);
915 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
916 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
917 PIPE_CONFIG(ADDR_SURF_P2);
918 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
919 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
920 PIPE_CONFIG(ADDR_SURF_P2) |
921 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
922 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
923 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
924 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
925 NUM_BANKS(ADDR_SURF_16_BANK);
926 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
927 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
928 PIPE_CONFIG(ADDR_SURF_P2) |
929 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
930 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
931 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
932 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
933 NUM_BANKS(ADDR_SURF_16_BANK);
934 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
935 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
936 PIPE_CONFIG(ADDR_SURF_P2) |
937 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
938 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
939 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
940 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
941 NUM_BANKS(ADDR_SURF_16_BANK);
942 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
943 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
944 PIPE_CONFIG(ADDR_SURF_P2) |
945 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
946 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
947 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
948 NUM_BANKS(ADDR_SURF_16_BANK) |
949 TILE_SPLIT(split_equal_to_row_size);
950 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
951 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
952 PIPE_CONFIG(ADDR_SURF_P2);
953 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
954 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
955 PIPE_CONFIG(ADDR_SURF_P2) |
956 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
957 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
958 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
959 NUM_BANKS(ADDR_SURF_16_BANK) |
960 TILE_SPLIT(split_equal_to_row_size);
961 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
962 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
963 PIPE_CONFIG(ADDR_SURF_P2) |
964 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
965 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
966 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
967 NUM_BANKS(ADDR_SURF_16_BANK) |
968 TILE_SPLIT(split_equal_to_row_size);
969 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
970 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
971 PIPE_CONFIG(ADDR_SURF_P2) |
972 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
973 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
974 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
975 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
976 NUM_BANKS(ADDR_SURF_8_BANK);
977 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
978 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
979 PIPE_CONFIG(ADDR_SURF_P2) |
980 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
981 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
982 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
983 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
984 NUM_BANKS(ADDR_SURF_8_BANK);
985 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
986 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
987 PIPE_CONFIG(ADDR_SURF_P2) |
988 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
989 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
990 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
991 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
992 NUM_BANKS(ADDR_SURF_8_BANK);
993 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
994 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
995 PIPE_CONFIG(ADDR_SURF_P2) |
996 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
997 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
998 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
999 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1000 NUM_BANKS(ADDR_SURF_8_BANK);
1001 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1002 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1003 PIPE_CONFIG(ADDR_SURF_P2) |
1004 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1005 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1006 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1007 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1008 NUM_BANKS(ADDR_SURF_4_BANK);
1009 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1010 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1011 PIPE_CONFIG(ADDR_SURF_P2) |
1012 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1013 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1014 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1015 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1016 NUM_BANKS(ADDR_SURF_4_BANK);
1017 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1018 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1019 PIPE_CONFIG(ADDR_SURF_P2) |
1020 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1021 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1022 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1023 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1024 NUM_BANKS(ADDR_SURF_4_BANK);
1025 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1026 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1027 PIPE_CONFIG(ADDR_SURF_P2) |
1028 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1029 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1030 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1031 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1032 NUM_BANKS(ADDR_SURF_4_BANK);
1033 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1034 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1035 PIPE_CONFIG(ADDR_SURF_P2) |
1036 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1037 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1038 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1039 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1040 NUM_BANKS(ADDR_SURF_4_BANK);
1041 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1042 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1043 PIPE_CONFIG(ADDR_SURF_P2) |
1044 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1045 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1046 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1047 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1048 NUM_BANKS(ADDR_SURF_4_BANK);
1049 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1050 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
1051 } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) {
1052 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1053 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1054 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1055 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1056 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1057 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1058 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1059 NUM_BANKS(ADDR_SURF_16_BANK);
1060 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1061 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1062 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1063 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1064 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1065 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1066 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1067 NUM_BANKS(ADDR_SURF_16_BANK);
1068 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1069 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1070 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1071 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1072 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1073 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1074 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1075 NUM_BANKS(ADDR_SURF_16_BANK);
1076 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1077 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1078 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1079 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1080 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1081 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1082 NUM_BANKS(ADDR_SURF_4_BANK) |
1083 TILE_SPLIT(split_equal_to_row_size);
1084 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1085 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1086 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1087 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1088 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1089 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1090 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1091 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1092 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1093 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1094 NUM_BANKS(ADDR_SURF_2_BANK);
1095 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1096 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1097 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1098 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1099 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1100 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1101 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1102 NUM_BANKS(ADDR_SURF_2_BANK);
1103 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1104 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1105 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1106 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1107 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1108 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1109 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1110 NUM_BANKS(ADDR_SURF_2_BANK);
1111 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
1112 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1113 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1114 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1115 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1116 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1117 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1118 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1119 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1120 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1121 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1122 NUM_BANKS(ADDR_SURF_16_BANK);
1123 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1124 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1125 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1126 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1127 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1128 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1129 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1130 NUM_BANKS(ADDR_SURF_16_BANK);
1131 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1132 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1133 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1134 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1135 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1136 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1137 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1138 NUM_BANKS(ADDR_SURF_16_BANK);
1139 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1140 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1141 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1142 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1143 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1144 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1145 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1146 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1147 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1148 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1149 NUM_BANKS(ADDR_SURF_16_BANK);
1150 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1151 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1152 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1153 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1154 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1155 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1156 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1157 NUM_BANKS(ADDR_SURF_16_BANK);
1158 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1159 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1160 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1161 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1162 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1163 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1164 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1165 NUM_BANKS(ADDR_SURF_16_BANK);
1166 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1167 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1168 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1169 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1170 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1171 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1172 NUM_BANKS(ADDR_SURF_16_BANK) |
1173 TILE_SPLIT(split_equal_to_row_size);
1174 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1175 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1176 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1177 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1178 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1179 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1180 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1181 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1182 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1183 NUM_BANKS(ADDR_SURF_16_BANK) |
1184 TILE_SPLIT(split_equal_to_row_size);
1185 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1186 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1187 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1188 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1189 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1190 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1191 NUM_BANKS(ADDR_SURF_16_BANK) |
1192 TILE_SPLIT(split_equal_to_row_size);
1193 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1194 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1195 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1196 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1197 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1198 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1199 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1200 NUM_BANKS(ADDR_SURF_4_BANK);
1201 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1202 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1203 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1204 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1205 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1206 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1207 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1208 NUM_BANKS(ADDR_SURF_4_BANK);
1209 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1210 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1211 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1212 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1213 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1214 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1215 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1216 NUM_BANKS(ADDR_SURF_2_BANK);
1217 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1218 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1219 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1220 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1221 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1222 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1223 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1224 NUM_BANKS(ADDR_SURF_2_BANK);
1225 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1226 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1227 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1228 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1229 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1230 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1231 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1232 NUM_BANKS(ADDR_SURF_2_BANK);
1233 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1234 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1235 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1236 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1237 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1238 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1239 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1240 NUM_BANKS(ADDR_SURF_2_BANK);
1241 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1242 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1243 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1244 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1245 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1246 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1247 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1248 NUM_BANKS(ADDR_SURF_2_BANK);
1249 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1250 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1251 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1252 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1253 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1254 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1255 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1256 NUM_BANKS(ADDR_SURF_2_BANK);
1257 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1258 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1259 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1260 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1261 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1262 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1263 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1264 NUM_BANKS(ADDR_SURF_2_BANK);
1265 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1266 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1267 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1268 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1269 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1270 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1271 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1272 NUM_BANKS(ADDR_SURF_2_BANK);
1273 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1274 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
1276 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1280 static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1281 u32 sh_num, u32 instance)
1285 if (instance == 0xffffffff)
1286 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1288 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1290 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1291 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1292 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
1293 else if (se_num == 0xffffffff)
1294 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
1295 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
1296 else if (sh_num == 0xffffffff)
1297 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1298 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1300 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
1301 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1302 WREG32(mmGRBM_GFX_INDEX, data);
1305 static u32 gfx_v6_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1309 data = RREG32(mmCC_RB_BACKEND_DISABLE) |
1310 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1312 data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE);
1314 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se/
1315 adev->gfx.config.max_sh_per_se);
1317 return ~data & mask;
1320 static void gfx_v6_0_raster_config(struct amdgpu_device *adev, u32 *rconf)
1322 switch (adev->asic_type) {
1326 (2 << PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT) |
1327 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) |
1328 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) |
1329 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT) |
1330 (2 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT) |
1331 (2 << PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT) |
1332 (2 << PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT);
1336 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) |
1337 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) |
1338 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT);
1341 *rconf |= (1 << PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT);
1347 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1352 static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev,
1353 u32 raster_config, unsigned rb_mask,
1356 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
1357 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
1358 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
1359 unsigned rb_per_se = num_rb / num_se;
1360 unsigned se_mask[4];
1363 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
1364 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
1365 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
1366 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
1368 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
1369 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
1370 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
1372 for (se = 0; se < num_se; se++) {
1373 unsigned raster_config_se = raster_config;
1374 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
1375 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
1376 int idx = (se / 2) * 2;
1378 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
1379 raster_config_se &= ~PA_SC_RASTER_CONFIG__SE_MAP_MASK;
1382 raster_config_se |= RASTER_CONFIG_SE_MAP_3 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT;
1384 raster_config_se |= RASTER_CONFIG_SE_MAP_0 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT;
1387 pkr0_mask &= rb_mask;
1388 pkr1_mask &= rb_mask;
1389 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
1390 raster_config_se &= ~PA_SC_RASTER_CONFIG__PKR_MAP_MASK;
1393 raster_config_se |= RASTER_CONFIG_PKR_MAP_3 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT;
1395 raster_config_se |= RASTER_CONFIG_PKR_MAP_0 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT;
1398 if (rb_per_se >= 2) {
1399 unsigned rb0_mask = 1 << (se * rb_per_se);
1400 unsigned rb1_mask = rb0_mask << 1;
1402 rb0_mask &= rb_mask;
1403 rb1_mask &= rb_mask;
1404 if (!rb0_mask || !rb1_mask) {
1405 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK;
1409 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT;
1412 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT;
1415 if (rb_per_se > 2) {
1416 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
1417 rb1_mask = rb0_mask << 1;
1418 rb0_mask &= rb_mask;
1419 rb1_mask &= rb_mask;
1420 if (!rb0_mask || !rb1_mask) {
1421 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK;
1425 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT;
1428 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT;
1433 /* GRBM_GFX_INDEX has a different offset on SI */
1434 gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
1435 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
1438 /* GRBM_GFX_INDEX has a different offset on SI */
1439 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1442 static void gfx_v6_0_setup_rb(struct amdgpu_device *adev)
1446 u32 raster_config = 0;
1448 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1449 adev->gfx.config.max_sh_per_se;
1450 unsigned num_rb_pipes;
1452 mutex_lock(&adev->grbm_idx_mutex);
1453 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1454 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1455 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1456 data = gfx_v6_0_get_rb_active_bitmap(adev);
1457 active_rbs |= data <<
1458 ((i * adev->gfx.config.max_sh_per_se + j) *
1459 rb_bitmap_width_per_sh);
1462 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1464 adev->gfx.config.backend_enable_mask = active_rbs;
1465 adev->gfx.config.num_rbs = hweight32(active_rbs);
1467 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
1468 adev->gfx.config.max_shader_engines, 16);
1470 gfx_v6_0_raster_config(adev, &raster_config);
1472 if (!adev->gfx.config.backend_enable_mask ||
1473 adev->gfx.config.num_rbs >= num_rb_pipes)
1474 WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
1476 gfx_v6_0_write_harvested_raster_configs(adev, raster_config,
1477 adev->gfx.config.backend_enable_mask,
1480 /* cache the values for userspace */
1481 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1482 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1483 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1484 adev->gfx.config.rb_config[i][j].rb_backend_disable =
1485 RREG32(mmCC_RB_BACKEND_DISABLE);
1486 adev->gfx.config.rb_config[i][j].user_rb_backend_disable =
1487 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1488 adev->gfx.config.rb_config[i][j].raster_config =
1489 RREG32(mmPA_SC_RASTER_CONFIG);
1492 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1493 mutex_unlock(&adev->grbm_idx_mutex);
1496 static void gfx_v6_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
1504 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
1505 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
1507 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
1510 static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev)
1514 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) |
1515 RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
1517 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
1518 return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask;
1522 static void gfx_v6_0_setup_spi(struct amdgpu_device *adev)
1528 mutex_lock(&adev->grbm_idx_mutex);
1529 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1530 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1531 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1532 data = RREG32(mmSPI_STATIC_THREAD_MGMT_3);
1533 active_cu = gfx_v6_0_get_cu_enabled(adev);
1536 for (k = 0; k < 16; k++) {
1538 if (active_cu & mask) {
1540 WREG32(mmSPI_STATIC_THREAD_MGMT_3, data);
1546 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1547 mutex_unlock(&adev->grbm_idx_mutex);
1550 static void gfx_v6_0_config_init(struct amdgpu_device *adev)
1552 adev->gfx.config.double_offchip_lds_buf = 0;
1555 static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
1557 u32 gb_addr_config = 0;
1558 u32 mc_shared_chmap, mc_arb_ramcfg;
1560 u32 hdp_host_path_cntl;
1563 switch (adev->asic_type) {
1565 adev->gfx.config.max_shader_engines = 2;
1566 adev->gfx.config.max_tile_pipes = 12;
1567 adev->gfx.config.max_cu_per_sh = 8;
1568 adev->gfx.config.max_sh_per_se = 2;
1569 adev->gfx.config.max_backends_per_se = 4;
1570 adev->gfx.config.max_texture_channel_caches = 12;
1571 adev->gfx.config.max_gprs = 256;
1572 adev->gfx.config.max_gs_threads = 32;
1573 adev->gfx.config.max_hw_contexts = 8;
1575 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1576 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1577 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1578 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1579 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1582 adev->gfx.config.max_shader_engines = 2;
1583 adev->gfx.config.max_tile_pipes = 8;
1584 adev->gfx.config.max_cu_per_sh = 5;
1585 adev->gfx.config.max_sh_per_se = 2;
1586 adev->gfx.config.max_backends_per_se = 4;
1587 adev->gfx.config.max_texture_channel_caches = 8;
1588 adev->gfx.config.max_gprs = 256;
1589 adev->gfx.config.max_gs_threads = 32;
1590 adev->gfx.config.max_hw_contexts = 8;
1592 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1593 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1594 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1595 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1596 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1599 adev->gfx.config.max_shader_engines = 1;
1600 adev->gfx.config.max_tile_pipes = 4;
1601 adev->gfx.config.max_cu_per_sh = 5;
1602 adev->gfx.config.max_sh_per_se = 2;
1603 adev->gfx.config.max_backends_per_se = 4;
1604 adev->gfx.config.max_texture_channel_caches = 4;
1605 adev->gfx.config.max_gprs = 256;
1606 adev->gfx.config.max_gs_threads = 32;
1607 adev->gfx.config.max_hw_contexts = 8;
1609 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1610 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1611 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1612 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1613 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1616 adev->gfx.config.max_shader_engines = 1;
1617 adev->gfx.config.max_tile_pipes = 4;
1618 adev->gfx.config.max_cu_per_sh = 6;
1619 adev->gfx.config.max_sh_per_se = 1;
1620 adev->gfx.config.max_backends_per_se = 2;
1621 adev->gfx.config.max_texture_channel_caches = 4;
1622 adev->gfx.config.max_gprs = 256;
1623 adev->gfx.config.max_gs_threads = 16;
1624 adev->gfx.config.max_hw_contexts = 8;
1626 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1627 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1628 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1629 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1630 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1633 adev->gfx.config.max_shader_engines = 1;
1634 adev->gfx.config.max_tile_pipes = 4;
1635 adev->gfx.config.max_cu_per_sh = 5;
1636 adev->gfx.config.max_sh_per_se = 1;
1637 adev->gfx.config.max_backends_per_se = 1;
1638 adev->gfx.config.max_texture_channel_caches = 2;
1639 adev->gfx.config.max_gprs = 256;
1640 adev->gfx.config.max_gs_threads = 16;
1641 adev->gfx.config.max_hw_contexts = 8;
1643 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1644 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1645 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1646 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1647 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN;
1654 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
1655 WREG32(mmSRBM_INT_CNTL, 1);
1656 WREG32(mmSRBM_INT_ACK, 1);
1658 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
1660 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
1661 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
1662 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
1664 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1665 adev->gfx.config.mem_max_burst_length_bytes = 256;
1666 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
1667 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1668 if (adev->gfx.config.mem_row_size_in_kb > 4)
1669 adev->gfx.config.mem_row_size_in_kb = 4;
1670 adev->gfx.config.shader_engine_tile_size = 32;
1671 adev->gfx.config.num_gpus = 1;
1672 adev->gfx.config.multi_gpu_tile_size = 64;
1674 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
1675 switch (adev->gfx.config.mem_row_size_in_kb) {
1678 gb_addr_config |= 0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1681 gb_addr_config |= 1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1684 gb_addr_config |= 2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1687 gb_addr_config &= ~GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK;
1688 if (adev->gfx.config.max_shader_engines == 2)
1689 gb_addr_config |= 1 << GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT;
1690 adev->gfx.config.gb_addr_config = gb_addr_config;
1692 WREG32(mmGB_ADDR_CONFIG, gb_addr_config);
1693 WREG32(mmDMIF_ADDR_CONFIG, gb_addr_config);
1694 WREG32(mmDMIF_ADDR_CALC, gb_addr_config);
1695 WREG32(mmHDP_ADDR_CONFIG, gb_addr_config);
1696 WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1697 WREG32(mmDMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
1700 if (adev->has_uvd) {
1701 WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config);
1702 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
1703 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
1706 gfx_v6_0_tiling_mode_table_init(adev);
1708 gfx_v6_0_setup_rb(adev);
1710 gfx_v6_0_setup_spi(adev);
1712 gfx_v6_0_get_cu_info(adev);
1713 gfx_v6_0_config_init(adev);
1715 WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) |
1716 (0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT)));
1717 WREG32(mmCP_MEQ_THRESHOLDS, (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
1718 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
1720 sx_debug_1 = RREG32(mmSX_DEBUG_1);
1721 WREG32(mmSX_DEBUG_1, sx_debug_1);
1723 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
1725 WREG32(mmPA_SC_FIFO_SIZE, ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1726 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1727 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1728 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
1730 WREG32(mmVGT_NUM_INSTANCES, 1);
1731 WREG32(mmCP_PERFMON_CNTL, 0);
1732 WREG32(mmSQ_CONFIG, 0);
1733 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
1734 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
1736 WREG32(mmVGT_CACHE_INVALIDATION,
1737 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
1738 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
1740 WREG32(mmVGT_GS_VERTEX_REUSE, 16);
1741 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
1743 WREG32(mmCB_PERFCOUNTER0_SELECT0, 0);
1744 WREG32(mmCB_PERFCOUNTER0_SELECT1, 0);
1745 WREG32(mmCB_PERFCOUNTER1_SELECT0, 0);
1746 WREG32(mmCB_PERFCOUNTER1_SELECT1, 0);
1747 WREG32(mmCB_PERFCOUNTER2_SELECT0, 0);
1748 WREG32(mmCB_PERFCOUNTER2_SELECT1, 0);
1749 WREG32(mmCB_PERFCOUNTER3_SELECT0, 0);
1750 WREG32(mmCB_PERFCOUNTER3_SELECT1, 0);
1752 hdp_host_path_cntl = RREG32(mmHDP_HOST_PATH_CNTL);
1753 WREG32(mmHDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1755 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
1756 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
1762 static void gfx_v6_0_scratch_init(struct amdgpu_device *adev)
1764 adev->gfx.scratch.num_reg = 8;
1765 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
1766 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
1769 static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring)
1771 struct amdgpu_device *adev = ring->adev;
1777 r = amdgpu_gfx_scratch_get(adev, &scratch);
1779 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
1782 WREG32(scratch, 0xCAFEDEAD);
1784 r = amdgpu_ring_alloc(ring, 3);
1786 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r);
1787 amdgpu_gfx_scratch_free(adev, scratch);
1790 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1791 amdgpu_ring_write(ring, (scratch - PACKET3_SET_CONFIG_REG_START));
1792 amdgpu_ring_write(ring, 0xDEADBEEF);
1793 amdgpu_ring_commit(ring);
1795 for (i = 0; i < adev->usec_timeout; i++) {
1796 tmp = RREG32(scratch);
1797 if (tmp == 0xDEADBEEF)
1801 if (i < adev->usec_timeout) {
1802 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i);
1804 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
1805 ring->idx, scratch, tmp);
1808 amdgpu_gfx_scratch_free(adev, scratch);
1812 static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
1814 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
1815 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
1819 static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1820 u64 seq, unsigned flags)
1822 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
1823 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
1824 /* flush read cache over gart */
1825 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1826 amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START));
1827 amdgpu_ring_write(ring, 0);
1828 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1829 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1830 PACKET3_TC_ACTION_ENA |
1831 PACKET3_SH_KCACHE_ACTION_ENA |
1832 PACKET3_SH_ICACHE_ACTION_ENA);
1833 amdgpu_ring_write(ring, 0xFFFFFFFF);
1834 amdgpu_ring_write(ring, 0);
1835 amdgpu_ring_write(ring, 10); /* poll interval */
1836 /* EVENT_WRITE_EOP - flush caches, send int */
1837 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1838 amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
1839 amdgpu_ring_write(ring, addr & 0xfffffffc);
1840 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
1841 ((write64bit ? 2 : 1) << CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT) |
1842 ((int_sel ? 2 : 0) << CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT));
1843 amdgpu_ring_write(ring, lower_32_bits(seq));
1844 amdgpu_ring_write(ring, upper_32_bits(seq));
1847 static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
1848 struct amdgpu_ib *ib,
1849 unsigned vmid, bool ctx_switch)
1851 u32 header, control = 0;
1853 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
1855 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1856 amdgpu_ring_write(ring, 0);
1859 if (ib->flags & AMDGPU_IB_FLAG_CE)
1860 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
1862 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
1864 control |= ib->length_dw | (vmid << 24);
1866 amdgpu_ring_write(ring, header);
1867 amdgpu_ring_write(ring,
1871 (ib->gpu_addr & 0xFFFFFFFC));
1872 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
1873 amdgpu_ring_write(ring, control);
1877 * gfx_v6_0_ring_test_ib - basic ring IB test
1879 * @ring: amdgpu_ring structure holding ring information
1881 * Allocate an IB and execute it on the gfx ring (SI).
1882 * Provides a basic gfx ring test to verify that IBs are working.
1883 * Returns 0 on success, error on failure.
1885 static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1887 struct amdgpu_device *adev = ring->adev;
1888 struct amdgpu_ib ib;
1889 struct dma_fence *f = NULL;
1894 r = amdgpu_gfx_scratch_get(adev, &scratch);
1896 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
1899 WREG32(scratch, 0xCAFEDEAD);
1900 memset(&ib, 0, sizeof(ib));
1901 r = amdgpu_ib_get(adev, NULL, 256, &ib);
1903 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1906 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
1907 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_START));
1908 ib.ptr[2] = 0xDEADBEEF;
1911 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1915 r = dma_fence_wait_timeout(f, false, timeout);
1917 DRM_ERROR("amdgpu: IB test timed out\n");
1921 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1924 tmp = RREG32(scratch);
1925 if (tmp == 0xDEADBEEF) {
1926 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
1929 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
1935 amdgpu_ib_free(adev, &ib, NULL);
1938 amdgpu_gfx_scratch_free(adev, scratch);
1942 static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
1946 WREG32(mmCP_ME_CNTL, 0);
1948 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK |
1949 CP_ME_CNTL__PFP_HALT_MASK |
1950 CP_ME_CNTL__CE_HALT_MASK));
1951 WREG32(mmSCRATCH_UMSK, 0);
1952 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1953 adev->gfx.gfx_ring[i].ready = false;
1954 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1955 adev->gfx.compute_ring[i].ready = false;
1960 static int gfx_v6_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
1963 const struct gfx_firmware_header_v1_0 *pfp_hdr;
1964 const struct gfx_firmware_header_v1_0 *ce_hdr;
1965 const struct gfx_firmware_header_v1_0 *me_hdr;
1966 const __le32 *fw_data;
1969 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
1972 gfx_v6_0_cp_gfx_enable(adev, false);
1973 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
1974 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
1975 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
1977 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
1978 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
1979 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
1982 fw_data = (const __le32 *)
1983 (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
1984 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
1985 WREG32(mmCP_PFP_UCODE_ADDR, 0);
1986 for (i = 0; i < fw_size; i++)
1987 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
1988 WREG32(mmCP_PFP_UCODE_ADDR, 0);
1991 fw_data = (const __le32 *)
1992 (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
1993 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
1994 WREG32(mmCP_CE_UCODE_ADDR, 0);
1995 for (i = 0; i < fw_size; i++)
1996 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
1997 WREG32(mmCP_CE_UCODE_ADDR, 0);
2000 fw_data = (const __be32 *)
2001 (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2002 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2003 WREG32(mmCP_ME_RAM_WADDR, 0);
2004 for (i = 0; i < fw_size; i++)
2005 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2006 WREG32(mmCP_ME_RAM_WADDR, 0);
2008 WREG32(mmCP_PFP_UCODE_ADDR, 0);
2009 WREG32(mmCP_CE_UCODE_ADDR, 0);
2010 WREG32(mmCP_ME_RAM_WADDR, 0);
2011 WREG32(mmCP_ME_RAM_RADDR, 0);
2015 static int gfx_v6_0_cp_gfx_start(struct amdgpu_device *adev)
2017 const struct cs_section_def *sect = NULL;
2018 const struct cs_extent_def *ext = NULL;
2019 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2022 r = amdgpu_ring_alloc(ring, 7 + 4);
2024 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2027 amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2028 amdgpu_ring_write(ring, 0x1);
2029 amdgpu_ring_write(ring, 0x0);
2030 amdgpu_ring_write(ring, adev->gfx.config.max_hw_contexts - 1);
2031 amdgpu_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2032 amdgpu_ring_write(ring, 0);
2033 amdgpu_ring_write(ring, 0);
2035 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2036 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2037 amdgpu_ring_write(ring, 0xc000);
2038 amdgpu_ring_write(ring, 0xe000);
2039 amdgpu_ring_commit(ring);
2041 gfx_v6_0_cp_gfx_enable(adev, true);
2043 r = amdgpu_ring_alloc(ring, gfx_v6_0_get_csb_size(adev) + 10);
2045 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2049 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2050 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2052 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2053 for (ext = sect->section; ext->extent != NULL; ++ext) {
2054 if (sect->id == SECT_CONTEXT) {
2055 amdgpu_ring_write(ring,
2056 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2057 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2058 for (i = 0; i < ext->reg_count; i++)
2059 amdgpu_ring_write(ring, ext->extent[i]);
2064 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2065 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2067 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2068 amdgpu_ring_write(ring, 0);
2070 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2071 amdgpu_ring_write(ring, 0x00000316);
2072 amdgpu_ring_write(ring, 0x0000000e);
2073 amdgpu_ring_write(ring, 0x00000010);
2075 amdgpu_ring_commit(ring);
2080 static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev)
2082 struct amdgpu_ring *ring;
2088 WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
2089 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2091 /* Set the write pointer delay */
2092 WREG32(mmCP_RB_WPTR_DELAY, 0);
2094 WREG32(mmCP_DEBUG, 0);
2095 WREG32(mmSCRATCH_ADDR, 0);
2097 /* ring 0 - compute and gfx */
2098 /* Set ring buffer size */
2099 ring = &adev->gfx.gfx_ring[0];
2100 rb_bufsz = order_base_2(ring->ring_size / 8);
2101 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2104 tmp |= BUF_SWAP_32BIT;
2106 WREG32(mmCP_RB0_CNTL, tmp);
2108 /* Initialize the ring buffer's read and write pointers */
2109 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2111 WREG32(mmCP_RB0_WPTR, ring->wptr);
2113 /* set the wb address whether it's enabled or not */
2114 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2115 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2116 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2118 WREG32(mmSCRATCH_UMSK, 0);
2121 WREG32(mmCP_RB0_CNTL, tmp);
2123 WREG32(mmCP_RB0_BASE, ring->gpu_addr >> 8);
2125 /* start the rings */
2126 gfx_v6_0_cp_gfx_start(adev);
2128 r = amdgpu_ring_test_ring(ring);
2130 ring->ready = false;
2137 static u64 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
2139 return ring->adev->wb.wb[ring->rptr_offs];
2142 static u64 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
2144 struct amdgpu_device *adev = ring->adev;
2146 if (ring == &adev->gfx.gfx_ring[0])
2147 return RREG32(mmCP_RB0_WPTR);
2148 else if (ring == &adev->gfx.compute_ring[0])
2149 return RREG32(mmCP_RB1_WPTR);
2150 else if (ring == &adev->gfx.compute_ring[1])
2151 return RREG32(mmCP_RB2_WPTR);
2156 static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2158 struct amdgpu_device *adev = ring->adev;
2160 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2161 (void)RREG32(mmCP_RB0_WPTR);
2164 static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2166 struct amdgpu_device *adev = ring->adev;
2168 if (ring == &adev->gfx.compute_ring[0]) {
2169 WREG32(mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
2170 (void)RREG32(mmCP_RB1_WPTR);
2171 } else if (ring == &adev->gfx.compute_ring[1]) {
2172 WREG32(mmCP_RB2_WPTR, lower_32_bits(ring->wptr));
2173 (void)RREG32(mmCP_RB2_WPTR);
2180 static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev)
2182 struct amdgpu_ring *ring;
2188 /* ring1 - compute only */
2189 /* Set ring buffer size */
2191 ring = &adev->gfx.compute_ring[0];
2192 rb_bufsz = order_base_2(ring->ring_size / 8);
2193 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2195 tmp |= BUF_SWAP_32BIT;
2197 WREG32(mmCP_RB1_CNTL, tmp);
2199 WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK);
2201 WREG32(mmCP_RB1_WPTR, ring->wptr);
2203 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2204 WREG32(mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
2205 WREG32(mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2208 WREG32(mmCP_RB1_CNTL, tmp);
2209 WREG32(mmCP_RB1_BASE, ring->gpu_addr >> 8);
2211 ring = &adev->gfx.compute_ring[1];
2212 rb_bufsz = order_base_2(ring->ring_size / 8);
2213 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2215 tmp |= BUF_SWAP_32BIT;
2217 WREG32(mmCP_RB2_CNTL, tmp);
2219 WREG32(mmCP_RB2_CNTL, tmp | CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK);
2221 WREG32(mmCP_RB2_WPTR, ring->wptr);
2222 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2223 WREG32(mmCP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr));
2224 WREG32(mmCP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2227 WREG32(mmCP_RB2_CNTL, tmp);
2228 WREG32(mmCP_RB2_BASE, ring->gpu_addr >> 8);
2230 adev->gfx.compute_ring[0].ready = false;
2231 adev->gfx.compute_ring[1].ready = false;
2233 for (i = 0; i < 2; i++) {
2234 r = amdgpu_ring_test_ring(&adev->gfx.compute_ring[i]);
2237 adev->gfx.compute_ring[i].ready = true;
2243 static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable)
2245 gfx_v6_0_cp_gfx_enable(adev, enable);
2248 static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev)
2250 return gfx_v6_0_cp_gfx_load_microcode(adev);
2253 static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
2256 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
2261 tmp |= (CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK |
2262 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK);
2264 tmp &= ~(CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK |
2265 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK);
2266 WREG32(mmCP_INT_CNTL_RING0, tmp);
2269 /* read a gfx register */
2270 tmp = RREG32(mmDB_DEPTH_INFO);
2272 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS;
2273 for (i = 0; i < adev->usec_timeout; i++) {
2274 if ((RREG32(mmRLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS))
2281 static int gfx_v6_0_cp_resume(struct amdgpu_device *adev)
2285 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2287 r = gfx_v6_0_cp_load_microcode(adev);
2291 r = gfx_v6_0_cp_gfx_resume(adev);
2294 r = gfx_v6_0_cp_compute_resume(adev);
2298 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2303 static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
2305 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2306 uint32_t seq = ring->fence_drv.sync_seq;
2307 uint64_t addr = ring->fence_drv.gpu_addr;
2309 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2310 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
2311 WAIT_REG_MEM_FUNCTION(3) | /* equal */
2312 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
2313 amdgpu_ring_write(ring, addr & 0xfffffffc);
2314 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
2315 amdgpu_ring_write(ring, seq);
2316 amdgpu_ring_write(ring, 0xffffffff);
2317 amdgpu_ring_write(ring, 4); /* poll interval */
2320 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
2321 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2322 amdgpu_ring_write(ring, 0);
2323 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2324 amdgpu_ring_write(ring, 0);
2328 static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
2329 unsigned vmid, uint64_t pd_addr)
2331 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2333 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
2335 /* wait for the invalidate to complete */
2336 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2337 amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */
2338 WAIT_REG_MEM_ENGINE(0))); /* me */
2339 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
2340 amdgpu_ring_write(ring, 0);
2341 amdgpu_ring_write(ring, 0); /* ref */
2342 amdgpu_ring_write(ring, 0); /* mask */
2343 amdgpu_ring_write(ring, 0x20); /* poll interval */
2346 /* sync PFP to ME, otherwise we might get invalid PFP reads */
2347 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2348 amdgpu_ring_write(ring, 0x0);
2350 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
2351 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2352 amdgpu_ring_write(ring, 0);
2353 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2354 amdgpu_ring_write(ring, 0);
2358 static void gfx_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,
2359 uint32_t reg, uint32_t val)
2361 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2363 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2364 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
2365 WRITE_DATA_DST_SEL(0)));
2366 amdgpu_ring_write(ring, reg);
2367 amdgpu_ring_write(ring, 0);
2368 amdgpu_ring_write(ring, val);
2371 static void gfx_v6_0_rlc_fini(struct amdgpu_device *adev)
2373 amdgpu_bo_free_kernel(&adev->gfx.rlc.save_restore_obj, NULL, NULL);
2374 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, NULL, NULL);
2375 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, NULL, NULL);
2378 static int gfx_v6_0_rlc_init(struct amdgpu_device *adev)
2381 volatile u32 *dst_ptr;
2383 u64 reg_list_mc_addr;
2384 const struct cs_section_def *cs_data;
2387 adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list;
2388 adev->gfx.rlc.reg_list_size =
2389 (u32)ARRAY_SIZE(verde_rlc_save_restore_register_list);
2391 adev->gfx.rlc.cs_data = si_cs_data;
2392 src_ptr = adev->gfx.rlc.reg_list;
2393 dws = adev->gfx.rlc.reg_list_size;
2394 cs_data = adev->gfx.rlc.cs_data;
2397 /* save restore block */
2398 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
2399 AMDGPU_GEM_DOMAIN_VRAM,
2400 &adev->gfx.rlc.save_restore_obj,
2401 &adev->gfx.rlc.save_restore_gpu_addr,
2402 (void **)&adev->gfx.rlc.sr_ptr);
2404 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n",
2406 gfx_v6_0_rlc_fini(adev);
2410 /* write the sr buffer */
2411 dst_ptr = adev->gfx.rlc.sr_ptr;
2412 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
2413 dst_ptr[i] = cpu_to_le32(src_ptr[i]);
2415 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);
2416 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
2420 /* clear state block */
2421 adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev);
2422 dws = adev->gfx.rlc.clear_state_size + (256 / 4);
2424 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
2425 AMDGPU_GEM_DOMAIN_VRAM,
2426 &adev->gfx.rlc.clear_state_obj,
2427 &adev->gfx.rlc.clear_state_gpu_addr,
2428 (void **)&adev->gfx.rlc.cs_ptr);
2430 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
2431 gfx_v6_0_rlc_fini(adev);
2435 /* set up the cs buffer */
2436 dst_ptr = adev->gfx.rlc.cs_ptr;
2437 reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256;
2438 dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr));
2439 dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr));
2440 dst_ptr[2] = cpu_to_le32(adev->gfx.rlc.clear_state_size);
2441 gfx_v6_0_get_csb_buffer(adev, &dst_ptr[(256/4)]);
2442 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
2443 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
2449 static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
2451 WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
2454 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2455 WREG32(mmSPI_LB_CU_MASK, 0x00ff);
2459 static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2463 for (i = 0; i < adev->usec_timeout; i++) {
2464 if (RREG32(mmRLC_SERDES_MASTER_BUSY_0) == 0)
2469 for (i = 0; i < adev->usec_timeout; i++) {
2470 if (RREG32(mmRLC_SERDES_MASTER_BUSY_1) == 0)
2476 static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
2480 tmp = RREG32(mmRLC_CNTL);
2482 WREG32(mmRLC_CNTL, rlc);
2485 static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev)
2489 orig = data = RREG32(mmRLC_CNTL);
2491 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
2492 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
2493 WREG32(mmRLC_CNTL, data);
2495 gfx_v6_0_wait_for_rlc_serdes(adev);
2501 static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev)
2503 WREG32(mmRLC_CNTL, 0);
2505 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2506 gfx_v6_0_wait_for_rlc_serdes(adev);
2509 static void gfx_v6_0_rlc_start(struct amdgpu_device *adev)
2511 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
2513 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2518 static void gfx_v6_0_rlc_reset(struct amdgpu_device *adev)
2520 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2522 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2526 static bool gfx_v6_0_lbpw_supported(struct amdgpu_device *adev)
2530 /* Enable LBPW only for DDR3 */
2531 tmp = RREG32(mmMC_SEQ_MISC0);
2532 if ((tmp & 0xF0000000) == 0xB0000000)
2537 static void gfx_v6_0_init_cg(struct amdgpu_device *adev)
2541 static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev)
2544 const struct rlc_firmware_header_v1_0 *hdr;
2545 const __le32 *fw_data;
2549 if (!adev->gfx.rlc_fw)
2552 gfx_v6_0_rlc_stop(adev);
2553 gfx_v6_0_rlc_reset(adev);
2554 gfx_v6_0_init_pg(adev);
2555 gfx_v6_0_init_cg(adev);
2557 WREG32(mmRLC_RL_BASE, 0);
2558 WREG32(mmRLC_RL_SIZE, 0);
2559 WREG32(mmRLC_LB_CNTL, 0);
2560 WREG32(mmRLC_LB_CNTR_MAX, 0xffffffff);
2561 WREG32(mmRLC_LB_CNTR_INIT, 0);
2562 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
2564 WREG32(mmRLC_MC_CNTL, 0);
2565 WREG32(mmRLC_UCODE_CNTL, 0);
2567 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
2568 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2569 fw_data = (const __le32 *)
2570 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2572 amdgpu_ucode_print_rlc_hdr(&hdr->header);
2574 for (i = 0; i < fw_size; i++) {
2575 WREG32(mmRLC_UCODE_ADDR, i);
2576 WREG32(mmRLC_UCODE_DATA, le32_to_cpup(fw_data++));
2578 WREG32(mmRLC_UCODE_ADDR, 0);
2580 gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev));
2581 gfx_v6_0_rlc_start(adev);
2586 static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
2588 u32 data, orig, tmp;
2590 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
2592 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
2593 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2595 WREG32(mmRLC_GCPM_GENERAL_3, 0x00000080);
2597 tmp = gfx_v6_0_halt_rlc(adev);
2599 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2600 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2601 WREG32(mmRLC_SERDES_WR_CTRL, 0x00b000ff);
2603 gfx_v6_0_wait_for_rlc_serdes(adev);
2604 gfx_v6_0_update_rlc(adev, tmp);
2606 WREG32(mmRLC_SERDES_WR_CTRL, 0x007000ff);
2608 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
2610 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2612 RREG32(mmCB_CGTT_SCLK_CTRL);
2613 RREG32(mmCB_CGTT_SCLK_CTRL);
2614 RREG32(mmCB_CGTT_SCLK_CTRL);
2615 RREG32(mmCB_CGTT_SCLK_CTRL);
2617 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
2621 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
2625 static void gfx_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
2628 u32 data, orig, tmp = 0;
2630 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
2631 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
2634 WREG32(mmCGTS_SM_CTRL_REG, data);
2636 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
2637 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
2638 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2640 WREG32(mmCP_MEM_SLP_CNTL, data);
2643 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
2646 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
2648 tmp = gfx_v6_0_halt_rlc(adev);
2650 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2651 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2652 WREG32(mmRLC_SERDES_WR_CTRL, 0x00d000ff);
2654 gfx_v6_0_update_rlc(adev, tmp);
2656 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
2659 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
2661 data = RREG32(mmCP_MEM_SLP_CNTL);
2662 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
2663 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2664 WREG32(mmCP_MEM_SLP_CNTL, data);
2666 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
2667 data |= CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK | CGTS_SM_CTRL_REG__OVERRIDE_MASK;
2669 WREG32(mmCGTS_SM_CTRL_REG, data);
2671 tmp = gfx_v6_0_halt_rlc(adev);
2673 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2674 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2675 WREG32(mmRLC_SERDES_WR_CTRL, 0x00e000ff);
2677 gfx_v6_0_update_rlc(adev, tmp);
2681 static void gfx_v6_0_update_cg(struct amdgpu_device *adev,
2684 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2686 gfx_v6_0_enable_mgcg(adev, true);
2687 gfx_v6_0_enable_cgcg(adev, true);
2689 gfx_v6_0_enable_cgcg(adev, false);
2690 gfx_v6_0_enable_mgcg(adev, false);
2692 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2696 static void gfx_v6_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
2701 static void gfx_v6_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
2706 static void gfx_v6_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
2710 orig = data = RREG32(mmRLC_PG_CNTL);
2711 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
2716 WREG32(mmRLC_PG_CNTL, data);
2719 static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
2723 static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev)
2725 const __le32 *fw_data;
2726 volatile u32 *dst_ptr;
2727 int me, i, max_me = 4;
2729 u32 table_offset, table_size;
2731 if (adev->asic_type == CHIP_KAVERI)
2734 if (adev->gfx.rlc.cp_table_ptr == NULL)
2737 dst_ptr = adev->gfx.rlc.cp_table_ptr;
2738 for (me = 0; me < max_me; me++) {
2740 const struct gfx_firmware_header_v1_0 *hdr =
2741 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2742 fw_data = (const __le32 *)
2743 (adev->gfx.ce_fw->data +
2744 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2745 table_offset = le32_to_cpu(hdr->jt_offset);
2746 table_size = le32_to_cpu(hdr->jt_size);
2747 } else if (me == 1) {
2748 const struct gfx_firmware_header_v1_0 *hdr =
2749 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2750 fw_data = (const __le32 *)
2751 (adev->gfx.pfp_fw->data +
2752 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2753 table_offset = le32_to_cpu(hdr->jt_offset);
2754 table_size = le32_to_cpu(hdr->jt_size);
2755 } else if (me == 2) {
2756 const struct gfx_firmware_header_v1_0 *hdr =
2757 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2758 fw_data = (const __le32 *)
2759 (adev->gfx.me_fw->data +
2760 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2761 table_offset = le32_to_cpu(hdr->jt_offset);
2762 table_size = le32_to_cpu(hdr->jt_size);
2763 } else if (me == 3) {
2764 const struct gfx_firmware_header_v1_0 *hdr =
2765 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2766 fw_data = (const __le32 *)
2767 (adev->gfx.mec_fw->data +
2768 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2769 table_offset = le32_to_cpu(hdr->jt_offset);
2770 table_size = le32_to_cpu(hdr->jt_size);
2772 const struct gfx_firmware_header_v1_0 *hdr =
2773 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2774 fw_data = (const __le32 *)
2775 (adev->gfx.mec2_fw->data +
2776 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2777 table_offset = le32_to_cpu(hdr->jt_offset);
2778 table_size = le32_to_cpu(hdr->jt_size);
2781 for (i = 0; i < table_size; i ++) {
2782 dst_ptr[bo_offset + i] =
2783 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
2786 bo_offset += table_size;
2790 static void gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device *adev,
2793 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
2794 WREG32(mmRLC_TTOP_D, RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10));
2795 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1);
2796 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 1);
2798 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0);
2799 (void)RREG32(mmDB_RENDER_CONTROL);
2803 static void gfx_v6_0_init_ao_cu_mask(struct amdgpu_device *adev)
2807 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
2809 tmp = RREG32(mmRLC_MAX_PG_CU);
2810 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
2811 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
2812 WREG32(mmRLC_MAX_PG_CU, tmp);
2815 static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
2820 orig = data = RREG32(mmRLC_PG_CNTL);
2821 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
2822 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2824 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2826 WREG32(mmRLC_PG_CNTL, data);
2829 static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
2834 orig = data = RREG32(mmRLC_PG_CNTL);
2835 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
2836 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2838 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2840 WREG32(mmRLC_PG_CNTL, data);
2843 static void gfx_v6_0_init_gfx_cgpg(struct amdgpu_device *adev)
2847 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2848 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1);
2849 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2851 tmp = RREG32(mmRLC_AUTO_PG_CTRL);
2852 tmp &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
2853 tmp |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
2854 tmp &= ~RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK;
2855 WREG32(mmRLC_AUTO_PG_CTRL, tmp);
2858 static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
2860 gfx_v6_0_enable_gfx_cgpg(adev, enable);
2861 gfx_v6_0_enable_gfx_static_mgpg(adev, enable);
2862 gfx_v6_0_enable_gfx_dynamic_mgpg(adev, enable);
2865 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev)
2868 const struct cs_section_def *sect = NULL;
2869 const struct cs_extent_def *ext = NULL;
2871 if (adev->gfx.rlc.cs_data == NULL)
2874 /* begin clear state */
2876 /* context control state */
2879 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2880 for (ext = sect->section; ext->extent != NULL; ++ext) {
2881 if (sect->id == SECT_CONTEXT)
2882 count += 2 + ext->reg_count;
2887 /* pa_sc_raster_config */
2889 /* end clear state */
2897 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev,
2898 volatile u32 *buffer)
2901 const struct cs_section_def *sect = NULL;
2902 const struct cs_extent_def *ext = NULL;
2904 if (adev->gfx.rlc.cs_data == NULL)
2909 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2910 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2911 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2912 buffer[count++] = cpu_to_le32(0x80000000);
2913 buffer[count++] = cpu_to_le32(0x80000000);
2915 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2916 for (ext = sect->section; ext->extent != NULL; ++ext) {
2917 if (sect->id == SECT_CONTEXT) {
2919 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2920 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000);
2921 for (i = 0; i < ext->reg_count; i++)
2922 buffer[count++] = cpu_to_le32(ext->extent[i]);
2929 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
2930 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2931 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config);
2933 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2934 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
2936 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
2937 buffer[count++] = cpu_to_le32(0);
2940 static void gfx_v6_0_init_pg(struct amdgpu_device *adev)
2942 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2943 AMD_PG_SUPPORT_GFX_SMG |
2944 AMD_PG_SUPPORT_GFX_DMG |
2946 AMD_PG_SUPPORT_GDS |
2947 AMD_PG_SUPPORT_RLC_SMU_HS)) {
2948 gfx_v6_0_enable_sclk_slowdown_on_pu(adev, true);
2949 gfx_v6_0_enable_sclk_slowdown_on_pd(adev, true);
2950 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
2951 gfx_v6_0_init_gfx_cgpg(adev);
2952 gfx_v6_0_enable_cp_pg(adev, true);
2953 gfx_v6_0_enable_gds_pg(adev, true);
2955 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2956 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2959 gfx_v6_0_init_ao_cu_mask(adev);
2960 gfx_v6_0_update_gfx_pg(adev, true);
2963 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2964 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2968 static void gfx_v6_0_fini_pg(struct amdgpu_device *adev)
2970 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2971 AMD_PG_SUPPORT_GFX_SMG |
2972 AMD_PG_SUPPORT_GFX_DMG |
2974 AMD_PG_SUPPORT_GDS |
2975 AMD_PG_SUPPORT_RLC_SMU_HS)) {
2976 gfx_v6_0_update_gfx_pg(adev, false);
2977 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
2978 gfx_v6_0_enable_cp_pg(adev, false);
2979 gfx_v6_0_enable_gds_pg(adev, false);
2984 static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev)
2988 mutex_lock(&adev->gfx.gpu_clock_mutex);
2989 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
2990 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
2991 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
2992 mutex_unlock(&adev->gfx.gpu_clock_mutex);
2996 static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
2998 if (flags & AMDGPU_HAVE_CTX_SWITCH)
2999 gfx_v6_0_ring_emit_vgt_flush(ring);
3000 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3001 amdgpu_ring_write(ring, 0x80000000);
3002 amdgpu_ring_write(ring, 0);
3006 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
3008 WREG32(mmSQ_IND_INDEX,
3009 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
3010 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
3011 (address << SQ_IND_INDEX__INDEX__SHIFT) |
3012 (SQ_IND_INDEX__FORCE_READ_MASK));
3013 return RREG32(mmSQ_IND_DATA);
3016 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
3017 uint32_t wave, uint32_t thread,
3018 uint32_t regno, uint32_t num, uint32_t *out)
3020 WREG32(mmSQ_IND_INDEX,
3021 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
3022 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
3023 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
3024 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
3025 (SQ_IND_INDEX__FORCE_READ_MASK) |
3026 (SQ_IND_INDEX__AUTO_INCR_MASK));
3028 *(out++) = RREG32(mmSQ_IND_DATA);
3031 static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
3033 /* type 0 wave data */
3034 dst[(*no_fields)++] = 0;
3035 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
3036 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
3037 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
3038 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
3039 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
3040 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
3041 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
3042 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
3043 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
3044 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
3045 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
3046 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
3047 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO);
3048 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI);
3049 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO);
3050 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);
3051 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
3052 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
3055 static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
3056 uint32_t wave, uint32_t start,
3057 uint32_t size, uint32_t *dst)
3060 adev, simd, wave, 0,
3061 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
3064 static void gfx_v6_0_select_me_pipe_q(struct amdgpu_device *adev,
3065 u32 me, u32 pipe, u32 q)
3067 DRM_INFO("Not implemented\n");
3070 static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = {
3071 .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter,
3072 .select_se_sh = &gfx_v6_0_select_se_sh,
3073 .read_wave_data = &gfx_v6_0_read_wave_data,
3074 .read_wave_sgprs = &gfx_v6_0_read_wave_sgprs,
3075 .select_me_pipe_q = &gfx_v6_0_select_me_pipe_q
3078 static int gfx_v6_0_early_init(void *handle)
3080 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3082 adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS;
3083 adev->gfx.num_compute_rings = GFX6_NUM_COMPUTE_RINGS;
3084 adev->gfx.funcs = &gfx_v6_0_gfx_funcs;
3085 gfx_v6_0_set_ring_funcs(adev);
3086 gfx_v6_0_set_irq_funcs(adev);
3091 static int gfx_v6_0_sw_init(void *handle)
3093 struct amdgpu_ring *ring;
3094 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3097 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq);
3101 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 184, &adev->gfx.priv_reg_irq);
3105 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 185, &adev->gfx.priv_inst_irq);
3109 gfx_v6_0_scratch_init(adev);
3111 r = gfx_v6_0_init_microcode(adev);
3113 DRM_ERROR("Failed to load gfx firmware!\n");
3117 r = gfx_v6_0_rlc_init(adev);
3119 DRM_ERROR("Failed to init rlc BOs!\n");
3123 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3124 ring = &adev->gfx.gfx_ring[i];
3125 ring->ring_obj = NULL;
3126 sprintf(ring->name, "gfx");
3127 r = amdgpu_ring_init(adev, ring, 1024,
3128 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
3133 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3136 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
3137 DRM_ERROR("Too many (%d) compute rings!\n", i);
3140 ring = &adev->gfx.compute_ring[i];
3141 ring->ring_obj = NULL;
3142 ring->use_doorbell = false;
3143 ring->doorbell_index = 0;
3147 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
3148 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
3149 r = amdgpu_ring_init(adev, ring, 1024,
3150 &adev->gfx.eop_irq, irq_type);
3158 static int gfx_v6_0_sw_fini(void *handle)
3161 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3163 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3164 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
3165 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3166 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
3168 gfx_v6_0_rlc_fini(adev);
3173 static int gfx_v6_0_hw_init(void *handle)
3176 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3178 gfx_v6_0_gpu_init(adev);
3180 r = gfx_v6_0_rlc_resume(adev);
3184 r = gfx_v6_0_cp_resume(adev);
3188 adev->gfx.ce_ram_size = 0x8000;
3193 static int gfx_v6_0_hw_fini(void *handle)
3195 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3197 gfx_v6_0_cp_enable(adev, false);
3198 gfx_v6_0_rlc_stop(adev);
3199 gfx_v6_0_fini_pg(adev);
3204 static int gfx_v6_0_suspend(void *handle)
3206 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3208 return gfx_v6_0_hw_fini(adev);
3211 static int gfx_v6_0_resume(void *handle)
3213 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3215 return gfx_v6_0_hw_init(adev);
3218 static bool gfx_v6_0_is_idle(void *handle)
3220 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3222 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
3228 static int gfx_v6_0_wait_for_idle(void *handle)
3231 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3233 for (i = 0; i < adev->usec_timeout; i++) {
3234 if (gfx_v6_0_is_idle(handle))
3241 static int gfx_v6_0_soft_reset(void *handle)
3246 static void gfx_v6_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
3247 enum amdgpu_interrupt_state state)
3252 case AMDGPU_IRQ_STATE_DISABLE:
3253 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3254 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
3255 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3257 case AMDGPU_IRQ_STATE_ENABLE:
3258 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3259 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
3260 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3267 static void gfx_v6_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
3269 enum amdgpu_interrupt_state state)
3273 case AMDGPU_IRQ_STATE_DISABLE:
3275 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
3276 cp_int_cntl &= ~CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK;
3277 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);
3280 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);
3281 cp_int_cntl &= ~CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK;
3282 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);
3286 case AMDGPU_IRQ_STATE_ENABLE:
3288 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
3289 cp_int_cntl |= CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK;
3290 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);
3293 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);
3294 cp_int_cntl |= CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK;
3295 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);
3307 static int gfx_v6_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
3308 struct amdgpu_irq_src *src,
3310 enum amdgpu_interrupt_state state)
3315 case AMDGPU_IRQ_STATE_DISABLE:
3316 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3317 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
3318 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3320 case AMDGPU_IRQ_STATE_ENABLE:
3321 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3322 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
3323 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3332 static int gfx_v6_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
3333 struct amdgpu_irq_src *src,
3335 enum amdgpu_interrupt_state state)
3340 case AMDGPU_IRQ_STATE_DISABLE:
3341 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3342 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
3343 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3345 case AMDGPU_IRQ_STATE_ENABLE:
3346 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3347 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
3348 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3357 static int gfx_v6_0_set_eop_interrupt_state(struct amdgpu_device *adev,
3358 struct amdgpu_irq_src *src,
3360 enum amdgpu_interrupt_state state)
3363 case AMDGPU_CP_IRQ_GFX_EOP:
3364 gfx_v6_0_set_gfx_eop_interrupt_state(adev, state);
3366 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
3367 gfx_v6_0_set_compute_eop_interrupt_state(adev, 0, state);
3369 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
3370 gfx_v6_0_set_compute_eop_interrupt_state(adev, 1, state);
3378 static int gfx_v6_0_eop_irq(struct amdgpu_device *adev,
3379 struct amdgpu_irq_src *source,
3380 struct amdgpu_iv_entry *entry)
3382 switch (entry->ring_id) {
3384 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
3388 amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id - 1]);
3396 static int gfx_v6_0_priv_reg_irq(struct amdgpu_device *adev,
3397 struct amdgpu_irq_src *source,
3398 struct amdgpu_iv_entry *entry)
3400 DRM_ERROR("Illegal register access in command stream\n");
3401 schedule_work(&adev->reset_work);
3405 static int gfx_v6_0_priv_inst_irq(struct amdgpu_device *adev,
3406 struct amdgpu_irq_src *source,
3407 struct amdgpu_iv_entry *entry)
3409 DRM_ERROR("Illegal instruction in command stream\n");
3410 schedule_work(&adev->reset_work);
3414 static int gfx_v6_0_set_clockgating_state(void *handle,
3415 enum amd_clockgating_state state)
3418 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3420 if (state == AMD_CG_STATE_GATE)
3423 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
3425 gfx_v6_0_enable_mgcg(adev, true);
3426 gfx_v6_0_enable_cgcg(adev, true);
3428 gfx_v6_0_enable_cgcg(adev, false);
3429 gfx_v6_0_enable_mgcg(adev, false);
3431 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
3436 static int gfx_v6_0_set_powergating_state(void *handle,
3437 enum amd_powergating_state state)
3440 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3442 if (state == AMD_PG_STATE_GATE)
3445 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
3446 AMD_PG_SUPPORT_GFX_SMG |
3447 AMD_PG_SUPPORT_GFX_DMG |
3449 AMD_PG_SUPPORT_GDS |
3450 AMD_PG_SUPPORT_RLC_SMU_HS)) {
3451 gfx_v6_0_update_gfx_pg(adev, gate);
3452 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
3453 gfx_v6_0_enable_cp_pg(adev, gate);
3454 gfx_v6_0_enable_gds_pg(adev, gate);
3461 static const struct amd_ip_funcs gfx_v6_0_ip_funcs = {
3463 .early_init = gfx_v6_0_early_init,
3465 .sw_init = gfx_v6_0_sw_init,
3466 .sw_fini = gfx_v6_0_sw_fini,
3467 .hw_init = gfx_v6_0_hw_init,
3468 .hw_fini = gfx_v6_0_hw_fini,
3469 .suspend = gfx_v6_0_suspend,
3470 .resume = gfx_v6_0_resume,
3471 .is_idle = gfx_v6_0_is_idle,
3472 .wait_for_idle = gfx_v6_0_wait_for_idle,
3473 .soft_reset = gfx_v6_0_soft_reset,
3474 .set_clockgating_state = gfx_v6_0_set_clockgating_state,
3475 .set_powergating_state = gfx_v6_0_set_powergating_state,
3478 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
3479 .type = AMDGPU_RING_TYPE_GFX,
3482 .support_64bit_ptrs = false,
3483 .get_rptr = gfx_v6_0_ring_get_rptr,
3484 .get_wptr = gfx_v6_0_ring_get_wptr,
3485 .set_wptr = gfx_v6_0_ring_set_wptr_gfx,
3487 5 + 5 + /* hdp flush / invalidate */
3488 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
3489 7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */
3490 SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v6_0_ring_emit_vm_flush */
3491 3 + 2, /* gfx_v6_ring_emit_cntxcntl including vgt flush */
3492 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */
3493 .emit_ib = gfx_v6_0_ring_emit_ib,
3494 .emit_fence = gfx_v6_0_ring_emit_fence,
3495 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3496 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
3497 .test_ring = gfx_v6_0_ring_test_ring,
3498 .test_ib = gfx_v6_0_ring_test_ib,
3499 .insert_nop = amdgpu_ring_insert_nop,
3500 .emit_cntxcntl = gfx_v6_ring_emit_cntxcntl,
3501 .emit_wreg = gfx_v6_0_ring_emit_wreg,
3504 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
3505 .type = AMDGPU_RING_TYPE_COMPUTE,
3508 .get_rptr = gfx_v6_0_ring_get_rptr,
3509 .get_wptr = gfx_v6_0_ring_get_wptr,
3510 .set_wptr = gfx_v6_0_ring_set_wptr_compute,
3512 5 + 5 + /* hdp flush / invalidate */
3513 7 + /* gfx_v6_0_ring_emit_pipeline_sync */
3514 SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v6_0_ring_emit_vm_flush */
3515 14 + 14 + 14, /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
3516 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */
3517 .emit_ib = gfx_v6_0_ring_emit_ib,
3518 .emit_fence = gfx_v6_0_ring_emit_fence,
3519 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3520 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
3521 .test_ring = gfx_v6_0_ring_test_ring,
3522 .test_ib = gfx_v6_0_ring_test_ib,
3523 .insert_nop = amdgpu_ring_insert_nop,
3524 .emit_wreg = gfx_v6_0_ring_emit_wreg,
3527 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev)
3531 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3532 adev->gfx.gfx_ring[i].funcs = &gfx_v6_0_ring_funcs_gfx;
3533 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3534 adev->gfx.compute_ring[i].funcs = &gfx_v6_0_ring_funcs_compute;
3537 static const struct amdgpu_irq_src_funcs gfx_v6_0_eop_irq_funcs = {
3538 .set = gfx_v6_0_set_eop_interrupt_state,
3539 .process = gfx_v6_0_eop_irq,
3542 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_reg_irq_funcs = {
3543 .set = gfx_v6_0_set_priv_reg_fault_state,
3544 .process = gfx_v6_0_priv_reg_irq,
3547 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_inst_irq_funcs = {
3548 .set = gfx_v6_0_set_priv_inst_fault_state,
3549 .process = gfx_v6_0_priv_inst_irq,
3552 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev)
3554 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
3555 adev->gfx.eop_irq.funcs = &gfx_v6_0_eop_irq_funcs;
3557 adev->gfx.priv_reg_irq.num_types = 1;
3558 adev->gfx.priv_reg_irq.funcs = &gfx_v6_0_priv_reg_irq_funcs;
3560 adev->gfx.priv_inst_irq.num_types = 1;
3561 adev->gfx.priv_inst_irq.funcs = &gfx_v6_0_priv_inst_irq_funcs;
3564 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev)
3566 int i, j, k, counter, active_cu_number = 0;
3567 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
3568 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
3569 unsigned disable_masks[4 * 2];
3572 if (adev->flags & AMD_IS_APU)
3575 ao_cu_num = adev->gfx.config.max_cu_per_sh;
3577 memset(cu_info, 0, sizeof(*cu_info));
3579 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
3581 mutex_lock(&adev->grbm_idx_mutex);
3582 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3583 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3587 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
3589 gfx_v6_0_set_user_cu_inactive_bitmap(
3590 adev, disable_masks[i * 2 + j]);
3591 bitmap = gfx_v6_0_get_cu_enabled(adev);
3592 cu_info->bitmap[i][j] = bitmap;
3594 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
3595 if (bitmap & mask) {
3596 if (counter < ao_cu_num)
3602 active_cu_number += counter;
3604 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
3605 cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
3609 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3610 mutex_unlock(&adev->grbm_idx_mutex);
3612 cu_info->number = active_cu_number;
3613 cu_info->ao_cu_mask = ao_cu_mask;
3616 const struct amdgpu_ip_block_version gfx_v6_0_ip_block =
3618 .type = AMD_IP_BLOCK_TYPE_GFX,
3622 .funcs = &gfx_v6_0_ip_funcs,
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