drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/kernel.h>
  26 #include <linux/firmware.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_gfx.h"
  31 #include "amdgpu_psp.h"
  32 #include "amdgpu_smu.h"
  33 #include "nv.h"
  34 #include "nvd.h"
  35
  36 #include "gc/gc_10_1_0_offset.h"
  37 #include "gc/gc_10_1_0_sh_mask.h"
  38 #include "smuio/smuio_11_0_0_offset.h"
  39 #include "smuio/smuio_11_0_0_sh_mask.h"
  40 #include "navi10_enum.h"
  41 #include "hdp/hdp_5_0_0_offset.h"
  42 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
  43
  44 #include "soc15.h"
  45 #include "soc15d.h"
  46 #include "soc15_common.h"
  47 #include "clearstate_gfx10.h"
  48 #include "v10_structs.h"
  49 #include "gfx_v10_0.h"
  50 #include "nbio_v2_3.h"
  51
  52 /**
  53  * Navi10 has two graphic rings to share each graphic pipe.
  54  * 1. Primary ring
  55  * 2. Async ring
  56  */
  57 #define GFX10_NUM_GFX_RINGS_NV1X        1
  58 #define GFX10_MEC_HPD_SIZE      2048
  59
  60 #define F32_CE_PROGRAM_RAM_SIZE         65536
  61 #define RLCG_UCODE_LOADING_START_ADDRESS        0x00002000L
  62
  63 #define mmCGTT_GS_NGG_CLK_CTRL  0x5087
  64 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
  65
  66 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
  67 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
  68 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
  69 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
  70 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
  71 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
  72
  73 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
  74 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
  75 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
  76 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
  77 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
  78 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
  79 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
  80 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
  81 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
  82 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
  83 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
  84
  85 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
  86 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
  87 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
  88 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
  89 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
  90 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
  91
  92 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
  93 {
  94         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
  95         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
  96         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
  97         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
  98         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
  99         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
 101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
 103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
 104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
 105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
 107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
 108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
 112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
 114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
 115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
 118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
 120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
 123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
 124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
 127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
 129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
 132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
 133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
 134 };
 135
 136 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
 137 {
 138         /* Pending on emulation bring up */
 139 };
 140
 141 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] =
 142 {
 143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
 144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
 186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
 194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
 362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
 850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
 854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
 858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
 862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
 866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
 870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
 874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
 878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
 882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
 886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
 890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
 894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
 898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
 902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
 906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
 910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
 914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
 918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
 922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
 926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
 930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
 934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
 938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
 942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
 946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
 950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
 954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
 958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
 962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
 966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
 970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
 974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
 978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
 982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
 986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
 990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
 994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
 998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1195 };
1196
1197 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
1198 {
1199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1237 };
1238
1239 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
1240 {
1241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
1256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000)
1281 };
1282
1283 static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v)
1284 {
1285         static void *scratch_reg0;
1286         static void *scratch_reg1;
1287         static void *scratch_reg2;
1288         static void *scratch_reg3;
1289         static void *spare_int;
1290         static uint32_t grbm_cntl;
1291         static uint32_t grbm_idx;
1292         uint32_t i = 0;
1293         uint32_t retries = 50000;
1294
1295         scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4;
1296         scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4;
1297         scratch_reg2 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2)*4;
1298         scratch_reg3 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3)*4;
1299         spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT)*4;
1300
1301         grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;
1302         grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX;
1303
1304         if (amdgpu_sriov_runtime(adev)) {
1305                 pr_err("shouldn't call rlcg write register during runtime\n");
1306                 return;
1307         }
1308
1309         writel(v, scratch_reg0);
1310         writel(offset | 0x80000000, scratch_reg1);
1311         writel(1, spare_int);
1312         for (i = 0; i < retries; i++) {
1313                 u32 tmp;
1314
1315                 tmp = readl(scratch_reg1);
1316                 if (!(tmp & 0x80000000))
1317                         break;
1318
1319                 udelay(10);
1320         }
1321
1322         if (i >= retries)
1323                 pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset);
1324 }
1325
1326 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
1327 {
1328         /* Pending on emulation bring up */
1329 };
1330
1331 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] =
1332 {
1333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
1696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
1872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
1876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
1880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
1884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
1888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
1892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
1896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
1900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
1904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
1908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
1912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
1916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
1940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
1942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
1944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
1946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
1948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
1950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
1952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1953 };
1954
1955 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
1956 {
1957         /* Pending on emulation bring up */
1958 };
1959
1960 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] =
1961 {
1962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
1963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
2885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
2889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
2893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
2897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
2901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
2905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
2909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
2913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
2917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
2921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
2925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
2929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
2933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
2937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
2941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
2945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
2949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
2953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
2957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
2961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
2965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
2969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
2991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
2995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3014 };
3015
3016 #define DEFAULT_SH_MEM_CONFIG \
3017         ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3018          (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3019          (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3020          (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3021
3022
3023 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3024 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3025 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3026 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3027 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3028                                  struct amdgpu_cu_info *cu_info);
3029 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3030 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3031                                    u32 sh_num, u32 instance);
3032 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3033
3034 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3035 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3036 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3037 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3038 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3039 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3040 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3041
3042 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3043 {
3044         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3045         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3046                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
3047         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
3048         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
3049         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
3050         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
3051         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
3052         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
3053 }
3054
3055 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3056                                  struct amdgpu_ring *ring)
3057 {
3058         struct amdgpu_device *adev = kiq_ring->adev;
3059         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3060         uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3061         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3062
3063         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3064         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3065         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3066                           PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3067                           PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3068                           PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3069                           PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3070                           PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3071                           PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3072                           PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3073                           PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3074                           PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3075         amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3076         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3077         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3078         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3079         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3080 }
3081
3082 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3083                                    struct amdgpu_ring *ring,
3084                                    enum amdgpu_unmap_queues_action action,
3085                                    u64 gpu_addr, u64 seq)
3086 {
3087         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3088
3089         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3090         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3091                           PACKET3_UNMAP_QUEUES_ACTION(action) |
3092                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3093                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3094                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3095         amdgpu_ring_write(kiq_ring,
3096                   PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3097
3098         if (action == PREEMPT_QUEUES_NO_UNMAP) {
3099                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3100                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3101                 amdgpu_ring_write(kiq_ring, seq);
3102         } else {
3103                 amdgpu_ring_write(kiq_ring, 0);
3104                 amdgpu_ring_write(kiq_ring, 0);
3105                 amdgpu_ring_write(kiq_ring, 0);
3106         }
3107 }
3108
3109 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3110                                    struct amdgpu_ring *ring,
3111                                    u64 addr,
3112                                    u64 seq)
3113 {
3114         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3115
3116         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3117         amdgpu_ring_write(kiq_ring,
3118                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3119                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3120                           PACKET3_QUERY_STATUS_COMMAND(2));
3121         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3122                           PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3123                           PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3124         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3125         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3126         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3127         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3128 }
3129
3130 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3131                                 uint16_t pasid, uint32_t flush_type,
3132                                 bool all_hub)
3133 {
3134         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
3135         amdgpu_ring_write(kiq_ring,
3136                         PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
3137                         PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
3138                         PACKET3_INVALIDATE_TLBS_PASID(pasid) |
3139                         PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
3140 }
3141
3142 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3143         .kiq_set_resources = gfx10_kiq_set_resources,
3144         .kiq_map_queues = gfx10_kiq_map_queues,
3145         .kiq_unmap_queues = gfx10_kiq_unmap_queues,
3146         .kiq_query_status = gfx10_kiq_query_status,
3147         .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3148         .set_resources_size = 8,
3149         .map_queues_size = 7,
3150         .unmap_queues_size = 6,
3151         .query_status_size = 7,
3152         .invalidate_tlbs_size = 2,
3153 };
3154
3155 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3156 {
3157         adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
3158 }
3159
3160 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3161 {
3162         switch (adev->asic_type) {
3163         case CHIP_NAVI10:
3164                 soc15_program_register_sequence(adev,
3165                                                 golden_settings_gc_10_1,
3166                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3167                 soc15_program_register_sequence(adev,
3168                                                 golden_settings_gc_10_0_nv10,
3169                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3170                 soc15_program_register_sequence(adev,
3171                                                 golden_settings_gc_rlc_spm_10_0_nv10,
3172                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3173                 break;
3174         case CHIP_NAVI14:
3175                 soc15_program_register_sequence(adev,
3176                                                 golden_settings_gc_10_1_1,
3177                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3178                 soc15_program_register_sequence(adev,
3179                                                 golden_settings_gc_10_1_nv14,
3180                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3181                 soc15_program_register_sequence(adev,
3182                                                 golden_settings_gc_rlc_spm_10_1_nv14,
3183                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3184                 break;
3185         case CHIP_NAVI12:
3186                 soc15_program_register_sequence(adev,
3187                                                 golden_settings_gc_10_1_2,
3188                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3189                 soc15_program_register_sequence(adev,
3190                                                 golden_settings_gc_10_1_2_nv12,
3191                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3192                 soc15_program_register_sequence(adev,
3193                                                 golden_settings_gc_rlc_spm_10_1_2_nv12,
3194                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3195                 break;
3196         default:
3197                 break;
3198         }
3199 }
3200
3201 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev)
3202 {
3203         adev->gfx.scratch.num_reg = 8;
3204         adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
3205         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
3206 }
3207
3208 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3209                                        bool wc, uint32_t reg, uint32_t val)
3210 {
3211         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3212         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3213                           WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3214         amdgpu_ring_write(ring, reg);
3215         amdgpu_ring_write(ring, 0);
3216         amdgpu_ring_write(ring, val);
3217 }
3218
3219 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3220                                   int mem_space, int opt, uint32_t addr0,
3221                                   uint32_t addr1, uint32_t ref, uint32_t mask,
3222                                   uint32_t inv)
3223 {
3224         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3225         amdgpu_ring_write(ring,
3226                           /* memory (1) or register (0) */
3227                           (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3228                            WAIT_REG_MEM_OPERATION(opt) | /* wait */
3229                            WAIT_REG_MEM_FUNCTION(3) |  /* equal */
3230                            WAIT_REG_MEM_ENGINE(eng_sel)));
3231
3232         if (mem_space)
3233                 BUG_ON(addr0 & 0x3); /* Dword align */
3234         amdgpu_ring_write(ring, addr0);
3235         amdgpu_ring_write(ring, addr1);
3236         amdgpu_ring_write(ring, ref);
3237         amdgpu_ring_write(ring, mask);
3238         amdgpu_ring_write(ring, inv); /* poll interval */
3239 }
3240
3241 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3242 {
3243         struct amdgpu_device *adev = ring->adev;
3244         uint32_t scratch;
3245         uint32_t tmp = 0;
3246         unsigned i;
3247         int r;
3248
3249         r = amdgpu_gfx_scratch_get(adev, &scratch);
3250         if (r) {
3251                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
3252                 return r;
3253         }
3254
3255         WREG32(scratch, 0xCAFEDEAD);
3256
3257         r = amdgpu_ring_alloc(ring, 3);
3258         if (r) {
3259                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
3260                           ring->idx, r);
3261                 amdgpu_gfx_scratch_free(adev, scratch);
3262                 return r;
3263         }
3264
3265         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3266         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
3267         amdgpu_ring_write(ring, 0xDEADBEEF);
3268         amdgpu_ring_commit(ring);
3269
3270         for (i = 0; i < adev->usec_timeout; i++) {
3271                 tmp = RREG32(scratch);
3272                 if (tmp == 0xDEADBEEF)
3273                         break;
3274                 if (amdgpu_emu_mode == 1)
3275                         msleep(1);
3276                 else
3277                         udelay(1);
3278         }
3279
3280         if (i >= adev->usec_timeout)
3281                 r = -ETIMEDOUT;
3282
3283         amdgpu_gfx_scratch_free(adev, scratch);
3284
3285         return r;
3286 }
3287
3288 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3289 {
3290         struct amdgpu_device *adev = ring->adev;
3291         struct amdgpu_ib ib;
3292         struct dma_fence *f = NULL;
3293         unsigned index;
3294         uint64_t gpu_addr;
3295         uint32_t tmp;
3296         long r;
3297
3298         r = amdgpu_device_wb_get(adev, &index);
3299         if (r)
3300                 return r;
3301
3302         gpu_addr = adev->wb.gpu_addr + (index * 4);
3303         adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
3304         memset(&ib, 0, sizeof(ib));
3305         r = amdgpu_ib_get(adev, NULL, 16,
3306                                         AMDGPU_IB_POOL_DIRECT, &ib);
3307         if (r)
3308                 goto err1;
3309
3310         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
3311         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
3312         ib.ptr[2] = lower_32_bits(gpu_addr);
3313         ib.ptr[3] = upper_32_bits(gpu_addr);
3314         ib.ptr[4] = 0xDEADBEEF;
3315         ib.length_dw = 5;
3316
3317         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
3318         if (r)
3319                 goto err2;
3320
3321         r = dma_fence_wait_timeout(f, false, timeout);
3322         if (r == 0) {
3323                 r = -ETIMEDOUT;
3324                 goto err2;
3325         } else if (r < 0) {
3326                 goto err2;
3327         }
3328
3329         tmp = adev->wb.wb[index];
3330         if (tmp == 0xDEADBEEF)
3331                 r = 0;
3332         else
3333                 r = -EINVAL;
3334 err2:
3335         amdgpu_ib_free(adev, &ib, NULL);
3336         dma_fence_put(f);
3337 err1:
3338         amdgpu_device_wb_free(adev, index);
3339         return r;
3340 }
3341
3342 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
3343 {
3344         release_firmware(adev->gfx.pfp_fw);
3345         adev->gfx.pfp_fw = NULL;
3346         release_firmware(adev->gfx.me_fw);
3347         adev->gfx.me_fw = NULL;
3348         release_firmware(adev->gfx.ce_fw);
3349         adev->gfx.ce_fw = NULL;
3350         release_firmware(adev->gfx.rlc_fw);
3351         adev->gfx.rlc_fw = NULL;
3352         release_firmware(adev->gfx.mec_fw);
3353         adev->gfx.mec_fw = NULL;
3354         release_firmware(adev->gfx.mec2_fw);
3355         adev->gfx.mec2_fw = NULL;
3356
3357         kfree(adev->gfx.rlc.register_list_format);
3358 }
3359
3360 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
3361 {
3362         adev->gfx.cp_fw_write_wait = false;
3363
3364         switch (adev->asic_type) {
3365         case CHIP_NAVI10:
3366         case CHIP_NAVI12:
3367         case CHIP_NAVI14:
3368                 if ((adev->gfx.me_fw_version >= 0x00000046) &&
3369                     (adev->gfx.me_feature_version >= 27) &&
3370                     (adev->gfx.pfp_fw_version >= 0x00000068) &&
3371                     (adev->gfx.pfp_feature_version >= 27) &&
3372                     (adev->gfx.mec_fw_version >= 0x0000005b) &&
3373                     (adev->gfx.mec_feature_version >= 27))
3374                         adev->gfx.cp_fw_write_wait = true;
3375                 break;
3376         default:
3377                 break;
3378         }
3379
3380         if (adev->gfx.cp_fw_write_wait == false)
3381                 DRM_WARN_ONCE("CP firmware version too old, please update!");
3382 }
3383
3384
3385 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
3386 {
3387         const struct rlc_firmware_header_v2_1 *rlc_hdr;
3388
3389         rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
3390         adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
3391         adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
3392         adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
3393         adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
3394         adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
3395         adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
3396         adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
3397         adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
3398         adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
3399         adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
3400         adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
3401         adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
3402         adev->gfx.rlc.reg_list_format_direct_reg_list_length =
3403                         le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
3404 }
3405
3406 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
3407 {
3408         bool ret = false;
3409
3410         switch (adev->pdev->revision) {
3411         case 0xc2:
3412         case 0xc3:
3413                 ret = true;
3414                 break;
3415         default:
3416                 ret = false;
3417                 break;
3418         }
3419
3420         return ret ;
3421 }
3422
3423 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
3424 {
3425         switch (adev->asic_type) {
3426         case CHIP_NAVI10:
3427                 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
3428                         adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3429                 break;
3430         default:
3431                 break;
3432         }
3433 }
3434
3435 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
3436 {
3437         const char *chip_name;
3438         char fw_name[40];
3439         char wks[10];
3440         int err;
3441         struct amdgpu_firmware_info *info = NULL;
3442         const struct common_firmware_header *header = NULL;
3443         const struct gfx_firmware_header_v1_0 *cp_hdr;
3444         const struct rlc_firmware_header_v2_0 *rlc_hdr;
3445         unsigned int *tmp = NULL;
3446         unsigned int i = 0;
3447         uint16_t version_major;
3448         uint16_t version_minor;
3449
3450         DRM_DEBUG("\n");
3451
3452         memset(wks, 0, sizeof(wks));
3453         switch (adev->asic_type) {
3454         case CHIP_NAVI10:
3455                 chip_name = "navi10";
3456                 break;
3457         case CHIP_NAVI14:
3458                 chip_name = "navi14";
3459                 if (!(adev->pdev->device == 0x7340 &&
3460                       adev->pdev->revision != 0x00))
3461                         snprintf(wks, sizeof(wks), "_wks");
3462                 break;
3463         case CHIP_NAVI12:
3464                 chip_name = "navi12";
3465                 break;
3466         default:
3467                 BUG();
3468         }
3469
3470         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);
3471         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
3472         if (err)
3473                 goto out;
3474         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
3475         if (err)
3476                 goto out;
3477         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
3478         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3479         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3480
3481         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
3482         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
3483         if (err)
3484                 goto out;
3485         err = amdgpu_ucode_validate(adev->gfx.me_fw);
3486         if (err)
3487                 goto out;
3488         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
3489         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3490         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3491
3492         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
3493         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
3494         if (err)
3495                 goto out;
3496         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
3497         if (err)
3498                 goto out;
3499         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
3500         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3501         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3502
3503         if (!amdgpu_sriov_vf(adev)) {
3504                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
3505                 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
3506                 if (err)
3507                         goto out;
3508                 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
3509                 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
3510                 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
3511                 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
3512                 if (version_major == 2 && version_minor == 1)
3513                         adev->gfx.rlc.is_rlc_v2_1 = true;
3514
3515                 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
3516                 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
3517                 adev->gfx.rlc.save_and_restore_offset =
3518                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
3519                 adev->gfx.rlc.clear_state_descriptor_offset =
3520                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
3521                 adev->gfx.rlc.avail_scratch_ram_locations =
3522                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
3523                 adev->gfx.rlc.reg_restore_list_size =
3524                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
3525                 adev->gfx.rlc.reg_list_format_start =
3526                         le32_to_cpu(rlc_hdr->reg_list_format_start);
3527                 adev->gfx.rlc.reg_list_format_separate_start =
3528                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
3529                 adev->gfx.rlc.starting_offsets_start =
3530                         le32_to_cpu(rlc_hdr->starting_offsets_start);
3531                 adev->gfx.rlc.reg_list_format_size_bytes =
3532                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
3533                 adev->gfx.rlc.reg_list_size_bytes =
3534                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
3535                 adev->gfx.rlc.register_list_format =
3536                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
3537                                         adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
3538                 if (!adev->gfx.rlc.register_list_format) {
3539                         err = -ENOMEM;
3540                         goto out;
3541                 }
3542
3543                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
3544                                                            le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
3545                 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
3546                         adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
3547
3548                 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
3549
3550                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
3551                                                            le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
3552                 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
3553                         adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
3554
3555                 if (adev->gfx.rlc.is_rlc_v2_1)
3556                         gfx_v10_0_init_rlc_ext_microcode(adev);
3557         }
3558
3559         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
3560         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
3561         if (err)
3562                 goto out;
3563         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
3564         if (err)
3565                 goto out;
3566         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3567         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3568         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3569
3570         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
3571         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
3572         if (!err) {
3573                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
3574                 if (err)
3575                         goto out;
3576                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
3577                 adev->gfx.mec2_fw->data;
3578                 adev->gfx.mec2_fw_version =
3579                 le32_to_cpu(cp_hdr->header.ucode_version);
3580                 adev->gfx.mec2_feature_version =
3581                 le32_to_cpu(cp_hdr->ucode_feature_version);
3582         } else {
3583                 err = 0;
3584                 adev->gfx.mec2_fw = NULL;
3585         }
3586
3587         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
3588                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
3589                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
3590                 info->fw = adev->gfx.pfp_fw;
3591                 header = (const struct common_firmware_header *)info->fw->data;
3592                 adev->firmware.fw_size +=
3593                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3594
3595                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
3596                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
3597                 info->fw = adev->gfx.me_fw;
3598                 header = (const struct common_firmware_header *)info->fw->data;
3599                 adev->firmware.fw_size +=
3600                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3601
3602                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
3603                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
3604                 info->fw = adev->gfx.ce_fw;
3605                 header = (const struct common_firmware_header *)info->fw->data;
3606                 adev->firmware.fw_size +=
3607                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3608
3609                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
3610                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
3611                 info->fw = adev->gfx.rlc_fw;
3612                 if (info->fw) {
3613                         header = (const struct common_firmware_header *)info->fw->data;
3614                         adev->firmware.fw_size +=
3615                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3616                 }
3617                 if (adev->gfx.rlc.is_rlc_v2_1 &&
3618                     adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
3619                     adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
3620                     adev->gfx.rlc.save_restore_list_srm_size_bytes) {
3621                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
3622                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
3623                         info->fw = adev->gfx.rlc_fw;
3624                         adev->firmware.fw_size +=
3625                                 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
3626
3627                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
3628                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
3629                         info->fw = adev->gfx.rlc_fw;
3630                         adev->firmware.fw_size +=
3631                                 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
3632
3633                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
3634                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
3635                         info->fw = adev->gfx.rlc_fw;
3636                         adev->firmware.fw_size +=
3637                                 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
3638                 }
3639
3640                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
3641                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
3642                 info->fw = adev->gfx.mec_fw;
3643                 header = (const struct common_firmware_header *)info->fw->data;
3644                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
3645                 adev->firmware.fw_size +=
3646                         ALIGN(le32_to_cpu(header->ucode_size_bytes) -
3647                               le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
3648
3649                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
3650                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
3651                 info->fw = adev->gfx.mec_fw;
3652                 adev->firmware.fw_size +=
3653                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
3654
3655                 if (adev->gfx.mec2_fw) {
3656                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
3657                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
3658                         info->fw = adev->gfx.mec2_fw;
3659                         header = (const struct common_firmware_header *)info->fw->data;
3660                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
3661                         adev->firmware.fw_size +=
3662                                 ALIGN(le32_to_cpu(header->ucode_size_bytes) -
3663                                       le32_to_cpu(cp_hdr->jt_size) * 4,
3664                                       PAGE_SIZE);
3665                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
3666                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
3667                         info->fw = adev->gfx.mec2_fw;
3668                         adev->firmware.fw_size +=
3669                                 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
3670                                       PAGE_SIZE);
3671                 }
3672         }
3673
3674         gfx_v10_0_check_fw_write_wait(adev);
3675 out:
3676         if (err) {
3677                 dev_err(adev->dev,
3678                         "gfx10: Failed to load firmware \"%s\"\n",
3679                         fw_name);
3680                 release_firmware(adev->gfx.pfp_fw);
3681                 adev->gfx.pfp_fw = NULL;
3682                 release_firmware(adev->gfx.me_fw);
3683                 adev->gfx.me_fw = NULL;
3684                 release_firmware(adev->gfx.ce_fw);
3685                 adev->gfx.ce_fw = NULL;
3686                 release_firmware(adev->gfx.rlc_fw);
3687                 adev->gfx.rlc_fw = NULL;
3688                 release_firmware(adev->gfx.mec_fw);
3689                 adev->gfx.mec_fw = NULL;
3690                 release_firmware(adev->gfx.mec2_fw);
3691                 adev->gfx.mec2_fw = NULL;
3692         }
3693
3694         gfx_v10_0_check_gfxoff_flag(adev);
3695
3696         return err;
3697 }
3698
3699 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
3700 {
3701         u32 count = 0;
3702         const struct cs_section_def *sect = NULL;
3703         const struct cs_extent_def *ext = NULL;
3704
3705         /* begin clear state */
3706         count += 2;
3707         /* context control state */
3708         count += 3;
3709
3710         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
3711                 for (ext = sect->section; ext->extent != NULL; ++ext) {
3712                         if (sect->id == SECT_CONTEXT)
3713                                 count += 2 + ext->reg_count;
3714                         else
3715                                 return 0;
3716                 }
3717         }
3718
3719         /* set PA_SC_TILE_STEERING_OVERRIDE */
3720         count += 3;
3721         /* end clear state */
3722         count += 2;
3723         /* clear state */
3724         count += 2;
3725
3726         return count;
3727 }
3728
3729 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
3730                                     volatile u32 *buffer)
3731 {
3732         u32 count = 0, i;
3733         const struct cs_section_def *sect = NULL;
3734         const struct cs_extent_def *ext = NULL;
3735         int ctx_reg_offset;
3736
3737         if (adev->gfx.rlc.cs_data == NULL)
3738                 return;
3739         if (buffer == NULL)
3740                 return;
3741
3742         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3743         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
3744
3745         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3746         buffer[count++] = cpu_to_le32(0x80000000);
3747         buffer[count++] = cpu_to_le32(0x80000000);
3748
3749         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
3750                 for (ext = sect->section; ext->extent != NULL; ++ext) {
3751                         if (sect->id == SECT_CONTEXT) {
3752                                 buffer[count++] =
3753                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
3754                                 buffer[count++] = cpu_to_le32(ext->reg_index -
3755                                                 PACKET3_SET_CONTEXT_REG_START);
3756                                 for (i = 0; i < ext->reg_count; i++)
3757                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
3758                         } else {
3759                                 return;
3760                         }
3761                 }
3762         }
3763
3764         ctx_reg_offset =
3765                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
3766         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
3767         buffer[count++] = cpu_to_le32(ctx_reg_offset);
3768         buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
3769
3770         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3771         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
3772
3773         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
3774         buffer[count++] = cpu_to_le32(0);
3775 }
3776
3777 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
3778 {
3779         /* clear state block */
3780         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
3781                         &adev->gfx.rlc.clear_state_gpu_addr,
3782                         (void **)&adev->gfx.rlc.cs_ptr);
3783
3784         /* jump table block */
3785         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
3786                         &adev->gfx.rlc.cp_table_gpu_addr,
3787                         (void **)&adev->gfx.rlc.cp_table_ptr);
3788 }
3789
3790 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
3791 {
3792         const struct cs_section_def *cs_data;
3793         int r;
3794
3795         adev->gfx.rlc.cs_data = gfx10_cs_data;
3796
3797         cs_data = adev->gfx.rlc.cs_data;
3798
3799         if (cs_data) {
3800                 /* init clear state block */
3801                 r = amdgpu_gfx_rlc_init_csb(adev);
3802                 if (r)
3803                         return r;
3804         }
3805
3806         /* init spm vmid with 0xf */
3807         if (adev->gfx.rlc.funcs->update_spm_vmid)
3808                 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
3809
3810         return 0;
3811 }
3812
3813 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
3814 {
3815         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
3816         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
3817 }
3818
3819 static int gfx_v10_0_me_init(struct amdgpu_device *adev)
3820 {
3821         int r;
3822
3823         bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
3824
3825         amdgpu_gfx_graphics_queue_acquire(adev);
3826
3827         r = gfx_v10_0_init_microcode(adev);
3828         if (r)
3829                 DRM_ERROR("Failed to load gfx firmware!\n");
3830
3831         return r;
3832 }
3833
3834 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
3835 {
3836         int r;
3837         u32 *hpd;
3838         const __le32 *fw_data = NULL;
3839         unsigned fw_size;
3840         u32 *fw = NULL;
3841         size_t mec_hpd_size;
3842
3843         const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
3844
3845         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
3846
3847         /* take ownership of the relevant compute queues */
3848         amdgpu_gfx_compute_queue_acquire(adev);
3849         mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
3850
3851         r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
3852                                       AMDGPU_GEM_DOMAIN_GTT,
3853                                       &adev->gfx.mec.hpd_eop_obj,
3854                                       &adev->gfx.mec.hpd_eop_gpu_addr,
3855                                       (void **)&hpd);
3856         if (r) {
3857                 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
3858                 gfx_v10_0_mec_fini(adev);
3859                 return r;
3860         }
3861
3862         memset(hpd, 0, mec_hpd_size);
3863
3864         amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
3865         amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
3866
3867         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
3868                 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3869
3870                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
3871                          le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
3872                 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
3873
3874                 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
3875                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
3876                                               &adev->gfx.mec.mec_fw_obj,
3877                                               &adev->gfx.mec.mec_fw_gpu_addr,
3878                                               (void **)&fw);
3879                 if (r) {
3880                         dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
3881                         gfx_v10_0_mec_fini(adev);
3882                         return r;
3883                 }
3884
3885                 memcpy(fw, fw_data, fw_size);
3886
3887                 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
3888                 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
3889         }
3890
3891         return 0;
3892 }
3893
3894 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
3895 {
3896         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
3897                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
3898                 (address << SQ_IND_INDEX__INDEX__SHIFT));
3899         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
3900 }
3901
3902 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
3903                            uint32_t thread, uint32_t regno,
3904                            uint32_t num, uint32_t *out)
3905 {
3906         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
3907                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
3908                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
3909                 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
3910                 (SQ_IND_INDEX__AUTO_INCR_MASK));
3911         while (num--)
3912                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
3913 }
3914
3915 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
3916 {
3917         /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
3918          * field when performing a select_se_sh so it should be
3919          * zero here */
3920         WARN_ON(simd != 0);
3921
3922         /* type 2 wave data */
3923         dst[(*no_fields)++] = 2;
3924         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
3925         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
3926         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
3927         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
3928         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
3929         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
3930         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
3931         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
3932         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
3933         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
3934         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
3935         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
3936         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
3937         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
3938         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
3939 }
3940
3941 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
3942                                      uint32_t wave, uint32_t start,
3943                                      uint32_t size, uint32_t *dst)
3944 {
3945         WARN_ON(simd != 0);
3946
3947         wave_read_regs(
3948                 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
3949                 dst);
3950 }
3951
3952 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
3953                                       uint32_t wave, uint32_t thread,
3954                                       uint32_t start, uint32_t size,
3955                                       uint32_t *dst)
3956 {
3957         wave_read_regs(
3958                 adev, wave, thread,
3959                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
3960 }
3961
3962 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
3963                                                                           u32 me, u32 pipe, u32 q, u32 vm)
3964  {
3965        nv_grbm_select(adev, me, pipe, q, vm);
3966  }
3967
3968
3969 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
3970         .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
3971         .select_se_sh = &gfx_v10_0_select_se_sh,
3972         .read_wave_data = &gfx_v10_0_read_wave_data,
3973         .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
3974         .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
3975         .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
3976 };
3977
3978 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
3979 {
3980         u32 gb_addr_config;
3981
3982         adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
3983
3984         switch (adev->asic_type) {
3985         case CHIP_NAVI10:
3986         case CHIP_NAVI14:
3987         case CHIP_NAVI12:
3988                 adev->gfx.config.max_hw_contexts = 8;
3989                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
3990                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
3991                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
3992                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
3993                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
3994                 break;
3995         default:
3996                 BUG();
3997                 break;
3998         }
3999
4000         adev->gfx.config.gb_addr_config = gb_addr_config;
4001
4002         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4003                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4004                                       GB_ADDR_CONFIG, NUM_PIPES);
4005
4006         adev->gfx.config.max_tile_pipes =
4007                 adev->gfx.config.gb_addr_config_fields.num_pipes;
4008
4009         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4010                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4011                                       GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4012         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4013                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4014                                       GB_ADDR_CONFIG, NUM_RB_PER_SE);
4015         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4016                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4017                                       GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4018         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4019                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4020                                       GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4021 }
4022
4023 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4024                                    int me, int pipe, int queue)
4025 {
4026         int r;
4027         struct amdgpu_ring *ring;
4028         unsigned int irq_type;
4029
4030         ring = &adev->gfx.gfx_ring[ring_id];
4031
4032         ring->me = me;
4033         ring->pipe = pipe;
4034         ring->queue = queue;
4035
4036         ring->ring_obj = NULL;
4037         ring->use_doorbell = true;
4038
4039         if (!ring_id)
4040                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4041         else
4042                 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4043         sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4044
4045         irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4046         r = amdgpu_ring_init(adev, ring, 1024,
4047                              &adev->gfx.eop_irq, irq_type,
4048                              AMDGPU_RING_PRIO_DEFAULT);
4049         if (r)
4050                 return r;
4051         return 0;
4052 }
4053
4054 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4055                                        int mec, int pipe, int queue)
4056 {
4057         int r;
4058         unsigned irq_type;
4059         struct amdgpu_ring *ring;
4060         unsigned int hw_prio;
4061
4062         ring = &adev->gfx.compute_ring[ring_id];
4063
4064         /* mec0 is me1 */
4065         ring->me = mec + 1;
4066         ring->pipe = pipe;
4067         ring->queue = queue;
4068
4069         ring->ring_obj = NULL;
4070         ring->use_doorbell = true;
4071         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4072         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4073                                 + (ring_id * GFX10_MEC_HPD_SIZE);
4074         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4075
4076         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4077                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4078                 + ring->pipe;
4079         hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue) ?
4080                         AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4081         /* type-2 packets are deprecated on MEC, use type-3 instead */
4082         r = amdgpu_ring_init(adev, ring, 1024,
4083                              &adev->gfx.eop_irq, irq_type, hw_prio);
4084         if (r)
4085                 return r;
4086
4087         return 0;
4088 }
4089
4090 static int gfx_v10_0_sw_init(void *handle)
4091 {
4092         int i, j, k, r, ring_id = 0;
4093         struct amdgpu_kiq *kiq;
4094         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4095
4096         switch (adev->asic_type) {
4097         case CHIP_NAVI10:
4098         case CHIP_NAVI14:
4099         case CHIP_NAVI12:
4100                 adev->gfx.me.num_me = 1;
4101                 adev->gfx.me.num_pipe_per_me = 1;
4102                 adev->gfx.me.num_queue_per_pipe = 1;
4103                 adev->gfx.mec.num_mec = 2;
4104                 adev->gfx.mec.num_pipe_per_mec = 4;
4105                 adev->gfx.mec.num_queue_per_pipe = 8;
4106                 break;
4107         default:
4108                 adev->gfx.me.num_me = 1;
4109                 adev->gfx.me.num_pipe_per_me = 1;
4110                 adev->gfx.me.num_queue_per_pipe = 1;
4111                 adev->gfx.mec.num_mec = 1;
4112                 adev->gfx.mec.num_pipe_per_mec = 4;
4113                 adev->gfx.mec.num_queue_per_pipe = 8;
4114                 break;
4115         }
4116
4117         /* KIQ event */
4118         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4119                               GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4120                               &adev->gfx.kiq.irq);
4121         if (r)
4122                 return r;
4123
4124         /* EOP Event */
4125         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4126                               GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4127                               &adev->gfx.eop_irq);
4128         if (r)
4129                 return r;
4130
4131         /* Privileged reg */
4132         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4133                               &adev->gfx.priv_reg_irq);
4134         if (r)
4135                 return r;
4136
4137         /* Privileged inst */
4138         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4139                               &adev->gfx.priv_inst_irq);
4140         if (r)
4141                 return r;
4142
4143         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4144
4145         gfx_v10_0_scratch_init(adev);
4146
4147         r = gfx_v10_0_me_init(adev);
4148         if (r)
4149                 return r;
4150
4151         r = gfx_v10_0_rlc_init(adev);
4152         if (r) {
4153                 DRM_ERROR("Failed to init rlc BOs!\n");
4154                 return r;
4155         }
4156
4157         r = gfx_v10_0_mec_init(adev);
4158         if (r) {
4159                 DRM_ERROR("Failed to init MEC BOs!\n");
4160                 return r;
4161         }
4162
4163         /* set up the gfx ring */
4164         for (i = 0; i < adev->gfx.me.num_me; i++) {
4165                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4166                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4167                                 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4168                                         continue;
4169
4170                                 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4171                                                             i, k, j);
4172                                 if (r)
4173                                         return r;
4174                                 ring_id++;
4175                         }
4176                 }
4177         }
4178
4179         ring_id = 0;
4180         /* set up the compute queues - allocate horizontally across pipes */
4181         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4182                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4183                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4184                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
4185                                                                      j))
4186                                         continue;
4187
4188                                 r = gfx_v10_0_compute_ring_init(adev, ring_id,
4189                                                                 i, k, j);
4190                                 if (r)
4191                                         return r;
4192
4193                                 ring_id++;
4194                         }
4195                 }
4196         }
4197
4198         r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE);
4199         if (r) {
4200                 DRM_ERROR("Failed to init KIQ BOs!\n");
4201                 return r;
4202         }
4203
4204         kiq = &adev->gfx.kiq;
4205         r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
4206         if (r)
4207                 return r;
4208
4209         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
4210         if (r)
4211                 return r;
4212
4213         /* allocate visible FB for rlc auto-loading fw */
4214         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4215                 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4216                 if (r)
4217                         return r;
4218         }
4219
4220         adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4221
4222         gfx_v10_0_gpu_early_init(adev);
4223
4224         return 0;
4225 }
4226
4227 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4228 {
4229         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4230                               &adev->gfx.pfp.pfp_fw_gpu_addr,
4231                               (void **)&adev->gfx.pfp.pfp_fw_ptr);
4232 }
4233
4234 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4235 {
4236         amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4237                               &adev->gfx.ce.ce_fw_gpu_addr,
4238                               (void **)&adev->gfx.ce.ce_fw_ptr);
4239 }
4240
4241 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4242 {
4243         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4244                               &adev->gfx.me.me_fw_gpu_addr,
4245                               (void **)&adev->gfx.me.me_fw_ptr);
4246 }
4247
4248 static int gfx_v10_0_sw_fini(void *handle)
4249 {
4250         int i;
4251         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4252
4253         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4254                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4255         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4256                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4257
4258         amdgpu_gfx_mqd_sw_fini(adev);
4259         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
4260         amdgpu_gfx_kiq_fini(adev);
4261
4262         gfx_v10_0_pfp_fini(adev);
4263         gfx_v10_0_ce_fini(adev);
4264         gfx_v10_0_me_fini(adev);
4265         gfx_v10_0_rlc_fini(adev);
4266         gfx_v10_0_mec_fini(adev);
4267
4268         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
4269                 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
4270
4271         gfx_v10_0_free_microcode(adev);
4272
4273         return 0;
4274 }
4275
4276
4277 static void gfx_v10_0_tiling_mode_table_init(struct amdgpu_device *adev)
4278 {
4279         /* TODO */
4280 }
4281
4282 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
4283                                    u32 sh_num, u32 instance)
4284 {
4285         u32 data;
4286
4287         if (instance == 0xffffffff)
4288                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
4289                                      INSTANCE_BROADCAST_WRITES, 1);
4290         else
4291                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
4292                                      instance);
4293
4294         if (se_num == 0xffffffff)
4295                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
4296                                      1);
4297         else
4298                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
4299
4300         if (sh_num == 0xffffffff)
4301                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
4302                                      1);
4303         else
4304                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
4305
4306         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
4307 }
4308
4309 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
4310 {
4311         u32 data, mask;
4312
4313         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
4314         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
4315
4316         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
4317         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
4318
4319         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
4320                                          adev->gfx.config.max_sh_per_se);
4321
4322         return (~data) & mask;
4323 }
4324
4325 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
4326 {
4327         int i, j;
4328         u32 data;
4329         u32 active_rbs = 0;
4330         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
4331                                         adev->gfx.config.max_sh_per_se;
4332
4333         mutex_lock(&adev->grbm_idx_mutex);
4334         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4335                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4336                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4337                         data = gfx_v10_0_get_rb_active_bitmap(adev);
4338                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
4339                                                rb_bitmap_width_per_sh);
4340                 }
4341         }
4342         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4343         mutex_unlock(&adev->grbm_idx_mutex);
4344
4345         adev->gfx.config.backend_enable_mask = active_rbs;
4346         adev->gfx.config.num_rbs = hweight32(active_rbs);
4347 }
4348
4349 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
4350 {
4351         uint32_t num_sc;
4352         uint32_t enabled_rb_per_sh;
4353         uint32_t active_rb_bitmap;
4354         uint32_t num_rb_per_sc;
4355         uint32_t num_packer_per_sc;
4356         uint32_t pa_sc_tile_steering_override;
4357
4358         /* init num_sc */
4359         num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
4360                         adev->gfx.config.num_sc_per_sh;
4361         /* init num_rb_per_sc */
4362         active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
4363         enabled_rb_per_sh = hweight32(active_rb_bitmap);
4364         num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
4365         /* init num_packer_per_sc */
4366         num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
4367
4368         pa_sc_tile_steering_override = 0;
4369         pa_sc_tile_steering_override |=
4370                 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
4371                 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
4372         pa_sc_tile_steering_override |=
4373                 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
4374                 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
4375         pa_sc_tile_steering_override |=
4376                 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
4377                 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
4378
4379         return pa_sc_tile_steering_override;
4380 }
4381
4382 #define DEFAULT_SH_MEM_BASES    (0x6000)
4383 #define FIRST_COMPUTE_VMID      (8)
4384 #define LAST_COMPUTE_VMID       (16)
4385
4386 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
4387 {
4388         int i;
4389         uint32_t sh_mem_bases;
4390
4391         /*
4392          * Configure apertures:
4393          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
4394          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
4395          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
4396          */
4397         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
4398
4399         mutex_lock(&adev->srbm_mutex);
4400         for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
4401                 nv_grbm_select(adev, 0, 0, 0, i);
4402                 /* CP and shaders */
4403                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4404                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
4405         }
4406         nv_grbm_select(adev, 0, 0, 0, 0);
4407         mutex_unlock(&adev->srbm_mutex);
4408
4409         /* Initialize all compute VMIDs to have no GDS, GWS, or OA
4410            acccess. These should be enabled by FW for target VMIDs. */
4411         for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
4412                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
4413                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
4414                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
4415                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
4416         }
4417 }
4418
4419 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
4420 {
4421         int vmid;
4422
4423         /*
4424          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
4425          * access. Compute VMIDs should be enabled by FW for target VMIDs,
4426          * the driver can enable them for graphics. VMID0 should maintain
4427          * access so that HWS firmware can save/restore entries.
4428          */
4429         for (vmid = 1; vmid < 16; vmid++) {
4430                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
4431                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
4432                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
4433                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
4434         }
4435 }
4436
4437
4438 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
4439 {
4440         int i, j, k;
4441         int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
4442         u32 tmp, wgp_active_bitmap = 0;
4443         u32 gcrd_targets_disable_tcp = 0;
4444         u32 utcl_invreq_disable = 0;
4445         /*
4446          * GCRD_TARGETS_DISABLE field contains
4447          * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
4448          * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
4449          */
4450         u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
4451                 2 * max_wgp_per_sh + /* TCP */
4452                 max_wgp_per_sh + /* SQC */
4453                 4); /* GL1C */
4454         /*
4455          * UTCL1_UTCL0_INVREQ_DISABLE field contains
4456          * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
4457          * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
4458          */
4459         u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
4460                 2 * max_wgp_per_sh + /* TCP */
4461                 2 * max_wgp_per_sh + /* SQC */
4462                 4 + /* RMI */
4463                 1); /* SQG */
4464
4465         if (adev->asic_type == CHIP_NAVI10 ||
4466             adev->asic_type == CHIP_NAVI14 ||
4467             adev->asic_type == CHIP_NAVI12) {
4468                 mutex_lock(&adev->grbm_idx_mutex);
4469                 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4470                         for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4471                                 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4472                                 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
4473                                 /*
4474                                  * Set corresponding TCP bits for the inactive WGPs in
4475                                  * GCRD_SA_TARGETS_DISABLE
4476                                  */
4477                                 gcrd_targets_disable_tcp = 0;
4478                                 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
4479                                 utcl_invreq_disable = 0;
4480
4481                                 for (k = 0; k < max_wgp_per_sh; k++) {
4482                                         if (!(wgp_active_bitmap & (1 << k))) {
4483                                                 gcrd_targets_disable_tcp |= 3 << (2 * k);
4484                                                 utcl_invreq_disable |= (3 << (2 * k)) |
4485                                                         (3 << (2 * (max_wgp_per_sh + k)));
4486                                         }
4487                                 }
4488
4489                                 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
4490                                 /* only override TCP & SQC bits */
4491                                 tmp &= 0xffffffff << (4 * max_wgp_per_sh);
4492                                 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
4493                                 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
4494
4495                                 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
4496                                 /* only override TCP bits */
4497                                 tmp &= 0xffffffff << (2 * max_wgp_per_sh);
4498                                 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
4499                                 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
4500                         }
4501                 }
4502
4503                 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4504                 mutex_unlock(&adev->grbm_idx_mutex);
4505         }
4506 }
4507
4508 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
4509 {
4510         /* TCCs are global (not instanced). */
4511         uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
4512                                RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
4513
4514         adev->gfx.config.tcc_disabled_mask =
4515                 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
4516                 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
4517 }
4518
4519 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
4520 {
4521         u32 tmp;
4522         int i;
4523
4524         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
4525
4526         gfx_v10_0_tiling_mode_table_init(adev);
4527
4528         gfx_v10_0_setup_rb(adev);
4529         gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
4530         gfx_v10_0_get_tcc_info(adev);
4531         adev->gfx.config.pa_sc_tile_steering_override =
4532                 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
4533
4534         /* XXX SH_MEM regs */
4535         /* where to put LDS, scratch, GPUVM in FSA64 space */
4536         mutex_lock(&adev->srbm_mutex);
4537         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
4538                 nv_grbm_select(adev, 0, 0, 0, i);
4539                 /* CP and shaders */
4540                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4541                 if (i != 0) {
4542                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
4543                                 (adev->gmc.private_aperture_start >> 48));
4544                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
4545                                 (adev->gmc.shared_aperture_start >> 48));
4546                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
4547                 }
4548         }
4549         nv_grbm_select(adev, 0, 0, 0, 0);
4550
4551         mutex_unlock(&adev->srbm_mutex);
4552
4553         gfx_v10_0_init_compute_vmid(adev);
4554         gfx_v10_0_init_gds_vmid(adev);
4555
4556 }
4557
4558 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
4559                                                bool enable)
4560 {
4561         u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
4562
4563         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
4564                             enable ? 1 : 0);
4565         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
4566                             enable ? 1 : 0);
4567         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
4568                             enable ? 1 : 0);
4569         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
4570                             enable ? 1 : 0);
4571
4572         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
4573 }
4574
4575 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
4576 {
4577         adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
4578
4579         /* csib */
4580         WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
4581                          adev->gfx.rlc.clear_state_gpu_addr >> 32);
4582         WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
4583                          adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
4584         WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
4585
4586         return 0;
4587 }
4588
4589 void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
4590 {
4591         u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
4592
4593         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
4594         WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
4595 }
4596
4597 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
4598 {
4599         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
4600         udelay(50);
4601         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
4602         udelay(50);
4603 }
4604
4605 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
4606                                              bool enable)
4607 {
4608         uint32_t rlc_pg_cntl;
4609
4610         rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
4611
4612         if (!enable) {
4613                 /* RLC_PG_CNTL[23] = 0 (default)
4614                  * RLC will wait for handshake acks with SMU
4615                  * GFXOFF will be enabled
4616                  * RLC_PG_CNTL[23] = 1
4617                  * RLC will not issue any message to SMU
4618                  * hence no handshake between SMU & RLC
4619                  * GFXOFF will be disabled
4620                  */
4621                 rlc_pg_cntl |= 0x800000;
4622         } else
4623                 rlc_pg_cntl &= ~0x800000;
4624         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
4625 }
4626
4627 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
4628 {
4629         /* TODO: enable rlc & smu handshake until smu
4630          * and gfxoff feature works as expected */
4631         if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
4632                 gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
4633
4634         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
4635         udelay(50);
4636 }
4637
4638 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
4639 {
4640         uint32_t tmp;
4641
4642         /* enable Save Restore Machine */
4643         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
4644         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
4645         tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
4646         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
4647 }
4648
4649 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
4650 {
4651         const struct rlc_firmware_header_v2_0 *hdr;
4652         const __le32 *fw_data;
4653         unsigned i, fw_size;
4654
4655         if (!adev->gfx.rlc_fw)
4656                 return -EINVAL;
4657
4658         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
4659         amdgpu_ucode_print_rlc_hdr(&hdr->header);
4660
4661         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
4662                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
4663         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
4664
4665         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
4666                      RLCG_UCODE_LOADING_START_ADDRESS);
4667
4668         for (i = 0; i < fw_size; i++)
4669                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
4670                              le32_to_cpup(fw_data++));
4671
4672         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
4673
4674         return 0;
4675 }
4676
4677 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
4678 {
4679         int r;
4680
4681         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
4682
4683                 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
4684                 if (r)
4685                         return r;
4686
4687                 gfx_v10_0_init_csb(adev);
4688
4689                 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
4690                         gfx_v10_0_rlc_enable_srm(adev);
4691         } else {
4692                 if (amdgpu_sriov_vf(adev)) {
4693                         gfx_v10_0_init_csb(adev);
4694                         return 0;
4695                 }
4696
4697                 adev->gfx.rlc.funcs->stop(adev);
4698
4699                 /* disable CG */
4700                 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
4701
4702                 /* disable PG */
4703                 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
4704
4705                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4706                         /* legacy rlc firmware loading */
4707                         r = gfx_v10_0_rlc_load_microcode(adev);
4708                         if (r)
4709                                 return r;
4710                 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4711                         /* rlc backdoor autoload firmware */
4712                         r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
4713                         if (r)
4714                                 return r;
4715                 }
4716
4717                 gfx_v10_0_init_csb(adev);
4718
4719                 adev->gfx.rlc.funcs->start(adev);
4720
4721                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4722                         r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
4723                         if (r)
4724                                 return r;
4725                 }
4726         }
4727         return 0;
4728 }
4729
4730 static struct {
4731         FIRMWARE_ID     id;
4732         unsigned int    offset;
4733         unsigned int    size;
4734 } rlc_autoload_info[FIRMWARE_ID_MAX];
4735
4736 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
4737 {
4738         int ret;
4739         RLC_TABLE_OF_CONTENT *rlc_toc;
4740
4741         ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE,
4742                                         AMDGPU_GEM_DOMAIN_GTT,
4743                                         &adev->gfx.rlc.rlc_toc_bo,
4744                                         &adev->gfx.rlc.rlc_toc_gpu_addr,
4745                                         (void **)&adev->gfx.rlc.rlc_toc_buf);
4746         if (ret) {
4747                 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
4748                 return ret;
4749         }
4750
4751         /* Copy toc from psp sos fw to rlc toc buffer */
4752         memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size);
4753
4754         rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
4755         while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
4756                 (rlc_toc->id < FIRMWARE_ID_MAX)) {
4757                 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
4758                     (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
4759                         /* Offset needs 4KB alignment */
4760                         rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
4761                 }
4762
4763                 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
4764                 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
4765                 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
4766
4767                 rlc_toc++;
4768         }
4769
4770         return 0;
4771 }
4772
4773 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
4774 {
4775         uint32_t total_size = 0;
4776         FIRMWARE_ID id;
4777         int ret;
4778
4779         ret = gfx_v10_0_parse_rlc_toc(adev);
4780         if (ret) {
4781                 dev_err(adev->dev, "failed to parse rlc toc\n");
4782                 return 0;
4783         }
4784
4785         for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
4786                 total_size += rlc_autoload_info[id].size;
4787
4788         /* In case the offset in rlc toc ucode is aligned */
4789         if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
4790                 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
4791                                 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
4792
4793         return total_size;
4794 }
4795
4796 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
4797 {
4798         int r;
4799         uint32_t total_size;
4800
4801         total_size = gfx_v10_0_calc_toc_total_size(adev);
4802
4803         r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
4804                                       AMDGPU_GEM_DOMAIN_GTT,
4805                                       &adev->gfx.rlc.rlc_autoload_bo,
4806                                       &adev->gfx.rlc.rlc_autoload_gpu_addr,
4807                                       (void **)&adev->gfx.rlc.rlc_autoload_ptr);
4808         if (r) {
4809                 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
4810                 return r;
4811         }
4812
4813         return 0;
4814 }
4815
4816 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
4817 {
4818         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
4819                               &adev->gfx.rlc.rlc_toc_gpu_addr,
4820                               (void **)&adev->gfx.rlc.rlc_toc_buf);
4821         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
4822                               &adev->gfx.rlc.rlc_autoload_gpu_addr,
4823                               (void **)&adev->gfx.rlc.rlc_autoload_ptr);
4824 }
4825
4826 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
4827                                                        FIRMWARE_ID id,
4828                                                        const void *fw_data,
4829                                                        uint32_t fw_size)
4830 {
4831         uint32_t toc_offset;
4832         uint32_t toc_fw_size;
4833         char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
4834
4835         if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
4836                 return;
4837
4838         toc_offset = rlc_autoload_info[id].offset;
4839         toc_fw_size = rlc_autoload_info[id].size;
4840
4841         if (fw_size == 0)
4842                 fw_size = toc_fw_size;
4843
4844         if (fw_size > toc_fw_size)
4845                 fw_size = toc_fw_size;
4846
4847         memcpy(ptr + toc_offset, fw_data, fw_size);
4848
4849         if (fw_size < toc_fw_size)
4850                 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
4851 }
4852
4853 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
4854 {
4855         void *data;
4856         uint32_t size;
4857
4858         data = adev->gfx.rlc.rlc_toc_buf;
4859         size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
4860
4861         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
4862                                                    FIRMWARE_ID_RLC_TOC,
4863                                                    data, size);
4864 }
4865
4866 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
4867 {
4868         const __le32 *fw_data;
4869         uint32_t fw_size;
4870         const struct gfx_firmware_header_v1_0 *cp_hdr;
4871         const struct rlc_firmware_header_v2_0 *rlc_hdr;
4872
4873         /* pfp ucode */
4874         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
4875                 adev->gfx.pfp_fw->data;
4876         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
4877                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
4878         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
4879         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
4880                                                    FIRMWARE_ID_CP_PFP,
4881                                                    fw_data, fw_size);
4882
4883         /* ce ucode */
4884         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
4885                 adev->gfx.ce_fw->data;
4886         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
4887                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
4888         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
4889         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
4890                                                    FIRMWARE_ID_CP_CE,
4891                                                    fw_data, fw_size);
4892
4893         /* me ucode */
4894         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
4895                 adev->gfx.me_fw->data;
4896         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
4897                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
4898         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
4899         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
4900                                                    FIRMWARE_ID_CP_ME,
4901                                                    fw_data, fw_size);
4902
4903         /* rlc ucode */
4904         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
4905                 adev->gfx.rlc_fw->data;
4906         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
4907                 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
4908         fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
4909         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
4910                                                    FIRMWARE_ID_RLC_G_UCODE,
4911                                                    fw_data, fw_size);
4912
4913         /* mec1 ucode */
4914         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
4915                 adev->gfx.mec_fw->data;
4916         fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4917                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
4918         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
4919                 cp_hdr->jt_size * 4;
4920         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
4921                                                    FIRMWARE_ID_CP_MEC,
4922                                                    fw_data, fw_size);
4923         /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
4924 }
4925
4926 /* Temporarily put sdma part here */
4927 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
4928 {
4929         const __le32 *fw_data;
4930         uint32_t fw_size;
4931         const struct sdma_firmware_header_v1_0 *sdma_hdr;
4932         int i;
4933
4934         for (i = 0; i < adev->sdma.num_instances; i++) {
4935                 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
4936                         adev->sdma.instance[i].fw->data;
4937                 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
4938                         le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
4939                 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
4940
4941                 if (i == 0) {
4942                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
4943                                 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
4944                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
4945                                 FIRMWARE_ID_SDMA0_JT,
4946                                 (uint32_t *)fw_data +
4947                                 sdma_hdr->jt_offset,
4948                                 sdma_hdr->jt_size * 4);
4949                 } else if (i == 1) {
4950                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
4951                                 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
4952                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
4953                                 FIRMWARE_ID_SDMA1_JT,
4954                                 (uint32_t *)fw_data +
4955                                 sdma_hdr->jt_offset,
4956                                 sdma_hdr->jt_size * 4);
4957                 }
4958         }
4959 }
4960
4961 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
4962 {
4963         uint32_t rlc_g_offset, rlc_g_size, tmp;
4964         uint64_t gpu_addr;
4965
4966         gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
4967         gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
4968         gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
4969
4970         rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
4971         rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
4972         gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
4973
4974         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
4975         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
4976         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
4977
4978         tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
4979         if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
4980                    RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
4981                 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
4982                 return -EINVAL;
4983         }
4984
4985         tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
4986         if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
4987                 DRM_ERROR("RLC ROM should halt itself\n");
4988                 return -EINVAL;
4989         }
4990
4991         return 0;
4992 }
4993
4994 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
4995 {
4996         uint32_t usec_timeout = 50000;  /* wait for 50ms */
4997         uint32_t tmp;
4998         int i;
4999         uint64_t addr;
5000
5001         /* Trigger an invalidation of the L1 instruction caches */
5002         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5003         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5004         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5005
5006         /* Wait for invalidation complete */
5007         for (i = 0; i < usec_timeout; i++) {
5008                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5009                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5010                         INVALIDATE_CACHE_COMPLETE))
5011                         break;
5012                 udelay(1);
5013         }
5014
5015         if (i >= usec_timeout) {
5016                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5017                 return -EINVAL;
5018         }
5019
5020         /* Program me ucode address into intruction cache address register */
5021         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5022                 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5023         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5024                         lower_32_bits(addr) & 0xFFFFF000);
5025         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5026                         upper_32_bits(addr));
5027
5028         return 0;
5029 }
5030
5031 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5032 {
5033         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5034         uint32_t tmp;
5035         int i;
5036         uint64_t addr;
5037
5038         /* Trigger an invalidation of the L1 instruction caches */
5039         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5040         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5041         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5042
5043         /* Wait for invalidation complete */
5044         for (i = 0; i < usec_timeout; i++) {
5045                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5046                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5047                         INVALIDATE_CACHE_COMPLETE))
5048                         break;
5049                 udelay(1);
5050         }
5051
5052         if (i >= usec_timeout) {
5053                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5054                 return -EINVAL;
5055         }
5056
5057         /* Program ce ucode address into intruction cache address register */
5058         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5059                 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5060         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5061                         lower_32_bits(addr) & 0xFFFFF000);
5062         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5063                         upper_32_bits(addr));
5064
5065         return 0;
5066 }
5067
5068 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5069 {
5070         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5071         uint32_t tmp;
5072         int i;
5073         uint64_t addr;
5074
5075         /* Trigger an invalidation of the L1 instruction caches */
5076         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5077         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5078         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5079
5080         /* Wait for invalidation complete */
5081         for (i = 0; i < usec_timeout; i++) {
5082                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5083                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5084                         INVALIDATE_CACHE_COMPLETE))
5085                         break;
5086                 udelay(1);
5087         }
5088
5089         if (i >= usec_timeout) {
5090                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5091                 return -EINVAL;
5092         }
5093
5094         /* Program pfp ucode address into intruction cache address register */
5095         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5096                 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5097         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5098                         lower_32_bits(addr) & 0xFFFFF000);
5099         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5100                         upper_32_bits(addr));
5101
5102         return 0;
5103 }
5104
5105 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5106 {
5107         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5108         uint32_t tmp;
5109         int i;
5110         uint64_t addr;
5111
5112         /* Trigger an invalidation of the L1 instruction caches */
5113         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5114         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5115         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5116
5117         /* Wait for invalidation complete */
5118         for (i = 0; i < usec_timeout; i++) {
5119                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5120                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5121                         INVALIDATE_CACHE_COMPLETE))
5122                         break;
5123                 udelay(1);
5124         }
5125
5126         if (i >= usec_timeout) {
5127                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5128                 return -EINVAL;
5129         }
5130
5131         /* Program mec1 ucode address into intruction cache address register */
5132         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5133                 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5134         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5135                         lower_32_bits(addr) & 0xFFFFF000);
5136         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5137                         upper_32_bits(addr));
5138
5139         return 0;
5140 }
5141
5142 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5143 {
5144         uint32_t cp_status;
5145         uint32_t bootload_status;
5146         int i, r;
5147
5148         for (i = 0; i < adev->usec_timeout; i++) {
5149                 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5150                 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
5151                 if ((cp_status == 0) &&
5152                     (REG_GET_FIELD(bootload_status,
5153                         RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
5154                         break;
5155                 }
5156                 udelay(1);
5157         }
5158
5159         if (i >= adev->usec_timeout) {
5160                 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
5161                 return -ETIMEDOUT;
5162         }
5163
5164         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5165                 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5166                 if (r)
5167                         return r;
5168
5169                 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5170                 if (r)
5171                         return r;
5172
5173                 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5174                 if (r)
5175                         return r;
5176
5177                 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5178                 if (r)
5179                         return r;
5180         }
5181
5182         return 0;
5183 }
5184
5185 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
5186 {
5187         int i;
5188         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
5189
5190         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
5191         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
5192         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
5193         WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
5194
5195         for (i = 0; i < adev->usec_timeout; i++) {
5196                 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
5197                         break;
5198                 udelay(1);
5199         }
5200
5201         if (i >= adev->usec_timeout)
5202                 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
5203
5204         return 0;
5205 }
5206
5207 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
5208 {
5209         int r;
5210         const struct gfx_firmware_header_v1_0 *pfp_hdr;
5211         const __le32 *fw_data;
5212         unsigned i, fw_size;
5213         uint32_t tmp;
5214         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5215
5216         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
5217                 adev->gfx.pfp_fw->data;
5218
5219         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
5220
5221         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5222                 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
5223         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
5224
5225         r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
5226                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5227                                       &adev->gfx.pfp.pfp_fw_obj,
5228                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
5229                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
5230         if (r) {
5231                 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
5232                 gfx_v10_0_pfp_fini(adev);
5233                 return r;
5234         }
5235
5236         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
5237
5238         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
5239         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
5240
5241         /* Trigger an invalidation of the L1 instruction caches */
5242         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5243         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5244         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5245
5246         /* Wait for invalidation complete */
5247         for (i = 0; i < usec_timeout; i++) {
5248                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5249                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5250                         INVALIDATE_CACHE_COMPLETE))
5251                         break;
5252                 udelay(1);
5253         }
5254
5255         if (i >= usec_timeout) {
5256                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5257                 return -EINVAL;
5258         }
5259
5260         if (amdgpu_emu_mode == 1)
5261                 adev->nbio.funcs->hdp_flush(adev, NULL);
5262
5263         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
5264         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
5265         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
5266         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
5267         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5268         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
5269         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5270                 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
5271         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5272                 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
5273
5274         return 0;
5275 }
5276
5277 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
5278 {
5279         int r;
5280         const struct gfx_firmware_header_v1_0 *ce_hdr;
5281         const __le32 *fw_data;
5282         unsigned i, fw_size;
5283         uint32_t tmp;
5284         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5285
5286         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
5287                 adev->gfx.ce_fw->data;
5288
5289         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
5290
5291         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5292                 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
5293         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
5294
5295         r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
5296                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5297                                       &adev->gfx.ce.ce_fw_obj,
5298                                       &adev->gfx.ce.ce_fw_gpu_addr,
5299                                       (void **)&adev->gfx.ce.ce_fw_ptr);
5300         if (r) {
5301                 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
5302                 gfx_v10_0_ce_fini(adev);
5303                 return r;
5304         }
5305
5306         memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
5307
5308         amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
5309         amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
5310
5311         /* Trigger an invalidation of the L1 instruction caches */
5312         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5313         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5314         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5315
5316         /* Wait for invalidation complete */
5317         for (i = 0; i < usec_timeout; i++) {
5318                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5319                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5320                         INVALIDATE_CACHE_COMPLETE))
5321                         break;
5322                 udelay(1);
5323         }
5324
5325         if (i >= usec_timeout) {
5326                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5327                 return -EINVAL;
5328         }
5329
5330         if (amdgpu_emu_mode == 1)
5331                 adev->nbio.funcs->hdp_flush(adev, NULL);
5332
5333         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
5334         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
5335         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
5336         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
5337         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5338         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5339                 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
5340         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5341                 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
5342
5343         return 0;
5344 }
5345
5346 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
5347 {
5348         int r;
5349         const struct gfx_firmware_header_v1_0 *me_hdr;
5350         const __le32 *fw_data;
5351         unsigned i, fw_size;
5352         uint32_t tmp;
5353         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5354
5355         me_hdr = (const struct gfx_firmware_header_v1_0 *)
5356                 adev->gfx.me_fw->data;
5357
5358         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
5359
5360         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5361                 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
5362         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
5363
5364         r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
5365                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5366                                       &adev->gfx.me.me_fw_obj,
5367                                       &adev->gfx.me.me_fw_gpu_addr,
5368                                       (void **)&adev->gfx.me.me_fw_ptr);
5369         if (r) {
5370                 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
5371                 gfx_v10_0_me_fini(adev);
5372                 return r;
5373         }
5374
5375         memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
5376
5377         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
5378         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
5379
5380         /* Trigger an invalidation of the L1 instruction caches */
5381         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5382         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5383         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5384
5385         /* Wait for invalidation complete */
5386         for (i = 0; i < usec_timeout; i++) {
5387                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5388                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5389                         INVALIDATE_CACHE_COMPLETE))
5390                         break;
5391                 udelay(1);
5392         }
5393
5394         if (i >= usec_timeout) {
5395                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5396                 return -EINVAL;
5397         }
5398
5399         if (amdgpu_emu_mode == 1)
5400                 adev->nbio.funcs->hdp_flush(adev, NULL);
5401
5402         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
5403         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
5404         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
5405         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
5406         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5407         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5408                 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
5409         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5410                 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
5411
5412         return 0;
5413 }
5414
5415 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
5416 {
5417         int r;
5418
5419         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
5420                 return -EINVAL;
5421
5422         gfx_v10_0_cp_gfx_enable(adev, false);
5423
5424         r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
5425         if (r) {
5426                 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
5427                 return r;
5428         }
5429
5430         r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
5431         if (r) {
5432                 dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
5433                 return r;
5434         }
5435
5436         r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
5437         if (r) {
5438                 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
5439                 return r;
5440         }
5441
5442         return 0;
5443 }
5444
5445 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
5446 {
5447         struct amdgpu_ring *ring;
5448         const struct cs_section_def *sect = NULL;
5449         const struct cs_extent_def *ext = NULL;
5450         int r, i;
5451         int ctx_reg_offset;
5452
5453         /* init the CP */
5454         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
5455                      adev->gfx.config.max_hw_contexts - 1);
5456         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
5457
5458         gfx_v10_0_cp_gfx_enable(adev, true);
5459
5460         ring = &adev->gfx.gfx_ring[0];
5461         r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
5462         if (r) {
5463                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
5464                 return r;
5465         }
5466
5467         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5468         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
5469
5470         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
5471         amdgpu_ring_write(ring, 0x80000000);
5472         amdgpu_ring_write(ring, 0x80000000);
5473
5474         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
5475                 for (ext = sect->section; ext->extent != NULL; ++ext) {
5476                         if (sect->id == SECT_CONTEXT) {
5477                                 amdgpu_ring_write(ring,
5478                                                   PACKET3(PACKET3_SET_CONTEXT_REG,
5479                                                           ext->reg_count));
5480                                 amdgpu_ring_write(ring, ext->reg_index -
5481                                                   PACKET3_SET_CONTEXT_REG_START);
5482                                 for (i = 0; i < ext->reg_count; i++)
5483                                         amdgpu_ring_write(ring, ext->extent[i]);
5484                         }
5485                 }
5486         }
5487
5488         ctx_reg_offset =
5489                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
5490         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
5491         amdgpu_ring_write(ring, ctx_reg_offset);
5492         amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
5493
5494         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5495         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
5496
5497         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
5498         amdgpu_ring_write(ring, 0);
5499
5500         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
5501         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
5502         amdgpu_ring_write(ring, 0x8000);
5503         amdgpu_ring_write(ring, 0x8000);
5504
5505         amdgpu_ring_commit(ring);
5506
5507         /* submit cs packet to copy state 0 to next available state */
5508         if (adev->gfx.num_gfx_rings > 1) {
5509                 /* maximum supported gfx ring is 2 */
5510                 ring = &adev->gfx.gfx_ring[1];
5511                 r = amdgpu_ring_alloc(ring, 2);
5512                 if (r) {
5513                         DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
5514                         return r;
5515                 }
5516
5517                 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
5518                 amdgpu_ring_write(ring, 0);
5519
5520                 amdgpu_ring_commit(ring);
5521         }
5522         return 0;
5523 }
5524
5525 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
5526                                          CP_PIPE_ID pipe)
5527 {
5528         u32 tmp;
5529
5530         tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
5531         tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
5532
5533         WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
5534 }
5535
5536 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
5537                                           struct amdgpu_ring *ring)
5538 {
5539         u32 tmp;
5540
5541         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
5542         if (ring->use_doorbell) {
5543                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5544                                     DOORBELL_OFFSET, ring->doorbell_index);
5545                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5546                                     DOORBELL_EN, 1);
5547         } else {
5548                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5549                                     DOORBELL_EN, 0);
5550         }
5551         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
5552         tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
5553                             DOORBELL_RANGE_LOWER, ring->doorbell_index);
5554         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
5555
5556         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
5557                      CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
5558 }
5559
5560 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
5561 {
5562         struct amdgpu_ring *ring;
5563         u32 tmp;
5564         u32 rb_bufsz;
5565         u64 rb_addr, rptr_addr, wptr_gpu_addr;
5566         u32 i;
5567
5568         /* Set the write pointer delay */
5569         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
5570
5571         /* set the RB to use vmid 0 */
5572         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
5573
5574         /* Init gfx ring 0 for pipe 0 */
5575         mutex_lock(&adev->srbm_mutex);
5576         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
5577
5578         /* Set ring buffer size */
5579         ring = &adev->gfx.gfx_ring[0];
5580         rb_bufsz = order_base_2(ring->ring_size / 8);
5581         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
5582         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
5583 #ifdef __BIG_ENDIAN
5584         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
5585 #endif
5586         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
5587
5588         /* Initialize the ring buffer's write pointers */
5589         ring->wptr = 0;
5590         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
5591         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
5592
5593         /* set the wb address wether it's enabled or not */
5594         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
5595         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
5596         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
5597                      CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
5598
5599         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
5600         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
5601                      lower_32_bits(wptr_gpu_addr));
5602         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
5603                      upper_32_bits(wptr_gpu_addr));
5604
5605         mdelay(1);
5606         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
5607
5608         rb_addr = ring->gpu_addr >> 8;
5609         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
5610         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
5611
5612         WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
5613
5614         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
5615         mutex_unlock(&adev->srbm_mutex);
5616
5617         /* Init gfx ring 1 for pipe 1 */
5618         if (adev->gfx.num_gfx_rings > 1) {
5619                 mutex_lock(&adev->srbm_mutex);
5620                 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
5621                 /* maximum supported gfx ring is 2 */
5622                 ring = &adev->gfx.gfx_ring[1];
5623                 rb_bufsz = order_base_2(ring->ring_size / 8);
5624                 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
5625                 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
5626                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
5627                 /* Initialize the ring buffer's write pointers */
5628                 ring->wptr = 0;
5629                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
5630                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
5631                 /* Set the wb address wether it's enabled or not */
5632                 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
5633                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
5634                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
5635                              CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
5636                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
5637                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
5638                              lower_32_bits(wptr_gpu_addr));
5639                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
5640                              upper_32_bits(wptr_gpu_addr));
5641
5642                 mdelay(1);
5643                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
5644
5645                 rb_addr = ring->gpu_addr >> 8;
5646                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
5647                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
5648                 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
5649
5650                 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
5651                 mutex_unlock(&adev->srbm_mutex);
5652         }
5653         /* Switch to pipe 0 */
5654         mutex_lock(&adev->srbm_mutex);
5655         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
5656         mutex_unlock(&adev->srbm_mutex);
5657
5658         /* start the ring */
5659         gfx_v10_0_cp_gfx_start(adev);
5660
5661         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
5662                 ring = &adev->gfx.gfx_ring[i];
5663                 ring->sched.ready = true;
5664         }
5665
5666         return 0;
5667 }
5668
5669 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
5670 {
5671         if (enable) {
5672                 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
5673         } else {
5674                 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
5675                              (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
5676                               CP_MEC_CNTL__MEC_ME2_HALT_MASK));
5677                 adev->gfx.kiq.ring.sched.ready = false;
5678         }
5679         udelay(50);
5680 }
5681
5682 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
5683 {
5684         const struct gfx_firmware_header_v1_0 *mec_hdr;
5685         const __le32 *fw_data;
5686         unsigned i;
5687         u32 tmp;
5688         u32 usec_timeout = 50000; /* Wait for 50 ms */
5689
5690         if (!adev->gfx.mec_fw)
5691                 return -EINVAL;
5692
5693         gfx_v10_0_cp_compute_enable(adev, false);
5694
5695         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
5696         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
5697
5698         fw_data = (const __le32 *)
5699                 (adev->gfx.mec_fw->data +
5700                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
5701
5702         /* Trigger an invalidation of the L1 instruction caches */
5703         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5704         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5705         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5706
5707         /* Wait for invalidation complete */
5708         for (i = 0; i < usec_timeout; i++) {
5709                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5710                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5711                                        INVALIDATE_CACHE_COMPLETE))
5712                         break;
5713                 udelay(1);
5714         }
5715
5716         if (i >= usec_timeout) {
5717                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5718                 return -EINVAL;
5719         }
5720
5721         if (amdgpu_emu_mode == 1)
5722                 adev->nbio.funcs->hdp_flush(adev, NULL);
5723
5724         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
5725         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
5726         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
5727         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5728         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
5729
5730         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
5731                      0xFFFFF000);
5732         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5733                      upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
5734
5735         /* MEC1 */
5736         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
5737
5738         for (i = 0; i < mec_hdr->jt_size; i++)
5739                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
5740                              le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
5741
5742         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
5743
5744         /*
5745          * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
5746          * different microcode than MEC1.
5747          */
5748
5749         return 0;
5750 }
5751
5752 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
5753 {
5754         uint32_t tmp;
5755         struct amdgpu_device *adev = ring->adev;
5756
5757         /* tell RLC which is KIQ queue */
5758         tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
5759         tmp &= 0xffffff00;
5760         tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
5761         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
5762         tmp |= 0x80;
5763         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
5764 }
5765
5766 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
5767 {
5768         struct amdgpu_device *adev = ring->adev;
5769         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
5770         uint64_t hqd_gpu_addr, wb_gpu_addr;
5771         uint32_t tmp;
5772         uint32_t rb_bufsz;
5773
5774         /* set up gfx hqd wptr */
5775         mqd->cp_gfx_hqd_wptr = 0;
5776         mqd->cp_gfx_hqd_wptr_hi = 0;
5777
5778         /* set the pointer to the MQD */
5779         mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc;
5780         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
5781
5782         /* set up mqd control */
5783         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
5784         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
5785         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
5786         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
5787         mqd->cp_gfx_mqd_control = tmp;
5788
5789         /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
5790         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
5791         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
5792         mqd->cp_gfx_hqd_vmid = 0;
5793
5794         /* set up default queue priority level
5795          * 0x0 = low priority, 0x1 = high priority */
5796         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
5797         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
5798         mqd->cp_gfx_hqd_queue_priority = tmp;
5799
5800         /* set up time quantum */
5801         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
5802         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
5803         mqd->cp_gfx_hqd_quantum = tmp;
5804
5805         /* set up gfx hqd base. this is similar as CP_RB_BASE */
5806         hqd_gpu_addr = ring->gpu_addr >> 8;
5807         mqd->cp_gfx_hqd_base = hqd_gpu_addr;
5808         mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
5809
5810         /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
5811         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
5812         mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
5813         mqd->cp_gfx_hqd_rptr_addr_hi =
5814                 upper_32_bits(wb_gpu_addr) & 0xffff;
5815
5816         /* set up rb_wptr_poll addr */
5817         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
5818         mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
5819         mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
5820
5821         /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
5822         rb_bufsz = order_base_2(ring->ring_size / 4) - 1;
5823         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
5824         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
5825         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
5826 #ifdef __BIG_ENDIAN
5827         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
5828 #endif
5829         mqd->cp_gfx_hqd_cntl = tmp;
5830
5831         /* set up cp_doorbell_control */
5832         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
5833         if (ring->use_doorbell) {
5834                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5835                                     DOORBELL_OFFSET, ring->doorbell_index);
5836                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5837                                     DOORBELL_EN, 1);
5838         } else
5839                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5840                                     DOORBELL_EN, 0);
5841         mqd->cp_rb_doorbell_control = tmp;
5842
5843         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
5844         ring->wptr = 0;
5845         mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
5846
5847         /* active the queue */
5848         mqd->cp_gfx_hqd_active = 1;
5849
5850         return 0;
5851 }
5852
5853 #ifdef BRING_UP_DEBUG
5854 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
5855 {
5856         struct amdgpu_device *adev = ring->adev;
5857         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
5858
5859         /* set mmCP_GFX_HQD_WPTR/_HI to 0 */
5860         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
5861         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
5862
5863         /* set GFX_MQD_BASE */
5864         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
5865         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
5866
5867         /* set GFX_MQD_CONTROL */
5868         WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
5869
5870         /* set GFX_HQD_VMID to 0 */
5871         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
5872
5873         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
5874                         mqd->cp_gfx_hqd_queue_priority);
5875         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
5876
5877         /* set GFX_HQD_BASE, similar as CP_RB_BASE */
5878         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
5879         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
5880
5881         /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
5882         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
5883         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
5884
5885         /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
5886         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
5887
5888         /* set RB_WPTR_POLL_ADDR */
5889         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
5890         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
5891
5892         /* set RB_DOORBELL_CONTROL */
5893         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
5894
5895         /* active the queue */
5896         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
5897
5898         return 0;
5899 }
5900 #endif
5901
5902 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
5903 {
5904         struct amdgpu_device *adev = ring->adev;
5905         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
5906         int mqd_idx = ring - &adev->gfx.gfx_ring[0];
5907
5908         if (!adev->in_gpu_reset && !adev->in_suspend) {
5909                 memset((void *)mqd, 0, sizeof(*mqd));
5910                 mutex_lock(&adev->srbm_mutex);
5911                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
5912                 gfx_v10_0_gfx_mqd_init(ring);
5913 #ifdef BRING_UP_DEBUG
5914                 gfx_v10_0_gfx_queue_init_register(ring);
5915 #endif
5916                 nv_grbm_select(adev, 0, 0, 0, 0);
5917                 mutex_unlock(&adev->srbm_mutex);
5918                 if (adev->gfx.me.mqd_backup[mqd_idx])
5919                         memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
5920         } else if (adev->in_gpu_reset) {
5921                 /* reset mqd with the backup copy */
5922                 if (adev->gfx.me.mqd_backup[mqd_idx])
5923                         memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
5924                 /* reset the ring */
5925                 ring->wptr = 0;
5926                 adev->wb.wb[ring->wptr_offs] = 0;
5927                 amdgpu_ring_clear_ring(ring);
5928 #ifdef BRING_UP_DEBUG
5929                 mutex_lock(&adev->srbm_mutex);
5930                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
5931                 gfx_v10_0_gfx_queue_init_register(ring);
5932                 nv_grbm_select(adev, 0, 0, 0, 0);
5933                 mutex_unlock(&adev->srbm_mutex);
5934 #endif
5935         } else {
5936                 amdgpu_ring_clear_ring(ring);
5937         }
5938
5939         return 0;
5940 }
5941
5942 #ifndef BRING_UP_DEBUG
5943 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
5944 {
5945         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
5946         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
5947         int r, i;
5948
5949         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
5950                 return -EINVAL;
5951
5952         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
5953                                         adev->gfx.num_gfx_rings);
5954         if (r) {
5955                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
5956                 return r;
5957         }
5958
5959         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
5960                 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
5961
5962         return amdgpu_ring_test_helper(kiq_ring);
5963 }
5964 #endif
5965
5966 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
5967 {
5968         int r, i;
5969         struct amdgpu_ring *ring;
5970
5971         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
5972                 ring = &adev->gfx.gfx_ring[i];
5973
5974                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
5975                 if (unlikely(r != 0))
5976                         goto done;
5977
5978                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
5979                 if (!r) {
5980                         r = gfx_v10_0_gfx_init_queue(ring);
5981                         amdgpu_bo_kunmap(ring->mqd_obj);
5982                         ring->mqd_ptr = NULL;
5983                 }
5984                 amdgpu_bo_unreserve(ring->mqd_obj);
5985                 if (r)
5986                         goto done;
5987         }
5988 #ifndef BRING_UP_DEBUG
5989         r = gfx_v10_0_kiq_enable_kgq(adev);
5990         if (r)
5991                 goto done;
5992 #endif
5993         r = gfx_v10_0_cp_gfx_start(adev);
5994         if (r)
5995                 goto done;
5996
5997         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
5998                 ring = &adev->gfx.gfx_ring[i];
5999                 ring->sched.ready = true;
6000         }
6001 done:
6002         return r;
6003 }
6004
6005 static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd)
6006 {
6007         struct amdgpu_device *adev = ring->adev;
6008
6009         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
6010                 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue)) {
6011                         mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
6012                         mqd->cp_hqd_queue_priority =
6013                                 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
6014                 }
6015         }
6016 }
6017
6018 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
6019 {
6020         struct amdgpu_device *adev = ring->adev;
6021         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6022         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6023         uint32_t tmp;
6024
6025         mqd->header = 0xC0310800;
6026         mqd->compute_pipelinestat_enable = 0x00000001;
6027         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6028         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6029         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6030         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6031         mqd->compute_misc_reserved = 0x00000003;
6032
6033         eop_base_addr = ring->eop_gpu_addr >> 8;
6034         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6035         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6036
6037         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6038         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6039         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6040                         (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6041
6042         mqd->cp_hqd_eop_control = tmp;
6043
6044         /* enable doorbell? */
6045         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6046
6047         if (ring->use_doorbell) {
6048                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6049                                     DOORBELL_OFFSET, ring->doorbell_index);
6050                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6051                                     DOORBELL_EN, 1);
6052                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6053                                     DOORBELL_SOURCE, 0);
6054                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6055                                     DOORBELL_HIT, 0);
6056         } else {
6057                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6058                                     DOORBELL_EN, 0);
6059         }
6060
6061         mqd->cp_hqd_pq_doorbell_control = tmp;
6062
6063         /* disable the queue if it's active */
6064         ring->wptr = 0;
6065         mqd->cp_hqd_dequeue_request = 0;
6066         mqd->cp_hqd_pq_rptr = 0;
6067         mqd->cp_hqd_pq_wptr_lo = 0;
6068         mqd->cp_hqd_pq_wptr_hi = 0;
6069
6070         /* set the pointer to the MQD */
6071         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
6072         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6073
6074         /* set MQD vmid to 0 */
6075         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6076         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6077         mqd->cp_mqd_control = tmp;
6078
6079         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6080         hqd_gpu_addr = ring->gpu_addr >> 8;
6081         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6082         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6083
6084         /* set up the HQD, this is similar to CP_RB0_CNTL */
6085         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6086         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6087                             (order_base_2(ring->ring_size / 4) - 1));
6088         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6089                             ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
6090 #ifdef __BIG_ENDIAN
6091         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6092 #endif
6093         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
6094         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
6095         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6096         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6097         mqd->cp_hqd_pq_control = tmp;
6098
6099         /* set the wb address whether it's enabled or not */
6100         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6101         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6102         mqd->cp_hqd_pq_rptr_report_addr_hi =
6103                 upper_32_bits(wb_gpu_addr) & 0xffff;
6104
6105         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6106         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6107         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6108         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6109
6110         tmp = 0;
6111         /* enable the doorbell if requested */
6112         if (ring->use_doorbell) {
6113                 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6114                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6115                                 DOORBELL_OFFSET, ring->doorbell_index);
6116
6117                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6118                                     DOORBELL_EN, 1);
6119                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6120                                     DOORBELL_SOURCE, 0);
6121                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6122                                     DOORBELL_HIT, 0);
6123         }
6124
6125         mqd->cp_hqd_pq_doorbell_control = tmp;
6126
6127         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6128         ring->wptr = 0;
6129         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6130
6131         /* set the vmid for the queue */
6132         mqd->cp_hqd_vmid = 0;
6133
6134         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6135         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
6136         mqd->cp_hqd_persistent_state = tmp;
6137
6138         /* set MIN_IB_AVAIL_SIZE */
6139         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
6140         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
6141         mqd->cp_hqd_ib_control = tmp;
6142
6143         /* set static priority for a compute queue/ring */
6144         gfx_v10_0_compute_mqd_set_priority(ring, mqd);
6145
6146         /* map_queues packet doesn't need activate the queue,
6147          * so only kiq need set this field.
6148          */
6149         if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
6150                 mqd->cp_hqd_active = 1;
6151
6152         return 0;
6153 }
6154
6155 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
6156 {
6157         struct amdgpu_device *adev = ring->adev;
6158         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6159         int j;
6160
6161         /* disable wptr polling */
6162         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
6163
6164         /* write the EOP addr */
6165         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
6166                mqd->cp_hqd_eop_base_addr_lo);
6167         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
6168                mqd->cp_hqd_eop_base_addr_hi);
6169
6170         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6171         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
6172                mqd->cp_hqd_eop_control);
6173
6174         /* enable doorbell? */
6175         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6176                mqd->cp_hqd_pq_doorbell_control);
6177
6178         /* disable the queue if it's active */
6179         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
6180                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
6181                 for (j = 0; j < adev->usec_timeout; j++) {
6182                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
6183                                 break;
6184                         udelay(1);
6185                 }
6186                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
6187                        mqd->cp_hqd_dequeue_request);
6188                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
6189                        mqd->cp_hqd_pq_rptr);
6190                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6191                        mqd->cp_hqd_pq_wptr_lo);
6192                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6193                        mqd->cp_hqd_pq_wptr_hi);
6194         }
6195
6196         /* set the pointer to the MQD */
6197         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
6198                mqd->cp_mqd_base_addr_lo);
6199         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
6200                mqd->cp_mqd_base_addr_hi);
6201
6202         /* set MQD vmid to 0 */
6203         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
6204                mqd->cp_mqd_control);
6205
6206         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6207         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
6208                mqd->cp_hqd_pq_base_lo);
6209         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
6210                mqd->cp_hqd_pq_base_hi);
6211
6212         /* set up the HQD, this is similar to CP_RB0_CNTL */
6213         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
6214                mqd->cp_hqd_pq_control);
6215
6216         /* set the wb address whether it's enabled or not */
6217         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
6218                 mqd->cp_hqd_pq_rptr_report_addr_lo);
6219         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
6220                 mqd->cp_hqd_pq_rptr_report_addr_hi);
6221
6222         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6223         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
6224                mqd->cp_hqd_pq_wptr_poll_addr_lo);
6225         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
6226                mqd->cp_hqd_pq_wptr_poll_addr_hi);
6227
6228         /* enable the doorbell if requested */
6229         if (ring->use_doorbell) {
6230                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
6231                         (adev->doorbell_index.kiq * 2) << 2);
6232                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
6233                         (adev->doorbell_index.userqueue_end * 2) << 2);
6234         }
6235
6236         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6237                mqd->cp_hqd_pq_doorbell_control);
6238
6239         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6240         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6241                mqd->cp_hqd_pq_wptr_lo);
6242         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6243                mqd->cp_hqd_pq_wptr_hi);
6244
6245         /* set the vmid for the queue */
6246         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
6247
6248         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
6249                mqd->cp_hqd_persistent_state);
6250
6251         /* activate the queue */
6252         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
6253                mqd->cp_hqd_active);
6254
6255         if (ring->use_doorbell)
6256                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
6257
6258         return 0;
6259 }
6260
6261 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
6262 {
6263         struct amdgpu_device *adev = ring->adev;
6264         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6265         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
6266
6267         gfx_v10_0_kiq_setting(ring);
6268
6269         if (adev->in_gpu_reset) { /* for GPU_RESET case */
6270                 /* reset MQD to a clean status */
6271                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6272                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6273
6274                 /* reset ring buffer */
6275                 ring->wptr = 0;
6276                 amdgpu_ring_clear_ring(ring);
6277
6278                 mutex_lock(&adev->srbm_mutex);
6279                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6280                 gfx_v10_0_kiq_init_register(ring);
6281                 nv_grbm_select(adev, 0, 0, 0, 0);
6282                 mutex_unlock(&adev->srbm_mutex);
6283         } else {
6284                 memset((void *)mqd, 0, sizeof(*mqd));
6285                 mutex_lock(&adev->srbm_mutex);
6286                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6287                 gfx_v10_0_compute_mqd_init(ring);
6288                 gfx_v10_0_kiq_init_register(ring);
6289                 nv_grbm_select(adev, 0, 0, 0, 0);
6290                 mutex_unlock(&adev->srbm_mutex);
6291
6292                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6293                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6294         }
6295
6296         return 0;
6297 }
6298
6299 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
6300 {
6301         struct amdgpu_device *adev = ring->adev;
6302         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6303         int mqd_idx = ring - &adev->gfx.compute_ring[0];
6304
6305         if (!adev->in_gpu_reset && !adev->in_suspend) {
6306                 memset((void *)mqd, 0, sizeof(*mqd));
6307                 mutex_lock(&adev->srbm_mutex);
6308                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6309                 gfx_v10_0_compute_mqd_init(ring);
6310                 nv_grbm_select(adev, 0, 0, 0, 0);
6311                 mutex_unlock(&adev->srbm_mutex);
6312
6313                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6314                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6315         } else if (adev->in_gpu_reset) { /* for GPU_RESET case */
6316                 /* reset MQD to a clean status */
6317                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6318                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6319
6320                 /* reset ring buffer */
6321                 ring->wptr = 0;
6322                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
6323                 amdgpu_ring_clear_ring(ring);
6324         } else {
6325                 amdgpu_ring_clear_ring(ring);
6326         }
6327
6328         return 0;
6329 }
6330
6331 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
6332 {
6333         struct amdgpu_ring *ring;
6334         int r;
6335
6336         ring = &adev->gfx.kiq.ring;
6337
6338         r = amdgpu_bo_reserve(ring->mqd_obj, false);
6339         if (unlikely(r != 0))
6340                 return r;
6341
6342         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6343         if (unlikely(r != 0))
6344                 return r;
6345
6346         gfx_v10_0_kiq_init_queue(ring);
6347         amdgpu_bo_kunmap(ring->mqd_obj);
6348         ring->mqd_ptr = NULL;
6349         amdgpu_bo_unreserve(ring->mqd_obj);
6350         ring->sched.ready = true;
6351         return 0;
6352 }
6353
6354 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
6355 {
6356         struct amdgpu_ring *ring = NULL;
6357         int r = 0, i;
6358
6359         gfx_v10_0_cp_compute_enable(adev, true);
6360
6361         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6362                 ring = &adev->gfx.compute_ring[i];
6363
6364                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6365                 if (unlikely(r != 0))
6366                         goto done;
6367                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6368                 if (!r) {
6369                         r = gfx_v10_0_kcq_init_queue(ring);
6370                         amdgpu_bo_kunmap(ring->mqd_obj);
6371                         ring->mqd_ptr = NULL;
6372                 }
6373                 amdgpu_bo_unreserve(ring->mqd_obj);
6374                 if (r)
6375                         goto done;
6376         }
6377
6378         r = amdgpu_gfx_enable_kcq(adev);
6379 done:
6380         return r;
6381 }
6382
6383 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
6384 {
6385         int r, i;
6386         struct amdgpu_ring *ring;
6387
6388         if (!(adev->flags & AMD_IS_APU))
6389                 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
6390
6391         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
6392                 /* legacy firmware loading */
6393                 r = gfx_v10_0_cp_gfx_load_microcode(adev);
6394                 if (r)
6395                         return r;
6396
6397                 r = gfx_v10_0_cp_compute_load_microcode(adev);
6398                 if (r)
6399                         return r;
6400         }
6401
6402         r = gfx_v10_0_kiq_resume(adev);
6403         if (r)
6404                 return r;
6405
6406         r = gfx_v10_0_kcq_resume(adev);
6407         if (r)
6408                 return r;
6409
6410         if (!amdgpu_async_gfx_ring) {
6411                 r = gfx_v10_0_cp_gfx_resume(adev);
6412                 if (r)
6413                         return r;
6414         } else {
6415                 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
6416                 if (r)
6417                         return r;
6418         }
6419
6420         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6421                 ring = &adev->gfx.gfx_ring[i];
6422                 r = amdgpu_ring_test_helper(ring);
6423                 if (r)
6424                         return r;
6425         }
6426
6427         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6428                 ring = &adev->gfx.compute_ring[i];
6429                 r = amdgpu_ring_test_helper(ring);
6430                 if (r)
6431                         return r;
6432         }
6433
6434         return 0;
6435 }
6436
6437 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
6438 {
6439         gfx_v10_0_cp_gfx_enable(adev, enable);
6440         gfx_v10_0_cp_compute_enable(adev, enable);
6441 }
6442
6443 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
6444 {
6445         uint32_t data, pattern = 0xDEADBEEF;
6446
6447         /* check if mmVGT_ESGS_RING_SIZE_UMD
6448          * has been remapped to mmVGT_ESGS_RING_SIZE */
6449         data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
6450
6451         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
6452
6453         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
6454
6455         if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
6456                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
6457                 return true;
6458         } else {
6459                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
6460                 return false;
6461         }
6462 }
6463
6464 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
6465 {
6466         uint32_t data;
6467
6468         /* initialize cam_index to 0
6469          * index will auto-inc after each data writting */
6470         WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
6471
6472         /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
6473         data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
6474                 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6475                (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
6476                 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6477         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6478         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6479
6480         /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
6481         data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
6482                 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6483                (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
6484                 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6485         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6486         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6487
6488         /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
6489         data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
6490                 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6491                (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
6492                 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6493         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6494         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6495
6496         /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
6497         data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
6498                 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6499                (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
6500                 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6501         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6502         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6503
6504         /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
6505         data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
6506                 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6507                (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
6508                 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6509         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6510         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6511
6512         /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
6513         data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
6514                 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6515                (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
6516                 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6517         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6518         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6519
6520         /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
6521         data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
6522                 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6523                (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
6524                 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6525         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6526         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6527 }
6528
6529 static int gfx_v10_0_hw_init(void *handle)
6530 {
6531         int r;
6532         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6533
6534         if (!amdgpu_emu_mode)
6535                 gfx_v10_0_init_golden_registers(adev);
6536
6537         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
6538                 /**
6539                  * For gfx 10, rlc firmware loading relies on smu firmware is
6540                  * loaded firstly, so in direct type, it has to load smc ucode
6541                  * here before rlc.
6542                  */
6543                 if (adev->smu.ppt_funcs != NULL) {
6544                         r = smu_load_microcode(&adev->smu);
6545                         if (r)
6546                                 return r;
6547
6548                         r = smu_check_fw_status(&adev->smu);
6549                         if (r) {
6550                                 pr_err("SMC firmware status is not correct\n");
6551                                 return r;
6552                         }
6553                 }
6554         }
6555
6556         /* if GRBM CAM not remapped, set up the remapping */
6557         if (!gfx_v10_0_check_grbm_cam_remapping(adev))
6558                 gfx_v10_0_setup_grbm_cam_remapping(adev);
6559
6560         gfx_v10_0_constants_init(adev);
6561
6562         r = gfx_v10_0_rlc_resume(adev);
6563         if (r)
6564                 return r;
6565
6566         /*
6567          * init golden registers and rlc resume may override some registers,
6568          * reconfig them here
6569          */
6570         gfx_v10_0_tcp_harvest(adev);
6571
6572         r = gfx_v10_0_cp_resume(adev);
6573         if (r)
6574                 return r;
6575
6576         return r;
6577 }
6578
6579 #ifndef BRING_UP_DEBUG
6580 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
6581 {
6582         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
6583         struct amdgpu_ring *kiq_ring = &kiq->ring;
6584         int i;
6585
6586         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
6587                 return -EINVAL;
6588
6589         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
6590                                         adev->gfx.num_gfx_rings))
6591                 return -ENOMEM;
6592
6593         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6594                 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
6595                                            PREEMPT_QUEUES, 0, 0);
6596
6597         return amdgpu_ring_test_helper(kiq_ring);
6598 }
6599 #endif
6600
6601 static int gfx_v10_0_hw_fini(void *handle)
6602 {
6603         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6604         int r;
6605
6606         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
6607         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
6608 #ifndef BRING_UP_DEBUG
6609         if (amdgpu_async_gfx_ring) {
6610                 r = gfx_v10_0_kiq_disable_kgq(adev);
6611                 if (r)
6612                         DRM_ERROR("KGQ disable failed\n");
6613         }
6614 #endif
6615         if (amdgpu_gfx_disable_kcq(adev))
6616                 DRM_ERROR("KCQ disable failed\n");
6617         if (amdgpu_sriov_vf(adev)) {
6618                 gfx_v10_0_cp_gfx_enable(adev, false);
6619                 return 0;
6620         }
6621         gfx_v10_0_cp_enable(adev, false);
6622         gfx_v10_0_enable_gui_idle_interrupt(adev, false);
6623
6624         return 0;
6625 }
6626
6627 static int gfx_v10_0_suspend(void *handle)
6628 {
6629         return gfx_v10_0_hw_fini(handle);
6630 }
6631
6632 static int gfx_v10_0_resume(void *handle)
6633 {
6634         return gfx_v10_0_hw_init(handle);
6635 }
6636
6637 static bool gfx_v10_0_is_idle(void *handle)
6638 {
6639         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6640
6641         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
6642                                 GRBM_STATUS, GUI_ACTIVE))
6643                 return false;
6644         else
6645                 return true;
6646 }
6647
6648 static int gfx_v10_0_wait_for_idle(void *handle)
6649 {
6650         unsigned i;
6651         u32 tmp;
6652         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6653
6654         for (i = 0; i < adev->usec_timeout; i++) {
6655                 /* read MC_STATUS */
6656                 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
6657                         GRBM_STATUS__GUI_ACTIVE_MASK;
6658
6659                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
6660                         return 0;
6661                 udelay(1);
6662         }
6663         return -ETIMEDOUT;
6664 }
6665
6666 static int gfx_v10_0_soft_reset(void *handle)
6667 {
6668         u32 grbm_soft_reset = 0;
6669         u32 tmp;
6670         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6671
6672         /* GRBM_STATUS */
6673         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
6674         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
6675                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
6676                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
6677                    GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
6678                    GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK
6679                    | GRBM_STATUS__BCI_BUSY_MASK)) {
6680                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
6681                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
6682                                                 1);
6683                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
6684                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX,
6685                                                 1);
6686         }
6687
6688         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
6689                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
6690                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
6691                                                 1);
6692         }
6693
6694         /* GRBM_STATUS2 */
6695         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
6696         if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
6697                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
6698                                                 GRBM_SOFT_RESET, SOFT_RESET_RLC,
6699                                                 1);
6700
6701         if (grbm_soft_reset) {
6702                 /* stop the rlc */
6703                 gfx_v10_0_rlc_stop(adev);
6704
6705                 /* Disable GFX parsing/prefetching */
6706                 gfx_v10_0_cp_gfx_enable(adev, false);
6707
6708                 /* Disable MEC parsing/prefetching */
6709                 gfx_v10_0_cp_compute_enable(adev, false);
6710
6711                 if (grbm_soft_reset) {
6712                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
6713                         tmp |= grbm_soft_reset;
6714                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
6715                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
6716                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
6717
6718                         udelay(50);
6719
6720                         tmp &= ~grbm_soft_reset;
6721                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
6722                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
6723                 }
6724
6725                 /* Wait a little for things to settle down */
6726                 udelay(50);
6727         }
6728         return 0;
6729 }
6730
6731 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
6732 {
6733         uint64_t clock;
6734
6735         amdgpu_gfx_off_ctrl(adev, false);
6736         mutex_lock(&adev->gfx.gpu_clock_mutex);
6737         clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) |
6738                 ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL);
6739         mutex_unlock(&adev->gfx.gpu_clock_mutex);
6740         amdgpu_gfx_off_ctrl(adev, true);
6741         return clock;
6742 }
6743
6744 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
6745                                            uint32_t vmid,
6746                                            uint32_t gds_base, uint32_t gds_size,
6747                                            uint32_t gws_base, uint32_t gws_size,
6748                                            uint32_t oa_base, uint32_t oa_size)
6749 {
6750         struct amdgpu_device *adev = ring->adev;
6751
6752         /* GDS Base */
6753         gfx_v10_0_write_data_to_reg(ring, 0, false,
6754                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
6755                                     gds_base);
6756
6757         /* GDS Size */
6758         gfx_v10_0_write_data_to_reg(ring, 0, false,
6759                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
6760                                     gds_size);
6761
6762         /* GWS */
6763         gfx_v10_0_write_data_to_reg(ring, 0, false,
6764                                     SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
6765                                     gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
6766
6767         /* OA */
6768         gfx_v10_0_write_data_to_reg(ring, 0, false,
6769                                     SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
6770                                     (1 << (oa_size + oa_base)) - (1 << oa_base));
6771 }
6772
6773 static int gfx_v10_0_early_init(void *handle)
6774 {
6775         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6776
6777         adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
6778
6779         adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
6780
6781         gfx_v10_0_set_kiq_pm4_funcs(adev);
6782         gfx_v10_0_set_ring_funcs(adev);
6783         gfx_v10_0_set_irq_funcs(adev);
6784         gfx_v10_0_set_gds_init(adev);
6785         gfx_v10_0_set_rlc_funcs(adev);
6786
6787         return 0;
6788 }
6789
6790 static int gfx_v10_0_late_init(void *handle)
6791 {
6792         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6793         int r;
6794
6795         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
6796         if (r)
6797                 return r;
6798
6799         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
6800         if (r)
6801                 return r;
6802
6803         return 0;
6804 }
6805
6806 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
6807 {
6808         uint32_t rlc_cntl;
6809
6810         /* if RLC is not enabled, do nothing */
6811         rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
6812         return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
6813 }
6814
6815 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
6816 {
6817         uint32_t data;
6818         unsigned i;
6819
6820         data = RLC_SAFE_MODE__CMD_MASK;
6821         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
6822         WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
6823
6824         /* wait for RLC_SAFE_MODE */
6825         for (i = 0; i < adev->usec_timeout; i++) {
6826                 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
6827                         break;
6828                 udelay(1);
6829         }
6830 }
6831
6832 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
6833 {
6834         uint32_t data;
6835
6836         data = RLC_SAFE_MODE__CMD_MASK;
6837         WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
6838 }
6839
6840 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
6841                                                       bool enable)
6842 {
6843         uint32_t data, def;
6844
6845         /* It is disabled by HW by default */
6846         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
6847                 /* 0 - Disable some blocks' MGCG */
6848                 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
6849                 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
6850                 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
6851                 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
6852
6853                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
6854                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
6855                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
6856                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
6857                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
6858
6859                 /* only for Vega10 & Raven1 */
6860                 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
6861
6862                 if (def != data)
6863                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
6864
6865                 /* MGLS is a global flag to control all MGLS in GFX */
6866                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
6867                         /* 2 - RLC memory Light sleep */
6868                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
6869                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
6870                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
6871                                 if (def != data)
6872                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
6873                         }
6874                         /* 3 - CP memory Light sleep */
6875                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
6876                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
6877                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
6878                                 if (def != data)
6879                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
6880                         }
6881                 }
6882         } else {
6883                 /* 1 - MGCG_OVERRIDE */
6884                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
6885                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
6886                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
6887                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
6888                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
6889                 if (def != data)
6890                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
6891
6892                 /* 2 - disable MGLS in CP */
6893                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
6894                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
6895                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
6896                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
6897                 }
6898
6899                 /* 3 - disable MGLS in RLC */
6900                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
6901                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
6902                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
6903                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
6904                 }
6905
6906         }
6907 }
6908
6909 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
6910                                            bool enable)
6911 {
6912         uint32_t data, def;
6913
6914         /* Enable 3D CGCG/CGLS */
6915         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
6916                 /* write cmd to clear cgcg/cgls ov */
6917                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
6918                 /* unset CGCG override */
6919                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
6920                 /* update CGCG and CGLS override bits */
6921                 if (def != data)
6922                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
6923                 /* enable 3Dcgcg FSM(0x0000363f) */
6924                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
6925                 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
6926                         RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
6927                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
6928                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
6929                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
6930                 if (def != data)
6931                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
6932
6933                 /* set IDLE_POLL_COUNT(0x00900100) */
6934                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
6935                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
6936                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
6937                 if (def != data)
6938                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
6939         } else {
6940                 /* Disable CGCG/CGLS */
6941                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
6942                 /* disable cgcg, cgls should be disabled */
6943                 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
6944                           RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
6945                 /* disable cgcg and cgls in FSM */
6946                 if (def != data)
6947                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
6948         }
6949 }
6950
6951 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
6952                                                       bool enable)
6953 {
6954         uint32_t def, data;
6955
6956         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
6957                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
6958                 /* unset CGCG override */
6959                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
6960                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
6961                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
6962                 else
6963                         data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
6964                 /* update CGCG and CGLS override bits */
6965                 if (def != data)
6966                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
6967
6968                 /* enable cgcg FSM(0x0000363F) */
6969                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
6970                 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
6971                         RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
6972                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
6973                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
6974                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
6975                 if (def != data)
6976                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
6977
6978                 /* set IDLE_POLL_COUNT(0x00900100) */
6979                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
6980                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
6981                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
6982                 if (def != data)
6983                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
6984         } else {
6985                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
6986                 /* reset CGCG/CGLS bits */
6987                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
6988                 /* disable cgcg and cgls in FSM */
6989                 if (def != data)
6990                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
6991         }
6992 }
6993
6994 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
6995                                             bool enable)
6996 {
6997         amdgpu_gfx_rlc_enter_safe_mode(adev);
6998
6999         if (enable) {
7000                 /* CGCG/CGLS should be enabled after MGCG/MGLS
7001                  * ===  MGCG + MGLS ===
7002                  */
7003                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7004                 /* ===  CGCG /CGLS for GFX 3D Only === */
7005                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7006                 /* ===  CGCG + CGLS === */
7007                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7008         } else {
7009                 /* CGCG/CGLS should be disabled before MGCG/MGLS
7010                  * ===  CGCG + CGLS ===
7011                  */
7012                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7013                 /* ===  CGCG /CGLS for GFX 3D Only === */
7014                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7015                 /* ===  MGCG + MGLS === */
7016                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7017         }
7018
7019         if (adev->cg_flags &
7020             (AMD_CG_SUPPORT_GFX_MGCG |
7021              AMD_CG_SUPPORT_GFX_CGLS |
7022              AMD_CG_SUPPORT_GFX_CGCG |
7023              AMD_CG_SUPPORT_GFX_CGLS |
7024              AMD_CG_SUPPORT_GFX_3D_CGCG |
7025              AMD_CG_SUPPORT_GFX_3D_CGLS))
7026                 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
7027
7028         amdgpu_gfx_rlc_exit_safe_mode(adev);
7029
7030         return 0;
7031 }
7032
7033 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
7034 {
7035         u32 reg, data;
7036
7037         reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
7038         if (amdgpu_sriov_is_pp_one_vf(adev))
7039                 data = RREG32_NO_KIQ(reg);
7040         else
7041                 data = RREG32(reg);
7042
7043         data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
7044         data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
7045
7046         if (amdgpu_sriov_is_pp_one_vf(adev))
7047                 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
7048         else
7049                 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
7050 }
7051
7052 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
7053                                         uint32_t offset,
7054                                         struct soc15_reg_rlcg *entries, int arr_size)
7055 {
7056         int i;
7057         uint32_t reg;
7058
7059         if (!entries)
7060                 return false;
7061
7062         for (i = 0; i < arr_size; i++) {
7063                 const struct soc15_reg_rlcg *entry;
7064
7065                 entry = &entries[i];
7066                 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
7067                 if (offset == reg)
7068                         return true;
7069         }
7070
7071         return false;
7072 }
7073
7074 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
7075 {
7076         return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
7077 }
7078
7079 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
7080         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7081         .set_safe_mode = gfx_v10_0_set_safe_mode,
7082         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
7083         .init = gfx_v10_0_rlc_init,
7084         .get_csb_size = gfx_v10_0_get_csb_size,
7085         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
7086         .resume = gfx_v10_0_rlc_resume,
7087         .stop = gfx_v10_0_rlc_stop,
7088         .reset = gfx_v10_0_rlc_reset,
7089         .start = gfx_v10_0_rlc_start,
7090         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
7091 };
7092
7093 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
7094         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7095         .set_safe_mode = gfx_v10_0_set_safe_mode,
7096         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
7097         .init = gfx_v10_0_rlc_init,
7098         .get_csb_size = gfx_v10_0_get_csb_size,
7099         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
7100         .resume = gfx_v10_0_rlc_resume,
7101         .stop = gfx_v10_0_rlc_stop,
7102         .reset = gfx_v10_0_rlc_reset,
7103         .start = gfx_v10_0_rlc_start,
7104         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
7105         .rlcg_wreg = gfx_v10_rlcg_wreg,
7106         .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
7107 };
7108
7109 static int gfx_v10_0_set_powergating_state(void *handle,
7110                                           enum amd_powergating_state state)
7111 {
7112         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7113         bool enable = (state == AMD_PG_STATE_GATE);
7114
7115         if (amdgpu_sriov_vf(adev))
7116                 return 0;
7117
7118         switch (adev->asic_type) {
7119         case CHIP_NAVI10:
7120         case CHIP_NAVI14:
7121                 amdgpu_gfx_off_ctrl(adev, enable);
7122                 break;
7123         default:
7124                 break;
7125         }
7126         return 0;
7127 }
7128
7129 static int gfx_v10_0_set_clockgating_state(void *handle,
7130                                           enum amd_clockgating_state state)
7131 {
7132         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7133
7134         if (amdgpu_sriov_vf(adev))
7135                 return 0;
7136
7137         switch (adev->asic_type) {
7138         case CHIP_NAVI10:
7139         case CHIP_NAVI14:
7140         case CHIP_NAVI12:
7141                 gfx_v10_0_update_gfx_clock_gating(adev,
7142                                                  state == AMD_CG_STATE_GATE);
7143                 break;
7144         default:
7145                 break;
7146         }
7147         return 0;
7148 }
7149
7150 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags)
7151 {
7152         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7153         int data;
7154
7155         /* AMD_CG_SUPPORT_GFX_MGCG */
7156         data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7157         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
7158                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
7159
7160         /* AMD_CG_SUPPORT_GFX_CGCG */
7161         data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7162         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
7163                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
7164
7165         /* AMD_CG_SUPPORT_GFX_CGLS */
7166         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
7167                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
7168
7169         /* AMD_CG_SUPPORT_GFX_RLC_LS */
7170         data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7171         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
7172                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
7173
7174         /* AMD_CG_SUPPORT_GFX_CP_LS */
7175         data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7176         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
7177                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
7178
7179         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
7180         data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7181         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
7182                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
7183
7184         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
7185         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
7186                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
7187 }
7188
7189 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
7190 {
7191         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/
7192 }
7193
7194 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
7195 {
7196         struct amdgpu_device *adev = ring->adev;
7197         u64 wptr;
7198
7199         /* XXX check if swapping is necessary on BE */
7200         if (ring->use_doorbell) {
7201                 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
7202         } else {
7203                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
7204                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
7205         }
7206
7207         return wptr;
7208 }
7209
7210 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
7211 {
7212         struct amdgpu_device *adev = ring->adev;
7213
7214         if (ring->use_doorbell) {
7215                 /* XXX check if swapping is necessary on BE */
7216                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
7217                 WDOORBELL64(ring->doorbell_index, ring->wptr);
7218         } else {
7219                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
7220                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
7221         }
7222 }
7223
7224 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
7225 {
7226         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */
7227 }
7228
7229 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
7230 {
7231         u64 wptr;
7232
7233         /* XXX check if swapping is necessary on BE */
7234         if (ring->use_doorbell)
7235                 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
7236         else
7237                 BUG();
7238         return wptr;
7239 }
7240
7241 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
7242 {
7243         struct amdgpu_device *adev = ring->adev;
7244
7245         /* XXX check if swapping is necessary on BE */
7246         if (ring->use_doorbell) {
7247                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
7248                 WDOORBELL64(ring->doorbell_index, ring->wptr);
7249         } else {
7250                 BUG(); /* only DOORBELL method supported on gfx10 now */
7251         }
7252 }
7253
7254 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
7255 {
7256         struct amdgpu_device *adev = ring->adev;
7257         u32 ref_and_mask, reg_mem_engine;
7258         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
7259
7260         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
7261                 switch (ring->me) {
7262                 case 1:
7263                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
7264                         break;
7265                 case 2:
7266                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
7267                         break;
7268                 default:
7269                         return;
7270                 }
7271                 reg_mem_engine = 0;
7272         } else {
7273                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
7274                 reg_mem_engine = 1; /* pfp */
7275         }
7276
7277         gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
7278                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
7279                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
7280                                ref_and_mask, ref_and_mask, 0x20);
7281 }
7282
7283 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
7284                                        struct amdgpu_job *job,
7285                                        struct amdgpu_ib *ib,
7286                                        uint32_t flags)
7287 {
7288         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
7289         u32 header, control = 0;
7290
7291         if (ib->flags & AMDGPU_IB_FLAG_CE)
7292                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
7293         else
7294                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
7295
7296         control |= ib->length_dw | (vmid << 24);
7297
7298         if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
7299                 control |= INDIRECT_BUFFER_PRE_ENB(1);
7300
7301                 if (flags & AMDGPU_IB_PREEMPTED)
7302                         control |= INDIRECT_BUFFER_PRE_RESUME(1);
7303
7304                 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
7305                         gfx_v10_0_ring_emit_de_meta(ring,
7306                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
7307         }
7308
7309         amdgpu_ring_write(ring, header);
7310         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
7311         amdgpu_ring_write(ring,
7312 #ifdef __BIG_ENDIAN
7313                 (2 << 0) |
7314 #endif
7315                 lower_32_bits(ib->gpu_addr));
7316         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
7317         amdgpu_ring_write(ring, control);
7318 }
7319
7320 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
7321                                            struct amdgpu_job *job,
7322                                            struct amdgpu_ib *ib,
7323                                            uint32_t flags)
7324 {
7325         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
7326         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
7327
7328         /* Currently, there is a high possibility to get wave ID mismatch
7329          * between ME and GDS, leading to a hw deadlock, because ME generates
7330          * different wave IDs than the GDS expects. This situation happens
7331          * randomly when at least 5 compute pipes use GDS ordered append.
7332          * The wave IDs generated by ME are also wrong after suspend/resume.
7333          * Those are probably bugs somewhere else in the kernel driver.
7334          *
7335          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
7336          * GDS to 0 for this ring (me/pipe).
7337          */
7338         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
7339                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
7340                 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
7341                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
7342         }
7343
7344         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
7345         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
7346         amdgpu_ring_write(ring,
7347 #ifdef __BIG_ENDIAN
7348                                 (2 << 0) |
7349 #endif
7350                                 lower_32_bits(ib->gpu_addr));
7351         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
7352         amdgpu_ring_write(ring, control);
7353 }
7354
7355 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
7356                                      u64 seq, unsigned flags)
7357 {
7358         struct amdgpu_device *adev = ring->adev;
7359         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
7360         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
7361
7362         /* Interrupt not work fine on GFX10.1 model yet. Use fallback instead */
7363         if (adev->pdev->device == 0x50)
7364                 int_sel = false;
7365
7366         /* RELEASE_MEM - flush caches, send int */
7367         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
7368         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
7369                                  PACKET3_RELEASE_MEM_GCR_GL2_WB |
7370                                  PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
7371                                  PACKET3_RELEASE_MEM_GCR_GLM_WB |
7372                                  PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
7373                                  PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
7374                                  PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
7375         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
7376                                  PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
7377
7378         /*
7379          * the address should be Qword aligned if 64bit write, Dword
7380          * aligned if only send 32bit data low (discard data high)
7381          */
7382         if (write64bit)
7383                 BUG_ON(addr & 0x7);
7384         else
7385                 BUG_ON(addr & 0x3);
7386         amdgpu_ring_write(ring, lower_32_bits(addr));
7387         amdgpu_ring_write(ring, upper_32_bits(addr));
7388         amdgpu_ring_write(ring, lower_32_bits(seq));
7389         amdgpu_ring_write(ring, upper_32_bits(seq));
7390         amdgpu_ring_write(ring, 0);
7391 }
7392
7393 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
7394 {
7395         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
7396         uint32_t seq = ring->fence_drv.sync_seq;
7397         uint64_t addr = ring->fence_drv.gpu_addr;
7398
7399         gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
7400                                upper_32_bits(addr), seq, 0xffffffff, 4);
7401 }
7402
7403 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
7404                                          unsigned vmid, uint64_t pd_addr)
7405 {
7406         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
7407
7408         /* compute doesn't have PFP */
7409         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
7410                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
7411                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
7412                 amdgpu_ring_write(ring, 0x0);
7413         }
7414 }
7415
7416 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
7417                                           u64 seq, unsigned int flags)
7418 {
7419         struct amdgpu_device *adev = ring->adev;
7420
7421         /* we only allocate 32bit for each seq wb address */
7422         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
7423
7424         /* write fence seq to the "addr" */
7425         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
7426         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
7427                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
7428         amdgpu_ring_write(ring, lower_32_bits(addr));
7429         amdgpu_ring_write(ring, upper_32_bits(addr));
7430         amdgpu_ring_write(ring, lower_32_bits(seq));
7431
7432         if (flags & AMDGPU_FENCE_FLAG_INT) {
7433                 /* set register to trigger INT */
7434                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
7435                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
7436                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
7437                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
7438                 amdgpu_ring_write(ring, 0);
7439                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
7440         }
7441 }
7442
7443 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
7444 {
7445         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
7446         amdgpu_ring_write(ring, 0);
7447 }
7448
7449 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
7450                                          uint32_t flags)
7451 {
7452         uint32_t dw2 = 0;
7453
7454         if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
7455                 gfx_v10_0_ring_emit_ce_meta(ring,
7456                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
7457
7458         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
7459         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
7460                 /* set load_global_config & load_global_uconfig */
7461                 dw2 |= 0x8001;
7462                 /* set load_cs_sh_regs */
7463                 dw2 |= 0x01000000;
7464                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
7465                 dw2 |= 0x10002;
7466
7467                 /* set load_ce_ram if preamble presented */
7468                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
7469                         dw2 |= 0x10000000;
7470         } else {
7471                 /* still load_ce_ram if this is the first time preamble presented
7472                  * although there is no context switch happens.
7473                  */
7474                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
7475                         dw2 |= 0x10000000;
7476         }
7477
7478         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
7479         amdgpu_ring_write(ring, dw2);
7480         amdgpu_ring_write(ring, 0);
7481 }
7482
7483 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
7484 {
7485         unsigned ret;
7486
7487         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
7488         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
7489         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
7490         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
7491         ret = ring->wptr & ring->buf_mask;
7492         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
7493
7494         return ret;
7495 }
7496
7497 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
7498 {
7499         unsigned cur;
7500         BUG_ON(offset > ring->buf_mask);
7501         BUG_ON(ring->ring[offset] != 0x55aa55aa);
7502
7503         cur = (ring->wptr - 1) & ring->buf_mask;
7504         if (likely(cur > offset))
7505                 ring->ring[offset] = cur - offset;
7506         else
7507                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
7508 }
7509
7510 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
7511 {
7512         int i, r = 0;
7513         struct amdgpu_device *adev = ring->adev;
7514         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
7515         struct amdgpu_ring *kiq_ring = &kiq->ring;
7516
7517         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
7518                 return -EINVAL;
7519
7520         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size))
7521                 return -ENOMEM;
7522
7523         /* assert preemption condition */
7524         amdgpu_ring_set_preempt_cond_exec(ring, false);
7525
7526         /* assert IB preemption, emit the trailing fence */
7527         kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
7528                                    ring->trail_fence_gpu_addr,
7529                                    ++ring->trail_seq);
7530         amdgpu_ring_commit(kiq_ring);
7531
7532         /* poll the trailing fence */
7533         for (i = 0; i < adev->usec_timeout; i++) {
7534                 if (ring->trail_seq ==
7535                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
7536                         break;
7537                 udelay(1);
7538         }
7539
7540         if (i >= adev->usec_timeout) {
7541                 r = -EINVAL;
7542                 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
7543         }
7544
7545         /* deassert preemption condition */
7546         amdgpu_ring_set_preempt_cond_exec(ring, true);
7547         return r;
7548 }
7549
7550 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
7551 {
7552         struct amdgpu_device *adev = ring->adev;
7553         struct v10_ce_ib_state ce_payload = {0};
7554         uint64_t csa_addr;
7555         int cnt;
7556
7557         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
7558         csa_addr = amdgpu_csa_vaddr(ring->adev);
7559
7560         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
7561         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
7562                                  WRITE_DATA_DST_SEL(8) |
7563                                  WR_CONFIRM) |
7564                                  WRITE_DATA_CACHE_POLICY(0));
7565         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
7566                               offsetof(struct v10_gfx_meta_data, ce_payload)));
7567         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
7568                               offsetof(struct v10_gfx_meta_data, ce_payload)));
7569
7570         if (resume)
7571                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
7572                                            offsetof(struct v10_gfx_meta_data,
7573                                                     ce_payload),
7574                                            sizeof(ce_payload) >> 2);
7575         else
7576                 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
7577                                            sizeof(ce_payload) >> 2);
7578 }
7579
7580 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
7581 {
7582         struct amdgpu_device *adev = ring->adev;
7583         struct v10_de_ib_state de_payload = {0};
7584         uint64_t csa_addr, gds_addr;
7585         int cnt;
7586
7587         csa_addr = amdgpu_csa_vaddr(ring->adev);
7588         gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size,
7589                          PAGE_SIZE);
7590         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
7591         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
7592
7593         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
7594         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
7595         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
7596                                  WRITE_DATA_DST_SEL(8) |
7597                                  WR_CONFIRM) |
7598                                  WRITE_DATA_CACHE_POLICY(0));
7599         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
7600                               offsetof(struct v10_gfx_meta_data, de_payload)));
7601         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
7602                               offsetof(struct v10_gfx_meta_data, de_payload)));
7603
7604         if (resume)
7605                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
7606                                            offsetof(struct v10_gfx_meta_data,
7607                                                     de_payload),
7608                                            sizeof(de_payload) >> 2);
7609         else
7610                 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
7611                                            sizeof(de_payload) >> 2);
7612 }
7613
7614 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
7615                                     bool secure)
7616 {
7617         uint32_t v = secure ? FRAME_TMZ : 0;
7618
7619         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
7620         amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
7621 }
7622
7623 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
7624                                      uint32_t reg_val_offs)
7625 {
7626         struct amdgpu_device *adev = ring->adev;
7627
7628         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
7629         amdgpu_ring_write(ring, 0 |     /* src: register*/
7630                                 (5 << 8) |      /* dst: memory */
7631                                 (1 << 20));     /* write confirm */
7632         amdgpu_ring_write(ring, reg);
7633         amdgpu_ring_write(ring, 0);
7634         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
7635                                 reg_val_offs * 4));
7636         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
7637                                 reg_val_offs * 4));
7638 }
7639
7640 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
7641                                    uint32_t val)
7642 {
7643         uint32_t cmd = 0;
7644
7645         switch (ring->funcs->type) {
7646         case AMDGPU_RING_TYPE_GFX:
7647                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
7648                 break;
7649         case AMDGPU_RING_TYPE_KIQ:
7650                 cmd = (1 << 16); /* no inc addr */
7651                 break;
7652         default:
7653                 cmd = WR_CONFIRM;
7654                 break;
7655         }
7656         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
7657         amdgpu_ring_write(ring, cmd);
7658         amdgpu_ring_write(ring, reg);
7659         amdgpu_ring_write(ring, 0);
7660         amdgpu_ring_write(ring, val);
7661 }
7662
7663 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
7664                                         uint32_t val, uint32_t mask)
7665 {
7666         gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
7667 }
7668
7669 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
7670                                                    uint32_t reg0, uint32_t reg1,
7671                                                    uint32_t ref, uint32_t mask)
7672 {
7673         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
7674         struct amdgpu_device *adev = ring->adev;
7675         bool fw_version_ok = false;
7676
7677         fw_version_ok = adev->gfx.cp_fw_write_wait;
7678
7679         if (fw_version_ok)
7680                 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
7681                                        ref, mask, 0x20);
7682         else
7683                 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
7684                                                            ref, mask);
7685 }
7686
7687 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
7688                                          unsigned vmid)
7689 {
7690         struct amdgpu_device *adev = ring->adev;
7691         uint32_t value = 0;
7692
7693         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
7694         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
7695         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
7696         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
7697         WREG32_SOC15(GC, 0, mmSQ_CMD, value);
7698 }
7699
7700 static void
7701 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
7702                                       uint32_t me, uint32_t pipe,
7703                                       enum amdgpu_interrupt_state state)
7704 {
7705         uint32_t cp_int_cntl, cp_int_cntl_reg;
7706
7707         if (!me) {
7708                 switch (pipe) {
7709                 case 0:
7710                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
7711                         break;
7712                 case 1:
7713                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
7714                         break;
7715                 default:
7716                         DRM_DEBUG("invalid pipe %d\n", pipe);
7717                         return;
7718                 }
7719         } else {
7720                 DRM_DEBUG("invalid me %d\n", me);
7721                 return;
7722         }
7723
7724         switch (state) {
7725         case AMDGPU_IRQ_STATE_DISABLE:
7726                 cp_int_cntl = RREG32(cp_int_cntl_reg);
7727                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
7728                                             TIME_STAMP_INT_ENABLE, 0);
7729                 WREG32(cp_int_cntl_reg, cp_int_cntl);
7730                 break;
7731         case AMDGPU_IRQ_STATE_ENABLE:
7732                 cp_int_cntl = RREG32(cp_int_cntl_reg);
7733                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
7734                                             TIME_STAMP_INT_ENABLE, 1);
7735                 WREG32(cp_int_cntl_reg, cp_int_cntl);
7736                 break;
7737         default:
7738                 break;
7739         }
7740 }
7741
7742 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
7743                                                      int me, int pipe,
7744                                                      enum amdgpu_interrupt_state state)
7745 {
7746         u32 mec_int_cntl, mec_int_cntl_reg;
7747
7748         /*
7749          * amdgpu controls only the first MEC. That's why this function only
7750          * handles the setting of interrupts for this specific MEC. All other
7751          * pipes' interrupts are set by amdkfd.
7752          */
7753
7754         if (me == 1) {
7755                 switch (pipe) {
7756                 case 0:
7757                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
7758                         break;
7759                 case 1:
7760                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
7761                         break;
7762                 case 2:
7763                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
7764                         break;
7765                 case 3:
7766                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
7767                         break;
7768                 default:
7769                         DRM_DEBUG("invalid pipe %d\n", pipe);
7770                         return;
7771                 }
7772         } else {
7773                 DRM_DEBUG("invalid me %d\n", me);
7774                 return;
7775         }
7776
7777         switch (state) {
7778         case AMDGPU_IRQ_STATE_DISABLE:
7779                 mec_int_cntl = RREG32(mec_int_cntl_reg);
7780                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
7781                                              TIME_STAMP_INT_ENABLE, 0);
7782                 WREG32(mec_int_cntl_reg, mec_int_cntl);
7783                 break;
7784         case AMDGPU_IRQ_STATE_ENABLE:
7785                 mec_int_cntl = RREG32(mec_int_cntl_reg);
7786                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
7787                                              TIME_STAMP_INT_ENABLE, 1);
7788                 WREG32(mec_int_cntl_reg, mec_int_cntl);
7789                 break;
7790         default:
7791                 break;
7792         }
7793 }
7794
7795 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
7796                                             struct amdgpu_irq_src *src,
7797                                             unsigned type,
7798                                             enum amdgpu_interrupt_state state)
7799 {
7800         switch (type) {
7801         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
7802                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
7803                 break;
7804         case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
7805                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
7806                 break;
7807         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
7808                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
7809                 break;
7810         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
7811                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
7812                 break;
7813         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
7814                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
7815                 break;
7816         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
7817                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
7818                 break;
7819         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
7820                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
7821                 break;
7822         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
7823                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
7824                 break;
7825         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
7826                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
7827                 break;
7828         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
7829                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
7830                 break;
7831         default:
7832                 break;
7833         }
7834         return 0;
7835 }
7836
7837 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
7838                              struct amdgpu_irq_src *source,
7839                              struct amdgpu_iv_entry *entry)
7840 {
7841         int i;
7842         u8 me_id, pipe_id, queue_id;
7843         struct amdgpu_ring *ring;
7844
7845         DRM_DEBUG("IH: CP EOP\n");
7846         me_id = (entry->ring_id & 0x0c) >> 2;
7847         pipe_id = (entry->ring_id & 0x03) >> 0;
7848         queue_id = (entry->ring_id & 0x70) >> 4;
7849
7850         switch (me_id) {
7851         case 0:
7852                 if (pipe_id == 0)
7853                         amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
7854                 else
7855                         amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
7856                 break;
7857         case 1:
7858         case 2:
7859                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7860                         ring = &adev->gfx.compute_ring[i];
7861                         /* Per-queue interrupt is supported for MEC starting from VI.
7862                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
7863                           */
7864                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
7865                                 amdgpu_fence_process(ring);
7866                 }
7867                 break;
7868         }
7869         return 0;
7870 }
7871
7872 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
7873                                               struct amdgpu_irq_src *source,
7874                                               unsigned type,
7875                                               enum amdgpu_interrupt_state state)
7876 {
7877         switch (state) {
7878         case AMDGPU_IRQ_STATE_DISABLE:
7879         case AMDGPU_IRQ_STATE_ENABLE:
7880                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
7881                                PRIV_REG_INT_ENABLE,
7882                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
7883                 break;
7884         default:
7885                 break;
7886         }
7887
7888         return 0;
7889 }
7890
7891 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
7892                                                struct amdgpu_irq_src *source,
7893                                                unsigned type,
7894                                                enum amdgpu_interrupt_state state)
7895 {
7896         switch (state) {
7897         case AMDGPU_IRQ_STATE_DISABLE:
7898         case AMDGPU_IRQ_STATE_ENABLE:
7899                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
7900                                PRIV_INSTR_INT_ENABLE,
7901                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
7902         default:
7903                 break;
7904         }
7905
7906         return 0;
7907 }
7908
7909 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
7910                                         struct amdgpu_iv_entry *entry)
7911 {
7912         u8 me_id, pipe_id, queue_id;
7913         struct amdgpu_ring *ring;
7914         int i;
7915
7916         me_id = (entry->ring_id & 0x0c) >> 2;
7917         pipe_id = (entry->ring_id & 0x03) >> 0;
7918         queue_id = (entry->ring_id & 0x70) >> 4;
7919
7920         switch (me_id) {
7921         case 0:
7922                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
7923                         ring = &adev->gfx.gfx_ring[i];
7924                         /* we only enabled 1 gfx queue per pipe for now */
7925                         if (ring->me == me_id && ring->pipe == pipe_id)
7926                                 drm_sched_fault(&ring->sched);
7927                 }
7928                 break;
7929         case 1:
7930         case 2:
7931                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7932                         ring = &adev->gfx.compute_ring[i];
7933                         if (ring->me == me_id && ring->pipe == pipe_id &&
7934                             ring->queue == queue_id)
7935                                 drm_sched_fault(&ring->sched);
7936                 }
7937                 break;
7938         default:
7939                 BUG();
7940         }
7941 }
7942
7943 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
7944                                   struct amdgpu_irq_src *source,
7945                                   struct amdgpu_iv_entry *entry)
7946 {
7947         DRM_ERROR("Illegal register access in command stream\n");
7948         gfx_v10_0_handle_priv_fault(adev, entry);
7949         return 0;
7950 }
7951
7952 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
7953                                    struct amdgpu_irq_src *source,
7954                                    struct amdgpu_iv_entry *entry)
7955 {
7956         DRM_ERROR("Illegal instruction in command stream\n");
7957         gfx_v10_0_handle_priv_fault(adev, entry);
7958         return 0;
7959 }
7960
7961 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
7962                                              struct amdgpu_irq_src *src,
7963                                              unsigned int type,
7964                                              enum amdgpu_interrupt_state state)
7965 {
7966         uint32_t tmp, target;
7967         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
7968
7969         if (ring->me == 1)
7970                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
7971         else
7972                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
7973         target += ring->pipe;
7974
7975         switch (type) {
7976         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
7977                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
7978                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
7979                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
7980                                             GENERIC2_INT_ENABLE, 0);
7981                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
7982
7983                         tmp = RREG32(target);
7984                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
7985                                             GENERIC2_INT_ENABLE, 0);
7986                         WREG32(target, tmp);
7987                 } else {
7988                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
7989                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
7990                                             GENERIC2_INT_ENABLE, 1);
7991                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
7992
7993                         tmp = RREG32(target);
7994                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
7995                                             GENERIC2_INT_ENABLE, 1);
7996                         WREG32(target, tmp);
7997                 }
7998                 break;
7999         default:
8000                 BUG(); /* kiq only support GENERIC2_INT now */
8001                 break;
8002         }
8003         return 0;
8004 }
8005
8006 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
8007                              struct amdgpu_irq_src *source,
8008                              struct amdgpu_iv_entry *entry)
8009 {
8010         u8 me_id, pipe_id, queue_id;
8011         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8012
8013         me_id = (entry->ring_id & 0x0c) >> 2;
8014         pipe_id = (entry->ring_id & 0x03) >> 0;
8015         queue_id = (entry->ring_id & 0x70) >> 4;
8016         DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
8017                    me_id, pipe_id, queue_id);
8018
8019         amdgpu_fence_process(ring);
8020         return 0;
8021 }
8022
8023 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
8024 {
8025         const unsigned int gcr_cntl =
8026                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
8027                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
8028                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
8029                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
8030                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
8031                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
8032                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
8033                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
8034
8035         /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
8036         amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
8037         amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
8038         amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
8039         amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
8040         amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
8041         amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
8042         amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
8043         amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
8044 }
8045
8046 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
8047         .name = "gfx_v10_0",
8048         .early_init = gfx_v10_0_early_init,
8049         .late_init = gfx_v10_0_late_init,
8050         .sw_init = gfx_v10_0_sw_init,
8051         .sw_fini = gfx_v10_0_sw_fini,
8052         .hw_init = gfx_v10_0_hw_init,
8053         .hw_fini = gfx_v10_0_hw_fini,
8054         .suspend = gfx_v10_0_suspend,
8055         .resume = gfx_v10_0_resume,
8056         .is_idle = gfx_v10_0_is_idle,
8057         .wait_for_idle = gfx_v10_0_wait_for_idle,
8058         .soft_reset = gfx_v10_0_soft_reset,
8059         .set_clockgating_state = gfx_v10_0_set_clockgating_state,
8060         .set_powergating_state = gfx_v10_0_set_powergating_state,
8061         .get_clockgating_state = gfx_v10_0_get_clockgating_state,
8062 };
8063
8064 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
8065         .type = AMDGPU_RING_TYPE_GFX,
8066         .align_mask = 0xff,
8067         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8068         .support_64bit_ptrs = true,
8069         .vmhub = AMDGPU_GFXHUB_0,
8070         .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
8071         .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
8072         .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
8073         .emit_frame_size = /* totally 242 maximum if 16 IBs */
8074                 5 + /* COND_EXEC */
8075                 7 + /* PIPELINE_SYNC */
8076                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8077                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8078                 2 + /* VM_FLUSH */
8079                 8 + /* FENCE for VM_FLUSH */
8080                 20 + /* GDS switch */
8081                 4 + /* double SWITCH_BUFFER,
8082                      * the first COND_EXEC jump to the place
8083                      * just prior to this double SWITCH_BUFFER
8084                      */
8085                 5 + /* COND_EXEC */
8086                 7 + /* HDP_flush */
8087                 4 + /* VGT_flush */
8088                 14 + /* CE_META */
8089                 31 + /* DE_META */
8090                 3 + /* CNTX_CTRL */
8091                 5 + /* HDP_INVL */
8092                 8 + 8 + /* FENCE x2 */
8093                 2 + /* SWITCH_BUFFER */
8094                 8, /* gfx_v10_0_emit_mem_sync */
8095         .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
8096         .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
8097         .emit_fence = gfx_v10_0_ring_emit_fence,
8098         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
8099         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
8100         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
8101         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
8102         .test_ring = gfx_v10_0_ring_test_ring,
8103         .test_ib = gfx_v10_0_ring_test_ib,
8104         .insert_nop = amdgpu_ring_insert_nop,
8105         .pad_ib = amdgpu_ring_generic_pad_ib,
8106         .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
8107         .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
8108         .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
8109         .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
8110         .preempt_ib = gfx_v10_0_ring_preempt_ib,
8111         .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
8112         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8113         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8114         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8115         .soft_recovery = gfx_v10_0_ring_soft_recovery,
8116         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
8117 };
8118
8119 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
8120         .type = AMDGPU_RING_TYPE_COMPUTE,
8121         .align_mask = 0xff,
8122         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8123         .support_64bit_ptrs = true,
8124         .vmhub = AMDGPU_GFXHUB_0,
8125         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
8126         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
8127         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
8128         .emit_frame_size =
8129                 20 + /* gfx_v10_0_ring_emit_gds_switch */
8130                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
8131                 5 + /* hdp invalidate */
8132                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
8133                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8134                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8135                 2 + /* gfx_v10_0_ring_emit_vm_flush */
8136                 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
8137                 8, /* gfx_v10_0_emit_mem_sync */
8138         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
8139         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
8140         .emit_fence = gfx_v10_0_ring_emit_fence,
8141         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
8142         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
8143         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
8144         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
8145         .test_ring = gfx_v10_0_ring_test_ring,
8146         .test_ib = gfx_v10_0_ring_test_ib,
8147         .insert_nop = amdgpu_ring_insert_nop,
8148         .pad_ib = amdgpu_ring_generic_pad_ib,
8149         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8150         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8151         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8152         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
8153 };
8154
8155 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
8156         .type = AMDGPU_RING_TYPE_KIQ,
8157         .align_mask = 0xff,
8158         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8159         .support_64bit_ptrs = true,
8160         .vmhub = AMDGPU_GFXHUB_0,
8161         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
8162         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
8163         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
8164         .emit_frame_size =
8165                 20 + /* gfx_v10_0_ring_emit_gds_switch */
8166                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
8167                 5 + /*hdp invalidate */
8168                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
8169                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8170                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8171                 2 + /* gfx_v10_0_ring_emit_vm_flush */
8172                 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
8173         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
8174         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
8175         .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
8176         .test_ring = gfx_v10_0_ring_test_ring,
8177         .test_ib = gfx_v10_0_ring_test_ib,
8178         .insert_nop = amdgpu_ring_insert_nop,
8179         .pad_ib = amdgpu_ring_generic_pad_ib,
8180         .emit_rreg = gfx_v10_0_ring_emit_rreg,
8181         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8182         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8183         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8184 };
8185
8186 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
8187 {
8188         int i;
8189
8190         adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
8191
8192         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
8193                 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
8194
8195         for (i = 0; i < adev->gfx.num_compute_rings; i++)
8196                 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
8197 }
8198
8199 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
8200         .set = gfx_v10_0_set_eop_interrupt_state,
8201         .process = gfx_v10_0_eop_irq,
8202 };
8203
8204 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
8205         .set = gfx_v10_0_set_priv_reg_fault_state,
8206         .process = gfx_v10_0_priv_reg_irq,
8207 };
8208
8209 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
8210         .set = gfx_v10_0_set_priv_inst_fault_state,
8211         .process = gfx_v10_0_priv_inst_irq,
8212 };
8213
8214 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
8215         .set = gfx_v10_0_kiq_set_interrupt_state,
8216         .process = gfx_v10_0_kiq_irq,
8217 };
8218
8219 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
8220 {
8221         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
8222         adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
8223
8224         adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
8225         adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
8226
8227         adev->gfx.priv_reg_irq.num_types = 1;
8228         adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
8229
8230         adev->gfx.priv_inst_irq.num_types = 1;
8231         adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
8232 }
8233
8234 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
8235 {
8236         switch (adev->asic_type) {
8237         case CHIP_NAVI10:
8238         case CHIP_NAVI14:
8239                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
8240                 break;
8241         case CHIP_NAVI12:
8242                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
8243                 break;
8244         default:
8245                 break;
8246         }
8247 }
8248
8249 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
8250 {
8251         unsigned total_cu = adev->gfx.config.max_cu_per_sh *
8252                             adev->gfx.config.max_sh_per_se *
8253                             adev->gfx.config.max_shader_engines;
8254
8255         adev->gds.gds_size = 0x10000;
8256         adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
8257         adev->gds.gws_size = 64;
8258         adev->gds.oa_size = 16;
8259 }
8260
8261 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
8262                                                           u32 bitmap)
8263 {
8264         u32 data;
8265
8266         if (!bitmap)
8267                 return;
8268
8269         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
8270         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
8271
8272         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
8273 }
8274
8275 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
8276 {
8277         u32 data, wgp_bitmask;
8278         data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
8279         data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
8280
8281         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
8282         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
8283
8284         wgp_bitmask =
8285                 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
8286
8287         return (~data) & wgp_bitmask;
8288 }
8289
8290 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
8291 {
8292         u32 wgp_idx, wgp_active_bitmap;
8293         u32 cu_bitmap_per_wgp, cu_active_bitmap;
8294
8295         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
8296         cu_active_bitmap = 0;
8297
8298         for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
8299                 /* if there is one WGP enabled, it means 2 CUs will be enabled */
8300                 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
8301                 if (wgp_active_bitmap & (1 << wgp_idx))
8302                         cu_active_bitmap |= cu_bitmap_per_wgp;
8303         }
8304
8305         return cu_active_bitmap;
8306 }
8307
8308 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
8309                                  struct amdgpu_cu_info *cu_info)
8310 {
8311         int i, j, k, counter, active_cu_number = 0;
8312         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
8313         unsigned disable_masks[4 * 2];
8314
8315         if (!adev || !cu_info)
8316                 return -EINVAL;
8317
8318         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
8319
8320         mutex_lock(&adev->grbm_idx_mutex);
8321         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
8322                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
8323                         mask = 1;
8324                         ao_bitmap = 0;
8325                         counter = 0;
8326                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
8327                         if (i < 4 && j < 2)
8328                                 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
8329                                         adev, disable_masks[i * 2 + j]);
8330                         bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
8331                         cu_info->bitmap[i][j] = bitmap;
8332
8333                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
8334                                 if (bitmap & mask) {
8335                                         if (counter < adev->gfx.config.max_cu_per_sh)
8336                                                 ao_bitmap |= mask;
8337                                         counter++;
8338                                 }
8339                                 mask <<= 1;
8340                         }
8341                         active_cu_number += counter;
8342                         if (i < 2 && j < 2)
8343                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
8344                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
8345                 }
8346         }
8347         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
8348         mutex_unlock(&adev->grbm_idx_mutex);
8349
8350         cu_info->number = active_cu_number;
8351         cu_info->ao_cu_mask = ao_cu_mask;
8352         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
8353
8354         return 0;
8355 }
8356
8357 const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
8358 {
8359         .type = AMD_IP_BLOCK_TYPE_GFX,
8360         .major = 10,
8361         .minor = 0,
8362         .rev = 0,
8363         .funcs = &gfx_v10_0_ip_funcs,
8364 };